1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Samsung S5H1411 VSB/QAM demodulator driver
5 Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/string.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <media/dvb_frontend.h>
19 struct s5h1411_state {
21 struct i2c_adapter *i2c;
23 /* configuration settings */
24 const struct s5h1411_config *config;
26 struct dvb_frontend frontend;
28 enum fe_modulation current_modulation;
29 unsigned int first_tune:1;
31 u32 current_frequency;
39 #define dprintk(arg...) do { \
44 /* Register values to initialise the demod, defaults to VSB */
45 static struct init_tab {
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
59 { S5H1411_I2C_TOP_ADDR, 0x28, 0x070f, },
60 { S5H1411_I2C_TOP_ADDR, 0x29, 0x2820, },
61 { S5H1411_I2C_TOP_ADDR, 0x2a, 0x102e, },
62 { S5H1411_I2C_TOP_ADDR, 0x2b, 0x0220, },
63 { S5H1411_I2C_TOP_ADDR, 0x2e, 0x0d0e, },
64 { S5H1411_I2C_TOP_ADDR, 0x2f, 0x1013, },
65 { S5H1411_I2C_TOP_ADDR, 0x31, 0x171b, },
66 { S5H1411_I2C_TOP_ADDR, 0x32, 0x0e0f, },
67 { S5H1411_I2C_TOP_ADDR, 0x33, 0x0f10, },
68 { S5H1411_I2C_TOP_ADDR, 0x34, 0x170e, },
69 { S5H1411_I2C_TOP_ADDR, 0x35, 0x4b10, },
70 { S5H1411_I2C_TOP_ADDR, 0x36, 0x0f17, },
71 { S5H1411_I2C_TOP_ADDR, 0x3c, 0x1577, },
72 { S5H1411_I2C_TOP_ADDR, 0x3d, 0x081a, },
73 { S5H1411_I2C_TOP_ADDR, 0x3e, 0x77ee, },
74 { S5H1411_I2C_TOP_ADDR, 0x40, 0x1e09, },
75 { S5H1411_I2C_TOP_ADDR, 0x41, 0x0f0c, },
76 { S5H1411_I2C_TOP_ADDR, 0x42, 0x1f10, },
77 { S5H1411_I2C_TOP_ADDR, 0x4d, 0x0509, },
78 { S5H1411_I2C_TOP_ADDR, 0x4e, 0x0a00, },
79 { S5H1411_I2C_TOP_ADDR, 0x50, 0x0000, },
80 { S5H1411_I2C_TOP_ADDR, 0x5b, 0x0000, },
81 { S5H1411_I2C_TOP_ADDR, 0x5c, 0x0008, },
82 { S5H1411_I2C_TOP_ADDR, 0x57, 0x1101, },
83 { S5H1411_I2C_TOP_ADDR, 0x65, 0x007c, },
84 { S5H1411_I2C_TOP_ADDR, 0x68, 0x0512, },
85 { S5H1411_I2C_TOP_ADDR, 0x69, 0x0258, },
86 { S5H1411_I2C_TOP_ADDR, 0x70, 0x0004, },
87 { S5H1411_I2C_TOP_ADDR, 0x71, 0x0007, },
88 { S5H1411_I2C_TOP_ADDR, 0x76, 0x00a9, },
89 { S5H1411_I2C_TOP_ADDR, 0x78, 0x3141, },
90 { S5H1411_I2C_TOP_ADDR, 0x7a, 0x3141, },
91 { S5H1411_I2C_TOP_ADDR, 0xb3, 0x8003, },
92 { S5H1411_I2C_TOP_ADDR, 0xb5, 0xa6bb, },
93 { S5H1411_I2C_TOP_ADDR, 0xb6, 0x0609, },
94 { S5H1411_I2C_TOP_ADDR, 0xb7, 0x2f06, },
95 { S5H1411_I2C_TOP_ADDR, 0xb8, 0x003f, },
96 { S5H1411_I2C_TOP_ADDR, 0xb9, 0x2700, },
97 { S5H1411_I2C_TOP_ADDR, 0xba, 0xfac8, },
98 { S5H1411_I2C_TOP_ADDR, 0xbe, 0x1003, },
99 { S5H1411_I2C_TOP_ADDR, 0xbf, 0x103f, },
100 { S5H1411_I2C_TOP_ADDR, 0xce, 0x2000, },
101 { S5H1411_I2C_TOP_ADDR, 0xcf, 0x0800, },
102 { S5H1411_I2C_TOP_ADDR, 0xd0, 0x0800, },
103 { S5H1411_I2C_TOP_ADDR, 0xd1, 0x0400, },
104 { S5H1411_I2C_TOP_ADDR, 0xd2, 0x0800, },
105 { S5H1411_I2C_TOP_ADDR, 0xd3, 0x2000, },
106 { S5H1411_I2C_TOP_ADDR, 0xd4, 0x3000, },
107 { S5H1411_I2C_TOP_ADDR, 0xdb, 0x4a9b, },
108 { S5H1411_I2C_TOP_ADDR, 0xdc, 0x1000, },
109 { S5H1411_I2C_TOP_ADDR, 0xde, 0x0001, },
110 { S5H1411_I2C_TOP_ADDR, 0xdf, 0x0000, },
111 { S5H1411_I2C_TOP_ADDR, 0xe3, 0x0301, },
112 { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0000, },
113 { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0001, },
114 { S5H1411_I2C_QAM_ADDR, 0x08, 0x0600, },
115 { S5H1411_I2C_QAM_ADDR, 0x18, 0x4201, },
116 { S5H1411_I2C_QAM_ADDR, 0x1e, 0x6476, },
117 { S5H1411_I2C_QAM_ADDR, 0x21, 0x0830, },
118 { S5H1411_I2C_QAM_ADDR, 0x0c, 0x5679, },
119 { S5H1411_I2C_QAM_ADDR, 0x0d, 0x579b, },
120 { S5H1411_I2C_QAM_ADDR, 0x24, 0x0102, },
121 { S5H1411_I2C_QAM_ADDR, 0x31, 0x7488, },
122 { S5H1411_I2C_QAM_ADDR, 0x32, 0x0a08, },
123 { S5H1411_I2C_QAM_ADDR, 0x3d, 0x8689, },
124 { S5H1411_I2C_QAM_ADDR, 0x49, 0x0048, },
125 { S5H1411_I2C_QAM_ADDR, 0x57, 0x2012, },
126 { S5H1411_I2C_QAM_ADDR, 0x5d, 0x7676, },
127 { S5H1411_I2C_QAM_ADDR, 0x04, 0x0400, },
128 { S5H1411_I2C_QAM_ADDR, 0x58, 0x00c0, },
129 { S5H1411_I2C_QAM_ADDR, 0x5b, 0x0100, },
132 /* VSB SNR lookup table */
133 static struct vsb_snr_tab {
177 /* QAM64 SNR lookup table */
178 static struct qam64_snr_tab {
181 } qam64_snr_tab[] = {
250 /* QAM256 SNR lookup table */
251 static struct qam256_snr_tab {
254 } qam256_snr_tab[] = {
329 /* 8 bit registers, 16 bit values */
330 static int s5h1411_writereg(struct s5h1411_state *state,
331 u8 addr, u8 reg, u16 data)
334 u8 buf[] = { reg, data >> 8, data & 0xff };
336 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 3 };
338 ret = i2c_transfer(state->i2c, &msg, 1);
341 printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, ret == %i)\n",
342 __func__, addr, reg, data, ret);
344 return (ret != 1) ? -1 : 0;
347 static u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg)
353 struct i2c_msg msg[] = {
354 { .addr = addr, .flags = 0, .buf = b0, .len = 1 },
355 { .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 2 } };
357 ret = i2c_transfer(state->i2c, msg, 2);
360 printk(KERN_ERR "%s: readreg error (ret == %i)\n",
362 return (b1[0] << 8) | b1[1];
365 static int s5h1411_softreset(struct dvb_frontend *fe)
367 struct s5h1411_state *state = fe->demodulator_priv;
369 dprintk("%s()\n", __func__);
371 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0);
372 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1);
376 static int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz)
378 struct s5h1411_state *state = fe->demodulator_priv;
380 dprintk("%s(%d KHz)\n", __func__, KHz);
384 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d5);
385 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342);
386 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9);
389 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225);
390 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96);
391 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225);
394 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc);
395 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e);
396 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd);
399 dprintk("%s(%d KHz) Invalid, defaulting to 5380\n",
404 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4);
405 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655);
406 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4);
410 state->if_freq = KHz;
415 static int s5h1411_set_mpeg_timing(struct dvb_frontend *fe, int mode)
417 struct s5h1411_state *state = fe->demodulator_priv;
420 dprintk("%s(%d)\n", __func__, mode);
422 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff;
424 case S5H1411_MPEGTIMING_CONTINUOUS_INVERTING_CLOCK:
427 case S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK:
428 dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode);
431 case S5H1411_MPEGTIMING_NONCONTINUOUS_INVERTING_CLOCK:
434 case S5H1411_MPEGTIMING_NONCONTINUOUS_NONINVERTING_CLOCK:
441 /* Configure MPEG Signal Timing charactistics */
442 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val);
445 static int s5h1411_set_spectralinversion(struct dvb_frontend *fe, int inversion)
447 struct s5h1411_state *state = fe->demodulator_priv;
450 dprintk("%s(%d)\n", __func__, inversion);
451 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000;
454 val |= 0x1000; /* Inverted */
456 state->inversion = inversion;
457 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val);
460 static int s5h1411_set_serialmode(struct dvb_frontend *fe, int serial)
462 struct s5h1411_state *state = fe->demodulator_priv;
465 dprintk("%s(%d)\n", __func__, serial);
466 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbd) & ~0x100;
471 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, val);
474 static int s5h1411_enable_modulation(struct dvb_frontend *fe,
475 enum fe_modulation m)
477 struct s5h1411_state *state = fe->demodulator_priv;
479 dprintk("%s(0x%08x)\n", __func__, m);
481 if ((state->first_tune == 0) && (m == state->current_modulation)) {
482 dprintk("%s() Already at desired modulation. Skipping...\n",
489 dprintk("%s() VSB_8\n", __func__);
490 s5h1411_set_if_freq(fe, state->config->vsb_if);
491 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71);
492 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00);
493 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1);
498 dprintk("%s() QAM_AUTO (64/256)\n", __func__);
499 s5h1411_set_if_freq(fe, state->config->qam_if);
500 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171);
501 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001);
502 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101);
503 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0);
506 dprintk("%s() Invalid modulation\n", __func__);
510 state->current_modulation = m;
511 state->first_tune = 0;
512 s5h1411_softreset(fe);
517 static int s5h1411_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
519 struct s5h1411_state *state = fe->demodulator_priv;
521 dprintk("%s(%d)\n", __func__, enable);
524 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
526 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0);
529 static int s5h1411_set_gpio(struct dvb_frontend *fe, int enable)
531 struct s5h1411_state *state = fe->demodulator_priv;
534 dprintk("%s(%d)\n", __func__, enable);
536 val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02;
539 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0,
542 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val);
545 static int s5h1411_set_powerstate(struct dvb_frontend *fe, int enable)
547 struct s5h1411_state *state = fe->demodulator_priv;
549 dprintk("%s(%d)\n", __func__, enable);
552 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1);
554 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0);
555 s5h1411_softreset(fe);
561 static int s5h1411_sleep(struct dvb_frontend *fe)
563 return s5h1411_set_powerstate(fe, 1);
566 static int s5h1411_register_reset(struct dvb_frontend *fe)
568 struct s5h1411_state *state = fe->demodulator_priv;
570 dprintk("%s()\n", __func__);
572 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0);
575 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
576 static int s5h1411_set_frontend(struct dvb_frontend *fe)
578 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
579 struct s5h1411_state *state = fe->demodulator_priv;
581 dprintk("%s(frequency=%d)\n", __func__, p->frequency);
583 s5h1411_softreset(fe);
585 state->current_frequency = p->frequency;
587 s5h1411_enable_modulation(fe, p->modulation);
589 if (fe->ops.tuner_ops.set_params) {
590 if (fe->ops.i2c_gate_ctrl)
591 fe->ops.i2c_gate_ctrl(fe, 1);
593 fe->ops.tuner_ops.set_params(fe);
595 if (fe->ops.i2c_gate_ctrl)
596 fe->ops.i2c_gate_ctrl(fe, 0);
599 /* Issue a reset to the demod so it knows to resync against the
600 newly tuned frequency */
601 s5h1411_softreset(fe);
606 /* Reset the demod hardware and reset all of the configuration registers
607 to a default state. */
608 static int s5h1411_init(struct dvb_frontend *fe)
610 struct s5h1411_state *state = fe->demodulator_priv;
613 dprintk("%s()\n", __func__);
615 s5h1411_set_powerstate(fe, 0);
616 s5h1411_register_reset(fe);
618 for (i = 0; i < ARRAY_SIZE(init_tab); i++)
619 s5h1411_writereg(state, init_tab[i].addr,
623 /* The datasheet says that after initialisation, VSB is default */
624 state->current_modulation = VSB_8;
626 /* Although the datasheet says it's in VSB, empirical evidence
627 shows problems getting lock on the first tuning request. Make
628 sure we call enable_modulation the first time around */
629 state->first_tune = 1;
631 if (state->config->output_mode == S5H1411_SERIAL_OUTPUT)
633 s5h1411_set_serialmode(fe, 1);
636 s5h1411_set_serialmode(fe, 0);
638 s5h1411_set_spectralinversion(fe, state->config->inversion);
639 s5h1411_set_if_freq(fe, state->config->vsb_if);
640 s5h1411_set_gpio(fe, state->config->gpio);
641 s5h1411_set_mpeg_timing(fe, state->config->mpeg_timing);
642 s5h1411_softreset(fe);
644 /* Note: Leaving the I2C gate closed. */
645 s5h1411_i2c_gate_ctrl(fe, 0);
650 static int s5h1411_read_status(struct dvb_frontend *fe, enum fe_status *status)
652 struct s5h1411_state *state = fe->demodulator_priv;
654 u32 tuner_status = 0;
658 /* Register F2 bit 15 = Master Lock, removed */
660 switch (state->current_modulation) {
663 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0);
664 if (reg & 0x10) /* QAM FEC Lock */
665 *status |= FE_HAS_SYNC | FE_HAS_LOCK;
666 if (reg & 0x100) /* QAM EQ Lock */
667 *status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL;
671 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2);
672 if (reg & 0x1000) /* FEC Lock */
673 *status |= FE_HAS_SYNC | FE_HAS_LOCK;
674 if (reg & 0x2000) /* EQ Lock */
675 *status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL;
677 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x53);
678 if (reg & 0x1) /* AFC Lock */
679 *status |= FE_HAS_SIGNAL;
686 switch (state->config->status_mode) {
687 case S5H1411_DEMODLOCKING:
688 if (*status & FE_HAS_VITERBI)
689 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
691 case S5H1411_TUNERLOCKING:
692 /* Get the tuner status */
693 if (fe->ops.tuner_ops.get_status) {
694 if (fe->ops.i2c_gate_ctrl)
695 fe->ops.i2c_gate_ctrl(fe, 1);
697 fe->ops.tuner_ops.get_status(fe, &tuner_status);
699 if (fe->ops.i2c_gate_ctrl)
700 fe->ops.i2c_gate_ctrl(fe, 0);
703 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
707 dprintk("%s() status 0x%08x\n", __func__, *status);
712 static int s5h1411_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
714 int i, ret = -EINVAL;
715 dprintk("%s()\n", __func__);
717 for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) {
718 if (v < qam256_snr_tab[i].val) {
719 *snr = qam256_snr_tab[i].data;
727 static int s5h1411_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
729 int i, ret = -EINVAL;
730 dprintk("%s()\n", __func__);
732 for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) {
733 if (v < qam64_snr_tab[i].val) {
734 *snr = qam64_snr_tab[i].data;
742 static int s5h1411_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
744 int i, ret = -EINVAL;
745 dprintk("%s()\n", __func__);
747 for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) {
748 if (v > vsb_snr_tab[i].val) {
749 *snr = vsb_snr_tab[i].data;
754 dprintk("%s() snr=%d\n", __func__, *snr);
758 static int s5h1411_read_snr(struct dvb_frontend *fe, u16 *snr)
760 struct s5h1411_state *state = fe->demodulator_priv;
762 dprintk("%s()\n", __func__);
764 switch (state->current_modulation) {
766 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
767 return s5h1411_qam64_lookup_snr(fe, snr, reg);
769 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
770 return s5h1411_qam256_lookup_snr(fe, snr, reg);
772 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR,
774 return s5h1411_vsb_lookup_snr(fe, snr, reg);
782 static int s5h1411_read_signal_strength(struct dvb_frontend *fe,
783 u16 *signal_strength)
785 /* borrowed from lgdt330x.c
787 * Calculate strength from SNR up to 35dB
788 * Even though the SNR can go higher than 35dB,
789 * there is some comfort factor in having a range of
790 * strong signals that can show at 100%
794 int ret = s5h1411_read_snr(fe, &snr);
796 *signal_strength = 0;
799 /* The following calculation method was chosen
800 * purely for the sake of code re-use from the
801 * other demod drivers that use this method */
803 /* Convert from SNR in dB * 10 to 8.24 fixed-point */
804 tmp = (snr * ((1 << 24) / 10));
806 /* Convert from 8.24 fixed-point to
807 * scale the range 0 - 35*2^24 into 0 - 65535*/
808 if (tmp >= 8960 * 0x10000)
809 *signal_strength = 0xffff;
811 *signal_strength = tmp / 8960;
817 static int s5h1411_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
819 struct s5h1411_state *state = fe->demodulator_priv;
821 *ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9);
826 static int s5h1411_read_ber(struct dvb_frontend *fe, u32 *ber)
828 return s5h1411_read_ucblocks(fe, ber);
831 static int s5h1411_get_frontend(struct dvb_frontend *fe,
832 struct dtv_frontend_properties *p)
834 struct s5h1411_state *state = fe->demodulator_priv;
836 p->frequency = state->current_frequency;
837 p->modulation = state->current_modulation;
842 static int s5h1411_get_tune_settings(struct dvb_frontend *fe,
843 struct dvb_frontend_tune_settings *tune)
845 tune->min_delay_ms = 1000;
849 static void s5h1411_release(struct dvb_frontend *fe)
851 struct s5h1411_state *state = fe->demodulator_priv;
855 static const struct dvb_frontend_ops s5h1411_ops;
857 struct dvb_frontend *s5h1411_attach(const struct s5h1411_config *config,
858 struct i2c_adapter *i2c)
860 struct s5h1411_state *state = NULL;
863 /* allocate memory for the internal state */
864 state = kzalloc(sizeof(struct s5h1411_state), GFP_KERNEL);
868 /* setup the state */
869 state->config = config;
871 state->current_modulation = VSB_8;
872 state->inversion = state->config->inversion;
874 /* check if the demod exists */
875 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05);
879 /* create dvb_frontend */
880 memcpy(&state->frontend.ops, &s5h1411_ops,
881 sizeof(struct dvb_frontend_ops));
883 state->frontend.demodulator_priv = state;
885 if (s5h1411_init(&state->frontend) != 0) {
886 printk(KERN_ERR "%s: Failed to initialize correctly\n",
891 /* Note: Leaving the I2C gate open here. */
892 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
894 /* Put the device into low-power mode until first use */
895 s5h1411_set_powerstate(&state->frontend, 1);
897 return &state->frontend;
903 EXPORT_SYMBOL(s5h1411_attach);
905 static const struct dvb_frontend_ops s5h1411_ops = {
906 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
908 .name = "Samsung S5H1411 QAM/8VSB Frontend",
909 .frequency_min_hz = 54 * MHz,
910 .frequency_max_hz = 858 * MHz,
911 .frequency_stepsize_hz = 62500,
912 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
915 .init = s5h1411_init,
916 .sleep = s5h1411_sleep,
917 .i2c_gate_ctrl = s5h1411_i2c_gate_ctrl,
918 .set_frontend = s5h1411_set_frontend,
919 .get_frontend = s5h1411_get_frontend,
920 .get_tune_settings = s5h1411_get_tune_settings,
921 .read_status = s5h1411_read_status,
922 .read_ber = s5h1411_read_ber,
923 .read_signal_strength = s5h1411_read_signal_strength,
924 .read_snr = s5h1411_read_snr,
925 .read_ucblocks = s5h1411_read_ucblocks,
926 .release = s5h1411_release,
929 module_param(debug, int, 0644);
930 MODULE_PARM_DESC(debug, "Enable verbose debug messages");
932 MODULE_DESCRIPTION("Samsung S5H1411 QAM-B/ATSC Demodulator driver");
933 MODULE_AUTHOR("Steven Toth");
934 MODULE_LICENSE("GPL");