2 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
4 * Copyright (C) 2010-2013 Mauro Carvalho Chehab <mchehab@redhat.com>
5 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
17 #include <linux/kernel.h>
18 #include <asm/div64.h>
20 #include "dvb_frontend.h"
26 module_param(debug, int, 0644);
27 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
29 enum mb86a20s_bandwidth {
31 MB86A20S_13SEG_PARTIAL = 1,
36 u8 mb86a20s_subchannel[] = {
37 0xb0, 0xc0, 0xd0, 0xe0,
38 0xf0, 0x00, 0x10, 0x20,
41 struct mb86a20s_state {
42 struct i2c_adapter *i2c;
43 const struct mb86a20s_config *config;
46 struct dvb_frontend frontend;
49 enum mb86a20s_bandwidth bw;
53 u32 estimated_rate[NUM_LAYERS];
54 unsigned long get_strength_time;
64 #define BER_SAMPLING_RATE 1 /* Seconds */
67 * Initialization sequence: Use whatevere default values that PV SBTVD
68 * does on its initialisation, obtained via USB snoop
70 static struct regdata mb86a20s_init1[] = {
74 { 0x50, 0xd1 }, { 0x51, 0x20 },
77 static struct regdata mb86a20s_init2[] = {
78 { 0x28, 0x22 }, { 0x29, 0x00 }, { 0x2a, 0x1f }, { 0x2b, 0xf0 },
82 { 0x04, 0x08 }, { 0x05, 0x03 },
83 { 0x04, 0x0e }, { 0x05, 0x00 },
84 { 0x04, 0x0f }, { 0x05, 0x37 },
85 { 0x04, 0x0b }, { 0x05, 0x78 },
86 { 0x04, 0x00 }, { 0x05, 0x00 },
87 { 0x04, 0x01 }, { 0x05, 0x1e },
88 { 0x04, 0x02 }, { 0x05, 0x07 },
89 { 0x04, 0x03 }, { 0x05, 0xd0 },
90 { 0x04, 0x09 }, { 0x05, 0x00 },
91 { 0x04, 0x0a }, { 0x05, 0xff },
92 { 0x04, 0x27 }, { 0x05, 0x00 },
93 { 0x04, 0x28 }, { 0x05, 0x00 },
94 { 0x04, 0x1e }, { 0x05, 0x00 },
95 { 0x04, 0x29 }, { 0x05, 0x64 },
96 { 0x04, 0x32 }, { 0x05, 0x02 },
97 { 0x04, 0x14 }, { 0x05, 0x02 },
98 { 0x04, 0x04 }, { 0x05, 0x00 },
99 { 0x04, 0x05 }, { 0x05, 0x22 },
100 { 0x04, 0x06 }, { 0x05, 0x0e },
101 { 0x04, 0x07 }, { 0x05, 0xd8 },
102 { 0x04, 0x12 }, { 0x05, 0x00 },
103 { 0x04, 0x13 }, { 0x05, 0xff },
104 { 0x04, 0x15 }, { 0x05, 0x4e },
105 { 0x04, 0x16 }, { 0x05, 0x20 },
108 * On this demod, when the bit count reaches the count below,
109 * it collects the bit error count. The bit counters are initialized
110 * to 65535 here. This warrants that all of them will be quickly
111 * calculated when device gets locked. As TMCC is parsed, the values
112 * will be adjusted later in the driver's code.
114 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
115 { 0x50, 0xa7 }, { 0x51, 0x00 },
116 { 0x50, 0xa8 }, { 0x51, 0xff },
117 { 0x50, 0xa9 }, { 0x51, 0xff },
118 { 0x50, 0xaa }, { 0x51, 0x00 },
119 { 0x50, 0xab }, { 0x51, 0xff },
120 { 0x50, 0xac }, { 0x51, 0xff },
121 { 0x50, 0xad }, { 0x51, 0x00 },
122 { 0x50, 0xae }, { 0x51, 0xff },
123 { 0x50, 0xaf }, { 0x51, 0xff },
126 * On this demod, post BER counts blocks. When the count reaches the
127 * value below, it collects the block error count. The block counters
128 * are initialized to 127 here. This warrants that all of them will be
129 * quickly calculated when device gets locked. As TMCC is parsed, the
130 * values will be adjusted later in the driver's code.
132 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
133 { 0x50, 0xdc }, { 0x51, 0x00 },
134 { 0x50, 0xdd }, { 0x51, 0x7f },
135 { 0x50, 0xde }, { 0x51, 0x00 },
136 { 0x50, 0xdf }, { 0x51, 0x7f },
137 { 0x50, 0xe0 }, { 0x51, 0x00 },
138 { 0x50, 0xe1 }, { 0x51, 0x7f },
141 * On this demod, when the block count reaches the count below,
142 * it collects the block error count. The block counters are initialized
143 * to 127 here. This warrants that all of them will be quickly
144 * calculated when device gets locked. As TMCC is parsed, the values
145 * will be adjusted later in the driver's code.
147 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
148 { 0x50, 0xb2 }, { 0x51, 0x00 },
149 { 0x50, 0xb3 }, { 0x51, 0x7f },
150 { 0x50, 0xb4 }, { 0x51, 0x00 },
151 { 0x50, 0xb5 }, { 0x51, 0x7f },
152 { 0x50, 0xb6 }, { 0x51, 0x00 },
153 { 0x50, 0xb7 }, { 0x51, 0x7f },
155 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
156 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
157 { 0x45, 0x04 }, /* CN symbol 4 */
158 { 0x48, 0x04 }, /* CN manual mode */
160 { 0x50, 0xd6 }, { 0x51, 0x1f },
161 { 0x50, 0xd2 }, { 0x51, 0x03 },
162 { 0x50, 0xd7 }, { 0x51, 0xbf },
163 { 0x28, 0x74 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xff },
164 { 0x28, 0x46 }, { 0x29, 0x00 }, { 0x2a, 0x1a }, { 0x2b, 0x0c },
166 { 0x04, 0x40 }, { 0x05, 0x00 },
167 { 0x28, 0x00 }, { 0x2b, 0x08 },
168 { 0x28, 0x05 }, { 0x2b, 0x00 },
170 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x1f },
171 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x18 },
172 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x12 },
173 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x30 },
174 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x37 },
175 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
176 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x09 },
177 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x06 },
178 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7b },
179 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x76 },
180 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x7d },
181 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x08 },
182 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0b },
183 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
184 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf2 },
185 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xf3 },
186 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x05 },
187 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
188 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
189 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xef },
190 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xd8 },
191 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xf1 },
192 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x3d },
193 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x94 },
194 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0xba },
195 { 0x50, 0x1e }, { 0x51, 0x5d },
196 { 0x50, 0x22 }, { 0x51, 0x00 },
197 { 0x50, 0x23 }, { 0x51, 0xc8 },
198 { 0x50, 0x24 }, { 0x51, 0x00 },
199 { 0x50, 0x25 }, { 0x51, 0xf0 },
200 { 0x50, 0x26 }, { 0x51, 0x00 },
201 { 0x50, 0x27 }, { 0x51, 0xc3 },
202 { 0x50, 0x39 }, { 0x51, 0x02 },
205 { 0x28, 0x6a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x00 },
209 static struct regdata mb86a20s_reset_reception[] = {
216 static struct regdata mb86a20s_per_ber_reset[] = {
217 { 0x53, 0x00 }, /* pre BER Counter reset */
220 { 0x5f, 0x00 }, /* post BER Counter reset */
223 { 0x50, 0xb1 }, /* PER Counter reset */
229 * I2C read/write functions and macros
232 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
233 u8 i2c_addr, u8 reg, u8 data)
235 u8 buf[] = { reg, data };
236 struct i2c_msg msg = {
237 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
241 rc = i2c_transfer(state->i2c, &msg, 1);
243 dev_err(&state->i2c->dev,
244 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
245 __func__, rc, reg, data);
252 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
253 u8 i2c_addr, struct regdata *rd, int size)
257 for (i = 0; i < size; i++) {
258 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
266 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
271 struct i2c_msg msg[] = {
272 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
273 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
276 rc = i2c_transfer(state->i2c, msg, 2);
279 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
281 return (rc < 0) ? rc : -EIO;
287 #define mb86a20s_readreg(state, reg) \
288 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
289 #define mb86a20s_writereg(state, reg, val) \
290 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
291 #define mb86a20s_writeregdata(state, regdata) \
292 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
293 regdata, ARRAY_SIZE(regdata))
296 * Ancillary internal routines (likely compiled inlined)
298 * The functions below assume that gateway lock has already obtained
301 static int mb86a20s_read_status(struct dvb_frontend *fe, fe_status_t *status)
303 struct mb86a20s_state *state = fe->demodulator_priv;
308 val = mb86a20s_readreg(state, 0x0a) & 0xf;
313 *status |= FE_HAS_SIGNAL;
316 *status |= FE_HAS_CARRIER;
319 *status |= FE_HAS_VITERBI;
322 *status |= FE_HAS_SYNC;
324 if (val >= 8) /* Maybe 9? */
325 *status |= FE_HAS_LOCK;
327 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
328 __func__, *status, val);
333 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
335 struct mb86a20s_state *state = fe->demodulator_priv;
336 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
338 unsigned rf_max, rf_min, rf;
340 if (state->get_strength_time &&
341 (!time_after(jiffies, state->get_strength_time)))
342 return c->strength.stat[0].uvalue;
344 /* Reset its value if an error happen */
345 c->strength.stat[0].uvalue = 0;
347 /* Does a binary search to get RF strength */
351 rf = (rf_max + rf_min) / 2;
352 rc = mb86a20s_writereg(state, 0x04, 0x1f);
355 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
358 rc = mb86a20s_writereg(state, 0x04, 0x20);
361 rc = mb86a20s_writereg(state, 0x05, rf);
365 rc = mb86a20s_readreg(state, 0x02);
369 rf_min = (rf_max + rf_min) / 2;
371 rf_max = (rf_max + rf_min) / 2;
372 if (rf_max - rf_min < 4) {
373 rf = (rf_max + rf_min) / 2;
375 /* Rescale it from 2^12 (4096) to 2^16 */
376 rf = rf << (16 - 12);
380 dev_dbg(&state->i2c->dev,
381 "%s: signal strength = %d (%d < RF=%d < %d)\n",
382 __func__, rf, rf_min, rf >> 4, rf_max);
383 c->strength.stat[0].uvalue = rf;
384 state->get_strength_time = jiffies +
385 msecs_to_jiffies(1000);
391 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
395 static unsigned char reg[] = {
396 [0] = 0x86, /* Layer A */
397 [1] = 0x8a, /* Layer B */
398 [2] = 0x8e, /* Layer C */
401 if (layer >= ARRAY_SIZE(reg))
403 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
406 rc = mb86a20s_readreg(state, 0x6e);
409 switch ((rc >> 4) & 0x07) {
423 static int mb86a20s_get_fec(struct mb86a20s_state *state,
428 static unsigned char reg[] = {
429 [0] = 0x87, /* Layer A */
430 [1] = 0x8b, /* Layer B */
431 [2] = 0x8f, /* Layer C */
434 if (layer >= ARRAY_SIZE(reg))
436 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
439 rc = mb86a20s_readreg(state, 0x6e);
442 switch ((rc >> 4) & 0x07) {
458 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
463 static unsigned char reg[] = {
464 [0] = 0x88, /* Layer A */
465 [1] = 0x8c, /* Layer B */
466 [2] = 0x90, /* Layer C */
469 if (layer >= ARRAY_SIZE(reg))
471 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
474 rc = mb86a20s_readreg(state, 0x6e);
478 switch ((rc >> 4) & 0x07) {
480 return GUARD_INTERVAL_1_4;
482 return GUARD_INTERVAL_1_8;
484 return GUARD_INTERVAL_1_16;
486 return GUARD_INTERVAL_1_32;
490 return GUARD_INTERVAL_AUTO;
494 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
498 static unsigned char reg[] = {
499 [0] = 0x89, /* Layer A */
500 [1] = 0x8d, /* Layer B */
501 [2] = 0x91, /* Layer C */
504 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
506 if (layer >= ARRAY_SIZE(reg))
509 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
512 rc = mb86a20s_readreg(state, 0x6e);
515 count = (rc >> 4) & 0x0f;
517 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
522 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
524 struct mb86a20s_state *state = fe->demodulator_priv;
525 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
527 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
529 /* Fixed parameters */
530 c->delivery_system = SYS_ISDBT;
531 c->bandwidth_hz = 6000000;
533 /* Initialize values that will be later autodetected */
534 c->isdbt_layer_enabled = 0;
535 c->transmission_mode = TRANSMISSION_MODE_AUTO;
536 c->guard_interval = GUARD_INTERVAL_AUTO;
537 c->isdbt_sb_mode = 0;
538 c->isdbt_sb_segment_count = 0;
542 * Estimates the bit rate using the per-segment bit rate given by
543 * ABNT/NBR 15601 spec (table 4).
545 static u32 isdbt_rate[3][5][4] = {
547 { 280850, 312060, 330420, 340430 }, /* 1/2 */
548 { 374470, 416080, 440560, 453910 }, /* 2/3 */
549 { 421280, 468090, 495630, 510650 }, /* 3/4 */
550 { 468090, 520100, 550700, 567390 }, /* 5/6 */
551 { 491500, 546110, 578230, 595760 }, /* 7/8 */
553 { 561710, 624130, 660840, 680870 }, /* 1/2 */
554 { 748950, 832170, 881120, 907820 }, /* 2/3 */
555 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
556 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
557 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
559 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
560 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
561 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
562 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
563 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
567 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
568 u32 modulation, u32 forward_error_correction,
572 struct mb86a20s_state *state = fe->demodulator_priv;
577 * If modulation/fec/interleaving is not detected, the default is
578 * to consider the lowest bit rate, to avoid taking too long time
581 switch (modulation) {
595 switch (forward_error_correction) {
615 switch (interleaving) {
617 case GUARD_INTERVAL_1_4:
620 case GUARD_INTERVAL_1_8:
623 case GUARD_INTERVAL_1_16:
626 case GUARD_INTERVAL_1_32:
631 /* Samples BER at BER_SAMPLING_RATE seconds */
632 rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE;
634 /* Avoids sampling too quickly or to overflow the register */
637 else if (rate > (1 << 24) - 1)
638 rate = (1 << 24) - 1;
640 dev_dbg(&state->i2c->dev,
641 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
642 __func__, 'A' + layer,
643 segment * isdbt_rate[mod][fec][guard]/1000,
646 state->estimated_rate[layer] = rate;
649 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
651 struct mb86a20s_state *state = fe->demodulator_priv;
652 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
655 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
657 /* Reset frontend cache to default values */
658 mb86a20s_reset_frontend_cache(fe);
660 /* Check for partial reception */
661 rc = mb86a20s_writereg(state, 0x6d, 0x85);
664 rc = mb86a20s_readreg(state, 0x6e);
667 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
669 /* Get per-layer data */
671 for (layer = 0; layer < NUM_LAYERS; layer++) {
672 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
673 __func__, 'A' + layer);
675 rc = mb86a20s_get_segment_count(state, layer);
677 goto noperlayer_error;
678 if (rc >= 0 && rc < 14) {
679 c->layer[layer].segment_count = rc;
681 c->layer[layer].segment_count = 0;
682 state->estimated_rate[layer] = 0;
685 c->isdbt_layer_enabled |= 1 << layer;
686 rc = mb86a20s_get_modulation(state, layer);
688 goto noperlayer_error;
689 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
691 c->layer[layer].modulation = rc;
692 rc = mb86a20s_get_fec(state, layer);
694 goto noperlayer_error;
695 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
697 c->layer[layer].fec = rc;
698 rc = mb86a20s_get_interleaving(state, layer);
700 goto noperlayer_error;
701 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
703 c->layer[layer].interleaving = rc;
704 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation,
706 c->layer[layer].interleaving,
707 c->layer[layer].segment_count);
710 rc = mb86a20s_writereg(state, 0x6d, 0x84);
713 if ((rc & 0x60) == 0x20) {
714 c->isdbt_sb_mode = 1;
715 /* At least, one segment should exist */
716 if (!c->isdbt_sb_segment_count)
717 c->isdbt_sb_segment_count = 1;
720 /* Get transmission mode and guard interval */
721 rc = mb86a20s_readreg(state, 0x07);
724 if ((rc & 0x60) == 0x20) {
725 switch (rc & 0x0c >> 2) {
727 c->transmission_mode = TRANSMISSION_MODE_2K;
730 c->transmission_mode = TRANSMISSION_MODE_4K;
733 c->transmission_mode = TRANSMISSION_MODE_8K;
740 c->guard_interval = GUARD_INTERVAL_1_4;
743 c->guard_interval = GUARD_INTERVAL_1_8;
746 c->guard_interval = GUARD_INTERVAL_1_16;
754 /* per-layer info is incomplete; discard all per-layer */
755 c->isdbt_layer_enabled = 0;
760 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
762 struct mb86a20s_state *state = fe->demodulator_priv;
763 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
766 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
768 /* Reset the counters, if the channel changed */
769 if (state->last_frequency != c->frequency) {
770 memset(&c->cnr, 0, sizeof(c->cnr));
771 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
772 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
773 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
774 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
775 memset(&c->block_error, 0, sizeof(c->block_error));
776 memset(&c->block_count, 0, sizeof(c->block_count));
778 state->last_frequency = c->frequency;
781 /* Clear status for most stats */
783 /* BER/PER counter reset */
784 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
788 /* CNR counter reset */
789 rc = mb86a20s_readreg(state, 0x45);
793 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
796 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
800 /* MER counter reset */
801 rc = mb86a20s_writereg(state, 0x50, 0x50);
804 rc = mb86a20s_readreg(state, 0x51);
808 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
811 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
817 dev_err(&state->i2c->dev,
818 "%s: Can't reset FE statistics (error %d).\n",
824 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
826 u32 *error, u32 *count)
828 struct mb86a20s_state *state = fe->demodulator_priv;
831 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
833 if (layer >= NUM_LAYERS)
836 /* Check if the BER measures are already available */
837 rc = mb86a20s_readreg(state, 0x54);
841 /* Check if data is available for that layer */
842 if (!(rc & (1 << layer))) {
843 dev_dbg(&state->i2c->dev,
844 "%s: preBER for layer %c is not available yet.\n",
845 __func__, 'A' + layer);
849 /* Read Bit Error Count */
850 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
854 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
858 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
863 dev_dbg(&state->i2c->dev,
864 "%s: bit error before Viterbi for layer %c: %d.\n",
865 __func__, 'A' + layer, *error);
868 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
871 rc = mb86a20s_readreg(state, 0x51);
875 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
878 rc = mb86a20s_readreg(state, 0x51);
882 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
885 rc = mb86a20s_readreg(state, 0x51);
890 dev_dbg(&state->i2c->dev,
891 "%s: bit count before Viterbi for layer %c: %d.\n",
892 __func__, 'A' + layer, *count);
896 * As we get TMCC data from the frontend, we can better estimate the
897 * BER bit counters, in order to do the BER measure during a longer
898 * time. Use those data, if available, to update the bit count
902 if (state->estimated_rate[layer]
903 && state->estimated_rate[layer] != *count) {
904 dev_dbg(&state->i2c->dev,
905 "%s: updating layer %c preBER counter to %d.\n",
906 __func__, 'A' + layer, state->estimated_rate[layer]);
908 /* Turn off BER before Viterbi */
909 rc = mb86a20s_writereg(state, 0x52, 0x00);
911 /* Update counter for this layer */
912 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
915 rc = mb86a20s_writereg(state, 0x51,
916 state->estimated_rate[layer] >> 16);
919 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
922 rc = mb86a20s_writereg(state, 0x51,
923 state->estimated_rate[layer] >> 8);
926 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
929 rc = mb86a20s_writereg(state, 0x51,
930 state->estimated_rate[layer]);
934 /* Turn on BER before Viterbi */
935 rc = mb86a20s_writereg(state, 0x52, 0x01);
937 /* Reset all preBER counters */
938 rc = mb86a20s_writereg(state, 0x53, 0x00);
941 rc = mb86a20s_writereg(state, 0x53, 0x07);
943 /* Reset counter to collect new data */
944 rc = mb86a20s_readreg(state, 0x53);
948 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
951 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
957 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
959 u32 *error, u32 *count)
961 struct mb86a20s_state *state = fe->demodulator_priv;
962 u32 counter, collect_rate;
965 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
967 if (layer >= NUM_LAYERS)
970 /* Check if the BER measures are already available */
971 rc = mb86a20s_readreg(state, 0x60);
975 /* Check if data is available for that layer */
976 if (!(rc & (1 << layer))) {
977 dev_dbg(&state->i2c->dev,
978 "%s: post BER for layer %c is not available yet.\n",
979 __func__, 'A' + layer);
983 /* Read Bit Error Count */
984 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
988 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
992 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
997 dev_dbg(&state->i2c->dev,
998 "%s: post bit error for layer %c: %d.\n",
999 __func__, 'A' + layer, *error);
1001 /* Read Bit Count */
1002 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1005 rc = mb86a20s_readreg(state, 0x51);
1009 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1012 rc = mb86a20s_readreg(state, 0x51);
1016 *count = counter * 204 * 8;
1018 dev_dbg(&state->i2c->dev,
1019 "%s: post bit count for layer %c: %d.\n",
1020 __func__, 'A' + layer, *count);
1023 * As we get TMCC data from the frontend, we can better estimate the
1024 * BER bit counters, in order to do the BER measure during a longer
1025 * time. Use those data, if available, to update the bit count
1029 if (!state->estimated_rate[layer])
1030 goto reset_measurement;
1032 collect_rate = state->estimated_rate[layer] / 204 / 8;
1033 if (collect_rate < 32)
1035 if (collect_rate > 65535)
1036 collect_rate = 65535;
1037 if (collect_rate != counter) {
1038 dev_dbg(&state->i2c->dev,
1039 "%s: updating postBER counter on layer %c to %d.\n",
1040 __func__, 'A' + layer, collect_rate);
1042 /* Turn off BER after Viterbi */
1043 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1045 /* Update counter for this layer */
1046 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1049 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1052 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1055 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1059 /* Turn on BER after Viterbi */
1060 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1062 /* Reset all preBER counters */
1063 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1066 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1072 /* Reset counter to collect new data */
1073 rc = mb86a20s_readreg(state, 0x5f);
1077 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1080 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1085 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1087 u32 *error, u32 *count)
1089 struct mb86a20s_state *state = fe->demodulator_priv;
1092 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1094 if (layer >= NUM_LAYERS)
1097 /* Check if the PER measures are already available */
1098 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1101 rc = mb86a20s_readreg(state, 0x51);
1105 /* Check if data is available for that layer */
1107 if (!(rc & (1 << layer))) {
1108 dev_dbg(&state->i2c->dev,
1109 "%s: block counts for layer %c aren't available yet.\n",
1110 __func__, 'A' + layer);
1114 /* Read Packet error Count */
1115 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1118 rc = mb86a20s_readreg(state, 0x51);
1122 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1125 rc = mb86a20s_readreg(state, 0x51);
1129 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1130 __func__, 'A' + layer, *error);
1132 /* Read Bit Count */
1133 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1136 rc = mb86a20s_readreg(state, 0x51);
1140 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1143 rc = mb86a20s_readreg(state, 0x51);
1148 dev_dbg(&state->i2c->dev,
1149 "%s: block count for layer %c: %d.\n",
1150 __func__, 'A' + layer, *count);
1153 * As we get TMCC data from the frontend, we can better estimate the
1154 * BER bit counters, in order to do the BER measure during a longer
1155 * time. Use those data, if available, to update the bit count
1159 if (!state->estimated_rate[layer])
1160 goto reset_measurement;
1162 collect_rate = state->estimated_rate[layer] / 204 / 8;
1163 if (collect_rate < 32)
1165 if (collect_rate > 65535)
1166 collect_rate = 65535;
1168 if (collect_rate != *count) {
1169 dev_dbg(&state->i2c->dev,
1170 "%s: updating PER counter on layer %c to %d.\n",
1171 __func__, 'A' + layer, collect_rate);
1173 /* Stop PER measurement */
1174 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1177 rc = mb86a20s_writereg(state, 0x51, 0x00);
1181 /* Update this layer's counter */
1182 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1185 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1188 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1191 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1195 /* start PER measurement */
1196 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1199 rc = mb86a20s_writereg(state, 0x51, 0x07);
1203 /* Reset all counters to collect new data */
1204 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1207 rc = mb86a20s_writereg(state, 0x51, 0x07);
1210 rc = mb86a20s_writereg(state, 0x51, 0x00);
1216 /* Reset counter to collect new data */
1217 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1220 rc = mb86a20s_readreg(state, 0x51);
1224 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1227 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1232 struct linear_segments {
1237 * All tables below return a dB/1000 measurement
1240 static struct linear_segments cnr_to_db_table[] = {
1274 static struct linear_segments cnr_64qam_table[] = {
1308 static struct linear_segments cnr_16qam_table[] = {
1342 struct linear_segments cnr_qpsk_table[] = {
1376 static u32 interpolate_value(u32 value, struct linear_segments *segments,
1383 if (value >= segments[0].x)
1384 return segments[0].y;
1385 if (value < segments[len-1].x)
1386 return segments[len-1].y;
1388 for (i = 1; i < len - 1; i++) {
1389 /* If value is identical, no need to interpolate */
1390 if (value == segments[i].x)
1391 return segments[i].y;
1392 if (value > segments[i].x)
1396 /* Linear interpolation between the two (x,y) points */
1397 dy = segments[i].y - segments[i - 1].y;
1398 dx = segments[i - 1].x - segments[i].x;
1399 tmp64 = value - segments[i].x;
1402 ret = segments[i].y - tmp64;
1407 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1409 struct mb86a20s_state *state = fe->demodulator_priv;
1410 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1411 u32 cnr_linear, cnr;
1414 /* Check if CNR is available */
1415 rc = mb86a20s_readreg(state, 0x45);
1420 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
1426 rc = mb86a20s_readreg(state, 0x46);
1429 cnr_linear = rc << 8;
1431 rc = mb86a20s_readreg(state, 0x46);
1436 cnr = interpolate_value(cnr_linear,
1437 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1439 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1440 c->cnr.stat[0].svalue = cnr;
1442 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1443 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1445 /* CNR counter reset */
1446 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1449 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1454 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1456 struct mb86a20s_state *state = fe->demodulator_priv;
1457 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1460 struct linear_segments *segs;
1463 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1465 /* Check if the measures are already available */
1466 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1469 rc = mb86a20s_readreg(state, 0x51);
1473 /* Check if data is available */
1475 dev_dbg(&state->i2c->dev,
1476 "%s: MER measures aren't available yet.\n", __func__);
1480 /* Read all layers */
1481 for (layer = 0; layer < NUM_LAYERS; layer++) {
1482 if (!(c->isdbt_layer_enabled & (1 << layer))) {
1483 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1487 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
1490 rc = mb86a20s_readreg(state, 0x51);
1494 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
1497 rc = mb86a20s_readreg(state, 0x51);
1501 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
1504 rc = mb86a20s_readreg(state, 0x51);
1509 switch (c->layer[layer].modulation) {
1512 segs = cnr_qpsk_table;
1513 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1516 segs = cnr_16qam_table;
1517 segs_len = ARRAY_SIZE(cnr_16qam_table);
1521 segs = cnr_64qam_table;
1522 segs_len = ARRAY_SIZE(cnr_64qam_table);
1525 cnr = interpolate_value(mer, segs, segs_len);
1527 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1528 c->cnr.stat[1 + layer].svalue = cnr;
1530 dev_dbg(&state->i2c->dev,
1531 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1532 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
1536 /* Start a new MER measurement */
1537 /* MER counter reset */
1538 rc = mb86a20s_writereg(state, 0x50, 0x50);
1541 rc = mb86a20s_readreg(state, 0x51);
1546 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1549 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1556 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1558 struct mb86a20s_state *state = fe->demodulator_priv;
1559 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1562 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1564 /* Fill the length of each status counter */
1566 /* Only global stats */
1567 c->strength.len = 1;
1569 /* Per-layer stats - 3 layers + global */
1570 c->cnr.len = NUM_LAYERS + 1;
1571 c->pre_bit_error.len = NUM_LAYERS + 1;
1572 c->pre_bit_count.len = NUM_LAYERS + 1;
1573 c->post_bit_error.len = NUM_LAYERS + 1;
1574 c->post_bit_count.len = NUM_LAYERS + 1;
1575 c->block_error.len = NUM_LAYERS + 1;
1576 c->block_count.len = NUM_LAYERS + 1;
1578 /* Signal is always available */
1579 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1580 c->strength.stat[0].uvalue = 0;
1582 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1583 for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1584 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1585 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1586 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1587 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1588 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1589 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1590 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1594 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
1596 struct mb86a20s_state *state = fe->demodulator_priv;
1597 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1599 u32 bit_error = 0, bit_count = 0;
1600 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1601 u32 t_post_bit_error = 0, t_post_bit_count = 0;
1602 u32 block_error = 0, block_count = 0;
1603 u32 t_block_error = 0, t_block_count = 0;
1604 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1607 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1609 mb86a20s_get_main_CNR(fe);
1611 /* Get per-layer stats */
1612 mb86a20s_get_blk_error_layer_CNR(fe);
1615 * At state 7, only CNR is available
1616 * For BER measures, state=9 is required
1617 * FIXME: we may get MER measures with state=8
1622 for (layer = 0; layer < NUM_LAYERS; layer++) {
1623 if (c->isdbt_layer_enabled & (1 << layer)) {
1624 /* Layer is active and has rc segments */
1627 /* Handle BER before vterbi */
1628 rc = mb86a20s_get_pre_ber(fe, layer,
1629 &bit_error, &bit_count);
1631 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1632 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1633 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1634 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
1635 } else if (rc != -EBUSY) {
1637 * If an I/O error happened,
1638 * measures are now unavailable
1640 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1641 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1642 dev_err(&state->i2c->dev,
1643 "%s: Can't get BER for layer %c (error %d).\n",
1644 __func__, 'A' + layer, rc);
1646 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1649 /* Handle BER post vterbi */
1650 rc = mb86a20s_get_post_ber(fe, layer,
1651 &bit_error, &bit_count);
1653 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1654 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1655 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1656 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
1657 } else if (rc != -EBUSY) {
1659 * If an I/O error happened,
1660 * measures are now unavailable
1662 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1663 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1664 dev_err(&state->i2c->dev,
1665 "%s: Can't get BER for layer %c (error %d).\n",
1666 __func__, 'A' + layer, rc);
1668 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1671 /* Handle Block errors for PER/UCB reports */
1672 rc = mb86a20s_get_blk_error(fe, layer,
1676 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1677 c->block_error.stat[1 + layer].uvalue += block_error;
1678 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1679 c->block_count.stat[1 + layer].uvalue += block_count;
1680 } else if (rc != -EBUSY) {
1682 * If an I/O error happened,
1683 * measures are now unavailable
1685 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1686 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1687 dev_err(&state->i2c->dev,
1688 "%s: Can't get PER for layer %c (error %d).\n",
1689 __func__, 'A' + layer, rc);
1692 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1695 /* Update total preBER */
1696 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1697 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
1699 /* Update total postBER */
1700 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1701 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
1703 /* Update total PER */
1704 t_block_error += c->block_error.stat[1 + layer].uvalue;
1705 t_block_count += c->block_count.stat[1 + layer].uvalue;
1710 * Start showing global count if at least one error count is
1713 if (pre_ber_layers) {
1715 * At least one per-layer BER measure was read. We can now
1716 * calculate the total BER
1718 * Total Bit Error/Count is calculated as the sum of the
1719 * bit errors on all active layers.
1721 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1722 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1723 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1724 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1726 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1727 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1731 * Start showing global count if at least one error count is
1734 if (post_ber_layers) {
1736 * At least one per-layer BER measure was read. We can now
1737 * calculate the total BER
1739 * Total Bit Error/Count is calculated as the sum of the
1740 * bit errors on all active layers.
1742 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1743 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1744 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1745 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1747 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1748 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1753 * At least one per-layer UCB measure was read. We can now
1754 * calculate the total UCB
1756 * Total block Error/Count is calculated as the sum of the
1757 * block errors on all active layers.
1759 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1760 c->block_error.stat[0].uvalue = t_block_error;
1761 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1762 c->block_count.stat[0].uvalue = t_block_count;
1764 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1765 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1772 * The functions below are called via DVB callbacks, so they need to
1773 * properly use the I2C gate control
1776 static int mb86a20s_initfe(struct dvb_frontend *fe)
1778 struct mb86a20s_state *state = fe->demodulator_priv;
1782 u8 regD5 = 1, reg71, reg09 = 0x3a;
1784 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1786 if (fe->ops.i2c_gate_ctrl)
1787 fe->ops.i2c_gate_ctrl(fe, 0);
1789 /* Initialize the frontend */
1790 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
1794 if (!state->inversion)
1796 rc = mb86a20s_writereg(state, 0x09, reg09);
1803 rc = mb86a20s_writereg(state, 0x39, reg71);
1806 rc = mb86a20s_writereg(state, 0x71, state->bw);
1809 if (state->subchannel) {
1810 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1815 fclk = state->config->fclk;
1819 /* Adjust IF frequency to match tuner */
1820 if (fe->ops.tuner_ops.get_if_frequency)
1821 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1823 if (!state->if_freq)
1824 state->if_freq = 3300000;
1826 pll = (((u64)1) << 34) * state->if_freq;
1827 do_div(pll, 63 * fclk);
1828 pll = (1 << 25) - pll;
1829 rc = mb86a20s_writereg(state, 0x28, 0x2a);
1832 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1835 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1838 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1841 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1842 __func__, fclk, state->if_freq, (long long)pll);
1844 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1845 pll = state->if_freq * 1677721600L;
1846 do_div(pll, 1628571429L);
1847 rc = mb86a20s_writereg(state, 0x28, 0x20);
1850 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1853 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1856 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1859 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
1860 __func__, state->if_freq, (long long)pll);
1862 if (!state->config->is_serial)
1865 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1868 rc = mb86a20s_writereg(state, 0x51, regD5);
1872 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1878 if (fe->ops.i2c_gate_ctrl)
1879 fe->ops.i2c_gate_ctrl(fe, 1);
1882 state->need_init = true;
1883 dev_info(&state->i2c->dev,
1884 "mb86a20s: Init failed. Will try again later\n");
1886 state->need_init = false;
1887 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1892 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1894 struct mb86a20s_state *state = fe->demodulator_priv;
1895 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1897 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1899 if (!c->isdbt_layer_enabled)
1900 c->isdbt_layer_enabled = 7;
1902 if (c->isdbt_layer_enabled == 1)
1903 state->bw = MB86A20S_1SEG;
1904 else if (c->isdbt_partial_reception)
1905 state->bw = MB86A20S_13SEG_PARTIAL;
1907 state->bw = MB86A20S_13SEG;
1909 if (c->inversion == INVERSION_ON)
1910 state->inversion = true;
1912 state->inversion = false;
1914 if (!c->isdbt_sb_mode) {
1915 state->subchannel = 0;
1917 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
1918 c->isdbt_sb_subchannel = 0;
1920 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1924 * Gate should already be opened, but it doesn't hurt to
1927 if (fe->ops.i2c_gate_ctrl)
1928 fe->ops.i2c_gate_ctrl(fe, 1);
1929 fe->ops.tuner_ops.set_params(fe);
1931 if (fe->ops.tuner_ops.get_if_frequency)
1932 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1935 * Make it more reliable: if, for some reason, the initial
1936 * device initialization doesn't happen, initialize it when
1937 * a SBTVD parameters are adjusted.
1939 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1940 * the agc callback logic is not called during DVB attach time,
1941 * causing mb86a20s to not be initialized with Kworld SBTVD.
1942 * So, this hack is needed, in order to make Kworld SBTVD to work.
1944 * It is also needed to change the IF after the initial init.
1946 * HACK: Always init the frontend when set_frontend is called:
1947 * it was noticed that, on some devices, it fails to lock on a
1948 * different channel. So, it is better to reset everything, even
1949 * wasting some time, than to loose channel lock.
1951 mb86a20s_initfe(fe);
1953 if (fe->ops.i2c_gate_ctrl)
1954 fe->ops.i2c_gate_ctrl(fe, 0);
1956 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1957 mb86a20s_reset_counters(fe);
1958 mb86a20s_stats_not_ready(fe);
1960 if (fe->ops.i2c_gate_ctrl)
1961 fe->ops.i2c_gate_ctrl(fe, 1);
1966 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1967 fe_status_t *status)
1969 struct mb86a20s_state *state = fe->demodulator_priv;
1972 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1974 if (fe->ops.i2c_gate_ctrl)
1975 fe->ops.i2c_gate_ctrl(fe, 0);
1978 status_nr = mb86a20s_read_status(fe, status);
1979 if (status_nr < 7) {
1980 mb86a20s_stats_not_ready(fe);
1981 mb86a20s_reset_frontend_cache(fe);
1983 if (status_nr < 0) {
1984 dev_err(&state->i2c->dev,
1985 "%s: Can't read frontend lock status\n", __func__);
1989 /* Get signal strength */
1990 rc = mb86a20s_read_signal_strength(fe);
1992 dev_err(&state->i2c->dev,
1993 "%s: Can't reset VBER registers.\n", __func__);
1994 mb86a20s_stats_not_ready(fe);
1995 mb86a20s_reset_frontend_cache(fe);
1997 rc = 0; /* Status is OK */
2001 if (status_nr >= 7) {
2003 rc = mb86a20s_get_frontend(fe);
2005 dev_err(&state->i2c->dev,
2006 "%s: Can't get FE TMCC data.\n", __func__);
2007 rc = 0; /* Status is OK */
2011 /* Get statistics */
2012 rc = mb86a20s_get_stats(fe, status_nr);
2013 if (rc < 0 && rc != -EBUSY) {
2014 dev_err(&state->i2c->dev,
2015 "%s: Can't get FE statistics.\n", __func__);
2019 rc = 0; /* Don't return EBUSY to userspace */
2024 mb86a20s_stats_not_ready(fe);
2027 if (fe->ops.i2c_gate_ctrl)
2028 fe->ops.i2c_gate_ctrl(fe, 1);
2033 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2036 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2039 *strength = c->strength.stat[0].uvalue;
2044 static int mb86a20s_get_frontend_dummy(struct dvb_frontend *fe)
2047 * get_frontend is now handled together with other stats
2048 * retrival, when read_status() is called, as some statistics
2049 * will depend on the layers detection.
2054 static int mb86a20s_tune(struct dvb_frontend *fe,
2056 unsigned int mode_flags,
2057 unsigned int *delay,
2058 fe_status_t *status)
2060 struct mb86a20s_state *state = fe->demodulator_priv;
2063 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2066 rc = mb86a20s_set_frontend(fe);
2068 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
2069 mb86a20s_read_status_and_stats(fe, status);
2074 static void mb86a20s_release(struct dvb_frontend *fe)
2076 struct mb86a20s_state *state = fe->demodulator_priv;
2078 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2083 static struct dvb_frontend_ops mb86a20s_ops;
2085 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2086 struct i2c_adapter *i2c)
2088 struct mb86a20s_state *state;
2091 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2093 /* allocate memory for the internal state */
2094 state = kzalloc(sizeof(struct mb86a20s_state), GFP_KERNEL);
2095 if (state == NULL) {
2097 "%s: unable to allocate memory for state\n", __func__);
2101 /* setup the state */
2102 state->config = config;
2105 /* create dvb_frontend */
2106 memcpy(&state->frontend.ops, &mb86a20s_ops,
2107 sizeof(struct dvb_frontend_ops));
2108 state->frontend.demodulator_priv = state;
2110 /* Check if it is a mb86a20s frontend */
2111 rev = mb86a20s_readreg(state, 0);
2115 "Detected a Fujitsu mb86a20s frontend\n");
2118 "Frontend revision %d is unknown - aborting.\n",
2123 return &state->frontend;
2129 EXPORT_SYMBOL(mb86a20s_attach);
2131 static struct dvb_frontend_ops mb86a20s_ops = {
2132 .delsys = { SYS_ISDBT },
2133 /* Use dib8000 values per default */
2135 .name = "Fujitsu mb86A20s",
2136 .caps = FE_CAN_RECOVER |
2137 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2138 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2139 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2140 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2141 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2142 /* Actually, those values depend on the used tuner */
2143 .frequency_min = 45000000,
2144 .frequency_max = 864000000,
2145 .frequency_stepsize = 62500,
2148 .release = mb86a20s_release,
2150 .init = mb86a20s_initfe,
2151 .set_frontend = mb86a20s_set_frontend,
2152 .get_frontend = mb86a20s_get_frontend_dummy,
2153 .read_status = mb86a20s_read_status_and_stats,
2154 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2155 .tune = mb86a20s_tune,
2158 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2159 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2160 MODULE_LICENSE("GPL");