1 // SPDX-License-Identifier: GPL-2.0-only
3 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
5 * Copyright (C) 2010-2013 Mauro Carvalho Chehab
6 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
9 #include <linux/kernel.h>
10 #include <asm/div64.h>
12 #include <media/dvb_frontend.h>
17 enum mb86a20s_bandwidth {
19 MB86A20S_13SEG_PARTIAL = 1,
24 static u8 mb86a20s_subchannel[] = {
25 0xb0, 0xc0, 0xd0, 0xe0,
26 0xf0, 0x00, 0x10, 0x20,
29 struct mb86a20s_state {
30 struct i2c_adapter *i2c;
31 const struct mb86a20s_config *config;
34 struct dvb_frontend frontend;
37 enum mb86a20s_bandwidth bw;
41 u32 estimated_rate[NUM_LAYERS];
42 unsigned long get_strength_time;
52 #define BER_SAMPLING_RATE 1 /* Seconds */
55 * Initialization sequence: Use whatevere default values that PV SBTVD
56 * does on its initialisation, obtained via USB snoop
58 static struct regdata mb86a20s_init1[] = {
62 { 0x50, 0xd1 }, { 0x51, 0x20 },
65 static struct regdata mb86a20s_init2[] = {
66 { 0x50, 0xd1 }, { 0x51, 0x22 },
72 { 0x04, 0x08 }, { 0x05, 0x05 },
73 { 0x04, 0x0e }, { 0x05, 0x00 },
74 { 0x04, 0x0f }, { 0x05, 0x14 },
75 { 0x04, 0x0b }, { 0x05, 0x8c },
76 { 0x04, 0x00 }, { 0x05, 0x00 },
77 { 0x04, 0x01 }, { 0x05, 0x07 },
78 { 0x04, 0x02 }, { 0x05, 0x0f },
79 { 0x04, 0x03 }, { 0x05, 0xa0 },
80 { 0x04, 0x09 }, { 0x05, 0x00 },
81 { 0x04, 0x0a }, { 0x05, 0xff },
82 { 0x04, 0x27 }, { 0x05, 0x64 },
83 { 0x04, 0x28 }, { 0x05, 0x00 },
84 { 0x04, 0x1e }, { 0x05, 0xff },
85 { 0x04, 0x29 }, { 0x05, 0x0a },
86 { 0x04, 0x32 }, { 0x05, 0x0a },
87 { 0x04, 0x14 }, { 0x05, 0x02 },
88 { 0x04, 0x04 }, { 0x05, 0x00 },
89 { 0x04, 0x05 }, { 0x05, 0x22 },
90 { 0x04, 0x06 }, { 0x05, 0x0e },
91 { 0x04, 0x07 }, { 0x05, 0xd8 },
92 { 0x04, 0x12 }, { 0x05, 0x00 },
93 { 0x04, 0x13 }, { 0x05, 0xff },
96 * On this demod, when the bit count reaches the count below,
97 * it collects the bit error count. The bit counters are initialized
98 * to 65535 here. This warrants that all of them will be quickly
99 * calculated when device gets locked. As TMCC is parsed, the values
100 * will be adjusted later in the driver's code.
102 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
103 { 0x50, 0xa7 }, { 0x51, 0x00 },
104 { 0x50, 0xa8 }, { 0x51, 0xff },
105 { 0x50, 0xa9 }, { 0x51, 0xff },
106 { 0x50, 0xaa }, { 0x51, 0x00 },
107 { 0x50, 0xab }, { 0x51, 0xff },
108 { 0x50, 0xac }, { 0x51, 0xff },
109 { 0x50, 0xad }, { 0x51, 0x00 },
110 { 0x50, 0xae }, { 0x51, 0xff },
111 { 0x50, 0xaf }, { 0x51, 0xff },
114 * On this demod, post BER counts blocks. When the count reaches the
115 * value below, it collects the block error count. The block counters
116 * are initialized to 127 here. This warrants that all of them will be
117 * quickly calculated when device gets locked. As TMCC is parsed, the
118 * values will be adjusted later in the driver's code.
120 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
121 { 0x50, 0xdc }, { 0x51, 0x00 },
122 { 0x50, 0xdd }, { 0x51, 0x7f },
123 { 0x50, 0xde }, { 0x51, 0x00 },
124 { 0x50, 0xdf }, { 0x51, 0x7f },
125 { 0x50, 0xe0 }, { 0x51, 0x00 },
126 { 0x50, 0xe1 }, { 0x51, 0x7f },
129 * On this demod, when the block count reaches the count below,
130 * it collects the block error count. The block counters are initialized
131 * to 127 here. This warrants that all of them will be quickly
132 * calculated when device gets locked. As TMCC is parsed, the values
133 * will be adjusted later in the driver's code.
135 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
136 { 0x50, 0xb2 }, { 0x51, 0x00 },
137 { 0x50, 0xb3 }, { 0x51, 0x7f },
138 { 0x50, 0xb4 }, { 0x51, 0x00 },
139 { 0x50, 0xb5 }, { 0x51, 0x7f },
140 { 0x50, 0xb6 }, { 0x51, 0x00 },
141 { 0x50, 0xb7 }, { 0x51, 0x7f },
143 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
144 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
145 { 0x45, 0x04 }, /* CN symbol 4 */
146 { 0x48, 0x04 }, /* CN manual mode */
147 { 0x50, 0xd5 }, { 0x51, 0x01 },
148 { 0x50, 0xd6 }, { 0x51, 0x1f },
149 { 0x50, 0xd2 }, { 0x51, 0x03 },
150 { 0x50, 0xd7 }, { 0x51, 0x3f },
152 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
153 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
154 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
155 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
156 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
157 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
158 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
159 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
160 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
161 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
162 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
163 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
164 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
165 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
166 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
167 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
168 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
169 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
170 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
171 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
172 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
173 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
174 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
175 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
176 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
177 { 0x50, 0x1e }, { 0x51, 0x5d },
178 { 0x50, 0x22 }, { 0x51, 0x00 },
179 { 0x50, 0x23 }, { 0x51, 0xc8 },
180 { 0x50, 0x24 }, { 0x51, 0x00 },
181 { 0x50, 0x25 }, { 0x51, 0xf0 },
182 { 0x50, 0x26 }, { 0x51, 0x00 },
183 { 0x50, 0x27 }, { 0x51, 0xc3 },
184 { 0x50, 0x39 }, { 0x51, 0x02 },
185 { 0x50, 0xd5 }, { 0x51, 0x01 },
189 static struct regdata mb86a20s_reset_reception[] = {
196 static struct regdata mb86a20s_per_ber_reset[] = {
197 { 0x53, 0x00 }, /* pre BER Counter reset */
200 { 0x5f, 0x00 }, /* post BER Counter reset */
203 { 0x50, 0xb1 }, /* PER Counter reset */
209 * I2C read/write functions and macros
212 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
213 u8 i2c_addr, u8 reg, u8 data)
215 u8 buf[] = { reg, data };
216 struct i2c_msg msg = {
217 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
221 rc = i2c_transfer(state->i2c, &msg, 1);
223 dev_err(&state->i2c->dev,
224 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
225 __func__, rc, reg, data);
232 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
233 u8 i2c_addr, struct regdata *rd, int size)
237 for (i = 0; i < size; i++) {
238 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
246 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
251 struct i2c_msg msg[] = {
252 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
253 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
256 rc = i2c_transfer(state->i2c, msg, 2);
259 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
261 return (rc < 0) ? rc : -EIO;
267 #define mb86a20s_readreg(state, reg) \
268 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
269 #define mb86a20s_writereg(state, reg, val) \
270 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
271 #define mb86a20s_writeregdata(state, regdata) \
272 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
273 regdata, ARRAY_SIZE(regdata))
276 * Ancillary internal routines (likely compiled inlined)
278 * The functions below assume that gateway lock has already obtained
281 static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status)
283 struct mb86a20s_state *state = fe->demodulator_priv;
288 val = mb86a20s_readreg(state, 0x0a);
294 *status |= FE_HAS_SIGNAL;
297 *status |= FE_HAS_CARRIER;
300 *status |= FE_HAS_VITERBI;
303 *status |= FE_HAS_SYNC;
306 * Actually, on state S8, it starts receiving TS, but the TS
307 * output is only on normal state after the transition to S9.
310 *status |= FE_HAS_LOCK;
312 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
313 __func__, *status, val);
318 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
320 struct mb86a20s_state *state = fe->demodulator_priv;
321 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
323 unsigned rf_max, rf_min, rf;
325 if (state->get_strength_time &&
326 (!time_after(jiffies, state->get_strength_time)))
327 return c->strength.stat[0].uvalue;
329 /* Reset its value if an error happen */
330 c->strength.stat[0].uvalue = 0;
332 /* Does a binary search to get RF strength */
336 rf = (rf_max + rf_min) / 2;
337 rc = mb86a20s_writereg(state, 0x04, 0x1f);
340 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
343 rc = mb86a20s_writereg(state, 0x04, 0x20);
346 rc = mb86a20s_writereg(state, 0x05, rf);
350 rc = mb86a20s_readreg(state, 0x02);
354 rf_min = (rf_max + rf_min) / 2;
356 rf_max = (rf_max + rf_min) / 2;
357 if (rf_max - rf_min < 4) {
358 rf = (rf_max + rf_min) / 2;
360 /* Rescale it from 2^12 (4096) to 2^16 */
361 rf = rf << (16 - 12);
365 dev_dbg(&state->i2c->dev,
366 "%s: signal strength = %d (%d < RF=%d < %d)\n",
367 __func__, rf, rf_min, rf >> 4, rf_max);
368 c->strength.stat[0].uvalue = rf;
369 state->get_strength_time = jiffies +
370 msecs_to_jiffies(1000);
376 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
380 static unsigned char reg[] = {
381 [0] = 0x86, /* Layer A */
382 [1] = 0x8a, /* Layer B */
383 [2] = 0x8e, /* Layer C */
386 if (layer >= ARRAY_SIZE(reg))
388 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
391 rc = mb86a20s_readreg(state, 0x6e);
394 switch ((rc >> 4) & 0x07) {
408 static int mb86a20s_get_fec(struct mb86a20s_state *state,
413 static unsigned char reg[] = {
414 [0] = 0x87, /* Layer A */
415 [1] = 0x8b, /* Layer B */
416 [2] = 0x8f, /* Layer C */
419 if (layer >= ARRAY_SIZE(reg))
421 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
424 rc = mb86a20s_readreg(state, 0x6e);
427 switch ((rc >> 4) & 0x07) {
443 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
447 int interleaving[] = {
451 static unsigned char reg[] = {
452 [0] = 0x88, /* Layer A */
453 [1] = 0x8c, /* Layer B */
454 [2] = 0x90, /* Layer C */
457 if (layer >= ARRAY_SIZE(reg))
459 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
462 rc = mb86a20s_readreg(state, 0x6e);
466 return interleaving[(rc >> 4) & 0x07];
469 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
473 static unsigned char reg[] = {
474 [0] = 0x89, /* Layer A */
475 [1] = 0x8d, /* Layer B */
476 [2] = 0x91, /* Layer C */
479 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
481 if (layer >= ARRAY_SIZE(reg))
484 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
487 rc = mb86a20s_readreg(state, 0x6e);
490 count = (rc >> 4) & 0x0f;
492 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
497 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
499 struct mb86a20s_state *state = fe->demodulator_priv;
500 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
502 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
504 /* Fixed parameters */
505 c->delivery_system = SYS_ISDBT;
506 c->bandwidth_hz = 6000000;
508 /* Initialize values that will be later autodetected */
509 c->isdbt_layer_enabled = 0;
510 c->transmission_mode = TRANSMISSION_MODE_AUTO;
511 c->guard_interval = GUARD_INTERVAL_AUTO;
512 c->isdbt_sb_mode = 0;
513 c->isdbt_sb_segment_count = 0;
517 * Estimates the bit rate using the per-segment bit rate given by
518 * ABNT/NBR 15601 spec (table 4).
520 static u32 isdbt_rate[3][5][4] = {
522 { 280850, 312060, 330420, 340430 }, /* 1/2 */
523 { 374470, 416080, 440560, 453910 }, /* 2/3 */
524 { 421280, 468090, 495630, 510650 }, /* 3/4 */
525 { 468090, 520100, 550700, 567390 }, /* 5/6 */
526 { 491500, 546110, 578230, 595760 }, /* 7/8 */
528 { 561710, 624130, 660840, 680870 }, /* 1/2 */
529 { 748950, 832170, 881120, 907820 }, /* 2/3 */
530 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
531 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
532 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
534 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
535 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
536 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
537 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
538 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
542 static void mb86a20s_layer_bitrate(struct dvb_frontend *fe, u32 layer,
543 u32 modulation, u32 forward_error_correction,
547 struct mb86a20s_state *state = fe->demodulator_priv;
552 * If modulation/fec/guard is not detected, the default is
553 * to consider the lowest bit rate, to avoid taking too long time
556 switch (modulation) {
570 switch (forward_error_correction) {
590 switch (guard_interval) {
592 case GUARD_INTERVAL_1_4:
595 case GUARD_INTERVAL_1_8:
598 case GUARD_INTERVAL_1_16:
601 case GUARD_INTERVAL_1_32:
606 /* Samples BER at BER_SAMPLING_RATE seconds */
607 rate = isdbt_rate[mod][fec][guard] * segment * BER_SAMPLING_RATE;
609 /* Avoids sampling too quickly or to overflow the register */
612 else if (rate > (1 << 24) - 1)
613 rate = (1 << 24) - 1;
615 dev_dbg(&state->i2c->dev,
616 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
617 __func__, 'A' + layer,
618 segment * isdbt_rate[mod][fec][guard]/1000,
621 state->estimated_rate[layer] = rate;
624 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
626 struct mb86a20s_state *state = fe->demodulator_priv;
627 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
630 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
632 /* Reset frontend cache to default values */
633 mb86a20s_reset_frontend_cache(fe);
635 /* Check for partial reception */
636 rc = mb86a20s_writereg(state, 0x6d, 0x85);
639 rc = mb86a20s_readreg(state, 0x6e);
642 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
644 /* Get per-layer data */
646 for (layer = 0; layer < NUM_LAYERS; layer++) {
647 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
648 __func__, 'A' + layer);
650 rc = mb86a20s_get_segment_count(state, layer);
652 goto noperlayer_error;
653 if (rc >= 0 && rc < 14) {
654 c->layer[layer].segment_count = rc;
656 c->layer[layer].segment_count = 0;
657 state->estimated_rate[layer] = 0;
660 c->isdbt_layer_enabled |= 1 << layer;
661 rc = mb86a20s_get_modulation(state, layer);
663 goto noperlayer_error;
664 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
666 c->layer[layer].modulation = rc;
667 rc = mb86a20s_get_fec(state, layer);
669 goto noperlayer_error;
670 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
672 c->layer[layer].fec = rc;
673 rc = mb86a20s_get_interleaving(state, layer);
675 goto noperlayer_error;
676 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
678 c->layer[layer].interleaving = rc;
679 mb86a20s_layer_bitrate(fe, layer, c->layer[layer].modulation,
682 c->layer[layer].segment_count);
685 rc = mb86a20s_writereg(state, 0x6d, 0x84);
688 if ((rc & 0x60) == 0x20) {
689 c->isdbt_sb_mode = 1;
690 /* At least, one segment should exist */
691 if (!c->isdbt_sb_segment_count)
692 c->isdbt_sb_segment_count = 1;
695 /* Get transmission mode and guard interval */
696 rc = mb86a20s_readreg(state, 0x07);
699 c->transmission_mode = TRANSMISSION_MODE_AUTO;
700 if ((rc & 0x60) == 0x20) {
701 /* Only modes 2 and 3 are supported */
702 switch ((rc >> 2) & 0x03) {
704 c->transmission_mode = TRANSMISSION_MODE_4K;
707 c->transmission_mode = TRANSMISSION_MODE_8K;
711 c->guard_interval = GUARD_INTERVAL_AUTO;
713 /* Guard interval 1/32 is not supported */
716 c->guard_interval = GUARD_INTERVAL_1_4;
719 c->guard_interval = GUARD_INTERVAL_1_8;
722 c->guard_interval = GUARD_INTERVAL_1_16;
730 /* per-layer info is incomplete; discard all per-layer */
731 c->isdbt_layer_enabled = 0;
736 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
738 struct mb86a20s_state *state = fe->demodulator_priv;
739 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
742 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
744 /* Reset the counters, if the channel changed */
745 if (state->last_frequency != c->frequency) {
746 memset(&c->cnr, 0, sizeof(c->cnr));
747 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
748 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
749 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
750 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
751 memset(&c->block_error, 0, sizeof(c->block_error));
752 memset(&c->block_count, 0, sizeof(c->block_count));
754 state->last_frequency = c->frequency;
757 /* Clear status for most stats */
759 /* BER/PER counter reset */
760 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
764 /* CNR counter reset */
765 rc = mb86a20s_readreg(state, 0x45);
769 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
772 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
776 /* MER counter reset */
777 rc = mb86a20s_writereg(state, 0x50, 0x50);
780 rc = mb86a20s_readreg(state, 0x51);
784 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
787 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
793 dev_err(&state->i2c->dev,
794 "%s: Can't reset FE statistics (error %d).\n",
800 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
802 u32 *error, u32 *count)
804 struct mb86a20s_state *state = fe->demodulator_priv;
807 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
809 if (layer >= NUM_LAYERS)
812 /* Check if the BER measures are already available */
813 rc = mb86a20s_readreg(state, 0x54);
817 /* Check if data is available for that layer */
818 if (!(rc & (1 << layer))) {
819 dev_dbg(&state->i2c->dev,
820 "%s: preBER for layer %c is not available yet.\n",
821 __func__, 'A' + layer);
825 /* Read Bit Error Count */
826 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
830 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
834 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
839 dev_dbg(&state->i2c->dev,
840 "%s: bit error before Viterbi for layer %c: %d.\n",
841 __func__, 'A' + layer, *error);
844 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
847 rc = mb86a20s_readreg(state, 0x51);
851 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
854 rc = mb86a20s_readreg(state, 0x51);
858 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
861 rc = mb86a20s_readreg(state, 0x51);
866 dev_dbg(&state->i2c->dev,
867 "%s: bit count before Viterbi for layer %c: %d.\n",
868 __func__, 'A' + layer, *count);
872 * As we get TMCC data from the frontend, we can better estimate the
873 * BER bit counters, in order to do the BER measure during a longer
874 * time. Use those data, if available, to update the bit count
878 if (state->estimated_rate[layer]
879 && state->estimated_rate[layer] != *count) {
880 dev_dbg(&state->i2c->dev,
881 "%s: updating layer %c preBER counter to %d.\n",
882 __func__, 'A' + layer, state->estimated_rate[layer]);
884 /* Turn off BER before Viterbi */
885 rc = mb86a20s_writereg(state, 0x52, 0x00);
887 /* Update counter for this layer */
888 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
891 rc = mb86a20s_writereg(state, 0x51,
892 state->estimated_rate[layer] >> 16);
895 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
898 rc = mb86a20s_writereg(state, 0x51,
899 state->estimated_rate[layer] >> 8);
902 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
905 rc = mb86a20s_writereg(state, 0x51,
906 state->estimated_rate[layer]);
910 /* Turn on BER before Viterbi */
911 rc = mb86a20s_writereg(state, 0x52, 0x01);
913 /* Reset all preBER counters */
914 rc = mb86a20s_writereg(state, 0x53, 0x00);
917 rc = mb86a20s_writereg(state, 0x53, 0x07);
919 /* Reset counter to collect new data */
920 rc = mb86a20s_readreg(state, 0x53);
924 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
927 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
933 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
935 u32 *error, u32 *count)
937 struct mb86a20s_state *state = fe->demodulator_priv;
938 u32 counter, collect_rate;
941 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
943 if (layer >= NUM_LAYERS)
946 /* Check if the BER measures are already available */
947 rc = mb86a20s_readreg(state, 0x60);
951 /* Check if data is available for that layer */
952 if (!(rc & (1 << layer))) {
953 dev_dbg(&state->i2c->dev,
954 "%s: post BER for layer %c is not available yet.\n",
955 __func__, 'A' + layer);
959 /* Read Bit Error Count */
960 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
964 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
968 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
973 dev_dbg(&state->i2c->dev,
974 "%s: post bit error for layer %c: %d.\n",
975 __func__, 'A' + layer, *error);
978 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
981 rc = mb86a20s_readreg(state, 0x51);
985 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
988 rc = mb86a20s_readreg(state, 0x51);
992 *count = counter * 204 * 8;
994 dev_dbg(&state->i2c->dev,
995 "%s: post bit count for layer %c: %d.\n",
996 __func__, 'A' + layer, *count);
999 * As we get TMCC data from the frontend, we can better estimate the
1000 * BER bit counters, in order to do the BER measure during a longer
1001 * time. Use those data, if available, to update the bit count
1005 if (!state->estimated_rate[layer])
1006 goto reset_measurement;
1008 collect_rate = state->estimated_rate[layer] / 204 / 8;
1009 if (collect_rate < 32)
1011 if (collect_rate > 65535)
1012 collect_rate = 65535;
1013 if (collect_rate != counter) {
1014 dev_dbg(&state->i2c->dev,
1015 "%s: updating postBER counter on layer %c to %d.\n",
1016 __func__, 'A' + layer, collect_rate);
1018 /* Turn off BER after Viterbi */
1019 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1021 /* Update counter for this layer */
1022 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1025 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1028 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1031 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1035 /* Turn on BER after Viterbi */
1036 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1038 /* Reset all preBER counters */
1039 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1042 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1048 /* Reset counter to collect new data */
1049 rc = mb86a20s_readreg(state, 0x5f);
1053 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1056 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1061 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1063 u32 *error, u32 *count)
1065 struct mb86a20s_state *state = fe->demodulator_priv;
1068 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1070 if (layer >= NUM_LAYERS)
1073 /* Check if the PER measures are already available */
1074 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1077 rc = mb86a20s_readreg(state, 0x51);
1081 /* Check if data is available for that layer */
1083 if (!(rc & (1 << layer))) {
1084 dev_dbg(&state->i2c->dev,
1085 "%s: block counts for layer %c aren't available yet.\n",
1086 __func__, 'A' + layer);
1090 /* Read Packet error Count */
1091 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1094 rc = mb86a20s_readreg(state, 0x51);
1098 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1101 rc = mb86a20s_readreg(state, 0x51);
1105 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1106 __func__, 'A' + layer, *error);
1108 /* Read Bit Count */
1109 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1112 rc = mb86a20s_readreg(state, 0x51);
1116 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1119 rc = mb86a20s_readreg(state, 0x51);
1124 dev_dbg(&state->i2c->dev,
1125 "%s: block count for layer %c: %d.\n",
1126 __func__, 'A' + layer, *count);
1129 * As we get TMCC data from the frontend, we can better estimate the
1130 * BER bit counters, in order to do the BER measure during a longer
1131 * time. Use those data, if available, to update the bit count
1135 if (!state->estimated_rate[layer])
1136 goto reset_measurement;
1138 collect_rate = state->estimated_rate[layer] / 204 / 8;
1139 if (collect_rate < 32)
1141 if (collect_rate > 65535)
1142 collect_rate = 65535;
1144 if (collect_rate != *count) {
1145 dev_dbg(&state->i2c->dev,
1146 "%s: updating PER counter on layer %c to %d.\n",
1147 __func__, 'A' + layer, collect_rate);
1149 /* Stop PER measurement */
1150 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1153 rc = mb86a20s_writereg(state, 0x51, 0x00);
1157 /* Update this layer's counter */
1158 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1161 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1164 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1167 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1171 /* start PER measurement */
1172 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1175 rc = mb86a20s_writereg(state, 0x51, 0x07);
1179 /* Reset all counters to collect new data */
1180 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1183 rc = mb86a20s_writereg(state, 0x51, 0x07);
1186 rc = mb86a20s_writereg(state, 0x51, 0x00);
1192 /* Reset counter to collect new data */
1193 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1196 rc = mb86a20s_readreg(state, 0x51);
1200 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1203 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1208 struct linear_segments {
1213 * All tables below return a dB/1000 measurement
1216 static const struct linear_segments cnr_to_db_table[] = {
1250 static const struct linear_segments cnr_64qam_table[] = {
1284 static const struct linear_segments cnr_16qam_table[] = {
1318 static const struct linear_segments cnr_qpsk_table[] = {
1352 static u32 interpolate_value(u32 value, const struct linear_segments *segments,
1359 if (value >= segments[0].x)
1360 return segments[0].y;
1361 if (value < segments[len-1].x)
1362 return segments[len-1].y;
1364 for (i = 1; i < len - 1; i++) {
1365 /* If value is identical, no need to interpolate */
1366 if (value == segments[i].x)
1367 return segments[i].y;
1368 if (value > segments[i].x)
1372 /* Linear interpolation between the two (x,y) points */
1373 dy = segments[i].y - segments[i - 1].y;
1374 dx = segments[i - 1].x - segments[i].x;
1375 tmp64 = value - segments[i].x;
1378 ret = segments[i].y - tmp64;
1383 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1385 struct mb86a20s_state *state = fe->demodulator_priv;
1386 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1387 u32 cnr_linear, cnr;
1390 /* Check if CNR is available */
1391 rc = mb86a20s_readreg(state, 0x45);
1396 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
1402 rc = mb86a20s_readreg(state, 0x46);
1405 cnr_linear = rc << 8;
1407 rc = mb86a20s_readreg(state, 0x46);
1412 cnr = interpolate_value(cnr_linear,
1413 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1415 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1416 c->cnr.stat[0].svalue = cnr;
1418 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1419 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1421 /* CNR counter reset */
1422 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1425 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1430 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1432 struct mb86a20s_state *state = fe->demodulator_priv;
1433 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1436 const struct linear_segments *segs;
1439 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1441 /* Check if the measures are already available */
1442 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1445 rc = mb86a20s_readreg(state, 0x51);
1449 /* Check if data is available */
1451 dev_dbg(&state->i2c->dev,
1452 "%s: MER measures aren't available yet.\n", __func__);
1456 /* Read all layers */
1457 for (layer = 0; layer < NUM_LAYERS; layer++) {
1458 if (!(c->isdbt_layer_enabled & (1 << layer))) {
1459 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1463 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
1466 rc = mb86a20s_readreg(state, 0x51);
1470 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
1473 rc = mb86a20s_readreg(state, 0x51);
1477 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
1480 rc = mb86a20s_readreg(state, 0x51);
1485 switch (c->layer[layer].modulation) {
1488 segs = cnr_qpsk_table;
1489 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1492 segs = cnr_16qam_table;
1493 segs_len = ARRAY_SIZE(cnr_16qam_table);
1497 segs = cnr_64qam_table;
1498 segs_len = ARRAY_SIZE(cnr_64qam_table);
1501 cnr = interpolate_value(mer, segs, segs_len);
1503 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1504 c->cnr.stat[1 + layer].svalue = cnr;
1506 dev_dbg(&state->i2c->dev,
1507 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1508 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
1512 /* Start a new MER measurement */
1513 /* MER counter reset */
1514 rc = mb86a20s_writereg(state, 0x50, 0x50);
1517 rc = mb86a20s_readreg(state, 0x51);
1522 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1525 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1532 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1534 struct mb86a20s_state *state = fe->demodulator_priv;
1535 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1538 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1540 /* Fill the length of each status counter */
1542 /* Only global stats */
1543 c->strength.len = 1;
1545 /* Per-layer stats - 3 layers + global */
1546 c->cnr.len = NUM_LAYERS + 1;
1547 c->pre_bit_error.len = NUM_LAYERS + 1;
1548 c->pre_bit_count.len = NUM_LAYERS + 1;
1549 c->post_bit_error.len = NUM_LAYERS + 1;
1550 c->post_bit_count.len = NUM_LAYERS + 1;
1551 c->block_error.len = NUM_LAYERS + 1;
1552 c->block_count.len = NUM_LAYERS + 1;
1554 /* Signal is always available */
1555 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1556 c->strength.stat[0].uvalue = 0;
1558 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1559 for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1560 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1561 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1562 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1563 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1564 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1565 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1566 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1570 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
1572 struct mb86a20s_state *state = fe->demodulator_priv;
1573 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1575 u32 bit_error = 0, bit_count = 0;
1576 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1577 u32 t_post_bit_error = 0, t_post_bit_count = 0;
1578 u32 block_error = 0, block_count = 0;
1579 u32 t_block_error = 0, t_block_count = 0;
1580 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1583 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1585 mb86a20s_get_main_CNR(fe);
1587 /* Get per-layer stats */
1588 mb86a20s_get_blk_error_layer_CNR(fe);
1591 * At state 7, only CNR is available
1592 * For BER measures, state=9 is required
1593 * FIXME: we may get MER measures with state=8
1598 for (layer = 0; layer < NUM_LAYERS; layer++) {
1599 if (c->isdbt_layer_enabled & (1 << layer)) {
1600 /* Layer is active and has rc segments */
1603 /* Handle BER before vterbi */
1604 rc = mb86a20s_get_pre_ber(fe, layer,
1605 &bit_error, &bit_count);
1607 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1608 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1609 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1610 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
1611 } else if (rc != -EBUSY) {
1613 * If an I/O error happened,
1614 * measures are now unavailable
1616 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1617 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1618 dev_err(&state->i2c->dev,
1619 "%s: Can't get BER for layer %c (error %d).\n",
1620 __func__, 'A' + layer, rc);
1622 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1625 /* Handle BER post vterbi */
1626 rc = mb86a20s_get_post_ber(fe, layer,
1627 &bit_error, &bit_count);
1629 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1630 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1631 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1632 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
1633 } else if (rc != -EBUSY) {
1635 * If an I/O error happened,
1636 * measures are now unavailable
1638 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1639 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1640 dev_err(&state->i2c->dev,
1641 "%s: Can't get BER for layer %c (error %d).\n",
1642 __func__, 'A' + layer, rc);
1644 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1647 /* Handle Block errors for PER/UCB reports */
1648 rc = mb86a20s_get_blk_error(fe, layer,
1652 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1653 c->block_error.stat[1 + layer].uvalue += block_error;
1654 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1655 c->block_count.stat[1 + layer].uvalue += block_count;
1656 } else if (rc != -EBUSY) {
1658 * If an I/O error happened,
1659 * measures are now unavailable
1661 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1662 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1663 dev_err(&state->i2c->dev,
1664 "%s: Can't get PER for layer %c (error %d).\n",
1665 __func__, 'A' + layer, rc);
1668 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1671 /* Update total preBER */
1672 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1673 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
1675 /* Update total postBER */
1676 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1677 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
1679 /* Update total PER */
1680 t_block_error += c->block_error.stat[1 + layer].uvalue;
1681 t_block_count += c->block_count.stat[1 + layer].uvalue;
1686 * Start showing global count if at least one error count is
1689 if (pre_ber_layers) {
1691 * At least one per-layer BER measure was read. We can now
1692 * calculate the total BER
1694 * Total Bit Error/Count is calculated as the sum of the
1695 * bit errors on all active layers.
1697 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1698 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1699 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1700 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1702 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1703 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1707 * Start showing global count if at least one error count is
1710 if (post_ber_layers) {
1712 * At least one per-layer BER measure was read. We can now
1713 * calculate the total BER
1715 * Total Bit Error/Count is calculated as the sum of the
1716 * bit errors on all active layers.
1718 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1719 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1720 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1721 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1723 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1724 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1729 * At least one per-layer UCB measure was read. We can now
1730 * calculate the total UCB
1732 * Total block Error/Count is calculated as the sum of the
1733 * block errors on all active layers.
1735 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1736 c->block_error.stat[0].uvalue = t_block_error;
1737 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1738 c->block_count.stat[0].uvalue = t_block_count;
1740 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1741 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1748 * The functions below are called via DVB callbacks, so they need to
1749 * properly use the I2C gate control
1752 static int mb86a20s_initfe(struct dvb_frontend *fe)
1754 struct mb86a20s_state *state = fe->demodulator_priv;
1758 u8 regD5 = 1, reg71, reg09 = 0x3a;
1760 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1762 if (fe->ops.i2c_gate_ctrl)
1763 fe->ops.i2c_gate_ctrl(fe, 0);
1765 /* Initialize the frontend */
1766 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
1770 if (!state->inversion)
1772 rc = mb86a20s_writereg(state, 0x09, reg09);
1779 rc = mb86a20s_writereg(state, 0x39, reg71);
1782 rc = mb86a20s_writereg(state, 0x71, state->bw);
1785 if (state->subchannel) {
1786 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1791 fclk = state->config->fclk;
1795 /* Adjust IF frequency to match tuner */
1796 if (fe->ops.tuner_ops.get_if_frequency)
1797 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1799 if (!state->if_freq)
1800 state->if_freq = 3300000;
1802 pll = (((u64)1) << 34) * state->if_freq;
1803 do_div(pll, 63 * fclk);
1804 pll = (1 << 25) - pll;
1805 rc = mb86a20s_writereg(state, 0x28, 0x2a);
1808 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1811 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1814 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1817 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1818 __func__, fclk, state->if_freq, (long long)pll);
1820 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1821 pll = state->if_freq * 1677721600L;
1822 do_div(pll, 1628571429L);
1823 rc = mb86a20s_writereg(state, 0x28, 0x20);
1826 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1829 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1832 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1835 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
1836 __func__, state->if_freq, (long long)pll);
1838 if (!state->config->is_serial)
1841 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1844 rc = mb86a20s_writereg(state, 0x51, regD5);
1848 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1854 if (fe->ops.i2c_gate_ctrl)
1855 fe->ops.i2c_gate_ctrl(fe, 1);
1858 state->need_init = true;
1859 dev_info(&state->i2c->dev,
1860 "mb86a20s: Init failed. Will try again later\n");
1862 state->need_init = false;
1863 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1868 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1870 struct mb86a20s_state *state = fe->demodulator_priv;
1871 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1873 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1875 if (!c->isdbt_layer_enabled)
1876 c->isdbt_layer_enabled = 7;
1878 if (c->isdbt_layer_enabled == 1)
1879 state->bw = MB86A20S_1SEG;
1880 else if (c->isdbt_partial_reception)
1881 state->bw = MB86A20S_13SEG_PARTIAL;
1883 state->bw = MB86A20S_13SEG;
1885 if (c->inversion == INVERSION_ON)
1886 state->inversion = true;
1888 state->inversion = false;
1890 if (!c->isdbt_sb_mode) {
1891 state->subchannel = 0;
1893 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
1894 c->isdbt_sb_subchannel = 0;
1896 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1900 * Gate should already be opened, but it doesn't hurt to
1903 if (fe->ops.i2c_gate_ctrl)
1904 fe->ops.i2c_gate_ctrl(fe, 1);
1905 fe->ops.tuner_ops.set_params(fe);
1907 if (fe->ops.tuner_ops.get_if_frequency)
1908 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1911 * Make it more reliable: if, for some reason, the initial
1912 * device initialization doesn't happen, initialize it when
1913 * a SBTVD parameters are adjusted.
1915 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1916 * the agc callback logic is not called during DVB attach time,
1917 * causing mb86a20s to not be initialized with Kworld SBTVD.
1918 * So, this hack is needed, in order to make Kworld SBTVD to work.
1920 * It is also needed to change the IF after the initial init.
1922 * HACK: Always init the frontend when set_frontend is called:
1923 * it was noticed that, on some devices, it fails to lock on a
1924 * different channel. So, it is better to reset everything, even
1925 * wasting some time, than to loose channel lock.
1927 mb86a20s_initfe(fe);
1929 if (fe->ops.i2c_gate_ctrl)
1930 fe->ops.i2c_gate_ctrl(fe, 0);
1932 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1933 mb86a20s_reset_counters(fe);
1934 mb86a20s_stats_not_ready(fe);
1936 if (fe->ops.i2c_gate_ctrl)
1937 fe->ops.i2c_gate_ctrl(fe, 1);
1942 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1943 enum fe_status *status)
1945 struct mb86a20s_state *state = fe->demodulator_priv;
1948 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1950 if (fe->ops.i2c_gate_ctrl)
1951 fe->ops.i2c_gate_ctrl(fe, 0);
1954 status_nr = mb86a20s_read_status(fe, status);
1955 if (status_nr < 7) {
1956 mb86a20s_stats_not_ready(fe);
1957 mb86a20s_reset_frontend_cache(fe);
1959 if (status_nr < 0) {
1960 dev_err(&state->i2c->dev,
1961 "%s: Can't read frontend lock status\n", __func__);
1966 /* Get signal strength */
1967 rc = mb86a20s_read_signal_strength(fe);
1969 dev_err(&state->i2c->dev,
1970 "%s: Can't reset VBER registers.\n", __func__);
1971 mb86a20s_stats_not_ready(fe);
1972 mb86a20s_reset_frontend_cache(fe);
1974 rc = 0; /* Status is OK */
1978 if (status_nr >= 7) {
1980 rc = mb86a20s_get_frontend(fe);
1982 dev_err(&state->i2c->dev,
1983 "%s: Can't get FE TMCC data.\n", __func__);
1984 rc = 0; /* Status is OK */
1988 /* Get statistics */
1989 rc = mb86a20s_get_stats(fe, status_nr);
1990 if (rc < 0 && rc != -EBUSY) {
1991 dev_err(&state->i2c->dev,
1992 "%s: Can't get FE statistics.\n", __func__);
1996 rc = 0; /* Don't return EBUSY to userspace */
2001 mb86a20s_stats_not_ready(fe);
2004 if (fe->ops.i2c_gate_ctrl)
2005 fe->ops.i2c_gate_ctrl(fe, 1);
2010 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2013 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2016 *strength = c->strength.stat[0].uvalue;
2021 static int mb86a20s_tune(struct dvb_frontend *fe,
2023 unsigned int mode_flags,
2024 unsigned int *delay,
2025 enum fe_status *status)
2027 struct mb86a20s_state *state = fe->demodulator_priv;
2030 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2033 rc = mb86a20s_set_frontend(fe);
2035 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
2036 mb86a20s_read_status_and_stats(fe, status);
2041 static void mb86a20s_release(struct dvb_frontend *fe)
2043 struct mb86a20s_state *state = fe->demodulator_priv;
2045 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2050 static enum dvbfe_algo mb86a20s_get_frontend_algo(struct dvb_frontend *fe)
2052 return DVBFE_ALGO_HW;
2055 static const struct dvb_frontend_ops mb86a20s_ops;
2057 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2058 struct i2c_adapter *i2c)
2060 struct mb86a20s_state *state;
2063 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2065 /* allocate memory for the internal state */
2066 state = kzalloc(sizeof(*state), GFP_KERNEL);
2070 /* setup the state */
2071 state->config = config;
2074 /* create dvb_frontend */
2075 memcpy(&state->frontend.ops, &mb86a20s_ops,
2076 sizeof(struct dvb_frontend_ops));
2077 state->frontend.demodulator_priv = state;
2079 /* Check if it is a mb86a20s frontend */
2080 rev = mb86a20s_readreg(state, 0);
2084 "Frontend revision %d is unknown - aborting.\n",
2089 dev_info(&i2c->dev, "Detected a Fujitsu mb86a20s frontend\n");
2090 return &state->frontend;
2092 EXPORT_SYMBOL(mb86a20s_attach);
2094 static const struct dvb_frontend_ops mb86a20s_ops = {
2095 .delsys = { SYS_ISDBT },
2096 /* Use dib8000 values per default */
2098 .name = "Fujitsu mb86A20s",
2099 .caps = FE_CAN_RECOVER |
2100 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2101 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2102 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2103 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2104 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2105 /* Actually, those values depend on the used tuner */
2106 .frequency_min_hz = 45 * MHz,
2107 .frequency_max_hz = 864 * MHz,
2108 .frequency_stepsize_hz = 62500,
2111 .release = mb86a20s_release,
2113 .init = mb86a20s_initfe,
2114 .set_frontend = mb86a20s_set_frontend,
2115 .read_status = mb86a20s_read_status_and_stats,
2116 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2117 .tune = mb86a20s_tune,
2118 .get_frontend_algo = mb86a20s_get_frontend_algo,
2121 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2122 MODULE_AUTHOR("Mauro Carvalho Chehab");
2123 MODULE_LICENSE("GPL");