drivers/media/dvb-frontends/lgdt3306a.c

   1 /*
   2  *    Support for LGDT3306A - 8VSB/QAM-B
   3  *
   4  *    Copyright (C) 2013 Fred Richter <frichter@hauppauge.com>
   5  *    - driver structure based on lgdt3305.[ch] by Michael Krufky
   6  *    - code based on LG3306_V0.35 API by LG Electronics Inc.
   7  *
   8  *    This program is free software; you can redistribute it and/or modify
   9  *    it under the terms of the GNU General Public License as published by
  10  *    the Free Software Foundation; either version 2 of the License, or
  11  *    (at your option) any later version.
  12  *
  13  *    This program is distributed in the hope that it will be useful,
  14  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *    GNU General Public License for more details.
  17  */
  18
  19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  20
  21 #include <asm/div64.h>
  22 #include <linux/kernel.h>
  23 #include <linux/dvb/frontend.h>
  24 #include <media/dvb_math.h>
  25 #include "lgdt3306a.h"
  26 #include <linux/i2c-mux.h>
  27
  28
  29 static int debug;
  30 module_param(debug, int, 0644);
  31 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
  32
  33 #define DBG_INFO 1
  34 #define DBG_REG  2
  35 #define DBG_DUMP 4 /* FGR - comment out to remove dump code */
  36
  37 #define lg_debug(fmt, arg...) \
  38         printk(KERN_DEBUG pr_fmt(fmt), ## arg)
  39
  40 #define dbg_info(fmt, arg...)                                   \
  41         do {                                                    \
  42                 if (debug & DBG_INFO)                           \
  43                         lg_debug(fmt, ## arg);                  \
  44         } while (0)
  45
  46 #define dbg_reg(fmt, arg...)                                    \
  47         do {                                                    \
  48                 if (debug & DBG_REG)                            \
  49                         lg_debug(fmt, ## arg);                  \
  50         } while (0)
  51
  52 #define lg_chkerr(ret)                                                  \
  53 ({                                                                      \
  54         int __ret;                                                      \
  55         __ret = (ret < 0);                                              \
  56         if (__ret)                                                      \
  57                 pr_err("error %d on line %d\n", ret, __LINE__);         \
  58         __ret;                                                          \
  59 })
  60
  61 struct lgdt3306a_state {
  62         struct i2c_adapter *i2c_adap;
  63         const struct lgdt3306a_config *cfg;
  64
  65         struct dvb_frontend frontend;
  66
  67         enum fe_modulation current_modulation;
  68         u32 current_frequency;
  69         u32 snr;
  70
  71         struct i2c_mux_core *muxc;
  72 };
  73
  74 /*
  75  * LG3306A Register Usage
  76  *  (LG does not really name the registers, so this code does not either)
  77  *
  78  * 0000 -> 00FF Common control and status
  79  * 1000 -> 10FF Synchronizer control and status
  80  * 1F00 -> 1FFF Smart Antenna control and status
  81  * 2100 -> 21FF VSB Equalizer control and status
  82  * 2800 -> 28FF QAM Equalizer control and status
  83  * 3000 -> 30FF FEC control and status
  84  */
  85
  86 enum lgdt3306a_lock_status {
  87         LG3306_UNLOCK       = 0x00,
  88         LG3306_LOCK         = 0x01,
  89         LG3306_UNKNOWN_LOCK = 0xff
  90 };
  91
  92 enum lgdt3306a_neverlock_status {
  93         LG3306_NL_INIT    = 0x00,
  94         LG3306_NL_PROCESS = 0x01,
  95         LG3306_NL_LOCK    = 0x02,
  96         LG3306_NL_FAIL    = 0x03,
  97         LG3306_NL_UNKNOWN = 0xff
  98 };
  99
 100 enum lgdt3306a_modulation {
 101         LG3306_VSB          = 0x00,
 102         LG3306_QAM64        = 0x01,
 103         LG3306_QAM256       = 0x02,
 104         LG3306_UNKNOWN_MODE = 0xff
 105 };
 106
 107 enum lgdt3306a_lock_check {
 108         LG3306_SYNC_LOCK,
 109         LG3306_FEC_LOCK,
 110         LG3306_TR_LOCK,
 111         LG3306_AGC_LOCK,
 112 };
 113
 114
 115 #ifdef DBG_DUMP
 116 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state);
 117 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state);
 118 #endif
 119
 120
 121 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val)
 122 {
 123         int ret;
 124         u8 buf[] = { reg >> 8, reg & 0xff, val };
 125         struct i2c_msg msg = {
 126                 .addr = state->cfg->i2c_addr, .flags = 0,
 127                 .buf = buf, .len = 3,
 128         };
 129
 130         dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
 131
 132         ret = i2c_transfer(state->i2c_adap, &msg, 1);
 133
 134         if (ret != 1) {
 135                 pr_err("error (addr %02x %02x <- %02x, err = %i)\n",
 136                        msg.buf[0], msg.buf[1], msg.buf[2], ret);
 137                 if (ret < 0)
 138                         return ret;
 139                 else
 140                         return -EREMOTEIO;
 141         }
 142         return 0;
 143 }
 144
 145 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val)
 146 {
 147         int ret;
 148         u8 reg_buf[] = { reg >> 8, reg & 0xff };
 149         struct i2c_msg msg[] = {
 150                 { .addr = state->cfg->i2c_addr,
 151                   .flags = 0, .buf = reg_buf, .len = 2 },
 152                 { .addr = state->cfg->i2c_addr,
 153                   .flags = I2C_M_RD, .buf = val, .len = 1 },
 154         };
 155
 156         ret = i2c_transfer(state->i2c_adap, msg, 2);
 157
 158         if (ret != 2) {
 159                 pr_err("error (addr %02x reg %04x error (ret == %i)\n",
 160                        state->cfg->i2c_addr, reg, ret);
 161                 if (ret < 0)
 162                         return ret;
 163                 else
 164                         return -EREMOTEIO;
 165         }
 166         dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val);
 167
 168         return 0;
 169 }
 170
 171 #define read_reg(state, reg)                                            \
 172 ({                                                                      \
 173         u8 __val;                                                       \
 174         int ret = lgdt3306a_read_reg(state, reg, &__val);               \
 175         if (lg_chkerr(ret))                                             \
 176                 __val = 0;                                              \
 177         __val;                                                          \
 178 })
 179
 180 static int lgdt3306a_set_reg_bit(struct lgdt3306a_state *state,
 181                                 u16 reg, int bit, int onoff)
 182 {
 183         u8 val;
 184         int ret;
 185
 186         dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
 187
 188         ret = lgdt3306a_read_reg(state, reg, &val);
 189         if (lg_chkerr(ret))
 190                 goto fail;
 191
 192         val &= ~(1 << bit);
 193         val |= (onoff & 1) << bit;
 194
 195         ret = lgdt3306a_write_reg(state, reg, val);
 196         lg_chkerr(ret);
 197 fail:
 198         return ret;
 199 }
 200
 201 /* ------------------------------------------------------------------------ */
 202
 203 static int lgdt3306a_soft_reset(struct lgdt3306a_state *state)
 204 {
 205         int ret;
 206
 207         dbg_info("\n");
 208
 209         ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
 210         if (lg_chkerr(ret))
 211                 goto fail;
 212
 213         msleep(20);
 214         ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
 215         lg_chkerr(ret);
 216
 217 fail:
 218         return ret;
 219 }
 220
 221 static int lgdt3306a_mpeg_mode(struct lgdt3306a_state *state,
 222                                      enum lgdt3306a_mpeg_mode mode)
 223 {
 224         u8 val;
 225         int ret;
 226
 227         dbg_info("(%d)\n", mode);
 228         /* transport packet format - TPSENB=0x80 */
 229         ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
 230                                      mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
 231         if (lg_chkerr(ret))
 232                 goto fail;
 233
 234         /*
 235          * start of packet signal duration
 236          * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
 237          */
 238         ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
 239         if (lg_chkerr(ret))
 240                 goto fail;
 241
 242         ret = lgdt3306a_read_reg(state, 0x0070, &val);
 243         if (lg_chkerr(ret))
 244                 goto fail;
 245
 246         val |= 0x10; /* TPCLKSUPB=0x10 */
 247
 248         if (mode == LGDT3306A_MPEG_PARALLEL)
 249                 val &= ~0x10;
 250
 251         ret = lgdt3306a_write_reg(state, 0x0070, val);
 252         lg_chkerr(ret);
 253
 254 fail:
 255         return ret;
 256 }
 257
 258 static int lgdt3306a_mpeg_mode_polarity(struct lgdt3306a_state *state,
 259                                        enum lgdt3306a_tp_clock_edge edge,
 260                                        enum lgdt3306a_tp_valid_polarity valid)
 261 {
 262         u8 val;
 263         int ret;
 264
 265         dbg_info("edge=%d, valid=%d\n", edge, valid);
 266
 267         ret = lgdt3306a_read_reg(state, 0x0070, &val);
 268         if (lg_chkerr(ret))
 269                 goto fail;
 270
 271         val &= ~0x06; /* TPCLKPOL=0x04, TPVALPOL=0x02 */
 272
 273         if (edge == LGDT3306A_TPCLK_RISING_EDGE)
 274                 val |= 0x04;
 275         if (valid == LGDT3306A_TP_VALID_HIGH)
 276                 val |= 0x02;
 277
 278         ret = lgdt3306a_write_reg(state, 0x0070, val);
 279         lg_chkerr(ret);
 280
 281 fail:
 282         return ret;
 283 }
 284
 285 static int lgdt3306a_mpeg_tristate(struct lgdt3306a_state *state,
 286                                      int mode)
 287 {
 288         u8 val;
 289         int ret;
 290
 291         dbg_info("(%d)\n", mode);
 292
 293         if (mode) {
 294                 ret = lgdt3306a_read_reg(state, 0x0070, &val);
 295                 if (lg_chkerr(ret))
 296                         goto fail;
 297                 /*
 298                  * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
 299                  * TPDATAOUTEN=0x08
 300                  */
 301                 val &= ~0xa8;
 302                 ret = lgdt3306a_write_reg(state, 0x0070, val);
 303                 if (lg_chkerr(ret))
 304                         goto fail;
 305
 306                 /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
 307                 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
 308                 if (lg_chkerr(ret))
 309                         goto fail;
 310
 311         } else {
 312                 /* enable IFAGC pin */
 313                 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
 314                 if (lg_chkerr(ret))
 315                         goto fail;
 316
 317                 ret = lgdt3306a_read_reg(state, 0x0070, &val);
 318                 if (lg_chkerr(ret))
 319                         goto fail;
 320
 321                 val |= 0xa8; /* enable bus */
 322                 ret = lgdt3306a_write_reg(state, 0x0070, val);
 323                 if (lg_chkerr(ret))
 324                         goto fail;
 325         }
 326
 327 fail:
 328         return ret;
 329 }
 330
 331 static int lgdt3306a_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
 332 {
 333         struct lgdt3306a_state *state = fe->demodulator_priv;
 334
 335         dbg_info("acquire=%d\n", acquire);
 336
 337         return lgdt3306a_mpeg_tristate(state, acquire ? 0 : 1);
 338
 339 }
 340
 341 static int lgdt3306a_power(struct lgdt3306a_state *state,
 342                                      int mode)
 343 {
 344         int ret;
 345
 346         dbg_info("(%d)\n", mode);
 347
 348         if (mode == 0) {
 349                 /* into reset */
 350                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
 351                 if (lg_chkerr(ret))
 352                         goto fail;
 353
 354                 /* power down */
 355                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
 356                 if (lg_chkerr(ret))
 357                         goto fail;
 358
 359         } else {
 360                 /* out of reset */
 361                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
 362                 if (lg_chkerr(ret))
 363                         goto fail;
 364
 365                 /* power up */
 366                 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
 367                 if (lg_chkerr(ret))
 368                         goto fail;
 369         }
 370
 371 #ifdef DBG_DUMP
 372         lgdt3306a_DumpAllRegs(state);
 373 #endif
 374 fail:
 375         return ret;
 376 }
 377
 378
 379 static int lgdt3306a_set_vsb(struct lgdt3306a_state *state)
 380 {
 381         u8 val;
 382         int ret;
 383
 384         dbg_info("\n");
 385
 386         /* 0. Spectrum inversion detection manual; spectrum inverted */
 387         ret = lgdt3306a_read_reg(state, 0x0002, &val);
 388         val &= 0xf7; /* SPECINVAUTO Off */
 389         val |= 0x04; /* SPECINV On */
 390         ret = lgdt3306a_write_reg(state, 0x0002, val);
 391         if (lg_chkerr(ret))
 392                 goto fail;
 393
 394         /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
 395         ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
 396         if (lg_chkerr(ret))
 397                 goto fail;
 398
 399         /* 2. Bandwidth mode for VSB(6MHz) */
 400         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 401         val &= 0xe3;
 402         val |= 0x0c; /* STDOPDETTMODE[2:0]=3 */
 403         ret = lgdt3306a_write_reg(state, 0x0009, val);
 404         if (lg_chkerr(ret))
 405                 goto fail;
 406
 407         /* 3. QAM mode detection mode(None) */
 408         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 409         val &= 0xfc; /* STDOPDETCMODE[1:0]=0 */
 410         ret = lgdt3306a_write_reg(state, 0x0009, val);
 411         if (lg_chkerr(ret))
 412                 goto fail;
 413
 414         /* 4. ADC sampling frequency rate(2x sampling) */
 415         ret = lgdt3306a_read_reg(state, 0x000d, &val);
 416         val &= 0xbf; /* SAMPLING4XFEN=0 */
 417         ret = lgdt3306a_write_reg(state, 0x000d, val);
 418         if (lg_chkerr(ret))
 419                 goto fail;
 420
 421 #if 0
 422         /* FGR - disable any AICC filtering, testing only */
 423
 424         ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
 425         if (lg_chkerr(ret))
 426                 goto fail;
 427
 428         /* AICCFIXFREQ0 NT N-1(Video rejection) */
 429         ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
 430         ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
 431         ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
 432
 433         /* AICCFIXFREQ1 NT N-1(Audio rejection) */
 434         ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
 435         ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
 436         ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
 437
 438         /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
 439         ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
 440         ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
 441         ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
 442
 443         /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
 444         ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
 445         ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
 446         ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
 447
 448 #else
 449         /* FGR - this works well for HVR-1955,1975 */
 450
 451         /* 5. AICCOPMODE  NT N-1 Adj. */
 452         ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
 453         if (lg_chkerr(ret))
 454                 goto fail;
 455
 456         /* AICCFIXFREQ0 NT N-1(Video rejection) */
 457         ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
 458         ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
 459         ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
 460
 461         /* AICCFIXFREQ1 NT N-1(Audio rejection) */
 462         ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
 463         ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
 464         ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
 465
 466         /* AICCFIXFREQ2 NT Co-Channel(Video rejection) */
 467         ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
 468         ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
 469         ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
 470
 471         /* AICCFIXFREQ3 NT Co-Channel(Audio rejection) */
 472         ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
 473         ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
 474         ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
 475 #endif
 476
 477         ret = lgdt3306a_read_reg(state, 0x001e, &val);
 478         val &= 0x0f;
 479         val |= 0xa0;
 480         ret = lgdt3306a_write_reg(state, 0x001e, val);
 481
 482         ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
 483
 484         ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
 485
 486         ret = lgdt3306a_read_reg(state, 0x211f, &val);
 487         val &= 0xef;
 488         ret = lgdt3306a_write_reg(state, 0x211f, val);
 489
 490         ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
 491
 492         ret = lgdt3306a_read_reg(state, 0x1061, &val);
 493         val &= 0xf8;
 494         val |= 0x04;
 495         ret = lgdt3306a_write_reg(state, 0x1061, val);
 496
 497         ret = lgdt3306a_read_reg(state, 0x103d, &val);
 498         val &= 0xcf;
 499         ret = lgdt3306a_write_reg(state, 0x103d, val);
 500
 501         ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
 502
 503         ret = lgdt3306a_read_reg(state, 0x2141, &val);
 504         val &= 0x3f;
 505         ret = lgdt3306a_write_reg(state, 0x2141, val);
 506
 507         ret = lgdt3306a_read_reg(state, 0x2135, &val);
 508         val &= 0x0f;
 509         val |= 0x70;
 510         ret = lgdt3306a_write_reg(state, 0x2135, val);
 511
 512         ret = lgdt3306a_read_reg(state, 0x0003, &val);
 513         val &= 0xf7;
 514         ret = lgdt3306a_write_reg(state, 0x0003, val);
 515
 516         ret = lgdt3306a_read_reg(state, 0x001c, &val);
 517         val &= 0x7f;
 518         ret = lgdt3306a_write_reg(state, 0x001c, val);
 519
 520         /* 6. EQ step size */
 521         ret = lgdt3306a_read_reg(state, 0x2179, &val);
 522         val &= 0xf8;
 523         ret = lgdt3306a_write_reg(state, 0x2179, val);
 524
 525         ret = lgdt3306a_read_reg(state, 0x217a, &val);
 526         val &= 0xf8;
 527         ret = lgdt3306a_write_reg(state, 0x217a, val);
 528
 529         /* 7. Reset */
 530         ret = lgdt3306a_soft_reset(state);
 531         if (lg_chkerr(ret))
 532                 goto fail;
 533
 534         dbg_info("complete\n");
 535 fail:
 536         return ret;
 537 }
 538
 539 static int lgdt3306a_set_qam(struct lgdt3306a_state *state, int modulation)
 540 {
 541         u8 val;
 542         int ret;
 543
 544         dbg_info("modulation=%d\n", modulation);
 545
 546         /* 1. Selection of standard mode(0x08=QAM, 0x80=VSB) */
 547         ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
 548         if (lg_chkerr(ret))
 549                 goto fail;
 550
 551         /* 1a. Spectrum inversion detection to Auto */
 552         ret = lgdt3306a_read_reg(state, 0x0002, &val);
 553         val &= 0xfb; /* SPECINV Off */
 554         val |= 0x08; /* SPECINVAUTO On */
 555         ret = lgdt3306a_write_reg(state, 0x0002, val);
 556         if (lg_chkerr(ret))
 557                 goto fail;
 558
 559         /* 2. Bandwidth mode for QAM */
 560         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 561         val &= 0xe3; /* STDOPDETTMODE[2:0]=0 VSB Off */
 562         ret = lgdt3306a_write_reg(state, 0x0009, val);
 563         if (lg_chkerr(ret))
 564                 goto fail;
 565
 566         /* 3. : 64QAM/256QAM detection(manual, auto) */
 567         ret = lgdt3306a_read_reg(state, 0x0009, &val);
 568         val &= 0xfc;
 569         val |= 0x02; /* STDOPDETCMODE[1:0]=1=Manual 2=Auto */
 570         ret = lgdt3306a_write_reg(state, 0x0009, val);
 571         if (lg_chkerr(ret))
 572                 goto fail;
 573
 574         /* 3a. : 64QAM/256QAM selection for manual */
 575         ret = lgdt3306a_read_reg(state, 0x101a, &val);
 576         val &= 0xf8;
 577         if (modulation == QAM_64)
 578                 val |= 0x02; /* QMDQMODE[2:0]=2=QAM64 */
 579         else
 580                 val |= 0x04; /* QMDQMODE[2:0]=4=QAM256 */
 581
 582         ret = lgdt3306a_write_reg(state, 0x101a, val);
 583         if (lg_chkerr(ret))
 584                 goto fail;
 585
 586         /* 4. ADC sampling frequency rate(4x sampling) */
 587         ret = lgdt3306a_read_reg(state, 0x000d, &val);
 588         val &= 0xbf;
 589         val |= 0x40; /* SAMPLING4XFEN=1 */
 590         ret = lgdt3306a_write_reg(state, 0x000d, val);
 591         if (lg_chkerr(ret))
 592                 goto fail;
 593
 594         /* 5. No AICC operation in QAM mode */
 595         ret = lgdt3306a_read_reg(state, 0x0024, &val);
 596         val &= 0x00;
 597         ret = lgdt3306a_write_reg(state, 0x0024, val);
 598         if (lg_chkerr(ret))
 599                 goto fail;
 600
 601         /* 6. Reset */
 602         ret = lgdt3306a_soft_reset(state);
 603         if (lg_chkerr(ret))
 604                 goto fail;
 605
 606         dbg_info("complete\n");
 607 fail:
 608         return ret;
 609 }
 610
 611 static int lgdt3306a_set_modulation(struct lgdt3306a_state *state,
 612                                    struct dtv_frontend_properties *p)
 613 {
 614         int ret;
 615
 616         dbg_info("\n");
 617
 618         switch (p->modulation) {
 619         case VSB_8:
 620                 ret = lgdt3306a_set_vsb(state);
 621                 break;
 622         case QAM_64:
 623                 ret = lgdt3306a_set_qam(state, QAM_64);
 624                 break;
 625         case QAM_256:
 626                 ret = lgdt3306a_set_qam(state, QAM_256);
 627                 break;
 628         default:
 629                 return -EINVAL;
 630         }
 631         if (lg_chkerr(ret))
 632                 goto fail;
 633
 634         state->current_modulation = p->modulation;
 635
 636 fail:
 637         return ret;
 638 }
 639
 640 /* ------------------------------------------------------------------------ */
 641
 642 static int lgdt3306a_agc_setup(struct lgdt3306a_state *state,
 643                               struct dtv_frontend_properties *p)
 644 {
 645         /* TODO: anything we want to do here??? */
 646         dbg_info("\n");
 647
 648         switch (p->modulation) {
 649         case VSB_8:
 650                 break;
 651         case QAM_64:
 652         case QAM_256:
 653                 break;
 654         default:
 655                 return -EINVAL;
 656         }
 657         return 0;
 658 }
 659
 660 /* ------------------------------------------------------------------------ */
 661
 662 static int lgdt3306a_set_inversion(struct lgdt3306a_state *state,
 663                                        int inversion)
 664 {
 665         int ret;
 666
 667         dbg_info("(%d)\n", inversion);
 668
 669         ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
 670         return ret;
 671 }
 672
 673 static int lgdt3306a_set_inversion_auto(struct lgdt3306a_state *state,
 674                                        int enabled)
 675 {
 676         int ret;
 677
 678         dbg_info("(%d)\n", enabled);
 679
 680         /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
 681         ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
 682         return ret;
 683 }
 684
 685 static int lgdt3306a_spectral_inversion(struct lgdt3306a_state *state,
 686                                        struct dtv_frontend_properties *p,
 687                                        int inversion)
 688 {
 689         int ret = 0;
 690
 691         dbg_info("(%d)\n", inversion);
 692 #if 0
 693         /*
 694          * FGR - spectral_inversion defaults already set for VSB and QAM;
 695          * can enable later if desired
 696          */
 697
 698         ret = lgdt3306a_set_inversion(state, inversion);
 699
 700         switch (p->modulation) {
 701         case VSB_8:
 702                 /* Manual only for VSB */
 703                 ret = lgdt3306a_set_inversion_auto(state, 0);
 704                 break;
 705         case QAM_64:
 706         case QAM_256:
 707                 /* Auto ok for QAM */
 708                 ret = lgdt3306a_set_inversion_auto(state, 1);
 709                 break;
 710         default:
 711                 ret = -EINVAL;
 712         }
 713 #endif
 714         return ret;
 715 }
 716
 717 static int lgdt3306a_set_if(struct lgdt3306a_state *state,
 718                            struct dtv_frontend_properties *p)
 719 {
 720         int ret;
 721         u16 if_freq_khz;
 722         u8 nco1, nco2;
 723
 724         switch (p->modulation) {
 725         case VSB_8:
 726                 if_freq_khz = state->cfg->vsb_if_khz;
 727                 break;
 728         case QAM_64:
 729         case QAM_256:
 730                 if_freq_khz = state->cfg->qam_if_khz;
 731                 break;
 732         default:
 733                 return -EINVAL;
 734         }
 735
 736         switch (if_freq_khz) {
 737         default:
 738                 pr_warn("IF=%d KHz is not supported, 3250 assumed\n",
 739                         if_freq_khz);
 740                 /* fallthrough */
 741         case 3250: /* 3.25Mhz */
 742                 nco1 = 0x34;
 743                 nco2 = 0x00;
 744                 break;
 745         case 3500: /* 3.50Mhz */
 746                 nco1 = 0x38;
 747                 nco2 = 0x00;
 748                 break;
 749         case 4000: /* 4.00Mhz */
 750                 nco1 = 0x40;
 751                 nco2 = 0x00;
 752                 break;
 753         case 5000: /* 5.00Mhz */
 754                 nco1 = 0x50;
 755                 nco2 = 0x00;
 756                 break;
 757         case 5380: /* 5.38Mhz */
 758                 nco1 = 0x56;
 759                 nco2 = 0x14;
 760                 break;
 761         }
 762         ret = lgdt3306a_write_reg(state, 0x0010, nco1);
 763         if (ret)
 764                 return ret;
 765         ret = lgdt3306a_write_reg(state, 0x0011, nco2);
 766         if (ret)
 767                 return ret;
 768
 769         dbg_info("if_freq=%d KHz->[%04x]\n", if_freq_khz, nco1<<8 | nco2);
 770
 771         return 0;
 772 }
 773
 774 /* ------------------------------------------------------------------------ */
 775
 776 static int lgdt3306a_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 777 {
 778         struct lgdt3306a_state *state = fe->demodulator_priv;
 779
 780         if (state->cfg->deny_i2c_rptr) {
 781                 dbg_info("deny_i2c_rptr=%d\n", state->cfg->deny_i2c_rptr);
 782                 return 0;
 783         }
 784         dbg_info("(%d)\n", enable);
 785
 786         /* NI2CRPTEN=0x80 */
 787         return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
 788 }
 789
 790 static int lgdt3306a_sleep(struct lgdt3306a_state *state)
 791 {
 792         int ret;
 793
 794         dbg_info("\n");
 795         state->current_frequency = -1; /* force re-tune, when we wake */
 796
 797         ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
 798         if (lg_chkerr(ret))
 799                 goto fail;
 800
 801         ret = lgdt3306a_power(state, 0); /* power down */
 802         lg_chkerr(ret);
 803
 804 fail:
 805         return 0;
 806 }
 807
 808 static int lgdt3306a_fe_sleep(struct dvb_frontend *fe)
 809 {
 810         struct lgdt3306a_state *state = fe->demodulator_priv;
 811
 812         return lgdt3306a_sleep(state);
 813 }
 814
 815 static int lgdt3306a_init(struct dvb_frontend *fe)
 816 {
 817         struct lgdt3306a_state *state = fe->demodulator_priv;
 818         u8 val;
 819         int ret;
 820
 821         dbg_info("\n");
 822
 823         /* 1. Normal operation mode */
 824         ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
 825         if (lg_chkerr(ret))
 826                 goto fail;
 827
 828         /* 2. Spectrum inversion auto detection (Not valid for VSB) */
 829         ret = lgdt3306a_set_inversion_auto(state, 0);
 830         if (lg_chkerr(ret))
 831                 goto fail;
 832
 833         /* 3. Spectrum inversion(According to the tuner configuration) */
 834         ret = lgdt3306a_set_inversion(state, 1);
 835         if (lg_chkerr(ret))
 836                 goto fail;
 837
 838         /* 4. Peak-to-peak voltage of ADC input signal */
 839
 840         /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
 841         ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
 842         if (lg_chkerr(ret))
 843                 goto fail;
 844
 845         /* 5. ADC output data capture clock phase */
 846
 847         /* 0=same phase as ADC clock */
 848         ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
 849         if (lg_chkerr(ret))
 850                 goto fail;
 851
 852         /* 5a. ADC sampling clock source */
 853
 854         /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
 855         ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
 856         if (lg_chkerr(ret))
 857                 goto fail;
 858
 859         /* 6. Automatic PLL set */
 860
 861         /* PLLSETAUTO=0x40; 0=off */
 862         ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
 863         if (lg_chkerr(ret))
 864                 goto fail;
 865
 866         if (state->cfg->xtalMHz == 24) {        /* 24MHz */
 867                 /* 7. Frequency for PLL output(0x2564 for 192MHz for 24MHz) */
 868                 ret = lgdt3306a_read_reg(state, 0x0005, &val);
 869                 if (lg_chkerr(ret))
 870                         goto fail;
 871                 val &= 0xc0;
 872                 val |= 0x25;
 873                 ret = lgdt3306a_write_reg(state, 0x0005, val);
 874                 if (lg_chkerr(ret))
 875                         goto fail;
 876                 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
 877                 if (lg_chkerr(ret))
 878                         goto fail;
 879
 880                 /* 8. ADC sampling frequency(0x180000 for 24MHz sampling) */
 881                 ret = lgdt3306a_read_reg(state, 0x000d, &val);
 882                 if (lg_chkerr(ret))
 883                         goto fail;
 884                 val &= 0xc0;
 885                 val |= 0x18;
 886                 ret = lgdt3306a_write_reg(state, 0x000d, val);
 887                 if (lg_chkerr(ret))
 888                         goto fail;
 889
 890         } else if (state->cfg->xtalMHz == 25) { /* 25MHz */
 891                 /* 7. Frequency for PLL output */
 892                 ret = lgdt3306a_read_reg(state, 0x0005, &val);
 893                 if (lg_chkerr(ret))
 894                         goto fail;
 895                 val &= 0xc0;
 896                 val |= 0x25;
 897                 ret = lgdt3306a_write_reg(state, 0x0005, val);
 898                 if (lg_chkerr(ret))
 899                         goto fail;
 900                 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
 901                 if (lg_chkerr(ret))
 902                         goto fail;
 903
 904                 /* 8. ADC sampling frequency(0x190000 for 25MHz sampling) */
 905                 ret = lgdt3306a_read_reg(state, 0x000d, &val);
 906                 if (lg_chkerr(ret))
 907                         goto fail;
 908                 val &= 0xc0;
 909                 val |= 0x19;
 910                 ret = lgdt3306a_write_reg(state, 0x000d, val);
 911                 if (lg_chkerr(ret))
 912                         goto fail;
 913         } else {
 914                 pr_err("Bad xtalMHz=%d\n", state->cfg->xtalMHz);
 915         }
 916 #if 0
 917         ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
 918         ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
 919 #endif
 920
 921         /* 9. Center frequency of input signal of ADC */
 922         ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
 923         ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
 924
 925         /* 10. Fixed gain error value */
 926         ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
 927
 928         /* 10a. VSB TR BW gear shift initial step */
 929         ret = lgdt3306a_read_reg(state, 0x103c, &val);
 930         val &= 0x0f;
 931         val |= 0x20; /* SAMGSAUTOSTL_V[3:0] = 2 */
 932         ret = lgdt3306a_write_reg(state, 0x103c, val);
 933
 934         /* 10b. Timing offset calibration in low temperature for VSB */
 935         ret = lgdt3306a_read_reg(state, 0x103d, &val);
 936         val &= 0xfc;
 937         val |= 0x03;
 938         ret = lgdt3306a_write_reg(state, 0x103d, val);
 939
 940         /* 10c. Timing offset calibration in low temperature for QAM */
 941         ret = lgdt3306a_read_reg(state, 0x1036, &val);
 942         val &= 0xf0;
 943         val |= 0x0c;
 944         ret = lgdt3306a_write_reg(state, 0x1036, val);
 945
 946         /* 11. Using the imaginary part of CIR in CIR loading */
 947         ret = lgdt3306a_read_reg(state, 0x211f, &val);
 948         val &= 0xef; /* do not use imaginary of CIR */
 949         ret = lgdt3306a_write_reg(state, 0x211f, val);
 950
 951         /* 12. Control of no signal detector function */
 952         ret = lgdt3306a_read_reg(state, 0x2849, &val);
 953         val &= 0xef; /* NOUSENOSIGDET=0, enable no signal detector */
 954         ret = lgdt3306a_write_reg(state, 0x2849, val);
 955
 956         /* FGR - put demod in some known mode */
 957         ret = lgdt3306a_set_vsb(state);
 958
 959         /* 13. TP stream format */
 960         ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
 961
 962         /* 14. disable output buses */
 963         ret = lgdt3306a_mpeg_tristate(state, 1);
 964
 965         /* 15. Sleep (in reset) */
 966         ret = lgdt3306a_sleep(state);
 967         lg_chkerr(ret);
 968
 969 fail:
 970         return ret;
 971 }
 972
 973 static int lgdt3306a_set_parameters(struct dvb_frontend *fe)
 974 {
 975         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
 976         struct lgdt3306a_state *state = fe->demodulator_priv;
 977         int ret;
 978
 979         dbg_info("(%d, %d)\n", p->frequency, p->modulation);
 980
 981         if (state->current_frequency  == p->frequency &&
 982            state->current_modulation == p->modulation) {
 983                 dbg_info(" (already set, skipping ...)\n");
 984                 return 0;
 985         }
 986         state->current_frequency = -1;
 987         state->current_modulation = -1;
 988
 989         ret = lgdt3306a_power(state, 1); /* power up */
 990         if (lg_chkerr(ret))
 991                 goto fail;
 992
 993         if (fe->ops.tuner_ops.set_params) {
 994                 ret = fe->ops.tuner_ops.set_params(fe);
 995                 if (fe->ops.i2c_gate_ctrl)
 996                         fe->ops.i2c_gate_ctrl(fe, 0);
 997 #if 0
 998                 if (lg_chkerr(ret))
 999                         goto fail;
1000                 state->current_frequency = p->frequency;
1001 #endif
1002         }
1003
1004         ret = lgdt3306a_set_modulation(state, p);
1005         if (lg_chkerr(ret))
1006                 goto fail;
1007
1008         ret = lgdt3306a_agc_setup(state, p);
1009         if (lg_chkerr(ret))
1010                 goto fail;
1011
1012         ret = lgdt3306a_set_if(state, p);
1013         if (lg_chkerr(ret))
1014                 goto fail;
1015
1016         ret = lgdt3306a_spectral_inversion(state, p,
1017                                         state->cfg->spectral_inversion ? 1 : 0);
1018         if (lg_chkerr(ret))
1019                 goto fail;
1020
1021         ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1022         if (lg_chkerr(ret))
1023                 goto fail;
1024
1025         ret = lgdt3306a_mpeg_mode_polarity(state,
1026                                           state->cfg->tpclk_edge,
1027                                           state->cfg->tpvalid_polarity);
1028         if (lg_chkerr(ret))
1029                 goto fail;
1030
1031         ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
1032         if (lg_chkerr(ret))
1033                 goto fail;
1034
1035         ret = lgdt3306a_soft_reset(state);
1036         if (lg_chkerr(ret))
1037                 goto fail;
1038
1039 #ifdef DBG_DUMP
1040         lgdt3306a_DumpAllRegs(state);
1041 #endif
1042         state->current_frequency = p->frequency;
1043 fail:
1044         return ret;
1045 }
1046
1047 static int lgdt3306a_get_frontend(struct dvb_frontend *fe,
1048                                   struct dtv_frontend_properties *p)
1049 {
1050         struct lgdt3306a_state *state = fe->demodulator_priv;
1051
1052         dbg_info("(%u, %d)\n",
1053                  state->current_frequency, state->current_modulation);
1054
1055         p->modulation = state->current_modulation;
1056         p->frequency = state->current_frequency;
1057         return 0;
1058 }
1059
1060 static enum dvbfe_algo lgdt3306a_get_frontend_algo(struct dvb_frontend *fe)
1061 {
1062 #if 1
1063         return DVBFE_ALGO_CUSTOM;
1064 #else
1065         return DVBFE_ALGO_HW;
1066 #endif
1067 }
1068
1069 /* ------------------------------------------------------------------------ */
1070 static int lgdt3306a_monitor_vsb(struct lgdt3306a_state *state)
1071 {
1072         u8 val;
1073         int ret;
1074         u8 snrRef, maxPowerMan, nCombDet;
1075         u16 fbDlyCir;
1076
1077         ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1078         if (ret)
1079                 return ret;
1080         snrRef = val & 0x3f;
1081
1082         ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
1083         if (ret)
1084                 return ret;
1085
1086         ret = lgdt3306a_read_reg(state, 0x2191, &val);
1087         if (ret)
1088                 return ret;
1089         nCombDet = (val & 0x80) >> 7;
1090
1091         ret = lgdt3306a_read_reg(state, 0x2180, &val);
1092         if (ret)
1093                 return ret;
1094         fbDlyCir = (val & 0x03) << 8;
1095
1096         ret = lgdt3306a_read_reg(state, 0x2181, &val);
1097         if (ret)
1098                 return ret;
1099         fbDlyCir |= val;
1100
1101         dbg_info("snrRef=%d maxPowerMan=0x%x nCombDet=%d fbDlyCir=0x%x\n",
1102                 snrRef, maxPowerMan, nCombDet, fbDlyCir);
1103
1104         /* Carrier offset sub loop bandwidth */
1105         ret = lgdt3306a_read_reg(state, 0x1061, &val);
1106         if (ret)
1107                 return ret;
1108         val &= 0xf8;
1109         if ((snrRef > 18) && (maxPowerMan > 0x68)
1110             && (nCombDet == 0x01)
1111             && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
1112                 /* SNR is over 18dB and no ghosting */
1113                 val |= 0x00; /* final bandwidth = 0 */
1114         } else {
1115                 val |= 0x04; /* final bandwidth = 4 */
1116         }
1117         ret = lgdt3306a_write_reg(state, 0x1061, val);
1118         if (ret)
1119                 return ret;
1120
1121         /* Adjust Notch Filter */
1122         ret = lgdt3306a_read_reg(state, 0x0024, &val);
1123         if (ret)
1124                 return ret;
1125         val &= 0x0f;
1126         if (nCombDet == 0) { /* Turn on the Notch Filter */
1127                 val |= 0x50;
1128         }
1129         ret = lgdt3306a_write_reg(state, 0x0024, val);
1130         if (ret)
1131                 return ret;
1132
1133         /* VSB Timing Recovery output normalization */
1134         ret = lgdt3306a_read_reg(state, 0x103d, &val);
1135         if (ret)
1136                 return ret;
1137         val &= 0xcf;
1138         val |= 0x20;
1139         ret = lgdt3306a_write_reg(state, 0x103d, val);
1140
1141         return ret;
1142 }
1143
1144 static enum lgdt3306a_modulation
1145 lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
1146 {
1147         u8 val = 0;
1148         int ret;
1149
1150         ret = lgdt3306a_read_reg(state, 0x0081, &val);
1151         if (ret)
1152                 goto err;
1153
1154         if (val & 0x80) {
1155                 dbg_info("VSB\n");
1156                 return LG3306_VSB;
1157         }
1158         if (val & 0x08) {
1159                 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1160                 if (ret)
1161                         goto err;
1162                 val = val >> 2;
1163                 if (val & 0x01) {
1164                         dbg_info("QAM256\n");
1165                         return LG3306_QAM256;
1166                 }
1167                 dbg_info("QAM64\n");
1168                 return LG3306_QAM64;
1169         }
1170 err:
1171         pr_warn("UNKNOWN\n");
1172         return LG3306_UNKNOWN_MODE;
1173 }
1174
1175 static enum lgdt3306a_lock_status
1176 lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
1177                             enum lgdt3306a_lock_check whatLock)
1178 {
1179         u8 val = 0;
1180         int ret;
1181         enum lgdt3306a_modulation       modeOper;
1182         enum lgdt3306a_lock_status lockStatus;
1183
1184         modeOper = LG3306_UNKNOWN_MODE;
1185
1186         switch (whatLock) {
1187         case LG3306_SYNC_LOCK:
1188         {
1189                 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1190                 if (ret)
1191                         return ret;
1192
1193                 if ((val & 0x80) == 0x80)
1194                         lockStatus = LG3306_LOCK;
1195                 else
1196                         lockStatus = LG3306_UNLOCK;
1197
1198                 dbg_info("SYNC_LOCK=%x\n", lockStatus);
1199                 break;
1200         }
1201         case LG3306_AGC_LOCK:
1202         {
1203                 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1204                 if (ret)
1205                         return ret;
1206
1207                 if ((val & 0x40) == 0x40)
1208                         lockStatus = LG3306_LOCK;
1209                 else
1210                         lockStatus = LG3306_UNLOCK;
1211
1212                 dbg_info("AGC_LOCK=%x\n", lockStatus);
1213                 break;
1214         }
1215         case LG3306_TR_LOCK:
1216         {
1217                 modeOper = lgdt3306a_check_oper_mode(state);
1218                 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1219                         ret = lgdt3306a_read_reg(state, 0x1094, &val);
1220                         if (ret)
1221                                 return ret;
1222
1223                         if ((val & 0x80) == 0x80)
1224                                 lockStatus = LG3306_LOCK;
1225                         else
1226                                 lockStatus = LG3306_UNLOCK;
1227                 } else
1228                         lockStatus = LG3306_UNKNOWN_LOCK;
1229
1230                 dbg_info("TR_LOCK=%x\n", lockStatus);
1231                 break;
1232         }
1233         case LG3306_FEC_LOCK:
1234         {
1235                 modeOper = lgdt3306a_check_oper_mode(state);
1236                 if ((modeOper == LG3306_QAM64) || (modeOper == LG3306_QAM256)) {
1237                         ret = lgdt3306a_read_reg(state, 0x0080, &val);
1238                         if (ret)
1239                                 return ret;
1240
1241                         if ((val & 0x10) == 0x10)
1242                                 lockStatus = LG3306_LOCK;
1243                         else
1244                                 lockStatus = LG3306_UNLOCK;
1245                 } else
1246                         lockStatus = LG3306_UNKNOWN_LOCK;
1247
1248                 dbg_info("FEC_LOCK=%x\n", lockStatus);
1249                 break;
1250         }
1251
1252         default:
1253                 lockStatus = LG3306_UNKNOWN_LOCK;
1254                 pr_warn("UNKNOWN whatLock=%d\n", whatLock);
1255                 break;
1256         }
1257
1258         return lockStatus;
1259 }
1260
1261 static enum lgdt3306a_neverlock_status
1262 lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
1263 {
1264         u8 val = 0;
1265         int ret;
1266         enum lgdt3306a_neverlock_status lockStatus;
1267
1268         ret = lgdt3306a_read_reg(state, 0x0080, &val);
1269         if (ret)
1270                 return ret;
1271         lockStatus = (enum lgdt3306a_neverlock_status)(val & 0x03);
1272
1273         dbg_info("NeverLock=%d", lockStatus);
1274
1275         return lockStatus;
1276 }
1277
1278 static int lgdt3306a_pre_monitoring(struct lgdt3306a_state *state)
1279 {
1280         u8 val = 0;
1281         int ret;
1282         u8 currChDiffACQ, snrRef, mainStrong, aiccrejStatus;
1283
1284         /* Channel variation */
1285         ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
1286         if (ret)
1287                 return ret;
1288
1289         /* SNR of Frame sync */
1290         ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1291         if (ret)
1292                 return ret;
1293         snrRef = val & 0x3f;
1294
1295         /* Strong Main CIR */
1296         ret = lgdt3306a_read_reg(state, 0x2199, &val);
1297         if (ret)
1298                 return ret;
1299         mainStrong = (val & 0x40) >> 6;
1300
1301         ret = lgdt3306a_read_reg(state, 0x0090, &val);
1302         if (ret)
1303                 return ret;
1304         aiccrejStatus = (val & 0xf0) >> 4;
1305
1306         dbg_info("snrRef=%d mainStrong=%d aiccrejStatus=%d currChDiffACQ=0x%x\n",
1307                 snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
1308
1309 #if 0
1310         /* Dynamic ghost exists */
1311         if ((mainStrong == 0) && (currChDiffACQ > 0x70))
1312 #endif
1313         if (mainStrong == 0) {
1314                 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1315                 if (ret)
1316                         return ret;
1317                 val &= 0x0f;
1318                 val |= 0xa0;
1319                 ret = lgdt3306a_write_reg(state, 0x2135, val);
1320                 if (ret)
1321                         return ret;
1322
1323                 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1324                 if (ret)
1325                         return ret;
1326                 val &= 0x3f;
1327                 val |= 0x80;
1328                 ret = lgdt3306a_write_reg(state, 0x2141, val);
1329                 if (ret)
1330                         return ret;
1331
1332                 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
1333                 if (ret)
1334                         return ret;
1335         } else { /* Weak ghost or static channel */
1336                 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1337                 if (ret)
1338                         return ret;
1339                 val &= 0x0f;
1340                 val |= 0x70;
1341                 ret = lgdt3306a_write_reg(state, 0x2135, val);
1342                 if (ret)
1343                         return ret;
1344
1345                 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1346                 if (ret)
1347                         return ret;
1348                 val &= 0x3f;
1349                 val |= 0x40;
1350                 ret = lgdt3306a_write_reg(state, 0x2141, val);
1351                 if (ret)
1352                         return ret;
1353
1354                 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
1355                 if (ret)
1356                         return ret;
1357         }
1358         return 0;
1359 }
1360
1361 static enum lgdt3306a_lock_status
1362 lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
1363 {
1364         enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
1365         int     i;
1366
1367         for (i = 0; i < 2; i++) {
1368                 msleep(30);
1369
1370                 syncLockStatus = lgdt3306a_check_lock_status(state,
1371                                                              LG3306_SYNC_LOCK);
1372
1373                 if (syncLockStatus == LG3306_LOCK) {
1374                         dbg_info("locked(%d)\n", i);
1375                         return LG3306_LOCK;
1376                 }
1377         }
1378         dbg_info("not locked\n");
1379         return LG3306_UNLOCK;
1380 }
1381
1382 static enum lgdt3306a_lock_status
1383 lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
1384 {
1385         enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
1386         int     i;
1387
1388         for (i = 0; i < 2; i++) {
1389                 msleep(30);
1390
1391                 FECLockStatus = lgdt3306a_check_lock_status(state,
1392                                                             LG3306_FEC_LOCK);
1393
1394                 if (FECLockStatus == LG3306_LOCK) {
1395                         dbg_info("locked(%d)\n", i);
1396                         return FECLockStatus;
1397                 }
1398         }
1399         dbg_info("not locked\n");
1400         return FECLockStatus;
1401 }
1402
1403 static enum lgdt3306a_neverlock_status
1404 lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
1405 {
1406         enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
1407         int     i;
1408
1409         for (i = 0; i < 5; i++) {
1410                 msleep(30);
1411
1412                 NLLockStatus = lgdt3306a_check_neverlock_status(state);
1413
1414                 if (NLLockStatus == LG3306_NL_LOCK) {
1415                         dbg_info("NL_LOCK(%d)\n", i);
1416                         return NLLockStatus;
1417                 }
1418         }
1419         dbg_info("NLLockStatus=%d\n", NLLockStatus);
1420         return NLLockStatus;
1421 }
1422
1423 static u8 lgdt3306a_get_packet_error(struct lgdt3306a_state *state)
1424 {
1425         u8 val;
1426         int ret;
1427
1428         ret = lgdt3306a_read_reg(state, 0x00fa, &val);
1429         if (ret)
1430                 return ret;
1431
1432         return val;
1433 }
1434
1435 static const u32 valx_x10[] = {
1436         10,  11,  13,  15,  17,  20,  25,  33,  41,  50,  59,  73,  87,  100
1437 };
1438 static const u32 log10x_x1000[] = {
1439         0,   41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
1440 };
1441
1442 static u32 log10_x1000(u32 x)
1443 {
1444         u32 diff_val, step_val, step_log10;
1445         u32 log_val = 0;
1446         u32 i;
1447
1448         if (x <= 0)
1449                 return -1000000; /* signal error */
1450
1451         if (x == 10)
1452                 return 0; /* log(1)=0 */
1453
1454         if (x < 10) {
1455                 while (x < 10) {
1456                         x = x * 10;
1457                         log_val--;
1458                 }
1459         } else {        /* x > 10 */
1460                 while (x >= 100) {
1461                         x = x / 10;
1462                         log_val++;
1463                 }
1464         }
1465         log_val *= 1000;
1466
1467         if (x == 10) /* was our input an exact multiple of 10 */
1468                 return log_val; /* don't need to interpolate */
1469
1470         /* find our place on the log curve */
1471         for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
1472                 if (valx_x10[i] >= x)
1473                         break;
1474         }
1475         if (i == ARRAY_SIZE(valx_x10))
1476                 return log_val + log10x_x1000[i - 1];
1477
1478         diff_val   = x - valx_x10[i-1];
1479         step_val   = valx_x10[i] - valx_x10[i - 1];
1480         step_log10 = log10x_x1000[i] - log10x_x1000[i - 1];
1481
1482         /* do a linear interpolation to get in-between values */
1483         return log_val + log10x_x1000[i - 1] +
1484                 ((diff_val*step_log10) / step_val);
1485 }
1486
1487 static u32 lgdt3306a_calculate_snr_x100(struct lgdt3306a_state *state)
1488 {
1489         u32 mse; /* Mean-Square Error */
1490         u32 pwr; /* Constelation power */
1491         u32 snr_x100;
1492
1493         mse = (read_reg(state, 0x00ec) << 8) |
1494               (read_reg(state, 0x00ed));
1495         pwr = (read_reg(state, 0x00e8) << 8) |
1496               (read_reg(state, 0x00e9));
1497
1498         if (mse == 0) /* no signal */
1499                 return 0;
1500
1501         snr_x100 = log10_x1000((pwr * 10000) / mse) - 3000;
1502         dbg_info("mse=%u, pwr=%u, snr_x100=%d\n", mse, pwr, snr_x100);
1503
1504         return snr_x100;
1505 }
1506
1507 static enum lgdt3306a_lock_status
1508 lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
1509 {
1510         int ret;
1511         u8 cnt = 0;
1512         u8 packet_error;
1513         u32 snr;
1514
1515         for (cnt = 0; cnt < 10; cnt++) {
1516                 if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
1517                         dbg_info("no sync lock!\n");
1518                         return LG3306_UNLOCK;
1519                 }
1520
1521                 msleep(20);
1522                 ret = lgdt3306a_pre_monitoring(state);
1523                 if (ret)
1524                         break;
1525
1526                 packet_error = lgdt3306a_get_packet_error(state);
1527                 snr = lgdt3306a_calculate_snr_x100(state);
1528                 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1529
1530                 if ((snr >= 1500) && (packet_error < 0xff))
1531                         return LG3306_LOCK;
1532         }
1533
1534         dbg_info("not locked!\n");
1535         return LG3306_UNLOCK;
1536 }
1537
1538 static enum lgdt3306a_lock_status
1539 lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
1540 {
1541         u8 cnt;
1542         u8 packet_error;
1543         u32     snr;
1544
1545         for (cnt = 0; cnt < 10; cnt++) {
1546                 if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
1547                         dbg_info("no fec lock!\n");
1548                         return LG3306_UNLOCK;
1549                 }
1550
1551                 msleep(20);
1552
1553                 packet_error = lgdt3306a_get_packet_error(state);
1554                 snr = lgdt3306a_calculate_snr_x100(state);
1555                 dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
1556
1557                 if ((snr >= 1500) && (packet_error < 0xff))
1558                         return LG3306_LOCK;
1559         }
1560
1561         dbg_info("not locked!\n");
1562         return LG3306_UNLOCK;
1563 }
1564
1565 static int lgdt3306a_read_status(struct dvb_frontend *fe,
1566                                  enum fe_status *status)
1567 {
1568         struct lgdt3306a_state *state = fe->demodulator_priv;
1569         u16 strength = 0;
1570         int ret = 0;
1571
1572         if (fe->ops.tuner_ops.get_rf_strength) {
1573                 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
1574                 if (ret == 0)
1575                         dbg_info("strength=%d\n", strength);
1576                 else
1577                         dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
1578         }
1579
1580         *status = 0;
1581         if (lgdt3306a_neverlock_poll(state) == LG3306_NL_LOCK) {
1582                 *status |= FE_HAS_SIGNAL;
1583                 *status |= FE_HAS_CARRIER;
1584
1585                 switch (state->current_modulation) {
1586                 case QAM_256:
1587                 case QAM_64:
1588                         if (lgdt3306a_qam_lock_poll(state) == LG3306_LOCK) {
1589                                 *status |= FE_HAS_VITERBI;
1590                                 *status |= FE_HAS_SYNC;
1591
1592                                 *status |= FE_HAS_LOCK;
1593                         }
1594                         break;
1595                 case VSB_8:
1596                         if (lgdt3306a_vsb_lock_poll(state) == LG3306_LOCK) {
1597                                 *status |= FE_HAS_VITERBI;
1598                                 *status |= FE_HAS_SYNC;
1599
1600                                 *status |= FE_HAS_LOCK;
1601
1602                                 ret = lgdt3306a_monitor_vsb(state);
1603                         }
1604                         break;
1605                 default:
1606                         ret = -EINVAL;
1607                 }
1608         }
1609         return ret;
1610 }
1611
1612
1613 static int lgdt3306a_read_snr(struct dvb_frontend *fe, u16 *snr)
1614 {
1615         struct lgdt3306a_state *state = fe->demodulator_priv;
1616
1617         state->snr = lgdt3306a_calculate_snr_x100(state);
1618         /* report SNR in dB * 10 */
1619         *snr = state->snr/10;
1620
1621         return 0;
1622 }
1623
1624 static int lgdt3306a_read_signal_strength(struct dvb_frontend *fe,
1625                                          u16 *strength)
1626 {
1627         /*
1628          * Calculate some sort of "strength" from SNR
1629          */
1630         struct lgdt3306a_state *state = fe->demodulator_priv;
1631         u16 snr; /* snr_x10 */
1632         int ret;
1633         u32 ref_snr; /* snr*100 */
1634         u32 str;
1635
1636         *strength = 0;
1637
1638         switch (state->current_modulation) {
1639         case VSB_8:
1640                  ref_snr = 1600; /* 16dB */
1641                  break;
1642         case QAM_64:
1643                  ref_snr = 2200; /* 22dB */
1644                  break;
1645         case QAM_256:
1646                  ref_snr = 2800; /* 28dB */
1647                  break;
1648         default:
1649                 return -EINVAL;
1650         }
1651
1652         ret = fe->ops.read_snr(fe, &snr);
1653         if (lg_chkerr(ret))
1654                 goto fail;
1655
1656         if (state->snr <= (ref_snr - 100))
1657                 str = 0;
1658         else if (state->snr <= ref_snr)
1659                 str = (0xffff * 65) / 100; /* 65% */
1660         else {
1661                 str = state->snr - ref_snr;
1662                 str /= 50;
1663                 str += 78; /* 78%-100% */
1664                 if (str > 100)
1665                         str = 100;
1666                 str = (0xffff * str) / 100;
1667         }
1668         *strength = (u16)str;
1669         dbg_info("strength=%u\n", *strength);
1670
1671 fail:
1672         return ret;
1673 }
1674
1675 /* ------------------------------------------------------------------------ */
1676
1677 static int lgdt3306a_read_ber(struct dvb_frontend *fe, u32 *ber)
1678 {
1679         struct lgdt3306a_state *state = fe->demodulator_priv;
1680         u32 tmp;
1681
1682         *ber = 0;
1683 #if 1
1684         /* FGR - FIXME - I don't know what value is expected by dvb_core
1685          * what is the scale of the value?? */
1686         tmp =              read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
1687         tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
1688         tmp = (tmp << 8) | read_reg(state, 0x00fe); /* NBERVALUE[8-15] */
1689         tmp = (tmp << 8) | read_reg(state, 0x00ff); /* NBERVALUE[0-7] */
1690         *ber = tmp;
1691         dbg_info("ber=%u\n", tmp);
1692 #endif
1693         return 0;
1694 }
1695
1696 static int lgdt3306a_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1697 {
1698         struct lgdt3306a_state *state = fe->demodulator_priv;
1699
1700         *ucblocks = 0;
1701 #if 1
1702         /* FGR - FIXME - I don't know what value is expected by dvb_core
1703          * what happens when value wraps? */
1704         *ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
1705         dbg_info("ucblocks=%u\n", *ucblocks);
1706 #endif
1707
1708         return 0;
1709 }
1710
1711 static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
1712                           unsigned int mode_flags, unsigned int *delay,
1713                           enum fe_status *status)
1714 {
1715         int ret = 0;
1716         struct lgdt3306a_state *state = fe->demodulator_priv;
1717
1718         dbg_info("re_tune=%u\n", re_tune);
1719
1720         if (re_tune) {
1721                 state->current_frequency = -1; /* force re-tune */
1722                 ret = lgdt3306a_set_parameters(fe);
1723                 if (ret != 0)
1724                         return ret;
1725         }
1726         *delay = 125;
1727         ret = lgdt3306a_read_status(fe, status);
1728
1729         return ret;
1730 }
1731
1732 static int lgdt3306a_get_tune_settings(struct dvb_frontend *fe,
1733                                        struct dvb_frontend_tune_settings
1734                                        *fe_tune_settings)
1735 {
1736         fe_tune_settings->min_delay_ms = 100;
1737         dbg_info("\n");
1738         return 0;
1739 }
1740
1741 static int lgdt3306a_search(struct dvb_frontend *fe)
1742 {
1743         enum fe_status status = 0;
1744         int ret;
1745
1746         /* set frontend */
1747         ret = lgdt3306a_set_parameters(fe);
1748         if (ret)
1749                 goto error;
1750
1751         ret = lgdt3306a_read_status(fe, &status);
1752         if (ret)
1753                 goto error;
1754
1755         /* check if we have a valid signal */
1756         if (status & FE_HAS_LOCK)
1757                 return DVBFE_ALGO_SEARCH_SUCCESS;
1758         else
1759                 return DVBFE_ALGO_SEARCH_AGAIN;
1760
1761 error:
1762         dbg_info("failed (%d)\n", ret);
1763         return DVBFE_ALGO_SEARCH_ERROR;
1764 }
1765
1766 static void lgdt3306a_release(struct dvb_frontend *fe)
1767 {
1768         struct lgdt3306a_state *state = fe->demodulator_priv;
1769
1770         dbg_info("\n");
1771         kfree(state);
1772 }
1773
1774 static const struct dvb_frontend_ops lgdt3306a_ops;
1775
1776 struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config,
1777                                       struct i2c_adapter *i2c_adap)
1778 {
1779         struct lgdt3306a_state *state = NULL;
1780         int ret;
1781         u8 val;
1782
1783         dbg_info("(%d-%04x)\n",
1784                i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1785                config ? config->i2c_addr : 0);
1786
1787         state = kzalloc(sizeof(struct lgdt3306a_state), GFP_KERNEL);
1788         if (state == NULL)
1789                 goto fail;
1790
1791         state->cfg = config;
1792         state->i2c_adap = i2c_adap;
1793
1794         memcpy(&state->frontend.ops, &lgdt3306a_ops,
1795                sizeof(struct dvb_frontend_ops));
1796         state->frontend.demodulator_priv = state;
1797
1798         /* verify that we're talking to a lg3306a */
1799         /* FGR - NOTE - there is no obvious ChipId to check; we check
1800          * some "known" bits after reset, but it's still just a guess */
1801         ret = lgdt3306a_read_reg(state, 0x0000, &val);
1802         if (lg_chkerr(ret))
1803                 goto fail;
1804         if ((val & 0x74) != 0x74) {
1805                 pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
1806 #if 0
1807                 /* FIXME - re-enable when we know this is right */
1808                 goto fail;
1809 #endif
1810         }
1811         ret = lgdt3306a_read_reg(state, 0x0001, &val);
1812         if (lg_chkerr(ret))
1813                 goto fail;
1814         if ((val & 0xf6) != 0xc6) {
1815                 pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
1816 #if 0
1817                 /* FIXME - re-enable when we know this is right */
1818                 goto fail;
1819 #endif
1820         }
1821         ret = lgdt3306a_read_reg(state, 0x0002, &val);
1822         if (lg_chkerr(ret))
1823                 goto fail;
1824         if ((val & 0x73) != 0x03) {
1825                 pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
1826 #if 0
1827                 /* FIXME - re-enable when we know this is right */
1828                 goto fail;
1829 #endif
1830         }
1831
1832         state->current_frequency = -1;
1833         state->current_modulation = -1;
1834
1835         lgdt3306a_sleep(state);
1836
1837         return &state->frontend;
1838
1839 fail:
1840         pr_warn("unable to detect LGDT3306A hardware\n");
1841         kfree(state);
1842         return NULL;
1843 }
1844 EXPORT_SYMBOL(lgdt3306a_attach);
1845
1846 #ifdef DBG_DUMP
1847
1848 static const short regtab[] = {
1849         0x0000, /* SOFTRSTB 1'b1 1'b1 1'b1 ADCPDB 1'b1 PLLPDB GBBPDB 11111111 */
1850         0x0001, /* 1'b1 1'b1 1'b0 1'b0 AUTORPTRS */
1851         0x0002, /* NI2CRPTEN 1'b0 1'b0 1'b0 SPECINVAUT */
1852         0x0003, /* AGCRFOUT */
1853         0x0004, /* ADCSEL1V ADCCNT ADCCNF ADCCNS ADCCLKPLL */
1854         0x0005, /* PLLINDIVSE */
1855         0x0006, /* PLLCTRL[7:0] 11100001 */
1856         0x0007, /* SYSINITWAITTIME[7:0] (msec) 00001000 */
1857         0x0008, /* STDOPMODE[7:0] 10000000 */
1858         0x0009, /* 1'b0 1'b0 1'b0 STDOPDETTMODE[2:0] STDOPDETCMODE[1:0] 00011110 */
1859         0x000a, /* DAFTEN 1'b1 x x SCSYSLOCK */
1860         0x000b, /* SCSYSLOCKCHKTIME[7:0] (10msec) 01100100 */
1861         0x000d, /* x SAMPLING4 */
1862         0x000e, /* SAMFREQ[15:8] 00000000 */
1863         0x000f, /* SAMFREQ[7:0] 00000000 */
1864         0x0010, /* IFFREQ[15:8] 01100000 */
1865         0x0011, /* IFFREQ[7:0] 00000000 */
1866         0x0012, /* AGCEN AGCREFMO */
1867         0x0013, /* AGCRFFIXB AGCIFFIXB AGCLOCKDETRNGSEL[1:0] 1'b1 1'b0 1'b0 1'b0 11101000 */
1868         0x0014, /* AGCFIXVALUE[7:0] 01111111 */
1869         0x0015, /* AGCREF[15:8] 00001010 */
1870         0x0016, /* AGCREF[7:0] 11100100 */
1871         0x0017, /* AGCDELAY[7:0] 00100000 */
1872         0x0018, /* AGCRFBW[3:0] AGCIFBW[3:0] 10001000 */
1873         0x0019, /* AGCUDOUTMODE[1:0] AGCUDCTRLLEN[1:0] AGCUDCTRL */
1874         0x001c, /* 1'b1 PFEN MFEN AICCVSYNC */
1875         0x001d, /* 1'b0 1'b1 1'b0 1'b1 AICCVSYNC */
1876         0x001e, /* AICCALPHA[3:0] 1'b1 1'b0 1'b1 1'b0 01111010 */
1877         0x001f, /* AICCDETTH[19:16] AICCOFFTH[19:16] 00000000 */
1878         0x0020, /* AICCDETTH[15:8] 01111100 */
1879         0x0021, /* AICCDETTH[7:0] 00000000 */
1880         0x0022, /* AICCOFFTH[15:8] 00000101 */
1881         0x0023, /* AICCOFFTH[7:0] 11100000 */
1882         0x0024, /* AICCOPMODE3[1:0] AICCOPMODE2[1:0] AICCOPMODE1[1:0] AICCOPMODE0[1:0] 00000000 */
1883         0x0025, /* AICCFIXFREQ3[23:16] 00000000 */
1884         0x0026, /* AICCFIXFREQ3[15:8] 00000000 */
1885         0x0027, /* AICCFIXFREQ3[7:0] 00000000 */
1886         0x0028, /* AICCFIXFREQ2[23:16] 00000000 */
1887         0x0029, /* AICCFIXFREQ2[15:8] 00000000 */
1888         0x002a, /* AICCFIXFREQ2[7:0] 00000000 */
1889         0x002b, /* AICCFIXFREQ1[23:16] 00000000 */
1890         0x002c, /* AICCFIXFREQ1[15:8] 00000000 */
1891         0x002d, /* AICCFIXFREQ1[7:0] 00000000 */
1892         0x002e, /* AICCFIXFREQ0[23:16] 00000000 */
1893         0x002f, /* AICCFIXFREQ0[15:8] 00000000 */
1894         0x0030, /* AICCFIXFREQ0[7:0] 00000000 */
1895         0x0031, /* 1'b0 1'b1 1'b0 1'b0 x DAGC1STER */
1896         0x0032, /* DAGC1STEN DAGC1STER */
1897         0x0033, /* DAGC1STREF[15:8] 00001010 */
1898         0x0034, /* DAGC1STREF[7:0] 11100100 */
1899         0x0035, /* DAGC2NDE */
1900         0x0036, /* DAGC2NDREF[15:8] 00001010 */
1901         0x0037, /* DAGC2NDREF[7:0] 10000000 */
1902         0x0038, /* DAGC2NDLOCKDETRNGSEL[1:0] */
1903         0x003d, /* 1'b1 SAMGEARS */
1904         0x0040, /* SAMLFGMA */
1905         0x0041, /* SAMLFBWM */
1906         0x0044, /* 1'b1 CRGEARSHE */
1907         0x0045, /* CRLFGMAN */
1908         0x0046, /* CFLFBWMA */
1909         0x0047, /* CRLFGMAN */
1910         0x0048, /* x x x x CRLFGSTEP_VS[3:0] xxxx1001 */
1911         0x0049, /* CRLFBWMA */
1912         0x004a, /* CRLFBWMA */
1913         0x0050, /* 1'b0 1'b1 1'b1 1'b0 MSECALCDA */
1914         0x0070, /* TPOUTEN TPIFEN TPCLKOUTE */
1915         0x0071, /* TPSENB TPSSOPBITE */
1916         0x0073, /* TP47HINS x x CHBERINT PERMODE[1:0] PERINT[1:0] 1xx11100 */
1917         0x0075, /* x x x x x IQSWAPCTRL[2:0] xxxxx000 */
1918         0x0076, /* NBERCON NBERST NBERPOL NBERWSYN */
1919         0x0077, /* x NBERLOSTTH[2:0] NBERACQTH[3:0] x0000000 */
1920         0x0078, /* NBERPOLY[31:24] 00000000 */
1921         0x0079, /* NBERPOLY[23:16] 00000000 */
1922         0x007a, /* NBERPOLY[15:8] 00000000 */
1923         0x007b, /* NBERPOLY[7:0] 00000000 */
1924         0x007c, /* NBERPED[31:24] 00000000 */
1925         0x007d, /* NBERPED[23:16] 00000000 */
1926         0x007e, /* NBERPED[15:8] 00000000 */
1927         0x007f, /* NBERPED[7:0] 00000000 */
1928         0x0080, /* x AGCLOCK DAGCLOCK SYSLOCK x x NEVERLOCK[1:0] */
1929         0x0085, /* SPECINVST */
1930         0x0088, /* SYSLOCKTIME[15:8] */
1931         0x0089, /* SYSLOCKTIME[7:0] */
1932         0x008c, /* FECLOCKTIME[15:8] */
1933         0x008d, /* FECLOCKTIME[7:0] */
1934         0x008e, /* AGCACCOUT[15:8] */
1935         0x008f, /* AGCACCOUT[7:0] */
1936         0x0090, /* AICCREJSTATUS[3:0] AICCREJBUSY[3:0] */
1937         0x0091, /* AICCVSYNC */
1938         0x009c, /* CARRFREQOFFSET[15:8] */
1939         0x009d, /* CARRFREQOFFSET[7:0] */
1940         0x00a1, /* SAMFREQOFFSET[23:16] */
1941         0x00a2, /* SAMFREQOFFSET[15:8] */
1942         0x00a3, /* SAMFREQOFFSET[7:0] */
1943         0x00a6, /* SYNCLOCK SYNCLOCKH */
1944 #if 0 /* covered elsewhere */
1945         0x00e8, /* CONSTPWR[15:8] */
1946         0x00e9, /* CONSTPWR[7:0] */
1947         0x00ea, /* BMSE[15:8] */
1948         0x00eb, /* BMSE[7:0] */
1949         0x00ec, /* MSE[15:8] */
1950         0x00ed, /* MSE[7:0] */
1951         0x00ee, /* CONSTI[7:0] */
1952         0x00ef, /* CONSTQ[7:0] */
1953 #endif
1954         0x00f4, /* TPIFTPERRCNT[7:0] */
1955         0x00f5, /* TPCORREC */
1956         0x00f6, /* VBBER[15:8] */
1957         0x00f7, /* VBBER[7:0] */
1958         0x00f8, /* VABER[15:8] */
1959         0x00f9, /* VABER[7:0] */
1960         0x00fa, /* TPERRCNT[7:0] */
1961         0x00fb, /* NBERLOCK x x x x x x x */
1962         0x00fc, /* NBERVALUE[31:24] */
1963         0x00fd, /* NBERVALUE[23:16] */
1964         0x00fe, /* NBERVALUE[15:8] */
1965         0x00ff, /* NBERVALUE[7:0] */
1966         0x1000, /* 1'b0 WODAGCOU */
1967         0x1005, /* x x 1'b1 1'b1 x SRD_Q_QM */
1968         0x1009, /* SRDWAITTIME[7:0] (10msec) 00100011 */
1969         0x100a, /* SRDWAITTIME_CQS[7:0] (msec) 01100100 */
1970         0x101a, /* x 1'b1 1'b0 1'b0 x QMDQAMMODE[2:0] x100x010 */
1971         0x1036, /* 1'b0 1'b1 1'b0 1'b0 SAMGSEND_CQS[3:0] 01001110 */
1972         0x103c, /* SAMGSAUTOSTL_V[3:0] SAMGSAUTOEDL_V[3:0] 01000110 */
1973         0x103d, /* 1'b1 1'b1 SAMCNORMBP_V[1:0] 1'b0 1'b0 SAMMODESEL_V[1:0] 11100001 */
1974         0x103f, /* SAMZTEDSE */
1975         0x105d, /* EQSTATUSE */
1976         0x105f, /* x PMAPG2_V[2:0] x DMAPG2_V[2:0] x001x011 */
1977         0x1060, /* 1'b1 EQSTATUSE */
1978         0x1061, /* CRMAPBWSTL_V[3:0] CRMAPBWEDL_V[3:0] 00000100 */
1979         0x1065, /* 1'b0 x CRMODE_V[1:0] 1'b1 x 1'b1 x 0x111x1x */
1980         0x1066, /* 1'b0 1'b0 1'b1 1'b0 1'b1 PNBOOSTSE */
1981         0x1068, /* CREPHNGAIN2_V[3:0] CREPHNPBW_V[3:0] 10010001 */
1982         0x106e, /* x x x x x CREPHNEN_ */
1983         0x106f, /* CREPHNTH_V[7:0] 00010101 */
1984         0x1072, /* CRSWEEPN */
1985         0x1073, /* CRPGAIN_V[3:0] x x 1'b1 1'b1 1001xx11 */
1986         0x1074, /* CRPBW_V[3:0] x x 1'b1 1'b1 0001xx11 */
1987         0x1080, /* DAFTSTATUS[1:0] x x x x x x */
1988         0x1081, /* SRDSTATUS[1:0] x x x x x SRDLOCK */
1989         0x10a9, /* EQSTATUS_CQS[1:0] x x x x x x */
1990         0x10b7, /* EQSTATUS_V[1:0] x x x x x x */
1991 #if 0 /* SMART_ANT */
1992         0x1f00, /* MODEDETE */
1993         0x1f01, /* x x x x x x x SFNRST xxxxxxx0 */
1994         0x1f03, /* NUMOFANT[7:0] 10000000 */
1995         0x1f04, /* x SELMASK[6:0] x0000000 */
1996         0x1f05, /* x SETMASK[6:0] x0000000 */
1997         0x1f06, /* x TXDATA[6:0] x0000000 */
1998         0x1f07, /* x CHNUMBER[6:0] x0000000 */
1999         0x1f09, /* AGCTIME[23:16] 10011000 */
2000         0x1f0a, /* AGCTIME[15:8] 10010110 */
2001         0x1f0b, /* AGCTIME[7:0] 10000000 */
2002         0x1f0c, /* ANTTIME[31:24] 00000000 */
2003         0x1f0d, /* ANTTIME[23:16] 00000011 */
2004         0x1f0e, /* ANTTIME[15:8] 10010000 */
2005         0x1f0f, /* ANTTIME[7:0] 10010000 */
2006         0x1f11, /* SYNCTIME[23:16] 10011000 */
2007         0x1f12, /* SYNCTIME[15:8] 10010110 */
2008         0x1f13, /* SYNCTIME[7:0] 10000000 */
2009         0x1f14, /* SNRTIME[31:24] 00000001 */
2010         0x1f15, /* SNRTIME[23:16] 01111101 */
2011         0x1f16, /* SNRTIME[15:8] 01111000 */
2012         0x1f17, /* SNRTIME[7:0] 01000000 */
2013         0x1f19, /* FECTIME[23:16] 00000000 */
2014         0x1f1a, /* FECTIME[15:8] 01110010 */
2015         0x1f1b, /* FECTIME[7:0] 01110000 */
2016         0x1f1d, /* FECTHD[7:0] 00000011 */
2017         0x1f1f, /* SNRTHD[23:16] 00001000 */
2018         0x1f20, /* SNRTHD[15:8] 01111111 */
2019         0x1f21, /* SNRTHD[7:0] 10000101 */
2020         0x1f80, /* IRQFLG x x SFSDRFLG MODEBFLG SAVEFLG SCANFLG TRACKFLG */
2021         0x1f81, /* x SYNCCON SNRCON FECCON x STDBUSY SYNCRST AGCFZCO */
2022         0x1f82, /* x x x SCANOPCD[4:0] */
2023         0x1f83, /* x x x x MAINOPCD[3:0] */
2024         0x1f84, /* x x RXDATA[13:8] */
2025         0x1f85, /* RXDATA[7:0] */
2026         0x1f86, /* x x SDTDATA[13:8] */
2027         0x1f87, /* SDTDATA[7:0] */
2028         0x1f89, /* ANTSNR[23:16] */
2029         0x1f8a, /* ANTSNR[15:8] */
2030         0x1f8b, /* ANTSNR[7:0] */
2031         0x1f8c, /* x x x x ANTFEC[13:8] */
2032         0x1f8d, /* ANTFEC[7:0] */
2033         0x1f8e, /* MAXCNT[7:0] */
2034         0x1f8f, /* SCANCNT[7:0] */
2035         0x1f91, /* MAXPW[23:16] */
2036         0x1f92, /* MAXPW[15:8] */
2037         0x1f93, /* MAXPW[7:0] */
2038         0x1f95, /* CURPWMSE[23:16] */
2039         0x1f96, /* CURPWMSE[15:8] */
2040         0x1f97, /* CURPWMSE[7:0] */
2041 #endif /* SMART_ANT */
2042         0x211f, /* 1'b1 1'b1 1'b1 CIRQEN x x 1'b0 1'b0 1111xx00 */
2043         0x212a, /* EQAUTOST */
2044         0x2122, /* CHFAST[7:0] 01100000 */
2045         0x212b, /* FFFSTEP_V[3:0] x FBFSTEP_V[2:0] 0001x001 */
2046         0x212c, /* PHDEROTBWSEL[3:0] 1'b1 1'b1 1'b1 1'b0 10001110 */
2047         0x212d, /* 1'b1 1'b1 1'b1 1'b1 x x TPIFLOCKS */
2048         0x2135, /* DYNTRACKFDEQ[3:0] x 1'b0 1'b0 1'b0 1010x000 */
2049         0x2141, /* TRMODE[1:0] 1'b1 1'b1 1'b0 1'b1 1'b1 1'b1 01110111 */
2050         0x2162, /* AICCCTRLE */
2051         0x2173, /* PHNCNFCNT[7:0] 00000100 */
2052         0x2179, /* 1'b0 1'b0 1'b0 1'b1 x BADSINGLEDYNTRACKFBF[2:0] 0001x001 */
2053         0x217a, /* 1'b0 1'b0 1'b0 1'b1 x BADSLOWSINGLEDYNTRACKFBF[2:0] 0001x001 */
2054         0x217e, /* CNFCNTTPIF[7:0] 00001000 */
2055         0x217f, /* TPERRCNTTPIF[7:0] 00000001 */
2056         0x2180, /* x x x x x x FBDLYCIR[9:8] */
2057         0x2181, /* FBDLYCIR[7:0] */
2058         0x2185, /* MAXPWRMAIN[7:0] */
2059         0x2191, /* NCOMBDET x x x x x x x */
2060         0x2199, /* x MAINSTRON */
2061         0x219a, /* FFFEQSTEPOUT_V[3:0] FBFSTEPOUT_V[2:0] */
2062         0x21a1, /* x x SNRREF[5:0] */
2063         0x2845, /* 1'b0 1'b1 x x FFFSTEP_CQS[1:0] FFFCENTERTAP[1:0] 01xx1110 */
2064         0x2846, /* 1'b0 x 1'b0 1'b1 FBFSTEP_CQS[1:0] 1'b1 1'b0 0x011110 */
2065         0x2847, /* ENNOSIGDE */
2066         0x2849, /* 1'b1 1'b1 NOUSENOSI */
2067         0x284a, /* EQINITWAITTIME[7:0] 01100100 */
2068         0x3000, /* 1'b1 1'b1 1'b1 x x x 1'b0 RPTRSTM */
2069         0x3001, /* RPTRSTWAITTIME[7:0] (100msec) 00110010 */
2070         0x3031, /* FRAMELOC */
2071         0x3032, /* 1'b1 1'b0 1'b0 1'b0 x x FRAMELOCKMODE_CQS[1:0] 1000xx11 */
2072         0x30a9, /* VDLOCK_Q FRAMELOCK */
2073         0x30aa, /* MPEGLOCK */
2074 };
2075
2076 #define numDumpRegs (ARRAY_SIZE(regtab))
2077 static u8 regval1[numDumpRegs] = {0, };
2078 static u8 regval2[numDumpRegs] = {0, };
2079
2080 static void lgdt3306a_DumpAllRegs(struct lgdt3306a_state *state)
2081 {
2082                 memset(regval2, 0xff, sizeof(regval2));
2083                 lgdt3306a_DumpRegs(state);
2084 }
2085
2086 static void lgdt3306a_DumpRegs(struct lgdt3306a_state *state)
2087 {
2088         int i;
2089         int sav_debug = debug;
2090
2091         if ((debug & DBG_DUMP) == 0)
2092                 return;
2093         debug &= ~DBG_REG; /* suppress DBG_REG during reg dump */
2094
2095         lg_debug("\n");
2096
2097         for (i = 0; i < numDumpRegs; i++) {
2098                 lgdt3306a_read_reg(state, regtab[i], &regval1[i]);
2099                 if (regval1[i] != regval2[i]) {
2100                         lg_debug(" %04X = %02X\n", regtab[i], regval1[i]);
2101                         regval2[i] = regval1[i];
2102                 }
2103         }
2104         debug = sav_debug;
2105 }
2106 #endif /* DBG_DUMP */
2107
2108
2109
2110 static const struct dvb_frontend_ops lgdt3306a_ops = {
2111         .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
2112         .info = {
2113                 .name = "LG Electronics LGDT3306A VSB/QAM Frontend",
2114                 .frequency_min      = 54000000,
2115                 .frequency_max      = 858000000,
2116                 .frequency_stepsize = 62500,
2117                 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
2118         },
2119         .i2c_gate_ctrl        = lgdt3306a_i2c_gate_ctrl,
2120         .init                 = lgdt3306a_init,
2121         .sleep                = lgdt3306a_fe_sleep,
2122         /* if this is set, it overrides the default swzigzag */
2123         .tune                 = lgdt3306a_tune,
2124         .set_frontend         = lgdt3306a_set_parameters,
2125         .get_frontend         = lgdt3306a_get_frontend,
2126         .get_frontend_algo    = lgdt3306a_get_frontend_algo,
2127         .get_tune_settings    = lgdt3306a_get_tune_settings,
2128         .read_status          = lgdt3306a_read_status,
2129         .read_ber             = lgdt3306a_read_ber,
2130         .read_signal_strength = lgdt3306a_read_signal_strength,
2131         .read_snr             = lgdt3306a_read_snr,
2132         .read_ucblocks        = lgdt3306a_read_ucblocks,
2133         .release              = lgdt3306a_release,
2134         .ts_bus_ctrl          = lgdt3306a_ts_bus_ctrl,
2135         .search               = lgdt3306a_search,
2136 };
2137
2138 static int lgdt3306a_select(struct i2c_mux_core *muxc, u32 chan)
2139 {
2140         struct i2c_client *client = i2c_mux_priv(muxc);
2141         struct lgdt3306a_state *state = i2c_get_clientdata(client);
2142
2143         return lgdt3306a_i2c_gate_ctrl(&state->frontend, 1);
2144 }
2145
2146 static int lgdt3306a_deselect(struct i2c_mux_core *muxc, u32 chan)
2147 {
2148         struct i2c_client *client = i2c_mux_priv(muxc);
2149         struct lgdt3306a_state *state = i2c_get_clientdata(client);
2150
2151         return lgdt3306a_i2c_gate_ctrl(&state->frontend, 0);
2152 }
2153
2154 static int lgdt3306a_probe(struct i2c_client *client,
2155                 const struct i2c_device_id *id)
2156 {
2157         struct lgdt3306a_config *config;
2158         struct lgdt3306a_state *state;
2159         struct dvb_frontend *fe;
2160         int ret;
2161
2162         config = kzalloc(sizeof(struct lgdt3306a_config), GFP_KERNEL);
2163         if (config == NULL) {
2164                 ret = -ENOMEM;
2165                 goto fail;
2166         }
2167
2168         memcpy(config, client->dev.platform_data,
2169                         sizeof(struct lgdt3306a_config));
2170
2171         config->i2c_addr = client->addr;
2172         fe = lgdt3306a_attach(config, client->adapter);
2173         if (fe == NULL) {
2174                 ret = -ENODEV;
2175                 goto err_fe;
2176         }
2177
2178         i2c_set_clientdata(client, fe->demodulator_priv);
2179         state = fe->demodulator_priv;
2180
2181         /* create mux i2c adapter for tuner */
2182         state->muxc = i2c_mux_alloc(client->adapter, &client->dev,
2183                                   1, 0, I2C_MUX_LOCKED,
2184                                   lgdt3306a_select, lgdt3306a_deselect);
2185         if (!state->muxc) {
2186                 ret = -ENOMEM;
2187                 goto err_kfree;
2188         }
2189         state->muxc->priv = client;
2190         ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
2191         if (ret)
2192                 goto err_kfree;
2193
2194         /* create dvb_frontend */
2195         fe->ops.i2c_gate_ctrl = NULL;
2196         *config->i2c_adapter = state->muxc->adapter[0];
2197         *config->fe = fe;
2198
2199         return 0;
2200
2201 err_kfree:
2202         kfree(state);
2203 err_fe:
2204         kfree(config);
2205 fail:
2206         dev_dbg(&client->dev, "failed=%d\n", ret);
2207         return ret;
2208 }
2209
2210 static int lgdt3306a_remove(struct i2c_client *client)
2211 {
2212         struct lgdt3306a_state *state = i2c_get_clientdata(client);
2213
2214         i2c_mux_del_adapters(state->muxc);
2215
2216         state->frontend.ops.release = NULL;
2217         state->frontend.demodulator_priv = NULL;
2218
2219         kfree(state->cfg);
2220         kfree(state);
2221
2222         return 0;
2223 }
2224
2225 static const struct i2c_device_id lgdt3306a_id_table[] = {
2226         {"lgdt3306a", 0},
2227         {}
2228 };
2229 MODULE_DEVICE_TABLE(i2c, lgdt3306a_id_table);
2230
2231 static struct i2c_driver lgdt3306a_driver = {
2232         .driver = {
2233                 .name                = "lgdt3306a",
2234                 .suppress_bind_attrs = true,
2235         },
2236         .probe          = lgdt3306a_probe,
2237         .remove         = lgdt3306a_remove,
2238         .id_table       = lgdt3306a_id_table,
2239 };
2240
2241 module_i2c_driver(lgdt3306a_driver);
2242
2243 MODULE_DESCRIPTION("LG Electronics LGDT3306A ATSC/QAM-B Demodulator Driver");
2244 MODULE_AUTHOR("Fred Richter <frichter@hauppauge.com>");
2245 MODULE_LICENSE("GPL");
2246 MODULE_VERSION("0.2");