drivers/media/dvb-frontends/drxk_hard.c

   1 /*
   2  * drxk_hard: DRX-K DVB-C/T demodulator driver
   3  *
   4  * Copyright (C) 2010-2011 Digital Devices GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * To obtain the license, point your browser to
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/moduleparam.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/firmware.h>
  28 #include <linux/i2c.h>
  29 #include <linux/hardirq.h>
  30 #include <asm/div64.h>
  31
  32 #include <media/dvb_frontend.h>
  33 #include "drxk.h"
  34 #include "drxk_hard.h"
  35 #include <media/dvb_math.h>
  36
  37 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
  38 static int power_down_qam(struct drxk_state *state);
  39 static int set_dvbt_standard(struct drxk_state *state,
  40                            enum operation_mode o_mode);
  41 static int set_qam_standard(struct drxk_state *state,
  42                           enum operation_mode o_mode);
  43 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
  44                   s32 tuner_freq_offset);
  45 static int set_dvbt_standard(struct drxk_state *state,
  46                            enum operation_mode o_mode);
  47 static int dvbt_start(struct drxk_state *state);
  48 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
  49                    s32 tuner_freq_offset);
  50 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
  51 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
  52 static int switch_antenna_to_qam(struct drxk_state *state);
  53 static int switch_antenna_to_dvbt(struct drxk_state *state);
  54
  55 static bool is_dvbt(struct drxk_state *state)
  56 {
  57         return state->m_operation_mode == OM_DVBT;
  58 }
  59
  60 static bool is_qam(struct drxk_state *state)
  61 {
  62         return state->m_operation_mode == OM_QAM_ITU_A ||
  63             state->m_operation_mode == OM_QAM_ITU_B ||
  64             state->m_operation_mode == OM_QAM_ITU_C;
  65 }
  66
  67 #define NOA1ROM 0
  68
  69 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
  70 #define DRXDAP_FASI_LONG_FORMAT(addr)  (((addr) & 0xFC30FF80) != 0)
  71
  72 #define DEFAULT_MER_83  165
  73 #define DEFAULT_MER_93  250
  74
  75 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
  76 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
  77 #endif
  78
  79 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
  80 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
  81 #endif
  82
  83 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
  84 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
  85
  86 #ifndef DRXK_KI_RAGC_ATV
  87 #define DRXK_KI_RAGC_ATV   4
  88 #endif
  89 #ifndef DRXK_KI_IAGC_ATV
  90 #define DRXK_KI_IAGC_ATV   6
  91 #endif
  92 #ifndef DRXK_KI_DAGC_ATV
  93 #define DRXK_KI_DAGC_ATV   7
  94 #endif
  95
  96 #ifndef DRXK_KI_RAGC_QAM
  97 #define DRXK_KI_RAGC_QAM   3
  98 #endif
  99 #ifndef DRXK_KI_IAGC_QAM
 100 #define DRXK_KI_IAGC_QAM   4
 101 #endif
 102 #ifndef DRXK_KI_DAGC_QAM
 103 #define DRXK_KI_DAGC_QAM   7
 104 #endif
 105 #ifndef DRXK_KI_RAGC_DVBT
 106 #define DRXK_KI_RAGC_DVBT  (IsA1WithPatchCode(state) ? 3 : 2)
 107 #endif
 108 #ifndef DRXK_KI_IAGC_DVBT
 109 #define DRXK_KI_IAGC_DVBT  (IsA1WithPatchCode(state) ? 4 : 2)
 110 #endif
 111 #ifndef DRXK_KI_DAGC_DVBT
 112 #define DRXK_KI_DAGC_DVBT  (IsA1WithPatchCode(state) ? 10 : 7)
 113 #endif
 114
 115 #ifndef DRXK_AGC_DAC_OFFSET
 116 #define DRXK_AGC_DAC_OFFSET (0x800)
 117 #endif
 118
 119 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
 120 #define DRXK_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)
 121 #endif
 122
 123 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
 124 #define DRXK_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)
 125 #endif
 126
 127 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
 128 #define DRXK_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
 129 #endif
 130
 131 #ifndef DRXK_QAM_SYMBOLRATE_MAX
 132 #define DRXK_QAM_SYMBOLRATE_MAX         (7233000)
 133 #endif
 134
 135 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT    56
 136 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A   64
 137 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C   0x5FE0
 138 #define DRXK_BL_ROM_OFFSET_TAPS_BG      24
 139 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP  32
 140 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC    40
 141 #define DRXK_BL_ROM_OFFSET_TAPS_FM      48
 142 #define DRXK_BL_ROM_OFFSET_UCODE        0
 143
 144 #define DRXK_BLC_TIMEOUT                100
 145
 146 #define DRXK_BLCC_NR_ELEMENTS_TAPS      2
 147 #define DRXK_BLCC_NR_ELEMENTS_UCODE     6
 148
 149 #define DRXK_BLDC_NR_ELEMENTS_TAPS      28
 150
 151 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
 152 #define DRXK_OFDM_NE_NOTCH_WIDTH             (4)
 153 #endif
 154
 155 #define DRXK_QAM_SL_SIG_POWER_QAM16       (40960)
 156 #define DRXK_QAM_SL_SIG_POWER_QAM32       (20480)
 157 #define DRXK_QAM_SL_SIG_POWER_QAM64       (43008)
 158 #define DRXK_QAM_SL_SIG_POWER_QAM128      (20992)
 159 #define DRXK_QAM_SL_SIG_POWER_QAM256      (43520)
 160
 161 static unsigned int debug;
 162 module_param(debug, int, 0644);
 163 MODULE_PARM_DESC(debug, "enable debug messages");
 164
 165 #define dprintk(level, fmt, arg...) do {                                \
 166 if (debug >= level)                                                     \
 167         printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \
 168 } while (0)
 169
 170
 171 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
 172 {
 173         u64 tmp64;
 174
 175         tmp64 = (u64) a * (u64) b;
 176         do_div(tmp64, c);
 177
 178         return (u32) tmp64;
 179 }
 180
 181 static inline u32 Frac28a(u32 a, u32 c)
 182 {
 183         int i = 0;
 184         u32 Q1 = 0;
 185         u32 R0 = 0;
 186
 187         R0 = (a % c) << 4;      /* 32-28 == 4 shifts possible at max */
 188         Q1 = a / c;             /*
 189                                  * integer part, only the 4 least significant
 190                                  * bits will be visible in the result
 191                                  */
 192
 193         /* division using radix 16, 7 nibbles in the result */
 194         for (i = 0; i < 7; i++) {
 195                 Q1 = (Q1 << 4) | (R0 / c);
 196                 R0 = (R0 % c) << 4;
 197         }
 198         /* rounding */
 199         if ((R0 >> 3) >= c)
 200                 Q1++;
 201
 202         return Q1;
 203 }
 204
 205 static inline u32 log10times100(u32 value)
 206 {
 207         return (100L * intlog10(value)) >> 24;
 208 }
 209
 210 /***************************************************************************/
 211 /* I2C **********************************************************************/
 212 /***************************************************************************/
 213
 214 static int drxk_i2c_lock(struct drxk_state *state)
 215 {
 216         i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
 217         state->drxk_i2c_exclusive_lock = true;
 218
 219         return 0;
 220 }
 221
 222 static void drxk_i2c_unlock(struct drxk_state *state)
 223 {
 224         if (!state->drxk_i2c_exclusive_lock)
 225                 return;
 226
 227         i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
 228         state->drxk_i2c_exclusive_lock = false;
 229 }
 230
 231 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
 232                              unsigned len)
 233 {
 234         if (state->drxk_i2c_exclusive_lock)
 235                 return __i2c_transfer(state->i2c, msgs, len);
 236         else
 237                 return i2c_transfer(state->i2c, msgs, len);
 238 }
 239
 240 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
 241 {
 242         struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
 243                                     .buf = val, .len = 1}
 244         };
 245
 246         return drxk_i2c_transfer(state, msgs, 1);
 247 }
 248
 249 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
 250 {
 251         int status;
 252         struct i2c_msg msg = {
 253             .addr = adr, .flags = 0, .buf = data, .len = len };
 254
 255         dprintk(3, ":");
 256         if (debug > 2) {
 257                 int i;
 258                 for (i = 0; i < len; i++)
 259                         pr_cont(" %02x", data[i]);
 260                 pr_cont("\n");
 261         }
 262         status = drxk_i2c_transfer(state, &msg, 1);
 263         if (status >= 0 && status != 1)
 264                 status = -EIO;
 265
 266         if (status < 0)
 267                 pr_err("i2c write error at addr 0x%02x\n", adr);
 268
 269         return status;
 270 }
 271
 272 static int i2c_read(struct drxk_state *state,
 273                     u8 adr, u8 *msg, int len, u8 *answ, int alen)
 274 {
 275         int status;
 276         struct i2c_msg msgs[2] = {
 277                 {.addr = adr, .flags = 0,
 278                                     .buf = msg, .len = len},
 279                 {.addr = adr, .flags = I2C_M_RD,
 280                  .buf = answ, .len = alen}
 281         };
 282
 283         status = drxk_i2c_transfer(state, msgs, 2);
 284         if (status != 2) {
 285                 if (debug > 2)
 286                         pr_cont(": ERROR!\n");
 287                 if (status >= 0)
 288                         status = -EIO;
 289
 290                 pr_err("i2c read error at addr 0x%02x\n", adr);
 291                 return status;
 292         }
 293         if (debug > 2) {
 294                 int i;
 295                 dprintk(2, ": read from");
 296                 for (i = 0; i < len; i++)
 297                         pr_cont(" %02x", msg[i]);
 298                 pr_cont(", value = ");
 299                 for (i = 0; i < alen; i++)
 300                         pr_cont(" %02x", answ[i]);
 301                 pr_cont("\n");
 302         }
 303         return 0;
 304 }
 305
 306 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
 307 {
 308         int status;
 309         u8 adr = state->demod_address, mm1[4], mm2[2], len;
 310
 311         if (state->single_master)
 312                 flags |= 0xC0;
 313
 314         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 315                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
 316                 mm1[1] = ((reg >> 16) & 0xFF);
 317                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
 318                 mm1[3] = ((reg >> 7) & 0xFF);
 319                 len = 4;
 320         } else {
 321                 mm1[0] = ((reg << 1) & 0xFF);
 322                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 323                 len = 2;
 324         }
 325         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
 326         status = i2c_read(state, adr, mm1, len, mm2, 2);
 327         if (status < 0)
 328                 return status;
 329         if (data)
 330                 *data = mm2[0] | (mm2[1] << 8);
 331
 332         return 0;
 333 }
 334
 335 static int read16(struct drxk_state *state, u32 reg, u16 *data)
 336 {
 337         return read16_flags(state, reg, data, 0);
 338 }
 339
 340 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
 341 {
 342         int status;
 343         u8 adr = state->demod_address, mm1[4], mm2[4], len;
 344
 345         if (state->single_master)
 346                 flags |= 0xC0;
 347
 348         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 349                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
 350                 mm1[1] = ((reg >> 16) & 0xFF);
 351                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
 352                 mm1[3] = ((reg >> 7) & 0xFF);
 353                 len = 4;
 354         } else {
 355                 mm1[0] = ((reg << 1) & 0xFF);
 356                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 357                 len = 2;
 358         }
 359         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
 360         status = i2c_read(state, adr, mm1, len, mm2, 4);
 361         if (status < 0)
 362                 return status;
 363         if (data)
 364                 *data = mm2[0] | (mm2[1] << 8) |
 365                     (mm2[2] << 16) | (mm2[3] << 24);
 366
 367         return 0;
 368 }
 369
 370 static int read32(struct drxk_state *state, u32 reg, u32 *data)
 371 {
 372         return read32_flags(state, reg, data, 0);
 373 }
 374
 375 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
 376 {
 377         u8 adr = state->demod_address, mm[6], len;
 378
 379         if (state->single_master)
 380                 flags |= 0xC0;
 381         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 382                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
 383                 mm[1] = ((reg >> 16) & 0xFF);
 384                 mm[2] = ((reg >> 24) & 0xFF) | flags;
 385                 mm[3] = ((reg >> 7) & 0xFF);
 386                 len = 4;
 387         } else {
 388                 mm[0] = ((reg << 1) & 0xFF);
 389                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 390                 len = 2;
 391         }
 392         mm[len] = data & 0xff;
 393         mm[len + 1] = (data >> 8) & 0xff;
 394
 395         dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
 396         return i2c_write(state, adr, mm, len + 2);
 397 }
 398
 399 static int write16(struct drxk_state *state, u32 reg, u16 data)
 400 {
 401         return write16_flags(state, reg, data, 0);
 402 }
 403
 404 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
 405 {
 406         u8 adr = state->demod_address, mm[8], len;
 407
 408         if (state->single_master)
 409                 flags |= 0xC0;
 410         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 411                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
 412                 mm[1] = ((reg >> 16) & 0xFF);
 413                 mm[2] = ((reg >> 24) & 0xFF) | flags;
 414                 mm[3] = ((reg >> 7) & 0xFF);
 415                 len = 4;
 416         } else {
 417                 mm[0] = ((reg << 1) & 0xFF);
 418                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 419                 len = 2;
 420         }
 421         mm[len] = data & 0xff;
 422         mm[len + 1] = (data >> 8) & 0xff;
 423         mm[len + 2] = (data >> 16) & 0xff;
 424         mm[len + 3] = (data >> 24) & 0xff;
 425         dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
 426
 427         return i2c_write(state, adr, mm, len + 4);
 428 }
 429
 430 static int write32(struct drxk_state *state, u32 reg, u32 data)
 431 {
 432         return write32_flags(state, reg, data, 0);
 433 }
 434
 435 static int write_block(struct drxk_state *state, u32 address,
 436                       const int block_size, const u8 p_block[])
 437 {
 438         int status = 0, blk_size = block_size;
 439         u8 flags = 0;
 440
 441         if (state->single_master)
 442                 flags |= 0xC0;
 443
 444         while (blk_size > 0) {
 445                 int chunk = blk_size > state->m_chunk_size ?
 446                     state->m_chunk_size : blk_size;
 447                 u8 *adr_buf = &state->chunk[0];
 448                 u32 adr_length = 0;
 449
 450                 if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
 451                         adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
 452                         adr_buf[1] = ((address >> 16) & 0xFF);
 453                         adr_buf[2] = ((address >> 24) & 0xFF);
 454                         adr_buf[3] = ((address >> 7) & 0xFF);
 455                         adr_buf[2] |= flags;
 456                         adr_length = 4;
 457                         if (chunk == state->m_chunk_size)
 458                                 chunk -= 2;
 459                 } else {
 460                         adr_buf[0] = ((address << 1) & 0xFF);
 461                         adr_buf[1] = (((address >> 16) & 0x0F) |
 462                                      ((address >> 18) & 0xF0));
 463                         adr_length = 2;
 464                 }
 465                 memcpy(&state->chunk[adr_length], p_block, chunk);
 466                 dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
 467                 if (debug > 1) {
 468                         int i;
 469                         if (p_block)
 470                                 for (i = 0; i < chunk; i++)
 471                                         pr_cont(" %02x", p_block[i]);
 472                         pr_cont("\n");
 473                 }
 474                 status = i2c_write(state, state->demod_address,
 475                                    &state->chunk[0], chunk + adr_length);
 476                 if (status < 0) {
 477                         pr_err("%s: i2c write error at addr 0x%02x\n",
 478                                __func__, address);
 479                         break;
 480                 }
 481                 p_block += chunk;
 482                 address += (chunk >> 1);
 483                 blk_size -= chunk;
 484         }
 485         return status;
 486 }
 487
 488 #ifndef DRXK_MAX_RETRIES_POWERUP
 489 #define DRXK_MAX_RETRIES_POWERUP 20
 490 #endif
 491
 492 static int power_up_device(struct drxk_state *state)
 493 {
 494         int status;
 495         u8 data = 0;
 496         u16 retry_count = 0;
 497
 498         dprintk(1, "\n");
 499
 500         status = i2c_read1(state, state->demod_address, &data);
 501         if (status < 0) {
 502                 do {
 503                         data = 0;
 504                         status = i2c_write(state, state->demod_address,
 505                                            &data, 1);
 506                         usleep_range(10000, 11000);
 507                         retry_count++;
 508                         if (status < 0)
 509                                 continue;
 510                         status = i2c_read1(state, state->demod_address,
 511                                            &data);
 512                 } while (status < 0 &&
 513                          (retry_count < DRXK_MAX_RETRIES_POWERUP));
 514                 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
 515                         goto error;
 516         }
 517
 518         /* Make sure all clk domains are active */
 519         status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
 520         if (status < 0)
 521                 goto error;
 522         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
 523         if (status < 0)
 524                 goto error;
 525         /* Enable pll lock tests */
 526         status = write16(state, SIO_CC_PLL_LOCK__A, 1);
 527         if (status < 0)
 528                 goto error;
 529
 530         state->m_current_power_mode = DRX_POWER_UP;
 531
 532 error:
 533         if (status < 0)
 534                 pr_err("Error %d on %s\n", status, __func__);
 535
 536         return status;
 537 }
 538
 539
 540 static int init_state(struct drxk_state *state)
 541 {
 542         /*
 543          * FIXME: most (all?) of the values below should be moved into
 544          * struct drxk_config, as they are probably board-specific
 545          */
 546         u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
 547         u32 ul_vsb_if_agc_output_level = 0;
 548         u32 ul_vsb_if_agc_min_level = 0;
 549         u32 ul_vsb_if_agc_max_level = 0x7FFF;
 550         u32 ul_vsb_if_agc_speed = 3;
 551
 552         u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
 553         u32 ul_vsb_rf_agc_output_level = 0;
 554         u32 ul_vsb_rf_agc_min_level = 0;
 555         u32 ul_vsb_rf_agc_max_level = 0x7FFF;
 556         u32 ul_vsb_rf_agc_speed = 3;
 557         u32 ul_vsb_rf_agc_top = 9500;
 558         u32 ul_vsb_rf_agc_cut_off_current = 4000;
 559
 560         u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
 561         u32 ul_atv_if_agc_output_level = 0;
 562         u32 ul_atv_if_agc_min_level = 0;
 563         u32 ul_atv_if_agc_max_level = 0;
 564         u32 ul_atv_if_agc_speed = 3;
 565
 566         u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
 567         u32 ul_atv_rf_agc_output_level = 0;
 568         u32 ul_atv_rf_agc_min_level = 0;
 569         u32 ul_atv_rf_agc_max_level = 0;
 570         u32 ul_atv_rf_agc_top = 9500;
 571         u32 ul_atv_rf_agc_cut_off_current = 4000;
 572         u32 ul_atv_rf_agc_speed = 3;
 573
 574         u32 ulQual83 = DEFAULT_MER_83;
 575         u32 ulQual93 = DEFAULT_MER_93;
 576
 577         u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
 578         u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
 579
 580         /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
 581         /* io_pad_cfg_mode output mode is drive always */
 582         /* io_pad_cfg_drive is set to power 2 (23 mA) */
 583         u32 ul_gpio_cfg = 0x0113;
 584         u32 ul_invert_ts_clock = 0;
 585         u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
 586         u32 ul_dvbt_bitrate = 50000000;
 587         u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
 588
 589         u32 ul_insert_rs_byte = 0;
 590
 591         u32 ul_rf_mirror = 1;
 592         u32 ul_power_down = 0;
 593
 594         dprintk(1, "\n");
 595
 596         state->m_has_lna = false;
 597         state->m_has_dvbt = false;
 598         state->m_has_dvbc = false;
 599         state->m_has_atv = false;
 600         state->m_has_oob = false;
 601         state->m_has_audio = false;
 602
 603         if (!state->m_chunk_size)
 604                 state->m_chunk_size = 124;
 605
 606         state->m_osc_clock_freq = 0;
 607         state->m_smart_ant_inverted = false;
 608         state->m_b_p_down_open_bridge = false;
 609
 610         /* real system clock frequency in kHz */
 611         state->m_sys_clock_freq = 151875;
 612         /* Timing div, 250ns/Psys */
 613         /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
 614         state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
 615                                    HI_I2C_DELAY) / 1000;
 616         /* Clipping */
 617         if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
 618                 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
 619         state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
 620         /* port/bridge/power down ctrl */
 621         state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
 622
 623         state->m_b_power_down = (ul_power_down != 0);
 624
 625         state->m_drxk_a3_patch_code = false;
 626
 627         /* Init AGC and PGA parameters */
 628         /* VSB IF */
 629         state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
 630         state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
 631         state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
 632         state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
 633         state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
 634         state->m_vsb_pga_cfg = 140;
 635
 636         /* VSB RF */
 637         state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
 638         state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
 639         state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
 640         state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
 641         state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
 642         state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
 643         state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
 644         state->m_vsb_pre_saw_cfg.reference = 0x07;
 645         state->m_vsb_pre_saw_cfg.use_pre_saw = true;
 646
 647         state->m_Quality83percent = DEFAULT_MER_83;
 648         state->m_Quality93percent = DEFAULT_MER_93;
 649         if (ulQual93 <= 500 && ulQual83 < ulQual93) {
 650                 state->m_Quality83percent = ulQual83;
 651                 state->m_Quality93percent = ulQual93;
 652         }
 653
 654         /* ATV IF */
 655         state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
 656         state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
 657         state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
 658         state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
 659         state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
 660
 661         /* ATV RF */
 662         state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
 663         state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
 664         state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
 665         state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
 666         state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
 667         state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
 668         state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
 669         state->m_atv_pre_saw_cfg.reference = 0x04;
 670         state->m_atv_pre_saw_cfg.use_pre_saw = true;
 671
 672
 673         /* DVBT RF */
 674         state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
 675         state->m_dvbt_rf_agc_cfg.output_level = 0;
 676         state->m_dvbt_rf_agc_cfg.min_output_level = 0;
 677         state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
 678         state->m_dvbt_rf_agc_cfg.top = 0x2100;
 679         state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
 680         state->m_dvbt_rf_agc_cfg.speed = 1;
 681
 682
 683         /* DVBT IF */
 684         state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
 685         state->m_dvbt_if_agc_cfg.output_level = 0;
 686         state->m_dvbt_if_agc_cfg.min_output_level = 0;
 687         state->m_dvbt_if_agc_cfg.max_output_level = 9000;
 688         state->m_dvbt_if_agc_cfg.top = 13424;
 689         state->m_dvbt_if_agc_cfg.cut_off_current = 0;
 690         state->m_dvbt_if_agc_cfg.speed = 3;
 691         state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
 692         state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
 693         /* state->m_dvbtPgaCfg = 140; */
 694
 695         state->m_dvbt_pre_saw_cfg.reference = 4;
 696         state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
 697
 698         /* QAM RF */
 699         state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
 700         state->m_qam_rf_agc_cfg.output_level = 0;
 701         state->m_qam_rf_agc_cfg.min_output_level = 6023;
 702         state->m_qam_rf_agc_cfg.max_output_level = 27000;
 703         state->m_qam_rf_agc_cfg.top = 0x2380;
 704         state->m_qam_rf_agc_cfg.cut_off_current = 4000;
 705         state->m_qam_rf_agc_cfg.speed = 3;
 706
 707         /* QAM IF */
 708         state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
 709         state->m_qam_if_agc_cfg.output_level = 0;
 710         state->m_qam_if_agc_cfg.min_output_level = 0;
 711         state->m_qam_if_agc_cfg.max_output_level = 9000;
 712         state->m_qam_if_agc_cfg.top = 0x0511;
 713         state->m_qam_if_agc_cfg.cut_off_current = 0;
 714         state->m_qam_if_agc_cfg.speed = 3;
 715         state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
 716         state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
 717
 718         state->m_qam_pga_cfg = 140;
 719         state->m_qam_pre_saw_cfg.reference = 4;
 720         state->m_qam_pre_saw_cfg.use_pre_saw = false;
 721
 722         state->m_operation_mode = OM_NONE;
 723         state->m_drxk_state = DRXK_UNINITIALIZED;
 724
 725         /* MPEG output configuration */
 726         state->m_enable_mpeg_output = true;     /* If TRUE; enable MPEG output */
 727         state->m_insert_rs_byte = false;        /* If TRUE; insert RS byte */
 728         state->m_invert_data = false;   /* If TRUE; invert DATA signals */
 729         state->m_invert_err = false;    /* If TRUE; invert ERR signal */
 730         state->m_invert_str = false;    /* If TRUE; invert STR signals */
 731         state->m_invert_val = false;    /* If TRUE; invert VAL signals */
 732         state->m_invert_clk = (ul_invert_ts_clock != 0);        /* If TRUE; invert CLK signals */
 733
 734         /* If TRUE; static MPEG clockrate will be used;
 735            otherwise clockrate will adapt to the bitrate of the TS */
 736
 737         state->m_dvbt_bitrate = ul_dvbt_bitrate;
 738         state->m_dvbc_bitrate = ul_dvbc_bitrate;
 739
 740         state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
 741
 742         /* Maximum bitrate in b/s in case static clockrate is selected */
 743         state->m_mpeg_ts_static_bitrate = 19392658;
 744         state->m_disable_te_ihandling = false;
 745
 746         if (ul_insert_rs_byte)
 747                 state->m_insert_rs_byte = true;
 748
 749         state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
 750         if (ul_mpeg_lock_time_out < 10000)
 751                 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
 752         state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
 753         if (ul_demod_lock_time_out < 10000)
 754                 state->m_demod_lock_time_out = ul_demod_lock_time_out;
 755
 756         /* QAM defaults */
 757         state->m_constellation = DRX_CONSTELLATION_AUTO;
 758         state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
 759         state->m_fec_rs_plen = 204 * 8; /* fecRsPlen  annex A */
 760         state->m_fec_rs_prescale = 1;
 761
 762         state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
 763         state->m_agcfast_clip_ctrl_delay = 0;
 764
 765         state->m_gpio_cfg = ul_gpio_cfg;
 766
 767         state->m_b_power_down = false;
 768         state->m_current_power_mode = DRX_POWER_DOWN;
 769
 770         state->m_rfmirror = (ul_rf_mirror == 0);
 771         state->m_if_agc_pol = false;
 772         return 0;
 773 }
 774
 775 static int drxx_open(struct drxk_state *state)
 776 {
 777         int status = 0;
 778         u32 jtag = 0;
 779         u16 bid = 0;
 780         u16 key = 0;
 781
 782         dprintk(1, "\n");
 783         /* stop lock indicator process */
 784         status = write16(state, SCU_RAM_GPIO__A,
 785                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
 786         if (status < 0)
 787                 goto error;
 788         /* Check device id */
 789         status = read16(state, SIO_TOP_COMM_KEY__A, &key);
 790         if (status < 0)
 791                 goto error;
 792         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
 793         if (status < 0)
 794                 goto error;
 795         status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
 796         if (status < 0)
 797                 goto error;
 798         status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
 799         if (status < 0)
 800                 goto error;
 801         status = write16(state, SIO_TOP_COMM_KEY__A, key);
 802 error:
 803         if (status < 0)
 804                 pr_err("Error %d on %s\n", status, __func__);
 805         return status;
 806 }
 807
 808 static int get_device_capabilities(struct drxk_state *state)
 809 {
 810         u16 sio_pdr_ohw_cfg = 0;
 811         u32 sio_top_jtagid_lo = 0;
 812         int status;
 813         const char *spin = "";
 814
 815         dprintk(1, "\n");
 816
 817         /* driver 0.9.0 */
 818         /* stop lock indicator process */
 819         status = write16(state, SCU_RAM_GPIO__A,
 820                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
 821         if (status < 0)
 822                 goto error;
 823         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
 824         if (status < 0)
 825                 goto error;
 826         status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
 827         if (status < 0)
 828                 goto error;
 829         status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
 830         if (status < 0)
 831                 goto error;
 832
 833         switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
 834         case 0:
 835                 /* ignore (bypass ?) */
 836                 break;
 837         case 1:
 838                 /* 27 MHz */
 839                 state->m_osc_clock_freq = 27000;
 840                 break;
 841         case 2:
 842                 /* 20.25 MHz */
 843                 state->m_osc_clock_freq = 20250;
 844                 break;
 845         case 3:
 846                 /* 4 MHz */
 847                 state->m_osc_clock_freq = 20250;
 848                 break;
 849         default:
 850                 pr_err("Clock Frequency is unknown\n");
 851                 return -EINVAL;
 852         }
 853         /*
 854                 Determine device capabilities
 855                 Based on pinning v14
 856                 */
 857         status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
 858         if (status < 0)
 859                 goto error;
 860
 861         pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
 862
 863         /* driver 0.9.0 */
 864         switch ((sio_top_jtagid_lo >> 29) & 0xF) {
 865         case 0:
 866                 state->m_device_spin = DRXK_SPIN_A1;
 867                 spin = "A1";
 868                 break;
 869         case 2:
 870                 state->m_device_spin = DRXK_SPIN_A2;
 871                 spin = "A2";
 872                 break;
 873         case 3:
 874                 state->m_device_spin = DRXK_SPIN_A3;
 875                 spin = "A3";
 876                 break;
 877         default:
 878                 state->m_device_spin = DRXK_SPIN_UNKNOWN;
 879                 status = -EINVAL;
 880                 pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF);
 881                 goto error2;
 882         }
 883         switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
 884         case 0x13:
 885                 /* typeId = DRX3913K_TYPE_ID */
 886                 state->m_has_lna = false;
 887                 state->m_has_oob = false;
 888                 state->m_has_atv = false;
 889                 state->m_has_audio = false;
 890                 state->m_has_dvbt = true;
 891                 state->m_has_dvbc = true;
 892                 state->m_has_sawsw = true;
 893                 state->m_has_gpio2 = false;
 894                 state->m_has_gpio1 = false;
 895                 state->m_has_irqn = false;
 896                 break;
 897         case 0x15:
 898                 /* typeId = DRX3915K_TYPE_ID */
 899                 state->m_has_lna = false;
 900                 state->m_has_oob = false;
 901                 state->m_has_atv = true;
 902                 state->m_has_audio = false;
 903                 state->m_has_dvbt = true;
 904                 state->m_has_dvbc = false;
 905                 state->m_has_sawsw = true;
 906                 state->m_has_gpio2 = true;
 907                 state->m_has_gpio1 = true;
 908                 state->m_has_irqn = false;
 909                 break;
 910         case 0x16:
 911                 /* typeId = DRX3916K_TYPE_ID */
 912                 state->m_has_lna = false;
 913                 state->m_has_oob = false;
 914                 state->m_has_atv = true;
 915                 state->m_has_audio = false;
 916                 state->m_has_dvbt = true;
 917                 state->m_has_dvbc = false;
 918                 state->m_has_sawsw = true;
 919                 state->m_has_gpio2 = true;
 920                 state->m_has_gpio1 = true;
 921                 state->m_has_irqn = false;
 922                 break;
 923         case 0x18:
 924                 /* typeId = DRX3918K_TYPE_ID */
 925                 state->m_has_lna = false;
 926                 state->m_has_oob = false;
 927                 state->m_has_atv = true;
 928                 state->m_has_audio = true;
 929                 state->m_has_dvbt = true;
 930                 state->m_has_dvbc = false;
 931                 state->m_has_sawsw = true;
 932                 state->m_has_gpio2 = true;
 933                 state->m_has_gpio1 = true;
 934                 state->m_has_irqn = false;
 935                 break;
 936         case 0x21:
 937                 /* typeId = DRX3921K_TYPE_ID */
 938                 state->m_has_lna = false;
 939                 state->m_has_oob = false;
 940                 state->m_has_atv = true;
 941                 state->m_has_audio = true;
 942                 state->m_has_dvbt = true;
 943                 state->m_has_dvbc = true;
 944                 state->m_has_sawsw = true;
 945                 state->m_has_gpio2 = true;
 946                 state->m_has_gpio1 = true;
 947                 state->m_has_irqn = false;
 948                 break;
 949         case 0x23:
 950                 /* typeId = DRX3923K_TYPE_ID */
 951                 state->m_has_lna = false;
 952                 state->m_has_oob = false;
 953                 state->m_has_atv = true;
 954                 state->m_has_audio = true;
 955                 state->m_has_dvbt = true;
 956                 state->m_has_dvbc = true;
 957                 state->m_has_sawsw = true;
 958                 state->m_has_gpio2 = true;
 959                 state->m_has_gpio1 = true;
 960                 state->m_has_irqn = false;
 961                 break;
 962         case 0x25:
 963                 /* typeId = DRX3925K_TYPE_ID */
 964                 state->m_has_lna = false;
 965                 state->m_has_oob = false;
 966                 state->m_has_atv = true;
 967                 state->m_has_audio = true;
 968                 state->m_has_dvbt = true;
 969                 state->m_has_dvbc = true;
 970                 state->m_has_sawsw = true;
 971                 state->m_has_gpio2 = true;
 972                 state->m_has_gpio1 = true;
 973                 state->m_has_irqn = false;
 974                 break;
 975         case 0x26:
 976                 /* typeId = DRX3926K_TYPE_ID */
 977                 state->m_has_lna = false;
 978                 state->m_has_oob = false;
 979                 state->m_has_atv = true;
 980                 state->m_has_audio = false;
 981                 state->m_has_dvbt = true;
 982                 state->m_has_dvbc = true;
 983                 state->m_has_sawsw = true;
 984                 state->m_has_gpio2 = true;
 985                 state->m_has_gpio1 = true;
 986                 state->m_has_irqn = false;
 987                 break;
 988         default:
 989                 pr_err("DeviceID 0x%02x not supported\n",
 990                         ((sio_top_jtagid_lo >> 12) & 0xFF));
 991                 status = -EINVAL;
 992                 goto error2;
 993         }
 994
 995         pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
 996                ((sio_top_jtagid_lo >> 12) & 0xFF), spin,
 997                state->m_osc_clock_freq / 1000,
 998                state->m_osc_clock_freq % 1000);
 999
1000 error:
1001         if (status < 0)
1002                 pr_err("Error %d on %s\n", status, __func__);
1003
1004 error2:
1005         return status;
1006 }
1007
1008 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
1009 {
1010         int status;
1011         bool powerdown_cmd;
1012
1013         dprintk(1, "\n");
1014
1015         /* Write command */
1016         status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1017         if (status < 0)
1018                 goto error;
1019         if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1020                 usleep_range(1000, 2000);
1021
1022         powerdown_cmd =
1023             (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1024                     ((state->m_hi_cfg_ctrl) &
1025                      SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1026                     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1027         if (!powerdown_cmd) {
1028                 /* Wait until command rdy */
1029                 u32 retry_count = 0;
1030                 u16 wait_cmd;
1031
1032                 do {
1033                         usleep_range(1000, 2000);
1034                         retry_count += 1;
1035                         status = read16(state, SIO_HI_RA_RAM_CMD__A,
1036                                           &wait_cmd);
1037                 } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES)
1038                          && (wait_cmd != 0));
1039                 if (status < 0)
1040                         goto error;
1041                 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1042         }
1043 error:
1044         if (status < 0)
1045                 pr_err("Error %d on %s\n", status, __func__);
1046
1047         return status;
1048 }
1049
1050 static int hi_cfg_command(struct drxk_state *state)
1051 {
1052         int status;
1053
1054         dprintk(1, "\n");
1055
1056         mutex_lock(&state->mutex);
1057
1058         status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1059                          state->m_hi_cfg_timeout);
1060         if (status < 0)
1061                 goto error;
1062         status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1063                          state->m_hi_cfg_ctrl);
1064         if (status < 0)
1065                 goto error;
1066         status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1067                          state->m_hi_cfg_wake_up_key);
1068         if (status < 0)
1069                 goto error;
1070         status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1071                          state->m_hi_cfg_bridge_delay);
1072         if (status < 0)
1073                 goto error;
1074         status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1075                          state->m_hi_cfg_timing_div);
1076         if (status < 0)
1077                 goto error;
1078         status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1079                          SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1080         if (status < 0)
1081                 goto error;
1082         status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1083         if (status < 0)
1084                 goto error;
1085
1086         state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1087 error:
1088         mutex_unlock(&state->mutex);
1089         if (status < 0)
1090                 pr_err("Error %d on %s\n", status, __func__);
1091         return status;
1092 }
1093
1094 static int init_hi(struct drxk_state *state)
1095 {
1096         dprintk(1, "\n");
1097
1098         state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1099         state->m_hi_cfg_timeout = 0x96FF;
1100         /* port/bridge/power down ctrl */
1101         state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1102
1103         return hi_cfg_command(state);
1104 }
1105
1106 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1107 {
1108         int status = -1;
1109         u16 sio_pdr_mclk_cfg = 0;
1110         u16 sio_pdr_mdx_cfg = 0;
1111         u16 err_cfg = 0;
1112
1113         dprintk(1, ": mpeg %s, %s mode\n",
1114                 mpeg_enable ? "enable" : "disable",
1115                 state->m_enable_parallel ? "parallel" : "serial");
1116
1117         /* stop lock indicator process */
1118         status = write16(state, SCU_RAM_GPIO__A,
1119                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1120         if (status < 0)
1121                 goto error;
1122
1123         /*  MPEG TS pad configuration */
1124         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1125         if (status < 0)
1126                 goto error;
1127
1128         if (!mpeg_enable) {
1129                 /*  Set MPEG TS pads to inputmode */
1130                 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1131                 if (status < 0)
1132                         goto error;
1133                 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1134                 if (status < 0)
1135                         goto error;
1136                 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1137                 if (status < 0)
1138                         goto error;
1139                 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1140                 if (status < 0)
1141                         goto error;
1142                 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1143                 if (status < 0)
1144                         goto error;
1145                 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1146                 if (status < 0)
1147                         goto error;
1148                 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1149                 if (status < 0)
1150                         goto error;
1151                 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1152                 if (status < 0)
1153                         goto error;
1154                 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1155                 if (status < 0)
1156                         goto error;
1157                 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1158                 if (status < 0)
1159                         goto error;
1160                 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1161                 if (status < 0)
1162                         goto error;
1163                 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1164                 if (status < 0)
1165                         goto error;
1166         } else {
1167                 /* Enable MPEG output */
1168                 sio_pdr_mdx_cfg =
1169                         ((state->m_ts_data_strength <<
1170                         SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1171                 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1172                                         SIO_PDR_MCLK_CFG_DRIVE__B) |
1173                                         0x0003);
1174
1175                 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1176                 if (status < 0)
1177                         goto error;
1178
1179                 if (state->enable_merr_cfg)
1180                         err_cfg = sio_pdr_mdx_cfg;
1181
1182                 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1183                 if (status < 0)
1184                         goto error;
1185                 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1186                 if (status < 0)
1187                         goto error;
1188
1189                 if (state->m_enable_parallel) {
1190                         /* parallel -> enable MD1 to MD7 */
1191                         status = write16(state, SIO_PDR_MD1_CFG__A,
1192                                          sio_pdr_mdx_cfg);
1193                         if (status < 0)
1194                                 goto error;
1195                         status = write16(state, SIO_PDR_MD2_CFG__A,
1196                                          sio_pdr_mdx_cfg);
1197                         if (status < 0)
1198                                 goto error;
1199                         status = write16(state, SIO_PDR_MD3_CFG__A,
1200                                          sio_pdr_mdx_cfg);
1201                         if (status < 0)
1202                                 goto error;
1203                         status = write16(state, SIO_PDR_MD4_CFG__A,
1204                                          sio_pdr_mdx_cfg);
1205                         if (status < 0)
1206                                 goto error;
1207                         status = write16(state, SIO_PDR_MD5_CFG__A,
1208                                          sio_pdr_mdx_cfg);
1209                         if (status < 0)
1210                                 goto error;
1211                         status = write16(state, SIO_PDR_MD6_CFG__A,
1212                                          sio_pdr_mdx_cfg);
1213                         if (status < 0)
1214                                 goto error;
1215                         status = write16(state, SIO_PDR_MD7_CFG__A,
1216                                          sio_pdr_mdx_cfg);
1217                         if (status < 0)
1218                                 goto error;
1219                 } else {
1220                         sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1221                                                 SIO_PDR_MD0_CFG_DRIVE__B)
1222                                         | 0x0003);
1223                         /* serial -> disable MD1 to MD7 */
1224                         status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1225                         if (status < 0)
1226                                 goto error;
1227                         status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1228                         if (status < 0)
1229                                 goto error;
1230                         status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1231                         if (status < 0)
1232                                 goto error;
1233                         status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1234                         if (status < 0)
1235                                 goto error;
1236                         status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1237                         if (status < 0)
1238                                 goto error;
1239                         status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1240                         if (status < 0)
1241                                 goto error;
1242                         status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1243                         if (status < 0)
1244                                 goto error;
1245                 }
1246                 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1247                 if (status < 0)
1248                         goto error;
1249                 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1250                 if (status < 0)
1251                         goto error;
1252         }
1253         /*  Enable MB output over MPEG pads and ctl input */
1254         status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1255         if (status < 0)
1256                 goto error;
1257         /*  Write nomagic word to enable pdr reg write */
1258         status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1259 error:
1260         if (status < 0)
1261                 pr_err("Error %d on %s\n", status, __func__);
1262         return status;
1263 }
1264
1265 static int mpegts_disable(struct drxk_state *state)
1266 {
1267         dprintk(1, "\n");
1268
1269         return mpegts_configure_pins(state, false);
1270 }
1271
1272 static int bl_chain_cmd(struct drxk_state *state,
1273                       u16 rom_offset, u16 nr_of_elements, u32 time_out)
1274 {
1275         u16 bl_status = 0;
1276         int status;
1277         unsigned long end;
1278
1279         dprintk(1, "\n");
1280         mutex_lock(&state->mutex);
1281         status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1282         if (status < 0)
1283                 goto error;
1284         status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1285         if (status < 0)
1286                 goto error;
1287         status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1288         if (status < 0)
1289                 goto error;
1290         status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1291         if (status < 0)
1292                 goto error;
1293
1294         end = jiffies + msecs_to_jiffies(time_out);
1295         do {
1296                 usleep_range(1000, 2000);
1297                 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1298                 if (status < 0)
1299                         goto error;
1300         } while ((bl_status == 0x1) &&
1301                         ((time_is_after_jiffies(end))));
1302
1303         if (bl_status == 0x1) {
1304                 pr_err("SIO not ready\n");
1305                 status = -EINVAL;
1306                 goto error2;
1307         }
1308 error:
1309         if (status < 0)
1310                 pr_err("Error %d on %s\n", status, __func__);
1311 error2:
1312         mutex_unlock(&state->mutex);
1313         return status;
1314 }
1315
1316
1317 static int download_microcode(struct drxk_state *state,
1318                              const u8 p_mc_image[], u32 length)
1319 {
1320         const u8 *p_src = p_mc_image;
1321         u32 address;
1322         u16 n_blocks;
1323         u16 block_size;
1324         u32 offset = 0;
1325         u32 i;
1326         int status = 0;
1327
1328         dprintk(1, "\n");
1329
1330         /* down the drain (we don't care about MAGIC_WORD) */
1331 #if 0
1332         /* For future reference */
1333         drain = (p_src[0] << 8) | p_src[1];
1334 #endif
1335         p_src += sizeof(u16);
1336         offset += sizeof(u16);
1337         n_blocks = (p_src[0] << 8) | p_src[1];
1338         p_src += sizeof(u16);
1339         offset += sizeof(u16);
1340
1341         for (i = 0; i < n_blocks; i += 1) {
1342                 address = (p_src[0] << 24) | (p_src[1] << 16) |
1343                     (p_src[2] << 8) | p_src[3];
1344                 p_src += sizeof(u32);
1345                 offset += sizeof(u32);
1346
1347                 block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
1348                 p_src += sizeof(u16);
1349                 offset += sizeof(u16);
1350
1351 #if 0
1352                 /* For future reference */
1353                 flags = (p_src[0] << 8) | p_src[1];
1354 #endif
1355                 p_src += sizeof(u16);
1356                 offset += sizeof(u16);
1357
1358 #if 0
1359                 /* For future reference */
1360                 block_crc = (p_src[0] << 8) | p_src[1];
1361 #endif
1362                 p_src += sizeof(u16);
1363                 offset += sizeof(u16);
1364
1365                 if (offset + block_size > length) {
1366                         pr_err("Firmware is corrupted.\n");
1367                         return -EINVAL;
1368                 }
1369
1370                 status = write_block(state, address, block_size, p_src);
1371                 if (status < 0) {
1372                         pr_err("Error %d while loading firmware\n", status);
1373                         break;
1374                 }
1375                 p_src += block_size;
1376                 offset += block_size;
1377         }
1378         return status;
1379 }
1380
1381 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1382 {
1383         int status;
1384         u16 data = 0;
1385         u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1386         u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1387         unsigned long end;
1388
1389         dprintk(1, "\n");
1390
1391         if (!enable) {
1392                 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1393                 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1394         }
1395
1396         status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1397         if (status >= 0 && data == desired_status) {
1398                 /* tokenring already has correct status */
1399                 return status;
1400         }
1401         /* Disable/enable dvbt tokenring bridge   */
1402         status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1403
1404         end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1405         do {
1406                 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1407                 if ((status >= 0 && data == desired_status)
1408                     || time_is_after_jiffies(end))
1409                         break;
1410                 usleep_range(1000, 2000);
1411         } while (1);
1412         if (data != desired_status) {
1413                 pr_err("SIO not ready\n");
1414                 return -EINVAL;
1415         }
1416         return status;
1417 }
1418
1419 static int mpegts_stop(struct drxk_state *state)
1420 {
1421         int status = 0;
1422         u16 fec_oc_snc_mode = 0;
1423         u16 fec_oc_ipr_mode = 0;
1424
1425         dprintk(1, "\n");
1426
1427         /* Graceful shutdown (byte boundaries) */
1428         status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1429         if (status < 0)
1430                 goto error;
1431         fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1432         status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1433         if (status < 0)
1434                 goto error;
1435
1436         /* Suppress MCLK during absence of data */
1437         status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1438         if (status < 0)
1439                 goto error;
1440         fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1441         status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1442
1443 error:
1444         if (status < 0)
1445                 pr_err("Error %d on %s\n", status, __func__);
1446
1447         return status;
1448 }
1449
1450 static int scu_command(struct drxk_state *state,
1451                        u16 cmd, u8 parameter_len,
1452                        u16 *parameter, u8 result_len, u16 *result)
1453 {
1454 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1455 #error DRXK register mapping no longer compatible with this routine!
1456 #endif
1457         u16 cur_cmd = 0;
1458         int status = -EINVAL;
1459         unsigned long end;
1460         u8 buffer[34];
1461         int cnt = 0, ii;
1462         const char *p;
1463         char errname[30];
1464
1465         dprintk(1, "\n");
1466
1467         if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
1468             ((result_len > 0) && (result == NULL))) {
1469                 pr_err("Error %d on %s\n", status, __func__);
1470                 return status;
1471         }
1472
1473         mutex_lock(&state->mutex);
1474
1475         /* assume that the command register is ready
1476                 since it is checked afterwards */
1477         if (parameter) {
1478                 for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
1479                         buffer[cnt++] = (parameter[ii] & 0xFF);
1480                         buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1481                 }
1482         }
1483         buffer[cnt++] = (cmd & 0xFF);
1484         buffer[cnt++] = ((cmd >> 8) & 0xFF);
1485
1486         write_block(state, SCU_RAM_PARAM_0__A -
1487                         (parameter_len - 1), cnt, buffer);
1488         /* Wait until SCU has processed command */
1489         end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1490         do {
1491                 usleep_range(1000, 2000);
1492                 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1493                 if (status < 0)
1494                         goto error;
1495         } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1496         if (cur_cmd != DRX_SCU_READY) {
1497                 pr_err("SCU not ready\n");
1498                 status = -EIO;
1499                 goto error2;
1500         }
1501         /* read results */
1502         if ((result_len > 0) && (result != NULL)) {
1503                 s16 err;
1504                 int ii;
1505
1506                 for (ii = result_len - 1; ii >= 0; ii -= 1) {
1507                         status = read16(state, SCU_RAM_PARAM_0__A - ii,
1508                                         &result[ii]);
1509                         if (status < 0)
1510                                 goto error;
1511                 }
1512
1513                 /* Check if an error was reported by SCU */
1514                 err = (s16)result[0];
1515                 if (err >= 0)
1516                         goto error;
1517
1518                 /* check for the known error codes */
1519                 switch (err) {
1520                 case SCU_RESULT_UNKCMD:
1521                         p = "SCU_RESULT_UNKCMD";
1522                         break;
1523                 case SCU_RESULT_UNKSTD:
1524                         p = "SCU_RESULT_UNKSTD";
1525                         break;
1526                 case SCU_RESULT_SIZE:
1527                         p = "SCU_RESULT_SIZE";
1528                         break;
1529                 case SCU_RESULT_INVPAR:
1530                         p = "SCU_RESULT_INVPAR";
1531                         break;
1532                 default: /* Other negative values are errors */
1533                         sprintf(errname, "ERROR: %d\n", err);
1534                         p = errname;
1535                 }
1536                 pr_err("%s while sending cmd 0x%04x with params:", p, cmd);
1537                 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1538                 status = -EINVAL;
1539                 goto error2;
1540         }
1541
1542 error:
1543         if (status < 0)
1544                 pr_err("Error %d on %s\n", status, __func__);
1545 error2:
1546         mutex_unlock(&state->mutex);
1547         return status;
1548 }
1549
1550 static int set_iqm_af(struct drxk_state *state, bool active)
1551 {
1552         u16 data = 0;
1553         int status;
1554
1555         dprintk(1, "\n");
1556
1557         /* Configure IQM */
1558         status = read16(state, IQM_AF_STDBY__A, &data);
1559         if (status < 0)
1560                 goto error;
1561
1562         if (!active) {
1563                 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1564                                 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1565                                 | IQM_AF_STDBY_STDBY_PD_STANDBY
1566                                 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1567                                 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1568         } else {
1569                 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1570                                 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1571                                 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1572                                 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1573                                 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1574                         );
1575         }
1576         status = write16(state, IQM_AF_STDBY__A, data);
1577
1578 error:
1579         if (status < 0)
1580                 pr_err("Error %d on %s\n", status, __func__);
1581         return status;
1582 }
1583
1584 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1585 {
1586         int status = 0;
1587         u16 sio_cc_pwd_mode = 0;
1588
1589         dprintk(1, "\n");
1590
1591         /* Check arguments */
1592         if (mode == NULL)
1593                 return -EINVAL;
1594
1595         switch (*mode) {
1596         case DRX_POWER_UP:
1597                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
1598                 break;
1599         case DRXK_POWER_DOWN_OFDM:
1600                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1601                 break;
1602         case DRXK_POWER_DOWN_CORE:
1603                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1604                 break;
1605         case DRXK_POWER_DOWN_PLL:
1606                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
1607                 break;
1608         case DRX_POWER_DOWN:
1609                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
1610                 break;
1611         default:
1612                 /* Unknow sleep mode */
1613                 return -EINVAL;
1614         }
1615
1616         /* If already in requested power mode, do nothing */
1617         if (state->m_current_power_mode == *mode)
1618                 return 0;
1619
1620         /* For next steps make sure to start from DRX_POWER_UP mode */
1621         if (state->m_current_power_mode != DRX_POWER_UP) {
1622                 status = power_up_device(state);
1623                 if (status < 0)
1624                         goto error;
1625                 status = dvbt_enable_ofdm_token_ring(state, true);
1626                 if (status < 0)
1627                         goto error;
1628         }
1629
1630         if (*mode == DRX_POWER_UP) {
1631                 /* Restore analog & pin configuration */
1632         } else {
1633                 /* Power down to requested mode */
1634                 /* Backup some register settings */
1635                 /* Set pins with possible pull-ups connected
1636                    to them in input mode */
1637                 /* Analog power down */
1638                 /* ADC power down */
1639                 /* Power down device */
1640                 /* stop all comm_exec */
1641                 /* Stop and power down previous standard */
1642                 switch (state->m_operation_mode) {
1643                 case OM_DVBT:
1644                         status = mpegts_stop(state);
1645                         if (status < 0)
1646                                 goto error;
1647                         status = power_down_dvbt(state, false);
1648                         if (status < 0)
1649                                 goto error;
1650                         break;
1651                 case OM_QAM_ITU_A:
1652                 case OM_QAM_ITU_C:
1653                         status = mpegts_stop(state);
1654                         if (status < 0)
1655                                 goto error;
1656                         status = power_down_qam(state);
1657                         if (status < 0)
1658                                 goto error;
1659                         break;
1660                 default:
1661                         break;
1662                 }
1663                 status = dvbt_enable_ofdm_token_ring(state, false);
1664                 if (status < 0)
1665                         goto error;
1666                 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1667                 if (status < 0)
1668                         goto error;
1669                 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1670                 if (status < 0)
1671                         goto error;
1672
1673                 if (*mode != DRXK_POWER_DOWN_OFDM) {
1674                         state->m_hi_cfg_ctrl |=
1675                                 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1676                         status = hi_cfg_command(state);
1677                         if (status < 0)
1678                                 goto error;
1679                 }
1680         }
1681         state->m_current_power_mode = *mode;
1682
1683 error:
1684         if (status < 0)
1685                 pr_err("Error %d on %s\n", status, __func__);
1686
1687         return status;
1688 }
1689
1690 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1691 {
1692         enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
1693         u16 cmd_result = 0;
1694         u16 data = 0;
1695         int status;
1696
1697         dprintk(1, "\n");
1698
1699         status = read16(state, SCU_COMM_EXEC__A, &data);
1700         if (status < 0)
1701                 goto error;
1702         if (data == SCU_COMM_EXEC_ACTIVE) {
1703                 /* Send OFDM stop command */
1704                 status = scu_command(state,
1705                                      SCU_RAM_COMMAND_STANDARD_OFDM
1706                                      | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
1707                                      0, NULL, 1, &cmd_result);
1708                 if (status < 0)
1709                         goto error;
1710                 /* Send OFDM reset command */
1711                 status = scu_command(state,
1712                                      SCU_RAM_COMMAND_STANDARD_OFDM
1713                                      | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
1714                                      0, NULL, 1, &cmd_result);
1715                 if (status < 0)
1716                         goto error;
1717         }
1718
1719         /* Reset datapath for OFDM, processors first */
1720         status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1721         if (status < 0)
1722                 goto error;
1723         status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1724         if (status < 0)
1725                 goto error;
1726         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1727         if (status < 0)
1728                 goto error;
1729
1730         /* powerdown AFE                   */
1731         status = set_iqm_af(state, false);
1732         if (status < 0)
1733                 goto error;
1734
1735         /* powerdown to OFDM mode          */
1736         if (set_power_mode) {
1737                 status = ctrl_power_mode(state, &power_mode);
1738                 if (status < 0)
1739                         goto error;
1740         }
1741 error:
1742         if (status < 0)
1743                 pr_err("Error %d on %s\n", status, __func__);
1744         return status;
1745 }
1746
1747 static int setoperation_mode(struct drxk_state *state,
1748                             enum operation_mode o_mode)
1749 {
1750         int status = 0;
1751
1752         dprintk(1, "\n");
1753         /*
1754            Stop and power down previous standard
1755            TODO investigate total power down instead of partial
1756            power down depending on "previous" standard.
1757          */
1758
1759         /* disable HW lock indicator */
1760         status = write16(state, SCU_RAM_GPIO__A,
1761                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1762         if (status < 0)
1763                 goto error;
1764
1765         /* Device is already at the required mode */
1766         if (state->m_operation_mode == o_mode)
1767                 return 0;
1768
1769         switch (state->m_operation_mode) {
1770                 /* OM_NONE was added for start up */
1771         case OM_NONE:
1772                 break;
1773         case OM_DVBT:
1774                 status = mpegts_stop(state);
1775                 if (status < 0)
1776                         goto error;
1777                 status = power_down_dvbt(state, true);
1778                 if (status < 0)
1779                         goto error;
1780                 state->m_operation_mode = OM_NONE;
1781                 break;
1782         case OM_QAM_ITU_A:      /* fallthrough */
1783         case OM_QAM_ITU_C:
1784                 status = mpegts_stop(state);
1785                 if (status < 0)
1786                         goto error;
1787                 status = power_down_qam(state);
1788                 if (status < 0)
1789                         goto error;
1790                 state->m_operation_mode = OM_NONE;
1791                 break;
1792         case OM_QAM_ITU_B:
1793         default:
1794                 status = -EINVAL;
1795                 goto error;
1796         }
1797
1798         /*
1799                 Power up new standard
1800                 */
1801         switch (o_mode) {
1802         case OM_DVBT:
1803                 dprintk(1, ": DVB-T\n");
1804                 state->m_operation_mode = o_mode;
1805                 status = set_dvbt_standard(state, o_mode);
1806                 if (status < 0)
1807                         goto error;
1808                 break;
1809         case OM_QAM_ITU_A:      /* fallthrough */
1810         case OM_QAM_ITU_C:
1811                 dprintk(1, ": DVB-C Annex %c\n",
1812                         (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1813                 state->m_operation_mode = o_mode;
1814                 status = set_qam_standard(state, o_mode);
1815                 if (status < 0)
1816                         goto error;
1817                 break;
1818         case OM_QAM_ITU_B:
1819         default:
1820                 status = -EINVAL;
1821         }
1822 error:
1823         if (status < 0)
1824                 pr_err("Error %d on %s\n", status, __func__);
1825         return status;
1826 }
1827
1828 static int start(struct drxk_state *state, s32 offset_freq,
1829                  s32 intermediate_frequency)
1830 {
1831         int status = -EINVAL;
1832
1833         u16 i_freqk_hz;
1834         s32 offsetk_hz = offset_freq / 1000;
1835
1836         dprintk(1, "\n");
1837         if (state->m_drxk_state != DRXK_STOPPED &&
1838                 state->m_drxk_state != DRXK_DTV_STARTED)
1839                 goto error;
1840
1841         state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1842
1843         if (intermediate_frequency < 0) {
1844                 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1845                 intermediate_frequency = -intermediate_frequency;
1846         }
1847
1848         switch (state->m_operation_mode) {
1849         case OM_QAM_ITU_A:
1850         case OM_QAM_ITU_C:
1851                 i_freqk_hz = (intermediate_frequency / 1000);
1852                 status = set_qam(state, i_freqk_hz, offsetk_hz);
1853                 if (status < 0)
1854                         goto error;
1855                 state->m_drxk_state = DRXK_DTV_STARTED;
1856                 break;
1857         case OM_DVBT:
1858                 i_freqk_hz = (intermediate_frequency / 1000);
1859                 status = mpegts_stop(state);
1860                 if (status < 0)
1861                         goto error;
1862                 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1863                 if (status < 0)
1864                         goto error;
1865                 status = dvbt_start(state);
1866                 if (status < 0)
1867                         goto error;
1868                 state->m_drxk_state = DRXK_DTV_STARTED;
1869                 break;
1870         default:
1871                 break;
1872         }
1873 error:
1874         if (status < 0)
1875                 pr_err("Error %d on %s\n", status, __func__);
1876         return status;
1877 }
1878
1879 static int shut_down(struct drxk_state *state)
1880 {
1881         dprintk(1, "\n");
1882
1883         mpegts_stop(state);
1884         return 0;
1885 }
1886
1887 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1888 {
1889         int status = -EINVAL;
1890
1891         dprintk(1, "\n");
1892
1893         if (p_lock_status == NULL)
1894                 goto error;
1895
1896         *p_lock_status = NOT_LOCKED;
1897
1898         /* define the SCU command code */
1899         switch (state->m_operation_mode) {
1900         case OM_QAM_ITU_A:
1901         case OM_QAM_ITU_B:
1902         case OM_QAM_ITU_C:
1903                 status = get_qam_lock_status(state, p_lock_status);
1904                 break;
1905         case OM_DVBT:
1906                 status = get_dvbt_lock_status(state, p_lock_status);
1907                 break;
1908         default:
1909                 pr_debug("Unsupported operation mode %d in %s\n",
1910                         state->m_operation_mode, __func__);
1911                 return 0;
1912         }
1913 error:
1914         if (status < 0)
1915                 pr_err("Error %d on %s\n", status, __func__);
1916         return status;
1917 }
1918
1919 static int mpegts_start(struct drxk_state *state)
1920 {
1921         int status;
1922
1923         u16 fec_oc_snc_mode = 0;
1924
1925         /* Allow OC to sync again */
1926         status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1927         if (status < 0)
1928                 goto error;
1929         fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1930         status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1931         if (status < 0)
1932                 goto error;
1933         status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1934 error:
1935         if (status < 0)
1936                 pr_err("Error %d on %s\n", status, __func__);
1937         return status;
1938 }
1939
1940 static int mpegts_dto_init(struct drxk_state *state)
1941 {
1942         int status;
1943
1944         dprintk(1, "\n");
1945
1946         /* Rate integration settings */
1947         status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1948         if (status < 0)
1949                 goto error;
1950         status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1951         if (status < 0)
1952                 goto error;
1953         status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1954         if (status < 0)
1955                 goto error;
1956         status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1957         if (status < 0)
1958                 goto error;
1959         status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1960         if (status < 0)
1961                 goto error;
1962         status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1963         if (status < 0)
1964                 goto error;
1965         status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1966         if (status < 0)
1967                 goto error;
1968         status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1969         if (status < 0)
1970                 goto error;
1971
1972         /* Additional configuration */
1973         status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1974         if (status < 0)
1975                 goto error;
1976         status = write16(state, FEC_OC_SNC_LWM__A, 2);
1977         if (status < 0)
1978                 goto error;
1979         status = write16(state, FEC_OC_SNC_HWM__A, 12);
1980 error:
1981         if (status < 0)
1982                 pr_err("Error %d on %s\n", status, __func__);
1983
1984         return status;
1985 }
1986
1987 static int mpegts_dto_setup(struct drxk_state *state,
1988                           enum operation_mode o_mode)
1989 {
1990         int status;
1991
1992         u16 fec_oc_reg_mode = 0;        /* FEC_OC_MODE       register value */
1993         u16 fec_oc_reg_ipr_mode = 0;    /* FEC_OC_IPR_MODE   register value */
1994         u16 fec_oc_dto_mode = 0;        /* FEC_OC_IPR_INVERT register value */
1995         u16 fec_oc_fct_mode = 0;        /* FEC_OC_IPR_INVERT register value */
1996         u16 fec_oc_dto_period = 2;      /* FEC_OC_IPR_INVERT register value */
1997         u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */
1998         u32 fec_oc_rcn_ctl_rate = 0;    /* FEC_OC_IPR_INVERT register value */
1999         u16 fec_oc_tmd_mode = 0;
2000         u16 fec_oc_tmd_int_upd_rate = 0;
2001         u32 max_bit_rate = 0;
2002         bool static_clk = false;
2003
2004         dprintk(1, "\n");
2005
2006         /* Check insertion of the Reed-Solomon parity bytes */
2007         status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
2008         if (status < 0)
2009                 goto error;
2010         status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
2011         if (status < 0)
2012                 goto error;
2013         fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
2014         fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2015         if (state->m_insert_rs_byte) {
2016                 /* enable parity symbol forward */
2017                 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
2018                 /* MVAL disable during parity bytes */
2019                 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2020                 /* TS burst length to 204 */
2021                 fec_oc_dto_burst_len = 204;
2022         }
2023
2024         /* Check serial or parallel output */
2025         fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2026         if (!state->m_enable_parallel) {
2027                 /* MPEG data output is serial -> set ipr_mode[0] */
2028                 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2029         }
2030
2031         switch (o_mode) {
2032         case OM_DVBT:
2033                 max_bit_rate = state->m_dvbt_bitrate;
2034                 fec_oc_tmd_mode = 3;
2035                 fec_oc_rcn_ctl_rate = 0xC00000;
2036                 static_clk = state->m_dvbt_static_clk;
2037                 break;
2038         case OM_QAM_ITU_A:      /* fallthrough */
2039         case OM_QAM_ITU_C:
2040                 fec_oc_tmd_mode = 0x0004;
2041                 fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */
2042                 max_bit_rate = state->m_dvbc_bitrate;
2043                 static_clk = state->m_dvbc_static_clk;
2044                 break;
2045         default:
2046                 status = -EINVAL;
2047         }               /* switch (standard) */
2048         if (status < 0)
2049                 goto error;
2050
2051         /* Configure DTO's */
2052         if (static_clk) {
2053                 u32 bit_rate = 0;
2054
2055                 /* Rational DTO for MCLK source (static MCLK rate),
2056                         Dynamic DTO for optimal grouping
2057                         (avoid intra-packet gaps),
2058                         DTO offset enable to sync TS burst with MSTRT */
2059                 fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2060                                 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2061                 fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2062                                 FEC_OC_FCT_MODE_VIRT_ENA__M);
2063
2064                 /* Check user defined bitrate */
2065                 bit_rate = max_bit_rate;
2066                 if (bit_rate > 75900000UL) {    /* max is 75.9 Mb/s */
2067                         bit_rate = 75900000UL;
2068                 }
2069                 /* Rational DTO period:
2070                         dto_period = (Fsys / bitrate) - 2
2071
2072                         result should be floored,
2073                         to make sure >= requested bitrate
2074                         */
2075                 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2076                                                 * 1000) / bit_rate);
2077                 if (fec_oc_dto_period <= 2)
2078                         fec_oc_dto_period = 0;
2079                 else
2080                         fec_oc_dto_period -= 2;
2081                 fec_oc_tmd_int_upd_rate = 8;
2082         } else {
2083                 /* (commonAttr->static_clk == false) => dynamic mode */
2084                 fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
2085                 fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
2086                 fec_oc_tmd_int_upd_rate = 5;
2087         }
2088
2089         /* Write appropriate registers with requested configuration */
2090         status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2091         if (status < 0)
2092                 goto error;
2093         status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2094         if (status < 0)
2095                 goto error;
2096         status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2097         if (status < 0)
2098                 goto error;
2099         status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2100         if (status < 0)
2101                 goto error;
2102         status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2103         if (status < 0)
2104                 goto error;
2105         status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2106         if (status < 0)
2107                 goto error;
2108
2109         /* Rate integration settings */
2110         status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2111         if (status < 0)
2112                 goto error;
2113         status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2114                          fec_oc_tmd_int_upd_rate);
2115         if (status < 0)
2116                 goto error;
2117         status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2118 error:
2119         if (status < 0)
2120                 pr_err("Error %d on %s\n", status, __func__);
2121         return status;
2122 }
2123
2124 static int mpegts_configure_polarity(struct drxk_state *state)
2125 {
2126         u16 fec_oc_reg_ipr_invert = 0;
2127
2128         /* Data mask for the output data byte */
2129         u16 invert_data_mask =
2130             FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2131             FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2132             FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2133             FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2134
2135         dprintk(1, "\n");
2136
2137         /* Control selective inversion of output bits */
2138         fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2139         if (state->m_invert_data)
2140                 fec_oc_reg_ipr_invert |= invert_data_mask;
2141         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2142         if (state->m_invert_err)
2143                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2144         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2145         if (state->m_invert_str)
2146                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2147         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2148         if (state->m_invert_val)
2149                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2150         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2151         if (state->m_invert_clk)
2152                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
2153
2154         return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
2155 }
2156
2157 #define   SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2158
2159 static int set_agc_rf(struct drxk_state *state,
2160                     struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2161 {
2162         int status = -EINVAL;
2163         u16 data = 0;
2164         struct s_cfg_agc *p_if_agc_settings;
2165
2166         dprintk(1, "\n");
2167
2168         if (p_agc_cfg == NULL)
2169                 goto error;
2170
2171         switch (p_agc_cfg->ctrl_mode) {
2172         case DRXK_AGC_CTRL_AUTO:
2173                 /* Enable RF AGC DAC */
2174                 status = read16(state, IQM_AF_STDBY__A, &data);
2175                 if (status < 0)
2176                         goto error;
2177                 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2178                 status = write16(state, IQM_AF_STDBY__A, data);
2179                 if (status < 0)
2180                         goto error;
2181                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2182                 if (status < 0)
2183                         goto error;
2184
2185                 /* Enable SCU RF AGC loop */
2186                 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2187
2188                 /* Polarity */
2189                 if (state->m_rf_agc_pol)
2190                         data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2191                 else
2192                         data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2193                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2194                 if (status < 0)
2195                         goto error;
2196
2197                 /* Set speed (using complementary reduction value) */
2198                 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2199                 if (status < 0)
2200                         goto error;
2201
2202                 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2203                 data |= (~(p_agc_cfg->speed <<
2204                                 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2205                                 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2206
2207                 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2208                 if (status < 0)
2209                         goto error;
2210
2211                 if (is_dvbt(state))
2212                         p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2213                 else if (is_qam(state))
2214                         p_if_agc_settings = &state->m_qam_if_agc_cfg;
2215                 else
2216                         p_if_agc_settings = &state->m_atv_if_agc_cfg;
2217                 if (p_if_agc_settings == NULL) {
2218                         status = -EINVAL;
2219                         goto error;
2220                 }
2221
2222                 /* Set TOP, only if IF-AGC is in AUTO mode */
2223                 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) {
2224                         status = write16(state,
2225                                          SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2226                                          p_agc_cfg->top);
2227                         if (status < 0)
2228                                 goto error;
2229                 }
2230
2231                 /* Cut-Off current */
2232                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2233                                  p_agc_cfg->cut_off_current);
2234                 if (status < 0)
2235                         goto error;
2236
2237                 /* Max. output level */
2238                 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2239                                  p_agc_cfg->max_output_level);
2240                 if (status < 0)
2241                         goto error;
2242
2243                 break;
2244
2245         case DRXK_AGC_CTRL_USER:
2246                 /* Enable RF AGC DAC */
2247                 status = read16(state, IQM_AF_STDBY__A, &data);
2248                 if (status < 0)
2249                         goto error;
2250                 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2251                 status = write16(state, IQM_AF_STDBY__A, data);
2252                 if (status < 0)
2253                         goto error;
2254
2255                 /* Disable SCU RF AGC loop */
2256                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2257                 if (status < 0)
2258                         goto error;
2259                 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2260                 if (state->m_rf_agc_pol)
2261                         data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2262                 else
2263                         data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2264                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2265                 if (status < 0)
2266                         goto error;
2267
2268                 /* SCU c.o.c. to 0, enabling full control range */
2269                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2270                 if (status < 0)
2271                         goto error;
2272
2273                 /* Write value to output pin */
2274                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2275                                  p_agc_cfg->output_level);
2276                 if (status < 0)
2277                         goto error;
2278                 break;
2279
2280         case DRXK_AGC_CTRL_OFF:
2281                 /* Disable RF AGC DAC */
2282                 status = read16(state, IQM_AF_STDBY__A, &data);
2283                 if (status < 0)
2284                         goto error;
2285                 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2286                 status = write16(state, IQM_AF_STDBY__A, data);
2287                 if (status < 0)
2288                         goto error;
2289
2290                 /* Disable SCU RF AGC loop */
2291                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2292                 if (status < 0)
2293                         goto error;
2294                 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2295                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2296                 if (status < 0)
2297                         goto error;
2298                 break;
2299
2300         default:
2301                 status = -EINVAL;
2302
2303         }
2304 error:
2305         if (status < 0)
2306                 pr_err("Error %d on %s\n", status, __func__);
2307         return status;
2308 }
2309
2310 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2311
2312 static int set_agc_if(struct drxk_state *state,
2313                     struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2314 {
2315         u16 data = 0;
2316         int status = 0;
2317         struct s_cfg_agc *p_rf_agc_settings;
2318
2319         dprintk(1, "\n");
2320
2321         switch (p_agc_cfg->ctrl_mode) {
2322         case DRXK_AGC_CTRL_AUTO:
2323
2324                 /* Enable IF AGC DAC */
2325                 status = read16(state, IQM_AF_STDBY__A, &data);
2326                 if (status < 0)
2327                         goto error;
2328                 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2329                 status = write16(state, IQM_AF_STDBY__A, data);
2330                 if (status < 0)
2331                         goto error;
2332
2333                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2334                 if (status < 0)
2335                         goto error;
2336
2337                 /* Enable SCU IF AGC loop */
2338                 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2339
2340                 /* Polarity */
2341                 if (state->m_if_agc_pol)
2342                         data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2343                 else
2344                         data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2345                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2346                 if (status < 0)
2347                         goto error;
2348
2349                 /* Set speed (using complementary reduction value) */
2350                 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2351                 if (status < 0)
2352                         goto error;
2353                 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2354                 data |= (~(p_agc_cfg->speed <<
2355                                 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2356                                 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2357
2358                 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2359                 if (status < 0)
2360                         goto error;
2361
2362                 if (is_qam(state))
2363                         p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2364                 else
2365                         p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2366                 if (p_rf_agc_settings == NULL)
2367                         return -1;
2368                 /* Restore TOP */
2369                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2370                                  p_rf_agc_settings->top);
2371                 if (status < 0)
2372                         goto error;
2373                 break;
2374
2375         case DRXK_AGC_CTRL_USER:
2376
2377                 /* Enable IF AGC DAC */
2378                 status = read16(state, IQM_AF_STDBY__A, &data);
2379                 if (status < 0)
2380                         goto error;
2381                 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2382                 status = write16(state, IQM_AF_STDBY__A, data);
2383                 if (status < 0)
2384                         goto error;
2385
2386                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2387                 if (status < 0)
2388                         goto error;
2389
2390                 /* Disable SCU IF AGC loop */
2391                 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2392
2393                 /* Polarity */
2394                 if (state->m_if_agc_pol)
2395                         data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2396                 else
2397                         data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2398                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2399                 if (status < 0)
2400                         goto error;
2401
2402                 /* Write value to output pin */
2403                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2404                                  p_agc_cfg->output_level);
2405                 if (status < 0)
2406                         goto error;
2407                 break;
2408
2409         case DRXK_AGC_CTRL_OFF:
2410
2411                 /* Disable If AGC DAC */
2412                 status = read16(state, IQM_AF_STDBY__A, &data);
2413                 if (status < 0)
2414                         goto error;
2415                 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2416                 status = write16(state, IQM_AF_STDBY__A, data);
2417                 if (status < 0)
2418                         goto error;
2419
2420                 /* Disable SCU IF AGC loop */
2421                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2422                 if (status < 0)
2423                         goto error;
2424                 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2425                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2426                 if (status < 0)
2427                         goto error;
2428                 break;
2429         }               /* switch (agcSettingsIf->ctrl_mode) */
2430
2431         /* always set the top to support
2432                 configurations without if-loop */
2433         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2434 error:
2435         if (status < 0)
2436                 pr_err("Error %d on %s\n", status, __func__);
2437         return status;
2438 }
2439
2440 static int get_qam_signal_to_noise(struct drxk_state *state,
2441                                s32 *p_signal_to_noise)
2442 {
2443         int status = 0;
2444         u16 qam_sl_err_power = 0;       /* accum. error between
2445                                         raw and sliced symbols */
2446         u32 qam_sl_sig_power = 0;       /* used for MER, depends of
2447                                         QAM modulation */
2448         u32 qam_sl_mer = 0;     /* QAM MER */
2449
2450         dprintk(1, "\n");
2451
2452         /* MER calculation */
2453
2454         /* get the register value needed for MER */
2455         status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2456         if (status < 0) {
2457                 pr_err("Error %d on %s\n", status, __func__);
2458                 return -EINVAL;
2459         }
2460
2461         switch (state->props.modulation) {
2462         case QAM_16:
2463                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2464                 break;
2465         case QAM_32:
2466                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2467                 break;
2468         case QAM_64:
2469                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2470                 break;
2471         case QAM_128:
2472                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2473                 break;
2474         default:
2475         case QAM_256:
2476                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2477                 break;
2478         }
2479
2480         if (qam_sl_err_power > 0) {
2481                 qam_sl_mer = log10times100(qam_sl_sig_power) -
2482                         log10times100((u32) qam_sl_err_power);
2483         }
2484         *p_signal_to_noise = qam_sl_mer;
2485
2486         return status;
2487 }
2488
2489 static int get_dvbt_signal_to_noise(struct drxk_state *state,
2490                                 s32 *p_signal_to_noise)
2491 {
2492         int status;
2493         u16 reg_data = 0;
2494         u32 eq_reg_td_sqr_err_i = 0;
2495         u32 eq_reg_td_sqr_err_q = 0;
2496         u16 eq_reg_td_sqr_err_exp = 0;
2497         u16 eq_reg_td_tps_pwr_ofs = 0;
2498         u16 eq_reg_td_req_smb_cnt = 0;
2499         u32 tps_cnt = 0;
2500         u32 sqr_err_iq = 0;
2501         u32 a = 0;
2502         u32 b = 0;
2503         u32 c = 0;
2504         u32 i_mer = 0;
2505         u16 transmission_params = 0;
2506
2507         dprintk(1, "\n");
2508
2509         status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2510                         &eq_reg_td_tps_pwr_ofs);
2511         if (status < 0)
2512                 goto error;
2513         status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2514                         &eq_reg_td_req_smb_cnt);
2515         if (status < 0)
2516                 goto error;
2517         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2518                         &eq_reg_td_sqr_err_exp);
2519         if (status < 0)
2520                 goto error;
2521         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2522                         &reg_data);
2523         if (status < 0)
2524                 goto error;
2525         /* Extend SQR_ERR_I operational range */
2526         eq_reg_td_sqr_err_i = (u32) reg_data;
2527         if ((eq_reg_td_sqr_err_exp > 11) &&
2528                 (eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
2529                 eq_reg_td_sqr_err_i += 0x00010000UL;
2530         }
2531         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);
2532         if (status < 0)
2533                 goto error;
2534         /* Extend SQR_ERR_Q operational range */
2535         eq_reg_td_sqr_err_q = (u32) reg_data;
2536         if ((eq_reg_td_sqr_err_exp > 11) &&
2537                 (eq_reg_td_sqr_err_q < 0x00000FFFUL))
2538                 eq_reg_td_sqr_err_q += 0x00010000UL;
2539
2540         status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2541                         &transmission_params);
2542         if (status < 0)
2543                 goto error;
2544
2545         /* Check input data for MER */
2546
2547         /* MER calculation (in 0.1 dB) without math.h */
2548         if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
2549                 i_mer = 0;
2550         else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
2551                 /* No error at all, this must be the HW reset value
2552                         * Apparently no first measurement yet
2553                         * Set MER to 0.0 */
2554                 i_mer = 0;
2555         } else {
2556                 sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
2557                         eq_reg_td_sqr_err_exp;
2558                 if ((transmission_params &
2559                         OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2560                         == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2561                         tps_cnt = 17;
2562                 else
2563                         tps_cnt = 68;
2564
2565                 /* IMER = 100 * log10 (x)
2566                         where x = (eq_reg_td_tps_pwr_ofs^2 *
2567                         eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq
2568
2569                         => IMER = a + b -c
2570                         where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2)
2571                         b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt)
2572                         c = 100 * log10 (sqr_err_iq)
2573                         */
2574
2575                 /* log(x) x = 9bits * 9bits->18 bits  */
2576                 a = log10times100(eq_reg_td_tps_pwr_ofs *
2577                                         eq_reg_td_tps_pwr_ofs);
2578                 /* log(x) x = 16bits * 7bits->23 bits  */
2579                 b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt);
2580                 /* log(x) x = (16bits + 16bits) << 15 ->32 bits  */
2581                 c = log10times100(sqr_err_iq);
2582
2583                 i_mer = a + b - c;
2584         }
2585         *p_signal_to_noise = i_mer;
2586
2587 error:
2588         if (status < 0)
2589                 pr_err("Error %d on %s\n", status, __func__);
2590         return status;
2591 }
2592
2593 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2594 {
2595         dprintk(1, "\n");
2596
2597         *p_signal_to_noise = 0;
2598         switch (state->m_operation_mode) {
2599         case OM_DVBT:
2600                 return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2601         case OM_QAM_ITU_A:
2602         case OM_QAM_ITU_C:
2603                 return get_qam_signal_to_noise(state, p_signal_to_noise);
2604         default:
2605                 break;
2606         }
2607         return 0;
2608 }
2609
2610 #if 0
2611 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2612 {
2613         /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2614         int status = 0;
2615
2616         dprintk(1, "\n");
2617
2618         static s32 QE_SN[] = {
2619                 51,             /* QPSK 1/2 */
2620                 69,             /* QPSK 2/3 */
2621                 79,             /* QPSK 3/4 */
2622                 89,             /* QPSK 5/6 */
2623                 97,             /* QPSK 7/8 */
2624                 108,            /* 16-QAM 1/2 */
2625                 131,            /* 16-QAM 2/3 */
2626                 146,            /* 16-QAM 3/4 */
2627                 156,            /* 16-QAM 5/6 */
2628                 160,            /* 16-QAM 7/8 */
2629                 165,            /* 64-QAM 1/2 */
2630                 187,            /* 64-QAM 2/3 */
2631                 202,            /* 64-QAM 3/4 */
2632                 216,            /* 64-QAM 5/6 */
2633                 225,            /* 64-QAM 7/8 */
2634         };
2635
2636         *p_quality = 0;
2637
2638         do {
2639                 s32 signal_to_noise = 0;
2640                 u16 constellation = 0;
2641                 u16 code_rate = 0;
2642                 u32 signal_to_noise_rel;
2643                 u32 ber_quality;
2644
2645                 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2646                 if (status < 0)
2647                         break;
2648                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2649                                 &constellation);
2650                 if (status < 0)
2651                         break;
2652                 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2653
2654                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2655                                 &code_rate);
2656                 if (status < 0)
2657                         break;
2658                 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2659
2660                 if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2661                     code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2662                         break;
2663                 signal_to_noise_rel = signal_to_noise -
2664                     QE_SN[constellation * 5 + code_rate];
2665                 ber_quality = 100;
2666
2667                 if (signal_to_noise_rel < -70)
2668                         *p_quality = 0;
2669                 else if (signal_to_noise_rel < 30)
2670                         *p_quality = ((signal_to_noise_rel + 70) *
2671                                      ber_quality) / 100;
2672                 else
2673                         *p_quality = ber_quality;
2674         } while (0);
2675         return 0;
2676 };
2677
2678 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2679 {
2680         int status = 0;
2681         *p_quality = 0;
2682
2683         dprintk(1, "\n");
2684
2685         do {
2686                 u32 signal_to_noise = 0;
2687                 u32 ber_quality = 100;
2688                 u32 signal_to_noise_rel = 0;
2689
2690                 status = get_qam_signal_to_noise(state, &signal_to_noise);
2691                 if (status < 0)
2692                         break;
2693
2694                 switch (state->props.modulation) {
2695                 case QAM_16:
2696                         signal_to_noise_rel = signal_to_noise - 200;
2697                         break;
2698                 case QAM_32:
2699                         signal_to_noise_rel = signal_to_noise - 230;
2700                         break;  /* Not in NorDig */
2701                 case QAM_64:
2702                         signal_to_noise_rel = signal_to_noise - 260;
2703                         break;
2704                 case QAM_128:
2705                         signal_to_noise_rel = signal_to_noise - 290;
2706                         break;
2707                 default:
2708                 case QAM_256:
2709                         signal_to_noise_rel = signal_to_noise - 320;
2710                         break;
2711                 }
2712
2713                 if (signal_to_noise_rel < -70)
2714                         *p_quality = 0;
2715                 else if (signal_to_noise_rel < 30)
2716                         *p_quality = ((signal_to_noise_rel + 70) *
2717                                      ber_quality) / 100;
2718                 else
2719                         *p_quality = ber_quality;
2720         } while (0);
2721
2722         return status;
2723 }
2724
2725 static int get_quality(struct drxk_state *state, s32 *p_quality)
2726 {
2727         dprintk(1, "\n");
2728
2729         switch (state->m_operation_mode) {
2730         case OM_DVBT:
2731                 return get_dvbt_quality(state, p_quality);
2732         case OM_QAM_ITU_A:
2733                 return get_dvbc_quality(state, p_quality);
2734         default:
2735                 break;
2736         }
2737
2738         return 0;
2739 }
2740 #endif
2741
2742 /* Free data ram in SIO HI */
2743 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2744 #define SIO_HI_RA_RAM_USR_END__A   0x420060
2745
2746 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2747 #define DRXK_HI_ATOMIC_BUF_END   (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2748 #define DRXK_HI_ATOMIC_READ      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2749 #define DRXK_HI_ATOMIC_WRITE     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2750
2751 #define DRXDAP_FASI_ADDR2BLOCK(addr)  (((addr) >> 22) & 0x3F)
2752 #define DRXDAP_FASI_ADDR2BANK(addr)   (((addr) >> 16) & 0x3F)
2753 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2754
2755 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2756 {
2757         int status = -EINVAL;
2758
2759         dprintk(1, "\n");
2760
2761         if (state->m_drxk_state == DRXK_UNINITIALIZED)
2762                 return 0;
2763         if (state->m_drxk_state == DRXK_POWERED_DOWN)
2764                 goto error;
2765
2766         if (state->no_i2c_bridge)
2767                 return 0;
2768
2769         status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2770                          SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2771         if (status < 0)
2772                 goto error;
2773         if (b_enable_bridge) {
2774                 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2775                                  SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2776                 if (status < 0)
2777                         goto error;
2778         } else {
2779                 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2780                                  SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2781                 if (status < 0)
2782                         goto error;
2783         }
2784
2785         status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2786
2787 error:
2788         if (status < 0)
2789                 pr_err("Error %d on %s\n", status, __func__);
2790         return status;
2791 }
2792
2793 static int set_pre_saw(struct drxk_state *state,
2794                      struct s_cfg_pre_saw *p_pre_saw_cfg)
2795 {
2796         int status = -EINVAL;
2797
2798         dprintk(1, "\n");
2799
2800         if ((p_pre_saw_cfg == NULL)
2801             || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
2802                 goto error;
2803
2804         status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2805 error:
2806         if (status < 0)
2807                 pr_err("Error %d on %s\n", status, __func__);
2808         return status;
2809 }
2810
2811 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2812                        u16 rom_offset, u16 nr_of_elements, u32 time_out)
2813 {
2814         u16 bl_status = 0;
2815         u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
2816         u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
2817         int status;
2818         unsigned long end;
2819
2820         dprintk(1, "\n");
2821
2822         mutex_lock(&state->mutex);
2823         status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2824         if (status < 0)
2825                 goto error;
2826         status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2827         if (status < 0)
2828                 goto error;
2829         status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2830         if (status < 0)
2831                 goto error;
2832         status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2833         if (status < 0)
2834                 goto error;
2835         status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2836         if (status < 0)
2837                 goto error;
2838         status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2839         if (status < 0)
2840                 goto error;
2841
2842         end = jiffies + msecs_to_jiffies(time_out);
2843         do {
2844                 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2845                 if (status < 0)
2846                         goto error;
2847         } while ((bl_status == 0x1) && time_is_after_jiffies(end));
2848         if (bl_status == 0x1) {
2849                 pr_err("SIO not ready\n");
2850                 status = -EINVAL;
2851                 goto error2;
2852         }
2853 error:
2854         if (status < 0)
2855                 pr_err("Error %d on %s\n", status, __func__);
2856 error2:
2857         mutex_unlock(&state->mutex);
2858         return status;
2859
2860 }
2861
2862 static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2863 {
2864         u16 data = 0;
2865         int status;
2866
2867         dprintk(1, "\n");
2868
2869         /* start measurement */
2870         status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2871         if (status < 0)
2872                 goto error;
2873         status = write16(state, IQM_AF_START_LOCK__A, 1);
2874         if (status < 0)
2875                 goto error;
2876
2877         *count = 0;
2878         status = read16(state, IQM_AF_PHASE0__A, &data);
2879         if (status < 0)
2880                 goto error;
2881         if (data == 127)
2882                 *count = *count + 1;
2883         status = read16(state, IQM_AF_PHASE1__A, &data);
2884         if (status < 0)
2885                 goto error;
2886         if (data == 127)
2887                 *count = *count + 1;
2888         status = read16(state, IQM_AF_PHASE2__A, &data);
2889         if (status < 0)
2890                 goto error;
2891         if (data == 127)
2892                 *count = *count + 1;
2893
2894 error:
2895         if (status < 0)
2896                 pr_err("Error %d on %s\n", status, __func__);
2897         return status;
2898 }
2899
2900 static int adc_synchronization(struct drxk_state *state)
2901 {
2902         u16 count = 0;
2903         int status;
2904
2905         dprintk(1, "\n");
2906
2907         status = adc_sync_measurement(state, &count);
2908         if (status < 0)
2909                 goto error;
2910
2911         if (count == 1) {
2912                 /* Try sampling on a different edge */
2913                 u16 clk_neg = 0;
2914
2915                 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2916                 if (status < 0)
2917                         goto error;
2918                 if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2919                         IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2920                         clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2921                         clk_neg |=
2922                                 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2923                 } else {
2924                         clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2925                         clk_neg |=
2926                                 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2927                 }
2928                 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2929                 if (status < 0)
2930                         goto error;
2931                 status = adc_sync_measurement(state, &count);
2932                 if (status < 0)
2933                         goto error;
2934         }
2935
2936         if (count < 2)
2937                 status = -EINVAL;
2938 error:
2939         if (status < 0)
2940                 pr_err("Error %d on %s\n", status, __func__);
2941         return status;
2942 }
2943
2944 static int set_frequency_shifter(struct drxk_state *state,
2945                                u16 intermediate_freqk_hz,
2946                                s32 tuner_freq_offset, bool is_dtv)
2947 {
2948         bool select_pos_image = false;
2949         u32 rf_freq_residual = tuner_freq_offset;
2950         u32 fm_frequency_shift = 0;
2951         bool tuner_mirror = !state->m_b_mirror_freq_spect;
2952         u32 adc_freq;
2953         bool adc_flip;
2954         int status;
2955         u32 if_freq_actual;
2956         u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2957         u32 frequency_shift;
2958         bool image_to_select;
2959
2960         dprintk(1, "\n");
2961
2962         /*
2963            Program frequency shifter
2964            No need to account for mirroring on RF
2965          */
2966         if (is_dtv) {
2967                 if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2968                     (state->m_operation_mode == OM_QAM_ITU_C) ||
2969                     (state->m_operation_mode == OM_DVBT))
2970                         select_pos_image = true;
2971                 else
2972                         select_pos_image = false;
2973         }
2974         if (tuner_mirror)
2975                 /* tuner doesn't mirror */
2976                 if_freq_actual = intermediate_freqk_hz +
2977                     rf_freq_residual + fm_frequency_shift;
2978         else
2979                 /* tuner mirrors */
2980                 if_freq_actual = intermediate_freqk_hz -
2981                     rf_freq_residual - fm_frequency_shift;
2982         if (if_freq_actual > sampling_frequency / 2) {
2983                 /* adc mirrors */
2984                 adc_freq = sampling_frequency - if_freq_actual;
2985                 adc_flip = true;
2986         } else {
2987                 /* adc doesn't mirror */
2988                 adc_freq = if_freq_actual;
2989                 adc_flip = false;
2990         }
2991
2992         frequency_shift = adc_freq;
2993         image_to_select = state->m_rfmirror ^ tuner_mirror ^
2994             adc_flip ^ select_pos_image;
2995         state->m_iqm_fs_rate_ofs =
2996             Frac28a((frequency_shift), sampling_frequency);
2997
2998         if (image_to_select)
2999                 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
3000
3001         /* Program frequency shifter with tuner offset compensation */
3002         /* frequency_shift += tuner_freq_offset; TODO */
3003         status = write32(state, IQM_FS_RATE_OFS_LO__A,
3004                          state->m_iqm_fs_rate_ofs);
3005         if (status < 0)
3006                 pr_err("Error %d on %s\n", status, __func__);
3007         return status;
3008 }
3009
3010 static int init_agc(struct drxk_state *state, bool is_dtv)
3011 {
3012         u16 ingain_tgt = 0;
3013         u16 ingain_tgt_min = 0;
3014         u16 ingain_tgt_max = 0;
3015         u16 clp_cyclen = 0;
3016         u16 clp_sum_min = 0;
3017         u16 clp_dir_to = 0;
3018         u16 sns_sum_min = 0;
3019         u16 sns_sum_max = 0;
3020         u16 clp_sum_max = 0;
3021         u16 sns_dir_to = 0;
3022         u16 ki_innergain_min = 0;
3023         u16 if_iaccu_hi_tgt = 0;
3024         u16 if_iaccu_hi_tgt_min = 0;
3025         u16 if_iaccu_hi_tgt_max = 0;
3026         u16 data = 0;
3027         u16 fast_clp_ctrl_delay = 0;
3028         u16 clp_ctrl_mode = 0;
3029         int status = 0;
3030
3031         dprintk(1, "\n");
3032
3033         /* Common settings */
3034         sns_sum_max = 1023;
3035         if_iaccu_hi_tgt_min = 2047;
3036         clp_cyclen = 500;
3037         clp_sum_max = 1023;
3038
3039         /* AGCInit() not available for DVBT; init done in microcode */
3040         if (!is_qam(state)) {
3041                 pr_err("%s: mode %d is not DVB-C\n",
3042                        __func__, state->m_operation_mode);
3043                 return -EINVAL;
3044         }
3045
3046         /* FIXME: Analog TV AGC require different settings */
3047
3048         /* Standard specific settings */
3049         clp_sum_min = 8;
3050         clp_dir_to = (u16) -9;
3051         clp_ctrl_mode = 0;
3052         sns_sum_min = 8;
3053         sns_dir_to = (u16) -9;
3054         ki_innergain_min = (u16) -1030;
3055         if_iaccu_hi_tgt_max = 0x2380;
3056         if_iaccu_hi_tgt = 0x2380;
3057         ingain_tgt_min = 0x0511;
3058         ingain_tgt = 0x0511;
3059         ingain_tgt_max = 5119;
3060         fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3061
3062         status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3063                          fast_clp_ctrl_delay);
3064         if (status < 0)
3065                 goto error;
3066
3067         status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3068         if (status < 0)
3069                 goto error;
3070         status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3071         if (status < 0)
3072                 goto error;
3073         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3074         if (status < 0)
3075                 goto error;
3076         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3077         if (status < 0)
3078                 goto error;
3079         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3080                          if_iaccu_hi_tgt_min);
3081         if (status < 0)
3082                 goto error;
3083         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3084                          if_iaccu_hi_tgt_max);
3085         if (status < 0)
3086                 goto error;
3087         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3088         if (status < 0)
3089                 goto error;
3090         status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3091         if (status < 0)
3092                 goto error;
3093         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3094         if (status < 0)
3095                 goto error;
3096         status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3097         if (status < 0)
3098                 goto error;
3099         status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3100         if (status < 0)
3101                 goto error;
3102         status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3103         if (status < 0)
3104                 goto error;
3105
3106         status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3107                          ki_innergain_min);
3108         if (status < 0)
3109                 goto error;
3110         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3111                          if_iaccu_hi_tgt);
3112         if (status < 0)
3113                 goto error;
3114         status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3115         if (status < 0)
3116                 goto error;
3117
3118         status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3119         if (status < 0)
3120                 goto error;
3121         status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3122         if (status < 0)
3123                 goto error;
3124         status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3125         if (status < 0)
3126                 goto error;
3127
3128         status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3129         if (status < 0)
3130                 goto error;
3131         status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3132         if (status < 0)
3133                 goto error;
3134         status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3135         if (status < 0)
3136                 goto error;
3137         status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3138         if (status < 0)
3139                 goto error;
3140         status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3141         if (status < 0)
3142                 goto error;
3143         status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3144         if (status < 0)
3145                 goto error;
3146         status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3147         if (status < 0)
3148                 goto error;
3149         status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3150         if (status < 0)
3151                 goto error;
3152         status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3153         if (status < 0)
3154                 goto error;
3155         status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3156         if (status < 0)
3157                 goto error;
3158         status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3159         if (status < 0)
3160                 goto error;
3161         status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3162         if (status < 0)
3163                 goto error;
3164         status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3165         if (status < 0)
3166                 goto error;
3167         status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3168         if (status < 0)
3169                 goto error;
3170         status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3171         if (status < 0)
3172                 goto error;
3173         status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3174         if (status < 0)
3175                 goto error;
3176         status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3177         if (status < 0)
3178                 goto error;
3179         status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3180         if (status < 0)
3181                 goto error;
3182         status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3183         if (status < 0)
3184                 goto error;
3185
3186         /* Initialize inner-loop KI gain factors */
3187         status = read16(state, SCU_RAM_AGC_KI__A, &data);
3188         if (status < 0)
3189                 goto error;
3190
3191         data = 0x0657;
3192         data &= ~SCU_RAM_AGC_KI_RF__M;
3193         data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3194         data &= ~SCU_RAM_AGC_KI_IF__M;
3195         data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3196
3197         status = write16(state, SCU_RAM_AGC_KI__A, data);
3198 error:
3199         if (status < 0)
3200                 pr_err("Error %d on %s\n", status, __func__);
3201         return status;
3202 }
3203
3204 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3205 {
3206         int status;
3207
3208         dprintk(1, "\n");
3209         if (packet_err == NULL)
3210                 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3211         else
3212                 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3213                                 packet_err);
3214         if (status < 0)
3215                 pr_err("Error %d on %s\n", status, __func__);
3216         return status;
3217 }
3218
3219 static int dvbt_sc_command(struct drxk_state *state,
3220                          u16 cmd, u16 subcmd,
3221                          u16 param0, u16 param1, u16 param2,
3222                          u16 param3, u16 param4)
3223 {
3224         u16 cur_cmd = 0;
3225         u16 err_code = 0;
3226         u16 retry_cnt = 0;
3227         u16 sc_exec = 0;
3228         int status;
3229
3230         dprintk(1, "\n");
3231         status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3232         if (sc_exec != 1) {
3233                 /* SC is not running */
3234                 status = -EINVAL;
3235         }
3236         if (status < 0)
3237                 goto error;
3238
3239         /* Wait until sc is ready to receive command */
3240         retry_cnt = 0;
3241         do {
3242                 usleep_range(1000, 2000);
3243                 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3244                 retry_cnt++;
3245         } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3246         if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3247                 goto error;
3248
3249         /* Write sub-command */
3250         switch (cmd) {
3251                 /* All commands using sub-cmd */
3252         case OFDM_SC_RA_RAM_CMD_PROC_START:
3253         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3254         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3255                 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3256                 if (status < 0)
3257                         goto error;
3258                 break;
3259         default:
3260                 /* Do nothing */
3261                 break;
3262         }
3263
3264         /* Write needed parameters and the command */
3265         status = 0;
3266         switch (cmd) {
3267                 /* All commands using 5 parameters */
3268                 /* All commands using 4 parameters */
3269                 /* All commands using 3 parameters */
3270                 /* All commands using 2 parameters */
3271         case OFDM_SC_RA_RAM_CMD_PROC_START:
3272         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3273         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3274                 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3275                 /* fall through - All commands using 1 parameters */
3276         case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3277         case OFDM_SC_RA_RAM_CMD_USER_IO:
3278                 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3279                 /* fall through - All commands using 0 parameters */
3280         case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3281         case OFDM_SC_RA_RAM_CMD_NULL:
3282                 /* Write command */
3283                 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3284                 break;
3285         default:
3286                 /* Unknown command */
3287                 status = -EINVAL;
3288         }
3289         if (status < 0)
3290                 goto error;
3291
3292         /* Wait until sc is ready processing command */
3293         retry_cnt = 0;
3294         do {
3295                 usleep_range(1000, 2000);
3296                 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3297                 retry_cnt++;
3298         } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3299         if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3300                 goto error;
3301
3302         /* Check for illegal cmd */
3303         status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3304         if (err_code == 0xFFFF) {
3305                 /* illegal command */
3306                 status = -EINVAL;
3307         }
3308         if (status < 0)
3309                 goto error;
3310
3311         /* Retrieve results parameters from SC */
3312         switch (cmd) {
3313                 /* All commands yielding 5 results */
3314                 /* All commands yielding 4 results */
3315                 /* All commands yielding 3 results */
3316                 /* All commands yielding 2 results */
3317                 /* All commands yielding 1 result */
3318         case OFDM_SC_RA_RAM_CMD_USER_IO:
3319         case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3320                 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3321                 /* All commands yielding 0 results */
3322         case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3323         case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3324         case OFDM_SC_RA_RAM_CMD_PROC_START:
3325         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3326         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3327         case OFDM_SC_RA_RAM_CMD_NULL:
3328                 break;
3329         default:
3330                 /* Unknown command */
3331                 status = -EINVAL;
3332                 break;
3333         }                       /* switch (cmd->cmd) */
3334 error:
3335         if (status < 0)
3336                 pr_err("Error %d on %s\n", status, __func__);
3337         return status;
3338 }
3339
3340 static int power_up_dvbt(struct drxk_state *state)
3341 {
3342         enum drx_power_mode power_mode = DRX_POWER_UP;
3343         int status;
3344
3345         dprintk(1, "\n");
3346         status = ctrl_power_mode(state, &power_mode);
3347         if (status < 0)
3348                 pr_err("Error %d on %s\n", status, __func__);
3349         return status;
3350 }
3351
3352 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3353 {
3354         int status;
3355
3356         dprintk(1, "\n");
3357         if (*enabled)
3358                 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3359         else
3360                 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3361         if (status < 0)
3362                 pr_err("Error %d on %s\n", status, __func__);
3363         return status;
3364 }
3365
3366 #define DEFAULT_FR_THRES_8K     4000
3367 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3368 {
3369
3370         int status;
3371
3372         dprintk(1, "\n");
3373         if (*enabled) {
3374                 /* write mask to 1 */
3375                 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3376                                    DEFAULT_FR_THRES_8K);
3377         } else {
3378                 /* write mask to 0 */
3379                 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3380         }
3381         if (status < 0)
3382                 pr_err("Error %d on %s\n", status, __func__);
3383
3384         return status;
3385 }
3386
3387 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3388                                 struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
3389 {
3390         u16 data = 0;
3391         int status;
3392
3393         dprintk(1, "\n");
3394         status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3395         if (status < 0)
3396                 goto error;
3397
3398         switch (echo_thres->fft_mode) {
3399         case DRX_FFTMODE_2K:
3400                 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3401                 data |= ((echo_thres->threshold <<
3402                         OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3403                         & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3404                 break;
3405         case DRX_FFTMODE_8K:
3406                 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3407                 data |= ((echo_thres->threshold <<
3408                         OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3409                         & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3410                 break;
3411         default:
3412                 return -EINVAL;
3413         }
3414
3415         status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3416 error:
3417         if (status < 0)
3418                 pr_err("Error %d on %s\n", status, __func__);
3419         return status;
3420 }
3421
3422 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3423                                enum drxk_cfg_dvbt_sqi_speed *speed)
3424 {
3425         int status = -EINVAL;
3426
3427         dprintk(1, "\n");
3428
3429         switch (*speed) {
3430         case DRXK_DVBT_SQI_SPEED_FAST:
3431         case DRXK_DVBT_SQI_SPEED_MEDIUM:
3432         case DRXK_DVBT_SQI_SPEED_SLOW:
3433                 break;
3434         default:
3435                 goto error;
3436         }
3437         status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3438                            (u16) *speed);
3439 error:
3440         if (status < 0)
3441                 pr_err("Error %d on %s\n", status, __func__);
3442         return status;
3443 }
3444
3445 /*============================================================================*/
3446
3447 /*
3448 * \brief Activate DVBT specific presets
3449 * \param demod instance of demodulator.
3450 * \return DRXStatus_t.
3451 *
3452 * Called in DVBTSetStandard
3453 *
3454 */
3455 static int dvbt_activate_presets(struct drxk_state *state)
3456 {
3457         int status;
3458         bool setincenable = false;
3459         bool setfrenable = true;
3460
3461         struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
3462         struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
3463
3464         dprintk(1, "\n");
3465         status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3466         if (status < 0)
3467                 goto error;
3468         status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3469         if (status < 0)
3470                 goto error;
3471         status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3472         if (status < 0)
3473                 goto error;
3474         status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3475         if (status < 0)
3476                 goto error;
3477         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3478                          state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3479 error:
3480         if (status < 0)
3481                 pr_err("Error %d on %s\n", status, __func__);
3482         return status;
3483 }
3484
3485 /*============================================================================*/
3486
3487 /*
3488 * \brief Initialize channelswitch-independent settings for DVBT.
3489 * \param demod instance of demodulator.
3490 * \return DRXStatus_t.
3491 *
3492 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3493 * the DVB-T taps from the drxk_filters.h are used.
3494 */
3495 static int set_dvbt_standard(struct drxk_state *state,
3496                            enum operation_mode o_mode)
3497 {
3498         u16 cmd_result = 0;
3499         u16 data = 0;
3500         int status;
3501
3502         dprintk(1, "\n");
3503
3504         power_up_dvbt(state);
3505         /* added antenna switch */
3506         switch_antenna_to_dvbt(state);
3507         /* send OFDM reset command */
3508         status = scu_command(state,
3509                              SCU_RAM_COMMAND_STANDARD_OFDM
3510                              | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
3511                              0, NULL, 1, &cmd_result);
3512         if (status < 0)
3513                 goto error;
3514
3515         /* send OFDM setenv command */
3516         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3517                              | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
3518                              0, NULL, 1, &cmd_result);
3519         if (status < 0)
3520                 goto error;
3521
3522         /* reset datapath for OFDM, processors first */
3523         status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3524         if (status < 0)
3525                 goto error;
3526         status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3527         if (status < 0)
3528                 goto error;
3529         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3530         if (status < 0)
3531                 goto error;
3532
3533         /* IQM setup */
3534         /* synchronize on ofdstate->m_festart */
3535         status = write16(state, IQM_AF_UPD_SEL__A, 1);
3536         if (status < 0)
3537                 goto error;
3538         /* window size for clipping ADC detection */
3539         status = write16(state, IQM_AF_CLP_LEN__A, 0);
3540         if (status < 0)
3541                 goto error;
3542         /* window size for for sense pre-SAW detection */
3543         status = write16(state, IQM_AF_SNS_LEN__A, 0);
3544         if (status < 0)
3545                 goto error;
3546         /* sense threshold for sense pre-SAW detection */
3547         status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3548         if (status < 0)
3549                 goto error;
3550         status = set_iqm_af(state, true);
3551         if (status < 0)
3552                 goto error;
3553
3554         status = write16(state, IQM_AF_AGC_RF__A, 0);
3555         if (status < 0)
3556                 goto error;
3557
3558         /* Impulse noise cruncher setup */
3559         status = write16(state, IQM_AF_INC_LCT__A, 0);  /* crunch in IQM_CF */
3560         if (status < 0)
3561                 goto error;
3562         status = write16(state, IQM_CF_DET_LCT__A, 0);  /* detect in IQM_CF */
3563         if (status < 0)
3564                 goto error;
3565         status = write16(state, IQM_CF_WND_LEN__A, 3);  /* peak detector window length */
3566         if (status < 0)
3567                 goto error;
3568
3569         status = write16(state, IQM_RC_STRETCH__A, 16);
3570         if (status < 0)
3571                 goto error;
3572         status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3573         if (status < 0)
3574                 goto error;
3575         status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3576         if (status < 0)
3577                 goto error;
3578         status = write16(state, IQM_CF_SCALE__A, 1600);
3579         if (status < 0)
3580                 goto error;
3581         status = write16(state, IQM_CF_SCALE_SH__A, 0);
3582         if (status < 0)
3583                 goto error;
3584
3585         /* virtual clipping threshold for clipping ADC detection */
3586         status = write16(state, IQM_AF_CLP_TH__A, 448);
3587         if (status < 0)
3588                 goto error;
3589         status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3590         if (status < 0)
3591                 goto error;
3592
3593         status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3594                               DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3595         if (status < 0)
3596                 goto error;
3597
3598         status = write16(state, IQM_CF_PKDTH__A, 2);    /* peak detector threshold */
3599         if (status < 0)
3600                 goto error;
3601         status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3602         if (status < 0)
3603                 goto error;
3604         /* enable power measurement interrupt */
3605         status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3606         if (status < 0)
3607                 goto error;
3608         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3609         if (status < 0)
3610                 goto error;
3611
3612         /* IQM will not be reset from here, sync ADC and update/init AGC */
3613         status = adc_synchronization(state);
3614         if (status < 0)
3615                 goto error;
3616         status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3617         if (status < 0)
3618                 goto error;
3619
3620         /* Halt SCU to enable safe non-atomic accesses */
3621         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3622         if (status < 0)
3623                 goto error;
3624
3625         status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3626         if (status < 0)
3627                 goto error;
3628         status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3629         if (status < 0)
3630                 goto error;
3631
3632         /* Set Noise Estimation notch width and enable DC fix */
3633         status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3634         if (status < 0)
3635                 goto error;
3636         data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3637         status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3638         if (status < 0)
3639                 goto error;
3640
3641         /* Activate SCU to enable SCU commands */
3642         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3643         if (status < 0)
3644                 goto error;
3645
3646         if (!state->m_drxk_a3_rom_code) {
3647                 /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay  */
3648                 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3649                                  state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3650                 if (status < 0)
3651                         goto error;
3652         }
3653
3654         /* OFDM_SC setup */
3655 #ifdef COMPILE_FOR_NONRT
3656         status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3657         if (status < 0)
3658                 goto error;
3659         status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3660         if (status < 0)
3661                 goto error;
3662 #endif
3663
3664         /* FEC setup */
3665         status = write16(state, FEC_DI_INPUT_CTL__A, 1);        /* OFDM input */
3666         if (status < 0)
3667                 goto error;
3668
3669
3670 #ifdef COMPILE_FOR_NONRT
3671         status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3672         if (status < 0)
3673                 goto error;
3674 #else
3675         status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3676         if (status < 0)
3677                 goto error;
3678 #endif
3679         status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3680         if (status < 0)
3681                 goto error;
3682
3683         /* Setup MPEG bus */
3684         status = mpegts_dto_setup(state, OM_DVBT);
3685         if (status < 0)
3686                 goto error;
3687         /* Set DVBT Presets */
3688         status = dvbt_activate_presets(state);
3689         if (status < 0)
3690                 goto error;
3691
3692 error:
3693         if (status < 0)
3694                 pr_err("Error %d on %s\n", status, __func__);
3695         return status;
3696 }
3697
3698 /*============================================================================*/
3699 /*
3700 * \brief start dvbt demodulating for channel.
3701 * \param demod instance of demodulator.
3702 * \return DRXStatus_t.
3703 */
3704 static int dvbt_start(struct drxk_state *state)
3705 {
3706         u16 param1;
3707         int status;
3708         /* drxk_ofdm_sc_cmd_t scCmd; */
3709
3710         dprintk(1, "\n");
3711         /* start correct processes to get in lock */
3712         /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3713         param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3714         status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3715                                  OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
3716                                  0, 0, 0);
3717         if (status < 0)
3718                 goto error;
3719         /* start FEC OC */
3720         status = mpegts_start(state);
3721         if (status < 0)
3722                 goto error;
3723         status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3724         if (status < 0)
3725                 goto error;
3726 error:
3727         if (status < 0)
3728                 pr_err("Error %d on %s\n", status, __func__);
3729         return status;
3730 }
3731
3732
3733 /*============================================================================*/
3734
3735 /*
3736 * \brief Set up dvbt demodulator for channel.
3737 * \param demod instance of demodulator.
3738 * \return DRXStatus_t.
3739 * // original DVBTSetChannel()
3740 */
3741 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3742                    s32 tuner_freq_offset)
3743 {
3744         u16 cmd_result = 0;
3745         u16 transmission_params = 0;
3746         u16 operation_mode = 0;
3747         u32 iqm_rc_rate_ofs = 0;
3748         u32 bandwidth = 0;
3749         u16 param1;
3750         int status;
3751
3752         dprintk(1, "IF =%d, TFO = %d\n",
3753                 intermediate_freqk_hz, tuner_freq_offset);
3754
3755         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3756                             | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
3757                             0, NULL, 1, &cmd_result);
3758         if (status < 0)
3759                 goto error;
3760
3761         /* Halt SCU to enable safe non-atomic accesses */
3762         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3763         if (status < 0)
3764                 goto error;
3765
3766         /* Stop processors */
3767         status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3768         if (status < 0)
3769                 goto error;
3770         status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3771         if (status < 0)
3772                 goto error;
3773
3774         /* Mandatory fix, always stop CP, required to set spl offset back to
3775                 hardware default (is set to 0 by ucode during pilot detection */
3776         status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3777         if (status < 0)
3778                 goto error;
3779
3780         /*== Write channel settings to device ================================*/
3781
3782         /* mode */
3783         switch (state->props.transmission_mode) {
3784         case TRANSMISSION_MODE_AUTO:
3785         default:
3786                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3787                 /* fall through - try first guess DRX_FFTMODE_8K */
3788         case TRANSMISSION_MODE_8K:
3789                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3790                 break;
3791         case TRANSMISSION_MODE_2K:
3792                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3793                 break;
3794         }
3795
3796         /* guard */
3797         switch (state->props.guard_interval) {
3798         default:
3799         case GUARD_INTERVAL_AUTO:
3800                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3801                 /* fall through - try first guess DRX_GUARD_1DIV4 */
3802         case GUARD_INTERVAL_1_4:
3803                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3804                 break;
3805         case GUARD_INTERVAL_1_32:
3806                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3807                 break;
3808         case GUARD_INTERVAL_1_16:
3809                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3810                 break;
3811         case GUARD_INTERVAL_1_8:
3812                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3813                 break;
3814         }
3815
3816         /* hierarchy */
3817         switch (state->props.hierarchy) {
3818         case HIERARCHY_AUTO:
3819         case HIERARCHY_NONE:
3820         default:
3821                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3822                 /* try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3823                 /* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3824                 /* fall through */
3825         case HIERARCHY_1:
3826                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3827                 break;
3828         case HIERARCHY_2:
3829                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3830                 break;
3831         case HIERARCHY_4:
3832                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3833                 break;
3834         }
3835
3836
3837         /* modulation */
3838         switch (state->props.modulation) {
3839         case QAM_AUTO:
3840         default:
3841                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3842                 /* fall through - try first guess DRX_CONSTELLATION_QAM64 */
3843         case QAM_64:
3844                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3845                 break;
3846         case QPSK:
3847                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3848                 break;
3849         case QAM_16:
3850                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3851                 break;
3852         }
3853 #if 0
3854         /* No hierarchical channels support in BDA */
3855         /* Priority (only for hierarchical channels) */
3856         switch (channel->priority) {
3857         case DRX_PRIORITY_LOW:
3858                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3859                 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3860                         OFDM_EC_SB_PRIOR_LO);
3861                 break;
3862         case DRX_PRIORITY_HIGH:
3863                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3864                 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3865                         OFDM_EC_SB_PRIOR_HI));
3866                 break;
3867         case DRX_PRIORITY_UNKNOWN:      /* fall through */
3868         default:
3869                 status = -EINVAL;
3870                 goto error;
3871         }
3872 #else
3873         /* Set Priority high */
3874         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3875         status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3876         if (status < 0)
3877                 goto error;
3878 #endif
3879
3880         /* coderate */
3881         switch (state->props.code_rate_HP) {
3882         case FEC_AUTO:
3883         default:
3884                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3885                 /* fall through - try first guess DRX_CODERATE_2DIV3 */
3886         case FEC_2_3:
3887                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3888                 break;
3889         case FEC_1_2:
3890                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3891                 break;
3892         case FEC_3_4:
3893                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3894                 break;
3895         case FEC_5_6:
3896                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3897                 break;
3898         case FEC_7_8:
3899                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3900                 break;
3901         }
3902
3903         /*
3904          * SAW filter selection: normally not necessary, but if wanted
3905          * the application can select a SAW filter via the driver by
3906          * using UIOs
3907          */
3908
3909         /* First determine real bandwidth (Hz) */
3910         /* Also set delay for impulse noise cruncher */
3911         /*
3912          * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is
3913          * changed by SC for fix for some 8K,1/8 guard but is restored by
3914          * InitEC and ResetEC functions
3915          */
3916         switch (state->props.bandwidth_hz) {
3917         case 0:
3918                 state->props.bandwidth_hz = 8000000;
3919                 /* fall through */
3920         case 8000000:
3921                 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3922                 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3923                                  3052);
3924                 if (status < 0)
3925                         goto error;
3926                 /* cochannel protection for PAL 8 MHz */
3927                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3928                                  7);
3929                 if (status < 0)
3930                         goto error;
3931                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3932                                  7);
3933                 if (status < 0)
3934                         goto error;
3935                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3936                                  7);
3937                 if (status < 0)
3938                         goto error;
3939                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3940                                  1);
3941                 if (status < 0)
3942                         goto error;
3943                 break;
3944         case 7000000:
3945                 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3946                 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3947                                  3491);
3948                 if (status < 0)
3949                         goto error;
3950                 /* cochannel protection for PAL 7 MHz */
3951                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3952                                  8);
3953                 if (status < 0)
3954                         goto error;
3955                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3956                                  8);
3957                 if (status < 0)
3958                         goto error;
3959                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3960                                  4);
3961                 if (status < 0)
3962                         goto error;
3963                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3964                                  1);
3965                 if (status < 0)
3966                         goto error;
3967                 break;
3968         case 6000000:
3969                 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3970                 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3971                                  4073);
3972                 if (status < 0)
3973                         goto error;
3974                 /* cochannel protection for NTSC 6 MHz */
3975                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3976                                  19);
3977                 if (status < 0)
3978                         goto error;
3979                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3980                                  19);
3981                 if (status < 0)
3982                         goto error;
3983                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3984                                  14);
3985                 if (status < 0)
3986                         goto error;
3987                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3988                                  1);
3989                 if (status < 0)
3990                         goto error;
3991                 break;
3992         default:
3993                 status = -EINVAL;
3994                 goto error;
3995         }
3996
3997         if (iqm_rc_rate_ofs == 0) {
3998                 /* Now compute IQM_RC_RATE_OFS
3999                         (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4000                         =>
4001                         ((SysFreq / BandWidth) * (2^21)) - (2^23)
4002                         */
4003                 /* (SysFreq / BandWidth) * (2^28)  */
4004                 /*
4005                  * assert (MAX(sysClk)/MIN(bandwidth) < 16)
4006                  *      => assert(MAX(sysClk) < 16*MIN(bandwidth))
4007                  *      => assert(109714272 > 48000000) = true
4008                  * so Frac 28 can be used
4009                  */
4010                 iqm_rc_rate_ofs = Frac28a((u32)
4011                                         ((state->m_sys_clock_freq *
4012                                                 1000) / 3), bandwidth);
4013                 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4014                 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
4015                         iqm_rc_rate_ofs += 0x80L;
4016                 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
4017                 /* ((SysFreq / BandWidth) * (2^21)) - (2^23)  */
4018                 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
4019         }
4020
4021         iqm_rc_rate_ofs &=
4022                 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4023                 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4024         status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
4025         if (status < 0)
4026                 goto error;
4027
4028         /* Bandwidth setting done */
4029
4030 #if 0
4031         status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
4032         if (status < 0)
4033                 goto error;
4034 #endif
4035         status = set_frequency_shifter(state, intermediate_freqk_hz,
4036                                        tuner_freq_offset, true);
4037         if (status < 0)
4038                 goto error;
4039
4040         /*== start SC, write channel settings to SC ==========================*/
4041
4042         /* Activate SCU to enable SCU commands */
4043         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4044         if (status < 0)
4045                 goto error;
4046
4047         /* Enable SC after setting all other parameters */
4048         status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4049         if (status < 0)
4050                 goto error;
4051         status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4052         if (status < 0)
4053                 goto error;
4054
4055
4056         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4057                              | SCU_RAM_COMMAND_CMD_DEMOD_START,
4058                              0, NULL, 1, &cmd_result);
4059         if (status < 0)
4060                 goto error;
4061
4062         /* Write SC parameter registers, set all AUTO flags in operation mode */
4063         param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4064                         OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4065                         OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4066                         OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4067                         OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4068         status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4069                                 0, transmission_params, param1, 0, 0, 0);
4070         if (status < 0)
4071                 goto error;
4072
4073         if (!state->m_drxk_a3_rom_code)
4074                 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4075 error:
4076         if (status < 0)
4077                 pr_err("Error %d on %s\n", status, __func__);
4078
4079         return status;
4080 }
4081
4082
4083 /*============================================================================*/
4084
4085 /*
4086 * \brief Retrieve lock status .
4087 * \param demod    Pointer to demodulator instance.
4088 * \param lockStat Pointer to lock status structure.
4089 * \return DRXStatus_t.
4090 *
4091 */
4092 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
4093 {
4094         int status;
4095         const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4096                                     OFDM_SC_RA_RAM_LOCK_FEC__M);
4097         const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4098         const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4099
4100         u16 sc_ra_ram_lock = 0;
4101         u16 sc_comm_exec = 0;
4102
4103         dprintk(1, "\n");
4104
4105         *p_lock_status = NOT_LOCKED;
4106         /* driver 0.9.0 */
4107         /* Check if SC is running */
4108         status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4109         if (status < 0)
4110                 goto end;
4111         if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
4112                 goto end;
4113
4114         status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4115         if (status < 0)
4116                 goto end;
4117
4118         if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
4119                 *p_lock_status = MPEG_LOCK;
4120         else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
4121                 *p_lock_status = FEC_LOCK;
4122         else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
4123                 *p_lock_status = DEMOD_LOCK;
4124         else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4125                 *p_lock_status = NEVER_LOCK;
4126 end:
4127         if (status < 0)
4128                 pr_err("Error %d on %s\n", status, __func__);
4129
4130         return status;
4131 }
4132
4133 static int power_up_qam(struct drxk_state *state)
4134 {
4135         enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
4136         int status;
4137
4138         dprintk(1, "\n");
4139         status = ctrl_power_mode(state, &power_mode);
4140         if (status < 0)
4141                 pr_err("Error %d on %s\n", status, __func__);
4142
4143         return status;
4144 }
4145
4146
4147 /* Power Down QAM */
4148 static int power_down_qam(struct drxk_state *state)
4149 {
4150         u16 data = 0;
4151         u16 cmd_result;
4152         int status = 0;
4153
4154         dprintk(1, "\n");
4155         status = read16(state, SCU_COMM_EXEC__A, &data);
4156         if (status < 0)
4157                 goto error;
4158         if (data == SCU_COMM_EXEC_ACTIVE) {
4159                 /*
4160                         STOP demodulator
4161                         QAM and HW blocks
4162                         */
4163                 /* stop all comstate->m_exec */
4164                 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4165                 if (status < 0)
4166                         goto error;
4167                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4168                                      | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
4169                                      0, NULL, 1, &cmd_result);
4170                 if (status < 0)
4171                         goto error;
4172         }
4173         /* powerdown AFE                   */
4174         status = set_iqm_af(state, false);
4175
4176 error:
4177         if (status < 0)
4178                 pr_err("Error %d on %s\n", status, __func__);
4179
4180         return status;
4181 }
4182
4183 /*============================================================================*/
4184
4185 /*
4186 * \brief Setup of the QAM Measurement intervals for signal quality
4187 * \param demod instance of demod.
4188 * \param modulation current modulation.
4189 * \return DRXStatus_t.
4190 *
4191 *  NOTE:
4192 *  Take into account that for certain settings the errorcounters can overflow.
4193 *  The implementation does not check this.
4194 *
4195 */
4196 static int set_qam_measurement(struct drxk_state *state,
4197                              enum e_drxk_constellation modulation,
4198                              u32 symbol_rate)
4199 {
4200         u32 fec_bits_desired = 0;       /* BER accounting period */
4201         u32 fec_rs_period_total = 0;    /* Total period */
4202         u16 fec_rs_prescale = 0;        /* ReedSolomon Measurement Prescale */
4203         u16 fec_rs_period = 0;  /* Value for corresponding I2C register */
4204         int status = 0;
4205
4206         dprintk(1, "\n");
4207
4208         fec_rs_prescale = 1;
4209         /* fec_bits_desired = symbol_rate [kHz] *
4210                 FrameLenght [ms] *
4211                 (modulation + 1) *
4212                 SyncLoss (== 1) *
4213                 ViterbiLoss (==1)
4214                 */
4215         switch (modulation) {
4216         case DRX_CONSTELLATION_QAM16:
4217                 fec_bits_desired = 4 * symbol_rate;
4218                 break;
4219         case DRX_CONSTELLATION_QAM32:
4220                 fec_bits_desired = 5 * symbol_rate;
4221                 break;
4222         case DRX_CONSTELLATION_QAM64:
4223                 fec_bits_desired = 6 * symbol_rate;
4224                 break;
4225         case DRX_CONSTELLATION_QAM128:
4226                 fec_bits_desired = 7 * symbol_rate;
4227                 break;
4228         case DRX_CONSTELLATION_QAM256:
4229                 fec_bits_desired = 8 * symbol_rate;
4230                 break;
4231         default:
4232                 status = -EINVAL;
4233         }
4234         if (status < 0)
4235                 goto error;
4236
4237         fec_bits_desired /= 1000;       /* symbol_rate [Hz] -> symbol_rate [kHz] */
4238         fec_bits_desired *= 500;        /* meas. period [ms] */
4239
4240         /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4241         /* fec_rs_period_total = fec_bits_desired / 1632 */
4242         fec_rs_period_total = (fec_bits_desired / 1632UL) + 1;  /* roughly ceil */
4243
4244         /* fec_rs_period_total =  fec_rs_prescale * fec_rs_period  */
4245         fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
4246         if (fec_rs_prescale == 0) {
4247                 /* Divide by zero (though impossible) */
4248                 status = -EINVAL;
4249                 if (status < 0)
4250                         goto error;
4251         }
4252         fec_rs_period =
4253                 ((u16) fec_rs_period_total +
4254                 (fec_rs_prescale >> 1)) / fec_rs_prescale;
4255
4256         /* write corresponding registers */
4257         status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4258         if (status < 0)
4259                 goto error;
4260         status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4261                          fec_rs_prescale);
4262         if (status < 0)
4263                 goto error;
4264         status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4265 error:
4266         if (status < 0)
4267                 pr_err("Error %d on %s\n", status, __func__);
4268         return status;
4269 }
4270
4271 static int set_qam16(struct drxk_state *state)
4272 {
4273         int status = 0;
4274
4275         dprintk(1, "\n");
4276         /* QAM Equalizer Setup */
4277         /* Equalizer */
4278         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4279         if (status < 0)
4280                 goto error;
4281         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4282         if (status < 0)
4283                 goto error;
4284         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4285         if (status < 0)
4286                 goto error;
4287         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4288         if (status < 0)
4289                 goto error;
4290         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4291         if (status < 0)
4292                 goto error;
4293         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4294         if (status < 0)
4295                 goto error;
4296         /* Decision Feedback Equalizer */
4297         status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4298         if (status < 0)
4299                 goto error;
4300         status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4301         if (status < 0)
4302                 goto error;
4303         status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4304         if (status < 0)
4305                 goto error;
4306         status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4307         if (status < 0)
4308                 goto error;
4309         status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4310         if (status < 0)
4311                 goto error;
4312         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4313         if (status < 0)
4314                 goto error;
4315
4316         status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4317         if (status < 0)
4318                 goto error;
4319         status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4320         if (status < 0)
4321                 goto error;
4322         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4323         if (status < 0)
4324                 goto error;
4325
4326         /* QAM Slicer Settings */
4327         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4328                          DRXK_QAM_SL_SIG_POWER_QAM16);
4329         if (status < 0)
4330                 goto error;
4331
4332         /* QAM Loop Controller Coeficients */
4333         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4334         if (status < 0)
4335                 goto error;
4336         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4337         if (status < 0)
4338                 goto error;
4339         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4340         if (status < 0)
4341                 goto error;
4342         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4343         if (status < 0)
4344                 goto error;
4345         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4346         if (status < 0)
4347                 goto error;
4348         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4349         if (status < 0)
4350                 goto error;
4351         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4352         if (status < 0)
4353                 goto error;
4354         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4355         if (status < 0)
4356                 goto error;
4357
4358         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4359         if (status < 0)
4360                 goto error;
4361         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4362         if (status < 0)
4363                 goto error;
4364         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4365         if (status < 0)
4366                 goto error;
4367         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4368         if (status < 0)
4369                 goto error;
4370         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4371         if (status < 0)
4372                 goto error;
4373         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4374         if (status < 0)
4375                 goto error;
4376         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4377         if (status < 0)
4378                 goto error;
4379         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4380         if (status < 0)
4381                 goto error;
4382         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4383         if (status < 0)
4384                 goto error;
4385         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4386         if (status < 0)
4387                 goto error;
4388         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4389         if (status < 0)
4390                 goto error;
4391         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4392         if (status < 0)
4393                 goto error;
4394
4395
4396         /* QAM State Machine (FSM) Thresholds */
4397
4398         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4399         if (status < 0)
4400                 goto error;
4401         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4402         if (status < 0)
4403                 goto error;
4404         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4405         if (status < 0)
4406                 goto error;
4407         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4408         if (status < 0)
4409                 goto error;
4410         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4411         if (status < 0)
4412                 goto error;
4413         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4414         if (status < 0)
4415                 goto error;
4416
4417         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4418         if (status < 0)
4419                 goto error;
4420         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4421         if (status < 0)
4422                 goto error;
4423         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4424         if (status < 0)
4425                 goto error;
4426
4427
4428         /* QAM FSM Tracking Parameters */
4429
4430         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4431         if (status < 0)
4432                 goto error;
4433         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4434         if (status < 0)
4435                 goto error;
4436         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4437         if (status < 0)
4438                 goto error;
4439         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4440         if (status < 0)
4441                 goto error;
4442         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4443         if (status < 0)
4444                 goto error;
4445         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4446         if (status < 0)
4447                 goto error;
4448         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4449         if (status < 0)
4450                 goto error;
4451
4452 error:
4453         if (status < 0)
4454                 pr_err("Error %d on %s\n", status, __func__);
4455         return status;
4456 }
4457
4458 /*============================================================================*/
4459
4460 /*
4461 * \brief QAM32 specific setup
4462 * \param demod instance of demod.
4463 * \return DRXStatus_t.
4464 */
4465 static int set_qam32(struct drxk_state *state)
4466 {
4467         int status = 0;
4468
4469         dprintk(1, "\n");
4470
4471         /* QAM Equalizer Setup */
4472         /* Equalizer */
4473         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4474         if (status < 0)
4475                 goto error;
4476         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4477         if (status < 0)
4478                 goto error;
4479         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4480         if (status < 0)
4481                 goto error;
4482         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4483         if (status < 0)
4484                 goto error;
4485         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4486         if (status < 0)
4487                 goto error;
4488         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4489         if (status < 0)
4490                 goto error;
4491
4492         /* Decision Feedback Equalizer */
4493         status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4494         if (status < 0)
4495                 goto error;
4496         status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4497         if (status < 0)
4498                 goto error;
4499         status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4500         if (status < 0)
4501                 goto error;
4502         status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4503         if (status < 0)
4504                 goto error;
4505         status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4506         if (status < 0)
4507                 goto error;
4508         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4509         if (status < 0)
4510                 goto error;
4511
4512         status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4513         if (status < 0)
4514                 goto error;
4515         status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4516         if (status < 0)
4517                 goto error;
4518         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4519         if (status < 0)
4520                 goto error;
4521
4522         /* QAM Slicer Settings */
4523
4524         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4525                          DRXK_QAM_SL_SIG_POWER_QAM32);
4526         if (status < 0)
4527                 goto error;
4528
4529
4530         /* QAM Loop Controller Coeficients */
4531
4532         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4533         if (status < 0)
4534                 goto error;
4535         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4536         if (status < 0)
4537                 goto error;
4538         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4539         if (status < 0)
4540                 goto error;
4541         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4542         if (status < 0)
4543                 goto error;
4544         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4545         if (status < 0)
4546                 goto error;
4547         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4548         if (status < 0)
4549                 goto error;
4550         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4551         if (status < 0)
4552                 goto error;
4553         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4554         if (status < 0)
4555                 goto error;
4556
4557         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4558         if (status < 0)
4559                 goto error;
4560         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4561         if (status < 0)
4562                 goto error;
4563         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4564         if (status < 0)
4565                 goto error;
4566         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4567         if (status < 0)
4568                 goto error;
4569         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4570         if (status < 0)
4571                 goto error;
4572         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4573         if (status < 0)
4574                 goto error;
4575         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4576         if (status < 0)
4577                 goto error;
4578         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4579         if (status < 0)
4580                 goto error;
4581         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4582         if (status < 0)
4583                 goto error;
4584         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4585         if (status < 0)
4586                 goto error;
4587         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4588         if (status < 0)
4589                 goto error;
4590         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4591         if (status < 0)
4592                 goto error;
4593
4594
4595         /* QAM State Machine (FSM) Thresholds */
4596
4597         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4598         if (status < 0)
4599                 goto error;
4600         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4601         if (status < 0)
4602                 goto error;
4603         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4604         if (status < 0)
4605                 goto error;
4606         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4607         if (status < 0)
4608                 goto error;
4609         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4610         if (status < 0)
4611                 goto error;
4612         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4613         if (status < 0)
4614                 goto error;
4615
4616         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4617         if (status < 0)
4618                 goto error;
4619         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4620         if (status < 0)
4621                 goto error;
4622         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4623         if (status < 0)
4624                 goto error;
4625
4626
4627         /* QAM FSM Tracking Parameters */
4628
4629         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4630         if (status < 0)
4631                 goto error;
4632         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4633         if (status < 0)
4634                 goto error;
4635         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4636         if (status < 0)
4637                 goto error;
4638         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4639         if (status < 0)
4640                 goto error;
4641         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4642         if (status < 0)
4643                 goto error;
4644         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4645         if (status < 0)
4646                 goto error;
4647         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4648 error:
4649         if (status < 0)
4650                 pr_err("Error %d on %s\n", status, __func__);
4651         return status;
4652 }
4653
4654 /*============================================================================*/
4655
4656 /*
4657 * \brief QAM64 specific setup
4658 * \param demod instance of demod.
4659 * \return DRXStatus_t.
4660 */
4661 static int set_qam64(struct drxk_state *state)
4662 {
4663         int status = 0;
4664
4665         dprintk(1, "\n");
4666         /* QAM Equalizer Setup */
4667         /* Equalizer */
4668         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4669         if (status < 0)
4670                 goto error;
4671         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4672         if (status < 0)
4673                 goto error;
4674         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4675         if (status < 0)
4676                 goto error;
4677         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4678         if (status < 0)
4679                 goto error;
4680         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4681         if (status < 0)
4682                 goto error;
4683         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4684         if (status < 0)
4685                 goto error;
4686
4687         /* Decision Feedback Equalizer */
4688         status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4689         if (status < 0)
4690                 goto error;
4691         status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4692         if (status < 0)
4693                 goto error;
4694         status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4695         if (status < 0)
4696                 goto error;
4697         status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4698         if (status < 0)
4699                 goto error;
4700         status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4701         if (status < 0)
4702                 goto error;
4703         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4704         if (status < 0)
4705                 goto error;
4706
4707         status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4708         if (status < 0)
4709                 goto error;
4710         status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4711         if (status < 0)
4712                 goto error;
4713         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4714         if (status < 0)
4715                 goto error;
4716
4717         /* QAM Slicer Settings */
4718         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4719                          DRXK_QAM_SL_SIG_POWER_QAM64);
4720         if (status < 0)
4721                 goto error;
4722
4723
4724         /* QAM Loop Controller Coeficients */
4725
4726         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4727         if (status < 0)
4728                 goto error;
4729         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4730         if (status < 0)
4731                 goto error;
4732         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4733         if (status < 0)
4734                 goto error;
4735         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4736         if (status < 0)
4737                 goto error;
4738         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4739         if (status < 0)
4740                 goto error;
4741         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4742         if (status < 0)
4743                 goto error;
4744         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4745         if (status < 0)
4746                 goto error;
4747         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4748         if (status < 0)
4749                 goto error;
4750
4751         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4752         if (status < 0)
4753                 goto error;
4754         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4755         if (status < 0)
4756                 goto error;
4757         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4758         if (status < 0)
4759                 goto error;
4760         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4761         if (status < 0)
4762                 goto error;
4763         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4764         if (status < 0)
4765                 goto error;
4766         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4767         if (status < 0)
4768                 goto error;
4769         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4770         if (status < 0)
4771                 goto error;
4772         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4773         if (status < 0)
4774                 goto error;
4775         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4776         if (status < 0)
4777                 goto error;
4778         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4779         if (status < 0)
4780                 goto error;
4781         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4782         if (status < 0)
4783                 goto error;
4784         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4785         if (status < 0)
4786                 goto error;
4787
4788
4789         /* QAM State Machine (FSM) Thresholds */
4790
4791         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4792         if (status < 0)
4793                 goto error;
4794         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4795         if (status < 0)
4796                 goto error;
4797         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4798         if (status < 0)
4799                 goto error;
4800         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4801         if (status < 0)
4802                 goto error;
4803         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4804         if (status < 0)
4805                 goto error;
4806         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4807         if (status < 0)
4808                 goto error;
4809
4810         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4811         if (status < 0)
4812                 goto error;
4813         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4814         if (status < 0)
4815                 goto error;
4816         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4817         if (status < 0)
4818                 goto error;
4819
4820
4821         /* QAM FSM Tracking Parameters */
4822
4823         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4824         if (status < 0)
4825                 goto error;
4826         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4827         if (status < 0)
4828                 goto error;
4829         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4830         if (status < 0)
4831                 goto error;
4832         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4833         if (status < 0)
4834                 goto error;
4835         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4836         if (status < 0)
4837                 goto error;
4838         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4839         if (status < 0)
4840                 goto error;
4841         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4842 error:
4843         if (status < 0)
4844                 pr_err("Error %d on %s\n", status, __func__);
4845
4846         return status;
4847 }
4848
4849 /*============================================================================*/
4850
4851 /*
4852 * \brief QAM128 specific setup
4853 * \param demod: instance of demod.
4854 * \return DRXStatus_t.
4855 */
4856 static int set_qam128(struct drxk_state *state)
4857 {
4858         int status = 0;
4859
4860         dprintk(1, "\n");
4861         /* QAM Equalizer Setup */
4862         /* Equalizer */
4863         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4864         if (status < 0)
4865                 goto error;
4866         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4867         if (status < 0)
4868                 goto error;
4869         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4870         if (status < 0)
4871                 goto error;
4872         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4873         if (status < 0)
4874                 goto error;
4875         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4876         if (status < 0)
4877                 goto error;
4878         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4879         if (status < 0)
4880                 goto error;
4881
4882         /* Decision Feedback Equalizer */
4883         status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4884         if (status < 0)
4885                 goto error;
4886         status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4887         if (status < 0)
4888                 goto error;
4889         status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4890         if (status < 0)
4891                 goto error;
4892         status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4893         if (status < 0)
4894                 goto error;
4895         status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4896         if (status < 0)
4897                 goto error;
4898         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4899         if (status < 0)
4900                 goto error;
4901
4902         status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4903         if (status < 0)
4904                 goto error;
4905         status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4906         if (status < 0)
4907                 goto error;
4908         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4909         if (status < 0)
4910                 goto error;
4911
4912
4913         /* QAM Slicer Settings */
4914
4915         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4916                          DRXK_QAM_SL_SIG_POWER_QAM128);
4917         if (status < 0)
4918                 goto error;
4919
4920
4921         /* QAM Loop Controller Coeficients */
4922
4923         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4924         if (status < 0)
4925                 goto error;
4926         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4927         if (status < 0)
4928                 goto error;
4929         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4930         if (status < 0)
4931                 goto error;
4932         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4933         if (status < 0)
4934                 goto error;
4935         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4936         if (status < 0)
4937                 goto error;
4938         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4939         if (status < 0)
4940                 goto error;
4941         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4942         if (status < 0)
4943                 goto error;
4944         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4945         if (status < 0)
4946                 goto error;
4947
4948         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4949         if (status < 0)
4950                 goto error;
4951         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4952         if (status < 0)
4953                 goto error;
4954         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4955         if (status < 0)
4956                 goto error;
4957         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4958         if (status < 0)
4959                 goto error;
4960         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4961         if (status < 0)
4962                 goto error;
4963         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4964         if (status < 0)
4965                 goto error;
4966         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4967         if (status < 0)
4968                 goto error;
4969         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4970         if (status < 0)
4971                 goto error;
4972         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4973         if (status < 0)
4974                 goto error;
4975         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4976         if (status < 0)
4977                 goto error;
4978         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4979         if (status < 0)
4980                 goto error;
4981         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4982         if (status < 0)
4983                 goto error;
4984
4985
4986         /* QAM State Machine (FSM) Thresholds */
4987
4988         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4989         if (status < 0)
4990                 goto error;
4991         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4992         if (status < 0)
4993                 goto error;
4994         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4995         if (status < 0)
4996                 goto error;
4997         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4998         if (status < 0)
4999                 goto error;
5000         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5001         if (status < 0)
5002                 goto error;
5003         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5004         if (status < 0)
5005                 goto error;
5006
5007         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5008         if (status < 0)
5009                 goto error;
5010         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5011         if (status < 0)
5012                 goto error;
5013
5014         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5015         if (status < 0)
5016                 goto error;
5017
5018         /* QAM FSM Tracking Parameters */
5019
5020         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5021         if (status < 0)
5022                 goto error;
5023         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5024         if (status < 0)
5025                 goto error;
5026         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5027         if (status < 0)
5028                 goto error;
5029         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5030         if (status < 0)
5031                 goto error;
5032         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5033         if (status < 0)
5034                 goto error;
5035         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5036         if (status < 0)
5037                 goto error;
5038         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5039 error:
5040         if (status < 0)
5041                 pr_err("Error %d on %s\n", status, __func__);
5042
5043         return status;
5044 }
5045
5046 /*============================================================================*/
5047
5048 /*
5049 * \brief QAM256 specific setup
5050 * \param demod: instance of demod.
5051 * \return DRXStatus_t.
5052 */
5053 static int set_qam256(struct drxk_state *state)
5054 {
5055         int status = 0;
5056
5057         dprintk(1, "\n");
5058         /* QAM Equalizer Setup */
5059         /* Equalizer */
5060         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5061         if (status < 0)
5062                 goto error;
5063         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5064         if (status < 0)
5065                 goto error;
5066         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5067         if (status < 0)
5068                 goto error;
5069         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5070         if (status < 0)
5071                 goto error;
5072         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5073         if (status < 0)
5074                 goto error;
5075         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5076         if (status < 0)
5077                 goto error;
5078
5079         /* Decision Feedback Equalizer */
5080         status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5081         if (status < 0)
5082                 goto error;
5083         status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5084         if (status < 0)
5085                 goto error;
5086         status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5087         if (status < 0)
5088                 goto error;
5089         status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5090         if (status < 0)
5091                 goto error;
5092         status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5093         if (status < 0)
5094                 goto error;
5095         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5096         if (status < 0)
5097                 goto error;
5098
5099         status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5100         if (status < 0)
5101                 goto error;
5102         status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5103         if (status < 0)
5104                 goto error;
5105         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5106         if (status < 0)
5107                 goto error;
5108
5109         /* QAM Slicer Settings */
5110
5111         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5112                          DRXK_QAM_SL_SIG_POWER_QAM256);
5113         if (status < 0)
5114                 goto error;
5115
5116
5117         /* QAM Loop Controller Coeficients */
5118
5119         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5120         if (status < 0)
5121                 goto error;
5122         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5123         if (status < 0)
5124                 goto error;
5125         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5126         if (status < 0)
5127                 goto error;
5128         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5129         if (status < 0)
5130                 goto error;
5131         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5132         if (status < 0)
5133                 goto error;
5134         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5135         if (status < 0)
5136                 goto error;
5137         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5138         if (status < 0)
5139                 goto error;
5140         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5141         if (status < 0)
5142                 goto error;
5143
5144         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5145         if (status < 0)
5146                 goto error;
5147         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5148         if (status < 0)
5149                 goto error;
5150         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5151         if (status < 0)
5152                 goto error;
5153         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5154         if (status < 0)
5155                 goto error;
5156         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5157         if (status < 0)
5158                 goto error;
5159         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5160         if (status < 0)
5161                 goto error;
5162         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5163         if (status < 0)
5164                 goto error;
5165         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5166         if (status < 0)
5167                 goto error;
5168         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5169         if (status < 0)
5170                 goto error;
5171         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5172         if (status < 0)
5173                 goto error;
5174         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5175         if (status < 0)
5176                 goto error;
5177         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5178         if (status < 0)
5179                 goto error;
5180
5181
5182         /* QAM State Machine (FSM) Thresholds */
5183
5184         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5185         if (status < 0)
5186                 goto error;
5187         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5188         if (status < 0)
5189                 goto error;
5190         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5191         if (status < 0)
5192                 goto error;
5193         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5194         if (status < 0)
5195                 goto error;
5196         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5197         if (status < 0)
5198                 goto error;
5199         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5200         if (status < 0)
5201                 goto error;
5202
5203         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5204         if (status < 0)
5205                 goto error;
5206         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5207         if (status < 0)
5208                 goto error;
5209         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5210         if (status < 0)
5211                 goto error;
5212
5213
5214         /* QAM FSM Tracking Parameters */
5215
5216         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5217         if (status < 0)
5218                 goto error;
5219         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5220         if (status < 0)
5221                 goto error;
5222         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5223         if (status < 0)
5224                 goto error;
5225         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5226         if (status < 0)
5227                 goto error;
5228         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5229         if (status < 0)
5230                 goto error;
5231         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5232         if (status < 0)
5233                 goto error;
5234         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5235 error:
5236         if (status < 0)
5237                 pr_err("Error %d on %s\n", status, __func__);
5238         return status;
5239 }
5240
5241
5242 /*============================================================================*/
5243 /*
5244 * \brief Reset QAM block.
5245 * \param demod:   instance of demod.
5246 * \param channel: pointer to channel data.
5247 * \return DRXStatus_t.
5248 */
5249 static int qam_reset_qam(struct drxk_state *state)
5250 {
5251         int status;
5252         u16 cmd_result;
5253
5254         dprintk(1, "\n");
5255         /* Stop QAM comstate->m_exec */
5256         status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5257         if (status < 0)
5258                 goto error;
5259
5260         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5261                              | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
5262                              0, NULL, 1, &cmd_result);
5263 error:
5264         if (status < 0)
5265                 pr_err("Error %d on %s\n", status, __func__);
5266         return status;
5267 }
5268
5269 /*============================================================================*/
5270
5271 /*
5272 * \brief Set QAM symbolrate.
5273 * \param demod:   instance of demod.
5274 * \param channel: pointer to channel data.
5275 * \return DRXStatus_t.
5276 */
5277 static int qam_set_symbolrate(struct drxk_state *state)
5278 {
5279         u32 adc_frequency = 0;
5280         u32 symb_freq = 0;
5281         u32 iqm_rc_rate = 0;
5282         u16 ratesel = 0;
5283         u32 lc_symb_rate = 0;
5284         int status;
5285
5286         dprintk(1, "\n");
5287         /* Select & calculate correct IQM rate */
5288         adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5289         ratesel = 0;
5290         if (state->props.symbol_rate <= 1188750)
5291                 ratesel = 3;
5292         else if (state->props.symbol_rate <= 2377500)
5293                 ratesel = 2;
5294         else if (state->props.symbol_rate <= 4755000)
5295                 ratesel = 1;
5296         status = write16(state, IQM_FD_RATESEL__A, ratesel);
5297         if (status < 0)
5298                 goto error;
5299
5300         /*
5301                 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5302                 */
5303         symb_freq = state->props.symbol_rate * (1 << ratesel);
5304         if (symb_freq == 0) {
5305                 /* Divide by zero */
5306                 status = -EINVAL;
5307                 goto error;
5308         }
5309         iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
5310                 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) -
5311                 (1 << 23);
5312         status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5313         if (status < 0)
5314                 goto error;
5315         state->m_iqm_rc_rate = iqm_rc_rate;
5316         /*
5317                 LcSymbFreq = round (.125 *  symbolrate / adc_freq * (1<<15))
5318                 */
5319         symb_freq = state->props.symbol_rate;
5320         if (adc_frequency == 0) {
5321                 /* Divide by zero */
5322                 status = -EINVAL;
5323                 goto error;
5324         }
5325         lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
5326                 (Frac28a((symb_freq % adc_frequency), adc_frequency) >>
5327                 16);
5328         if (lc_symb_rate > 511)
5329                 lc_symb_rate = 511;
5330         status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5331
5332 error:
5333         if (status < 0)
5334                 pr_err("Error %d on %s\n", status, __func__);
5335         return status;
5336 }
5337
5338 /*============================================================================*/
5339
5340 /*
5341 * \brief Get QAM lock status.
5342 * \param demod:   instance of demod.
5343 * \param channel: pointer to channel data.
5344 * \return DRXStatus_t.
5345 */
5346
5347 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5348 {
5349         int status;
5350         u16 result[2] = { 0, 0 };
5351
5352         dprintk(1, "\n");
5353         *p_lock_status = NOT_LOCKED;
5354         status = scu_command(state,
5355                         SCU_RAM_COMMAND_STANDARD_QAM |
5356                         SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5357                         result);
5358         if (status < 0)
5359                 pr_err("Error %d on %s\n", status, __func__);
5360
5361         if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5362                 /* 0x0000 NOT LOCKED */
5363         } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5364                 /* 0x4000 DEMOD LOCKED */
5365                 *p_lock_status = DEMOD_LOCK;
5366         } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5367                 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5368                 *p_lock_status = MPEG_LOCK;
5369         } else {
5370                 /* 0xC000 NEVER LOCKED */
5371                 /* (system will never be able to lock to the signal) */
5372                 /*
5373                  * TODO: check this, intermediate & standard specific lock
5374                  * states are not taken into account here
5375                  */
5376                 *p_lock_status = NEVER_LOCK;
5377         }
5378         return status;
5379 }
5380
5381 #define QAM_MIRROR__M         0x03
5382 #define QAM_MIRROR_NORMAL     0x00
5383 #define QAM_MIRRORED          0x01
5384 #define QAM_MIRROR_AUTO_ON    0x02
5385 #define QAM_LOCKRANGE__M      0x10
5386 #define QAM_LOCKRANGE_NORMAL  0x10
5387
5388 static int qam_demodulator_command(struct drxk_state *state,
5389                                  int number_of_parameters)
5390 {
5391         int status;
5392         u16 cmd_result;
5393         u16 set_param_parameters[4] = { 0, 0, 0, 0 };
5394
5395         set_param_parameters[0] = state->m_constellation;       /* modulation     */
5396         set_param_parameters[1] = DRXK_QAM_I12_J17;     /* interleave mode   */
5397
5398         if (number_of_parameters == 2) {
5399                 u16 set_env_parameters[1] = { 0 };
5400
5401                 if (state->m_operation_mode == OM_QAM_ITU_C)
5402                         set_env_parameters[0] = QAM_TOP_ANNEX_C;
5403                 else
5404                         set_env_parameters[0] = QAM_TOP_ANNEX_A;
5405
5406                 status = scu_command(state,
5407                                      SCU_RAM_COMMAND_STANDARD_QAM
5408                                      | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5409                                      1, set_env_parameters, 1, &cmd_result);
5410                 if (status < 0)
5411                         goto error;
5412
5413                 status = scu_command(state,
5414                                      SCU_RAM_COMMAND_STANDARD_QAM
5415                                      | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5416                                      number_of_parameters, set_param_parameters,
5417                                      1, &cmd_result);
5418         } else if (number_of_parameters == 4) {
5419                 if (state->m_operation_mode == OM_QAM_ITU_C)
5420                         set_param_parameters[2] = QAM_TOP_ANNEX_C;
5421                 else
5422                         set_param_parameters[2] = QAM_TOP_ANNEX_A;
5423
5424                 set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
5425                 /* Env parameters */
5426                 /* check for LOCKRANGE Extended */
5427                 /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
5428
5429                 status = scu_command(state,
5430                                      SCU_RAM_COMMAND_STANDARD_QAM
5431                                      | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5432                                      number_of_parameters, set_param_parameters,
5433                                      1, &cmd_result);
5434         } else {
5435                 pr_warn("Unknown QAM demodulator parameter count %d\n",
5436                         number_of_parameters);
5437                 status = -EINVAL;
5438         }
5439
5440 error:
5441         if (status < 0)
5442                 pr_warn("Warning %d on %s\n", status, __func__);
5443         return status;
5444 }
5445
5446 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5447                   s32 tuner_freq_offset)
5448 {
5449         int status;
5450         u16 cmd_result;
5451         int qam_demod_param_count = state->qam_demod_parameter_count;
5452
5453         dprintk(1, "\n");
5454         /*
5455          * STEP 1: reset demodulator
5456          *      resets FEC DI and FEC RS
5457          *      resets QAM block
5458          *      resets SCU variables
5459          */
5460         status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5461         if (status < 0)
5462                 goto error;
5463         status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5464         if (status < 0)
5465                 goto error;
5466         status = qam_reset_qam(state);
5467         if (status < 0)
5468                 goto error;
5469
5470         /*
5471          * STEP 2: configure demodulator
5472          *      -set params; resets IQM,QAM,FEC HW; initializes some
5473          *       SCU variables
5474          */
5475         status = qam_set_symbolrate(state);
5476         if (status < 0)
5477                 goto error;
5478
5479         /* Set params */
5480         switch (state->props.modulation) {
5481         case QAM_256:
5482                 state->m_constellation = DRX_CONSTELLATION_QAM256;
5483                 break;
5484         case QAM_AUTO:
5485         case QAM_64:
5486                 state->m_constellation = DRX_CONSTELLATION_QAM64;
5487                 break;
5488         case QAM_16:
5489                 state->m_constellation = DRX_CONSTELLATION_QAM16;
5490                 break;
5491         case QAM_32:
5492                 state->m_constellation = DRX_CONSTELLATION_QAM32;
5493                 break;
5494         case QAM_128:
5495                 state->m_constellation = DRX_CONSTELLATION_QAM128;
5496                 break;
5497         default:
5498                 status = -EINVAL;
5499                 break;
5500         }
5501         if (status < 0)
5502                 goto error;
5503
5504         /* Use the 4-parameter if it's requested or we're probing for
5505          * the correct command. */
5506         if (state->qam_demod_parameter_count == 4
5507                 || !state->qam_demod_parameter_count) {
5508                 qam_demod_param_count = 4;
5509                 status = qam_demodulator_command(state, qam_demod_param_count);
5510         }
5511
5512         /* Use the 2-parameter command if it was requested or if we're
5513          * probing for the correct command and the 4-parameter command
5514          * failed. */
5515         if (state->qam_demod_parameter_count == 2
5516                 || (!state->qam_demod_parameter_count && status < 0)) {
5517                 qam_demod_param_count = 2;
5518                 status = qam_demodulator_command(state, qam_demod_param_count);
5519         }
5520
5521         if (status < 0) {
5522                 dprintk(1, "Could not set demodulator parameters.\n");
5523                 dprintk(1,
5524                         "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n",
5525                         state->qam_demod_parameter_count,
5526                         state->microcode_name);
5527                 goto error;
5528         } else if (!state->qam_demod_parameter_count) {
5529                 dprintk(1,
5530                         "Auto-probing the QAM command parameters was successful - using %d parameters.\n",
5531                         qam_demod_param_count);
5532
5533                 /*
5534                  * One of our commands was successful. We don't need to
5535                  * auto-probe anymore, now that we got the correct command.
5536                  */
5537                 state->qam_demod_parameter_count = qam_demod_param_count;
5538         }
5539
5540         /*
5541          * STEP 3: enable the system in a mode where the ADC provides valid
5542          * signal setup modulation independent registers
5543          */
5544 #if 0
5545         status = set_frequency(channel, tuner_freq_offset));
5546         if (status < 0)
5547                 goto error;
5548 #endif
5549         status = set_frequency_shifter(state, intermediate_freqk_hz,
5550                                        tuner_freq_offset, true);
5551         if (status < 0)
5552                 goto error;
5553
5554         /* Setup BER measurement */
5555         status = set_qam_measurement(state, state->m_constellation,
5556                                      state->props.symbol_rate);
5557         if (status < 0)
5558                 goto error;
5559
5560         /* Reset default values */
5561         status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5562         if (status < 0)
5563                 goto error;
5564         status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5565         if (status < 0)
5566                 goto error;
5567
5568         /* Reset default LC values */
5569         status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5570         if (status < 0)
5571                 goto error;
5572         status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5573         if (status < 0)
5574                 goto error;
5575         status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5576         if (status < 0)
5577                 goto error;
5578         status = write16(state, QAM_LC_MODE__A, 7);
5579         if (status < 0)
5580                 goto error;
5581
5582         status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5583         if (status < 0)
5584                 goto error;
5585         status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5586         if (status < 0)
5587                 goto error;
5588         status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5589         if (status < 0)
5590                 goto error;
5591         status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5592         if (status < 0)
5593                 goto error;
5594         status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5595         if (status < 0)
5596                 goto error;
5597         status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5598         if (status < 0)
5599                 goto error;
5600         status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5601         if (status < 0)
5602                 goto error;
5603         status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5604         if (status < 0)
5605                 goto error;
5606         status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5607         if (status < 0)
5608                 goto error;
5609         status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5610         if (status < 0)
5611                 goto error;
5612         status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5613         if (status < 0)
5614                 goto error;
5615         status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5616         if (status < 0)
5617                 goto error;
5618         status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5619         if (status < 0)
5620                 goto error;
5621         status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5622         if (status < 0)
5623                 goto error;
5624         status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5625         if (status < 0)
5626                 goto error;
5627
5628         /* Mirroring, QAM-block starting point not inverted */
5629         status = write16(state, QAM_SY_SP_INV__A,
5630                          QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5631         if (status < 0)
5632                 goto error;
5633
5634         /* Halt SCU to enable safe non-atomic accesses */
5635         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5636         if (status < 0)
5637                 goto error;
5638
5639         /* STEP 4: modulation specific setup */
5640         switch (state->props.modulation) {
5641         case QAM_16:
5642                 status = set_qam16(state);
5643                 break;
5644         case QAM_32:
5645                 status = set_qam32(state);
5646                 break;
5647         case QAM_AUTO:
5648         case QAM_64:
5649                 status = set_qam64(state);
5650                 break;
5651         case QAM_128:
5652                 status = set_qam128(state);
5653                 break;
5654         case QAM_256:
5655                 status = set_qam256(state);
5656                 break;
5657         default:
5658                 status = -EINVAL;
5659                 break;
5660         }
5661         if (status < 0)
5662                 goto error;
5663
5664         /* Activate SCU to enable SCU commands */
5665         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5666         if (status < 0)
5667                 goto error;
5668
5669         /* Re-configure MPEG output, requires knowledge of channel bitrate */
5670         /* extAttr->currentChannel.modulation = channel->modulation; */
5671         /* extAttr->currentChannel.symbolrate    = channel->symbolrate; */
5672         status = mpegts_dto_setup(state, state->m_operation_mode);
5673         if (status < 0)
5674                 goto error;
5675
5676         /* start processes */
5677         status = mpegts_start(state);
5678         if (status < 0)
5679                 goto error;
5680         status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5681         if (status < 0)
5682                 goto error;
5683         status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5684         if (status < 0)
5685                 goto error;
5686         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5687         if (status < 0)
5688                 goto error;
5689
5690         /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5691         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5692                              | SCU_RAM_COMMAND_CMD_DEMOD_START,
5693                              0, NULL, 1, &cmd_result);
5694         if (status < 0)
5695                 goto error;
5696
5697         /* update global DRXK data container */
5698 /*?     extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5699
5700 error:
5701         if (status < 0)
5702                 pr_err("Error %d on %s\n", status, __func__);
5703         return status;
5704 }
5705
5706 static int set_qam_standard(struct drxk_state *state,
5707                           enum operation_mode o_mode)
5708 {
5709         int status;
5710 #ifdef DRXK_QAM_TAPS
5711 #define DRXK_QAMA_TAPS_SELECT
5712 #include "drxk_filters.h"
5713 #undef DRXK_QAMA_TAPS_SELECT
5714 #endif
5715
5716         dprintk(1, "\n");
5717
5718         /* added antenna switch */
5719         switch_antenna_to_qam(state);
5720
5721         /* Ensure correct power-up mode */
5722         status = power_up_qam(state);
5723         if (status < 0)
5724                 goto error;
5725         /* Reset QAM block */
5726         status = qam_reset_qam(state);
5727         if (status < 0)
5728                 goto error;
5729
5730         /* Setup IQM */
5731
5732         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5733         if (status < 0)
5734                 goto error;
5735         status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5736         if (status < 0)
5737                 goto error;
5738
5739         /* Upload IQM Channel Filter settings by
5740                 boot loader from ROM table */
5741         switch (o_mode) {
5742         case OM_QAM_ITU_A:
5743                 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5744                                       DRXK_BLCC_NR_ELEMENTS_TAPS,
5745                         DRXK_BLC_TIMEOUT);
5746                 break;
5747         case OM_QAM_ITU_C:
5748                 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5749                                        DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5750                                        DRXK_BLDC_NR_ELEMENTS_TAPS,
5751                                        DRXK_BLC_TIMEOUT);
5752                 if (status < 0)
5753                         goto error;
5754                 status = bl_direct_cmd(state,
5755                                        IQM_CF_TAP_IM0__A,
5756                                        DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5757                                        DRXK_BLDC_NR_ELEMENTS_TAPS,
5758                                        DRXK_BLC_TIMEOUT);
5759                 break;
5760         default:
5761                 status = -EINVAL;
5762         }
5763         if (status < 0)
5764                 goto error;
5765
5766         status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5767         if (status < 0)
5768                 goto error;
5769         status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5770         if (status < 0)
5771                 goto error;
5772         status = write16(state, IQM_CF_MIDTAP__A,
5773                      ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5774         if (status < 0)
5775                 goto error;
5776
5777         status = write16(state, IQM_RC_STRETCH__A, 21);
5778         if (status < 0)
5779                 goto error;
5780         status = write16(state, IQM_AF_CLP_LEN__A, 0);
5781         if (status < 0)
5782                 goto error;
5783         status = write16(state, IQM_AF_CLP_TH__A, 448);
5784         if (status < 0)
5785                 goto error;
5786         status = write16(state, IQM_AF_SNS_LEN__A, 0);
5787         if (status < 0)
5788                 goto error;
5789         status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5790         if (status < 0)
5791                 goto error;
5792
5793         status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5794         if (status < 0)
5795                 goto error;
5796         status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5797         if (status < 0)
5798                 goto error;
5799         status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5800         if (status < 0)
5801                 goto error;
5802         status = write16(state, IQM_AF_UPD_SEL__A, 0);
5803         if (status < 0)
5804                 goto error;
5805
5806         /* IQM Impulse Noise Processing Unit */
5807         status = write16(state, IQM_CF_CLP_VAL__A, 500);
5808         if (status < 0)
5809                 goto error;
5810         status = write16(state, IQM_CF_DATATH__A, 1000);
5811         if (status < 0)
5812                 goto error;
5813         status = write16(state, IQM_CF_BYPASSDET__A, 1);
5814         if (status < 0)
5815                 goto error;
5816         status = write16(state, IQM_CF_DET_LCT__A, 0);
5817         if (status < 0)
5818                 goto error;
5819         status = write16(state, IQM_CF_WND_LEN__A, 1);
5820         if (status < 0)
5821                 goto error;
5822         status = write16(state, IQM_CF_PKDTH__A, 1);
5823         if (status < 0)
5824                 goto error;
5825         status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5826         if (status < 0)
5827                 goto error;
5828
5829         /* turn on IQMAF. Must be done before setAgc**() */
5830         status = set_iqm_af(state, true);
5831         if (status < 0)
5832                 goto error;
5833         status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5834         if (status < 0)
5835                 goto error;
5836
5837         /* IQM will not be reset from here, sync ADC and update/init AGC */
5838         status = adc_synchronization(state);
5839         if (status < 0)
5840                 goto error;
5841
5842         /* Set the FSM step period */
5843         status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5844         if (status < 0)
5845                 goto error;
5846
5847         /* Halt SCU to enable safe non-atomic accesses */
5848         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5849         if (status < 0)
5850                 goto error;
5851
5852         /* No more resets of the IQM, current standard correctly set =>
5853                 now AGCs can be configured. */
5854
5855         status = init_agc(state, true);
5856         if (status < 0)
5857                 goto error;
5858         status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5859         if (status < 0)
5860                 goto error;
5861
5862         /* Configure AGC's */
5863         status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5864         if (status < 0)
5865                 goto error;
5866         status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5867         if (status < 0)
5868                 goto error;
5869
5870         /* Activate SCU to enable SCU commands */
5871         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5872 error:
5873         if (status < 0)
5874                 pr_err("Error %d on %s\n", status, __func__);
5875         return status;
5876 }
5877
5878 static int write_gpio(struct drxk_state *state)
5879 {
5880         int status;
5881         u16 value = 0;
5882
5883         dprintk(1, "\n");
5884         /* stop lock indicator process */
5885         status = write16(state, SCU_RAM_GPIO__A,
5886                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5887         if (status < 0)
5888                 goto error;
5889
5890         /*  Write magic word to enable pdr reg write               */
5891         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5892         if (status < 0)
5893                 goto error;
5894
5895         if (state->m_has_sawsw) {
5896                 if (state->uio_mask & 0x0001) { /* UIO-1 */
5897                         /* write to io pad configuration register - output mode */
5898                         status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5899                                          state->m_gpio_cfg);
5900                         if (status < 0)
5901                                 goto error;
5902
5903                         /* use corresponding bit in io data output registar */
5904                         status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5905                         if (status < 0)
5906                                 goto error;
5907                         if ((state->m_gpio & 0x0001) == 0)
5908                                 value &= 0x7FFF;        /* write zero to 15th bit - 1st UIO */
5909                         else
5910                                 value |= 0x8000;        /* write one to 15th bit - 1st UIO */
5911                         /* write back to io data output register */
5912                         status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5913                         if (status < 0)
5914                                 goto error;
5915                 }
5916                 if (state->uio_mask & 0x0002) { /* UIO-2 */
5917                         /* write to io pad configuration register - output mode */
5918                         status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5919                                          state->m_gpio_cfg);
5920                         if (status < 0)
5921                                 goto error;
5922
5923                         /* use corresponding bit in io data output registar */
5924                         status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5925                         if (status < 0)
5926                                 goto error;
5927                         if ((state->m_gpio & 0x0002) == 0)
5928                                 value &= 0xBFFF;        /* write zero to 14th bit - 2st UIO */
5929                         else
5930                                 value |= 0x4000;        /* write one to 14th bit - 2st UIO */
5931                         /* write back to io data output register */
5932                         status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5933                         if (status < 0)
5934                                 goto error;
5935                 }
5936                 if (state->uio_mask & 0x0004) { /* UIO-3 */
5937                         /* write to io pad configuration register - output mode */
5938                         status = write16(state, SIO_PDR_GPIO_CFG__A,
5939                                          state->m_gpio_cfg);
5940                         if (status < 0)
5941                                 goto error;
5942
5943                         /* use corresponding bit in io data output registar */
5944                         status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5945                         if (status < 0)
5946                                 goto error;
5947                         if ((state->m_gpio & 0x0004) == 0)
5948                                 value &= 0xFFFB;            /* write zero to 2nd bit - 3rd UIO */
5949                         else
5950                                 value |= 0x0004;            /* write one to 2nd bit - 3rd UIO */
5951                         /* write back to io data output register */
5952                         status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5953                         if (status < 0)
5954                                 goto error;
5955                 }
5956         }
5957         /*  Write magic word to disable pdr reg write               */
5958         status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5959 error:
5960         if (status < 0)
5961                 pr_err("Error %d on %s\n", status, __func__);
5962         return status;
5963 }
5964
5965 static int switch_antenna_to_qam(struct drxk_state *state)
5966 {
5967         int status = 0;
5968         bool gpio_state;
5969
5970         dprintk(1, "\n");
5971
5972         if (!state->antenna_gpio)
5973                 return 0;
5974
5975         gpio_state = state->m_gpio & state->antenna_gpio;
5976
5977         if (state->antenna_dvbt ^ gpio_state) {
5978                 /* Antenna is on DVB-T mode. Switch */
5979                 if (state->antenna_dvbt)
5980                         state->m_gpio &= ~state->antenna_gpio;
5981                 else
5982                         state->m_gpio |= state->antenna_gpio;
5983                 status = write_gpio(state);
5984         }
5985         if (status < 0)
5986                 pr_err("Error %d on %s\n", status, __func__);
5987         return status;
5988 }
5989
5990 static int switch_antenna_to_dvbt(struct drxk_state *state)
5991 {
5992         int status = 0;
5993         bool gpio_state;
5994
5995         dprintk(1, "\n");
5996
5997         if (!state->antenna_gpio)
5998                 return 0;
5999
6000         gpio_state = state->m_gpio & state->antenna_gpio;
6001
6002         if (!(state->antenna_dvbt ^ gpio_state)) {
6003                 /* Antenna is on DVB-C mode. Switch */
6004                 if (state->antenna_dvbt)
6005                         state->m_gpio |= state->antenna_gpio;
6006                 else
6007                         state->m_gpio &= ~state->antenna_gpio;
6008                 status = write_gpio(state);
6009         }
6010         if (status < 0)
6011                 pr_err("Error %d on %s\n", status, __func__);
6012         return status;
6013 }
6014
6015
6016 static int power_down_device(struct drxk_state *state)
6017 {
6018         /* Power down to requested mode */
6019         /* Backup some register settings */
6020         /* Set pins with possible pull-ups connected to them in input mode */
6021         /* Analog power down */
6022         /* ADC power down */
6023         /* Power down device */
6024         int status;
6025
6026         dprintk(1, "\n");
6027         if (state->m_b_p_down_open_bridge) {
6028                 /* Open I2C bridge before power down of DRXK */
6029                 status = ConfigureI2CBridge(state, true);
6030                 if (status < 0)
6031                         goto error;
6032         }
6033         /* driver 0.9.0 */
6034         status = dvbt_enable_ofdm_token_ring(state, false);
6035         if (status < 0)
6036                 goto error;
6037
6038         status = write16(state, SIO_CC_PWD_MODE__A,
6039                          SIO_CC_PWD_MODE_LEVEL_CLOCK);
6040         if (status < 0)
6041                 goto error;
6042         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6043         if (status < 0)
6044                 goto error;
6045         state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
6046         status = hi_cfg_command(state);
6047 error:
6048         if (status < 0)
6049                 pr_err("Error %d on %s\n", status, __func__);
6050
6051         return status;
6052 }
6053
6054 static int init_drxk(struct drxk_state *state)
6055 {
6056         int status = 0, n = 0;
6057         enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
6058         u16 driver_version;
6059
6060         dprintk(1, "\n");
6061         if (state->m_drxk_state == DRXK_UNINITIALIZED) {
6062                 drxk_i2c_lock(state);
6063                 status = power_up_device(state);
6064                 if (status < 0)
6065                         goto error;
6066                 status = drxx_open(state);
6067                 if (status < 0)
6068                         goto error;
6069                 /* Soft reset of OFDM-, sys- and osc-clockdomain */
6070                 status = write16(state, SIO_CC_SOFT_RST__A,
6071                                  SIO_CC_SOFT_RST_OFDM__M
6072                                  | SIO_CC_SOFT_RST_SYS__M
6073                                  | SIO_CC_SOFT_RST_OSC__M);
6074                 if (status < 0)
6075                         goto error;
6076                 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6077                 if (status < 0)
6078                         goto error;
6079                 /*
6080                  * TODO is this needed? If yes, how much delay in
6081                  * worst case scenario
6082                  */
6083                 usleep_range(1000, 2000);
6084                 state->m_drxk_a3_patch_code = true;
6085                 status = get_device_capabilities(state);
6086                 if (status < 0)
6087                         goto error;
6088
6089                 /* Bridge delay, uses oscilator clock */
6090                 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6091                 /* SDA brdige delay */
6092                 state->m_hi_cfg_bridge_delay =
6093                         (u16) ((state->m_osc_clock_freq / 1000) *
6094                                 HI_I2C_BRIDGE_DELAY) / 1000;
6095                 /* Clipping */
6096                 if (state->m_hi_cfg_bridge_delay >
6097                         SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6098                         state->m_hi_cfg_bridge_delay =
6099                                 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6100                 }
6101                 /* SCL bridge delay, same as SDA for now */
6102                 state->m_hi_cfg_bridge_delay +=
6103                         state->m_hi_cfg_bridge_delay <<
6104                         SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6105
6106                 status = init_hi(state);
6107                 if (status < 0)
6108                         goto error;
6109                 /* disable various processes */
6110 #if NOA1ROM
6111                 if (!(state->m_DRXK_A1_ROM_CODE)
6112                         && !(state->m_DRXK_A2_ROM_CODE))
6113 #endif
6114                 {
6115                         status = write16(state, SCU_RAM_GPIO__A,
6116                                          SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6117                         if (status < 0)
6118                                 goto error;
6119                 }
6120
6121                 /* disable MPEG port */
6122                 status = mpegts_disable(state);
6123                 if (status < 0)
6124                         goto error;
6125
6126                 /* Stop AUD and SCU */
6127                 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6128                 if (status < 0)
6129                         goto error;
6130                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6131                 if (status < 0)
6132                         goto error;
6133
6134                 /* enable token-ring bus through OFDM block for possible ucode upload */
6135                 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6136                                  SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6137                 if (status < 0)
6138                         goto error;
6139
6140                 /* include boot loader section */
6141                 status = write16(state, SIO_BL_COMM_EXEC__A,
6142                                  SIO_BL_COMM_EXEC_ACTIVE);
6143                 if (status < 0)
6144                         goto error;
6145                 status = bl_chain_cmd(state, 0, 6, 100);
6146                 if (status < 0)
6147                         goto error;
6148
6149                 if (state->fw) {
6150                         status = download_microcode(state, state->fw->data,
6151                                                    state->fw->size);
6152                         if (status < 0)
6153                                 goto error;
6154                 }
6155
6156                 /* disable token-ring bus through OFDM block for possible ucode upload */
6157                 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6158                                  SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6159                 if (status < 0)
6160                         goto error;
6161
6162                 /* Run SCU for a little while to initialize microcode version numbers */
6163                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6164                 if (status < 0)
6165                         goto error;
6166                 status = drxx_open(state);
6167                 if (status < 0)
6168                         goto error;
6169                 /* added for test */
6170                 msleep(30);
6171
6172                 power_mode = DRXK_POWER_DOWN_OFDM;
6173                 status = ctrl_power_mode(state, &power_mode);
6174                 if (status < 0)
6175                         goto error;
6176
6177                 /* Stamp driver version number in SCU data RAM in BCD code
6178                         Done to enable field application engineers to retrieve drxdriver version
6179                         via I2C from SCU RAM.
6180                         Not using SCU command interface for SCU register access since no
6181                         microcode may be present.
6182                         */
6183                 driver_version =
6184                         (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6185                         (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6186                         ((DRXK_VERSION_MAJOR % 10) << 4) +
6187                         (DRXK_VERSION_MINOR % 10);
6188                 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6189                                  driver_version);
6190                 if (status < 0)
6191                         goto error;
6192                 driver_version =
6193                         (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6194                         (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6195                         (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6196                         (DRXK_VERSION_PATCH % 10);
6197                 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6198                                  driver_version);
6199                 if (status < 0)
6200                         goto error;
6201
6202                 pr_info("DRXK driver version %d.%d.%d\n",
6203                         DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6204                         DRXK_VERSION_PATCH);
6205
6206                 /*
6207                  * Dirty fix of default values for ROM/PATCH microcode
6208                  * Dirty because this fix makes it impossible to setup
6209                  * suitable values before calling DRX_Open. This solution
6210                  * requires changes to RF AGC speed to be done via the CTRL
6211                  * function after calling DRX_Open
6212                  */
6213
6214                 /* m_dvbt_rf_agc_cfg.speed = 3; */
6215
6216                 /* Reset driver debug flags to 0 */
6217                 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6218                 if (status < 0)
6219                         goto error;
6220                 /* driver 0.9.0 */
6221                 /* Setup FEC OC:
6222                         NOTE: No more full FEC resets allowed afterwards!! */
6223                 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6224                 if (status < 0)
6225                         goto error;
6226                 /* MPEGTS functions are still the same */
6227                 status = mpegts_dto_init(state);
6228                 if (status < 0)
6229                         goto error;
6230                 status = mpegts_stop(state);
6231                 if (status < 0)
6232                         goto error;
6233                 status = mpegts_configure_polarity(state);
6234                 if (status < 0)
6235                         goto error;
6236                 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6237                 if (status < 0)
6238                         goto error;
6239                 /* added: configure GPIO */
6240                 status = write_gpio(state);
6241                 if (status < 0)
6242                         goto error;
6243
6244                 state->m_drxk_state = DRXK_STOPPED;
6245
6246                 if (state->m_b_power_down) {
6247                         status = power_down_device(state);
6248                         if (status < 0)
6249                                 goto error;
6250                         state->m_drxk_state = DRXK_POWERED_DOWN;
6251                 } else
6252                         state->m_drxk_state = DRXK_STOPPED;
6253
6254                 /* Initialize the supported delivery systems */
6255                 n = 0;
6256                 if (state->m_has_dvbc) {
6257                         state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6258                         state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6259                         strlcat(state->frontend.ops.info.name, " DVB-C",
6260                                 sizeof(state->frontend.ops.info.name));
6261                 }
6262                 if (state->m_has_dvbt) {
6263                         state->frontend.ops.delsys[n++] = SYS_DVBT;
6264                         strlcat(state->frontend.ops.info.name, " DVB-T",
6265                                 sizeof(state->frontend.ops.info.name));
6266                 }
6267                 drxk_i2c_unlock(state);
6268         }
6269 error:
6270         if (status < 0) {
6271                 state->m_drxk_state = DRXK_NO_DEV;
6272                 drxk_i2c_unlock(state);
6273                 pr_err("Error %d on %s\n", status, __func__);
6274         }
6275
6276         return status;
6277 }
6278
6279 static void load_firmware_cb(const struct firmware *fw,
6280                              void *context)
6281 {
6282         struct drxk_state *state = context;
6283
6284         dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6285         if (!fw) {
6286                 pr_err("Could not load firmware file %s.\n",
6287                         state->microcode_name);
6288                 pr_info("Copy %s to your hotplug directory!\n",
6289                         state->microcode_name);
6290                 state->microcode_name = NULL;
6291
6292                 /*
6293                  * As firmware is now load asynchronous, it is not possible
6294                  * anymore to fail at frontend attach. We might silently
6295                  * return here, and hope that the driver won't crash.
6296                  * We might also change all DVB callbacks to return -ENODEV
6297                  * if the device is not initialized.
6298                  * As the DRX-K devices have their own internal firmware,
6299                  * let's just hope that it will match a firmware revision
6300                  * compatible with this driver and proceed.
6301                  */
6302         }
6303         state->fw = fw;
6304
6305         init_drxk(state);
6306 }
6307
6308 static void drxk_release(struct dvb_frontend *fe)
6309 {
6310         struct drxk_state *state = fe->demodulator_priv;
6311
6312         dprintk(1, "\n");
6313         release_firmware(state->fw);
6314
6315         kfree(state);
6316 }
6317
6318 static int drxk_sleep(struct dvb_frontend *fe)
6319 {
6320         struct drxk_state *state = fe->demodulator_priv;
6321
6322         dprintk(1, "\n");
6323
6324         if (state->m_drxk_state == DRXK_NO_DEV)
6325                 return -ENODEV;
6326         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6327                 return 0;
6328
6329         shut_down(state);
6330         return 0;
6331 }
6332
6333 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6334 {
6335         struct drxk_state *state = fe->demodulator_priv;
6336
6337         dprintk(1, ": %s\n", enable ? "enable" : "disable");
6338
6339         if (state->m_drxk_state == DRXK_NO_DEV)
6340                 return -ENODEV;
6341
6342         return ConfigureI2CBridge(state, enable ? true : false);
6343 }
6344
6345 static int drxk_set_parameters(struct dvb_frontend *fe)
6346 {
6347         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6348         u32 delsys  = p->delivery_system, old_delsys;
6349         struct drxk_state *state = fe->demodulator_priv;
6350         u32 IF;
6351
6352         dprintk(1, "\n");
6353
6354         if (state->m_drxk_state == DRXK_NO_DEV)
6355                 return -ENODEV;
6356
6357         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6358                 return -EAGAIN;
6359
6360         if (!fe->ops.tuner_ops.get_if_frequency) {
6361                 pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6362                 return -EINVAL;
6363         }
6364
6365         if (fe->ops.i2c_gate_ctrl)
6366                 fe->ops.i2c_gate_ctrl(fe, 1);
6367         if (fe->ops.tuner_ops.set_params)
6368                 fe->ops.tuner_ops.set_params(fe);
6369         if (fe->ops.i2c_gate_ctrl)
6370                 fe->ops.i2c_gate_ctrl(fe, 0);
6371
6372         old_delsys = state->props.delivery_system;
6373         state->props = *p;
6374
6375         if (old_delsys != delsys) {
6376                 shut_down(state);
6377                 switch (delsys) {
6378                 case SYS_DVBC_ANNEX_A:
6379                 case SYS_DVBC_ANNEX_C:
6380                         if (!state->m_has_dvbc)
6381                                 return -EINVAL;
6382                         state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6383                                                 true : false;
6384                         if (state->m_itut_annex_c)
6385                                 setoperation_mode(state, OM_QAM_ITU_C);
6386                         else
6387                                 setoperation_mode(state, OM_QAM_ITU_A);
6388                         break;
6389                 case SYS_DVBT:
6390                         if (!state->m_has_dvbt)
6391                                 return -EINVAL;
6392                         setoperation_mode(state, OM_DVBT);
6393                         break;
6394                 default:
6395                         return -EINVAL;
6396                 }
6397         }
6398
6399         fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6400         start(state, 0, IF);
6401
6402         /* After set_frontend, stats aren't available */
6403         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6404         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6405         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6406         p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6407         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6408         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6409         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6410         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6411
6412         /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6413
6414         return 0;
6415 }
6416
6417 static int get_strength(struct drxk_state *state, u64 *strength)
6418 {
6419         int status;
6420         struct s_cfg_agc   rf_agc, if_agc;
6421         u32          total_gain  = 0;
6422         u32          atten      = 0;
6423         u32          agc_range   = 0;
6424         u16            scu_lvl  = 0;
6425         u16            scu_coc  = 0;
6426         /* FIXME: those are part of the tuner presets */
6427         u16 tuner_rf_gain         = 50; /* Default value on az6007 driver */
6428         u16 tuner_if_gain         = 40; /* Default value on az6007 driver */
6429
6430         *strength = 0;
6431
6432         if (is_dvbt(state)) {
6433                 rf_agc = state->m_dvbt_rf_agc_cfg;
6434                 if_agc = state->m_dvbt_if_agc_cfg;
6435         } else if (is_qam(state)) {
6436                 rf_agc = state->m_qam_rf_agc_cfg;
6437                 if_agc = state->m_qam_if_agc_cfg;
6438         } else {
6439                 rf_agc = state->m_atv_rf_agc_cfg;
6440                 if_agc = state->m_atv_if_agc_cfg;
6441         }
6442
6443         if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6444                 /* SCU output_level */
6445                 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6446                 if (status < 0)
6447                         return status;
6448
6449                 /* SCU c.o.c. */
6450                 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6451                 if (status < 0)
6452                         return status;
6453
6454                 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6455                         rf_agc.output_level = scu_lvl + scu_coc;
6456                 else
6457                         rf_agc.output_level = 0xffff;
6458
6459                 /* Take RF gain into account */
6460                 total_gain += tuner_rf_gain;
6461
6462                 /* clip output value */
6463                 if (rf_agc.output_level < rf_agc.min_output_level)
6464                         rf_agc.output_level = rf_agc.min_output_level;
6465                 if (rf_agc.output_level > rf_agc.max_output_level)
6466                         rf_agc.output_level = rf_agc.max_output_level;
6467
6468                 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
6469                 if (agc_range > 0) {
6470                         atten += 100UL *
6471                                 ((u32)(tuner_rf_gain)) *
6472                                 ((u32)(rf_agc.output_level - rf_agc.min_output_level))
6473                                 / agc_range;
6474                 }
6475         }
6476
6477         if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6478                 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6479                                 &if_agc.output_level);
6480                 if (status < 0)
6481                         return status;
6482
6483                 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6484                                 &if_agc.top);
6485                 if (status < 0)
6486                         return status;
6487
6488                 /* Take IF gain into account */
6489                 total_gain += (u32) tuner_if_gain;
6490
6491                 /* clip output value */
6492                 if (if_agc.output_level < if_agc.min_output_level)
6493                         if_agc.output_level = if_agc.min_output_level;
6494                 if (if_agc.output_level > if_agc.max_output_level)
6495                         if_agc.output_level = if_agc.max_output_level;
6496
6497                 agc_range  = (u32)(if_agc.max_output_level - if_agc.min_output_level);
6498                 if (agc_range > 0) {
6499                         atten += 100UL *
6500                                 ((u32)(tuner_if_gain)) *
6501                                 ((u32)(if_agc.output_level - if_agc.min_output_level))
6502                                 / agc_range;
6503                 }
6504         }
6505
6506         /*
6507          * Convert to 0..65535 scale.
6508          * If it can't be measured (AGC is disabled), just show 100%.
6509          */
6510         if (total_gain > 0)
6511                 *strength = (65535UL * atten / total_gain / 100);
6512         else
6513                 *strength = 65535;
6514
6515         return 0;
6516 }
6517
6518 static int drxk_get_stats(struct dvb_frontend *fe)
6519 {
6520         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6521         struct drxk_state *state = fe->demodulator_priv;
6522         int status;
6523         u32 stat;
6524         u16 reg16;
6525         u32 post_bit_count;
6526         u32 post_bit_err_count;
6527         u32 post_bit_error_scale;
6528         u32 pre_bit_err_count;
6529         u32 pre_bit_count;
6530         u32 pkt_count;
6531         u32 pkt_error_count;
6532         s32 cnr;
6533
6534         if (state->m_drxk_state == DRXK_NO_DEV)
6535                 return -ENODEV;
6536         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6537                 return -EAGAIN;
6538
6539         /* get status */
6540         state->fe_status = 0;
6541         get_lock_status(state, &stat);
6542         if (stat == MPEG_LOCK)
6543                 state->fe_status |= 0x1f;
6544         if (stat == FEC_LOCK)
6545                 state->fe_status |= 0x0f;
6546         if (stat == DEMOD_LOCK)
6547                 state->fe_status |= 0x07;
6548
6549         /*
6550          * Estimate signal strength from AGC
6551          */
6552         get_strength(state, &c->strength.stat[0].uvalue);
6553         c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6554
6555
6556         if (stat >= DEMOD_LOCK) {
6557                 get_signal_to_noise(state, &cnr);
6558                 c->cnr.stat[0].svalue = cnr * 100;
6559                 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6560         } else {
6561                 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6562         }
6563
6564         if (stat < FEC_LOCK) {
6565                 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6566                 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6567                 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6568                 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6569                 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6570                 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6571                 return 0;
6572         }
6573
6574         /* Get post BER */
6575
6576         /* BER measurement is valid if at least FEC lock is achieved */
6577
6578         /*
6579          * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be
6580          * written to set nr of symbols or bits over which to measure
6581          * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg().
6582          */
6583
6584         /* Read registers for post/preViterbi BER calculation */
6585         status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);
6586         if (status < 0)
6587                 goto error;
6588         pre_bit_err_count = reg16;
6589
6590         status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);
6591         if (status < 0)
6592                 goto error;
6593         pre_bit_count = reg16;
6594
6595         /* Number of bit-errors */
6596         status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);
6597         if (status < 0)
6598                 goto error;
6599         post_bit_err_count = reg16;
6600
6601         status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);
6602         if (status < 0)
6603                 goto error;
6604         post_bit_error_scale = reg16;
6605
6606         status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);
6607         if (status < 0)
6608                 goto error;
6609         pkt_count = reg16;
6610
6611         status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);
6612         if (status < 0)
6613                 goto error;
6614         pkt_error_count = reg16;
6615         write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6616
6617         post_bit_err_count *= post_bit_error_scale;
6618
6619         post_bit_count = pkt_count * 204 * 8;
6620
6621         /* Store the results */
6622         c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6623         c->block_error.stat[0].uvalue += pkt_error_count;
6624         c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6625         c->block_count.stat[0].uvalue += pkt_count;
6626
6627         c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6628         c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6629         c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6630         c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6631
6632         c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6633         c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6634         c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6635         c->post_bit_count.stat[0].uvalue += post_bit_count;
6636
6637 error:
6638         return status;
6639 }
6640
6641
6642 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)
6643 {
6644         struct drxk_state *state = fe->demodulator_priv;
6645         int rc;
6646
6647         dprintk(1, "\n");
6648
6649         rc = drxk_get_stats(fe);
6650         if (rc < 0)
6651                 return rc;
6652
6653         *status = state->fe_status;
6654
6655         return 0;
6656 }
6657
6658 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6659                                      u16 *strength)
6660 {
6661         struct drxk_state *state = fe->demodulator_priv;
6662         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6663
6664         dprintk(1, "\n");
6665
6666         if (state->m_drxk_state == DRXK_NO_DEV)
6667                 return -ENODEV;
6668         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6669                 return -EAGAIN;
6670
6671         *strength = c->strength.stat[0].uvalue;
6672         return 0;
6673 }
6674
6675 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6676 {
6677         struct drxk_state *state = fe->demodulator_priv;
6678         s32 snr2;
6679
6680         dprintk(1, "\n");
6681
6682         if (state->m_drxk_state == DRXK_NO_DEV)
6683                 return -ENODEV;
6684         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6685                 return -EAGAIN;
6686
6687         get_signal_to_noise(state, &snr2);
6688
6689         /* No negative SNR, clip to zero */
6690         if (snr2 < 0)
6691                 snr2 = 0;
6692         *snr = snr2 & 0xffff;
6693         return 0;
6694 }
6695
6696 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6697 {
6698         struct drxk_state *state = fe->demodulator_priv;
6699         u16 err;
6700
6701         dprintk(1, "\n");
6702
6703         if (state->m_drxk_state == DRXK_NO_DEV)
6704                 return -ENODEV;
6705         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6706                 return -EAGAIN;
6707
6708         dvbtqam_get_acc_pkt_err(state, &err);
6709         *ucblocks = (u32) err;
6710         return 0;
6711 }
6712
6713 static int drxk_get_tune_settings(struct dvb_frontend *fe,
6714                                   struct dvb_frontend_tune_settings *sets)
6715 {
6716         struct drxk_state *state = fe->demodulator_priv;
6717         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6718
6719         dprintk(1, "\n");
6720
6721         if (state->m_drxk_state == DRXK_NO_DEV)
6722                 return -ENODEV;
6723         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6724                 return -EAGAIN;
6725
6726         switch (p->delivery_system) {
6727         case SYS_DVBC_ANNEX_A:
6728         case SYS_DVBC_ANNEX_C:
6729         case SYS_DVBT:
6730                 sets->min_delay_ms = 3000;
6731                 sets->max_drift = 0;
6732                 sets->step_size = 0;
6733                 return 0;
6734         default:
6735                 return -EINVAL;
6736         }
6737 }
6738
6739 static const struct dvb_frontend_ops drxk_ops = {
6740         /* .delsys will be filled dynamically */
6741         .info = {
6742                 .name = "DRXK",
6743                 .frequency_min_hz =  47 * MHz,
6744                 .frequency_max_hz = 865 * MHz,
6745                  /* For DVB-C */
6746                 .symbol_rate_min =   870000,
6747                 .symbol_rate_max = 11700000,
6748                 /* For DVB-T */
6749                 .frequency_stepsize_hz = 166667,
6750
6751                 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6752                         FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6753                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6754                         FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6755                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6756                         FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6757         },
6758
6759         .release = drxk_release,
6760         .sleep = drxk_sleep,
6761         .i2c_gate_ctrl = drxk_gate_ctrl,
6762
6763         .set_frontend = drxk_set_parameters,
6764         .get_tune_settings = drxk_get_tune_settings,
6765
6766         .read_status = drxk_read_status,
6767         .read_signal_strength = drxk_read_signal_strength,
6768         .read_snr = drxk_read_snr,
6769         .read_ucblocks = drxk_read_ucblocks,
6770 };
6771
6772 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6773                                  struct i2c_adapter *i2c)
6774 {
6775         struct dtv_frontend_properties *p;
6776         struct drxk_state *state = NULL;
6777         u8 adr = config->adr;
6778         int status;
6779
6780         dprintk(1, "\n");
6781         state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6782         if (!state)
6783                 return NULL;
6784
6785         state->i2c = i2c;
6786         state->demod_address = adr;
6787         state->single_master = config->single_master;
6788         state->microcode_name = config->microcode_name;
6789         state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6790         state->no_i2c_bridge = config->no_i2c_bridge;
6791         state->antenna_gpio = config->antenna_gpio;
6792         state->antenna_dvbt = config->antenna_dvbt;
6793         state->m_chunk_size = config->chunk_size;
6794         state->enable_merr_cfg = config->enable_merr_cfg;
6795
6796         if (config->dynamic_clk) {
6797                 state->m_dvbt_static_clk = false;
6798                 state->m_dvbc_static_clk = false;
6799         } else {
6800                 state->m_dvbt_static_clk = true;
6801                 state->m_dvbc_static_clk = true;
6802         }
6803
6804
6805         if (config->mpeg_out_clk_strength)
6806                 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6807         else
6808                 state->m_ts_clockk_strength = 0x06;
6809
6810         if (config->parallel_ts)
6811                 state->m_enable_parallel = true;
6812         else
6813                 state->m_enable_parallel = false;
6814
6815         /* NOTE: as more UIO bits will be used, add them to the mask */
6816         state->uio_mask = config->antenna_gpio;
6817
6818         /* Default gpio to DVB-C */
6819         if (!state->antenna_dvbt && state->antenna_gpio)
6820                 state->m_gpio |= state->antenna_gpio;
6821         else
6822                 state->m_gpio &= ~state->antenna_gpio;
6823
6824         mutex_init(&state->mutex);
6825
6826         memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6827         state->frontend.demodulator_priv = state;
6828
6829         init_state(state);
6830
6831         /* Load firmware and initialize DRX-K */
6832         if (state->microcode_name) {
6833                 const struct firmware *fw = NULL;
6834
6835                 status = request_firmware(&fw, state->microcode_name,
6836                                           state->i2c->dev.parent);
6837                 if (status < 0)
6838                         fw = NULL;
6839                 load_firmware_cb(fw, state);
6840         } else if (init_drxk(state) < 0)
6841                 goto error;
6842
6843
6844         /* Initialize stats */
6845         p = &state->frontend.dtv_property_cache;
6846         p->strength.len = 1;
6847         p->cnr.len = 1;
6848         p->block_error.len = 1;
6849         p->block_count.len = 1;
6850         p->pre_bit_error.len = 1;
6851         p->pre_bit_count.len = 1;
6852         p->post_bit_error.len = 1;
6853         p->post_bit_count.len = 1;
6854
6855         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6856         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6857         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6858         p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6859         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6860         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6861         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6862         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6863
6864         pr_info("frontend initialized.\n");
6865         return &state->frontend;
6866
6867 error:
6868         pr_err("not found\n");
6869         kfree(state);
6870         return NULL;
6871 }
6872 EXPORT_SYMBOL(drxk_attach);
6873
6874 MODULE_DESCRIPTION("DRX-K driver");
6875 MODULE_AUTHOR("Ralph Metzler");
6876 MODULE_LICENSE("GPL");