drivers/media/dvb-frontends/drxd_hard.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
   4  *
   5  * Copyright (C) 2003-2007 Micronas
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/firmware.h>
  14 #include <linux/i2c.h>
  15 #include <asm/div64.h>
  16
  17 #include <media/dvb_frontend.h>
  18 #include "drxd.h"
  19 #include "drxd_firm.h"
  20
  21 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
  22 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
  23
  24 #define CHUNK_SIZE 48
  25
  26 #define DRX_I2C_RMW           0x10
  27 #define DRX_I2C_BROADCAST     0x20
  28 #define DRX_I2C_CLEARCRC      0x80
  29 #define DRX_I2C_SINGLE_MASTER 0xC0
  30 #define DRX_I2C_MODEFLAGS     0xC0
  31 #define DRX_I2C_FLAGS         0xF0
  32
  33 #define DEFAULT_LOCK_TIMEOUT    1100
  34
  35 #define DRX_CHANNEL_AUTO 0
  36 #define DRX_CHANNEL_HIGH 1
  37 #define DRX_CHANNEL_LOW  2
  38
  39 #define DRX_LOCK_MPEG  1
  40 #define DRX_LOCK_FEC   2
  41 #define DRX_LOCK_DEMOD 4
  42
  43 /****************************************************************************/
  44
  45 enum CSCDState {
  46         CSCD_INIT = 0,
  47         CSCD_SET,
  48         CSCD_SAVED
  49 };
  50
  51 enum CDrxdState {
  52         DRXD_UNINITIALIZED = 0,
  53         DRXD_STOPPED,
  54         DRXD_STARTED
  55 };
  56
  57 enum AGC_CTRL_MODE {
  58         AGC_CTRL_AUTO = 0,
  59         AGC_CTRL_USER,
  60         AGC_CTRL_OFF
  61 };
  62
  63 enum OperationMode {
  64         OM_Default,
  65         OM_DVBT_Diversity_Front,
  66         OM_DVBT_Diversity_End
  67 };
  68
  69 struct SCfgAgc {
  70         enum AGC_CTRL_MODE ctrlMode;
  71         u16 outputLevel;        /* range [0, ... , 1023], 1/n of fullscale range */
  72         u16 settleLevel;        /* range [0, ... , 1023], 1/n of fullscale range */
  73         u16 minOutputLevel;     /* range [0, ... , 1023], 1/n of fullscale range */
  74         u16 maxOutputLevel;     /* range [0, ... , 1023], 1/n of fullscale range */
  75         u16 speed;              /* range [0, ... , 1023], 1/n of fullscale range */
  76
  77         u16 R1;
  78         u16 R2;
  79         u16 R3;
  80 };
  81
  82 struct SNoiseCal {
  83         int cpOpt;
  84         short cpNexpOfs;
  85         short tdCal2k;
  86         short tdCal8k;
  87 };
  88
  89 enum app_env {
  90         APPENV_STATIC = 0,
  91         APPENV_PORTABLE = 1,
  92         APPENV_MOBILE = 2
  93 };
  94
  95 enum EIFFilter {
  96         IFFILTER_SAW = 0,
  97         IFFILTER_DISCRETE = 1
  98 };
  99
 100 struct drxd_state {
 101         struct dvb_frontend frontend;
 102         struct dvb_frontend_ops ops;
 103         struct dtv_frontend_properties props;
 104
 105         const struct firmware *fw;
 106         struct device *dev;
 107
 108         struct i2c_adapter *i2c;
 109         void *priv;
 110         struct drxd_config config;
 111
 112         int i2c_access;
 113         int init_done;
 114         struct mutex mutex;
 115
 116         u8 chip_adr;
 117         u16 hi_cfg_timing_div;
 118         u16 hi_cfg_bridge_delay;
 119         u16 hi_cfg_wakeup_key;
 120         u16 hi_cfg_ctrl;
 121
 122         u16 intermediate_freq;
 123         u16 osc_clock_freq;
 124
 125         enum CSCDState cscd_state;
 126         enum CDrxdState drxd_state;
 127
 128         u16 sys_clock_freq;
 129         s16 osc_clock_deviation;
 130         u16 expected_sys_clock_freq;
 131
 132         u16 insert_rs_byte;
 133         u16 enable_parallel;
 134
 135         int operation_mode;
 136
 137         struct SCfgAgc if_agc_cfg;
 138         struct SCfgAgc rf_agc_cfg;
 139
 140         struct SNoiseCal noise_cal;
 141
 142         u32 fe_fs_add_incr;
 143         u32 org_fe_fs_add_incr;
 144         u16 current_fe_if_incr;
 145
 146         u16 m_FeAgRegAgPwd;
 147         u16 m_FeAgRegAgAgcSio;
 148
 149         u16 m_EcOcRegOcModeLop;
 150         u16 m_EcOcRegSncSncLvl;
 151         u8 *m_InitAtomicRead;
 152         u8 *m_HiI2cPatch;
 153
 154         u8 *m_ResetCEFR;
 155         u8 *m_InitFE_1;
 156         u8 *m_InitFE_2;
 157         u8 *m_InitCP;
 158         u8 *m_InitCE;
 159         u8 *m_InitEQ;
 160         u8 *m_InitSC;
 161         u8 *m_InitEC;
 162         u8 *m_ResetECRAM;
 163         u8 *m_InitDiversityFront;
 164         u8 *m_InitDiversityEnd;
 165         u8 *m_DisableDiversity;
 166         u8 *m_StartDiversityFront;
 167         u8 *m_StartDiversityEnd;
 168
 169         u8 *m_DiversityDelay8MHZ;
 170         u8 *m_DiversityDelay6MHZ;
 171
 172         u8 *microcode;
 173         u32 microcode_length;
 174
 175         int type_A;
 176         int PGA;
 177         int diversity;
 178         int tuner_mirrors;
 179
 180         enum app_env app_env_default;
 181         enum app_env app_env_diversity;
 182
 183 };
 184
 185 /****************************************************************************/
 186 /* I2C **********************************************************************/
 187 /****************************************************************************/
 188
 189 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
 190 {
 191         struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
 192
 193         if (i2c_transfer(adap, &msg, 1) != 1)
 194                 return -1;
 195         return 0;
 196 }
 197
 198 static int i2c_read(struct i2c_adapter *adap,
 199                     u8 adr, u8 *msg, int len, u8 *answ, int alen)
 200 {
 201         struct i2c_msg msgs[2] = {
 202                 {
 203                         .addr = adr, .flags = 0,
 204                         .buf = msg, .len = len
 205                 }, {
 206                         .addr = adr, .flags = I2C_M_RD,
 207                         .buf = answ, .len = alen
 208                 }
 209         };
 210         if (i2c_transfer(adap, msgs, 2) != 2)
 211                 return -1;
 212         return 0;
 213 }
 214
 215 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
 216 {
 217         u64 tmp64;
 218
 219         tmp64 = (u64)a * (u64)b;
 220         do_div(tmp64, c);
 221
 222         return (u32) tmp64;
 223 }
 224
 225 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
 226 {
 227         u8 adr = state->config.demod_address;
 228         u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
 229                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 230         };
 231         u8 mm2[2];
 232         if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
 233                 return -1;
 234         if (data)
 235                 *data = mm2[0] | (mm2[1] << 8);
 236         return mm2[0] | (mm2[1] << 8);
 237 }
 238
 239 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
 240 {
 241         u8 adr = state->config.demod_address;
 242         u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
 243                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 244         };
 245         u8 mm2[4];
 246
 247         if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
 248                 return -1;
 249         if (data)
 250                 *data =
 251                     mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
 252         return 0;
 253 }
 254
 255 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
 256 {
 257         u8 adr = state->config.demod_address;
 258         u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
 259                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
 260                 data & 0xff, (data >> 8) & 0xff
 261         };
 262
 263         if (i2c_write(state->i2c, adr, mm, 6) < 0)
 264                 return -1;
 265         return 0;
 266 }
 267
 268 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
 269 {
 270         u8 adr = state->config.demod_address;
 271         u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
 272                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
 273                 data & 0xff, (data >> 8) & 0xff,
 274                 (data >> 16) & 0xff, (data >> 24) & 0xff
 275         };
 276
 277         if (i2c_write(state->i2c, adr, mm, 8) < 0)
 278                 return -1;
 279         return 0;
 280 }
 281
 282 static int write_chunk(struct drxd_state *state,
 283                        u32 reg, u8 *data, u32 len, u8 flags)
 284 {
 285         u8 adr = state->config.demod_address;
 286         u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
 287                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 288         };
 289         int i;
 290
 291         for (i = 0; i < len; i++)
 292                 mm[4 + i] = data[i];
 293         if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
 294                 printk(KERN_ERR "error in write_chunk\n");
 295                 return -1;
 296         }
 297         return 0;
 298 }
 299
 300 static int WriteBlock(struct drxd_state *state,
 301                       u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
 302 {
 303         while (BlockSize > 0) {
 304                 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
 305
 306                 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
 307                         return -1;
 308                 pBlock += Chunk;
 309                 Address += (Chunk >> 1);
 310                 BlockSize -= Chunk;
 311         }
 312         return 0;
 313 }
 314
 315 static int WriteTable(struct drxd_state *state, u8 * pTable)
 316 {
 317         int status = 0;
 318
 319         if (!pTable)
 320                 return 0;
 321
 322         while (!status) {
 323                 u16 Length;
 324                 u32 Address = pTable[0] | (pTable[1] << 8) |
 325                     (pTable[2] << 16) | (pTable[3] << 24);
 326
 327                 if (Address == 0xFFFFFFFF)
 328                         break;
 329                 pTable += sizeof(u32);
 330
 331                 Length = pTable[0] | (pTable[1] << 8);
 332                 pTable += sizeof(u16);
 333                 if (!Length)
 334                         break;
 335                 status = WriteBlock(state, Address, Length * 2, pTable, 0);
 336                 pTable += (Length * 2);
 337         }
 338         return status;
 339 }
 340
 341 /****************************************************************************/
 342 /****************************************************************************/
 343 /****************************************************************************/
 344
 345 static int ResetCEFR(struct drxd_state *state)
 346 {
 347         return WriteTable(state, state->m_ResetCEFR);
 348 }
 349
 350 static int InitCP(struct drxd_state *state)
 351 {
 352         return WriteTable(state, state->m_InitCP);
 353 }
 354
 355 static int InitCE(struct drxd_state *state)
 356 {
 357         int status;
 358         enum app_env AppEnv = state->app_env_default;
 359
 360         do {
 361                 status = WriteTable(state, state->m_InitCE);
 362                 if (status < 0)
 363                         break;
 364
 365                 if (state->operation_mode == OM_DVBT_Diversity_Front ||
 366                     state->operation_mode == OM_DVBT_Diversity_End) {
 367                         AppEnv = state->app_env_diversity;
 368                 }
 369                 if (AppEnv == APPENV_STATIC) {
 370                         status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
 371                         if (status < 0)
 372                                 break;
 373                 } else if (AppEnv == APPENV_PORTABLE) {
 374                         status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
 375                         if (status < 0)
 376                                 break;
 377                 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
 378                         status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
 379                         if (status < 0)
 380                                 break;
 381                 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
 382                         status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
 383                         if (status < 0)
 384                                 break;
 385                 }
 386
 387                 /* start ce */
 388                 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
 389                 if (status < 0)
 390                         break;
 391         } while (0);
 392         return status;
 393 }
 394
 395 static int StopOC(struct drxd_state *state)
 396 {
 397         int status = 0;
 398         u16 ocSyncLvl = 0;
 399         u16 ocModeLop = state->m_EcOcRegOcModeLop;
 400         u16 dtoIncLop = 0;
 401         u16 dtoIncHip = 0;
 402
 403         do {
 404                 /* Store output configuration */
 405                 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
 406                 if (status < 0)
 407                         break;
 408                 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
 409                 state->m_EcOcRegSncSncLvl = ocSyncLvl;
 410                 /* m_EcOcRegOcModeLop = ocModeLop; */
 411
 412                 /* Flush FIFO (byte-boundary) at fixed rate */
 413                 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
 414                 if (status < 0)
 415                         break;
 416                 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
 417                 if (status < 0)
 418                         break;
 419                 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
 420                 if (status < 0)
 421                         break;
 422                 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
 423                 if (status < 0)
 424                         break;
 425                 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
 426                 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
 427                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
 428                 if (status < 0)
 429                         break;
 430                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
 431                 if (status < 0)
 432                         break;
 433
 434                 msleep(1);
 435                 /* Output pins to '0' */
 436                 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
 437                 if (status < 0)
 438                         break;
 439
 440                 /* Force the OC out of sync */
 441                 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
 442                 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
 443                 if (status < 0)
 444                         break;
 445                 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
 446                 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
 447                 ocModeLop |= 0x2;       /* Magically-out-of-sync */
 448                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
 449                 if (status < 0)
 450                         break;
 451                 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
 452                 if (status < 0)
 453                         break;
 454                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
 455                 if (status < 0)
 456                         break;
 457         } while (0);
 458
 459         return status;
 460 }
 461
 462 static int StartOC(struct drxd_state *state)
 463 {
 464         int status = 0;
 465
 466         do {
 467                 /* Stop OC */
 468                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
 469                 if (status < 0)
 470                         break;
 471
 472                 /* Restore output configuration */
 473                 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
 474                 if (status < 0)
 475                         break;
 476                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
 477                 if (status < 0)
 478                         break;
 479
 480                 /* Output pins active again */
 481                 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
 482                 if (status < 0)
 483                         break;
 484
 485                 /* Start OC */
 486                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
 487                 if (status < 0)
 488                         break;
 489         } while (0);
 490         return status;
 491 }
 492
 493 static int InitEQ(struct drxd_state *state)
 494 {
 495         return WriteTable(state, state->m_InitEQ);
 496 }
 497
 498 static int InitEC(struct drxd_state *state)
 499 {
 500         return WriteTable(state, state->m_InitEC);
 501 }
 502
 503 static int InitSC(struct drxd_state *state)
 504 {
 505         return WriteTable(state, state->m_InitSC);
 506 }
 507
 508 static int InitAtomicRead(struct drxd_state *state)
 509 {
 510         return WriteTable(state, state->m_InitAtomicRead);
 511 }
 512
 513 static int CorrectSysClockDeviation(struct drxd_state *state);
 514
 515 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
 516 {
 517         u16 ScRaRamLock = 0;
 518         const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
 519                                     SC_RA_RAM_LOCK_FEC__M |
 520                                     SC_RA_RAM_LOCK_DEMOD__M);
 521         const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
 522                                    SC_RA_RAM_LOCK_DEMOD__M);
 523         const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
 524
 525         int status;
 526
 527         *pLockStatus = 0;
 528
 529         status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
 530         if (status < 0) {
 531                 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
 532                 return status;
 533         }
 534
 535         if (state->drxd_state != DRXD_STARTED)
 536                 return 0;
 537
 538         if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
 539                 *pLockStatus |= DRX_LOCK_MPEG;
 540                 CorrectSysClockDeviation(state);
 541         }
 542
 543         if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
 544                 *pLockStatus |= DRX_LOCK_FEC;
 545
 546         if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
 547                 *pLockStatus |= DRX_LOCK_DEMOD;
 548         return 0;
 549 }
 550
 551 /****************************************************************************/
 552
 553 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
 554 {
 555         int status;
 556
 557         if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
 558                 return -1;
 559
 560         if (cfg->ctrlMode == AGC_CTRL_USER) {
 561                 do {
 562                         u16 FeAgRegPm1AgcWri;
 563                         u16 FeAgRegAgModeLop;
 564
 565                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
 566                         if (status < 0)
 567                                 break;
 568                         FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
 569                         FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
 570                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
 571                         if (status < 0)
 572                                 break;
 573
 574                         FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
 575                                                   FE_AG_REG_PM1_AGC_WRI__M);
 576                         status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
 577                         if (status < 0)
 578                                 break;
 579                 } while (0);
 580         } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
 581                 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
 582                     ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
 583                     ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
 584                     ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
 585                     )
 586                         return -1;
 587                 do {
 588                         u16 FeAgRegAgModeLop;
 589                         u16 FeAgRegEgcSetLvl;
 590                         u16 slope, offset;
 591
 592                         /* == Mode == */
 593
 594                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
 595                         if (status < 0)
 596                                 break;
 597                         FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
 598                         FeAgRegAgModeLop |=
 599                             FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
 600                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
 601                         if (status < 0)
 602                                 break;
 603
 604                         /* == Settle level == */
 605
 606                         FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
 607                                                   FE_AG_REG_EGC_SET_LVL__M);
 608                         status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
 609                         if (status < 0)
 610                                 break;
 611
 612                         /* == Min/Max == */
 613
 614                         slope = (u16) ((cfg->maxOutputLevel -
 615                                         cfg->minOutputLevel) / 2);
 616                         offset = (u16) ((cfg->maxOutputLevel +
 617                                          cfg->minOutputLevel) / 2 - 511);
 618
 619                         status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
 620                         if (status < 0)
 621                                 break;
 622                         status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
 623                         if (status < 0)
 624                                 break;
 625
 626                         /* == Speed == */
 627                         {
 628                                 const u16 maxRur = 8;
 629                                 static const u16 slowIncrDecLUT[] = {
 630                                         3, 4, 4, 5, 6 };
 631                                 static const u16 fastIncrDecLUT[] = {
 632                                         14, 15, 15, 16,
 633                                         17, 18, 18, 19,
 634                                         20, 21, 22, 23,
 635                                         24, 26, 27, 28,
 636                                         29, 31
 637                                 };
 638
 639                                 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
 640                                     (maxRur + 1);
 641                                 u16 fineSpeed = (u16) (cfg->speed -
 642                                                        ((cfg->speed /
 643                                                          fineSteps) *
 644                                                         fineSteps));
 645                                 u16 invRurCount = (u16) (cfg->speed /
 646                                                          fineSteps);
 647                                 u16 rurCount;
 648                                 if (invRurCount > maxRur) {
 649                                         rurCount = 0;
 650                                         fineSpeed += fineSteps;
 651                                 } else {
 652                                         rurCount = maxRur - invRurCount;
 653                                 }
 654
 655                                 /*
 656                                    fastInc = default *
 657                                    (2^(fineSpeed/fineSteps))
 658                                    => range[default...2*default>
 659                                    slowInc = default *
 660                                    (2^(fineSpeed/fineSteps))
 661                                  */
 662                                 {
 663                                         u16 fastIncrDec =
 664                                             fastIncrDecLUT[fineSpeed /
 665                                                            ((fineSteps /
 666                                                              (14 + 1)) + 1)];
 667                                         u16 slowIncrDec =
 668                                             slowIncrDecLUT[fineSpeed /
 669                                                            (fineSteps /
 670                                                             (3 + 1))];
 671
 672                                         status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
 673                                         if (status < 0)
 674                                                 break;
 675                                         status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
 676                                         if (status < 0)
 677                                                 break;
 678                                         status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
 679                                         if (status < 0)
 680                                                 break;
 681                                         status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
 682                                         if (status < 0)
 683                                                 break;
 684                                         status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
 685                                         if (status < 0)
 686                                                 break;
 687                                 }
 688                         }
 689                 } while (0);
 690
 691         } else {
 692                 /* No OFF mode for IF control */
 693                 return -1;
 694         }
 695         return status;
 696 }
 697
 698 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
 699 {
 700         int status = 0;
 701
 702         if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
 703                 return -1;
 704
 705         if (cfg->ctrlMode == AGC_CTRL_USER) {
 706                 do {
 707                         u16 AgModeLop = 0;
 708                         u16 level = (cfg->outputLevel);
 709
 710                         if (level == DRXD_FE_CTRL_MAX)
 711                                 level++;
 712
 713                         status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
 714                         if (status < 0)
 715                                 break;
 716
 717                         /*==== Mode ====*/
 718
 719                         /* Powerdown PD2, WRI source */
 720                         state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 721                         state->m_FeAgRegAgPwd |=
 722                             FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
 723                         status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
 724                         if (status < 0)
 725                                 break;
 726
 727                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 728                         if (status < 0)
 729                                 break;
 730                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 731                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 732                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 733                                       FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
 734                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 735                         if (status < 0)
 736                                 break;
 737
 738                         /* enable AGC2 pin */
 739                         {
 740                                 u16 FeAgRegAgAgcSio = 0;
 741                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 742                                 if (status < 0)
 743                                         break;
 744                                 FeAgRegAgAgcSio &=
 745                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 746                                 FeAgRegAgAgcSio |=
 747                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
 748                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 749                                 if (status < 0)
 750                                         break;
 751                         }
 752
 753                 } while (0);
 754         } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
 755                 u16 AgModeLop = 0;
 756
 757                 do {
 758                         u16 level;
 759                         /* Automatic control */
 760                         /* Powerup PD2, AGC2 as output, TGC source */
 761                         (state->m_FeAgRegAgPwd) &=
 762                             ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 763                         (state->m_FeAgRegAgPwd) |=
 764                             FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
 765                         status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
 766                         if (status < 0)
 767                                 break;
 768
 769                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 770                         if (status < 0)
 771                                 break;
 772                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 773                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 774                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 775                                       FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
 776                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 777                         if (status < 0)
 778                                 break;
 779                         /* Settle level */
 780                         level = (((cfg->settleLevel) >> 4) &
 781                                  FE_AG_REG_TGC_SET_LVL__M);
 782                         status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
 783                         if (status < 0)
 784                                 break;
 785
 786                         /* Min/max: don't care */
 787
 788                         /* Speed: TODO */
 789
 790                         /* enable AGC2 pin */
 791                         {
 792                                 u16 FeAgRegAgAgcSio = 0;
 793                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 794                                 if (status < 0)
 795                                         break;
 796                                 FeAgRegAgAgcSio &=
 797                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 798                                 FeAgRegAgAgcSio |=
 799                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
 800                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 801                                 if (status < 0)
 802                                         break;
 803                         }
 804
 805                 } while (0);
 806         } else {
 807                 u16 AgModeLop = 0;
 808
 809                 do {
 810                         /* No RF AGC control */
 811                         /* Powerdown PD2, AGC2 as output, WRI source */
 812                         (state->m_FeAgRegAgPwd) &=
 813                             ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 814                         (state->m_FeAgRegAgPwd) |=
 815                             FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
 816                         status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
 817                         if (status < 0)
 818                                 break;
 819
 820                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 821                         if (status < 0)
 822                                 break;
 823                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 824                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 825                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 826                                       FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
 827                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 828                         if (status < 0)
 829                                 break;
 830
 831                         /* set FeAgRegAgAgcSio AGC2 (RF) as input */
 832                         {
 833                                 u16 FeAgRegAgAgcSio = 0;
 834                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 835                                 if (status < 0)
 836                                         break;
 837                                 FeAgRegAgAgcSio &=
 838                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 839                                 FeAgRegAgAgcSio |=
 840                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
 841                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 842                                 if (status < 0)
 843                                         break;
 844                         }
 845                 } while (0);
 846         }
 847         return status;
 848 }
 849
 850 static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
 851 {
 852         int status = 0;
 853
 854         *pValue = 0;
 855         if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
 856                 u16 Value;
 857                 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
 858                 Value &= FE_AG_REG_GC1_AGC_DAT__M;
 859                 if (status >= 0) {
 860                         /*           3.3V
 861                            |
 862                            R1
 863                            |
 864                            Vin - R3 - * -- Vout
 865                            |
 866                            R2
 867                            |
 868                            GND
 869                          */
 870                         u32 R1 = state->if_agc_cfg.R1;
 871                         u32 R2 = state->if_agc_cfg.R2;
 872                         u32 R3 = state->if_agc_cfg.R3;
 873
 874                         u32 Vmax, Rpar, Vmin, Vout;
 875
 876                         if (R2 == 0 && (R1 == 0 || R3 == 0))
 877                                 return 0;
 878
 879                         Vmax = (3300 * R2) / (R1 + R2);
 880                         Rpar = (R2 * R3) / (R3 + R2);
 881                         Vmin = (3300 * Rpar) / (R1 + Rpar);
 882                         Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
 883
 884                         *pValue = Vout;
 885                 }
 886         }
 887         return status;
 888 }
 889
 890 static int load_firmware(struct drxd_state *state, const char *fw_name)
 891 {
 892         const struct firmware *fw;
 893
 894         if (request_firmware(&fw, fw_name, state->dev) < 0) {
 895                 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
 896                 return -EIO;
 897         }
 898
 899         state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
 900         if (!state->microcode) {
 901                 release_firmware(fw);
 902                 return -ENOMEM;
 903         }
 904
 905         state->microcode_length = fw->size;
 906         release_firmware(fw);
 907         return 0;
 908 }
 909
 910 static int DownloadMicrocode(struct drxd_state *state,
 911                              const u8 *pMCImage, u32 Length)
 912 {
 913         u8 *pSrc;
 914         u32 Address;
 915         u16 nBlocks;
 916         u16 BlockSize;
 917         u32 offset = 0;
 918         int i, status = 0;
 919
 920         pSrc = (u8 *) pMCImage;
 921         /* We're not using Flags */
 922         /* Flags = (pSrc[0] << 8) | pSrc[1]; */
 923         pSrc += sizeof(u16);
 924         offset += sizeof(u16);
 925         nBlocks = (pSrc[0] << 8) | pSrc[1];
 926         pSrc += sizeof(u16);
 927         offset += sizeof(u16);
 928
 929         for (i = 0; i < nBlocks; i++) {
 930                 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
 931                     (pSrc[2] << 8) | pSrc[3];
 932                 pSrc += sizeof(u32);
 933                 offset += sizeof(u32);
 934
 935                 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
 936                 pSrc += sizeof(u16);
 937                 offset += sizeof(u16);
 938
 939                 /* We're not using Flags */
 940                 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
 941                 pSrc += sizeof(u16);
 942                 offset += sizeof(u16);
 943
 944                 /* We're not using BlockCRC */
 945                 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
 946                 pSrc += sizeof(u16);
 947                 offset += sizeof(u16);
 948
 949                 status = WriteBlock(state, Address, BlockSize,
 950                                     pSrc, DRX_I2C_CLEARCRC);
 951                 if (status < 0)
 952                         break;
 953                 pSrc += BlockSize;
 954                 offset += BlockSize;
 955         }
 956
 957         return status;
 958 }
 959
 960 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
 961 {
 962         u32 nrRetries = 0;
 963         int status;
 964
 965         status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
 966         if (status < 0)
 967                 return status;
 968
 969         do {
 970                 nrRetries += 1;
 971                 if (nrRetries > DRXD_MAX_RETRIES) {
 972                         status = -1;
 973                         break;
 974                 }
 975                 status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0);
 976         } while (status != 0);
 977
 978         if (status >= 0)
 979                 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
 980         return status;
 981 }
 982
 983 static int HI_CfgCommand(struct drxd_state *state)
 984 {
 985         int status = 0;
 986
 987         mutex_lock(&state->mutex);
 988         Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
 989         Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
 990         Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
 991         Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
 992         Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
 993
 994         Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
 995
 996         if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
 997             HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
 998                 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
 999                                  HI_RA_RAM_SRV_CMD_CONFIG, 0);
1000         else
1001                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL);
1002         mutex_unlock(&state->mutex);
1003         return status;
1004 }
1005
1006 static int InitHI(struct drxd_state *state)
1007 {
1008         state->hi_cfg_wakeup_key = (state->chip_adr);
1009         /* port/bridge/power down ctrl */
1010         state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
1011         return HI_CfgCommand(state);
1012 }
1013
1014 static int HI_ResetCommand(struct drxd_state *state)
1015 {
1016         int status;
1017
1018         mutex_lock(&state->mutex);
1019         status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1020                          HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1021         if (status == 0)
1022                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL);
1023         mutex_unlock(&state->mutex);
1024         msleep(1);
1025         return status;
1026 }
1027
1028 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
1029 {
1030         state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
1031         if (bEnableBridge)
1032                 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1033         else
1034                 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1035
1036         return HI_CfgCommand(state);
1037 }
1038
1039 #define HI_TR_WRITE      0x9
1040 #define HI_TR_READ       0xA
1041 #define HI_TR_READ_WRITE 0xB
1042 #define HI_TR_BROADCAST  0x4
1043
1044 #if 0
1045 static int AtomicReadBlock(struct drxd_state *state,
1046                            u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1047 {
1048         int status;
1049         int i = 0;
1050
1051         /* Parameter check */
1052         if ((!pData) || ((DataSize & 1) != 0))
1053                 return -1;
1054
1055         mutex_lock(&state->mutex);
1056
1057         do {
1058                 /* Instruct HI to read n bytes */
1059                 /* TODO use proper names forthese egisters */
1060                 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1061                 if (status < 0)
1062                         break;
1063                 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1064                 if (status < 0)
1065                         break;
1066                 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1067                 if (status < 0)
1068                         break;
1069                 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1070                 if (status < 0)
1071                         break;
1072                 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1073                 if (status < 0)
1074                         break;
1075
1076                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1077                 if (status < 0)
1078                         break;
1079
1080         } while (0);
1081
1082         if (status >= 0) {
1083                 for (i = 0; i < (DataSize / 2); i += 1) {
1084                         u16 word;
1085
1086                         status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1087                                         &word, 0);
1088                         if (status < 0)
1089                                 break;
1090                         pData[2 * i] = (u8) (word & 0xFF);
1091                         pData[(2 * i) + 1] = (u8) (word >> 8);
1092                 }
1093         }
1094         mutex_unlock(&state->mutex);
1095         return status;
1096 }
1097
1098 static int AtomicReadReg32(struct drxd_state *state,
1099                            u32 Addr, u32 *pData, u8 Flags)
1100 {
1101         u8 buf[sizeof(u32)];
1102         int status;
1103
1104         if (!pData)
1105                 return -1;
1106         status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1107         *pData = (((u32) buf[0]) << 0) +
1108             (((u32) buf[1]) << 8) +
1109             (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1110         return status;
1111 }
1112 #endif
1113
1114 static int StopAllProcessors(struct drxd_state *state)
1115 {
1116         return Write16(state, HI_COMM_EXEC__A,
1117                        SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1118 }
1119
1120 static int EnableAndResetMB(struct drxd_state *state)
1121 {
1122         if (state->type_A) {
1123                 /* disable? monitor bus observe @ EC_OC */
1124                 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1125         }
1126
1127         /* do inverse broadcast, followed by explicit write to HI */
1128         Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1129         Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1130         return 0;
1131 }
1132
1133 static int InitCC(struct drxd_state *state)
1134 {
1135         int status = 0;
1136
1137         if (state->osc_clock_freq == 0 ||
1138             state->osc_clock_freq > 20000 ||
1139             (state->osc_clock_freq % 4000) != 0) {
1140                 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
1141                 return -1;
1142         }
1143
1144         status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1145         status |= Write16(state, CC_REG_PLL_MODE__A,
1146                                 CC_REG_PLL_MODE_BYPASS_PLL |
1147                                 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1148         status |= Write16(state, CC_REG_REF_DIVIDE__A,
1149                                 state->osc_clock_freq / 4000, 0);
1150         status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL,
1151                                 0);
1152         status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1153
1154         return status;
1155 }
1156
1157 static int ResetECOD(struct drxd_state *state)
1158 {
1159         int status = 0;
1160
1161         if (state->type_A)
1162                 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1163         else
1164                 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1165
1166         if (!(status < 0))
1167                 status = WriteTable(state, state->m_ResetECRAM);
1168         if (!(status < 0))
1169                 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1170         return status;
1171 }
1172
1173 /* Configure PGA switch */
1174
1175 static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1176 {
1177         int status;
1178         u16 AgModeLop = 0;
1179         u16 AgModeHip = 0;
1180         do {
1181                 if (pgaSwitch) {
1182                         /* PGA on */
1183                         /* fine gain */
1184                         status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1185                         if (status < 0)
1186                                 break;
1187                         AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1188                         AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1189                         status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1190                         if (status < 0)
1191                                 break;
1192
1193                         /* coarse gain */
1194                         status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1195                         if (status < 0)
1196                                 break;
1197                         AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1198                         AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1199                         status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1200                         if (status < 0)
1201                                 break;
1202
1203                         /* enable fine and coarse gain, enable AAF,
1204                            no ext resistor */
1205                         status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1206                         if (status < 0)
1207                                 break;
1208                 } else {
1209                         /* PGA off, bypass */
1210
1211                         /* fine gain */
1212                         status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1213                         if (status < 0)
1214                                 break;
1215                         AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1216                         AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1217                         status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1218                         if (status < 0)
1219                                 break;
1220
1221                         /* coarse gain */
1222                         status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1223                         if (status < 0)
1224                                 break;
1225                         AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1226                         AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1227                         status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1228                         if (status < 0)
1229                                 break;
1230
1231                         /* disable fine and coarse gain, enable AAF,
1232                            no ext resistor */
1233                         status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1234                         if (status < 0)
1235                                 break;
1236                 }
1237         } while (0);
1238         return status;
1239 }
1240
1241 static int InitFE(struct drxd_state *state)
1242 {
1243         int status;
1244
1245         do {
1246                 status = WriteTable(state, state->m_InitFE_1);
1247                 if (status < 0)
1248                         break;
1249
1250                 if (state->type_A) {
1251                         status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1252                                          FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1253                                          0);
1254                 } else {
1255                         if (state->PGA)
1256                                 status = SetCfgPga(state, 0);
1257                         else
1258                                 status =
1259                                     Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1260                                             B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1261                                             0);
1262                 }
1263
1264                 if (status < 0)
1265                         break;
1266                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1267                 if (status < 0)
1268                         break;
1269                 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1270                 if (status < 0)
1271                         break;
1272
1273                 status = WriteTable(state, state->m_InitFE_2);
1274                 if (status < 0)
1275                         break;
1276
1277         } while (0);
1278
1279         return status;
1280 }
1281
1282 static int InitFT(struct drxd_state *state)
1283 {
1284         /*
1285            norm OFFSET,  MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1286            SC stuff
1287          */
1288         return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1289 }
1290
1291 static int SC_WaitForReady(struct drxd_state *state)
1292 {
1293         int i;
1294
1295         for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1296                 int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0);
1297                 if (status == 0)
1298                         return status;
1299         }
1300         return -1;
1301 }
1302
1303 static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1304 {
1305         int status = 0, ret;
1306         u16 errCode;
1307
1308         status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1309         if (status < 0)
1310                 return status;
1311
1312         SC_WaitForReady(state);
1313
1314         ret = Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1315
1316         if (ret < 0 || errCode == 0xFFFF) {
1317                 printk(KERN_ERR "Command Error\n");
1318                 status = -1;
1319         }
1320
1321         return status;
1322 }
1323
1324 static int SC_ProcStartCommand(struct drxd_state *state,
1325                                u16 subCmd, u16 param0, u16 param1)
1326 {
1327         int ret, status = 0;
1328         u16 scExec;
1329
1330         mutex_lock(&state->mutex);
1331         do {
1332                 ret = Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1333                 if (ret < 0 || scExec != 1) {
1334                         status = -1;
1335                         break;
1336                 }
1337                 SC_WaitForReady(state);
1338                 status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1339                 status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1340                 status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1341
1342                 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1343         } while (0);
1344         mutex_unlock(&state->mutex);
1345         return status;
1346 }
1347
1348 static int SC_SetPrefParamCommand(struct drxd_state *state,
1349                                   u16 subCmd, u16 param0, u16 param1)
1350 {
1351         int status;
1352
1353         mutex_lock(&state->mutex);
1354         do {
1355                 status = SC_WaitForReady(state);
1356                 if (status < 0)
1357                         break;
1358                 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1359                 if (status < 0)
1360                         break;
1361                 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1362                 if (status < 0)
1363                         break;
1364                 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1365                 if (status < 0)
1366                         break;
1367
1368                 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1369                 if (status < 0)
1370                         break;
1371         } while (0);
1372         mutex_unlock(&state->mutex);
1373         return status;
1374 }
1375
1376 #if 0
1377 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1378 {
1379         int status = 0;
1380
1381         mutex_lock(&state->mutex);
1382         do {
1383                 status = SC_WaitForReady(state);
1384                 if (status < 0)
1385                         break;
1386                 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1387                 if (status < 0)
1388                         break;
1389                 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1390                 if (status < 0)
1391                         break;
1392         } while (0);
1393         mutex_unlock(&state->mutex);
1394         return status;
1395 }
1396 #endif
1397
1398 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1399 {
1400         int status;
1401
1402         do {
1403                 u16 EcOcRegIprInvMpg = 0;
1404                 u16 EcOcRegOcModeLop = 0;
1405                 u16 EcOcRegOcModeHip = 0;
1406                 u16 EcOcRegOcMpgSio = 0;
1407
1408                 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1409
1410                 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1411                         if (bEnableOutput) {
1412                                 EcOcRegOcModeHip |=
1413                                     B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1414                         } else
1415                                 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1416                         EcOcRegOcModeLop |=
1417                             EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1418                 } else {
1419                         EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1420
1421                         if (bEnableOutput)
1422                                 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1423                         else
1424                                 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1425
1426                         /* Don't Insert RS Byte */
1427                         if (state->insert_rs_byte) {
1428                                 EcOcRegOcModeLop &=
1429                                     (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1430                                 EcOcRegOcModeHip &=
1431                                     (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1432                                 EcOcRegOcModeHip |=
1433                                     EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1434                         } else {
1435                                 EcOcRegOcModeLop |=
1436                                     EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1437                                 EcOcRegOcModeHip &=
1438                                     (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1439                                 EcOcRegOcModeHip |=
1440                                     EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1441                         }
1442
1443                         /* Mode = Parallel */
1444                         if (state->enable_parallel)
1445                                 EcOcRegOcModeLop &=
1446                                     (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1447                         else
1448                                 EcOcRegOcModeLop |=
1449                                     EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1450                 }
1451                 /* Invert Data */
1452                 /* EcOcRegIprInvMpg |= 0x00FF; */
1453                 EcOcRegIprInvMpg &= (~(0x00FF));
1454
1455                 /* Invert Error ( we don't use the pin ) */
1456                 /*  EcOcRegIprInvMpg |= 0x0100; */
1457                 EcOcRegIprInvMpg &= (~(0x0100));
1458
1459                 /* Invert Start ( we don't use the pin ) */
1460                 /* EcOcRegIprInvMpg |= 0x0200; */
1461                 EcOcRegIprInvMpg &= (~(0x0200));
1462
1463                 /* Invert Valid ( we don't use the pin ) */
1464                 /* EcOcRegIprInvMpg |= 0x0400; */
1465                 EcOcRegIprInvMpg &= (~(0x0400));
1466
1467                 /* Invert Clock */
1468                 /* EcOcRegIprInvMpg |= 0x0800; */
1469                 EcOcRegIprInvMpg &= (~(0x0800));
1470
1471                 /* EcOcRegOcModeLop =0x05; */
1472                 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1473                 if (status < 0)
1474                         break;
1475                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1476                 if (status < 0)
1477                         break;
1478                 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1479                 if (status < 0)
1480                         break;
1481                 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1482                 if (status < 0)
1483                         break;
1484         } while (0);
1485         return status;
1486 }
1487
1488 static int SetDeviceTypeId(struct drxd_state *state)
1489 {
1490         int status = 0;
1491         u16 deviceId = 0;
1492
1493         do {
1494                 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1495                 if (status < 0)
1496                         break;
1497                 /* TODO: why twice? */
1498                 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1499                 if (status < 0)
1500                         break;
1501                 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
1502
1503                 state->type_A = 0;
1504                 state->PGA = 0;
1505                 state->diversity = 0;
1506                 if (deviceId == 0) {    /* on A2 only 3975 available */
1507                         state->type_A = 1;
1508                         printk(KERN_INFO "DRX3975D-A2\n");
1509                 } else {
1510                         deviceId >>= 12;
1511                         printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
1512                         switch (deviceId) {
1513                         case 4:
1514                                 state->diversity = 1;
1515                                 /* fall through */
1516                         case 3:
1517                         case 7:
1518                                 state->PGA = 1;
1519                                 break;
1520                         case 6:
1521                                 state->diversity = 1;
1522                                 /* fall through */
1523                         case 5:
1524                         case 8:
1525                                 break;
1526                         default:
1527                                 status = -1;
1528                                 break;
1529                         }
1530                 }
1531         } while (0);
1532
1533         if (status < 0)
1534                 return status;
1535
1536         /* Init Table selection */
1537         state->m_InitAtomicRead = DRXD_InitAtomicRead;
1538         state->m_InitSC = DRXD_InitSC;
1539         state->m_ResetECRAM = DRXD_ResetECRAM;
1540         if (state->type_A) {
1541                 state->m_ResetCEFR = DRXD_ResetCEFR;
1542                 state->m_InitFE_1 = DRXD_InitFEA2_1;
1543                 state->m_InitFE_2 = DRXD_InitFEA2_2;
1544                 state->m_InitCP = DRXD_InitCPA2;
1545                 state->m_InitCE = DRXD_InitCEA2;
1546                 state->m_InitEQ = DRXD_InitEQA2;
1547                 state->m_InitEC = DRXD_InitECA2;
1548                 if (load_firmware(state, DRX_FW_FILENAME_A2))
1549                         return -EIO;
1550         } else {
1551                 state->m_ResetCEFR = NULL;
1552                 state->m_InitFE_1 = DRXD_InitFEB1_1;
1553                 state->m_InitFE_2 = DRXD_InitFEB1_2;
1554                 state->m_InitCP = DRXD_InitCPB1;
1555                 state->m_InitCE = DRXD_InitCEB1;
1556                 state->m_InitEQ = DRXD_InitEQB1;
1557                 state->m_InitEC = DRXD_InitECB1;
1558                 if (load_firmware(state, DRX_FW_FILENAME_B1))
1559                         return -EIO;
1560         }
1561         if (state->diversity) {
1562                 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1563                 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1564                 state->m_DisableDiversity = DRXD_DisableDiversity;
1565                 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1566                 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1567                 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1568                 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1569         } else {
1570                 state->m_InitDiversityFront = NULL;
1571                 state->m_InitDiversityEnd = NULL;
1572                 state->m_DisableDiversity = NULL;
1573                 state->m_StartDiversityFront = NULL;
1574                 state->m_StartDiversityEnd = NULL;
1575                 state->m_DiversityDelay8MHZ = NULL;
1576                 state->m_DiversityDelay6MHZ = NULL;
1577         }
1578
1579         return status;
1580 }
1581
1582 static int CorrectSysClockDeviation(struct drxd_state *state)
1583 {
1584         int status;
1585         s32 incr = 0;
1586         s32 nomincr = 0;
1587         u32 bandwidth = 0;
1588         u32 sysClockInHz = 0;
1589         u32 sysClockFreq = 0;   /* in kHz */
1590         s16 oscClockDeviation;
1591         s16 Diff;
1592
1593         do {
1594                 /* Retrieve bandwidth and incr, sanity check */
1595
1596                 /* These accesses should be AtomicReadReg32, but that
1597                    causes trouble (at least for diversity */
1598                 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1599                 if (status < 0)
1600                         break;
1601                 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1602                 if (status < 0)
1603                         break;
1604
1605                 if (state->type_A) {
1606                         if ((nomincr - incr < -500) || (nomincr - incr > 500))
1607                                 break;
1608                 } else {
1609                         if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1610                                 break;
1611                 }
1612
1613                 switch (state->props.bandwidth_hz) {
1614                 case 8000000:
1615                         bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1616                         break;
1617                 case 7000000:
1618                         bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1619                         break;
1620                 case 6000000:
1621                         bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1622                         break;
1623                 default:
1624                         return -1;
1625                         break;
1626                 }
1627
1628                 /* Compute new sysclock value
1629                    sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1630                 incr += (1 << 23);
1631                 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1632                 sysClockFreq = (u32) (sysClockInHz / 1000);
1633                 /* rounding */
1634                 if ((sysClockInHz % 1000) > 500)
1635                         sysClockFreq++;
1636
1637                 /* Compute clock deviation in ppm */
1638                 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1639                                              (s32)
1640                                              (state->expected_sys_clock_freq)) *
1641                                             1000000L) /
1642                                            (s32)
1643                                            (state->expected_sys_clock_freq));
1644
1645                 Diff = oscClockDeviation - state->osc_clock_deviation;
1646                 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1647                 if (Diff >= -200 && Diff <= 200) {
1648                         state->sys_clock_freq = (u16) sysClockFreq;
1649                         if (oscClockDeviation != state->osc_clock_deviation) {
1650                                 if (state->config.osc_deviation) {
1651                                         state->config.osc_deviation(state->priv,
1652                                                                     oscClockDeviation,
1653                                                                     1);
1654                                         state->osc_clock_deviation =
1655                                             oscClockDeviation;
1656                                 }
1657                         }
1658                         /* switch OFF SRMM scan in SC */
1659                         status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1660                         if (status < 0)
1661                                 break;
1662                         /* overrule FE_IF internal value for
1663                            proper re-locking */
1664                         status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1665                         if (status < 0)
1666                                 break;
1667                         state->cscd_state = CSCD_SAVED;
1668                 }
1669         } while (0);
1670
1671         return status;
1672 }
1673
1674 static int DRX_Stop(struct drxd_state *state)
1675 {
1676         int status;
1677
1678         if (state->drxd_state != DRXD_STARTED)
1679                 return 0;
1680
1681         do {
1682                 if (state->cscd_state != CSCD_SAVED) {
1683                         u32 lock;
1684                         status = DRX_GetLockStatus(state, &lock);
1685                         if (status < 0)
1686                                 break;
1687                 }
1688
1689                 status = StopOC(state);
1690                 if (status < 0)
1691                         break;
1692
1693                 state->drxd_state = DRXD_STOPPED;
1694
1695                 status = ConfigureMPEGOutput(state, 0);
1696                 if (status < 0)
1697                         break;
1698
1699                 if (state->type_A) {
1700                         /* Stop relevant processors off the device */
1701                         status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1702                         if (status < 0)
1703                                 break;
1704
1705                         status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1706                         if (status < 0)
1707                                 break;
1708                         status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1709                         if (status < 0)
1710                                 break;
1711                 } else {
1712                         /* Stop all processors except HI & CC & FE */
1713                         status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1714                         if (status < 0)
1715                                 break;
1716                         status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1717                         if (status < 0)
1718                                 break;
1719                         status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1720                         if (status < 0)
1721                                 break;
1722                         status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1723                         if (status < 0)
1724                                 break;
1725                         status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1726                         if (status < 0)
1727                                 break;
1728                         status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1729                         if (status < 0)
1730                                 break;
1731                         status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1732                         if (status < 0)
1733                                 break;
1734                 }
1735
1736         } while (0);
1737         return status;
1738 }
1739
1740 #if 0   /* Currently unused */
1741 static int SetOperationMode(struct drxd_state *state, int oMode)
1742 {
1743         int status;
1744
1745         do {
1746                 if (state->drxd_state != DRXD_STOPPED) {
1747                         status = -1;
1748                         break;
1749                 }
1750
1751                 if (oMode == state->operation_mode) {
1752                         status = 0;
1753                         break;
1754                 }
1755
1756                 if (oMode != OM_Default && !state->diversity) {
1757                         status = -1;
1758                         break;
1759                 }
1760
1761                 switch (oMode) {
1762                 case OM_DVBT_Diversity_Front:
1763                         status = WriteTable(state, state->m_InitDiversityFront);
1764                         break;
1765                 case OM_DVBT_Diversity_End:
1766                         status = WriteTable(state, state->m_InitDiversityEnd);
1767                         break;
1768                 case OM_Default:
1769                         /* We need to check how to
1770                            get DRXD out of diversity */
1771                 default:
1772                         status = WriteTable(state, state->m_DisableDiversity);
1773                         break;
1774                 }
1775         } while (0);
1776
1777         if (!status)
1778                 state->operation_mode = oMode;
1779         return status;
1780 }
1781 #endif
1782
1783 static int StartDiversity(struct drxd_state *state)
1784 {
1785         int status = 0;
1786         u16 rcControl;
1787
1788         do {
1789                 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1790                         status = WriteTable(state, state->m_StartDiversityFront);
1791                         if (status < 0)
1792                                 break;
1793                 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1794                         status = WriteTable(state, state->m_StartDiversityEnd);
1795                         if (status < 0)
1796                                 break;
1797                         if (state->props.bandwidth_hz == 8000000) {
1798                                 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1799                                 if (status < 0)
1800                                         break;
1801                         } else {
1802                                 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1803                                 if (status < 0)
1804                                         break;
1805                         }
1806
1807                         status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1808                         if (status < 0)
1809                                 break;
1810                         rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1811                         rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1812                             /*  combining enabled */
1813                             B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1814                             B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1815                             B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1816                         status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1817                         if (status < 0)
1818                                 break;
1819                 }
1820         } while (0);
1821         return status;
1822 }
1823
1824 static int SetFrequencyShift(struct drxd_state *state,
1825                              u32 offsetFreq, int channelMirrored)
1826 {
1827         int negativeShift = (state->tuner_mirrors == channelMirrored);
1828
1829         /* Handle all mirroring
1830          *
1831          * Note: ADC mirroring (aliasing) is implictly handled by limiting
1832          * feFsRegAddInc to 28 bits below
1833          * (if the result before masking is more than 28 bits, this means
1834          *  that the ADC is mirroring.
1835          * The masking is in fact the aliasing of the ADC)
1836          *
1837          */
1838
1839         /* Compute register value, unsigned computation */
1840         state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1841                                          offsetFreq,
1842                                          1 << 28, state->sys_clock_freq);
1843         /* Remove integer part */
1844         state->fe_fs_add_incr &= 0x0FFFFFFFL;
1845         if (negativeShift)
1846                 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1847
1848         /* Save the frequency shift without tunerOffset compensation
1849            for CtrlGetChannel. */
1850         state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1851                                              1 << 28, state->sys_clock_freq);
1852         /* Remove integer part */
1853         state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1854         if (negativeShift)
1855                 state->org_fe_fs_add_incr = ((1L << 28) -
1856                                              state->org_fe_fs_add_incr);
1857
1858         return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1859                        state->fe_fs_add_incr, 0);
1860 }
1861
1862 static int SetCfgNoiseCalibration(struct drxd_state *state,
1863                                   struct SNoiseCal *noiseCal)
1864 {
1865         u16 beOptEna;
1866         int status = 0;
1867
1868         do {
1869                 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1870                 if (status < 0)
1871                         break;
1872                 if (noiseCal->cpOpt) {
1873                         beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1874                 } else {
1875                         beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1876                         status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1877                         if (status < 0)
1878                                 break;
1879                 }
1880                 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1881                 if (status < 0)
1882                         break;
1883
1884                 if (!state->type_A) {
1885                         status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1886                         if (status < 0)
1887                                 break;
1888                         status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1889                         if (status < 0)
1890                                 break;
1891                 }
1892         } while (0);
1893
1894         return status;
1895 }
1896
1897 static int DRX_Start(struct drxd_state *state, s32 off)
1898 {
1899         struct dtv_frontend_properties *p = &state->props;
1900         int status;
1901
1902         u16 transmissionParams = 0;
1903         u16 operationMode = 0;
1904         u16 qpskTdTpsPwr = 0;
1905         u16 qam16TdTpsPwr = 0;
1906         u16 qam64TdTpsPwr = 0;
1907         u32 feIfIncr = 0;
1908         u32 bandwidth = 0;
1909         int mirrorFreqSpect;
1910
1911         u16 qpskSnCeGain = 0;
1912         u16 qam16SnCeGain = 0;
1913         u16 qam64SnCeGain = 0;
1914         u16 qpskIsGainMan = 0;
1915         u16 qam16IsGainMan = 0;
1916         u16 qam64IsGainMan = 0;
1917         u16 qpskIsGainExp = 0;
1918         u16 qam16IsGainExp = 0;
1919         u16 qam64IsGainExp = 0;
1920         u16 bandwidthParam = 0;
1921
1922         if (off < 0)
1923                 off = (off - 500) / 1000;
1924         else
1925                 off = (off + 500) / 1000;
1926
1927         do {
1928                 if (state->drxd_state != DRXD_STOPPED)
1929                         return -1;
1930                 status = ResetECOD(state);
1931                 if (status < 0)
1932                         break;
1933                 if (state->type_A) {
1934                         status = InitSC(state);
1935                         if (status < 0)
1936                                 break;
1937                 } else {
1938                         status = InitFT(state);
1939                         if (status < 0)
1940                                 break;
1941                         status = InitCP(state);
1942                         if (status < 0)
1943                                 break;
1944                         status = InitCE(state);
1945                         if (status < 0)
1946                                 break;
1947                         status = InitEQ(state);
1948                         if (status < 0)
1949                                 break;
1950                         status = InitSC(state);
1951                         if (status < 0)
1952                                 break;
1953                 }
1954
1955                 /* Restore current IF & RF AGC settings */
1956
1957                 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1958                 if (status < 0)
1959                         break;
1960                 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1961                 if (status < 0)
1962                         break;
1963
1964                 mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1965
1966                 switch (p->transmission_mode) {
1967                 default:        /* Not set, detect it automatically */
1968                         operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1969                         /* fall through - try first guess DRX_FFTMODE_8K */
1970                 case TRANSMISSION_MODE_8K:
1971                         transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1972                         if (state->type_A) {
1973                                 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1974                                 if (status < 0)
1975                                         break;
1976                                 qpskSnCeGain = 99;
1977                                 qam16SnCeGain = 83;
1978                                 qam64SnCeGain = 67;
1979                         }
1980                         break;
1981                 case TRANSMISSION_MODE_2K:
1982                         transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1983                         if (state->type_A) {
1984                                 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1985                                 if (status < 0)
1986                                         break;
1987                                 qpskSnCeGain = 97;
1988                                 qam16SnCeGain = 71;
1989                                 qam64SnCeGain = 65;
1990                         }
1991                         break;
1992                 }
1993
1994                 switch (p->guard_interval) {
1995                 case GUARD_INTERVAL_1_4:
1996                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
1997                         break;
1998                 case GUARD_INTERVAL_1_8:
1999                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2000                         break;
2001                 case GUARD_INTERVAL_1_16:
2002                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2003                         break;
2004                 case GUARD_INTERVAL_1_32:
2005                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2006                         break;
2007                 default:        /* Not set, detect it automatically */
2008                         operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2009                         /* try first guess 1/4 */
2010                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2011                         break;
2012                 }
2013
2014                 switch (p->hierarchy) {
2015                 case HIERARCHY_1:
2016                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2017                         if (state->type_A) {
2018                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2019                                 if (status < 0)
2020                                         break;
2021                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2022                                 if (status < 0)
2023                                         break;
2024
2025                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2026                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2027                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2028
2029                                 qpskIsGainMan =
2030                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2031                                 qam16IsGainMan =
2032                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2033                                 qam64IsGainMan =
2034                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2035
2036                                 qpskIsGainExp =
2037                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2038                                 qam16IsGainExp =
2039                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2040                                 qam64IsGainExp =
2041                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2042                         }
2043                         break;
2044
2045                 case HIERARCHY_2:
2046                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2047                         if (state->type_A) {
2048                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2049                                 if (status < 0)
2050                                         break;
2051                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2052                                 if (status < 0)
2053                                         break;
2054
2055                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2056                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2057                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2058
2059                                 qpskIsGainMan =
2060                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2061                                 qam16IsGainMan =
2062                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
2063                                 qam64IsGainMan =
2064                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
2065
2066                                 qpskIsGainExp =
2067                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2068                                 qam16IsGainExp =
2069                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
2070                                 qam64IsGainExp =
2071                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
2072                         }
2073                         break;
2074                 case HIERARCHY_4:
2075                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2076                         if (state->type_A) {
2077                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2078                                 if (status < 0)
2079                                         break;
2080                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2081                                 if (status < 0)
2082                                         break;
2083
2084                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2085                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2086                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2087
2088                                 qpskIsGainMan =
2089                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2090                                 qam16IsGainMan =
2091                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
2092                                 qam64IsGainMan =
2093                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2094
2095                                 qpskIsGainExp =
2096                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2097                                 qam16IsGainExp =
2098                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2099                                 qam64IsGainExp =
2100                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2101                         }
2102                         break;
2103                 case HIERARCHY_AUTO:
2104                 default:
2105                         /* Not set, detect it automatically, start with none */
2106                         operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2107                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2108                         if (state->type_A) {
2109                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2110                                 if (status < 0)
2111                                         break;
2112                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2113                                 if (status < 0)
2114                                         break;
2115
2116                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2117                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2118                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2119
2120                                 qpskIsGainMan =
2121                                     SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2122                                 qam16IsGainMan =
2123                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2124                                 qam64IsGainMan =
2125                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2126
2127                                 qpskIsGainExp =
2128                                     SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2129                                 qam16IsGainExp =
2130                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2131                                 qam64IsGainExp =
2132                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2133                         }
2134                         break;
2135                 }
2136                 if (status < 0)
2137                         break;
2138
2139                 switch (p->modulation) {
2140                 default:
2141                         operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2142                         /* fall through - try first guess DRX_CONSTELLATION_QAM64 */
2143                 case QAM_64:
2144                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2145                         if (state->type_A) {
2146                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2147                                 if (status < 0)
2148                                         break;
2149                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2150                                 if (status < 0)
2151                                         break;
2152                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2153                                 if (status < 0)
2154                                         break;
2155                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2156                                 if (status < 0)
2157                                         break;
2158                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2159                                 if (status < 0)
2160                                         break;
2161
2162                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2163                                 if (status < 0)
2164                                         break;
2165                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2166                                 if (status < 0)
2167                                         break;
2168                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2169                                 if (status < 0)
2170                                         break;
2171                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2172                                 if (status < 0)
2173                                         break;
2174                         }
2175                         break;
2176                 case QPSK:
2177                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2178                         if (state->type_A) {
2179                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2180                                 if (status < 0)
2181                                         break;
2182                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2183                                 if (status < 0)
2184                                         break;
2185                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2186                                 if (status < 0)
2187                                         break;
2188                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2189                                 if (status < 0)
2190                                         break;
2191                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2192                                 if (status < 0)
2193                                         break;
2194
2195                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2196                                 if (status < 0)
2197                                         break;
2198                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2199                                 if (status < 0)
2200                                         break;
2201                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2202                                 if (status < 0)
2203                                         break;
2204                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2205                                 if (status < 0)
2206                                         break;
2207                         }
2208                         break;
2209
2210                 case QAM_16:
2211                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2212                         if (state->type_A) {
2213                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2214                                 if (status < 0)
2215                                         break;
2216                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2217                                 if (status < 0)
2218                                         break;
2219                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2220                                 if (status < 0)
2221                                         break;
2222                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2223                                 if (status < 0)
2224                                         break;
2225                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2226                                 if (status < 0)
2227                                         break;
2228
2229                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2230                                 if (status < 0)
2231                                         break;
2232                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2233                                 if (status < 0)
2234                                         break;
2235                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2236                                 if (status < 0)
2237                                         break;
2238                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2239                                 if (status < 0)
2240                                         break;
2241                         }
2242                         break;
2243
2244                 }
2245                 if (status < 0)
2246                         break;
2247
2248                 switch (DRX_CHANNEL_HIGH) {
2249                 default:
2250                 case DRX_CHANNEL_AUTO:
2251                 case DRX_CHANNEL_LOW:
2252                         transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2253                         status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2254                         break;
2255                 case DRX_CHANNEL_HIGH:
2256                         transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2257                         status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2258                         break;
2259                 }
2260
2261                 switch (p->code_rate_HP) {
2262                 case FEC_1_2:
2263                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2264                         if (state->type_A)
2265                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2266                         break;
2267                 default:
2268                         operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2269                         /* fall through */
2270                 case FEC_2_3:
2271                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2272                         if (state->type_A)
2273                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2274                         break;
2275                 case FEC_3_4:
2276                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2277                         if (state->type_A)
2278                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2279                         break;
2280                 case FEC_5_6:
2281                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2282                         if (state->type_A)
2283                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2284                         break;
2285                 case FEC_7_8:
2286                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2287                         if (state->type_A)
2288                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2289                         break;
2290                 }
2291                 if (status < 0)
2292                         break;
2293
2294                 /* First determine real bandwidth (Hz) */
2295                 /* Also set delay for impulse noise cruncher (only A2) */
2296                 /* Also set parameters for EC_OC fix, note
2297                    EC_OC_REG_TMD_HIL_MAR is changed
2298                    by SC for fix for some 8K,1/8 guard but is restored by
2299                    InitEC and ResetEC
2300                    functions */
2301                 switch (p->bandwidth_hz) {
2302                 case 0:
2303                         p->bandwidth_hz = 8000000;
2304                         /* fall through */
2305                 case 8000000:
2306                         /* (64/7)*(8/8)*1000000 */
2307                         bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2308
2309                         bandwidthParam = 0;
2310                         status = Write16(state,
2311                                          FE_AG_REG_IND_DEL__A, 50, 0x0000);
2312                         break;
2313                 case 7000000:
2314                         /* (64/7)*(7/8)*1000000 */
2315                         bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2316                         bandwidthParam = 0x4807;        /*binary:0100 1000 0000 0111 */
2317                         status = Write16(state,
2318                                          FE_AG_REG_IND_DEL__A, 59, 0x0000);
2319                         break;
2320                 case 6000000:
2321                         /* (64/7)*(6/8)*1000000 */
2322                         bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2323                         bandwidthParam = 0x0F07;        /*binary: 0000 1111 0000 0111 */
2324                         status = Write16(state,
2325                                          FE_AG_REG_IND_DEL__A, 71, 0x0000);
2326                         break;
2327                 default:
2328                         status = -EINVAL;
2329                 }
2330                 if (status < 0)
2331                         break;
2332
2333                 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2334                 if (status < 0)
2335                         break;
2336
2337                 {
2338                         u16 sc_config;
2339                         status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2340                         if (status < 0)
2341                                 break;
2342
2343                         /* enable SLAVE mode in 2k 1/32 to
2344                            prevent timing change glitches */
2345                         if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2346                             (p->guard_interval == GUARD_INTERVAL_1_32)) {
2347                                 /* enable slave */
2348                                 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2349                         } else {
2350                                 /* disable slave */
2351                                 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2352                         }
2353                         status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2354                         if (status < 0)
2355                                 break;
2356                 }
2357
2358                 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2359                 if (status < 0)
2360                         break;
2361
2362                 if (state->cscd_state == CSCD_INIT) {
2363                         /* switch on SRMM scan in SC */
2364                         status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2365                         if (status < 0)
2366                                 break;
2367 /*            CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2368                         state->cscd_state = CSCD_SET;
2369                 }
2370
2371                 /* Now compute FE_IF_REG_INCR */
2372                 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2373                    ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2374                 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2375                                     (1ULL << 21), bandwidth) - (1 << 23);
2376                 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2377                 if (status < 0)
2378                         break;
2379                 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2380                 if (status < 0)
2381                         break;
2382                 /* Bandwidth setting done */
2383
2384                 /* Mirror & frequency offset */
2385                 SetFrequencyShift(state, off, mirrorFreqSpect);
2386
2387                 /* Start SC, write channel settings to SC */
2388
2389                 /* Enable SC after setting all other parameters */
2390                 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2391                 if (status < 0)
2392                         break;
2393                 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2394                 if (status < 0)
2395                         break;
2396
2397                 /* Write SC parameter registers, operation mode */
2398 #if 1
2399                 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2400                                  SC_RA_RAM_OP_AUTO_GUARD__M |
2401                                  SC_RA_RAM_OP_AUTO_CONST__M |
2402                                  SC_RA_RAM_OP_AUTO_HIER__M |
2403                                  SC_RA_RAM_OP_AUTO_RATE__M);
2404 #endif
2405                 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2406                 if (status < 0)
2407                         break;
2408
2409                 /* Start correct processes to get in lock */
2410                 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2411                 if (status < 0)
2412                         break;
2413
2414                 status = StartOC(state);
2415                 if (status < 0)
2416                         break;
2417
2418                 if (state->operation_mode != OM_Default) {
2419                         status = StartDiversity(state);
2420                         if (status < 0)
2421                                 break;
2422                 }
2423
2424                 state->drxd_state = DRXD_STARTED;
2425         } while (0);
2426
2427         return status;
2428 }
2429
2430 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2431 {
2432         u32 ulRfAgcOutputLevel = 0xffffffff;
2433         u32 ulRfAgcSettleLevel = 528;   /* Optimum value for MT2060 */
2434         u32 ulRfAgcMinLevel = 0;        /* Currently unused */
2435         u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2436         u32 ulRfAgcSpeed = 0;   /* Currently unused */
2437         u32 ulRfAgcMode = 0;    /*2;   Off */
2438         u32 ulRfAgcR1 = 820;
2439         u32 ulRfAgcR2 = 2200;
2440         u32 ulRfAgcR3 = 150;
2441         u32 ulIfAgcMode = 0;    /* Auto */
2442         u32 ulIfAgcOutputLevel = 0xffffffff;
2443         u32 ulIfAgcSettleLevel = 0xffffffff;
2444         u32 ulIfAgcMinLevel = 0xffffffff;
2445         u32 ulIfAgcMaxLevel = 0xffffffff;
2446         u32 ulIfAgcSpeed = 0xffffffff;
2447         u32 ulIfAgcR1 = 820;
2448         u32 ulIfAgcR2 = 2200;
2449         u32 ulIfAgcR3 = 150;
2450         u32 ulClock = state->config.clock;
2451         u32 ulSerialMode = 0;
2452         u32 ulEcOcRegOcModeLop = 4;     /* Dynamic DTO source */
2453         u32 ulHiI2cDelay = HI_I2C_DELAY;
2454         u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2455         u32 ulHiI2cPatch = 0;
2456         u32 ulEnvironment = APPENV_PORTABLE;
2457         u32 ulEnvironmentDiversity = APPENV_MOBILE;
2458         u32 ulIFFilter = IFFILTER_SAW;
2459
2460         state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2461         state->if_agc_cfg.outputLevel = 0;
2462         state->if_agc_cfg.settleLevel = 140;
2463         state->if_agc_cfg.minOutputLevel = 0;
2464         state->if_agc_cfg.maxOutputLevel = 1023;
2465         state->if_agc_cfg.speed = 904;
2466
2467         if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2468                 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2469                 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2470         }
2471
2472         if (ulIfAgcMode == 0 &&
2473             ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2474             ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2475             ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2476             ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2477                 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2478                 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2479                 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2480                 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2481                 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2482         }
2483
2484         state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2485         state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2486         state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2487
2488         state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2489         state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2490         state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2491
2492         state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2493         /* rest of the RFAgcCfg structure currently unused */
2494         if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2495                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2496                 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2497         }
2498
2499         if (ulRfAgcMode == 0 &&
2500             ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2501             ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2502             ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2503             ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2504                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2505                 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2506                 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2507                 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2508                 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2509         }
2510
2511         if (ulRfAgcMode == 2)
2512                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2513
2514         if (ulEnvironment <= 2)
2515                 state->app_env_default = (enum app_env)
2516                     (ulEnvironment);
2517         if (ulEnvironmentDiversity <= 2)
2518                 state->app_env_diversity = (enum app_env)
2519                     (ulEnvironmentDiversity);
2520
2521         if (ulIFFilter == IFFILTER_DISCRETE) {
2522                 /* discrete filter */
2523                 state->noise_cal.cpOpt = 0;
2524                 state->noise_cal.cpNexpOfs = 40;
2525                 state->noise_cal.tdCal2k = -40;
2526                 state->noise_cal.tdCal8k = -24;
2527         } else {
2528                 /* SAW filter */
2529                 state->noise_cal.cpOpt = 1;
2530                 state->noise_cal.cpNexpOfs = 0;
2531                 state->noise_cal.tdCal2k = -21;
2532                 state->noise_cal.tdCal8k = -24;
2533         }
2534         state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2535
2536         state->chip_adr = (state->config.demod_address << 1) | 1;
2537         switch (ulHiI2cPatch) {
2538         case 1:
2539                 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2540                 break;
2541         case 3:
2542                 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2543                 break;
2544         default:
2545                 state->m_HiI2cPatch = NULL;
2546         }
2547
2548         /* modify tuner and clock attributes */
2549         state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2550         /* expected system clock frequency in kHz */
2551         state->expected_sys_clock_freq = 48000;
2552         /* real system clock frequency in kHz */
2553         state->sys_clock_freq = 48000;
2554         state->osc_clock_freq = (u16) ulClock;
2555         state->osc_clock_deviation = 0;
2556         state->cscd_state = CSCD_INIT;
2557         state->drxd_state = DRXD_UNINITIALIZED;
2558
2559         state->PGA = 0;
2560         state->type_A = 0;
2561         state->tuner_mirrors = 0;
2562
2563         /* modify MPEG output attributes */
2564         state->insert_rs_byte = state->config.insert_rs_byte;
2565         state->enable_parallel = (ulSerialMode != 1);
2566
2567         /* Timing div, 250ns/Psys */
2568         /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2569
2570         state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2571                                           ulHiI2cDelay) / 1000;
2572         /* Bridge delay, uses oscilator clock */
2573         /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2574         state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2575                                             ulHiI2cBridgeDelay) / 1000;
2576
2577         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2578         /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2579         state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2580         return 0;
2581 }
2582
2583 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
2584 {
2585         int status = 0;
2586         u32 driverVersion;
2587
2588         if (state->init_done)
2589                 return 0;
2590
2591         CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2592
2593         do {
2594                 state->operation_mode = OM_Default;
2595
2596                 status = SetDeviceTypeId(state);
2597                 if (status < 0)
2598                         break;
2599
2600                 /* Apply I2c address patch to B1 */
2601                 if (!state->type_A && state->m_HiI2cPatch) {
2602                         status = WriteTable(state, state->m_HiI2cPatch);
2603                         if (status < 0)
2604                                 break;
2605                 }
2606
2607                 if (state->type_A) {
2608                         /* HI firmware patch for UIO readout,
2609                            avoid clearing of result register */
2610                         status = Write16(state, 0x43012D, 0x047f, 0);
2611                         if (status < 0)
2612                                 break;
2613                 }
2614
2615                 status = HI_ResetCommand(state);
2616                 if (status < 0)
2617                         break;
2618
2619                 status = StopAllProcessors(state);
2620                 if (status < 0)
2621                         break;
2622                 status = InitCC(state);
2623                 if (status < 0)
2624                         break;
2625
2626                 state->osc_clock_deviation = 0;
2627
2628                 if (state->config.osc_deviation)
2629                         state->osc_clock_deviation =
2630                             state->config.osc_deviation(state->priv, 0, 0);
2631                 {
2632                         /* Handle clock deviation */
2633                         s32 devB;
2634                         s32 devA = (s32) (state->osc_clock_deviation) *
2635                             (s32) (state->expected_sys_clock_freq);
2636                         /* deviation in kHz */
2637                         s32 deviation = (devA / (1000000L));
2638                         /* rounding, signed */
2639                         if (devA > 0)
2640                                 devB = (2);
2641                         else
2642                                 devB = (-2);
2643                         if ((devB * (devA % 1000000L) > 1000000L)) {
2644                                 /* add +1 or -1 */
2645                                 deviation += (devB / 2);
2646                         }
2647
2648                         state->sys_clock_freq =
2649                             (u16) ((state->expected_sys_clock_freq) +
2650                                    deviation);
2651                 }
2652                 status = InitHI(state);
2653                 if (status < 0)
2654                         break;
2655                 status = InitAtomicRead(state);
2656                 if (status < 0)
2657                         break;
2658
2659                 status = EnableAndResetMB(state);
2660                 if (status < 0)
2661                         break;
2662                 if (state->type_A) {
2663                         status = ResetCEFR(state);
2664                         if (status < 0)
2665                                 break;
2666                 }
2667                 if (fw) {
2668                         status = DownloadMicrocode(state, fw, fw_size);
2669                         if (status < 0)
2670                                 break;
2671                 } else {
2672                         status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2673                         if (status < 0)
2674                                 break;
2675                 }
2676
2677                 if (state->PGA) {
2678                         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2679                         SetCfgPga(state, 0);    /* PGA = 0 dB */
2680                 } else {
2681                         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2682                 }
2683
2684                 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2685
2686                 status = InitFE(state);
2687                 if (status < 0)
2688                         break;
2689                 status = InitFT(state);
2690                 if (status < 0)
2691                         break;
2692                 status = InitCP(state);
2693                 if (status < 0)
2694                         break;
2695                 status = InitCE(state);
2696                 if (status < 0)
2697                         break;
2698                 status = InitEQ(state);
2699                 if (status < 0)
2700                         break;
2701                 status = InitEC(state);
2702                 if (status < 0)
2703                         break;
2704                 status = InitSC(state);
2705                 if (status < 0)
2706                         break;
2707
2708                 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2709                 if (status < 0)
2710                         break;
2711                 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2712                 if (status < 0)
2713                         break;
2714
2715                 state->cscd_state = CSCD_INIT;
2716                 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2717                 if (status < 0)
2718                         break;
2719                 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2720                 if (status < 0)
2721                         break;
2722
2723                 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2724                                  (VERSION_MAJOR % 10)) << 24;
2725                 driverVersion += (((VERSION_MINOR / 10) << 4) +
2726                                   (VERSION_MINOR % 10)) << 16;
2727                 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2728                     ((VERSION_PATCH / 100) << 8) +
2729                     ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2730
2731                 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2732                 if (status < 0)
2733                         break;
2734
2735                 status = StopOC(state);
2736                 if (status < 0)
2737                         break;
2738
2739                 state->drxd_state = DRXD_STOPPED;
2740                 state->init_done = 1;
2741                 status = 0;
2742         } while (0);
2743         return status;
2744 }
2745
2746 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
2747 {
2748         DRX_GetLockStatus(state, pLockStatus);
2749
2750         /*if (*pLockStatus&DRX_LOCK_MPEG) */
2751         if (*pLockStatus & DRX_LOCK_FEC) {
2752                 ConfigureMPEGOutput(state, 1);
2753                 /* Get status again, in case we have MPEG lock now */
2754                 /*DRX_GetLockStatus(state, pLockStatus); */
2755         }
2756
2757         return 0;
2758 }
2759
2760 /****************************************************************************/
2761 /****************************************************************************/
2762 /****************************************************************************/
2763
2764 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2765 {
2766         struct drxd_state *state = fe->demodulator_priv;
2767         u32 value;
2768         int res;
2769
2770         res = ReadIFAgc(state, &value);
2771         if (res < 0)
2772                 *strength = 0;
2773         else
2774                 *strength = 0xffff - (value << 4);
2775         return 0;
2776 }
2777
2778 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status)
2779 {
2780         struct drxd_state *state = fe->demodulator_priv;
2781         u32 lock;
2782
2783         DRXD_status(state, &lock);
2784         *status = 0;
2785         /* No MPEG lock in V255 firmware, bug ? */
2786 #if 1
2787         if (lock & DRX_LOCK_MPEG)
2788                 *status |= FE_HAS_LOCK;
2789 #else
2790         if (lock & DRX_LOCK_FEC)
2791                 *status |= FE_HAS_LOCK;
2792 #endif
2793         if (lock & DRX_LOCK_FEC)
2794                 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2795         if (lock & DRX_LOCK_DEMOD)
2796                 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2797
2798         return 0;
2799 }
2800
2801 static int drxd_init(struct dvb_frontend *fe)
2802 {
2803         struct drxd_state *state = fe->demodulator_priv;
2804
2805         return DRXD_init(state, NULL, 0);
2806 }
2807
2808 static int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2809 {
2810         struct drxd_state *state = fe->demodulator_priv;
2811
2812         if (state->config.disable_i2c_gate_ctrl == 1)
2813                 return 0;
2814
2815         return DRX_ConfigureI2CBridge(state, onoff);
2816 }
2817
2818 static int drxd_get_tune_settings(struct dvb_frontend *fe,
2819                                   struct dvb_frontend_tune_settings *sets)
2820 {
2821         sets->min_delay_ms = 10000;
2822         sets->max_drift = 0;
2823         sets->step_size = 0;
2824         return 0;
2825 }
2826
2827 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2828 {
2829         *ber = 0;
2830         return 0;
2831 }
2832
2833 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2834 {
2835         *snr = 0;
2836         return 0;
2837 }
2838
2839 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2840 {
2841         *ucblocks = 0;
2842         return 0;
2843 }
2844
2845 static int drxd_sleep(struct dvb_frontend *fe)
2846 {
2847         struct drxd_state *state = fe->demodulator_priv;
2848
2849         ConfigureMPEGOutput(state, 0);
2850         return 0;
2851 }
2852
2853 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2854 {
2855         return drxd_config_i2c(fe, enable);
2856 }
2857
2858 static int drxd_set_frontend(struct dvb_frontend *fe)
2859 {
2860         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2861         struct drxd_state *state = fe->demodulator_priv;
2862         s32 off = 0;
2863
2864         state->props = *p;
2865         DRX_Stop(state);
2866
2867         if (fe->ops.tuner_ops.set_params) {
2868                 fe->ops.tuner_ops.set_params(fe);
2869                 if (fe->ops.i2c_gate_ctrl)
2870                         fe->ops.i2c_gate_ctrl(fe, 0);
2871         }
2872
2873         msleep(200);
2874
2875         return DRX_Start(state, off);
2876 }
2877
2878 static void drxd_release(struct dvb_frontend *fe)
2879 {
2880         struct drxd_state *state = fe->demodulator_priv;
2881
2882         kfree(state);
2883 }
2884
2885 static const struct dvb_frontend_ops drxd_ops = {
2886         .delsys = { SYS_DVBT},
2887         .info = {
2888                  .name = "Micronas DRXD DVB-T",
2889                  .frequency_min_hz =  47125 * kHz,
2890                  .frequency_max_hz = 855250 * kHz,
2891                  .frequency_stepsize_hz = 166667,
2892                  .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2893                  FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2894                  FE_CAN_FEC_AUTO |
2895                  FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2896                  FE_CAN_QAM_AUTO |
2897                  FE_CAN_TRANSMISSION_MODE_AUTO |
2898                  FE_CAN_GUARD_INTERVAL_AUTO |
2899                  FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2900
2901         .release = drxd_release,
2902         .init = drxd_init,
2903         .sleep = drxd_sleep,
2904         .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2905
2906         .set_frontend = drxd_set_frontend,
2907         .get_tune_settings = drxd_get_tune_settings,
2908
2909         .read_status = drxd_read_status,
2910         .read_ber = drxd_read_ber,
2911         .read_signal_strength = drxd_read_signal_strength,
2912         .read_snr = drxd_read_snr,
2913         .read_ucblocks = drxd_read_ucblocks,
2914 };
2915
2916 struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2917                                  void *priv, struct i2c_adapter *i2c,
2918                                  struct device *dev)
2919 {
2920         struct drxd_state *state = NULL;
2921
2922         state = kzalloc(sizeof(*state), GFP_KERNEL);
2923         if (!state)
2924                 return NULL;
2925
2926         state->ops = drxd_ops;
2927         state->dev = dev;
2928         state->config = *config;
2929         state->i2c = i2c;
2930         state->priv = priv;
2931
2932         mutex_init(&state->mutex);
2933
2934         if (Read16(state, 0, NULL, 0) < 0)
2935                 goto error;
2936
2937         state->frontend.ops = drxd_ops;
2938         state->frontend.demodulator_priv = state;
2939         ConfigureMPEGOutput(state, 0);
2940         /* add few initialization to allow gate control */
2941         CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2942         InitHI(state);
2943
2944         return &state->frontend;
2945
2946 error:
2947         printk(KERN_ERR "drxd: not found\n");
2948         kfree(state);
2949         return NULL;
2950 }
2951 EXPORT_SYMBOL(drxd_attach);
2952
2953 MODULE_DESCRIPTION("DRXD driver");
2954 MODULE_AUTHOR("Micronas");
2955 MODULE_LICENSE("GPL");