2 * Linux-DVB Driver for DiBcom's second generation DiB7000P (PC).
4 * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/i2c.h>
16 #include <linux/mutex.h>
17 #include <asm/div64.h>
19 #include <media/dvb_math.h>
20 #include <media/dvb_frontend.h>
25 module_param(debug, int, 0644);
26 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
28 static int buggy_sfn_workaround;
29 module_param(buggy_sfn_workaround, int, 0644);
30 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
32 #define dprintk(fmt, arg...) do { \
34 printk(KERN_DEBUG pr_fmt("%s: " fmt), \
39 struct i2c_adapter *i2c_adap;
43 struct dib7000p_state {
44 struct dvb_frontend demod;
45 struct dib7000p_config cfg;
48 struct i2c_adapter *i2c_adap;
50 struct dibx000_i2c_master i2c_master;
55 u32 current_bandwidth;
56 struct dibx000_agc_config *current_agc;
68 u8 sfn_workaround_active:1;
70 #define SOC7090 0x7090
74 struct i2c_adapter dib7090_tuner_adap;
76 /* for the I2C transfer */
77 struct i2c_msg msg[2];
78 u8 i2c_write_buffer[4];
79 u8 i2c_read_buffer[2];
80 struct mutex i2c_buffer_lock;
86 unsigned long per_jiffies_stats;
87 unsigned long ber_jiffies_stats;
88 unsigned long get_stats_time;
91 enum dib7000p_power_mode {
92 DIB7000P_POWER_ALL = 0,
93 DIB7000P_POWER_ANALOG_ADC,
94 DIB7000P_POWER_INTERFACE_ONLY,
97 /* dib7090 specific functions */
98 static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
99 static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
100 static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode);
101 static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode);
103 static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
107 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
108 dprintk("could not acquire lock\n");
112 state->i2c_write_buffer[0] = reg >> 8;
113 state->i2c_write_buffer[1] = reg & 0xff;
115 memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
116 state->msg[0].addr = state->i2c_addr >> 1;
117 state->msg[0].flags = 0;
118 state->msg[0].buf = state->i2c_write_buffer;
119 state->msg[0].len = 2;
120 state->msg[1].addr = state->i2c_addr >> 1;
121 state->msg[1].flags = I2C_M_RD;
122 state->msg[1].buf = state->i2c_read_buffer;
123 state->msg[1].len = 2;
125 if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
126 dprintk("i2c read error on %d\n", reg);
128 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
129 mutex_unlock(&state->i2c_buffer_lock);
133 static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
137 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
138 dprintk("could not acquire lock\n");
142 state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
143 state->i2c_write_buffer[1] = reg & 0xff;
144 state->i2c_write_buffer[2] = (val >> 8) & 0xff;
145 state->i2c_write_buffer[3] = val & 0xff;
147 memset(&state->msg[0], 0, sizeof(struct i2c_msg));
148 state->msg[0].addr = state->i2c_addr >> 1;
149 state->msg[0].flags = 0;
150 state->msg[0].buf = state->i2c_write_buffer;
151 state->msg[0].len = 4;
153 ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ?
155 mutex_unlock(&state->i2c_buffer_lock);
159 static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf)
168 dib7000p_write_word(state, r, *n++);
175 static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
178 u16 outreg, fifo_threshold, smo_mode;
181 fifo_threshold = 1792;
182 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
184 dprintk("setting output mode for demod %p to %d\n", &state->demod, mode);
187 case OUTMODE_MPEG2_PAR_GATED_CLK:
188 outreg = (1 << 10); /* 0x0400 */
190 case OUTMODE_MPEG2_PAR_CONT_CLK:
191 outreg = (1 << 10) | (1 << 6); /* 0x0440 */
193 case OUTMODE_MPEG2_SERIAL:
194 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */
196 case OUTMODE_DIVERSITY:
197 if (state->cfg.hostbus_diversity)
198 outreg = (1 << 10) | (4 << 6); /* 0x0500 */
202 case OUTMODE_MPEG2_FIFO:
203 smo_mode |= (3 << 1);
204 fifo_threshold = 512;
205 outreg = (1 << 10) | (5 << 6);
207 case OUTMODE_ANALOG_ADC:
208 outreg = (1 << 10) | (3 << 6);
214 dprintk("Unhandled output_mode passed to be set for demod %p\n", &state->demod);
218 if (state->cfg.output_mpeg2_in_188_bytes)
219 smo_mode |= (1 << 5);
221 ret |= dib7000p_write_word(state, 235, smo_mode);
222 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
223 if (state->version != SOC7090)
224 ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */
229 static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
231 struct dib7000p_state *state = demod->demodulator_priv;
233 if (state->div_force_off) {
234 dprintk("diversity combination deactivated - forced by COFDM parameters\n");
236 dib7000p_write_word(state, 207, 0);
238 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
240 state->div_state = (u8) onoff;
243 dib7000p_write_word(state, 204, 6);
244 dib7000p_write_word(state, 205, 16);
245 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
247 dib7000p_write_word(state, 204, 1);
248 dib7000p_write_word(state, 205, 0);
254 static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
256 /* by default everything is powered off */
257 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
259 /* now, depending on the requested mode, we power on */
261 /* power up everything in the demod */
262 case DIB7000P_POWER_ALL:
267 if (state->version == SOC7090)
273 case DIB7000P_POWER_ANALOG_ADC:
274 /* dem, cfg, iqc, sad, agc */
275 reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
277 reg_776 &= ~((1 << 0));
279 if (state->version != SOC7090)
280 reg_1280 &= ~((1 << 11));
281 reg_1280 &= ~(1 << 6);
283 case DIB7000P_POWER_INTERFACE_ONLY:
284 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
285 /* TODO power up either SDIO or I2C */
286 if (state->version == SOC7090)
287 reg_1280 &= ~((1 << 7) | (1 << 5));
289 reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
292 /* TODO following stuff is just converted from the dib7000-driver - check when is used what */
295 dib7000p_write_word(state, 774, reg_774);
296 dib7000p_write_word(state, 775, reg_775);
297 dib7000p_write_word(state, 776, reg_776);
298 dib7000p_write_word(state, 1280, reg_1280);
299 if (state->version != SOC7090)
300 dib7000p_write_word(state, 899, reg_899);
305 static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
307 u16 reg_908 = 0, reg_909 = 0;
310 if (state->version != SOC7090) {
311 reg_908 = dib7000p_read_word(state, 908);
312 reg_909 = dib7000p_read_word(state, 909);
316 case DIBX000_SLOW_ADC_ON:
317 if (state->version == SOC7090) {
318 reg = dib7000p_read_word(state, 1925);
320 dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2)); /* en_slowAdc = 1 & reset_sladc = 1 */
322 reg = dib7000p_read_word(state, 1925); /* read access to make it works... strange ... */
324 dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */
326 reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12));
327 dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524); /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */
329 reg_909 |= (1 << 1) | (1 << 0);
330 dib7000p_write_word(state, 909, reg_909);
331 reg_909 &= ~(1 << 1);
335 case DIBX000_SLOW_ADC_OFF:
336 if (state->version == SOC7090) {
337 reg = dib7000p_read_word(state, 1925);
338 dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */
340 reg_909 |= (1 << 1) | (1 << 0);
348 case DIBX000_ADC_OFF:
349 reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
350 reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
353 case DIBX000_VBG_ENABLE:
354 reg_908 &= ~(1 << 15);
357 case DIBX000_VBG_DISABLE:
358 reg_908 |= (1 << 15);
365 // dprintk( "908: %x, 909: %x\n", reg_908, reg_909);
367 reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4;
368 reg_908 |= (state->cfg.enable_current_mirror & 1) << 7;
370 if (state->version != SOC7090) {
371 dib7000p_write_word(state, 908, reg_908);
372 dib7000p_write_word(state, 909, reg_909);
376 static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
380 // store the current bandwidth for later use
381 state->current_bandwidth = bw;
383 if (state->timf == 0) {
384 dprintk("using default timf\n");
385 timf = state->cfg.bw->timf;
387 dprintk("using updated timf\n");
391 timf = timf * (bw / 50) / 160;
393 dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
394 dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff));
399 static int dib7000p_sad_calib(struct dib7000p_state *state)
402 dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
404 if (state->version == SOC7090)
405 dib7000p_write_word(state, 74, 2048);
407 dib7000p_write_word(state, 74, 776);
409 /* do the calibration */
410 dib7000p_write_word(state, 73, (1 << 0));
411 dib7000p_write_word(state, 73, (0 << 0));
418 static int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
420 struct dib7000p_state *state = demod->demodulator_priv;
423 state->wbd_ref = value;
424 return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value);
427 static int dib7000p_get_agc_values(struct dvb_frontend *fe,
428 u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd)
430 struct dib7000p_state *state = fe->demodulator_priv;
432 if (agc_global != NULL)
433 *agc_global = dib7000p_read_word(state, 394);
435 *agc1 = dib7000p_read_word(state, 392);
437 *agc2 = dib7000p_read_word(state, 393);
439 *wbd = dib7000p_read_word(state, 397);
444 static int dib7000p_set_agc1_min(struct dvb_frontend *fe, u16 v)
446 struct dib7000p_state *state = fe->demodulator_priv;
447 return dib7000p_write_word(state, 108, v);
450 static void dib7000p_reset_pll(struct dib7000p_state *state)
452 struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
455 if (state->version == SOC7090) {
456 dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
458 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
461 dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
463 /* force PLL bypass */
464 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
465 (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
467 dib7000p_write_word(state, 900, clk_cfg0);
470 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
471 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
472 dib7000p_write_word(state, 900, clk_cfg0);
475 dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));
476 dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));
477 dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));
478 dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));
480 dib7000p_write_word(state, 72, bw->sad_cfg);
483 static u32 dib7000p_get_internal_freq(struct dib7000p_state *state)
485 u32 internal = (u32) dib7000p_read_word(state, 18) << 16;
486 internal |= (u32) dib7000p_read_word(state, 19);
492 static int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
494 struct dib7000p_state *state = fe->demodulator_priv;
495 u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856);
499 /* get back old values */
500 prediv = reg_1856 & 0x3f;
501 loopdiv = (reg_1856 >> 6) & 0x3f;
503 if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
504 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
506 reg_1857 = dib7000p_read_word(state, 1857);
507 dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));
509 dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
511 /* write new system clk into P_sec_len */
512 internal = dib7000p_get_internal_freq(state);
513 xtal = (internal / loopdiv) * prediv;
514 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */
515 dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff));
516 dib7000p_write_word(state, 19, (u16) (internal & 0xffff));
518 dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));
520 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
521 dprintk("Waiting for PLL to lock\n");
528 static int dib7000p_reset_gpio(struct dib7000p_state *st)
530 /* reset the GPIOs */
531 dprintk("gpio dir: %x: val: %x, pwm_pos: %x\n", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos);
533 dib7000p_write_word(st, 1029, st->gpio_dir);
534 dib7000p_write_word(st, 1030, st->gpio_val);
536 /* TODO 1031 is P_gpio_od */
538 dib7000p_write_word(st, 1032, st->cfg.gpio_pwm_pos);
540 dib7000p_write_word(st, 1037, st->cfg.pwm_freq_div);
544 static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val)
546 st->gpio_dir = dib7000p_read_word(st, 1029);
547 st->gpio_dir &= ~(1 << num); /* reset the direction bit */
548 st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
549 dib7000p_write_word(st, 1029, st->gpio_dir);
551 st->gpio_val = dib7000p_read_word(st, 1030);
552 st->gpio_val &= ~(1 << num); /* reset the direction bit */
553 st->gpio_val |= (val & 0x01) << num; /* set the new value */
554 dib7000p_write_word(st, 1030, st->gpio_val);
559 static int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val)
561 struct dib7000p_state *state = demod->demodulator_priv;
562 return dib7000p_cfg_gpio(state, num, dir, val);
565 static u16 dib7000p_defaults[] = {
566 // auto search configuration
569 (1<<3)|(1<<11)|(1<<12)|(1<<13),
570 0x0814, /* Equal Lock */
589 /* set ADC level to -16 */
591 (1 << 13) - 825 - 117,
592 (1 << 13) - 837 - 117,
593 (1 << 13) - 811 - 117,
594 (1 << 13) - 766 - 117,
595 (1 << 13) - 737 - 117,
596 (1 << 13) - 693 - 117,
597 (1 << 13) - 648 - 117,
598 (1 << 13) - 619 - 117,
599 (1 << 13) - 575 - 117,
600 (1 << 13) - 531 - 117,
601 (1 << 13) - 501 - 117,
606 /* disable power smoothing */
648 static void dib7000p_reset_stats(struct dvb_frontend *fe);
650 static int dib7000p_demod_reset(struct dib7000p_state *state)
652 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
654 if (state->version == SOC7090)
655 dibx000_reset_i2c_master(&state->i2c_master);
657 dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE);
659 /* restart all parts */
660 dib7000p_write_word(state, 770, 0xffff);
661 dib7000p_write_word(state, 771, 0xffff);
662 dib7000p_write_word(state, 772, 0x001f);
663 dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
665 dib7000p_write_word(state, 770, 0);
666 dib7000p_write_word(state, 771, 0);
667 dib7000p_write_word(state, 772, 0);
668 dib7000p_write_word(state, 1280, 0);
670 if (state->version != SOC7090) {
671 dib7000p_write_word(state, 898, 0x0003);
672 dib7000p_write_word(state, 898, 0);
676 dib7000p_reset_pll(state);
678 if (dib7000p_reset_gpio(state) != 0)
679 dprintk("GPIO reset was not successful.\n");
681 if (state->version == SOC7090) {
682 dib7000p_write_word(state, 899, 0);
685 dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
686 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
687 dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
688 dib7000p_write_word(state, 273, (0<<6) | 30);
690 if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
691 dprintk("OUTPUT_MODE could not be reset.\n");
693 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
694 dib7000p_sad_calib(state);
695 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
697 /* unforce divstr regardless whether i2c enumeration was done or not */
698 dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1));
700 dib7000p_set_bandwidth(state, 8000);
702 if (state->version == SOC7090) {
703 dib7000p_write_word(state, 36, 0x0755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
705 if (state->cfg.tuner_is_baseband)
706 dib7000p_write_word(state, 36, 0x0755);
708 dib7000p_write_word(state, 36, 0x1f55);
711 dib7000p_write_tab(state, dib7000p_defaults);
712 if (state->version != SOC7090) {
713 dib7000p_write_word(state, 901, 0x0006);
714 dib7000p_write_word(state, 902, (3 << 10) | (1 << 6));
715 dib7000p_write_word(state, 905, 0x2c8e);
718 dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
723 static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
726 tmp = dib7000p_read_word(state, 903);
727 dib7000p_write_word(state, 903, (tmp | 0x1));
728 tmp = dib7000p_read_word(state, 900);
729 dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));
732 static void dib7000p_restart_agc(struct dib7000p_state *state)
734 // P_restart_iqc & P_restart_agc
735 dib7000p_write_word(state, 770, (1 << 11) | (1 << 9));
736 dib7000p_write_word(state, 770, 0x0000);
739 static int dib7000p_update_lna(struct dib7000p_state *state)
743 if (state->cfg.update_lna) {
744 dyn_gain = dib7000p_read_word(state, 394);
745 if (state->cfg.update_lna(&state->demod, dyn_gain)) {
746 dib7000p_restart_agc(state);
754 static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
756 struct dibx000_agc_config *agc = NULL;
758 if (state->current_band == band && state->current_agc != NULL)
760 state->current_band = band;
762 for (i = 0; i < state->cfg.agc_config_count; i++)
763 if (state->cfg.agc[i].band_caps & band) {
764 agc = &state->cfg.agc[i];
769 dprintk("no valid AGC configuration found for band 0x%02x\n", band);
773 state->current_agc = agc;
776 dib7000p_write_word(state, 75, agc->setup);
777 dib7000p_write_word(state, 76, agc->inv_gain);
778 dib7000p_write_word(state, 77, agc->time_stabiliz);
779 dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
781 // Demod AGC loop configuration
782 dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
783 dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
786 dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d\n",
787 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
789 if (state->wbd_ref != 0)
790 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref);
792 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref);
794 dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
796 dib7000p_write_word(state, 107, agc->agc1_max);
797 dib7000p_write_word(state, 108, agc->agc1_min);
798 dib7000p_write_word(state, 109, agc->agc2_max);
799 dib7000p_write_word(state, 110, agc->agc2_min);
800 dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
801 dib7000p_write_word(state, 112, agc->agc1_pt3);
802 dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
803 dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
804 dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
808 static int dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
810 u32 internal = dib7000p_get_internal_freq(state);
811 s32 unit_khz_dds_val;
812 u32 abs_offset_khz = abs(offset_khz);
813 u32 dds = state->cfg.bw->ifreq & 0x1ffffff;
814 u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));
816 pr_warn("DIB7000P: dib7000p_get_internal_freq returned 0\n");
819 /* 2**26 / Fsampling is the unit 1KHz offset */
820 unit_khz_dds_val = 67108864 / (internal);
822 dprintk("setting a frequency offset of %dkHz internal freq = %d invert = %d\n", offset_khz, internal, invert);
825 unit_khz_dds_val *= -1;
829 dds -= (abs_offset_khz * unit_khz_dds_val); /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */
831 dds += (abs_offset_khz * unit_khz_dds_val);
833 if (abs_offset_khz <= (internal / 2)) { /* Max dds offset is the half of the demod freq */
834 dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9)));
835 dib7000p_write_word(state, 22, (u16) (dds & 0xffff));
840 static int dib7000p_agc_startup(struct dvb_frontend *demod)
842 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
843 struct dib7000p_state *state = demod->demodulator_priv;
845 u8 *agc_state = &state->agc_state;
848 u32 upd_demod_gain_period = 0x1000;
849 s32 frequency_offset = 0;
851 switch (state->agc_state) {
853 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
854 if (state->version == SOC7090) {
855 reg = dib7000p_read_word(state, 0x79b) & 0xff00;
856 dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF); /* lsb */
857 dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));
859 /* enable adc i & q */
860 reg = dib7000p_read_word(state, 0x780);
861 dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7)));
863 dib7000p_set_adc_state(state, DIBX000_ADC_ON);
864 dib7000p_pll_clk_cfg(state);
867 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0)
870 if (demod->ops.tuner_ops.get_frequency) {
873 demod->ops.tuner_ops.get_frequency(demod, &frequency_tuner);
874 frequency_offset = (s32)frequency_tuner / 1000 - ch->frequency / 1000;
877 if (dib7000p_set_dds(state, frequency_offset) < 0)
885 if (state->cfg.agc_control)
886 state->cfg.agc_control(&state->demod, 1);
888 dib7000p_write_word(state, 78, 32768);
889 if (!state->current_agc->perform_agc_softsplit) {
890 /* we are using the wbd - so slow AGC startup */
891 /* force 0 split on WBD and restart AGC */
892 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
896 /* default AGC startup */
898 /* wait AGC rough lock time */
902 dib7000p_restart_agc(state);
905 case 2: /* fast split search path after 5sec */
906 dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */
907 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */
912 case 3: /* split search ended */
913 agc_split = (u8) dib7000p_read_word(state, 396); /* store the split value for the next time */
914 dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
916 dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */
917 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
919 dib7000p_restart_agc(state);
921 dprintk("SPLIT %p: %hd\n", demod, agc_split);
927 case 4: /* LNA startup */
930 if (dib7000p_update_lna(state))
937 if (state->cfg.agc_control)
938 state->cfg.agc_control(&state->demod, 0);
947 static void dib7000p_update_timf(struct dib7000p_state *state)
949 u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428);
950 state->timf = timf * 160 / (state->current_bandwidth / 50);
951 dib7000p_write_word(state, 23, (u16) (timf >> 16));
952 dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
953 dprintk("updated timf_frequency: %d (default: %d)\n", state->timf, state->cfg.bw->timf);
957 static u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
959 struct dib7000p_state *state = fe->demodulator_priv;
964 case DEMOD_TIMF_UPDATE:
965 dib7000p_update_timf(state);
970 dib7000p_set_bandwidth(state, state->current_bandwidth);
974 static void dib7000p_set_channel(struct dib7000p_state *state,
975 struct dtv_frontend_properties *ch, u8 seq)
979 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
981 /* nfft, guard, qam, alpha */
983 switch (ch->transmission_mode) {
984 case TRANSMISSION_MODE_2K:
987 case TRANSMISSION_MODE_4K:
991 case TRANSMISSION_MODE_8K:
995 switch (ch->guard_interval) {
996 case GUARD_INTERVAL_1_32:
999 case GUARD_INTERVAL_1_16:
1002 case GUARD_INTERVAL_1_4:
1006 case GUARD_INTERVAL_1_8:
1010 switch (ch->modulation) {
1022 switch (HIERARCHY_1) {
1034 dib7000p_write_word(state, 0, value);
1035 dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */
1037 /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
1041 if (ch->hierarchy == 1)
1045 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
1063 dib7000p_write_word(state, 208, value);
1065 /* offset loop parameters */
1066 dib7000p_write_word(state, 26, 0x6680);
1067 dib7000p_write_word(state, 32, 0x0003);
1068 dib7000p_write_word(state, 29, 0x1273);
1069 dib7000p_write_word(state, 33, 0x0005);
1071 /* P_dvsy_sync_wait */
1072 switch (ch->transmission_mode) {
1073 case TRANSMISSION_MODE_8K:
1076 case TRANSMISSION_MODE_4K:
1079 case TRANSMISSION_MODE_2K:
1084 switch (ch->guard_interval) {
1085 case GUARD_INTERVAL_1_16:
1088 case GUARD_INTERVAL_1_8:
1091 case GUARD_INTERVAL_1_4:
1095 case GUARD_INTERVAL_1_32:
1099 if (state->cfg.diversity_delay == 0)
1100 state->div_sync_wait = (value * 3) / 2 + 48;
1102 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
1104 /* deactivate the possibility of diversity reception if extended interleaver */
1105 state->div_force_off = !1 && ch->transmission_mode != TRANSMISSION_MODE_8K;
1106 dib7000p_set_diversity_in(&state->demod, state->div_state);
1108 /* channel estimation fine configuration */
1109 switch (ch->modulation) {
1111 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
1112 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
1113 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
1114 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
1117 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
1118 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
1119 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
1120 est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
1123 est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
1124 est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
1125 est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
1126 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
1129 for (value = 0; value < 4; value++)
1130 dib7000p_write_word(state, 187 + value, est[value]);
1133 static int dib7000p_autosearch_start(struct dvb_frontend *demod)
1135 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
1136 struct dib7000p_state *state = demod->demodulator_priv;
1137 struct dtv_frontend_properties schan;
1139 u32 internal = dib7000p_get_internal_freq(state);
1142 schan.modulation = QAM_64;
1143 schan.guard_interval = GUARD_INTERVAL_1_32;
1144 schan.transmission_mode = TRANSMISSION_MODE_8K;
1145 schan.code_rate_HP = FEC_2_3;
1146 schan.code_rate_LP = FEC_3_4;
1147 schan.hierarchy = 0;
1149 dib7000p_set_channel(state, &schan, 7);
1151 factor = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
1152 if (factor >= 5000) {
1153 if (state->version == SOC7090)
1160 value = 30 * internal * factor;
1161 dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));
1162 dib7000p_write_word(state, 7, (u16) (value & 0xffff));
1163 value = 100 * internal * factor;
1164 dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));
1165 dib7000p_write_word(state, 9, (u16) (value & 0xffff));
1166 value = 500 * internal * factor;
1167 dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));
1168 dib7000p_write_word(state, 11, (u16) (value & 0xffff));
1170 value = dib7000p_read_word(state, 0);
1171 dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
1172 dib7000p_read_word(state, 1284);
1173 dib7000p_write_word(state, 0, (u16) value);
1178 static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
1180 struct dib7000p_state *state = demod->demodulator_priv;
1181 u16 irq_pending = dib7000p_read_word(state, 1284);
1183 if (irq_pending & 0x1)
1186 if (irq_pending & 0x2)
1192 static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
1194 static s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 };
1195 static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
1196 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
1197 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
1198 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
1199 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
1200 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
1201 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
1202 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
1203 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
1204 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
1205 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
1206 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
1207 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
1208 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
1209 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
1210 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
1211 255, 255, 255, 255, 255, 255
1214 u32 xtal = state->cfg.bw->xtal_hz / 1000;
1215 int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz;
1217 int coef_re[8], coef_im[8];
1221 dprintk("relative position of the Spur: %dk (RF: %dk, XTAL: %dk)\n", f_rel, rf_khz, xtal);
1223 if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2)
1228 dib7000p_write_word(state, 142, 0x0610);
1230 for (k = 0; k < 8; k++) {
1231 pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff;
1236 } else if (pha < 256) {
1237 coef_re[k] = sine[256 - (pha & 0xff)];
1238 coef_im[k] = sine[pha & 0xff];
1239 } else if (pha == 256) {
1242 } else if (pha < 512) {
1243 coef_re[k] = -sine[pha & 0xff];
1244 coef_im[k] = sine[256 - (pha & 0xff)];
1245 } else if (pha == 512) {
1248 } else if (pha < 768) {
1249 coef_re[k] = -sine[256 - (pha & 0xff)];
1250 coef_im[k] = -sine[pha & 0xff];
1251 } else if (pha == 768) {
1255 coef_re[k] = sine[pha & 0xff];
1256 coef_im[k] = -sine[256 - (pha & 0xff)];
1259 coef_re[k] *= notch[k];
1260 coef_re[k] += (1 << 14);
1261 if (coef_re[k] >= (1 << 24))
1262 coef_re[k] = (1 << 24) - 1;
1263 coef_re[k] /= (1 << 15);
1265 coef_im[k] *= notch[k];
1266 coef_im[k] += (1 << 14);
1267 if (coef_im[k] >= (1 << 24))
1268 coef_im[k] = (1 << 24) - 1;
1269 coef_im[k] /= (1 << 15);
1271 dprintk("PALF COEF: %d re: %d im: %d\n", k, coef_re[k], coef_im[k]);
1273 dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
1274 dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
1275 dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
1277 dib7000p_write_word(state, 143, 0);
1280 static int dib7000p_tune(struct dvb_frontend *demod)
1282 struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
1283 struct dib7000p_state *state = demod->demodulator_priv;
1287 dib7000p_set_channel(state, ch, 0);
1292 dib7000p_write_word(state, 770, 0x4000);
1293 dib7000p_write_word(state, 770, 0x0000);
1296 /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
1297 tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3);
1298 if (state->sfn_workaround_active) {
1299 dprintk("SFN workaround is active\n");
1301 dib7000p_write_word(state, 166, 0x4000);
1303 dib7000p_write_word(state, 166, 0x0000);
1305 dib7000p_write_word(state, 29, tmp);
1307 // never achieved a lock with that bandwidth so far - wait for osc-freq to update
1308 if (state->timf == 0)
1311 /* offset loop parameters */
1313 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
1314 tmp = (6 << 8) | 0x80;
1315 switch (ch->transmission_mode) {
1316 case TRANSMISSION_MODE_2K:
1319 case TRANSMISSION_MODE_4K:
1323 case TRANSMISSION_MODE_8K:
1327 dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */
1329 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
1331 switch (ch->transmission_mode) {
1332 case TRANSMISSION_MODE_2K:
1335 case TRANSMISSION_MODE_4K:
1339 case TRANSMISSION_MODE_8K:
1343 dib7000p_write_word(state, 32, tmp);
1345 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
1347 switch (ch->transmission_mode) {
1348 case TRANSMISSION_MODE_2K:
1351 case TRANSMISSION_MODE_4K:
1355 case TRANSMISSION_MODE_8K:
1359 dib7000p_write_word(state, 33, tmp);
1361 tmp = dib7000p_read_word(state, 509);
1362 if (!((tmp >> 6) & 0x1)) {
1363 /* restart the fec */
1364 tmp = dib7000p_read_word(state, 771);
1365 dib7000p_write_word(state, 771, tmp | (1 << 1));
1366 dib7000p_write_word(state, 771, tmp);
1368 tmp = dib7000p_read_word(state, 509);
1370 // we achieved a lock - it's time to update the osc freq
1371 if ((tmp >> 6) & 0x1) {
1372 dib7000p_update_timf(state);
1373 /* P_timf_alpha += 2 */
1374 tmp = dib7000p_read_word(state, 26);
1375 dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12));
1378 if (state->cfg.spur_protect)
1379 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1381 dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1383 dib7000p_reset_stats(demod);
1388 static int dib7000p_wakeup(struct dvb_frontend *demod)
1390 struct dib7000p_state *state = demod->demodulator_priv;
1391 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
1392 dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
1393 if (state->version == SOC7090)
1394 dib7000p_sad_calib(state);
1398 static int dib7000p_sleep(struct dvb_frontend *demod)
1400 struct dib7000p_state *state = demod->demodulator_priv;
1401 if (state->version == SOC7090)
1402 return dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1403 return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1406 static int dib7000p_identify(struct dib7000p_state *st)
1409 dprintk("checking demod on I2C address: %d (%x)\n", st->i2c_addr, st->i2c_addr);
1411 if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
1412 dprintk("wrong Vendor ID (read=0x%x)\n", value);
1416 if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
1417 dprintk("wrong Device ID (%x)\n", value);
1424 static int dib7000p_get_frontend(struct dvb_frontend *fe,
1425 struct dtv_frontend_properties *fep)
1427 struct dib7000p_state *state = fe->demodulator_priv;
1428 u16 tps = dib7000p_read_word(state, 463);
1430 fep->inversion = INVERSION_AUTO;
1432 fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
1434 switch ((tps >> 8) & 0x3) {
1436 fep->transmission_mode = TRANSMISSION_MODE_2K;
1439 fep->transmission_mode = TRANSMISSION_MODE_8K;
1441 /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
1444 switch (tps & 0x3) {
1446 fep->guard_interval = GUARD_INTERVAL_1_32;
1449 fep->guard_interval = GUARD_INTERVAL_1_16;
1452 fep->guard_interval = GUARD_INTERVAL_1_8;
1455 fep->guard_interval = GUARD_INTERVAL_1_4;
1459 switch ((tps >> 14) & 0x3) {
1461 fep->modulation = QPSK;
1464 fep->modulation = QAM_16;
1468 fep->modulation = QAM_64;
1472 /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
1473 /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
1475 fep->hierarchy = HIERARCHY_NONE;
1476 switch ((tps >> 5) & 0x7) {
1478 fep->code_rate_HP = FEC_1_2;
1481 fep->code_rate_HP = FEC_2_3;
1484 fep->code_rate_HP = FEC_3_4;
1487 fep->code_rate_HP = FEC_5_6;
1491 fep->code_rate_HP = FEC_7_8;
1496 switch ((tps >> 2) & 0x7) {
1498 fep->code_rate_LP = FEC_1_2;
1501 fep->code_rate_LP = FEC_2_3;
1504 fep->code_rate_LP = FEC_3_4;
1507 fep->code_rate_LP = FEC_5_6;
1511 fep->code_rate_LP = FEC_7_8;
1515 /* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */
1520 static int dib7000p_set_frontend(struct dvb_frontend *fe)
1522 struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1523 struct dib7000p_state *state = fe->demodulator_priv;
1526 if (state->version == SOC7090)
1527 dib7090_set_diversity_in(fe, 0);
1529 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
1531 /* maybe the parameter has been changed */
1532 state->sfn_workaround_active = buggy_sfn_workaround;
1534 if (fe->ops.tuner_ops.set_params)
1535 fe->ops.tuner_ops.set_params(fe);
1537 /* start up the AGC */
1538 state->agc_state = 0;
1540 time = dib7000p_agc_startup(fe);
1543 } while (time != -1);
1545 if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
1546 fep->guard_interval == GUARD_INTERVAL_AUTO || fep->modulation == QAM_AUTO || fep->code_rate_HP == FEC_AUTO) {
1549 dib7000p_autosearch_start(fe);
1552 found = dib7000p_autosearch_is_irq(fe);
1553 } while (found == 0 && i--);
1555 dprintk("autosearch returns: %d\n", found);
1556 if (found == 0 || found == 1)
1559 dib7000p_get_frontend(fe, fep);
1562 ret = dib7000p_tune(fe);
1564 /* make this a config parameter */
1565 if (state->version == SOC7090) {
1566 dib7090_set_output_mode(fe, state->cfg.output_mode);
1567 if (state->cfg.enMpegOutput == 0) {
1568 dib7090_setDibTxMux(state, MPEG_ON_DIBTX);
1569 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1572 dib7000p_set_output_mode(state, state->cfg.output_mode);
1577 static int dib7000p_get_stats(struct dvb_frontend *fe, enum fe_status stat);
1579 static int dib7000p_read_status(struct dvb_frontend *fe, enum fe_status *stat)
1581 struct dib7000p_state *state = fe->demodulator_priv;
1582 u16 lock = dib7000p_read_word(state, 509);
1587 *stat |= FE_HAS_SIGNAL;
1589 *stat |= FE_HAS_CARRIER;
1591 *stat |= FE_HAS_VITERBI;
1593 *stat |= FE_HAS_SYNC;
1594 if ((lock & 0x0038) == 0x38)
1595 *stat |= FE_HAS_LOCK;
1597 dib7000p_get_stats(fe, *stat);
1602 static int dib7000p_read_ber(struct dvb_frontend *fe, u32 * ber)
1604 struct dib7000p_state *state = fe->demodulator_priv;
1605 *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501);
1609 static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
1611 struct dib7000p_state *state = fe->demodulator_priv;
1612 *unc = dib7000p_read_word(state, 506);
1616 static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
1618 struct dib7000p_state *state = fe->demodulator_priv;
1619 u16 val = dib7000p_read_word(state, 394);
1620 *strength = 65535 - val;
1624 static u32 dib7000p_get_snr(struct dvb_frontend *fe)
1626 struct dib7000p_state *state = fe->demodulator_priv;
1628 s32 signal_mant, signal_exp, noise_mant, noise_exp;
1631 val = dib7000p_read_word(state, 479);
1632 noise_mant = (val >> 4) & 0xff;
1633 noise_exp = ((val & 0xf) << 2);
1634 val = dib7000p_read_word(state, 480);
1635 noise_exp += ((val >> 14) & 0x3);
1636 if ((noise_exp & 0x20) != 0)
1639 signal_mant = (val >> 6) & 0xFF;
1640 signal_exp = (val & 0x3F);
1641 if ((signal_exp & 0x20) != 0)
1644 if (signal_mant != 0)
1645 result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
1647 result = intlog10(2) * 10 * signal_exp - 100;
1649 if (noise_mant != 0)
1650 result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
1652 result -= intlog10(2) * 10 * noise_exp - 100;
1657 static int dib7000p_read_snr(struct dvb_frontend *fe, u16 *snr)
1661 result = dib7000p_get_snr(fe);
1663 *snr = result / ((1 << 24) / 10);
1667 static void dib7000p_reset_stats(struct dvb_frontend *demod)
1669 struct dib7000p_state *state = demod->demodulator_priv;
1670 struct dtv_frontend_properties *c = &demod->dtv_property_cache;
1673 memset(&c->strength, 0, sizeof(c->strength));
1674 memset(&c->cnr, 0, sizeof(c->cnr));
1675 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
1676 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
1677 memset(&c->block_error, 0, sizeof(c->block_error));
1679 c->strength.len = 1;
1681 c->block_error.len = 1;
1682 c->block_count.len = 1;
1683 c->post_bit_error.len = 1;
1684 c->post_bit_count.len = 1;
1686 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
1687 c->strength.stat[0].uvalue = 0;
1689 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1690 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1691 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1692 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1693 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1695 dib7000p_read_unc_blocks(demod, &ucb);
1697 state->old_ucb = ucb;
1698 state->ber_jiffies_stats = 0;
1699 state->per_jiffies_stats = 0;
1702 struct linear_segments {
1708 * Table to estimate signal strength in dBm.
1709 * This table should be empirically determinated by measuring the signal
1710 * strength generated by a RF generator directly connected into
1712 * This table was determinated by measuring the signal strength generated
1713 * by a DTA-2111 RF generator directly connected into a dib7000p device
1714 * (a Hauppauge Nova-TD stick), using a good quality 3 meters length
1715 * RC6 cable and good RC6 connectors, connected directly to antenna 1.
1716 * As the minimum output power of DTA-2111 is -31dBm, a 16 dBm attenuator
1717 * were used, for the lower power values.
1718 * The real value can actually be on other devices, or even at the
1719 * second antena input, depending on several factors, like if LNA
1720 * is enabled or not, if diversity is enabled, type of connectors, etc.
1721 * Yet, it is better to use this measure in dB than a random non-linear
1722 * percentage value, especially for antenna adjustments.
1723 * On my tests, the precision of the measure using this table is about
1724 * 0.5 dB, with sounds reasonable enough to adjust antennas.
1726 #define DB_OFFSET 131000
1728 static struct linear_segments strength_to_db_table[] = {
1729 { 63630, DB_OFFSET - 20500},
1730 { 62273, DB_OFFSET - 21000},
1731 { 60162, DB_OFFSET - 22000},
1732 { 58730, DB_OFFSET - 23000},
1733 { 58294, DB_OFFSET - 24000},
1734 { 57778, DB_OFFSET - 25000},
1735 { 57320, DB_OFFSET - 26000},
1736 { 56779, DB_OFFSET - 27000},
1737 { 56293, DB_OFFSET - 28000},
1738 { 55724, DB_OFFSET - 29000},
1739 { 55145, DB_OFFSET - 30000},
1740 { 54680, DB_OFFSET - 31000},
1741 { 54293, DB_OFFSET - 32000},
1742 { 53813, DB_OFFSET - 33000},
1743 { 53427, DB_OFFSET - 34000},
1744 { 52981, DB_OFFSET - 35000},
1746 { 52636, DB_OFFSET - 36000},
1747 { 52014, DB_OFFSET - 37000},
1748 { 51674, DB_OFFSET - 38000},
1749 { 50692, DB_OFFSET - 39000},
1750 { 49824, DB_OFFSET - 40000},
1751 { 49052, DB_OFFSET - 41000},
1752 { 48436, DB_OFFSET - 42000},
1753 { 47836, DB_OFFSET - 43000},
1754 { 47368, DB_OFFSET - 44000},
1755 { 46468, DB_OFFSET - 45000},
1756 { 45597, DB_OFFSET - 46000},
1757 { 44586, DB_OFFSET - 47000},
1758 { 43667, DB_OFFSET - 48000},
1759 { 42673, DB_OFFSET - 49000},
1760 { 41816, DB_OFFSET - 50000},
1761 { 40876, DB_OFFSET - 51000},
1765 static u32 interpolate_value(u32 value, struct linear_segments *segments,
1773 if (value >= segments[0].x)
1774 return segments[0].y;
1775 if (value < segments[len-1].x)
1776 return segments[len-1].y;
1778 for (i = 1; i < len - 1; i++) {
1779 /* If value is identical, no need to interpolate */
1780 if (value == segments[i].x)
1781 return segments[i].y;
1782 if (value > segments[i].x)
1786 /* Linear interpolation between the two (x,y) points */
1787 dy = segments[i - 1].y - segments[i].y;
1788 dx = segments[i - 1].x - segments[i].x;
1790 tmp64 = value - segments[i].x;
1793 ret = segments[i].y + tmp64;
1798 /* FIXME: may require changes - this one was borrowed from dib8000 */
1799 static u32 dib7000p_get_time_us(struct dvb_frontend *demod)
1801 struct dtv_frontend_properties *c = &demod->dtv_property_cache;
1804 int guard, rate_num, rate_denum = 1, bits_per_symbol;
1805 int interleaving = 0, fft_div;
1807 switch (c->guard_interval) {
1808 case GUARD_INTERVAL_1_4:
1811 case GUARD_INTERVAL_1_8:
1814 case GUARD_INTERVAL_1_16:
1818 case GUARD_INTERVAL_1_32:
1823 switch (c->transmission_mode) {
1824 case TRANSMISSION_MODE_2K:
1827 case TRANSMISSION_MODE_4K:
1831 case TRANSMISSION_MODE_8K:
1836 switch (c->modulation) {
1839 bits_per_symbol = 2;
1842 bits_per_symbol = 4;
1846 bits_per_symbol = 6;
1850 switch ((c->hierarchy == 0 || 1 == 1) ? c->code_rate_HP : c->code_rate_LP) {
1874 denom = bits_per_symbol * rate_num * fft_div * 384;
1877 * FIXME: check if the math makes sense. If so, fill the
1881 /* If calculus gets wrong, wait for 1s for the next stats */
1885 /* Estimate the period for the total bit rate */
1886 time_us = rate_denum * (1008 * 1562500L);
1888 do_div(tmp64, guard);
1889 time_us = time_us + tmp64;
1890 time_us += denom / 2;
1891 do_div(time_us, denom);
1893 tmp = 1008 * 96 * interleaving;
1894 time_us += tmp + tmp / guard;
1899 static int dib7000p_get_stats(struct dvb_frontend *demod, enum fe_status stat)
1901 struct dib7000p_state *state = demod->demodulator_priv;
1902 struct dtv_frontend_properties *c = &demod->dtv_property_cache;
1903 int show_per_stats = 0;
1904 u32 time_us = 0, val, snr;
1909 /* Get Signal strength */
1910 dib7000p_read_signal_strength(demod, &strength);
1912 db = interpolate_value(val,
1913 strength_to_db_table,
1914 ARRAY_SIZE(strength_to_db_table)) - DB_OFFSET;
1915 c->strength.stat[0].svalue = db;
1917 /* UCB/BER/CNR measures require lock */
1918 if (!(stat & FE_HAS_LOCK)) {
1920 c->block_count.len = 1;
1921 c->block_error.len = 1;
1922 c->post_bit_error.len = 1;
1923 c->post_bit_count.len = 1;
1924 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1925 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1926 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1927 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1928 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1932 /* Check if time for stats was elapsed */
1933 if (time_after(jiffies, state->per_jiffies_stats)) {
1934 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
1937 snr = dib7000p_get_snr(demod);
1939 snr = (1000L * snr) >> 24;
1942 c->cnr.stat[0].svalue = snr;
1943 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1945 /* Get UCB measures */
1946 dib7000p_read_unc_blocks(demod, &val);
1947 ucb = val - state->old_ucb;
1948 if (val < state->old_ucb)
1949 ucb += 0x100000000LL;
1951 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1952 c->block_error.stat[0].uvalue = ucb;
1954 /* Estimate the number of packets based on bitrate */
1956 time_us = dib7000p_get_time_us(demod);
1959 blocks = 1250000ULL * 1000000ULL;
1960 do_div(blocks, time_us * 8 * 204);
1961 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1962 c->block_count.stat[0].uvalue += blocks;
1968 /* Get post-BER measures */
1969 if (time_after(jiffies, state->ber_jiffies_stats)) {
1970 time_us = dib7000p_get_time_us(demod);
1971 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
1973 dprintk("Next all layers stats available in %u us.\n", time_us);
1975 dib7000p_read_ber(demod, &val);
1976 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1977 c->post_bit_error.stat[0].uvalue += val;
1979 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1980 c->post_bit_count.stat[0].uvalue += 100000000;
1983 /* Get PER measures */
1984 if (show_per_stats) {
1985 dib7000p_read_unc_blocks(demod, &val);
1987 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1988 c->block_error.stat[0].uvalue += val;
1990 time_us = dib7000p_get_time_us(demod);
1992 blocks = 1250000ULL * 1000000ULL;
1993 do_div(blocks, time_us * 8 * 204);
1994 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1995 c->block_count.stat[0].uvalue += blocks;
2001 static int dib7000p_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
2003 tune->min_delay_ms = 1000;
2007 static void dib7000p_release(struct dvb_frontend *demod)
2009 struct dib7000p_state *st = demod->demodulator_priv;
2010 dibx000_exit_i2c_master(&st->i2c_master);
2011 i2c_del_adapter(&st->dib7090_tuner_adap);
2015 static int dib7000pc_detection(struct i2c_adapter *i2c_adap)
2018 struct i2c_msg msg[2] = {
2019 {.addr = 18 >> 1, .flags = 0, .len = 2},
2020 {.addr = 18 >> 1, .flags = I2C_M_RD, .len = 2},
2024 tx = kzalloc(2, GFP_KERNEL);
2027 rx = kzalloc(2, GFP_KERNEL);
2030 goto rx_memory_error;
2039 if (i2c_transfer(i2c_adap, msg, 2) == 2)
2040 if (rx[0] == 0x01 && rx[1] == 0xb3) {
2041 dprintk("-D- DiB7000PC detected\n");
2045 msg[0].addr = msg[1].addr = 0x40;
2047 if (i2c_transfer(i2c_adap, msg, 2) == 2)
2048 if (rx[0] == 0x01 && rx[1] == 0xb3) {
2049 dprintk("-D- DiB7000PC detected\n");
2053 dprintk("-D- DiB7000PC not detected\n");
2061 static struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
2063 struct dib7000p_state *st = demod->demodulator_priv;
2064 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
2067 static int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
2069 struct dib7000p_state *state = fe->demodulator_priv;
2070 u16 val = dib7000p_read_word(state, 235) & 0xffef;
2071 val |= (onoff & 0x1) << 4;
2072 dprintk("PID filter enabled %d\n", onoff);
2073 return dib7000p_write_word(state, 235, val);
2076 static int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
2078 struct dib7000p_state *state = fe->demodulator_priv;
2079 dprintk("PID filter: index %x, PID %d, OnOff %d\n", id, pid, onoff);
2080 return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
2083 static int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
2085 struct dib7000p_state *dpst;
2089 dpst = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
2093 dpst->i2c_adap = i2c;
2094 mutex_init(&dpst->i2c_buffer_lock);
2096 for (k = no_of_demods - 1; k >= 0; k--) {
2099 /* designated i2c address */
2100 if (cfg[k].default_i2c_addr != 0)
2101 new_addr = cfg[k].default_i2c_addr + (k << 1);
2103 new_addr = (0x40 + k) << 1;
2104 dpst->i2c_addr = new_addr;
2105 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
2106 if (dib7000p_identify(dpst) != 0) {
2107 dpst->i2c_addr = default_addr;
2108 dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
2109 if (dib7000p_identify(dpst) != 0) {
2110 dprintk("DiB7000P #%d: not identified\n", k);
2116 /* start diversity to pull_down div_str - just for i2c-enumeration */
2117 dib7000p_set_output_mode(dpst, OUTMODE_DIVERSITY);
2119 /* set new i2c address and force divstart */
2120 dib7000p_write_word(dpst, 1285, (new_addr << 2) | 0x2);
2122 dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
2125 for (k = 0; k < no_of_demods; k++) {
2127 if (cfg[k].default_i2c_addr != 0)
2128 dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
2130 dpst->i2c_addr = (0x40 + k) << 1;
2133 dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2);
2135 /* deactivate div - it was just for i2c-enumeration */
2136 dib7000p_set_output_mode(dpst, OUTMODE_HIGH_Z);
2143 static const s32 lut_1000ln_mant[] = {
2144 6908, 6956, 7003, 7047, 7090, 7131, 7170, 7208, 7244, 7279, 7313, 7346, 7377, 7408, 7438, 7467, 7495, 7523, 7549, 7575, 7600
2147 static s32 dib7000p_get_adc_power(struct dvb_frontend *fe)
2149 struct dib7000p_state *state = fe->demodulator_priv;
2150 u32 tmp_val = 0, exp = 0, mant = 0;
2155 buf[0] = dib7000p_read_word(state, 0x184);
2156 buf[1] = dib7000p_read_word(state, 0x185);
2157 pow_i = (buf[0] << 16) | buf[1];
2158 dprintk("raw pow_i = %d\n", pow_i);
2161 while (tmp_val >>= 1)
2164 mant = (pow_i * 1000 / (1 << exp));
2165 dprintk(" mant = %d exp = %d\n", mant / 1000, exp);
2167 ix = (u8) ((mant - 1000) / 100); /* index of the LUT */
2168 dprintk(" ix = %d\n", ix);
2170 pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908);
2171 pow_i = (pow_i << 8) / 1000;
2172 dprintk(" pow_i = %d\n", pow_i);
2177 static int map_addr_to_serpar_number(struct i2c_msg *msg)
2179 if ((msg->buf[0] <= 15))
2181 else if (msg->buf[0] == 17)
2183 else if (msg->buf[0] == 16)
2185 else if (msg->buf[0] == 19)
2187 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
2189 else if (msg->buf[0] == 28)
2196 static int w7090p_tuner_write_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
2198 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
2201 u16 serpar_num = msg[0].buf[0];
2203 while (n_overflow == 1 && i) {
2204 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
2207 dprintk("Tuner ITF: write busy (overflow)\n");
2209 dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
2210 dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
2215 static int w7090p_tuner_read_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
2217 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
2218 u8 n_overflow = 1, n_empty = 1;
2220 u16 serpar_num = msg[0].buf[0];
2223 while (n_overflow == 1 && i) {
2224 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
2227 dprintk("TunerITF: read busy (overflow)\n");
2229 dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f));
2232 while (n_empty == 1 && i) {
2233 n_empty = dib7000p_read_word(state, 1984) & 0x1;
2236 dprintk("TunerITF: read busy (empty)\n");
2238 read_word = dib7000p_read_word(state, 1987);
2239 msg[1].buf[0] = (read_word >> 8) & 0xff;
2240 msg[1].buf[1] = (read_word) & 0xff;
2245 static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
2247 if (map_addr_to_serpar_number(&msg[0]) == 0) { /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_LT, PLL_CFG, PWM1_REG, ADCCLK, DIG_CFG_3; SLEEP_EN... */
2248 if (num == 1) { /* write */
2249 return w7090p_tuner_write_serpar(i2c_adap, msg, 1);
2251 return w7090p_tuner_read_serpar(i2c_adap, msg, 2);
2257 static int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap,
2258 struct i2c_msg msg[], int num, u16 apb_address)
2260 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
2263 if (num == 1) { /* write */
2264 dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
2266 word = dib7000p_read_word(state, apb_address);
2267 msg[1].buf[0] = (word >> 8) & 0xff;
2268 msg[1].buf[1] = (word) & 0xff;
2274 static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
2276 struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
2278 u16 apb_address = 0, word;
2280 switch (msg[0].buf[0]) {
2366 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
2367 word = dib7000p_read_word(state, 384 + i);
2368 msg[1].buf[0] = (word >> 8) & 0xff;
2369 msg[1].buf[1] = (word) & 0xff;
2372 if (num == 1) { /* write */
2373 word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]);
2375 word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);
2376 dib7000p_write_word(state, 72, word); /* Set the proper input */
2381 if (apb_address != 0) /* R/W access via APB */
2382 return dib7090p_rw_on_apb(i2c_adap, msg, num, apb_address);
2383 else /* R/W access via SERPAR */
2384 return w7090p_tuner_rw_serpar(i2c_adap, msg, num);
2389 static u32 dib7000p_i2c_func(struct i2c_adapter *adapter)
2391 return I2C_FUNC_I2C;
2394 static const struct i2c_algorithm dib7090_tuner_xfer_algo = {
2395 .master_xfer = dib7090_tuner_xfer,
2396 .functionality = dib7000p_i2c_func,
2399 static struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
2401 struct dib7000p_state *st = fe->demodulator_priv;
2402 return &st->dib7090_tuner_adap;
2405 static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive)
2409 /* drive host bus 2, 3, 4 */
2410 reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
2411 reg |= (drive << 12) | (drive << 6) | drive;
2412 dib7000p_write_word(state, 1798, reg);
2414 /* drive host bus 5,6 */
2415 reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
2416 reg |= (drive << 8) | (drive << 2);
2417 dib7000p_write_word(state, 1799, reg);
2419 /* drive host bus 7, 8, 9 */
2420 reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
2421 reg |= (drive << 12) | (drive << 6) | drive;
2422 dib7000p_write_word(state, 1800, reg);
2424 /* drive host bus 10, 11 */
2425 reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
2426 reg |= (drive << 8) | (drive << 2);
2427 dib7000p_write_word(state, 1801, reg);
2429 /* drive host bus 12, 13, 14 */
2430 reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
2431 reg |= (drive << 12) | (drive << 6) | drive;
2432 dib7000p_write_word(state, 1802, reg);
2437 static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 syncSize)
2440 u32 nom = (insertExtSynchro * P_Kin + syncSize);
2442 u32 syncFreq = ((nom << quantif) / denom);
2444 if ((syncFreq & ((1 << quantif) - 1)) != 0)
2445 syncFreq = (syncFreq >> quantif) + 1;
2447 syncFreq = (syncFreq >> quantif);
2450 syncFreq = syncFreq - 1;
2455 static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
2457 dprintk("Configure DibStream Tx\n");
2459 dib7000p_write_word(state, 1615, 1);
2460 dib7000p_write_word(state, 1603, P_Kin);
2461 dib7000p_write_word(state, 1605, P_Kout);
2462 dib7000p_write_word(state, 1606, insertExtSynchro);
2463 dib7000p_write_word(state, 1608, synchroMode);
2464 dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff);
2465 dib7000p_write_word(state, 1610, syncWord & 0xffff);
2466 dib7000p_write_word(state, 1612, syncSize);
2467 dib7000p_write_word(state, 1615, 0);
2472 static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize,
2477 dprintk("Configure DibStream Rx\n");
2478 if ((P_Kin != 0) && (P_Kout != 0)) {
2479 syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize);
2480 dib7000p_write_word(state, 1542, syncFreq);
2482 dib7000p_write_word(state, 1554, 1);
2483 dib7000p_write_word(state, 1536, P_Kin);
2484 dib7000p_write_word(state, 1537, P_Kout);
2485 dib7000p_write_word(state, 1539, synchroMode);
2486 dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff);
2487 dib7000p_write_word(state, 1541, syncWord & 0xffff);
2488 dib7000p_write_word(state, 1543, syncSize);
2489 dib7000p_write_word(state, 1544, dataOutRate);
2490 dib7000p_write_word(state, 1554, 0);
2495 static void dib7090_enMpegMux(struct dib7000p_state *state, int onoff)
2497 u16 reg_1287 = dib7000p_read_word(state, 1287);
2501 reg_1287 &= ~(1<<7);
2508 dib7000p_write_word(state, 1287, reg_1287);
2511 static void dib7090_configMpegMux(struct dib7000p_state *state,
2512 u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
2514 dprintk("Enable Mpeg mux\n");
2516 dib7090_enMpegMux(state, 0);
2518 /* If the input mode is MPEG do not divide the serial clock */
2519 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
2520 enSerialClkDiv2 = 0;
2522 dib7000p_write_word(state, 1287, ((pulseWidth & 0x1f) << 2)
2523 | ((enSerialMode & 0x1) << 1)
2524 | (enSerialClkDiv2 & 0x1));
2526 dib7090_enMpegMux(state, 1);
2529 static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode)
2531 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 7);
2535 dprintk("SET MPEG ON DIBSTREAM TX\n");
2536 dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
2540 dprintk("SET DIV_OUT ON DIBSTREAM TX\n");
2541 dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
2545 dprintk("SET ADC_OUT ON DIBSTREAM TX\n");
2546 dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
2552 dib7000p_write_word(state, 1288, reg_1288);
2555 static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode)
2557 u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 4);
2560 case DEMOUT_ON_HOSTBUS:
2561 dprintk("SET DEM OUT OLD INTERF ON HOST BUS\n");
2562 dib7090_enMpegMux(state, 0);
2565 case DIBTX_ON_HOSTBUS:
2566 dprintk("SET DIBSTREAM TX ON HOST BUS\n");
2567 dib7090_enMpegMux(state, 0);
2570 case MPEG_ON_HOSTBUS:
2571 dprintk("SET MPEG MUX ON HOST BUS\n");
2577 dib7000p_write_word(state, 1288, reg_1288);
2580 static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
2582 struct dib7000p_state *state = fe->demodulator_priv;
2586 case 0: /* only use the internal way - not the diversity input */
2587 dprintk("%s mode OFF : by default Enable Mpeg INPUT\n", __func__);
2588 dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
2590 /* Do not divide the serial clock of MPEG MUX */
2591 /* in SERIAL MODE in case input mode MPEG is used */
2592 reg_1287 = dib7000p_read_word(state, 1287);
2593 /* enSerialClkDiv2 == 1 ? */
2594 if ((reg_1287 & 0x1) == 1) {
2595 /* force enSerialClkDiv2 = 0 */
2597 dib7000p_write_word(state, 1287, reg_1287);
2599 state->input_mode_mpeg = 1;
2601 case 1: /* both ways */
2602 case 2: /* only the diversity input */
2603 dprintk("%s ON : Enable diversity INPUT\n", __func__);
2604 dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
2605 state->input_mode_mpeg = 0;
2609 dib7000p_set_diversity_in(&state->demod, onoff);
2613 static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
2615 struct dib7000p_state *state = fe->demodulator_priv;
2617 u16 outreg, smo_mode, fifo_threshold;
2618 u8 prefer_mpeg_mux_use = 1;
2621 dib7090_host_bus_drive(state, 1);
2623 fifo_threshold = 1792;
2624 smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
2625 outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1));
2628 case OUTMODE_HIGH_Z:
2632 case OUTMODE_MPEG2_SERIAL:
2633 if (prefer_mpeg_mux_use) {
2634 dprintk("setting output mode TS_SERIAL using Mpeg Mux\n");
2635 dib7090_configMpegMux(state, 3, 1, 1);
2636 dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
2637 } else {/* Use Smooth block */
2638 dprintk("setting output mode TS_SERIAL using Smooth bloc\n");
2639 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2640 outreg |= (2<<6) | (0 << 1);
2644 case OUTMODE_MPEG2_PAR_GATED_CLK:
2645 if (prefer_mpeg_mux_use) {
2646 dprintk("setting output mode TS_PARALLEL_GATED using Mpeg Mux\n");
2647 dib7090_configMpegMux(state, 2, 0, 0);
2648 dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
2649 } else { /* Use Smooth block */
2650 dprintk("setting output mode TS_PARALLEL_GATED using Smooth block\n");
2651 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2656 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
2657 dprintk("setting output mode TS_PARALLEL_CONT using Smooth block\n");
2658 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2662 case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */
2663 dprintk("setting output mode TS_FIFO using Smooth block\n");
2664 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2666 smo_mode |= (3 << 1);
2667 fifo_threshold = 512;
2670 case OUTMODE_DIVERSITY:
2671 dprintk("setting output mode MODE_DIVERSITY\n");
2672 dib7090_setDibTxMux(state, DIV_ON_DIBTX);
2673 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
2676 case OUTMODE_ANALOG_ADC:
2677 dprintk("setting output mode MODE_ANALOG_ADC\n");
2678 dib7090_setDibTxMux(state, ADC_ON_DIBTX);
2679 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
2682 if (mode != OUTMODE_HIGH_Z)
2683 outreg |= (1 << 10);
2685 if (state->cfg.output_mpeg2_in_188_bytes)
2686 smo_mode |= (1 << 5);
2688 ret |= dib7000p_write_word(state, 235, smo_mode);
2689 ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
2690 ret |= dib7000p_write_word(state, 1286, outreg);
2695 static int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
2697 struct dib7000p_state *state = fe->demodulator_priv;
2700 dprintk("sleep dib7090: %d\n", onoff);
2702 en_cur_state = dib7000p_read_word(state, 1922);
2704 if (en_cur_state > 0xff)
2705 state->tuner_enable = en_cur_state;
2708 en_cur_state &= 0x00ff;
2710 if (state->tuner_enable != 0)
2711 en_cur_state = state->tuner_enable;
2714 dib7000p_write_word(state, 1922, en_cur_state);
2719 static int dib7090_get_adc_power(struct dvb_frontend *fe)
2721 return dib7000p_get_adc_power(fe);
2724 static int dib7090_slave_reset(struct dvb_frontend *fe)
2726 struct dib7000p_state *state = fe->demodulator_priv;
2729 reg = dib7000p_read_word(state, 1794);
2730 dib7000p_write_word(state, 1794, reg | (4 << 12));
2732 dib7000p_write_word(state, 1032, 0xffff);
2736 static const struct dvb_frontend_ops dib7000p_ops;
2737 static struct dvb_frontend *dib7000p_init(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
2739 struct dvb_frontend *demod;
2740 struct dib7000p_state *st;
2741 st = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
2745 memcpy(&st->cfg, cfg, sizeof(struct dib7000p_config));
2746 st->i2c_adap = i2c_adap;
2747 st->i2c_addr = i2c_addr;
2748 st->gpio_val = cfg->gpio_val;
2749 st->gpio_dir = cfg->gpio_dir;
2751 /* Ensure the output mode remains at the previous default if it's
2752 * not specifically set by the caller.
2754 if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2755 st->cfg.output_mode = OUTMODE_MPEG2_FIFO;
2758 demod->demodulator_priv = st;
2759 memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
2760 mutex_init(&st->i2c_buffer_lock);
2762 dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
2764 if (dib7000p_identify(st) != 0)
2767 st->version = dib7000p_read_word(st, 897);
2769 /* FIXME: make sure the dev.parent field is initialized, or else
2770 request_firmware() will hit an OOPS (this should be moved somewhere
2772 st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent;
2774 dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
2776 /* init 7090 tuner adapter */
2777 strscpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface",
2778 sizeof(st->dib7090_tuner_adap.name));
2779 st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo;
2780 st->dib7090_tuner_adap.algo_data = NULL;
2781 st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent;
2782 i2c_set_adapdata(&st->dib7090_tuner_adap, st);
2783 i2c_add_adapter(&st->dib7090_tuner_adap);
2785 dib7000p_demod_reset(st);
2787 dib7000p_reset_stats(demod);
2789 if (st->version == SOC7090) {
2790 dib7090_set_output_mode(demod, st->cfg.output_mode);
2791 dib7090_set_diversity_in(demod, 0);
2801 void *dib7000p_attach(struct dib7000p_ops *ops)
2806 ops->slave_reset = dib7090_slave_reset;
2807 ops->get_adc_power = dib7090_get_adc_power;
2808 ops->dib7000pc_detection = dib7000pc_detection;
2809 ops->get_i2c_tuner = dib7090_get_i2c_tuner;
2810 ops->tuner_sleep = dib7090_tuner_sleep;
2811 ops->init = dib7000p_init;
2812 ops->set_agc1_min = dib7000p_set_agc1_min;
2813 ops->set_gpio = dib7000p_set_gpio;
2814 ops->i2c_enumeration = dib7000p_i2c_enumeration;
2815 ops->pid_filter = dib7000p_pid_filter;
2816 ops->pid_filter_ctrl = dib7000p_pid_filter_ctrl;
2817 ops->get_i2c_master = dib7000p_get_i2c_master;
2818 ops->update_pll = dib7000p_update_pll;
2819 ops->ctrl_timf = dib7000p_ctrl_timf;
2820 ops->get_agc_values = dib7000p_get_agc_values;
2821 ops->set_wbd_ref = dib7000p_set_wbd_ref;
2825 EXPORT_SYMBOL(dib7000p_attach);
2827 static const struct dvb_frontend_ops dib7000p_ops = {
2828 .delsys = { SYS_DVBT },
2830 .name = "DiBcom 7000PC",
2831 .frequency_min_hz = 44250 * kHz,
2832 .frequency_max_hz = 867250 * kHz,
2833 .frequency_stepsize_hz = 62500,
2834 .caps = FE_CAN_INVERSION_AUTO |
2835 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2836 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2837 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
2838 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
2841 .release = dib7000p_release,
2843 .init = dib7000p_wakeup,
2844 .sleep = dib7000p_sleep,
2846 .set_frontend = dib7000p_set_frontend,
2847 .get_tune_settings = dib7000p_fe_get_tune_settings,
2848 .get_frontend = dib7000p_get_frontend,
2850 .read_status = dib7000p_read_status,
2851 .read_ber = dib7000p_read_ber,
2852 .read_signal_strength = dib7000p_read_signal_strength,
2853 .read_snr = dib7000p_read_snr,
2854 .read_ucblocks = dib7000p_read_unc_blocks,
2857 MODULE_AUTHOR("Olivier Grenie <olivie.grenie@parrot.com>");
2858 MODULE_AUTHOR("Patrick Boettcher <patrick.boettcher@posteo.de>");
2859 MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator");
2860 MODULE_LICENSE("GPL");