drivers/media/dvb-frontends/cxd2841er.c

   1 /*
   2  * cxd2841er.c
   3  *
   4  * Sony CXD2441ER digital demodulator driver
   5  *
   6  * Copyright 2012 Sony Corporation
   7  * Copyright (C) 2014 NetUP Inc.
   8  * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
   9  * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20   */
  21
  22 #include <linux/module.h>
  23 #include <linux/init.h>
  24 #include <linux/string.h>
  25 #include <linux/slab.h>
  26 #include <linux/bitops.h>
  27 #include <linux/math64.h>
  28 #include <linux/log2.h>
  29 #include <linux/dynamic_debug.h>
  30
  31 #include "dvb_math.h"
  32 #include "dvb_frontend.h"
  33 #include "cxd2841er.h"
  34 #include "cxd2841er_priv.h"
  35
  36 enum cxd2841er_state {
  37         STATE_SHUTDOWN = 0,
  38         STATE_SLEEP_S,
  39         STATE_ACTIVE_S,
  40         STATE_SLEEP_TC,
  41         STATE_ACTIVE_TC
  42 };
  43
  44 struct cxd2841er_priv {
  45         struct dvb_frontend             frontend;
  46         struct i2c_adapter              *i2c;
  47         u8                              i2c_addr_slvx;
  48         u8                              i2c_addr_slvt;
  49         const struct cxd2841er_config   *config;
  50         enum cxd2841er_state            state;
  51         u8                              system;
  52 };
  53
  54 static const struct cxd2841er_cnr_data s_cn_data[] = {
  55         { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
  56         { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
  57         { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
  58         { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
  59         { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
  60         { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
  61         { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
  62         { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
  63         { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
  64         { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
  65         { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
  66         { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
  67         { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
  68         { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
  69         { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
  70         { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
  71         { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
  72         { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
  73         { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
  74         { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
  75         { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
  76         { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
  77         { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
  78         { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
  79         { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
  80         { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
  81         { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
  82         { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
  83         { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
  84         { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
  85         { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
  86         { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
  87         { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
  88         { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
  89         { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
  90         { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
  91         { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
  92         { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
  93         { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
  94         { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
  95         { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
  96         { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
  97         { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
  98         { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
  99         { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
 100         { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
 101         { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
 102         { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 103         { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 104         { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
 105         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 106         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 107         { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
 108         { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
 109         { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
 110         { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
 111         { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
 112         { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
 113         { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
 114         { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
 115         { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
 116         { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
 117         { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
 118         { 0x0015, 19900 }, { 0x0014, 20000 },
 119 };
 120
 121 static const struct cxd2841er_cnr_data s2_cn_data[] = {
 122         { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
 123         { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
 124         { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
 125         { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
 126         { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
 127         { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
 128         { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
 129         { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
 130         { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
 131         { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
 132         { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
 133         { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
 134         { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
 135         { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
 136         { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
 137         { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
 138         { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
 139         { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
 140         { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
 141         { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
 142         { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
 143         { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
 144         { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
 145         { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
 146         { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
 147         { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
 148         { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
 149         { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
 150         { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
 151         { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
 152         { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
 153         { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
 154         { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
 155         { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
 156         { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
 157         { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
 158         { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
 159         { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
 160         { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
 161         { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
 162         { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
 163         { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
 164         { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
 165         { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
 166         { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
 167         { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
 168         { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
 169         { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 170         { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 171         { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
 172         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 173         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 174         { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
 175         { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
 176         { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
 177         { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
 178         { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
 179         { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
 180         { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
 181         { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
 182         { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
 183         { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
 184         { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
 185         { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
 186 };
 187
 188 #define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
 189
 190 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
 191                                 u8 addr, u8 reg, u8 write,
 192                                 const u8 *data, u32 len)
 193 {
 194         dev_dbg(&priv->i2c->dev,
 195                 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
 196                 (write == 0 ? "read" : "write"), addr, reg, len);
 197         print_hex_dump_bytes("cxd2841er: I2C data: ",
 198                 DUMP_PREFIX_OFFSET, data, len);
 199 }
 200
 201 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
 202                                 u8 addr, u8 reg, const u8 *data, u32 len)
 203 {
 204         int ret;
 205         u8 buf[len+1];
 206         u8 i2c_addr = (addr == I2C_SLVX ?
 207                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 208         struct i2c_msg msg[1] = {
 209                 {
 210                         .addr = i2c_addr,
 211                         .flags = 0,
 212                         .len = sizeof(buf),
 213                         .buf = buf,
 214                 }
 215         };
 216
 217         cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
 218         buf[0] = reg;
 219         memcpy(&buf[1], data, len);
 220
 221         ret = i2c_transfer(priv->i2c, msg, 1);
 222         if (ret >= 0 && ret != 1)
 223                 ret = -EIO;
 224         if (ret < 0) {
 225                 dev_warn(&priv->i2c->dev,
 226                         "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
 227                         KBUILD_MODNAME, ret, i2c_addr, reg, len);
 228                 return ret;
 229         }
 230         return 0;
 231 }
 232
 233 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
 234                                u8 addr, u8 reg, u8 val)
 235 {
 236         return cxd2841er_write_regs(priv, addr, reg, &val, 1);
 237 }
 238
 239 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
 240                                u8 addr, u8 reg, u8 *val, u32 len)
 241 {
 242         int ret;
 243         u8 i2c_addr = (addr == I2C_SLVX ?
 244                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 245         struct i2c_msg msg[2] = {
 246                 {
 247                         .addr = i2c_addr,
 248                         .flags = 0,
 249                         .len = 1,
 250                         .buf = &reg,
 251                 }, {
 252                         .addr = i2c_addr,
 253                         .flags = I2C_M_RD,
 254                         .len = len,
 255                         .buf = val,
 256                 }
 257         };
 258
 259         ret = i2c_transfer(priv->i2c, &msg[0], 1);
 260         if (ret >= 0 && ret != 1)
 261                 ret = -EIO;
 262         if (ret < 0) {
 263                 dev_warn(&priv->i2c->dev,
 264                         "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
 265                         KBUILD_MODNAME, ret, i2c_addr, reg);
 266                 return ret;
 267         }
 268         ret = i2c_transfer(priv->i2c, &msg[1], 1);
 269         if (ret >= 0 && ret != 1)
 270                 ret = -EIO;
 271         if (ret < 0) {
 272                 dev_warn(&priv->i2c->dev,
 273                         "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
 274                         KBUILD_MODNAME, ret, i2c_addr, reg);
 275                 return ret;
 276         }
 277         return 0;
 278 }
 279
 280 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
 281                               u8 addr, u8 reg, u8 *val)
 282 {
 283         return cxd2841er_read_regs(priv, addr, reg, val, 1);
 284 }
 285
 286 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
 287                                   u8 addr, u8 reg, u8 data, u8 mask)
 288 {
 289         int res;
 290         u8 rdata;
 291
 292         if (mask != 0xff) {
 293                 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
 294                 if (res)
 295                         return res;
 296                 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
 297         }
 298         return cxd2841er_write_reg(priv, addr, reg, data);
 299 }
 300
 301 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
 302                                            u32 symbol_rate)
 303 {
 304         u32 reg_value = 0;
 305         u8 data[3] = {0, 0, 0};
 306
 307         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 308         /*
 309          * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
 310          *          = ((symbolRateKSps * 2^14) + 500) / 1000
 311          *          = ((symbolRateKSps * 16384) + 500) / 1000
 312          */
 313         reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
 314         if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
 315                 dev_err(&priv->i2c->dev,
 316                         "%s(): reg_value is out of range\n", __func__);
 317                 return -EINVAL;
 318         }
 319         data[0] = (u8)((reg_value >> 16) & 0x0F);
 320         data[1] = (u8)((reg_value >>  8) & 0xFF);
 321         data[2] = (u8)(reg_value & 0xFF);
 322         /* Set SLV-T Bank : 0xAE */
 323         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 324         cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
 325         return 0;
 326 }
 327
 328 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 329                                         u8 system);
 330
 331 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
 332                                          u8 system, u32 symbol_rate)
 333 {
 334         int ret;
 335         u8 data[4] = { 0, 0, 0, 0 };
 336
 337         if (priv->state != STATE_SLEEP_S) {
 338                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 339                         __func__, (int)priv->state);
 340                 return -EINVAL;
 341         }
 342         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 343         cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
 344         /* Set demod mode */
 345         if (system == SYS_DVBS) {
 346                 data[0] = 0x0A;
 347         } else if (system == SYS_DVBS2) {
 348                 data[0] = 0x0B;
 349         } else {
 350                 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
 351                         __func__, system);
 352                 return -EINVAL;
 353         }
 354         /* Set SLV-X Bank : 0x00 */
 355         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 356         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
 357         /* DVB-S/S2 */
 358         data[0] = 0x00;
 359         /* Set SLV-T Bank : 0x00 */
 360         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 361         /* Enable S/S2 auto detection 1 */
 362         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
 363         /* Set SLV-T Bank : 0xAE */
 364         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 365         /* Enable S/S2 auto detection 2 */
 366         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
 367         /* Set SLV-T Bank : 0x00 */
 368         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 369         /* Enable demod clock */
 370         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
 371         /* Enable ADC clock */
 372         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
 373         /* Enable ADC 1 */
 374         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 375         /* Enable ADC 2 */
 376         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
 377         /* Set SLV-X Bank : 0x00 */
 378         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 379         /* Enable ADC 3 */
 380         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
 381         /* Set SLV-T Bank : 0xA3 */
 382         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
 383         cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
 384         data[0] = 0x07;
 385         data[1] = 0x3B;
 386         data[2] = 0x08;
 387         data[3] = 0xC5;
 388         /* Set SLV-T Bank : 0xAB */
 389         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
 390         cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
 391         data[0] = 0x05;
 392         data[1] = 0x80;
 393         data[2] = 0x0A;
 394         data[3] = 0x80;
 395         cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
 396         data[0] = 0x0C;
 397         data[1] = 0xCC;
 398         cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
 399         /* Set demod parameter */
 400         ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
 401         if (ret != 0)
 402                 return ret;
 403         /* Set SLV-T Bank : 0x00 */
 404         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 405         /* disable Hi-Z setting 1 */
 406         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
 407         /* disable Hi-Z setting 2 */
 408         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
 409         priv->state = STATE_ACTIVE_S;
 410         return 0;
 411 }
 412
 413 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
 414                                                u32 bandwidth);
 415
 416 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
 417                                                 u32 bandwidth);
 418
 419 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
 420                                                u32 bandwidth);
 421
 422 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
 423                                    struct dtv_frontend_properties *p)
 424 {
 425         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 426         if (priv->state != STATE_ACTIVE_S &&
 427                         priv->state != STATE_ACTIVE_TC) {
 428                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
 429                         __func__, priv->state);
 430                 return -EINVAL;
 431         }
 432         /* Set SLV-T Bank : 0x00 */
 433         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 434         /* disable TS output */
 435         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 436         if (priv->state == STATE_ACTIVE_S)
 437                 return cxd2841er_dvbs2_set_symbol_rate(
 438                                 priv, p->symbol_rate / 1000);
 439         else if (priv->state == STATE_ACTIVE_TC) {
 440                 switch (priv->system) {
 441                 case SYS_DVBT:
 442                         return cxd2841er_sleep_tc_to_active_t_band(
 443                                         priv, p->bandwidth_hz);
 444                 case SYS_DVBT2:
 445                         return cxd2841er_sleep_tc_to_active_t2_band(
 446                                         priv, p->bandwidth_hz);
 447                 case SYS_DVBC_ANNEX_A:
 448                         return cxd2841er_sleep_tc_to_active_c_band(
 449                                         priv, 8000000);
 450                 }
 451         }
 452         dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
 453                 __func__, priv->system);
 454         return -EINVAL;
 455 }
 456
 457 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
 458 {
 459         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 460         if (priv->state != STATE_ACTIVE_S) {
 461                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 462                         __func__, priv->state);
 463                 return -EINVAL;
 464         }
 465         /* Set SLV-T Bank : 0x00 */
 466         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 467         /* disable TS output */
 468         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 469         /* enable Hi-Z setting 1 */
 470         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
 471         /* enable Hi-Z setting 2 */
 472         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 473         /* Set SLV-X Bank : 0x00 */
 474         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 475         /* disable ADC 1 */
 476         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 477         /* Set SLV-T Bank : 0x00 */
 478         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 479         /* disable ADC clock */
 480         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
 481         /* disable ADC 2 */
 482         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 483         /* disable ADC 3 */
 484         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 485         /* SADC Bias ON */
 486         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 487         /* disable demod clock */
 488         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 489         /* Set SLV-T Bank : 0xAE */
 490         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 491         /* disable S/S2 auto detection1 */
 492         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 493         /* Set SLV-T Bank : 0x00 */
 494         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 495         /* disable S/S2 auto detection2 */
 496         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
 497         priv->state = STATE_SLEEP_S;
 498         return 0;
 499 }
 500
 501 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
 502 {
 503         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 504         if (priv->state != STATE_SLEEP_S) {
 505                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 506                         __func__, priv->state);
 507                 return -EINVAL;
 508         }
 509         /* Set SLV-T Bank : 0x00 */
 510         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 511         /* Disable DSQOUT */
 512         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 513         /* Disable DSQIN */
 514         cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
 515         /* Set SLV-X Bank : 0x00 */
 516         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 517         /* Disable oscillator */
 518         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 519         /* Set demod mode */
 520         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 521         priv->state = STATE_SHUTDOWN;
 522         return 0;
 523 }
 524
 525 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
 526 {
 527         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 528         if (priv->state != STATE_SLEEP_TC) {
 529                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 530                         __func__, priv->state);
 531                 return -EINVAL;
 532         }
 533         /* Set SLV-X Bank : 0x00 */
 534         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 535         /* Disable oscillator */
 536         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 537         /* Set demod mode */
 538         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 539         priv->state = STATE_SHUTDOWN;
 540         return 0;
 541 }
 542
 543 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
 544 {
 545         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 546         if (priv->state != STATE_ACTIVE_TC) {
 547                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 548                         __func__, priv->state);
 549                 return -EINVAL;
 550         }
 551         /* Set SLV-T Bank : 0x00 */
 552         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 553         /* disable TS output */
 554         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 555         /* enable Hi-Z setting 1 */
 556         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 557         /* enable Hi-Z setting 2 */
 558         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 559         /* Set SLV-X Bank : 0x00 */
 560         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 561         /* disable ADC 1 */
 562         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 563         /* Set SLV-T Bank : 0x00 */
 564         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 565         /* Disable ADC 2 */
 566         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 567         /* Disable ADC 3 */
 568         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 569         /* Disable ADC clock */
 570         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 571         /* Disable RF level monitor */
 572         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 573         /* Disable demod clock */
 574         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 575         priv->state = STATE_SLEEP_TC;
 576         return 0;
 577 }
 578
 579 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
 580 {
 581         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 582         if (priv->state != STATE_ACTIVE_TC) {
 583                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 584                         __func__, priv->state);
 585                 return -EINVAL;
 586         }
 587         /* Set SLV-T Bank : 0x00 */
 588         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 589         /* disable TS output */
 590         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 591         /* enable Hi-Z setting 1 */
 592         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 593         /* enable Hi-Z setting 2 */
 594         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 595         /* Cancel DVB-T2 setting */
 596         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
 597         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
 598         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
 599         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
 600         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
 601         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
 602         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
 603         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
 604         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
 605         /* Set SLV-X Bank : 0x00 */
 606         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 607         /* disable ADC 1 */
 608         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 609         /* Set SLV-T Bank : 0x00 */
 610         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 611         /* Disable ADC 2 */
 612         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 613         /* Disable ADC 3 */
 614         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 615         /* Disable ADC clock */
 616         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 617         /* Disable RF level monitor */
 618         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 619         /* Disable demod clock */
 620         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 621         priv->state = STATE_SLEEP_TC;
 622         return 0;
 623 }
 624
 625 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
 626 {
 627         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 628         if (priv->state != STATE_ACTIVE_TC) {
 629                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 630                         __func__, priv->state);
 631                 return -EINVAL;
 632         }
 633         /* Set SLV-T Bank : 0x00 */
 634         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 635         /* disable TS output */
 636         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 637         /* enable Hi-Z setting 1 */
 638         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 639         /* enable Hi-Z setting 2 */
 640         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 641         /* Cancel DVB-C setting */
 642         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
 643         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
 644         /* Set SLV-X Bank : 0x00 */
 645         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 646         /* disable ADC 1 */
 647         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 648         /* Set SLV-T Bank : 0x00 */
 649         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 650         /* Disable ADC 2 */
 651         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 652         /* Disable ADC 3 */
 653         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 654         /* Disable ADC clock */
 655         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 656         /* Disable RF level monitor */
 657         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 658         /* Disable demod clock */
 659         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 660         priv->state = STATE_SLEEP_TC;
 661         return 0;
 662 }
 663
 664 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
 665 {
 666         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 667         if (priv->state != STATE_SHUTDOWN) {
 668                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 669                         __func__, priv->state);
 670                 return -EINVAL;
 671         }
 672         /* Set SLV-X Bank : 0x00 */
 673         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 674         /* Clear all demodulator registers */
 675         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 676         usleep_range(3000, 5000);
 677         /* Set SLV-X Bank : 0x00 */
 678         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 679         /* Set demod SW reset */
 680         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 681         /* Set X'tal clock to 20.5Mhz */
 682         cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 683         /* Set demod mode */
 684         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
 685         /* Clear demod SW reset */
 686         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 687         usleep_range(1000, 2000);
 688         /* Set SLV-T Bank : 0x00 */
 689         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 690         /* enable DSQOUT */
 691         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
 692         /* enable DSQIN */
 693         cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
 694         /* TADC Bias On */
 695         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 696         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 697         /* SADC Bias On */
 698         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 699         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 700         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 701         priv->state = STATE_SLEEP_S;
 702         return 0;
 703 }
 704
 705 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
 706 {
 707         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 708         if (priv->state != STATE_SHUTDOWN) {
 709                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 710                         __func__, priv->state);
 711                 return -EINVAL;
 712         }
 713         /* Set SLV-X Bank : 0x00 */
 714         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 715         /* Clear all demodulator registers */
 716         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 717         usleep_range(3000, 5000);
 718         /* Set SLV-X Bank : 0x00 */
 719         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 720         /* Set demod SW reset */
 721         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 722         /* Set X'tal clock to 20.5Mhz */
 723         cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
 724         cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 725         /* Clear demod SW reset */
 726         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 727         usleep_range(1000, 2000);
 728         /* Set SLV-T Bank : 0x00 */
 729         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 730         /* TADC Bias On */
 731         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 732         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 733         /* SADC Bias On */
 734         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 735         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 736         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 737         priv->state = STATE_SLEEP_TC;
 738         return 0;
 739 }
 740
 741 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
 742 {
 743         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 744         /* Set SLV-T Bank : 0x00 */
 745         cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
 746         /* SW Reset */
 747         cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
 748         /* Enable TS output */
 749         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
 750         return 0;
 751 }
 752
 753 /* Set TS parallel mode */
 754 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 755                                         u8 system)
 756 {
 757         u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
 758
 759         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 760         /* Set SLV-T Bank : 0x00 */
 761         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 762         cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
 763         cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
 764         cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
 765         dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
 766                 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
 767
 768         /*
 769          * slave    Bank    Addr    Bit    default    Name
 770          * <SLV-T>  00h     D9h     [7:0]  8'h08      OTSCKPERIOD
 771          */
 772         cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
 773         /*
 774          * Disable TS IF Clock
 775          * slave    Bank    Addr    Bit    default    Name
 776          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 777          */
 778         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
 779         /*
 780          * slave    Bank    Addr    Bit    default    Name
 781          * <SLV-T>  00h     33h     [1:0]  2'b01      OREG_CKSEL_TSIF
 782          */
 783         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
 784         /*
 785          * Enable TS IF Clock
 786          * slave    Bank    Addr    Bit    default    Name
 787          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 788          */
 789         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
 790
 791         if (system == SYS_DVBT) {
 792                 /* Enable parity period for DVB-T */
 793                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 794                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 795         } else if (system == SYS_DVBC_ANNEX_A) {
 796                 /* Enable parity period for DVB-C */
 797                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 798                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 799         }
 800 }
 801
 802 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
 803 {
 804         u8 chip_id;
 805
 806         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 807         cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
 808         cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
 809         return chip_id;
 810 }
 811
 812 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
 813                                    enum fe_status *status)
 814 {
 815         u8 reg = 0;
 816         struct cxd2841er_priv *priv = fe->demodulator_priv;
 817
 818         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 819         *status = 0;
 820         if (priv->state != STATE_ACTIVE_S) {
 821                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 822                         __func__, priv->state);
 823                 return -EINVAL;
 824         }
 825         /* Set SLV-T Bank : 0xA0 */
 826         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
 827         /*
 828          *  slave     Bank      Addr      Bit      Signal name
 829          * <SLV-T>    A0h       11h       [2]      ITSLOCK
 830          */
 831         cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
 832         if (reg & 0x04) {
 833                 *status = FE_HAS_SIGNAL
 834                         | FE_HAS_CARRIER
 835                         | FE_HAS_VITERBI
 836                         | FE_HAS_SYNC
 837                         | FE_HAS_LOCK;
 838         }
 839         dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
 840         return 0;
 841 }
 842
 843 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
 844                                       u8 *sync, u8 *tslock, u8 *unlock)
 845 {
 846         u8 data = 0;
 847
 848         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 849         if (priv->state != STATE_ACTIVE_TC)
 850                 return -EINVAL;
 851         if (priv->system == SYS_DVBT) {
 852                 /* Set SLV-T Bank : 0x10 */
 853                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 854         } else {
 855                 /* Set SLV-T Bank : 0x20 */
 856                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
 857         }
 858         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
 859         if ((data & 0x07) == 0x07) {
 860                 dev_dbg(&priv->i2c->dev,
 861                         "%s(): invalid hardware state detected\n", __func__);
 862                 *sync = 0;
 863                 *tslock = 0;
 864                 *unlock = 0;
 865         } else {
 866                 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
 867                 *tslock = ((data & 0x20) ? 1 : 0);
 868                 *unlock = ((data & 0x10) ? 1 : 0);
 869         }
 870         return 0;
 871 }
 872
 873 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
 874 {
 875         u8 data;
 876
 877         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 878         if (priv->state != STATE_ACTIVE_TC)
 879                 return -EINVAL;
 880         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 881         cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
 882         if ((data & 0x01) == 0) {
 883                 *tslock = 0;
 884         } else {
 885                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
 886                 *tslock = ((data & 0x20) ? 1 : 0);
 887         }
 888         return 0;
 889 }
 890
 891 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
 892                                     enum fe_status *status)
 893 {
 894         int ret = 0;
 895         u8 sync = 0;
 896         u8 tslock = 0;
 897         u8 unlock = 0;
 898         struct cxd2841er_priv *priv = fe->demodulator_priv;
 899
 900         *status = 0;
 901         if (priv->state == STATE_ACTIVE_TC) {
 902                 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
 903                         ret = cxd2841er_read_status_t_t2(
 904                                 priv, &sync, &tslock, &unlock);
 905                         if (ret)
 906                                 goto done;
 907                         if (unlock)
 908                                 goto done;
 909                         if (sync)
 910                                 *status = FE_HAS_SIGNAL |
 911                                         FE_HAS_CARRIER |
 912                                         FE_HAS_VITERBI |
 913                                         FE_HAS_SYNC;
 914                         if (tslock)
 915                                 *status |= FE_HAS_LOCK;
 916                 } else if (priv->system == SYS_DVBC_ANNEX_A) {
 917                         ret = cxd2841er_read_status_c(priv, &tslock);
 918                         if (ret)
 919                                 goto done;
 920                         if (tslock)
 921                                 *status = FE_HAS_SIGNAL |
 922                                         FE_HAS_CARRIER |
 923                                         FE_HAS_VITERBI |
 924                                         FE_HAS_SYNC |
 925                                         FE_HAS_LOCK;
 926                 }
 927         }
 928 done:
 929         dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
 930         return ret;
 931 }
 932
 933 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
 934                                              int *offset)
 935 {
 936         u8 data[3];
 937         u8 is_hs_mode;
 938         s32 cfrl_ctrlval;
 939         s32 temp_div, temp_q, temp_r;
 940
 941         if (priv->state != STATE_ACTIVE_S) {
 942                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
 943                         __func__, priv->state);
 944                 return -EINVAL;
 945         }
 946         /*
 947          * Get High Sampling Rate mode
 948          *  slave     Bank      Addr      Bit      Signal name
 949          * <SLV-T>    A0h       10h       [0]      ITRL_LOCK
 950          */
 951         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
 952         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
 953         if (data[0] & 0x01) {
 954                 /*
 955                  *  slave     Bank      Addr      Bit      Signal name
 956                  * <SLV-T>    A0h       50h       [4]      IHSMODE
 957                  */
 958                 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
 959                 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
 960         } else {
 961                 dev_dbg(&priv->i2c->dev,
 962                         "%s(): unable to detect sampling rate mode\n",
 963                         __func__);
 964                 return -EINVAL;
 965         }
 966         /*
 967          *  slave     Bank      Addr      Bit      Signal name
 968          * <SLV-T>    A0h       45h       [4:0]    ICFRL_CTRLVAL[20:16]
 969          * <SLV-T>    A0h       46h       [7:0]    ICFRL_CTRLVAL[15:8]
 970          * <SLV-T>    A0h       47h       [7:0]    ICFRL_CTRLVAL[7:0]
 971          */
 972         cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
 973         cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
 974                                 (((u32)data[1] & 0xFF) <<  8) |
 975                                 ((u32)data[2] & 0xFF), 20);
 976         temp_div = (is_hs_mode ? 1048576 : 1572864);
 977         if (cfrl_ctrlval > 0) {
 978                 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
 979                         temp_div, &temp_r);
 980         } else {
 981                 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
 982                         temp_div, &temp_r);
 983         }
 984         if (temp_r >= temp_div / 2)
 985                 temp_q++;
 986         if (cfrl_ctrlval > 0)
 987                 temp_q *= -1;
 988         *offset = temp_q;
 989         return 0;
 990 }
 991
 992 int cxd2841er_get_carrier_offset_t2(
 993         struct cxd2841er_priv *priv, u32 bandwidth, int *offset)
 994 {
 995         u8 data[4];
 996
 997         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 998         if (priv->state != STATE_ACTIVE_TC) {
 999                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1000                         __func__, priv->state);
1001                 return -EINVAL;
1002         }
1003         if (priv->system != SYS_DVBT2) {
1004                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1005                         __func__, priv->system);
1006                 return -EINVAL;
1007         }
1008         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1009         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1010         *offset = -1 * sign_extend32(
1011                 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1012                 ((u32)data[2] << 8) | (u32)data[3], 27);
1013         switch (bandwidth) {
1014         case 1712000:
1015                 *offset /= 582;
1016                 break;
1017         case 5000000:
1018         case 6000000:
1019         case 7000000:
1020         case 8000000:
1021                 *offset *= (bandwidth / 1000000);
1022                 *offset /= 940;
1023                 break;
1024         default:
1025                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1026                         __func__, bandwidth);
1027                 return -EINVAL;
1028         }
1029         return 0;
1030 }
1031
1032 int cxd2841er_get_carrier_offset_c(
1033         struct cxd2841er_priv *priv, int *offset)
1034 {
1035         u8 data[2];
1036
1037         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1038         if (priv->state != STATE_ACTIVE_TC) {
1039                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1040                         __func__, priv->state);
1041                 return -EINVAL;
1042         }
1043         if (priv->system != SYS_DVBC_ANNEX_A) {
1044                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1045                         __func__, priv->system);
1046                 return -EINVAL;
1047         }
1048         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1049         cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1050         *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1051                                                 | (u32)data[1], 13), 16384);
1052         return 0;
1053 }
1054
1055 static int cxd2841er_read_packet_errors_t(
1056                 struct cxd2841er_priv *priv, u32 *penum)
1057 {
1058         u8 data[3];
1059
1060         *penum = 0;
1061         if (priv->state != STATE_ACTIVE_TC) {
1062                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1063                         __func__, priv->state);
1064                 return -EINVAL;
1065         }
1066         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1067         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1068         if (data[2] & 0x01)
1069                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1070         return 0;
1071 }
1072
1073 static int cxd2841er_read_packet_errors_t2(
1074                 struct cxd2841er_priv *priv, u32 *penum)
1075 {
1076         u8 data[3];
1077
1078         *penum = 0;
1079         if (priv->state != STATE_ACTIVE_TC) {
1080                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1081                         __func__, priv->state);
1082                 return -EINVAL;
1083         }
1084         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1085         cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1086         if (data[0] & 0x01)
1087                 *penum = ((u32)data[1] << 8) | (u32)data[2];
1088         return 0;
1089 }
1090
1091 static u32 cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv)
1092 {
1093         u8 data[11];
1094         u32 bit_error, bit_count;
1095         u32 temp_q, temp_r;
1096
1097         /* Set SLV-T Bank : 0xA0 */
1098         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1099         /*
1100          *  slave     Bank      Addr      Bit      Signal name
1101          * <SLV-T>    A0h       35h       [0]      IFVBER_VALID
1102          * <SLV-T>    A0h       36h       [5:0]    IFVBER_BITERR[21:16]
1103          * <SLV-T>    A0h       37h       [7:0]    IFVBER_BITERR[15:8]
1104          * <SLV-T>    A0h       38h       [7:0]    IFVBER_BITERR[7:0]
1105          * <SLV-T>    A0h       3Dh       [5:0]    IFVBER_BITNUM[21:16]
1106          * <SLV-T>    A0h       3Eh       [7:0]    IFVBER_BITNUM[15:8]
1107          * <SLV-T>    A0h       3Fh       [7:0]    IFVBER_BITNUM[7:0]
1108          */
1109         cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1110         if (data[0] & 0x01) {
1111                 bit_error = ((u32)(data[1]  & 0x3F) << 16) |
1112                         ((u32)(data[2]  & 0xFF) <<  8) |
1113                         (u32)(data[3]  & 0xFF);
1114                 bit_count = ((u32)(data[8]  & 0x3F) << 16) |
1115                         ((u32)(data[9]  & 0xFF) <<  8) |
1116                         (u32)(data[10] & 0xFF);
1117                 /*
1118                  *      BER = bitError / bitCount
1119                  *      = (bitError * 10^7) / bitCount
1120                  *      = ((bitError * 625 * 125 * 128) / bitCount
1121                  */
1122                 if ((bit_count == 0) || (bit_error > bit_count)) {
1123                         dev_dbg(&priv->i2c->dev,
1124                                 "%s(): invalid bit_error %d, bit_count %d\n",
1125                                 __func__, bit_error, bit_count);
1126                         return 0;
1127                 }
1128                 temp_q = div_u64_rem(10000000ULL * bit_error,
1129                                                 bit_count, &temp_r);
1130                 if (bit_count != 1 && temp_r >= bit_count / 2)
1131                         temp_q++;
1132                 return temp_q;
1133         }
1134         dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1135         return 0;
1136 }
1137
1138
1139 static u32 cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv)
1140 {
1141         u8 data[5];
1142         u32 bit_error, period;
1143         u32 temp_q, temp_r;
1144         u32 result = 0;
1145
1146         /* Set SLV-T Bank : 0xB2 */
1147         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1148         /*
1149          *  slave     Bank      Addr      Bit      Signal name
1150          * <SLV-T>    B2h       30h       [0]      IFLBER_VALID
1151          * <SLV-T>    B2h       31h       [3:0]    IFLBER_BITERR[27:24]
1152          * <SLV-T>    B2h       32h       [7:0]    IFLBER_BITERR[23:16]
1153          * <SLV-T>    B2h       33h       [7:0]    IFLBER_BITERR[15:8]
1154          * <SLV-T>    B2h       34h       [7:0]    IFLBER_BITERR[7:0]
1155          */
1156         cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1157         if (data[0] & 0x01) {
1158                 /* Bit error count */
1159                 bit_error = ((u32)(data[1] & 0x0F) << 24) |
1160                         ((u32)(data[2] & 0xFF) << 16) |
1161                         ((u32)(data[3] & 0xFF) <<  8) |
1162                         (u32)(data[4] & 0xFF);
1163
1164                 /* Set SLV-T Bank : 0xA0 */
1165                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1166                 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1167                 /* Measurement period */
1168                 period = (u32)(1 << (data[0] & 0x0F));
1169                 if (period == 0) {
1170                         dev_dbg(&priv->i2c->dev,
1171                                 "%s(): period is 0\n", __func__);
1172                         return 0;
1173                 }
1174                 if (bit_error > (period * 64800)) {
1175                         dev_dbg(&priv->i2c->dev,
1176                                 "%s(): invalid bit_err 0x%x period 0x%x\n",
1177                                 __func__, bit_error, period);
1178                         return 0;
1179                 }
1180                 /*
1181                  * BER = bitError / (period * 64800)
1182                  *      = (bitError * 10^7) / (period * 64800)
1183                  *      = (bitError * 10^5) / (period * 648)
1184                  *      = (bitError * 12500) / (period * 81)
1185                  *      = (bitError * 10) * 1250 / (period * 81)
1186                  */
1187                 temp_q = div_u64_rem(12500ULL * bit_error,
1188                                         period * 81, &temp_r);
1189                 if (temp_r >= period * 40)
1190                         temp_q++;
1191                 result = temp_q;
1192         } else {
1193                 dev_dbg(&priv->i2c->dev,
1194                         "%s(): no data available\n", __func__);
1195         }
1196         return result;
1197 }
1198
1199 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, u32 *ber)
1200 {
1201         u8 data[4];
1202         u32 div, q, r;
1203         u32 bit_err, period_exp, n_ldpc;
1204
1205         *ber = 0;
1206         if (priv->state != STATE_ACTIVE_TC) {
1207                 dev_dbg(&priv->i2c->dev,
1208                         "%s(): invalid state %d\n", __func__, priv->state);
1209                 return -EINVAL;
1210         }
1211         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1212         cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1213         if (!(data[0] & 0x10)) {
1214                 dev_dbg(&priv->i2c->dev,
1215                         "%s(): no valid BER data\n", __func__);
1216                 return 0;
1217         }
1218         bit_err = ((u32)(data[0] & 0x0f) << 24) |
1219                 ((u32)data[1] << 16) |
1220                 ((u32)data[2] << 8) |
1221                 (u32)data[3];
1222         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1223         period_exp = data[0] & 0x0f;
1224         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1225         cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1226         n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1227         if (bit_err > ((1U << period_exp) * n_ldpc)) {
1228                 dev_dbg(&priv->i2c->dev,
1229                         "%s(): invalid BER value\n", __func__);
1230                 return -EINVAL;
1231         }
1232         if (period_exp >= 4) {
1233                 div = (1U << (period_exp - 4)) * (n_ldpc / 200);
1234                 q = div_u64_rem(3125ULL * bit_err, div, &r);
1235         } else {
1236                 div = (1U << period_exp) * (n_ldpc / 200);
1237                 q = div_u64_rem(50000ULL * bit_err, div, &r);
1238         }
1239         *ber = (r >= div / 2) ? q + 1 : q;
1240         return 0;
1241 }
1242
1243 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, u32 *ber)
1244 {
1245         u8 data[2];
1246         u32 div, q, r;
1247         u32 bit_err, period;
1248
1249         *ber = 0;
1250         if (priv->state != STATE_ACTIVE_TC) {
1251                 dev_dbg(&priv->i2c->dev,
1252                         "%s(): invalid state %d\n", __func__, priv->state);
1253                 return -EINVAL;
1254         }
1255         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1256         cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1257         if (!(data[0] & 0x01)) {
1258                 dev_dbg(&priv->i2c->dev,
1259                         "%s(): no valid BER data\n", __func__);
1260                 return 0;
1261         }
1262         cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1263         bit_err = ((u32)data[0] << 8) | (u32)data[1];
1264         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1265         period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1266         div = period / 128;
1267         q = div_u64_rem(78125ULL * bit_err, div, &r);
1268         *ber = (r >= div / 2) ? q + 1 : q;
1269         return 0;
1270 }
1271
1272 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1273 {
1274         u8 data[3];
1275         u32 res = 0, value;
1276         int min_index, max_index, index;
1277         static const struct cxd2841er_cnr_data *cn_data;
1278
1279         /* Set SLV-T Bank : 0xA1 */
1280         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1281         /*
1282          *  slave     Bank      Addr      Bit     Signal name
1283          * <SLV-T>    A1h       10h       [0]     ICPM_QUICKRDY
1284          * <SLV-T>    A1h       11h       [4:0]   ICPM_QUICKCNDT[12:8]
1285          * <SLV-T>    A1h       12h       [7:0]   ICPM_QUICKCNDT[7:0]
1286          */
1287         cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1288         if (data[0] & 0x01) {
1289                 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1290                 min_index = 0;
1291                 if (delsys == SYS_DVBS) {
1292                         cn_data = s_cn_data;
1293                         max_index = sizeof(s_cn_data) /
1294                                 sizeof(s_cn_data[0]) - 1;
1295                 } else {
1296                         cn_data = s2_cn_data;
1297                         max_index = sizeof(s2_cn_data) /
1298                                 sizeof(s2_cn_data[0]) - 1;
1299                 }
1300                 if (value >= cn_data[min_index].value) {
1301                         res = cn_data[min_index].cnr_x1000;
1302                         goto done;
1303                 }
1304                 if (value <= cn_data[max_index].value) {
1305                         res = cn_data[max_index].cnr_x1000;
1306                         goto done;
1307                 }
1308                 while ((max_index - min_index) > 1) {
1309                         index = (max_index + min_index) / 2;
1310                         if (value == cn_data[index].value) {
1311                                 res = cn_data[index].cnr_x1000;
1312                                 goto done;
1313                         } else if (value > cn_data[index].value)
1314                                 max_index = index;
1315                         else
1316                                 min_index = index;
1317                         if ((max_index - min_index) <= 1) {
1318                                 if (value == cn_data[max_index].value) {
1319                                         res = cn_data[max_index].cnr_x1000;
1320                                         goto done;
1321                                 } else {
1322                                         res = cn_data[min_index].cnr_x1000;
1323                                         goto done;
1324                                 }
1325                         }
1326                 }
1327         } else {
1328                 dev_dbg(&priv->i2c->dev,
1329                         "%s(): no data available\n", __func__);
1330         }
1331 done:
1332         return res;
1333 }
1334
1335 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1336 {
1337         u32 reg;
1338         u8 data[2];
1339
1340         *snr = 0;
1341         if (priv->state != STATE_ACTIVE_TC) {
1342                 dev_dbg(&priv->i2c->dev,
1343                         "%s(): invalid state %d\n", __func__, priv->state);
1344                 return -EINVAL;
1345         }
1346         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1347         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1348         reg = ((u32)data[0] << 8) | (u32)data[1];
1349         if (reg == 0) {
1350                 dev_dbg(&priv->i2c->dev,
1351                         "%s(): reg value out of range\n", __func__);
1352                 return 0;
1353         }
1354         if (reg > 4996)
1355                 reg = 4996;
1356         *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1357         return 0;
1358 }
1359
1360 int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1361 {
1362         u32 reg;
1363         u8 data[2];
1364
1365         *snr = 0;
1366         if (priv->state != STATE_ACTIVE_TC) {
1367                 dev_dbg(&priv->i2c->dev,
1368                         "%s(): invalid state %d\n", __func__, priv->state);
1369                 return -EINVAL;
1370         }
1371         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1372         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1373         reg = ((u32)data[0] << 8) | (u32)data[1];
1374         if (reg == 0) {
1375                 dev_dbg(&priv->i2c->dev,
1376                         "%s(): reg value out of range\n", __func__);
1377                 return 0;
1378         }
1379         if (reg > 10876)
1380                 reg = 10876;
1381         *snr = 10000 * ((intlog10(reg) -
1382                 intlog10(12600 - reg)) >> 24) + 32000;
1383         return 0;
1384 }
1385
1386 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1387                                         u8 delsys)
1388 {
1389         u8 data[2];
1390
1391         cxd2841er_write_reg(
1392                 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1393         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1394         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1395 }
1396
1397 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1398 {
1399         u8 data[2];
1400
1401         /* Set SLV-T Bank : 0xA0 */
1402         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1403         /*
1404          *  slave     Bank      Addr      Bit       Signal name
1405          * <SLV-T>    A0h       1Fh       [4:0]     IRFAGC_GAIN[12:8]
1406          * <SLV-T>    A0h       20h       [7:0]     IRFAGC_GAIN[7:0]
1407          */
1408         cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1409         return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1410 }
1411
1412 static int cxd2841er_read_ber(struct dvb_frontend *fe, u32 *ber)
1413 {
1414         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1415         struct cxd2841er_priv *priv = fe->demodulator_priv;
1416
1417         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1418         *ber = 0;
1419         switch (p->delivery_system) {
1420         case SYS_DVBS:
1421                 *ber = cxd2841er_mon_read_ber_s(priv);
1422                 break;
1423         case SYS_DVBS2:
1424                 *ber = cxd2841er_mon_read_ber_s2(priv);
1425                 break;
1426         case SYS_DVBT:
1427                 return cxd2841er_read_ber_t(priv, ber);
1428         case SYS_DVBT2:
1429                 return cxd2841er_read_ber_t2(priv, ber);
1430         default:
1431                 *ber = 0;
1432                 break;
1433         }
1434         return 0;
1435 }
1436
1437 static int cxd2841er_read_signal_strength(struct dvb_frontend *fe,
1438                                           u16 *strength)
1439 {
1440         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1441         struct cxd2841er_priv *priv = fe->demodulator_priv;
1442
1443         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1444         switch (p->delivery_system) {
1445         case SYS_DVBT:
1446         case SYS_DVBT2:
1447                 *strength = 65535 - cxd2841er_read_agc_gain_t_t2(
1448                         priv, p->delivery_system);
1449                 break;
1450         case SYS_DVBS:
1451         case SYS_DVBS2:
1452                 *strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1453                 break;
1454         default:
1455                 *strength = 0;
1456                 break;
1457         }
1458         return 0;
1459 }
1460
1461 static int cxd2841er_read_snr(struct dvb_frontend *fe, u16 *snr)
1462 {
1463         u32 tmp = 0;
1464         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1465         struct cxd2841er_priv *priv = fe->demodulator_priv;
1466
1467         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1468         switch (p->delivery_system) {
1469         case SYS_DVBT:
1470                 cxd2841er_read_snr_t(priv, &tmp);
1471                 break;
1472         case SYS_DVBT2:
1473                 cxd2841er_read_snr_t2(priv, &tmp);
1474                 break;
1475         case SYS_DVBS:
1476         case SYS_DVBS2:
1477                 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1478                 break;
1479         default:
1480                 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1481                         __func__, p->delivery_system);
1482                 break;
1483         }
1484         *snr = tmp & 0xffff;
1485         return 0;
1486 }
1487
1488 static int cxd2841er_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1489 {
1490         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1491         struct cxd2841er_priv *priv = fe->demodulator_priv;
1492
1493         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1494         switch (p->delivery_system) {
1495         case SYS_DVBT:
1496                 cxd2841er_read_packet_errors_t(priv, ucblocks);
1497                 break;
1498         case SYS_DVBT2:
1499                 cxd2841er_read_packet_errors_t2(priv, ucblocks);
1500                 break;
1501         default:
1502                 *ucblocks = 0;
1503                 break;
1504         }
1505         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1506         return 0;
1507 }
1508
1509 static int cxd2841er_dvbt2_set_profile(
1510         struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1511 {
1512         u8 tune_mode;
1513         u8 seq_not2d_time;
1514
1515         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1516         switch (profile) {
1517         case DVBT2_PROFILE_BASE:
1518                 tune_mode = 0x01;
1519                 seq_not2d_time = 12;
1520                 break;
1521         case DVBT2_PROFILE_LITE:
1522                 tune_mode = 0x05;
1523                 seq_not2d_time = 40;
1524                 break;
1525         case DVBT2_PROFILE_ANY:
1526                 tune_mode = 0x00;
1527                 seq_not2d_time = 40;
1528                 break;
1529         default:
1530                 return -EINVAL;
1531         }
1532         /* Set SLV-T Bank : 0x2E */
1533         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1534         /* Set profile and tune mode */
1535         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1536         /* Set SLV-T Bank : 0x2B */
1537         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1538         /* Set early unlock detection time */
1539         cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1540         return 0;
1541 }
1542
1543 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1544                                           u8 is_auto, u8 plp_id)
1545 {
1546         if (is_auto) {
1547                 dev_dbg(&priv->i2c->dev,
1548                         "%s() using auto PLP selection\n", __func__);
1549         } else {
1550                 dev_dbg(&priv->i2c->dev,
1551                         "%s() using manual PLP selection, ID %d\n",
1552                         __func__, plp_id);
1553         }
1554         /* Set SLV-T Bank : 0x23 */
1555         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1556         if (!is_auto) {
1557                 /* Manual PLP selection mode. Set the data PLP Id. */
1558                 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1559         }
1560         /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1561         cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1562         return 0;
1563 }
1564
1565 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1566                                                 u32 bandwidth)
1567 {
1568         u32 iffreq;
1569         u8 b20_9f[5];
1570         u8 b10_a6[14];
1571         u8 b10_b6[3];
1572         u8 b10_d7;
1573
1574         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1575         switch (bandwidth) {
1576         case 8000000:
1577                 /* bank 0x20, reg 0x9f */
1578                 b20_9f[0] = 0x11;
1579                 b20_9f[1] = 0xf0;
1580                 b20_9f[2] = 0x00;
1581                 b20_9f[3] = 0x00;
1582                 b20_9f[4] = 0x00;
1583                 /* bank 0x10, reg 0xa6 */
1584                 b10_a6[0] = 0x26;
1585                 b10_a6[1] = 0xaf;
1586                 b10_a6[2] = 0x06;
1587                 b10_a6[3] = 0xcd;
1588                 b10_a6[4] = 0x13;
1589                 b10_a6[5] = 0xbb;
1590                 b10_a6[6] = 0x28;
1591                 b10_a6[7] = 0xba;
1592                 b10_a6[8] = 0x23;
1593                 b10_a6[9] = 0xa9;
1594                 b10_a6[10] = 0x1f;
1595                 b10_a6[11] = 0xa8;
1596                 b10_a6[12] = 0x2c;
1597                 b10_a6[13] = 0xc8;
1598                 iffreq = MAKE_IFFREQ_CONFIG(4.80);
1599                 b10_d7 = 0x00;
1600                 break;
1601         case 7000000:
1602                 /* bank 0x20, reg 0x9f */
1603                 b20_9f[0] = 0x14;
1604                 b20_9f[1] = 0x80;
1605                 b20_9f[2] = 0x00;
1606                 b20_9f[3] = 0x00;
1607                 b20_9f[4] = 0x00;
1608                 /* bank 0x10, reg 0xa6 */
1609                 b10_a6[0] = 0x2C;
1610                 b10_a6[1] = 0xBD;
1611                 b10_a6[2] = 0x02;
1612                 b10_a6[3] = 0xCF;
1613                 b10_a6[4] = 0x04;
1614                 b10_a6[5] = 0xF8;
1615                 b10_a6[6] = 0x23;
1616                 b10_a6[7] = 0xA6;
1617                 b10_a6[8] = 0x29;
1618                 b10_a6[9] = 0xB0;
1619                 b10_a6[10] = 0x26;
1620                 b10_a6[11] = 0xA9;
1621                 b10_a6[12] = 0x21;
1622                 b10_a6[13] = 0xA5;
1623                 iffreq = MAKE_IFFREQ_CONFIG(4.2);
1624                 b10_d7 = 0x02;
1625                 break;
1626         case 6000000:
1627                 /* bank 0x20, reg 0x9f */
1628                 b20_9f[0] = 0x17;
1629                 b20_9f[1] = 0xEA;
1630                 b20_9f[2] = 0xAA;
1631                 b20_9f[3] = 0xAA;
1632                 b20_9f[4] = 0xAA;
1633                 /* bank 0x10, reg 0xa6 */
1634                 b10_a6[0] = 0x27;
1635                 b10_a6[1] = 0xA7;
1636                 b10_a6[2] = 0x28;
1637                 b10_a6[3] = 0xB3;
1638                 b10_a6[4] = 0x02;
1639                 b10_a6[5] = 0xF0;
1640                 b10_a6[6] = 0x01;
1641                 b10_a6[7] = 0xE8;
1642                 b10_a6[8] = 0x00;
1643                 b10_a6[9] = 0xCF;
1644                 b10_a6[10] = 0x00;
1645                 b10_a6[11] = 0xE6;
1646                 b10_a6[12] = 0x23;
1647                 b10_a6[13] = 0xA4;
1648                 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1649                 b10_d7 = 0x04;
1650                 break;
1651         case 5000000:
1652                 /* bank 0x20, reg 0x9f */
1653                 b20_9f[0] = 0x1C;
1654                 b20_9f[1] = 0xB3;
1655                 b20_9f[2] = 0x33;
1656                 b20_9f[3] = 0x33;
1657                 b20_9f[4] = 0x33;
1658                 /* bank 0x10, reg 0xa6 */
1659                 b10_a6[0] = 0x27;
1660                 b10_a6[1] = 0xA7;
1661                 b10_a6[2] = 0x28;
1662                 b10_a6[3] = 0xB3;
1663                 b10_a6[4] = 0x02;
1664                 b10_a6[5] = 0xF0;
1665                 b10_a6[6] = 0x01;
1666                 b10_a6[7] = 0xE8;
1667                 b10_a6[8] = 0x00;
1668                 b10_a6[9] = 0xCF;
1669                 b10_a6[10] = 0x00;
1670                 b10_a6[11] = 0xE6;
1671                 b10_a6[12] = 0x23;
1672                 b10_a6[13] = 0xA4;
1673                 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1674                 b10_d7 = 0x06;
1675                 break;
1676         case 1712000:
1677                 /* bank 0x20, reg 0x9f */
1678                 b20_9f[0] = 0x58;
1679                 b20_9f[1] = 0xE2;
1680                 b20_9f[2] = 0xAF;
1681                 b20_9f[3] = 0xE0;
1682                 b20_9f[4] = 0xBC;
1683                 /* bank 0x10, reg 0xa6 */
1684                 b10_a6[0] = 0x25;
1685                 b10_a6[1] = 0xA0;
1686                 b10_a6[2] = 0x36;
1687                 b10_a6[3] = 0x8D;
1688                 b10_a6[4] = 0x2E;
1689                 b10_a6[5] = 0x94;
1690                 b10_a6[6] = 0x28;
1691                 b10_a6[7] = 0x9B;
1692                 b10_a6[8] = 0x32;
1693                 b10_a6[9] = 0x90;
1694                 b10_a6[10] = 0x2C;
1695                 b10_a6[11] = 0x9D;
1696                 b10_a6[12] = 0x29;
1697                 b10_a6[13] = 0x99;
1698                 iffreq = MAKE_IFFREQ_CONFIG(3.5);
1699                 b10_d7 = 0x03;
1700                 break;
1701         default:
1702                 return -EINVAL;
1703         }
1704         /* Set SLV-T Bank : 0x20 */
1705         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x20);
1706         cxd2841er_write_regs(priv, I2C_SLVT, 0x9f, b20_9f, sizeof(b20_9f));
1707         /* Set SLV-T Bank : 0x27 */
1708         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1709         cxd2841er_set_reg_bits(
1710                 priv, I2C_SLVT, 0x7a,
1711                 (bandwidth == 1712000 ? 0x03 : 0x00), 0x0f);
1712         /* Set SLV-T Bank : 0x10 */
1713         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1714         /* Group delay equaliser sett. for ASCOT2E */
1715         cxd2841er_write_regs(priv, I2C_SLVT, 0xa6, b10_a6, sizeof(b10_a6));
1716         /* <IF freq setting> */
1717         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1718         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1719         b10_b6[2] = (u8)(iffreq & 0xff);
1720         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1721         /* System bandwidth setting */
1722         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, b10_d7, 0x07);
1723         return 0;
1724 }
1725
1726 static int cxd2841er_sleep_tc_to_active_t_band(
1727                 struct cxd2841er_priv *priv, u32 bandwidth)
1728 {
1729         u8 b13_9c[2] = { 0x01, 0x14 };
1730         u8 bw8mhz_b10_9f[] = { 0x11, 0xF0, 0x00, 0x00, 0x00 };
1731         u8 bw8mhz_b10_a6[] = { 0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB,
1732                         0x28, 0xBA, 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8 };
1733         u8 bw8mhz_b10_d9[] = { 0x01, 0xE0 };
1734         u8 bw8mhz_b17_38[] = { 0x01, 0x02 };
1735         u8 bw7mhz_b10_9f[] = { 0x14, 0x80, 0x00, 0x00, 0x00 };
1736         u8 bw7mhz_b10_a6[] = { 0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8,
1737                         0x23, 0xA6, 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5 };
1738         u8 bw7mhz_b10_d9[] = { 0x12, 0xF8 };
1739         u8 bw7mhz_b17_38[] = { 0x00, 0x03 };
1740         u8 bw6mhz_b10_9f[] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA };
1741         u8 bw6mhz_b10_a6[] = { 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0,
1742                         0x01, 0xE8, 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
1743         u8 bw6mhz_b10_d9[] = { 0x1F, 0xDC };
1744         u8 bw6mhz_b17_38[] = { 0x00, 0x03 };
1745         u8 bw5mhz_b10_9f[] = { 0x1C, 0xB3, 0x33, 0x33, 0x33 };
1746         u8 bw5mhz_b10_a6[] = { 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0,
1747                         0x01, 0xE8, 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
1748         u8 bw5mhz_b10_d9[] = { 0x26, 0x3C };
1749         u8 bw5mhz_b17_38[] = { 0x00, 0x03 };
1750         u8 b10_b6[3];
1751         u8 d7val;
1752         u32 iffreq;
1753         u8 *b10_9f;
1754         u8 *b10_a6;
1755         u8 *b10_d9;
1756         u8 *b17_38;
1757
1758         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1759         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
1760         /* Echo performance optimization setting */
1761         cxd2841er_write_regs(priv, I2C_SLVT, 0x9c, b13_9c, sizeof(b13_9c));
1762         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1763
1764         switch (bandwidth) {
1765         case 8000000:
1766                 b10_9f = bw8mhz_b10_9f;
1767                 b10_a6 = bw8mhz_b10_a6;
1768                 b10_d9 = bw8mhz_b10_d9;
1769                 b17_38 = bw8mhz_b17_38;
1770                 d7val = 0;
1771                 iffreq = MAKE_IFFREQ_CONFIG(4.80);
1772                 break;
1773         case 7000000:
1774                 b10_9f = bw7mhz_b10_9f;
1775                 b10_a6 = bw7mhz_b10_a6;
1776                 b10_d9 = bw7mhz_b10_d9;
1777                 b17_38 = bw7mhz_b17_38;
1778                 d7val = 2;
1779                 iffreq = MAKE_IFFREQ_CONFIG(4.20);
1780                 break;
1781         case 6000000:
1782                 b10_9f = bw6mhz_b10_9f;
1783                 b10_a6 = bw6mhz_b10_a6;
1784                 b10_d9 = bw6mhz_b10_d9;
1785                 b17_38 = bw6mhz_b17_38;
1786                 d7val = 4;
1787                 iffreq = MAKE_IFFREQ_CONFIG(3.60);
1788                 break;
1789         case 5000000:
1790                 b10_9f = bw5mhz_b10_9f;
1791                 b10_a6 = bw5mhz_b10_a6;
1792                 b10_d9 = bw5mhz_b10_d9;
1793                 b17_38 = bw5mhz_b17_38;
1794                 d7val = 6;
1795                 iffreq = MAKE_IFFREQ_CONFIG(3.60);
1796                 break;
1797         default:
1798                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1799                         __func__, bandwidth);
1800                 return -EINVAL;
1801         }
1802         /* <IF freq setting> */
1803         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1804         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1805         b10_b6[2] = (u8)(iffreq & 0xff);
1806         cxd2841er_write_regs(
1807                 priv, I2C_SLVT, 0x9f, b10_9f, sizeof(bw8mhz_b10_9f));
1808         cxd2841er_write_regs(
1809                 priv, I2C_SLVT, 0xa6, b10_a6, sizeof(bw8mhz_b10_a6));
1810         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1811         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, d7val, 0x7);
1812         cxd2841er_write_regs(
1813                 priv, I2C_SLVT, 0xd9, b10_d9, sizeof(bw8mhz_b10_d9));
1814         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
1815         cxd2841er_write_regs(
1816                 priv, I2C_SLVT, 0x38, b17_38, sizeof(bw8mhz_b17_38));
1817         return 0;
1818 }
1819
1820 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
1821                                                u32 bandwidth)
1822 {
1823         u8 bw7_8mhz_b10_a6[] = {
1824                 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
1825                 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
1826         u8 bw6mhz_b10_a6[] = {
1827                 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1828                 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
1829         u8 b10_b6[3];
1830         u32 iffreq;
1831
1832         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1833         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1834         switch (bandwidth) {
1835         case 8000000:
1836         case 7000000:
1837                 cxd2841er_write_regs(
1838                         priv, I2C_SLVT, 0xa6,
1839                         bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
1840                 iffreq = MAKE_IFFREQ_CONFIG(4.9);
1841                 break;
1842         case 6000000:
1843                 cxd2841er_write_regs(
1844                         priv, I2C_SLVT, 0xa6,
1845                         bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
1846                 iffreq = MAKE_IFFREQ_CONFIG(3.7);
1847                 break;
1848         default:
1849                 dev_dbg(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
1850                         __func__, bandwidth);
1851                 return -EINVAL;
1852         }
1853         /* <IF freq setting> */
1854         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1855         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1856         b10_b6[2] = (u8)(iffreq & 0xff);
1857         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1858         /* Set SLV-T Bank : 0x11 */
1859         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
1860         switch (bandwidth) {
1861         case 8000000:
1862         case 7000000:
1863                 cxd2841er_set_reg_bits(
1864                         priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
1865                 break;
1866         case 6000000:
1867                 cxd2841er_set_reg_bits(
1868                         priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
1869                 break;
1870         }
1871         /* Set SLV-T Bank : 0x40 */
1872         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1873         switch (bandwidth) {
1874         case 8000000:
1875                 cxd2841er_set_reg_bits(
1876                         priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
1877                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x3e);
1878                 break;
1879         case 7000000:
1880                 cxd2841er_set_reg_bits(
1881                         priv, I2C_SLVT, 0x26, 0x09, 0x0f);
1882                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0xd6);
1883                 break;
1884         case 6000000:
1885                 cxd2841er_set_reg_bits(
1886                         priv, I2C_SLVT, 0x26, 0x08, 0x0f);
1887                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x6e);
1888                 break;
1889         }
1890         return 0;
1891 }
1892
1893 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
1894                                           u32 bandwidth)
1895 {
1896         u8 data[2] = { 0x09, 0x54 };
1897
1898         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1899         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
1900         /* Set SLV-X Bank : 0x00 */
1901         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
1902         /* Set demod mode */
1903         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
1904         /* Set SLV-T Bank : 0x00 */
1905         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1906         /* Enable demod clock */
1907         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
1908         /* Disable RF level monitor */
1909         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
1910         /* Enable ADC clock */
1911         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
1912         /* Enable ADC 1 */
1913         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
1914         /* xtal freq 20.5MHz */
1915         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
1916         /* Enable ADC 4 */
1917         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
1918         /* Set SLV-T Bank : 0x10 */
1919         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1920         /* IFAGC gain settings */
1921         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
1922         /* Set SLV-T Bank : 0x11 */
1923         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
1924         /* BBAGC TARGET level setting */
1925         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
1926         /* Set SLV-T Bank : 0x10 */
1927         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1928         /* ASCOT setting ON */
1929         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
1930         /* Set SLV-T Bank : 0x18 */
1931         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
1932         /* Pre-RS BER moniter setting */
1933         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
1934         /* FEC Auto Recovery setting */
1935         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
1936         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
1937         /* Set SLV-T Bank : 0x00 */
1938         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1939         /* TSIF setting */
1940         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
1941         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
1942         cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
1943         /* Set SLV-T Bank : 0x00 */
1944         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1945         /* Disable HiZ Setting 1 */
1946         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
1947         /* Disable HiZ Setting 2 */
1948         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
1949         priv->state = STATE_ACTIVE_TC;
1950         return 0;
1951 }
1952
1953 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
1954                                            u32 bandwidth)
1955 {
1956         u8 data[2] = { 0x09, 0x54 };
1957
1958         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1959         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
1960         /* Set SLV-X Bank : 0x00 */
1961         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
1962         /* Set demod mode */
1963         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
1964         /* Set SLV-T Bank : 0x00 */
1965         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1966         /* Enable demod clock */
1967         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
1968         /* Disable RF level monitor */
1969         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
1970         /* Enable ADC clock */
1971         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
1972         /* Enable ADC 1 */
1973         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
1974         /* xtal freq 20.5MHz */
1975         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
1976         /* Enable ADC 4 */
1977         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
1978         /* Set SLV-T Bank : 0x10 */
1979         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1980         /* IFAGC gain settings */
1981         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
1982         /* Set SLV-T Bank : 0x11 */
1983         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
1984         /* BBAGC TARGET level setting */
1985         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
1986         /* Set SLV-T Bank : 0x10 */
1987         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1988         /* ASCOT setting ON */
1989         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
1990         /* Set SLV-T Bank : 0x20 */
1991         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1992         /* Acquisition optimization setting */
1993         cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
1994         /* Set SLV-T Bank : 0x2b */
1995         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1996         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
1997         /* Set SLV-T Bank : 0x00 */
1998         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1999         /* TSIF setting */
2000         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2001         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2002         /* DVB-T2 initial setting */
2003         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2004         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2005         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2006         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2007         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2008         /* Set SLV-T Bank : 0x2a */
2009         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2010         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2011         /* Set SLV-T Bank : 0x2b */
2012         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2013         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2014
2015         cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2016
2017         /* Set SLV-T Bank : 0x00 */
2018         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2019         /* Disable HiZ Setting 1 */
2020         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2021         /* Disable HiZ Setting 2 */
2022         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2023         priv->state = STATE_ACTIVE_TC;
2024         return 0;
2025 }
2026
2027 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2028                                           u32 bandwidth)
2029 {
2030         u8 data[2] = { 0x09, 0x54 };
2031
2032         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2033         cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2034         /* Set SLV-X Bank : 0x00 */
2035         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2036         /* Set demod mode */
2037         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2038         /* Set SLV-T Bank : 0x00 */
2039         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2040         /* Enable demod clock */
2041         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2042         /* Disable RF level monitor */
2043         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2044         /* Enable ADC clock */
2045         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2046         /* Enable ADC 1 */
2047         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2048         /* xtal freq 20.5MHz */
2049         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2050         /* Enable ADC 4 */
2051         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2052         /* Set SLV-T Bank : 0x10 */
2053         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2054         /* IFAGC gain settings */
2055         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2056         /* Set SLV-T Bank : 0x11 */
2057         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2058         /* BBAGC TARGET level setting */
2059         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2060         /* Set SLV-T Bank : 0x10 */
2061         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2062         /* ASCOT setting ON */
2063         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2064         /* Set SLV-T Bank : 0x40 */
2065         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2066         /* Demod setting */
2067         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2068         /* Set SLV-T Bank : 0x00 */
2069         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2070         /* TSIF setting */
2071         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2072         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2073
2074         cxd2841er_sleep_tc_to_active_c_band(priv, 8000000);
2075         /* Set SLV-T Bank : 0x00 */
2076         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2077         /* Disable HiZ Setting 1 */
2078         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2079         /* Disable HiZ Setting 2 */
2080         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2081         priv->state = STATE_ACTIVE_TC;
2082         return 0;
2083 }
2084
2085 static int cxd2841er_get_frontend(struct dvb_frontend *fe)
2086 {
2087         enum fe_status status = 0;
2088         u16 strength = 0, snr = 0;
2089         u32 errors = 0, ber = 0;
2090         struct cxd2841er_priv *priv = fe->demodulator_priv;
2091         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2092
2093         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2094         if (priv->state == STATE_ACTIVE_S)
2095                 cxd2841er_read_status_s(fe, &status);
2096         else if (priv->state == STATE_ACTIVE_TC)
2097                 cxd2841er_read_status_tc(fe, &status);
2098
2099         if (status & FE_HAS_LOCK) {
2100                 cxd2841er_read_signal_strength(fe, &strength);
2101                 p->strength.len = 1;
2102                 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2103                 p->strength.stat[0].uvalue = strength;
2104                 cxd2841er_read_snr(fe, &snr);
2105                 p->cnr.len = 1;
2106                 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2107                 p->cnr.stat[0].svalue = snr;
2108                 cxd2841er_read_ucblocks(fe, &errors);
2109                 p->block_error.len = 1;
2110                 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2111                 p->block_error.stat[0].uvalue = errors;
2112                 cxd2841er_read_ber(fe, &ber);
2113                 p->post_bit_error.len = 1;
2114                 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
2115                 p->post_bit_error.stat[0].uvalue = ber;
2116         } else {
2117                 p->strength.len = 1;
2118                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2119                 p->cnr.len = 1;
2120                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2121                 p->block_error.len = 1;
2122                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2123                 p->post_bit_error.len = 1;
2124                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2125         }
2126         return 0;
2127 }
2128
2129 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2130 {
2131         int ret = 0, i, timeout, carr_offset;
2132         enum fe_status status;
2133         struct cxd2841er_priv *priv = fe->demodulator_priv;
2134         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2135         u32 symbol_rate = p->symbol_rate/1000;
2136
2137         dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d\n",
2138                 __func__,
2139                 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
2140                  p->frequency, symbol_rate);
2141         switch (priv->state) {
2142         case STATE_SLEEP_S:
2143                 ret = cxd2841er_sleep_s_to_active_s(
2144                         priv, p->delivery_system, symbol_rate);
2145                 break;
2146         case STATE_ACTIVE_S:
2147                 ret = cxd2841er_retune_active(priv, p);
2148                 break;
2149         default:
2150                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2151                         __func__, priv->state);
2152                 ret = -EINVAL;
2153                 goto done;
2154         }
2155         if (ret) {
2156                 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
2157                 goto done;
2158         }
2159         if (fe->ops.i2c_gate_ctrl)
2160                 fe->ops.i2c_gate_ctrl(fe, 1);
2161         if (fe->ops.tuner_ops.set_params)
2162                 fe->ops.tuner_ops.set_params(fe);
2163         if (fe->ops.i2c_gate_ctrl)
2164                 fe->ops.i2c_gate_ctrl(fe, 0);
2165         cxd2841er_tune_done(priv);
2166         timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
2167         for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
2168                 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
2169                         (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
2170                 cxd2841er_read_status_s(fe, &status);
2171                 if (status & FE_HAS_LOCK)
2172                         break;
2173         }
2174         if (status & FE_HAS_LOCK) {
2175                 if (cxd2841er_get_carrier_offset_s_s2(
2176                                 priv, &carr_offset)) {
2177                         ret = -EINVAL;
2178                         goto done;
2179                 }
2180                 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
2181                         __func__, carr_offset);
2182         }
2183 done:
2184         return ret;
2185 }
2186
2187 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
2188 {
2189         int ret = 0, timeout;
2190         enum fe_status status;
2191         struct cxd2841er_priv *priv = fe->demodulator_priv;
2192         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2193
2194         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2195         if (p->delivery_system == SYS_DVBT) {
2196                 priv->system = SYS_DVBT;
2197                 switch (priv->state) {
2198                 case STATE_SLEEP_TC:
2199                         ret = cxd2841er_sleep_tc_to_active_t(
2200                                 priv, p->bandwidth_hz);
2201                         break;
2202                 case STATE_ACTIVE_TC:
2203                         ret = cxd2841er_retune_active(priv, p);
2204                         break;
2205                 default:
2206                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2207                                 __func__, priv->state);
2208                         ret = -EINVAL;
2209                 }
2210         } else if (p->delivery_system == SYS_DVBT2) {
2211                 priv->system = SYS_DVBT2;
2212                 cxd2841er_dvbt2_set_plp_config(priv,
2213                         (int)(p->stream_id > 255), p->stream_id);
2214                 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
2215                 switch (priv->state) {
2216                 case STATE_SLEEP_TC:
2217                         ret = cxd2841er_sleep_tc_to_active_t2(priv,
2218                                 p->bandwidth_hz);
2219                         break;
2220                 case STATE_ACTIVE_TC:
2221                         ret = cxd2841er_retune_active(priv, p);
2222                         break;
2223                 default:
2224                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2225                                 __func__, priv->state);
2226                         ret = -EINVAL;
2227                 }
2228         } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
2229                         p->delivery_system == SYS_DVBC_ANNEX_C) {
2230                 priv->system = SYS_DVBC_ANNEX_A;
2231                 switch (priv->state) {
2232                 case STATE_SLEEP_TC:
2233                         ret = cxd2841er_sleep_tc_to_active_c(
2234                                 priv, p->bandwidth_hz);
2235                         break;
2236                 case STATE_ACTIVE_TC:
2237                         ret = cxd2841er_retune_active(priv, p);
2238                         break;
2239                 default:
2240                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2241                                 __func__, priv->state);
2242                         ret = -EINVAL;
2243                 }
2244         } else {
2245                 dev_dbg(&priv->i2c->dev,
2246                         "%s(): invalid delivery system %d\n",
2247                         __func__, p->delivery_system);
2248                 ret = -EINVAL;
2249         }
2250         if (ret)
2251                 goto done;
2252         if (fe->ops.i2c_gate_ctrl)
2253                 fe->ops.i2c_gate_ctrl(fe, 1);
2254         if (fe->ops.tuner_ops.set_params)
2255                 fe->ops.tuner_ops.set_params(fe);
2256         if (fe->ops.i2c_gate_ctrl)
2257                 fe->ops.i2c_gate_ctrl(fe, 0);
2258         cxd2841er_tune_done(priv);
2259         timeout = 2500;
2260         while (timeout > 0) {
2261                 ret = cxd2841er_read_status_tc(fe, &status);
2262                 if (ret)
2263                         goto done;
2264                 if (status & FE_HAS_LOCK)
2265                         break;
2266                 msleep(20);
2267                 timeout -= 20;
2268         }
2269         if (timeout < 0)
2270                 dev_dbg(&priv->i2c->dev,
2271                         "%s(): LOCK wait timeout\n", __func__);
2272 done:
2273         return ret;
2274 }
2275
2276 static int cxd2841er_tune_s(struct dvb_frontend *fe,
2277                             bool re_tune,
2278                             unsigned int mode_flags,
2279                             unsigned int *delay,
2280                             enum fe_status *status)
2281 {
2282         int ret, carrier_offset;
2283         struct cxd2841er_priv *priv = fe->demodulator_priv;
2284         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2285
2286         dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
2287         if (re_tune) {
2288                 ret = cxd2841er_set_frontend_s(fe);
2289                 if (ret)
2290                         return ret;
2291                 cxd2841er_read_status_s(fe, status);
2292                 if (*status & FE_HAS_LOCK) {
2293                         if (cxd2841er_get_carrier_offset_s_s2(
2294                                         priv, &carrier_offset))
2295                                 return -EINVAL;
2296                         p->frequency += carrier_offset;
2297                         ret = cxd2841er_set_frontend_s(fe);
2298                         if (ret)
2299                                 return ret;
2300                 }
2301         }
2302         *delay = HZ / 5;
2303         return cxd2841er_read_status_s(fe, status);
2304 }
2305
2306 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
2307                              bool re_tune,
2308                              unsigned int mode_flags,
2309                              unsigned int *delay,
2310                              enum fe_status *status)
2311 {
2312         int ret, carrier_offset;
2313         struct cxd2841er_priv *priv = fe->demodulator_priv;
2314         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2315
2316         dev_dbg(&priv->i2c->dev, "%s(): re_tune %d\n", __func__, re_tune);
2317         if (re_tune) {
2318                 ret = cxd2841er_set_frontend_tc(fe);
2319                 if (ret)
2320                         return ret;
2321                 cxd2841er_read_status_tc(fe, status);
2322                 if (*status & FE_HAS_LOCK) {
2323                         switch (priv->system) {
2324                         case SYS_DVBT:
2325                         case SYS_DVBT2:
2326                                 ret = cxd2841er_get_carrier_offset_t2(
2327                                         priv, p->bandwidth_hz,
2328                                         &carrier_offset);
2329                                 break;
2330                         case SYS_DVBC_ANNEX_A:
2331                                 ret = cxd2841er_get_carrier_offset_c(
2332                                         priv, &carrier_offset);
2333                                 break;
2334                         default:
2335                                 dev_dbg(&priv->i2c->dev,
2336                                         "%s(): invalid delivery system %d\n",
2337                                         __func__, priv->system);
2338                                 return -EINVAL;
2339                         }
2340                         if (ret)
2341                                 return ret;
2342                         dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
2343                                 __func__, carrier_offset);
2344                         p->frequency += carrier_offset;
2345                         ret = cxd2841er_set_frontend_tc(fe);
2346                         if (ret)
2347                                 return ret;
2348                 }
2349         }
2350         *delay = HZ / 5;
2351         return cxd2841er_read_status_tc(fe, status);
2352 }
2353
2354 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
2355 {
2356         struct cxd2841er_priv *priv = fe->demodulator_priv;
2357
2358         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2359         cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
2360         cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
2361         return 0;
2362 }
2363
2364 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
2365 {
2366         struct cxd2841er_priv *priv = fe->demodulator_priv;
2367
2368         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2369         if (priv->state == STATE_ACTIVE_TC) {
2370                 switch (priv->system) {
2371                 case SYS_DVBT:
2372                         cxd2841er_active_t_to_sleep_tc(priv);
2373                         break;
2374                 case SYS_DVBT2:
2375                         cxd2841er_active_t2_to_sleep_tc(priv);
2376                         break;
2377                 case SYS_DVBC_ANNEX_A:
2378                         cxd2841er_active_c_to_sleep_tc(priv);
2379                         break;
2380                 default:
2381                         dev_warn(&priv->i2c->dev,
2382                                 "%s(): unknown delivery system %d\n",
2383                                 __func__, priv->system);
2384                 }
2385         }
2386         if (priv->state != STATE_SLEEP_TC) {
2387                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
2388                         __func__, priv->state);
2389                 return -EINVAL;
2390         }
2391         cxd2841er_sleep_tc_to_shutdown(priv);
2392         return 0;
2393 }
2394
2395 static int cxd2841er_send_burst(struct dvb_frontend *fe,
2396                                 enum fe_sec_mini_cmd burst)
2397 {
2398         u8 data;
2399         struct cxd2841er_priv *priv  = fe->demodulator_priv;
2400
2401         dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
2402                 (burst == SEC_MINI_A ? "A" : "B"));
2403         if (priv->state != STATE_SLEEP_S &&
2404                         priv->state != STATE_ACTIVE_S) {
2405                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
2406                         __func__, priv->state);
2407                 return -EINVAL;
2408         }
2409         data = (burst == SEC_MINI_A ? 0 : 1);
2410         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
2411         cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
2412         cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
2413         return 0;
2414 }
2415
2416 static int cxd2841er_set_tone(struct dvb_frontend *fe,
2417                               enum fe_sec_tone_mode tone)
2418 {
2419         u8 data;
2420         struct cxd2841er_priv *priv  = fe->demodulator_priv;
2421
2422         dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
2423                 (tone == SEC_TONE_ON ? "On" : "Off"));
2424         if (priv->state != STATE_SLEEP_S &&
2425                         priv->state != STATE_ACTIVE_S) {
2426                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
2427                         __func__, priv->state);
2428                 return -EINVAL;
2429         }
2430         data = (tone == SEC_TONE_ON ? 1 : 0);
2431         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
2432         cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
2433         return 0;
2434 }
2435
2436 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
2437                                      struct dvb_diseqc_master_cmd *cmd)
2438 {
2439         int i;
2440         u8 data[12];
2441         struct cxd2841er_priv *priv  = fe->demodulator_priv;
2442
2443         if (priv->state != STATE_SLEEP_S &&
2444                         priv->state != STATE_ACTIVE_S) {
2445                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
2446                         __func__, priv->state);
2447                 return -EINVAL;
2448         }
2449         dev_dbg(&priv->i2c->dev,
2450                 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
2451         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
2452         /* DiDEqC enable */
2453         cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
2454         /* cmd1 length & data */
2455         cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
2456         memset(data, 0, sizeof(data));
2457         for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
2458                 data[i] = cmd->msg[i];
2459         cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
2460         /* repeat count for cmd1 */
2461         cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
2462         /* repeat count for cmd2: always 0 */
2463         cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
2464         /* start transmit */
2465         cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
2466         /* wait for 1 sec timeout */
2467         for (i = 0; i < 50; i++) {
2468                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
2469                 if (!data[0]) {
2470                         dev_dbg(&priv->i2c->dev,
2471                                 "%s(): DiSEqC cmd has been sent\n", __func__);
2472                         return 0;
2473                 }
2474                 msleep(20);
2475         }
2476         dev_dbg(&priv->i2c->dev,
2477                 "%s(): DiSEqC cmd transmit timeout\n", __func__);
2478         return -ETIMEDOUT;
2479 }
2480
2481 static void cxd2841er_release(struct dvb_frontend *fe)
2482 {
2483         struct cxd2841er_priv *priv  = fe->demodulator_priv;
2484
2485         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2486         kfree(priv);
2487 }
2488
2489 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2490 {
2491         struct cxd2841er_priv *priv = fe->demodulator_priv;
2492
2493         dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
2494         cxd2841er_set_reg_bits(
2495                 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
2496         return 0;
2497 }
2498
2499 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
2500 {
2501         struct cxd2841er_priv *priv = fe->demodulator_priv;
2502
2503         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2504         return DVBFE_ALGO_HW;
2505 }
2506
2507 static int cxd2841er_init_s(struct dvb_frontend *fe)
2508 {
2509         struct cxd2841er_priv *priv = fe->demodulator_priv;
2510
2511         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2512         cxd2841er_shutdown_to_sleep_s(priv);
2513         /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
2514         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
2515         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
2516         return 0;
2517 }
2518
2519 static int cxd2841er_init_tc(struct dvb_frontend *fe)
2520 {
2521         struct cxd2841er_priv *priv = fe->demodulator_priv;
2522
2523         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2524         cxd2841er_shutdown_to_sleep_tc(priv);
2525         /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
2526         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2527         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
2528         /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
2529         cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
2530         /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
2531         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2532         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
2533         return 0;
2534 }
2535
2536 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
2537 static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops;
2538 static struct dvb_frontend_ops cxd2841er_dvbc_ops;
2539
2540 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
2541                                              struct i2c_adapter *i2c,
2542                                              u8 system)
2543 {
2544         u8 chip_id = 0;
2545         const char *type;
2546         struct cxd2841er_priv *priv = NULL;
2547
2548         /* allocate memory for the internal state */
2549         priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
2550         if (!priv)
2551                 return NULL;
2552         priv->i2c = i2c;
2553         priv->config = cfg;
2554         priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
2555         priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
2556         /* create dvb_frontend */
2557         switch (system) {
2558         case SYS_DVBS:
2559                 memcpy(&priv->frontend.ops,
2560                         &cxd2841er_dvbs_s2_ops,
2561                         sizeof(struct dvb_frontend_ops));
2562                 type = "S/S2";
2563                 break;
2564         case SYS_DVBT:
2565                 memcpy(&priv->frontend.ops,
2566                         &cxd2841er_dvbt_t2_ops,
2567                         sizeof(struct dvb_frontend_ops));
2568                 type = "T/T2";
2569                 break;
2570         case SYS_DVBC_ANNEX_A:
2571                 memcpy(&priv->frontend.ops,
2572                         &cxd2841er_dvbc_ops,
2573                         sizeof(struct dvb_frontend_ops));
2574                 type = "C/C2";
2575                 break;
2576         default:
2577                 kfree(priv);
2578                 return NULL;
2579         }
2580         priv->frontend.demodulator_priv = priv;
2581         dev_info(&priv->i2c->dev,
2582                 "%s(): attaching CXD2841ER DVB-%s frontend\n",
2583                 __func__, type);
2584         dev_info(&priv->i2c->dev,
2585                 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
2586                 __func__, priv->i2c,
2587                 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
2588         chip_id = cxd2841er_chip_id(priv);
2589         if (chip_id != CXD2841ER_CHIP_ID) {
2590                 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
2591                         __func__, chip_id);
2592                 priv->frontend.demodulator_priv = NULL;
2593                 kfree(priv);
2594                 return NULL;
2595         }
2596         dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
2597                 __func__, chip_id);
2598         return &priv->frontend;
2599 }
2600
2601 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
2602                                         struct i2c_adapter *i2c)
2603 {
2604         return cxd2841er_attach(cfg, i2c, SYS_DVBS);
2605 }
2606 EXPORT_SYMBOL(cxd2841er_attach_s);
2607
2608 struct dvb_frontend *cxd2841er_attach_t(struct cxd2841er_config *cfg,
2609                                         struct i2c_adapter *i2c)
2610 {
2611         return cxd2841er_attach(cfg, i2c, SYS_DVBT);
2612 }
2613 EXPORT_SYMBOL(cxd2841er_attach_t);
2614
2615 struct dvb_frontend *cxd2841er_attach_c(struct cxd2841er_config *cfg,
2616                                         struct i2c_adapter *i2c)
2617 {
2618         return cxd2841er_attach(cfg, i2c, SYS_DVBC_ANNEX_A);
2619 }
2620 EXPORT_SYMBOL(cxd2841er_attach_c);
2621
2622 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
2623         .delsys = { SYS_DVBS, SYS_DVBS2 },
2624         .info = {
2625                 .name           = "Sony CXD2841ER DVB-S/S2 demodulator",
2626                 .frequency_min  = 500000,
2627                 .frequency_max  = 2500000,
2628                 .frequency_stepsize     = 0,
2629                 .symbol_rate_min = 1000000,
2630                 .symbol_rate_max = 45000000,
2631                 .symbol_rate_tolerance = 500,
2632                 .caps = FE_CAN_INVERSION_AUTO |
2633                         FE_CAN_FEC_AUTO |
2634                         FE_CAN_QPSK,
2635         },
2636         .init = cxd2841er_init_s,
2637         .sleep = cxd2841er_sleep_s,
2638         .release = cxd2841er_release,
2639         .set_frontend = cxd2841er_set_frontend_s,
2640         .get_frontend = cxd2841er_get_frontend,
2641         .read_status = cxd2841er_read_status_s,
2642         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
2643         .get_frontend_algo = cxd2841er_get_algo,
2644         .set_tone = cxd2841er_set_tone,
2645         .diseqc_send_burst = cxd2841er_send_burst,
2646         .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
2647         .tune = cxd2841er_tune_s
2648 };
2649
2650 static struct  dvb_frontend_ops cxd2841er_dvbt_t2_ops = {
2651         .delsys = { SYS_DVBT, SYS_DVBT2 },
2652         .info = {
2653                 .name   = "Sony CXD2841ER DVB-T/T2 demodulator",
2654                 .caps = FE_CAN_FEC_1_2 |
2655                         FE_CAN_FEC_2_3 |
2656                         FE_CAN_FEC_3_4 |
2657                         FE_CAN_FEC_5_6 |
2658                         FE_CAN_FEC_7_8 |
2659                         FE_CAN_FEC_AUTO |
2660                         FE_CAN_QPSK |
2661                         FE_CAN_QAM_16 |
2662                         FE_CAN_QAM_32 |
2663                         FE_CAN_QAM_64 |
2664                         FE_CAN_QAM_128 |
2665                         FE_CAN_QAM_256 |
2666                         FE_CAN_QAM_AUTO |
2667                         FE_CAN_TRANSMISSION_MODE_AUTO |
2668                         FE_CAN_GUARD_INTERVAL_AUTO |
2669                         FE_CAN_HIERARCHY_AUTO |
2670                         FE_CAN_MUTE_TS |
2671                         FE_CAN_2G_MODULATION,
2672                 .frequency_min = 42000000,
2673                 .frequency_max = 1002000000
2674         },
2675         .init = cxd2841er_init_tc,
2676         .sleep = cxd2841er_sleep_tc,
2677         .release = cxd2841er_release,
2678         .set_frontend = cxd2841er_set_frontend_tc,
2679         .get_frontend = cxd2841er_get_frontend,
2680         .read_status = cxd2841er_read_status_tc,
2681         .tune = cxd2841er_tune_tc,
2682         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
2683         .get_frontend_algo = cxd2841er_get_algo
2684 };
2685
2686 static struct  dvb_frontend_ops cxd2841er_dvbc_ops = {
2687         .delsys = { SYS_DVBC_ANNEX_A },
2688         .info = {
2689                 .name   = "Sony CXD2841ER DVB-C demodulator",
2690                 .caps = FE_CAN_FEC_1_2 |
2691                         FE_CAN_FEC_2_3 |
2692                         FE_CAN_FEC_3_4 |
2693                         FE_CAN_FEC_5_6 |
2694                         FE_CAN_FEC_7_8 |
2695                         FE_CAN_FEC_AUTO |
2696                         FE_CAN_QAM_16 |
2697                         FE_CAN_QAM_32 |
2698                         FE_CAN_QAM_64 |
2699                         FE_CAN_QAM_128 |
2700                         FE_CAN_QAM_256 |
2701                         FE_CAN_QAM_AUTO |
2702                         FE_CAN_INVERSION_AUTO,
2703                 .frequency_min = 42000000,
2704                 .frequency_max = 1002000000
2705         },
2706         .init = cxd2841er_init_tc,
2707         .sleep = cxd2841er_sleep_tc,
2708         .release = cxd2841er_release,
2709         .set_frontend = cxd2841er_set_frontend_tc,
2710         .get_frontend = cxd2841er_get_frontend,
2711         .read_status = cxd2841er_read_status_tc,
2712         .tune = cxd2841er_tune_tc,
2713         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
2714         .get_frontend_algo = cxd2841er_get_algo,
2715 };
2716
2717 MODULE_DESCRIPTION("Sony CXD2841ER DVB-C/C2/T/T2/S/S2 demodulator driver");
2718 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>");
2719 MODULE_LICENSE("GPL");