drivers/media/dvb-frontends/cxd2841er.c

   1 /*
   2  * cxd2841er.c
   3  *
   4  * Sony digital demodulator driver for
   5  *      CXD2441ER - DVB-S/S2/T/T2/C/C2
   6  *      CXD2454ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
   7  *
   8  * Copyright 2012 Sony Corporation
   9  * Copyright (C) 2014 NetUP Inc.
  10  * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
  11  * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22   */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/bitops.h>
  29 #include <linux/math64.h>
  30 #include <linux/log2.h>
  31 #include <linux/dynamic_debug.h>
  32
  33 #include "dvb_math.h"
  34 #include "dvb_frontend.h"
  35 #include "cxd2841er.h"
  36 #include "cxd2841er_priv.h"
  37
  38 #define MAX_WRITE_REGSIZE       16
  39
  40 enum cxd2841er_state {
  41         STATE_SHUTDOWN = 0,
  42         STATE_SLEEP_S,
  43         STATE_ACTIVE_S,
  44         STATE_SLEEP_TC,
  45         STATE_ACTIVE_TC
  46 };
  47
  48 struct cxd2841er_priv {
  49         struct dvb_frontend             frontend;
  50         struct i2c_adapter              *i2c;
  51         u8                              i2c_addr_slvx;
  52         u8                              i2c_addr_slvt;
  53         const struct cxd2841er_config   *config;
  54         enum cxd2841er_state            state;
  55         u8                              system;
  56         enum cxd2841er_xtal             xtal;
  57 };
  58
  59 static const struct cxd2841er_cnr_data s_cn_data[] = {
  60         { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
  61         { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
  62         { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
  63         { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
  64         { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
  65         { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
  66         { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
  67         { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
  68         { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
  69         { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
  70         { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
  71         { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
  72         { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
  73         { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
  74         { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
  75         { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
  76         { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
  77         { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
  78         { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
  79         { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
  80         { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
  81         { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
  82         { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
  83         { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
  84         { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
  85         { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
  86         { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
  87         { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
  88         { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
  89         { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
  90         { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
  91         { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
  92         { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
  93         { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
  94         { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
  95         { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
  96         { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
  97         { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
  98         { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
  99         { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
 100         { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
 101         { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
 102         { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
 103         { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
 104         { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
 105         { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
 106         { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
 107         { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 108         { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 109         { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
 110         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 111         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 112         { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
 113         { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
 114         { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
 115         { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
 116         { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
 117         { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
 118         { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
 119         { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
 120         { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
 121         { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
 122         { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
 123         { 0x0015, 19900 }, { 0x0014, 20000 },
 124 };
 125
 126 static const struct cxd2841er_cnr_data s2_cn_data[] = {
 127         { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
 128         { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
 129         { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
 130         { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
 131         { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
 132         { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
 133         { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
 134         { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
 135         { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
 136         { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
 137         { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
 138         { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
 139         { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
 140         { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
 141         { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
 142         { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
 143         { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
 144         { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
 145         { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
 146         { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
 147         { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
 148         { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
 149         { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
 150         { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
 151         { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
 152         { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
 153         { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
 154         { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
 155         { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
 156         { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
 157         { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
 158         { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
 159         { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
 160         { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
 161         { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
 162         { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
 163         { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
 164         { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
 165         { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
 166         { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
 167         { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
 168         { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
 169         { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
 170         { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
 171         { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
 172         { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
 173         { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
 174         { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 175         { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 176         { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
 177         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 178         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 179         { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
 180         { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
 181         { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
 182         { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
 183         { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
 184         { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
 185         { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
 186         { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
 187         { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
 188         { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
 189         { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
 190         { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
 191 };
 192
 193 #define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
 194 #define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
 195                 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
 196                 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
 197
 198 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
 199                                 u8 addr, u8 reg, u8 write,
 200                                 const u8 *data, u32 len)
 201 {
 202         dev_dbg(&priv->i2c->dev,
 203                 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
 204                 (write == 0 ? "read" : "write"), addr, reg, len);
 205         print_hex_dump_bytes("cxd2841er: I2C data: ",
 206                 DUMP_PREFIX_OFFSET, data, len);
 207 }
 208
 209 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
 210                                 u8 addr, u8 reg, const u8 *data, u32 len)
 211 {
 212         int ret;
 213         u8 buf[MAX_WRITE_REGSIZE + 1];
 214         u8 i2c_addr = (addr == I2C_SLVX ?
 215                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 216         struct i2c_msg msg[1] = {
 217                 {
 218                         .addr = i2c_addr,
 219                         .flags = 0,
 220                         .len = len + 1,
 221                         .buf = buf,
 222                 }
 223         };
 224
 225         if (len + 1 >= sizeof(buf)) {
 226                 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
 227                          reg, len + 1);
 228                 return -E2BIG;
 229         }
 230
 231         cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
 232         buf[0] = reg;
 233         memcpy(&buf[1], data, len);
 234
 235         ret = i2c_transfer(priv->i2c, msg, 1);
 236         if (ret >= 0 && ret != 1)
 237                 ret = -EIO;
 238         if (ret < 0) {
 239                 dev_warn(&priv->i2c->dev,
 240                         "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
 241                         KBUILD_MODNAME, ret, i2c_addr, reg, len);
 242                 return ret;
 243         }
 244         return 0;
 245 }
 246
 247 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
 248                                u8 addr, u8 reg, u8 val)
 249 {
 250         return cxd2841er_write_regs(priv, addr, reg, &val, 1);
 251 }
 252
 253 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
 254                                u8 addr, u8 reg, u8 *val, u32 len)
 255 {
 256         int ret;
 257         u8 i2c_addr = (addr == I2C_SLVX ?
 258                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 259         struct i2c_msg msg[2] = {
 260                 {
 261                         .addr = i2c_addr,
 262                         .flags = 0,
 263                         .len = 1,
 264                         .buf = &reg,
 265                 }, {
 266                         .addr = i2c_addr,
 267                         .flags = I2C_M_RD,
 268                         .len = len,
 269                         .buf = val,
 270                 }
 271         };
 272
 273         ret = i2c_transfer(priv->i2c, &msg[0], 1);
 274         if (ret >= 0 && ret != 1)
 275                 ret = -EIO;
 276         if (ret < 0) {
 277                 dev_warn(&priv->i2c->dev,
 278                         "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
 279                         KBUILD_MODNAME, ret, i2c_addr, reg);
 280                 return ret;
 281         }
 282         ret = i2c_transfer(priv->i2c, &msg[1], 1);
 283         if (ret >= 0 && ret != 1)
 284                 ret = -EIO;
 285         if (ret < 0) {
 286                 dev_warn(&priv->i2c->dev,
 287                         "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
 288                         KBUILD_MODNAME, ret, i2c_addr, reg);
 289                 return ret;
 290         }
 291         cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
 292         return 0;
 293 }
 294
 295 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
 296                               u8 addr, u8 reg, u8 *val)
 297 {
 298         return cxd2841er_read_regs(priv, addr, reg, val, 1);
 299 }
 300
 301 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
 302                                   u8 addr, u8 reg, u8 data, u8 mask)
 303 {
 304         int res;
 305         u8 rdata;
 306
 307         if (mask != 0xff) {
 308                 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
 309                 if (res)
 310                         return res;
 311                 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
 312         }
 313         return cxd2841er_write_reg(priv, addr, reg, data);
 314 }
 315
 316 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
 317                                            u32 symbol_rate)
 318 {
 319         u32 reg_value = 0;
 320         u8 data[3] = {0, 0, 0};
 321
 322         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 323         /*
 324          * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
 325          *          = ((symbolRateKSps * 2^14) + 500) / 1000
 326          *          = ((symbolRateKSps * 16384) + 500) / 1000
 327          */
 328         reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
 329         if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
 330                 dev_err(&priv->i2c->dev,
 331                         "%s(): reg_value is out of range\n", __func__);
 332                 return -EINVAL;
 333         }
 334         data[0] = (u8)((reg_value >> 16) & 0x0F);
 335         data[1] = (u8)((reg_value >>  8) & 0xFF);
 336         data[2] = (u8)(reg_value & 0xFF);
 337         /* Set SLV-T Bank : 0xAE */
 338         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 339         cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
 340         return 0;
 341 }
 342
 343 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 344                                         u8 system);
 345
 346 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
 347                                          u8 system, u32 symbol_rate)
 348 {
 349         int ret;
 350         u8 data[4] = { 0, 0, 0, 0 };
 351
 352         if (priv->state != STATE_SLEEP_S) {
 353                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 354                         __func__, (int)priv->state);
 355                 return -EINVAL;
 356         }
 357         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 358         cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
 359         /* Set demod mode */
 360         if (system == SYS_DVBS) {
 361                 data[0] = 0x0A;
 362         } else if (system == SYS_DVBS2) {
 363                 data[0] = 0x0B;
 364         } else {
 365                 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
 366                         __func__, system);
 367                 return -EINVAL;
 368         }
 369         /* Set SLV-X Bank : 0x00 */
 370         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 371         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
 372         /* DVB-S/S2 */
 373         data[0] = 0x00;
 374         /* Set SLV-T Bank : 0x00 */
 375         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 376         /* Enable S/S2 auto detection 1 */
 377         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
 378         /* Set SLV-T Bank : 0xAE */
 379         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 380         /* Enable S/S2 auto detection 2 */
 381         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
 382         /* Set SLV-T Bank : 0x00 */
 383         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 384         /* Enable demod clock */
 385         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
 386         /* Enable ADC clock */
 387         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
 388         /* Enable ADC 1 */
 389         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 390         /* Enable ADC 2 */
 391         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
 392         /* Set SLV-X Bank : 0x00 */
 393         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 394         /* Enable ADC 3 */
 395         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
 396         /* Set SLV-T Bank : 0xA3 */
 397         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
 398         cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
 399         data[0] = 0x07;
 400         data[1] = 0x3B;
 401         data[2] = 0x08;
 402         data[3] = 0xC5;
 403         /* Set SLV-T Bank : 0xAB */
 404         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
 405         cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
 406         data[0] = 0x05;
 407         data[1] = 0x80;
 408         data[2] = 0x0A;
 409         data[3] = 0x80;
 410         cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
 411         data[0] = 0x0C;
 412         data[1] = 0xCC;
 413         cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
 414         /* Set demod parameter */
 415         ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
 416         if (ret != 0)
 417                 return ret;
 418         /* Set SLV-T Bank : 0x00 */
 419         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 420         /* disable Hi-Z setting 1 */
 421         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
 422         /* disable Hi-Z setting 2 */
 423         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
 424         priv->state = STATE_ACTIVE_S;
 425         return 0;
 426 }
 427
 428 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
 429                                                u32 bandwidth);
 430
 431 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
 432                                                 u32 bandwidth);
 433
 434 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
 435                                                u32 bandwidth);
 436
 437 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
 438                 u32 bandwidth);
 439
 440 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
 441
 442 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
 443
 444 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
 445
 446 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
 447                                    struct dtv_frontend_properties *p)
 448 {
 449         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 450         if (priv->state != STATE_ACTIVE_S &&
 451                         priv->state != STATE_ACTIVE_TC) {
 452                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
 453                         __func__, priv->state);
 454                 return -EINVAL;
 455         }
 456         /* Set SLV-T Bank : 0x00 */
 457         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 458         /* disable TS output */
 459         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 460         if (priv->state == STATE_ACTIVE_S)
 461                 return cxd2841er_dvbs2_set_symbol_rate(
 462                                 priv, p->symbol_rate / 1000);
 463         else if (priv->state == STATE_ACTIVE_TC) {
 464                 switch (priv->system) {
 465                 case SYS_DVBT:
 466                         return cxd2841er_sleep_tc_to_active_t_band(
 467                                         priv, p->bandwidth_hz);
 468                 case SYS_DVBT2:
 469                         return cxd2841er_sleep_tc_to_active_t2_band(
 470                                         priv, p->bandwidth_hz);
 471                 case SYS_DVBC_ANNEX_A:
 472                         return cxd2841er_sleep_tc_to_active_c_band(
 473                                         priv, p->bandwidth_hz);
 474                 case SYS_ISDBT:
 475                         cxd2841er_active_i_to_sleep_tc(priv);
 476                         cxd2841er_sleep_tc_to_shutdown(priv);
 477                         cxd2841er_shutdown_to_sleep_tc(priv);
 478                         return cxd2841er_sleep_tc_to_active_i(
 479                                         priv, p->bandwidth_hz);
 480                 }
 481         }
 482         dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
 483                 __func__, priv->system);
 484         return -EINVAL;
 485 }
 486
 487 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
 488 {
 489         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 490         if (priv->state != STATE_ACTIVE_S) {
 491                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 492                         __func__, priv->state);
 493                 return -EINVAL;
 494         }
 495         /* Set SLV-T Bank : 0x00 */
 496         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 497         /* disable TS output */
 498         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 499         /* enable Hi-Z setting 1 */
 500         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
 501         /* enable Hi-Z setting 2 */
 502         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 503         /* Set SLV-X Bank : 0x00 */
 504         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 505         /* disable ADC 1 */
 506         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 507         /* Set SLV-T Bank : 0x00 */
 508         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 509         /* disable ADC clock */
 510         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
 511         /* disable ADC 2 */
 512         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 513         /* disable ADC 3 */
 514         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 515         /* SADC Bias ON */
 516         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 517         /* disable demod clock */
 518         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 519         /* Set SLV-T Bank : 0xAE */
 520         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 521         /* disable S/S2 auto detection1 */
 522         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 523         /* Set SLV-T Bank : 0x00 */
 524         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 525         /* disable S/S2 auto detection2 */
 526         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
 527         priv->state = STATE_SLEEP_S;
 528         return 0;
 529 }
 530
 531 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
 532 {
 533         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 534         if (priv->state != STATE_SLEEP_S) {
 535                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 536                         __func__, priv->state);
 537                 return -EINVAL;
 538         }
 539         /* Set SLV-T Bank : 0x00 */
 540         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 541         /* Disable DSQOUT */
 542         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 543         /* Disable DSQIN */
 544         cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
 545         /* Set SLV-X Bank : 0x00 */
 546         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 547         /* Disable oscillator */
 548         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 549         /* Set demod mode */
 550         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 551         priv->state = STATE_SHUTDOWN;
 552         return 0;
 553 }
 554
 555 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
 556 {
 557         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 558         if (priv->state != STATE_SLEEP_TC) {
 559                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 560                         __func__, priv->state);
 561                 return -EINVAL;
 562         }
 563         /* Set SLV-X Bank : 0x00 */
 564         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 565         /* Disable oscillator */
 566         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 567         /* Set demod mode */
 568         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 569         priv->state = STATE_SHUTDOWN;
 570         return 0;
 571 }
 572
 573 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
 574 {
 575         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 576         if (priv->state != STATE_ACTIVE_TC) {
 577                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 578                         __func__, priv->state);
 579                 return -EINVAL;
 580         }
 581         /* Set SLV-T Bank : 0x00 */
 582         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 583         /* disable TS output */
 584         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 585         /* enable Hi-Z setting 1 */
 586         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 587         /* enable Hi-Z setting 2 */
 588         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 589         /* Set SLV-X Bank : 0x00 */
 590         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 591         /* disable ADC 1 */
 592         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 593         /* Set SLV-T Bank : 0x00 */
 594         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 595         /* Disable ADC 2 */
 596         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 597         /* Disable ADC 3 */
 598         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 599         /* Disable ADC clock */
 600         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 601         /* Disable RF level monitor */
 602         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 603         /* Disable demod clock */
 604         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 605         priv->state = STATE_SLEEP_TC;
 606         return 0;
 607 }
 608
 609 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
 610 {
 611         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 612         if (priv->state != STATE_ACTIVE_TC) {
 613                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 614                         __func__, priv->state);
 615                 return -EINVAL;
 616         }
 617         /* Set SLV-T Bank : 0x00 */
 618         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 619         /* disable TS output */
 620         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 621         /* enable Hi-Z setting 1 */
 622         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 623         /* enable Hi-Z setting 2 */
 624         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 625         /* Cancel DVB-T2 setting */
 626         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
 627         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
 628         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
 629         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
 630         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
 631         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
 632         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
 633         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
 634         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
 635         /* Set SLV-X Bank : 0x00 */
 636         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 637         /* disable ADC 1 */
 638         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 639         /* Set SLV-T Bank : 0x00 */
 640         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 641         /* Disable ADC 2 */
 642         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 643         /* Disable ADC 3 */
 644         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 645         /* Disable ADC clock */
 646         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 647         /* Disable RF level monitor */
 648         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 649         /* Disable demod clock */
 650         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 651         priv->state = STATE_SLEEP_TC;
 652         return 0;
 653 }
 654
 655 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
 656 {
 657         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 658         if (priv->state != STATE_ACTIVE_TC) {
 659                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 660                         __func__, priv->state);
 661                 return -EINVAL;
 662         }
 663         /* Set SLV-T Bank : 0x00 */
 664         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 665         /* disable TS output */
 666         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 667         /* enable Hi-Z setting 1 */
 668         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 669         /* enable Hi-Z setting 2 */
 670         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 671         /* Cancel DVB-C setting */
 672         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
 673         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
 674         /* Set SLV-X Bank : 0x00 */
 675         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 676         /* disable ADC 1 */
 677         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 678         /* Set SLV-T Bank : 0x00 */
 679         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 680         /* Disable ADC 2 */
 681         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 682         /* Disable ADC 3 */
 683         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 684         /* Disable ADC clock */
 685         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 686         /* Disable RF level monitor */
 687         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 688         /* Disable demod clock */
 689         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 690         priv->state = STATE_SLEEP_TC;
 691         return 0;
 692 }
 693
 694 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
 695 {
 696         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 697         if (priv->state != STATE_ACTIVE_TC) {
 698                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 699                                 __func__, priv->state);
 700                 return -EINVAL;
 701         }
 702         /* Set SLV-T Bank : 0x00 */
 703         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 704         /* disable TS output */
 705         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 706         /* enable Hi-Z setting 1 */
 707         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 708         /* enable Hi-Z setting 2 */
 709         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 710
 711         /* TODO: Cancel demod parameter */
 712
 713         /* Set SLV-X Bank : 0x00 */
 714         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 715         /* disable ADC 1 */
 716         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 717         /* Set SLV-T Bank : 0x00 */
 718         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 719         /* Disable ADC 2 */
 720         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 721         /* Disable ADC 3 */
 722         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 723         /* Disable ADC clock */
 724         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 725         /* Disable RF level monitor */
 726         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 727         /* Disable demod clock */
 728         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 729         priv->state = STATE_SLEEP_TC;
 730         return 0;
 731 }
 732
 733 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
 734 {
 735         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 736         if (priv->state != STATE_SHUTDOWN) {
 737                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 738                         __func__, priv->state);
 739                 return -EINVAL;
 740         }
 741         /* Set SLV-X Bank : 0x00 */
 742         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 743         /* Clear all demodulator registers */
 744         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 745         usleep_range(3000, 5000);
 746         /* Set SLV-X Bank : 0x00 */
 747         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 748         /* Set demod SW reset */
 749         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 750
 751         switch (priv->xtal) {
 752         case SONY_XTAL_20500:
 753                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 754                 break;
 755         case SONY_XTAL_24000:
 756                 /* Select demod frequency */
 757                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 758                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
 759                 break;
 760         case SONY_XTAL_41000:
 761                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
 762                 break;
 763         default:
 764                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
 765                                 __func__, priv->xtal);
 766                 return -EINVAL;
 767         }
 768
 769         /* Set demod mode */
 770         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
 771         /* Clear demod SW reset */
 772         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 773         usleep_range(1000, 2000);
 774         /* Set SLV-T Bank : 0x00 */
 775         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 776         /* enable DSQOUT */
 777         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
 778         /* enable DSQIN */
 779         cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
 780         /* TADC Bias On */
 781         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 782         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 783         /* SADC Bias On */
 784         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 785         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 786         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 787         priv->state = STATE_SLEEP_S;
 788         return 0;
 789 }
 790
 791 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
 792 {
 793         u8 data = 0;
 794         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 795         if (priv->state != STATE_SHUTDOWN) {
 796                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 797                         __func__, priv->state);
 798                 return -EINVAL;
 799         }
 800         /* Set SLV-X Bank : 0x00 */
 801         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 802         /* Clear all demodulator registers */
 803         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 804         usleep_range(3000, 5000);
 805         /* Set SLV-X Bank : 0x00 */
 806         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 807         /* Set demod SW reset */
 808         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 809   /* Select ADC clock mode */
 810         cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
 811
 812         switch (priv->xtal) {
 813         case SONY_XTAL_20500:
 814                 data = 0x0;
 815                 break;
 816         case SONY_XTAL_24000:
 817                 /* Select demod frequency */
 818                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 819                 data = 0x3;
 820                 break;
 821         case SONY_XTAL_41000:
 822                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 823                 data = 0x1;
 824                 break;
 825         }
 826         cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
 827         /* Clear demod SW reset */
 828         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 829         usleep_range(1000, 2000);
 830         /* Set SLV-T Bank : 0x00 */
 831         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 832         /* TADC Bias On */
 833         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 834         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 835         /* SADC Bias On */
 836         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 837         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 838         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 839         priv->state = STATE_SLEEP_TC;
 840         return 0;
 841 }
 842
 843 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
 844 {
 845         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 846         /* Set SLV-T Bank : 0x00 */
 847         cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
 848         /* SW Reset */
 849         cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
 850         /* Enable TS output */
 851         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
 852         return 0;
 853 }
 854
 855 /* Set TS parallel mode */
 856 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 857                                         u8 system)
 858 {
 859         u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
 860
 861         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 862         /* Set SLV-T Bank : 0x00 */
 863         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 864         cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
 865         cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
 866         cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
 867         dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
 868                 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
 869
 870         /*
 871          * slave    Bank    Addr    Bit    default    Name
 872          * <SLV-T>  00h     D9h     [7:0]  8'h08      OTSCKPERIOD
 873          */
 874         cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
 875         /*
 876          * Disable TS IF Clock
 877          * slave    Bank    Addr    Bit    default    Name
 878          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 879          */
 880         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
 881         /*
 882          * slave    Bank    Addr    Bit    default    Name
 883          * <SLV-T>  00h     33h     [1:0]  2'b01      OREG_CKSEL_TSIF
 884          */
 885         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
 886         /*
 887          * Enable TS IF Clock
 888          * slave    Bank    Addr    Bit    default    Name
 889          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 890          */
 891         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
 892
 893         if (system == SYS_DVBT) {
 894                 /* Enable parity period for DVB-T */
 895                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 896                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 897         } else if (system == SYS_DVBC_ANNEX_A) {
 898                 /* Enable parity period for DVB-C */
 899                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 900                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 901         }
 902 }
 903
 904 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
 905 {
 906         u8 chip_id = 0;
 907
 908         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 909         if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
 910                 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
 911         else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
 912                 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
 913
 914         return chip_id;
 915 }
 916
 917 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
 918                                    enum fe_status *status)
 919 {
 920         u8 reg = 0;
 921         struct cxd2841er_priv *priv = fe->demodulator_priv;
 922
 923         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 924         *status = 0;
 925         if (priv->state != STATE_ACTIVE_S) {
 926                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 927                         __func__, priv->state);
 928                 return -EINVAL;
 929         }
 930         /* Set SLV-T Bank : 0xA0 */
 931         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
 932         /*
 933          *  slave     Bank      Addr      Bit      Signal name
 934          * <SLV-T>    A0h       11h       [2]      ITSLOCK
 935          */
 936         cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
 937         if (reg & 0x04) {
 938                 *status = FE_HAS_SIGNAL
 939                         | FE_HAS_CARRIER
 940                         | FE_HAS_VITERBI
 941                         | FE_HAS_SYNC
 942                         | FE_HAS_LOCK;
 943         }
 944         dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
 945         return 0;
 946 }
 947
 948 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
 949                                       u8 *sync, u8 *tslock, u8 *unlock)
 950 {
 951         u8 data = 0;
 952
 953         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 954         if (priv->state != STATE_ACTIVE_TC)
 955                 return -EINVAL;
 956         if (priv->system == SYS_DVBT) {
 957                 /* Set SLV-T Bank : 0x10 */
 958                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 959         } else {
 960                 /* Set SLV-T Bank : 0x20 */
 961                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
 962         }
 963         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
 964         if ((data & 0x07) == 0x07) {
 965                 dev_dbg(&priv->i2c->dev,
 966                         "%s(): invalid hardware state detected\n", __func__);
 967                 *sync = 0;
 968                 *tslock = 0;
 969                 *unlock = 0;
 970         } else {
 971                 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
 972                 *tslock = ((data & 0x20) ? 1 : 0);
 973                 *unlock = ((data & 0x10) ? 1 : 0);
 974         }
 975         return 0;
 976 }
 977
 978 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
 979 {
 980         u8 data;
 981
 982         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 983         if (priv->state != STATE_ACTIVE_TC)
 984                 return -EINVAL;
 985         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 986         cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
 987         if ((data & 0x01) == 0) {
 988                 *tslock = 0;
 989         } else {
 990                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
 991                 *tslock = ((data & 0x20) ? 1 : 0);
 992         }
 993         return 0;
 994 }
 995
 996 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
 997                 u8 *sync, u8 *tslock, u8 *unlock)
 998 {
 999         u8 data = 0;
1000
1001         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1002         if (priv->state != STATE_ACTIVE_TC)
1003                 return -EINVAL;
1004         /* Set SLV-T Bank : 0x60 */
1005         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1006         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1007         dev_dbg(&priv->i2c->dev,
1008                         "%s(): lock=0x%x\n", __func__, data);
1009         *sync = ((data & 0x02) ? 1 : 0);
1010         *tslock = ((data & 0x01) ? 1 : 0);
1011         *unlock = ((data & 0x10) ? 1 : 0);
1012         return 0;
1013 }
1014
1015 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1016                                     enum fe_status *status)
1017 {
1018         int ret = 0;
1019         u8 sync = 0;
1020         u8 tslock = 0;
1021         u8 unlock = 0;
1022         struct cxd2841er_priv *priv = fe->demodulator_priv;
1023
1024         *status = 0;
1025         if (priv->state == STATE_ACTIVE_TC) {
1026                 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1027                         ret = cxd2841er_read_status_t_t2(
1028                                 priv, &sync, &tslock, &unlock);
1029                         if (ret)
1030                                 goto done;
1031                         if (unlock)
1032                                 goto done;
1033                         if (sync)
1034                                 *status = FE_HAS_SIGNAL |
1035                                         FE_HAS_CARRIER |
1036                                         FE_HAS_VITERBI |
1037                                         FE_HAS_SYNC;
1038                         if (tslock)
1039                                 *status |= FE_HAS_LOCK;
1040                 } else if (priv->system == SYS_ISDBT) {
1041                         ret = cxd2841er_read_status_i(
1042                                         priv, &sync, &tslock, &unlock);
1043                         if (ret)
1044                                 goto done;
1045                         if (unlock)
1046                                 goto done;
1047                         if (sync)
1048                                 *status = FE_HAS_SIGNAL |
1049                                         FE_HAS_CARRIER |
1050                                         FE_HAS_VITERBI |
1051                                         FE_HAS_SYNC;
1052                         if (tslock)
1053                                 *status |= FE_HAS_LOCK;
1054                 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1055                         ret = cxd2841er_read_status_c(priv, &tslock);
1056                         if (ret)
1057                                 goto done;
1058                         if (tslock)
1059                                 *status = FE_HAS_SIGNAL |
1060                                         FE_HAS_CARRIER |
1061                                         FE_HAS_VITERBI |
1062                                         FE_HAS_SYNC |
1063                                         FE_HAS_LOCK;
1064                 }
1065         }
1066 done:
1067         dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1068         return ret;
1069 }
1070
1071 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1072                                              int *offset)
1073 {
1074         u8 data[3];
1075         u8 is_hs_mode;
1076         s32 cfrl_ctrlval;
1077         s32 temp_div, temp_q, temp_r;
1078
1079         if (priv->state != STATE_ACTIVE_S) {
1080                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1081                         __func__, priv->state);
1082                 return -EINVAL;
1083         }
1084         /*
1085          * Get High Sampling Rate mode
1086          *  slave     Bank      Addr      Bit      Signal name
1087          * <SLV-T>    A0h       10h       [0]      ITRL_LOCK
1088          */
1089         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1090         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1091         if (data[0] & 0x01) {
1092                 /*
1093                  *  slave     Bank      Addr      Bit      Signal name
1094                  * <SLV-T>    A0h       50h       [4]      IHSMODE
1095                  */
1096                 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1097                 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1098         } else {
1099                 dev_dbg(&priv->i2c->dev,
1100                         "%s(): unable to detect sampling rate mode\n",
1101                         __func__);
1102                 return -EINVAL;
1103         }
1104         /*
1105          *  slave     Bank      Addr      Bit      Signal name
1106          * <SLV-T>    A0h       45h       [4:0]    ICFRL_CTRLVAL[20:16]
1107          * <SLV-T>    A0h       46h       [7:0]    ICFRL_CTRLVAL[15:8]
1108          * <SLV-T>    A0h       47h       [7:0]    ICFRL_CTRLVAL[7:0]
1109          */
1110         cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1111         cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1112                                 (((u32)data[1] & 0xFF) <<  8) |
1113                                 ((u32)data[2] & 0xFF), 20);
1114         temp_div = (is_hs_mode ? 1048576 : 1572864);
1115         if (cfrl_ctrlval > 0) {
1116                 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1117                         temp_div, &temp_r);
1118         } else {
1119                 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1120                         temp_div, &temp_r);
1121         }
1122         if (temp_r >= temp_div / 2)
1123                 temp_q++;
1124         if (cfrl_ctrlval > 0)
1125                 temp_q *= -1;
1126         *offset = temp_q;
1127         return 0;
1128 }
1129
1130 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1131                                            u32 bandwidth, int *offset)
1132 {
1133         u8 data[4];
1134
1135         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1136         if (priv->state != STATE_ACTIVE_TC) {
1137                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1138                         __func__, priv->state);
1139                 return -EINVAL;
1140         }
1141         if (priv->system != SYS_ISDBT) {
1142                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1143                         __func__, priv->system);
1144                 return -EINVAL;
1145         }
1146         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1147         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1148         *offset = -1 * sign_extend32(
1149                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1150                 ((u32)data[2] << 8) | (u32)data[3], 29);
1151
1152         switch (bandwidth) {
1153         case 6000000:
1154                 *offset = -1 * ((*offset) * 8/264);
1155                 break;
1156         case 7000000:
1157                 *offset = -1 * ((*offset) * 8/231);
1158                 break;
1159         case 8000000:
1160                 *offset = -1 * ((*offset) * 8/198);
1161                 break;
1162         default:
1163                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1164                                 __func__, bandwidth);
1165                 return -EINVAL;
1166         }
1167
1168         dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1169                         __func__, bandwidth, *offset);
1170
1171         return 0;
1172 }
1173
1174 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1175                                            u32 bandwidth, int *offset)
1176 {
1177         u8 data[4];
1178
1179         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1180         if (priv->state != STATE_ACTIVE_TC) {
1181                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1182                         __func__, priv->state);
1183                 return -EINVAL;
1184         }
1185         if (priv->system != SYS_DVBT) {
1186                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1187                         __func__, priv->system);
1188                 return -EINVAL;
1189         }
1190         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1191         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1192         *offset = -1 * sign_extend32(
1193                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1194                 ((u32)data[2] << 8) | (u32)data[3], 29);
1195         *offset *= (bandwidth / 1000000);
1196         *offset /= 235;
1197         return 0;
1198 }
1199
1200 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1201                                            u32 bandwidth, int *offset)
1202 {
1203         u8 data[4];
1204
1205         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1206         if (priv->state != STATE_ACTIVE_TC) {
1207                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1208                         __func__, priv->state);
1209                 return -EINVAL;
1210         }
1211         if (priv->system != SYS_DVBT2) {
1212                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1213                         __func__, priv->system);
1214                 return -EINVAL;
1215         }
1216         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1217         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1218         *offset = -1 * sign_extend32(
1219                 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1220                 ((u32)data[2] << 8) | (u32)data[3], 27);
1221         switch (bandwidth) {
1222         case 1712000:
1223                 *offset /= 582;
1224                 break;
1225         case 5000000:
1226         case 6000000:
1227         case 7000000:
1228         case 8000000:
1229                 *offset *= (bandwidth / 1000000);
1230                 *offset /= 940;
1231                 break;
1232         default:
1233                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1234                         __func__, bandwidth);
1235                 return -EINVAL;
1236         }
1237         return 0;
1238 }
1239
1240 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1241                                           int *offset)
1242 {
1243         u8 data[2];
1244
1245         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1246         if (priv->state != STATE_ACTIVE_TC) {
1247                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1248                         __func__, priv->state);
1249                 return -EINVAL;
1250         }
1251         if (priv->system != SYS_DVBC_ANNEX_A) {
1252                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1253                         __func__, priv->system);
1254                 return -EINVAL;
1255         }
1256         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1257         cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1258         *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1259                                                 | (u32)data[1], 13), 16384);
1260         return 0;
1261 }
1262
1263 static int cxd2841er_read_packet_errors_t(
1264                 struct cxd2841er_priv *priv, u32 *penum)
1265 {
1266         u8 data[3];
1267
1268         *penum = 0;
1269         if (priv->state != STATE_ACTIVE_TC) {
1270                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1271                         __func__, priv->state);
1272                 return -EINVAL;
1273         }
1274         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1275         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1276         if (data[2] & 0x01)
1277                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1278         return 0;
1279 }
1280
1281 static int cxd2841er_read_packet_errors_t2(
1282                 struct cxd2841er_priv *priv, u32 *penum)
1283 {
1284         u8 data[3];
1285
1286         *penum = 0;
1287         if (priv->state != STATE_ACTIVE_TC) {
1288                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1289                         __func__, priv->state);
1290                 return -EINVAL;
1291         }
1292         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1293         cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1294         if (data[0] & 0x01)
1295                 *penum = ((u32)data[1] << 8) | (u32)data[2];
1296         return 0;
1297 }
1298
1299 static int cxd2841er_read_packet_errors_i(
1300                 struct cxd2841er_priv *priv, u32 *penum)
1301 {
1302         u8 data[2];
1303
1304         *penum = 0;
1305         if (priv->state != STATE_ACTIVE_TC) {
1306                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1307                                 __func__, priv->state);
1308                 return -EINVAL;
1309         }
1310         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1311         cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1312
1313         if (!(data[0] & 0x01))
1314                 return 0;
1315
1316         /* Layer A */
1317         cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1318         *penum = ((u32)data[0] << 8) | (u32)data[1];
1319
1320         /* Layer B */
1321         cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1322         *penum += ((u32)data[0] << 8) | (u32)data[1];
1323
1324         /* Layer C */
1325         cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1326         *penum += ((u32)data[0] << 8) | (u32)data[1];
1327
1328         return 0;
1329 }
1330
1331 static u32 cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv)
1332 {
1333         u8 data[11];
1334         u32 bit_error, bit_count;
1335         u32 temp_q, temp_r;
1336
1337         /* Set SLV-T Bank : 0xA0 */
1338         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1339         /*
1340          *  slave     Bank      Addr      Bit      Signal name
1341          * <SLV-T>    A0h       35h       [0]      IFVBER_VALID
1342          * <SLV-T>    A0h       36h       [5:0]    IFVBER_BITERR[21:16]
1343          * <SLV-T>    A0h       37h       [7:0]    IFVBER_BITERR[15:8]
1344          * <SLV-T>    A0h       38h       [7:0]    IFVBER_BITERR[7:0]
1345          * <SLV-T>    A0h       3Dh       [5:0]    IFVBER_BITNUM[21:16]
1346          * <SLV-T>    A0h       3Eh       [7:0]    IFVBER_BITNUM[15:8]
1347          * <SLV-T>    A0h       3Fh       [7:0]    IFVBER_BITNUM[7:0]
1348          */
1349         cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1350         if (data[0] & 0x01) {
1351                 bit_error = ((u32)(data[1]  & 0x3F) << 16) |
1352                         ((u32)(data[2]  & 0xFF) <<  8) |
1353                         (u32)(data[3]  & 0xFF);
1354                 bit_count = ((u32)(data[8]  & 0x3F) << 16) |
1355                         ((u32)(data[9]  & 0xFF) <<  8) |
1356                         (u32)(data[10] & 0xFF);
1357                 /*
1358                  *      BER = bitError / bitCount
1359                  *      = (bitError * 10^7) / bitCount
1360                  *      = ((bitError * 625 * 125 * 128) / bitCount
1361                  */
1362                 if ((bit_count == 0) || (bit_error > bit_count)) {
1363                         dev_dbg(&priv->i2c->dev,
1364                                 "%s(): invalid bit_error %d, bit_count %d\n",
1365                                 __func__, bit_error, bit_count);
1366                         return 0;
1367                 }
1368                 temp_q = div_u64_rem(10000000ULL * bit_error,
1369                                                 bit_count, &temp_r);
1370                 if (bit_count != 1 && temp_r >= bit_count / 2)
1371                         temp_q++;
1372                 return temp_q;
1373         }
1374         dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1375         return 0;
1376 }
1377
1378
1379 static u32 cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv)
1380 {
1381         u8 data[5];
1382         u32 bit_error, period;
1383         u32 temp_q, temp_r;
1384         u32 result = 0;
1385
1386         /* Set SLV-T Bank : 0xB2 */
1387         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1388         /*
1389          *  slave     Bank      Addr      Bit      Signal name
1390          * <SLV-T>    B2h       30h       [0]      IFLBER_VALID
1391          * <SLV-T>    B2h       31h       [3:0]    IFLBER_BITERR[27:24]
1392          * <SLV-T>    B2h       32h       [7:0]    IFLBER_BITERR[23:16]
1393          * <SLV-T>    B2h       33h       [7:0]    IFLBER_BITERR[15:8]
1394          * <SLV-T>    B2h       34h       [7:0]    IFLBER_BITERR[7:0]
1395          */
1396         cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1397         if (data[0] & 0x01) {
1398                 /* Bit error count */
1399                 bit_error = ((u32)(data[1] & 0x0F) << 24) |
1400                         ((u32)(data[2] & 0xFF) << 16) |
1401                         ((u32)(data[3] & 0xFF) <<  8) |
1402                         (u32)(data[4] & 0xFF);
1403
1404                 /* Set SLV-T Bank : 0xA0 */
1405                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1406                 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1407                 /* Measurement period */
1408                 period = (u32)(1 << (data[0] & 0x0F));
1409                 if (period == 0) {
1410                         dev_dbg(&priv->i2c->dev,
1411                                 "%s(): period is 0\n", __func__);
1412                         return 0;
1413                 }
1414                 if (bit_error > (period * 64800)) {
1415                         dev_dbg(&priv->i2c->dev,
1416                                 "%s(): invalid bit_err 0x%x period 0x%x\n",
1417                                 __func__, bit_error, period);
1418                         return 0;
1419                 }
1420                 /*
1421                  * BER = bitError / (period * 64800)
1422                  *      = (bitError * 10^7) / (period * 64800)
1423                  *      = (bitError * 10^5) / (period * 648)
1424                  *      = (bitError * 12500) / (period * 81)
1425                  *      = (bitError * 10) * 1250 / (period * 81)
1426                  */
1427                 temp_q = div_u64_rem(12500ULL * bit_error,
1428                                         period * 81, &temp_r);
1429                 if (temp_r >= period * 40)
1430                         temp_q++;
1431                 result = temp_q;
1432         } else {
1433                 dev_dbg(&priv->i2c->dev,
1434                         "%s(): no data available\n", __func__);
1435         }
1436         return result;
1437 }
1438
1439 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, u32 *ber)
1440 {
1441         u8 data[4];
1442         u32 div, q, r;
1443         u32 bit_err, period_exp, n_ldpc;
1444
1445         *ber = 0;
1446         if (priv->state != STATE_ACTIVE_TC) {
1447                 dev_dbg(&priv->i2c->dev,
1448                         "%s(): invalid state %d\n", __func__, priv->state);
1449                 return -EINVAL;
1450         }
1451         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1452         cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1453         if (!(data[0] & 0x10)) {
1454                 dev_dbg(&priv->i2c->dev,
1455                         "%s(): no valid BER data\n", __func__);
1456                 return 0;
1457         }
1458         bit_err = ((u32)(data[0] & 0x0f) << 24) |
1459                 ((u32)data[1] << 16) |
1460                 ((u32)data[2] << 8) |
1461                 (u32)data[3];
1462         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1463         period_exp = data[0] & 0x0f;
1464         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1465         cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1466         n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1467         if (bit_err > ((1U << period_exp) * n_ldpc)) {
1468                 dev_dbg(&priv->i2c->dev,
1469                         "%s(): invalid BER value\n", __func__);
1470                 return -EINVAL;
1471         }
1472         if (period_exp >= 4) {
1473                 div = (1U << (period_exp - 4)) * (n_ldpc / 200);
1474                 q = div_u64_rem(3125ULL * bit_err, div, &r);
1475         } else {
1476                 div = (1U << period_exp) * (n_ldpc / 200);
1477                 q = div_u64_rem(50000ULL * bit_err, div, &r);
1478         }
1479         *ber = (r >= div / 2) ? q + 1 : q;
1480         return 0;
1481 }
1482
1483 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, u32 *ber)
1484 {
1485         u8 data[2];
1486         u32 div, q, r;
1487         u32 bit_err, period;
1488
1489         *ber = 0;
1490         if (priv->state != STATE_ACTIVE_TC) {
1491                 dev_dbg(&priv->i2c->dev,
1492                         "%s(): invalid state %d\n", __func__, priv->state);
1493                 return -EINVAL;
1494         }
1495         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1496         cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1497         if (!(data[0] & 0x01)) {
1498                 dev_dbg(&priv->i2c->dev,
1499                         "%s(): no valid BER data\n", __func__);
1500                 return 0;
1501         }
1502         cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1503         bit_err = ((u32)data[0] << 8) | (u32)data[1];
1504         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1505         period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1506         div = period / 128;
1507         q = div_u64_rem(78125ULL * bit_err, div, &r);
1508         *ber = (r >= div / 2) ? q + 1 : q;
1509         return 0;
1510 }
1511
1512 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1513 {
1514         u8 data[3];
1515         u32 res = 0, value;
1516         int min_index, max_index, index;
1517         static const struct cxd2841er_cnr_data *cn_data;
1518
1519         /* Set SLV-T Bank : 0xA1 */
1520         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1521         /*
1522          *  slave     Bank      Addr      Bit     Signal name
1523          * <SLV-T>    A1h       10h       [0]     ICPM_QUICKRDY
1524          * <SLV-T>    A1h       11h       [4:0]   ICPM_QUICKCNDT[12:8]
1525          * <SLV-T>    A1h       12h       [7:0]   ICPM_QUICKCNDT[7:0]
1526          */
1527         cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1528         if (data[0] & 0x01) {
1529                 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1530                 min_index = 0;
1531                 if (delsys == SYS_DVBS) {
1532                         cn_data = s_cn_data;
1533                         max_index = sizeof(s_cn_data) /
1534                                 sizeof(s_cn_data[0]) - 1;
1535                 } else {
1536                         cn_data = s2_cn_data;
1537                         max_index = sizeof(s2_cn_data) /
1538                                 sizeof(s2_cn_data[0]) - 1;
1539                 }
1540                 if (value >= cn_data[min_index].value) {
1541                         res = cn_data[min_index].cnr_x1000;
1542                         goto done;
1543                 }
1544                 if (value <= cn_data[max_index].value) {
1545                         res = cn_data[max_index].cnr_x1000;
1546                         goto done;
1547                 }
1548                 while ((max_index - min_index) > 1) {
1549                         index = (max_index + min_index) / 2;
1550                         if (value == cn_data[index].value) {
1551                                 res = cn_data[index].cnr_x1000;
1552                                 goto done;
1553                         } else if (value > cn_data[index].value)
1554                                 max_index = index;
1555                         else
1556                                 min_index = index;
1557                         if ((max_index - min_index) <= 1) {
1558                                 if (value == cn_data[max_index].value) {
1559                                         res = cn_data[max_index].cnr_x1000;
1560                                         goto done;
1561                                 } else {
1562                                         res = cn_data[min_index].cnr_x1000;
1563                                         goto done;
1564                                 }
1565                         }
1566                 }
1567         } else {
1568                 dev_dbg(&priv->i2c->dev,
1569                         "%s(): no data available\n", __func__);
1570         }
1571 done:
1572         return res;
1573 }
1574
1575 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1576 {
1577         u32 reg;
1578         u8 data[2];
1579
1580         *snr = 0;
1581         if (priv->state != STATE_ACTIVE_TC) {
1582                 dev_dbg(&priv->i2c->dev,
1583                         "%s(): invalid state %d\n", __func__, priv->state);
1584                 return -EINVAL;
1585         }
1586         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1587         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1588         reg = ((u32)data[0] << 8) | (u32)data[1];
1589         if (reg == 0) {
1590                 dev_dbg(&priv->i2c->dev,
1591                         "%s(): reg value out of range\n", __func__);
1592                 return 0;
1593         }
1594         if (reg > 4996)
1595                 reg = 4996;
1596         *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1597         return 0;
1598 }
1599
1600 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1601 {
1602         u32 reg;
1603         u8 data[2];
1604
1605         *snr = 0;
1606         if (priv->state != STATE_ACTIVE_TC) {
1607                 dev_dbg(&priv->i2c->dev,
1608                         "%s(): invalid state %d\n", __func__, priv->state);
1609                 return -EINVAL;
1610         }
1611         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1612         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1613         reg = ((u32)data[0] << 8) | (u32)data[1];
1614         if (reg == 0) {
1615                 dev_dbg(&priv->i2c->dev,
1616                         "%s(): reg value out of range\n", __func__);
1617                 return 0;
1618         }
1619         if (reg > 10876)
1620                 reg = 10876;
1621         *snr = 10000 * ((intlog10(reg) -
1622                 intlog10(12600 - reg)) >> 24) + 32000;
1623         return 0;
1624 }
1625
1626 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1627 {
1628         u32 reg;
1629         u8 data[2];
1630
1631         *snr = 0;
1632         if (priv->state != STATE_ACTIVE_TC) {
1633                 dev_dbg(&priv->i2c->dev,
1634                                 "%s(): invalid state %d\n", __func__,
1635                                 priv->state);
1636                 return -EINVAL;
1637         }
1638
1639         /* Freeze all registers */
1640         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1641
1642
1643         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1644         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1645         reg = ((u32)data[0] << 8) | (u32)data[1];
1646         if (reg == 0) {
1647                 dev_dbg(&priv->i2c->dev,
1648                                 "%s(): reg value out of range\n", __func__);
1649                 return 0;
1650         }
1651         if (reg > 4996)
1652                 reg = 4996;
1653         *snr = 100 * intlog10(reg) - 9031;
1654         return 0;
1655 }
1656
1657 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1658                                         u8 delsys)
1659 {
1660         u8 data[2];
1661
1662         cxd2841er_write_reg(
1663                 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1664         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1665         dev_dbg(&priv->i2c->dev,
1666                         "%s(): AGC value=%u\n",
1667                         __func__, (((u16)data[0] & 0x0F) << 8) |
1668                         (u16)(data[1] & 0xFF));
1669         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1670 }
1671
1672 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1673                 u8 delsys)
1674 {
1675         u8 data[2];
1676
1677         cxd2841er_write_reg(
1678                         priv, I2C_SLVT, 0x00, 0x60);
1679         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1680
1681         dev_dbg(&priv->i2c->dev,
1682                         "%s(): AGC value=%u\n",
1683                         __func__, (((u16)data[0] & 0x0F) << 8) |
1684                         (u16)(data[1] & 0xFF));
1685         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1686 }
1687
1688 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1689 {
1690         u8 data[2];
1691
1692         /* Set SLV-T Bank : 0xA0 */
1693         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1694         /*
1695          *  slave     Bank      Addr      Bit       Signal name
1696          * <SLV-T>    A0h       1Fh       [4:0]     IRFAGC_GAIN[12:8]
1697          * <SLV-T>    A0h       20h       [7:0]     IRFAGC_GAIN[7:0]
1698          */
1699         cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1700         return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1701 }
1702
1703 static int cxd2841er_read_ber(struct dvb_frontend *fe, u32 *ber)
1704 {
1705         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1706         struct cxd2841er_priv *priv = fe->demodulator_priv;
1707
1708         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1709         *ber = 0;
1710         switch (p->delivery_system) {
1711         case SYS_DVBS:
1712                 *ber = cxd2841er_mon_read_ber_s(priv);
1713                 break;
1714         case SYS_DVBS2:
1715                 *ber = cxd2841er_mon_read_ber_s2(priv);
1716                 break;
1717         case SYS_DVBT:
1718                 return cxd2841er_read_ber_t(priv, ber);
1719         case SYS_DVBT2:
1720                 return cxd2841er_read_ber_t2(priv, ber);
1721         default:
1722                 *ber = 0;
1723                 break;
1724         }
1725         return 0;
1726 }
1727
1728 static int cxd2841er_read_signal_strength(struct dvb_frontend *fe,
1729                                           u16 *strength)
1730 {
1731         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1732         struct cxd2841er_priv *priv = fe->demodulator_priv;
1733
1734         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1735         switch (p->delivery_system) {
1736         case SYS_DVBT:
1737         case SYS_DVBT2:
1738                 *strength = 65535 - cxd2841er_read_agc_gain_t_t2(
1739                         priv, p->delivery_system);
1740                 break;
1741         case SYS_ISDBT:
1742                 *strength = 65535 - cxd2841er_read_agc_gain_i(
1743                                 priv, p->delivery_system);
1744                 break;
1745         case SYS_DVBS:
1746         case SYS_DVBS2:
1747                 *strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1748                 break;
1749         default:
1750                 *strength = 0;
1751                 break;
1752         }
1753         return 0;
1754 }
1755
1756 static int cxd2841er_read_snr(struct dvb_frontend *fe, u16 *snr)
1757 {
1758         u32 tmp = 0;
1759         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1760         struct cxd2841er_priv *priv = fe->demodulator_priv;
1761
1762         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1763         switch (p->delivery_system) {
1764         case SYS_DVBT:
1765                 cxd2841er_read_snr_t(priv, &tmp);
1766                 break;
1767         case SYS_DVBT2:
1768                 cxd2841er_read_snr_t2(priv, &tmp);
1769                 break;
1770         case SYS_ISDBT:
1771                 cxd2841er_read_snr_i(priv, &tmp);
1772                 break;
1773         case SYS_DVBS:
1774         case SYS_DVBS2:
1775                 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1776                 break;
1777         default:
1778                 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1779                         __func__, p->delivery_system);
1780                 break;
1781         }
1782         *snr = tmp & 0xffff;
1783         return 0;
1784 }
1785
1786 static int cxd2841er_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1787 {
1788         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1789         struct cxd2841er_priv *priv = fe->demodulator_priv;
1790
1791         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1792         switch (p->delivery_system) {
1793         case SYS_DVBT:
1794                 cxd2841er_read_packet_errors_t(priv, ucblocks);
1795                 break;
1796         case SYS_DVBT2:
1797                 cxd2841er_read_packet_errors_t2(priv, ucblocks);
1798                 break;
1799         case SYS_ISDBT:
1800                 cxd2841er_read_packet_errors_i(priv, ucblocks);
1801                 break;
1802         default:
1803                 *ucblocks = 0;
1804                 break;
1805         }
1806         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1807         return 0;
1808 }
1809
1810 static int cxd2841er_dvbt2_set_profile(
1811         struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1812 {
1813         u8 tune_mode;
1814         u8 seq_not2d_time;
1815
1816         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1817         switch (profile) {
1818         case DVBT2_PROFILE_BASE:
1819                 tune_mode = 0x01;
1820                 /* Set early unlock time */
1821                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
1822                 break;
1823         case DVBT2_PROFILE_LITE:
1824                 tune_mode = 0x05;
1825                 /* Set early unlock time */
1826                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
1827                 break;
1828         case DVBT2_PROFILE_ANY:
1829                 tune_mode = 0x00;
1830                 /* Set early unlock time */
1831                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
1832                 break;
1833         default:
1834                 return -EINVAL;
1835         }
1836         /* Set SLV-T Bank : 0x2E */
1837         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1838         /* Set profile and tune mode */
1839         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1840         /* Set SLV-T Bank : 0x2B */
1841         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1842         /* Set early unlock detection time */
1843         cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1844         return 0;
1845 }
1846
1847 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1848                                           u8 is_auto, u8 plp_id)
1849 {
1850         if (is_auto) {
1851                 dev_dbg(&priv->i2c->dev,
1852                         "%s() using auto PLP selection\n", __func__);
1853         } else {
1854                 dev_dbg(&priv->i2c->dev,
1855                         "%s() using manual PLP selection, ID %d\n",
1856                         __func__, plp_id);
1857         }
1858         /* Set SLV-T Bank : 0x23 */
1859         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1860         if (!is_auto) {
1861                 /* Manual PLP selection mode. Set the data PLP Id. */
1862                 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1863         }
1864         /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1865         cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1866         return 0;
1867 }
1868
1869 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1870                                                 u32 bandwidth)
1871 {
1872         u32 iffreq;
1873         u8 data[MAX_WRITE_REGSIZE];
1874
1875         const uint8_t nominalRate8bw[3][5] = {
1876                 /* TRCG Nominal Rate [37:0] */
1877                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1878                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1879                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
1880         };
1881
1882         const uint8_t nominalRate7bw[3][5] = {
1883                 /* TRCG Nominal Rate [37:0] */
1884                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1885                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1886                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
1887         };
1888
1889         const uint8_t nominalRate6bw[3][5] = {
1890                 /* TRCG Nominal Rate [37:0] */
1891                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
1892                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1893                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
1894         };
1895
1896         const uint8_t nominalRate5bw[3][5] = {
1897                 /* TRCG Nominal Rate [37:0] */
1898                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
1899                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
1900                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
1901         };
1902
1903         const uint8_t nominalRate17bw[3][5] = {
1904                 /* TRCG Nominal Rate [37:0] */
1905                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
1906                 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
1907                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}  /* 41MHz XTal */
1908         };
1909
1910         const uint8_t itbCoef8bw[3][14] = {
1911                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1912                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
1913                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
1914                         0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
1915                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1916                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
1917         };
1918
1919         const uint8_t itbCoef7bw[3][14] = {
1920                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1921                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
1922                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
1923                         0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
1924                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1925                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
1926         };
1927
1928         const uint8_t itbCoef6bw[3][14] = {
1929                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1930                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1931                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1932                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
1933                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1934                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
1935         };
1936
1937         const uint8_t itbCoef5bw[3][14] = {
1938                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1939                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1940                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1941                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
1942                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1943                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
1944         };
1945
1946         const uint8_t itbCoef17bw[3][14] = {
1947                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
1948                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
1949                 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
1950                         0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal   */
1951                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
1952                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}  /* 41MHz XTal   */
1953         };
1954
1955         /* Set SLV-T Bank : 0x20 */
1956         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1957
1958         switch (bandwidth) {
1959         case 8000000:
1960                 /* <Timing Recovery setting> */
1961                 cxd2841er_write_regs(priv, I2C_SLVT,
1962                                 0x9F, nominalRate8bw[priv->xtal], 5);
1963
1964                 /* Set SLV-T Bank : 0x27 */
1965                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1966                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
1967                                 0x7a, 0x00, 0x0f);
1968
1969                 /* Set SLV-T Bank : 0x10 */
1970                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1971
1972                 /* Group delay equaliser settings for
1973                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
1974                  */
1975                 cxd2841er_write_regs(priv, I2C_SLVT,
1976                                 0xA6, itbCoef8bw[priv->xtal], 14);
1977                 /* <IF freq setting> */
1978                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
1979                 data[0] = (u8) ((iffreq >> 16) & 0xff);
1980                 data[1] = (u8)((iffreq >> 8) & 0xff);
1981                 data[2] = (u8)(iffreq & 0xff);
1982                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
1983                 /* System bandwidth setting */
1984                 cxd2841er_set_reg_bits(
1985                                 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
1986                 break;
1987         case 7000000:
1988                 /* <Timing Recovery setting> */
1989                 cxd2841er_write_regs(priv, I2C_SLVT,
1990                                 0x9F, nominalRate7bw[priv->xtal], 5);
1991
1992                 /* Set SLV-T Bank : 0x27 */
1993                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1994                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
1995                                 0x7a, 0x00, 0x0f);
1996
1997                 /* Set SLV-T Bank : 0x10 */
1998                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1999
2000                 /* Group delay equaliser settings for
2001                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2002                  */
2003                 cxd2841er_write_regs(priv, I2C_SLVT,
2004                                 0xA6, itbCoef7bw[priv->xtal], 14);
2005                 /* <IF freq setting> */
2006                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2007                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2008                 data[1] = (u8)((iffreq >> 8) & 0xff);
2009                 data[2] = (u8)(iffreq & 0xff);
2010                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2011                 /* System bandwidth setting */
2012                 cxd2841er_set_reg_bits(
2013                                 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2014                 break;
2015         case 6000000:
2016                 /* <Timing Recovery setting> */
2017                 cxd2841er_write_regs(priv, I2C_SLVT,
2018                                 0x9F, nominalRate6bw[priv->xtal], 5);
2019
2020                 /* Set SLV-T Bank : 0x27 */
2021                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2022                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2023                                 0x7a, 0x00, 0x0f);
2024
2025                 /* Set SLV-T Bank : 0x10 */
2026                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2027
2028                 /* Group delay equaliser settings for
2029                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2030                  */
2031                 cxd2841er_write_regs(priv, I2C_SLVT,
2032                                 0xA6, itbCoef6bw[priv->xtal], 14);
2033                 /* <IF freq setting> */
2034                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2035                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2036                 data[1] = (u8)((iffreq >> 8) & 0xff);
2037                 data[2] = (u8)(iffreq & 0xff);
2038                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2039                 /* System bandwidth setting */
2040                 cxd2841er_set_reg_bits(
2041                                 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2042                 break;
2043         case 5000000:
2044                 /* <Timing Recovery setting> */
2045                 cxd2841er_write_regs(priv, I2C_SLVT,
2046                                 0x9F, nominalRate5bw[priv->xtal], 5);
2047
2048                 /* Set SLV-T Bank : 0x27 */
2049                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2050                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2051                                 0x7a, 0x00, 0x0f);
2052
2053                 /* Set SLV-T Bank : 0x10 */
2054                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2055
2056                 /* Group delay equaliser settings for
2057                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2058                  */
2059                 cxd2841er_write_regs(priv, I2C_SLVT,
2060                                 0xA6, itbCoef5bw[priv->xtal], 14);
2061                 /* <IF freq setting> */
2062                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2063                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2064                 data[1] = (u8)((iffreq >> 8) & 0xff);
2065                 data[2] = (u8)(iffreq & 0xff);
2066                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2067                 /* System bandwidth setting */
2068                 cxd2841er_set_reg_bits(
2069                                 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2070                 break;
2071         case 1712000:
2072                 /* <Timing Recovery setting> */
2073                 cxd2841er_write_regs(priv, I2C_SLVT,
2074                                 0x9F, nominalRate17bw[priv->xtal], 5);
2075
2076                 /* Set SLV-T Bank : 0x27 */
2077                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2078                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2079                                 0x7a, 0x03, 0x0f);
2080
2081                 /* Set SLV-T Bank : 0x10 */
2082                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2083
2084                 /* Group delay equaliser settings for
2085                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2086                  */
2087                 cxd2841er_write_regs(priv, I2C_SLVT,
2088                                 0xA6, itbCoef17bw[priv->xtal], 14);
2089                 /* <IF freq setting> */
2090                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.50);
2091                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2092                 data[1] = (u8)((iffreq >> 8) & 0xff);
2093                 data[2] = (u8)(iffreq & 0xff);
2094                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2095                 /* System bandwidth setting */
2096                 cxd2841er_set_reg_bits(
2097                                 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2098                 break;
2099         default:
2100                 return -EINVAL;
2101         }
2102         return 0;
2103 }
2104
2105 static int cxd2841er_sleep_tc_to_active_t_band(
2106                 struct cxd2841er_priv *priv, u32 bandwidth)
2107 {
2108         u8 data[MAX_WRITE_REGSIZE];
2109         u32 iffreq;
2110         u8 nominalRate8bw[3][5] = {
2111                 /* TRCG Nominal Rate [37:0] */
2112                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2113                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2114                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2115         };
2116         u8 nominalRate7bw[3][5] = {
2117                 /* TRCG Nominal Rate [37:0] */
2118                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2119                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2120                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2121         };
2122         u8 nominalRate6bw[3][5] = {
2123                 /* TRCG Nominal Rate [37:0] */
2124                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2125                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2126                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2127         };
2128         u8 nominalRate5bw[3][5] = {
2129                 /* TRCG Nominal Rate [37:0] */
2130                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2131                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2132                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2133         };
2134
2135         u8 itbCoef8bw[3][14] = {
2136                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2137                         0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2138                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2139                         0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2140                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2141                         0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2142         };
2143         u8 itbCoef7bw[3][14] = {
2144                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2145                         0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2146                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2147                         0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2148                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2149                         0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2150         };
2151         u8 itbCoef6bw[3][14] = {
2152                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2153                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2154                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2155                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2156                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2157                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2158         };
2159         u8 itbCoef5bw[3][14] = {
2160                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2161                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2162                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2163                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2164                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2165                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2166         };
2167
2168         /* Set SLV-T Bank : 0x13 */
2169         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2170         /* Echo performance optimization setting */
2171         data[0] = 0x01;
2172         data[1] = 0x14;
2173         cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2174
2175         /* Set SLV-T Bank : 0x10 */
2176         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2177
2178         switch (bandwidth) {
2179         case 8000000:
2180                 /* <Timing Recovery setting> */
2181                 cxd2841er_write_regs(priv, I2C_SLVT,
2182                                 0x9F, nominalRate8bw[priv->xtal], 5);
2183                 /* Group delay equaliser settings for
2184                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2185                 */
2186                 cxd2841er_write_regs(priv, I2C_SLVT,
2187                                 0xA6, itbCoef8bw[priv->xtal], 14);
2188                 /* <IF freq setting> */
2189                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2190                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2191                 data[1] = (u8)((iffreq >> 8) & 0xff);
2192                 data[2] = (u8)(iffreq & 0xff);
2193                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2194                 /* System bandwidth setting */
2195                 cxd2841er_set_reg_bits(
2196                         priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2197
2198                 /* Demod core latency setting */
2199                 if (priv->xtal == SONY_XTAL_24000) {
2200                         data[0] = 0x15;
2201                         data[1] = 0x28;
2202                 } else {
2203                         data[0] = 0x01;
2204                         data[1] = 0xE0;
2205                 }
2206                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2207
2208                 /* Notch filter setting */
2209                 data[0] = 0x01;
2210                 data[1] = 0x02;
2211                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2212                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2213                 break;
2214         case 7000000:
2215                 /* <Timing Recovery setting> */
2216                 cxd2841er_write_regs(priv, I2C_SLVT,
2217                                 0x9F, nominalRate7bw[priv->xtal], 5);
2218                 /* Group delay equaliser settings for
2219                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2220                 */
2221                 cxd2841er_write_regs(priv, I2C_SLVT,
2222                                 0xA6, itbCoef7bw[priv->xtal], 14);
2223                 /* <IF freq setting> */
2224                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2225                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2226                 data[1] = (u8)((iffreq >> 8) & 0xff);
2227                 data[2] = (u8)(iffreq & 0xff);
2228                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2229                 /* System bandwidth setting */
2230                 cxd2841er_set_reg_bits(
2231                         priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2232
2233                 /* Demod core latency setting */
2234                 if (priv->xtal == SONY_XTAL_24000) {
2235                         data[0] = 0x1F;
2236                         data[1] = 0xF8;
2237                 } else {
2238                         data[0] = 0x12;
2239                         data[1] = 0xF8;
2240                 }
2241                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2242
2243                 /* Notch filter setting */
2244                 data[0] = 0x00;
2245                 data[1] = 0x03;
2246                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2247                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2248                 break;
2249         case 6000000:
2250                 /* <Timing Recovery setting> */
2251                 cxd2841er_write_regs(priv, I2C_SLVT,
2252                                 0x9F, nominalRate6bw[priv->xtal], 5);
2253                 /* Group delay equaliser settings for
2254                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2255                 */
2256                 cxd2841er_write_regs(priv, I2C_SLVT,
2257                                 0xA6, itbCoef6bw[priv->xtal], 14);
2258                 /* <IF freq setting> */
2259                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2260                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2261                 data[1] = (u8)((iffreq >> 8) & 0xff);
2262                 data[2] = (u8)(iffreq & 0xff);
2263                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2264                 /* System bandwidth setting */
2265                 cxd2841er_set_reg_bits(
2266                         priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2267
2268                 /* Demod core latency setting */
2269                 if (priv->xtal == SONY_XTAL_24000) {
2270                         data[0] = 0x25;
2271                         data[1] = 0x4C;
2272                 } else {
2273                         data[0] = 0x1F;
2274                         data[1] = 0xDC;
2275                 }
2276                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2277
2278                 /* Notch filter setting */
2279                 data[0] = 0x00;
2280                 data[1] = 0x03;
2281                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2282                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2283                 break;
2284         case 5000000:
2285                 /* <Timing Recovery setting> */
2286                 cxd2841er_write_regs(priv, I2C_SLVT,
2287                                 0x9F, nominalRate5bw[priv->xtal], 5);
2288                 /* Group delay equaliser settings for
2289                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2290                 */
2291                 cxd2841er_write_regs(priv, I2C_SLVT,
2292                                 0xA6, itbCoef5bw[priv->xtal], 14);
2293                 /* <IF freq setting> */
2294                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2295                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2296                 data[1] = (u8)((iffreq >> 8) & 0xff);
2297                 data[2] = (u8)(iffreq & 0xff);
2298                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2299                 /* System bandwidth setting */
2300                 cxd2841er_set_reg_bits(
2301                         priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2302
2303                 /* Demod core latency setting */
2304                 if (priv->xtal == SONY_XTAL_24000) {
2305                         data[0] = 0x2C;
2306                         data[1] = 0xC2;
2307                 } else {
2308                         data[0] = 0x26;
2309                         data[1] = 0x3C;
2310                 }
2311                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2312
2313                 /* Notch filter setting */
2314                 data[0] = 0x00;
2315                 data[1] = 0x03;
2316                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2317                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2318                 break;
2319         }
2320
2321         return 0;
2322 }
2323
2324 static int cxd2841er_sleep_tc_to_active_i_band(
2325                 struct cxd2841er_priv *priv, u32 bandwidth)
2326 {
2327         u32 iffreq;
2328         u8 data[3];
2329
2330         /* TRCG Nominal Rate */
2331         u8 nominalRate8bw[3][5] = {
2332                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2333                 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2334                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2335         };
2336
2337         u8 nominalRate7bw[3][5] = {
2338                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2339                 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2340                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2341         };
2342
2343         u8 nominalRate6bw[3][5] = {
2344                 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2345                 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2346                 {0x14, 0x2E, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2347         };
2348
2349         u8 itbCoef8bw[3][14] = {
2350                 {0x00}, /* 20.5MHz XTal */
2351                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2352                         0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2353                 {0x0}, /* 41MHz XTal   */
2354         };
2355
2356         u8 itbCoef7bw[3][14] = {
2357                 {0x00}, /* 20.5MHz XTal */
2358                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2359                         0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2360                 {0x00}, /* 41MHz XTal   */
2361         };
2362
2363         u8 itbCoef6bw[3][14] = {
2364                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2365                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2366                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2367                         0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal   */
2368                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2369                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal   */
2370         };
2371
2372         dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2373         /* Set SLV-T Bank : 0x10 */
2374         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2375
2376         /*  20.5/41MHz Xtal support is not available
2377          *  on ISDB-T 7MHzBW and 8MHzBW
2378         */
2379         if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2380                 dev_err(&priv->i2c->dev,
2381                         "%s(): bandwidth %d supported only for 24MHz xtal\n",
2382                         __func__, bandwidth);
2383                 return -EINVAL;
2384         }
2385
2386         switch (bandwidth) {
2387         case 8000000:
2388                 /* TRCG Nominal Rate */
2389                 cxd2841er_write_regs(priv, I2C_SLVT,
2390                                 0x9F, nominalRate8bw[priv->xtal], 5);
2391                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2392                 cxd2841er_write_regs(priv, I2C_SLVT,
2393                                 0xA6, itbCoef8bw[priv->xtal], 14);
2394
2395                 /* IF freq setting */
2396                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2397                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2398                 data[1] = (u8)((iffreq >> 8) & 0xff);
2399                 data[2] = (u8)(iffreq & 0xff);
2400                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2401
2402                 /* System bandwidth setting */
2403                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2404
2405                 /* Demod core latency setting */
2406                 data[0] = 0x13;
2407                 data[1] = 0xFC;
2408                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2409
2410                 /* Acquisition optimization setting */
2411                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2412                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2413                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2414                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2415                 break;
2416         case 7000000:
2417                 /* TRCG Nominal Rate */
2418                 cxd2841er_write_regs(priv, I2C_SLVT,
2419                                 0x9F, nominalRate7bw[priv->xtal], 5);
2420                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2421                 cxd2841er_write_regs(priv, I2C_SLVT,
2422                                 0xA6, itbCoef7bw[priv->xtal], 14);
2423
2424                 /* IF freq setting */
2425                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2426                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2427                 data[1] = (u8)((iffreq >> 8) & 0xff);
2428                 data[2] = (u8)(iffreq & 0xff);
2429                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2430
2431                 /* System bandwidth setting */
2432                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2433
2434                 /* Demod core latency setting */
2435                 data[0] = 0x1A;
2436                 data[1] = 0xFA;
2437                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2438
2439                 /* Acquisition optimization setting */
2440                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2441                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2442                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2443                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2444                 break;
2445         case 6000000:
2446                 /* TRCG Nominal Rate */
2447                 cxd2841er_write_regs(priv, I2C_SLVT,
2448                                 0x9F, nominalRate6bw[priv->xtal], 5);
2449                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2450                 cxd2841er_write_regs(priv, I2C_SLVT,
2451                                 0xA6, itbCoef6bw[priv->xtal], 14);
2452
2453                 /* IF freq setting */
2454                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2455                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2456                 data[1] = (u8)((iffreq >> 8) & 0xff);
2457                 data[2] = (u8)(iffreq & 0xff);
2458                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2459
2460                 /* System bandwidth setting */
2461                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2462
2463                 /* Demod core latency setting */
2464                 if (priv->xtal == SONY_XTAL_24000) {
2465                         data[0] = 0x1F;
2466                         data[1] = 0x79;
2467                 } else {
2468                         data[0] = 0x1A;
2469                         data[1] = 0xE2;
2470                 }
2471                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2472
2473                 /* Acquisition optimization setting */
2474                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2475                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2476                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2477                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2478                 break;
2479         default:
2480                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2481                                 __func__, bandwidth);
2482                 return -EINVAL;
2483         }
2484         return 0;
2485 }
2486
2487 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2488                                                u32 bandwidth)
2489 {
2490         u8 bw7_8mhz_b10_a6[] = {
2491                 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2492                 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2493         u8 bw6mhz_b10_a6[] = {
2494                 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2495                 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2496         u8 b10_b6[3];
2497         u32 iffreq;
2498
2499         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2500         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2501         switch (bandwidth) {
2502         case 8000000:
2503         case 7000000:
2504                 cxd2841er_write_regs(
2505                         priv, I2C_SLVT, 0xa6,
2506                         bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2507                 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2508                 break;
2509         case 6000000:
2510                 cxd2841er_write_regs(
2511                         priv, I2C_SLVT, 0xa6,
2512                         bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2513                 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2514                 break;
2515         default:
2516                 dev_dbg(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2517                         __func__, bandwidth);
2518                 return -EINVAL;
2519         }
2520         /* <IF freq setting> */
2521         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2522         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2523         b10_b6[2] = (u8)(iffreq & 0xff);
2524         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2525         /* Set SLV-T Bank : 0x11 */
2526         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2527         switch (bandwidth) {
2528         case 8000000:
2529         case 7000000:
2530                 cxd2841er_set_reg_bits(
2531                         priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2532                 break;
2533         case 6000000:
2534                 cxd2841er_set_reg_bits(
2535                         priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2536                 break;
2537         }
2538         /* Set SLV-T Bank : 0x40 */
2539         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2540         switch (bandwidth) {
2541         case 8000000:
2542                 cxd2841er_set_reg_bits(
2543                         priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2544                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x3e);
2545                 break;
2546         case 7000000:
2547                 cxd2841er_set_reg_bits(
2548                         priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2549                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0xd6);
2550                 break;
2551         case 6000000:
2552                 cxd2841er_set_reg_bits(
2553                         priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2554                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x6e);
2555                 break;
2556         }
2557         return 0;
2558 }
2559
2560 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2561                                           u32 bandwidth)
2562 {
2563         u8 data[2] = { 0x09, 0x54 };
2564         u8 data24m[3] = {0xDC, 0x6C, 0x00};
2565
2566         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2567         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2568         /* Set SLV-X Bank : 0x00 */
2569         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2570         /* Set demod mode */
2571         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2572         /* Set SLV-T Bank : 0x00 */
2573         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2574         /* Enable demod clock */
2575         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2576         /* Disable RF level monitor */
2577         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2578         /* Enable ADC clock */
2579         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2580         /* Enable ADC 1 */
2581         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2582         /* Enable ADC 2 & 3 */
2583         if (priv->xtal == SONY_XTAL_41000) {
2584                 data[0] = 0x0A;
2585                 data[1] = 0xD4;
2586         }
2587         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2588         /* Enable ADC 4 */
2589         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2590         /* Set SLV-T Bank : 0x10 */
2591         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2592         /* IFAGC gain settings */
2593         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2594         /* Set SLV-T Bank : 0x11 */
2595         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2596         /* BBAGC TARGET level setting */
2597         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2598         /* Set SLV-T Bank : 0x10 */
2599         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2600         /* ASCOT setting ON */
2601         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2602         /* Set SLV-T Bank : 0x18 */
2603         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2604         /* Pre-RS BER moniter setting */
2605         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2606         /* FEC Auto Recovery setting */
2607         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2608         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2609         /* Set SLV-T Bank : 0x00 */
2610         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2611         /* TSIF setting */
2612         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2613         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2614
2615         if (priv->xtal == SONY_XTAL_24000) {
2616                 /* Set SLV-T Bank : 0x10 */
2617                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2618                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2619                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2620                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2621         }
2622
2623         cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2624         /* Set SLV-T Bank : 0x00 */
2625         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2626         /* Disable HiZ Setting 1 */
2627         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2628         /* Disable HiZ Setting 2 */
2629         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2630         priv->state = STATE_ACTIVE_TC;
2631         return 0;
2632 }
2633
2634 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2635                                            u32 bandwidth)
2636 {
2637         u8 data[MAX_WRITE_REGSIZE];
2638
2639         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2640         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2641         /* Set SLV-X Bank : 0x00 */
2642         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2643         /* Set demod mode */
2644         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2645         /* Set SLV-T Bank : 0x00 */
2646         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2647         /* Enable demod clock */
2648         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2649         /* Disable RF level monitor */
2650         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2651         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2652         /* Enable ADC clock */
2653         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2654         /* Enable ADC 1 */
2655         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2656
2657         if (priv->xtal == SONY_XTAL_41000) {
2658                 data[0] = 0x0A;
2659                 data[1] = 0xD4;
2660         } else {
2661                 data[0] = 0x09;
2662                 data[1] = 0x54;
2663         }
2664
2665         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2666         /* Enable ADC 4 */
2667         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2668         /* Set SLV-T Bank : 0x10 */
2669         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2670         /* IFAGC gain settings */
2671         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2672         /* Set SLV-T Bank : 0x11 */
2673         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2674         /* BBAGC TARGET level setting */
2675         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2676         /* Set SLV-T Bank : 0x10 */
2677         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2678         /* ASCOT setting ON */
2679         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2680         /* Set SLV-T Bank : 0x20 */
2681         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2682         /* Acquisition optimization setting */
2683         cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2684         /* Set SLV-T Bank : 0x2b */
2685         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2686         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2687         /* Set SLV-T Bank : 0x23 */
2688         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2689         /* L1 Control setting */
2690         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
2691         /* Set SLV-T Bank : 0x00 */
2692         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2693         /* TSIF setting */
2694         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2695         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2696         /* DVB-T2 initial setting */
2697         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2698         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2699         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2700         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2701         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2702         /* Set SLV-T Bank : 0x2a */
2703         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2704         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2705         /* Set SLV-T Bank : 0x2b */
2706         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2707         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2708
2709         /* 24MHz Xtal setting */
2710         if (priv->xtal == SONY_XTAL_24000) {
2711                 /* Set SLV-T Bank : 0x11 */
2712                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2713                 data[0] = 0xEB;
2714                 data[1] = 0x03;
2715                 data[2] = 0x3B;
2716                 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
2717
2718                 /* Set SLV-T Bank : 0x20 */
2719                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2720                 data[0] = 0x5E;
2721                 data[1] = 0x5E;
2722                 data[2] = 0x47;
2723                 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
2724
2725                 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
2726
2727                 data[0] = 0x3F;
2728                 data[1] = 0xFF;
2729                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2730
2731                 /* Set SLV-T Bank : 0x24 */
2732                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
2733                 data[0] = 0x0B;
2734                 data[1] = 0x72;
2735                 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
2736
2737                 data[0] = 0x93;
2738                 data[1] = 0xF3;
2739                 data[2] = 0x00;
2740                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
2741
2742                 data[0] = 0x05;
2743                 data[1] = 0xB8;
2744                 data[2] = 0xD8;
2745                 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
2746
2747                 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
2748
2749                 /* Set SLV-T Bank : 0x25 */
2750                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
2751                 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
2752
2753                 /* Set SLV-T Bank : 0x27 */
2754                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2755                 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
2756
2757                 /* Set SLV-T Bank : 0x2B */
2758                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
2759                 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
2760                 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
2761
2762                 /* Set SLV-T Bank : 0x2D */
2763                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
2764                 data[0] = 0x89;
2765                 data[1] = 0x89;
2766                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
2767
2768                 /* Set SLV-T Bank : 0x5E */
2769                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
2770                 data[0] = 0x24;
2771                 data[1] = 0x95;
2772                 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
2773         }
2774
2775         cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2776
2777         /* Set SLV-T Bank : 0x00 */
2778         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2779         /* Disable HiZ Setting 1 */
2780         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2781         /* Disable HiZ Setting 2 */
2782         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2783         priv->state = STATE_ACTIVE_TC;
2784         return 0;
2785 }
2786
2787 /* ISDB-Tb part */
2788 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
2789                 u32 bandwidth)
2790 {
2791         u8 data[2] = { 0x09, 0x54 };
2792         u8 data24m[2] = {0x60, 0x00};
2793         u8 data24m2[3] = {0xB7, 0x1B, 0x00};
2794
2795         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2796         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2797         /* Set SLV-X Bank : 0x00 */
2798         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2799         /* Set demod mode */
2800         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
2801         /* Set SLV-T Bank : 0x00 */
2802         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2803         /* Enable demod clock */
2804         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2805         /* Enable RF level monitor */
2806         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
2807         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
2808         /* Enable ADC clock */
2809         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2810         /* Enable ADC 1 */
2811         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2812         /* xtal freq 20.5MHz or 24M */
2813         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2814         /* Enable ADC 4 */
2815         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2816         /* ASCOT setting ON */
2817         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2818         /* FEC Auto Recovery setting */
2819         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2820         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
2821         /* ISDB-T initial setting */
2822         /* Set SLV-T Bank : 0x00 */
2823         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2824         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
2825         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
2826         /* Set SLV-T Bank : 0x10 */
2827         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2828         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
2829         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
2830         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
2831         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
2832         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
2833         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
2834         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
2835         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
2836         /* Set SLV-T Bank : 0x15 */
2837         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2838         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
2839         /* Set SLV-T Bank : 0x1E */
2840         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
2841         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
2842         /* Set SLV-T Bank : 0x63 */
2843         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
2844         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
2845
2846         /* for xtal 24MHz */
2847         /* Set SLV-T Bank : 0x10 */
2848         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2849         cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
2850         /* Set SLV-T Bank : 0x60 */
2851         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
2852         cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
2853
2854         cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
2855         /* Set SLV-T Bank : 0x00 */
2856         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2857         /* Disable HiZ Setting 1 */
2858         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2859         /* Disable HiZ Setting 2 */
2860         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2861         priv->state = STATE_ACTIVE_TC;
2862         return 0;
2863 }
2864
2865 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2866                                           u32 bandwidth)
2867 {
2868         u8 data[2] = { 0x09, 0x54 };
2869
2870         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2871         cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2872         /* Set SLV-X Bank : 0x00 */
2873         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2874         /* Set demod mode */
2875         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2876         /* Set SLV-T Bank : 0x00 */
2877         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2878         /* Enable demod clock */
2879         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2880         /* Disable RF level monitor */
2881         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2882         /* Enable ADC clock */
2883         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2884         /* Enable ADC 1 */
2885         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2886         /* xtal freq 20.5MHz */
2887         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2888         /* Enable ADC 4 */
2889         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2890         /* Set SLV-T Bank : 0x10 */
2891         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2892         /* IFAGC gain settings */
2893         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2894         /* Set SLV-T Bank : 0x11 */
2895         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2896         /* BBAGC TARGET level setting */
2897         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2898         /* Set SLV-T Bank : 0x10 */
2899         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2900         /* ASCOT setting ON */
2901         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2902         /* Set SLV-T Bank : 0x40 */
2903         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2904         /* Demod setting */
2905         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2906         /* Set SLV-T Bank : 0x00 */
2907         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2908         /* TSIF setting */
2909         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2910         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2911
2912         cxd2841er_sleep_tc_to_active_c_band(priv, 8000000);
2913         /* Set SLV-T Bank : 0x00 */
2914         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2915         /* Disable HiZ Setting 1 */
2916         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2917         /* Disable HiZ Setting 2 */
2918         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2919         priv->state = STATE_ACTIVE_TC;
2920         return 0;
2921 }
2922
2923 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
2924                                   struct dtv_frontend_properties *p)
2925 {
2926         enum fe_status status = 0;
2927         u16 strength = 0, snr = 0;
2928         u32 errors = 0, ber = 0;
2929         struct cxd2841er_priv *priv = fe->demodulator_priv;
2930
2931         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2932         if (priv->state == STATE_ACTIVE_S)
2933                 cxd2841er_read_status_s(fe, &status);
2934         else if (priv->state == STATE_ACTIVE_TC)
2935                 cxd2841er_read_status_tc(fe, &status);
2936
2937         if (status & FE_HAS_LOCK) {
2938                 cxd2841er_read_signal_strength(fe, &strength);
2939                 p->strength.len = 1;
2940                 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2941                 p->strength.stat[0].uvalue = strength;
2942                 cxd2841er_read_snr(fe, &snr);
2943                 p->cnr.len = 1;
2944                 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2945                 p->cnr.stat[0].svalue = snr;
2946                 cxd2841er_read_ucblocks(fe, &errors);
2947                 p->block_error.len = 1;
2948                 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2949                 p->block_error.stat[0].uvalue = errors;
2950                 cxd2841er_read_ber(fe, &ber);
2951                 p->post_bit_error.len = 1;
2952                 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
2953                 p->post_bit_error.stat[0].uvalue = ber;
2954         } else {
2955                 p->strength.len = 1;
2956                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2957                 p->cnr.len = 1;
2958                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2959                 p->block_error.len = 1;
2960                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2961                 p->post_bit_error.len = 1;
2962                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2963         }
2964         return 0;
2965 }
2966
2967 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2968 {
2969         int ret = 0, i, timeout, carr_offset;
2970         enum fe_status status;
2971         struct cxd2841er_priv *priv = fe->demodulator_priv;
2972         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2973         u32 symbol_rate = p->symbol_rate/1000;
2974
2975         dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
2976                 __func__,
2977                 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
2978                  p->frequency, symbol_rate, priv->xtal);
2979         switch (priv->state) {
2980         case STATE_SLEEP_S:
2981                 ret = cxd2841er_sleep_s_to_active_s(
2982                         priv, p->delivery_system, symbol_rate);
2983                 break;
2984         case STATE_ACTIVE_S:
2985                 ret = cxd2841er_retune_active(priv, p);
2986                 break;
2987         default:
2988                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2989                         __func__, priv->state);
2990                 ret = -EINVAL;
2991                 goto done;
2992         }
2993         if (ret) {
2994                 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
2995                 goto done;
2996         }
2997         if (fe->ops.i2c_gate_ctrl)
2998                 fe->ops.i2c_gate_ctrl(fe, 1);
2999         if (fe->ops.tuner_ops.set_params)
3000                 fe->ops.tuner_ops.set_params(fe);
3001         if (fe->ops.i2c_gate_ctrl)
3002                 fe->ops.i2c_gate_ctrl(fe, 0);
3003         cxd2841er_tune_done(priv);
3004         timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3005         for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3006                 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3007                         (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3008                 cxd2841er_read_status_s(fe, &status);
3009                 if (status & FE_HAS_LOCK)
3010                         break;
3011         }
3012         if (status & FE_HAS_LOCK) {
3013                 if (cxd2841er_get_carrier_offset_s_s2(
3014                                 priv, &carr_offset)) {
3015                         ret = -EINVAL;
3016                         goto done;
3017                 }
3018                 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3019                         __func__, carr_offset);
3020         }
3021 done:
3022         return ret;
3023 }
3024
3025 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3026 {
3027         int ret = 0, timeout;
3028         enum fe_status status;
3029         struct cxd2841er_priv *priv = fe->demodulator_priv;
3030         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3031
3032         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3033         if (p->delivery_system == SYS_DVBT) {
3034                 priv->system = SYS_DVBT;
3035                 switch (priv->state) {
3036                 case STATE_SLEEP_TC:
3037                         ret = cxd2841er_sleep_tc_to_active_t(
3038                                 priv, p->bandwidth_hz);
3039                         break;
3040                 case STATE_ACTIVE_TC:
3041                         ret = cxd2841er_retune_active(priv, p);
3042                         break;
3043                 default:
3044                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3045                                 __func__, priv->state);
3046                         ret = -EINVAL;
3047                 }
3048         } else if (p->delivery_system == SYS_DVBT2) {
3049                 priv->system = SYS_DVBT2;
3050                 cxd2841er_dvbt2_set_plp_config(priv,
3051                         (int)(p->stream_id > 255), p->stream_id);
3052                 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3053                 switch (priv->state) {
3054                 case STATE_SLEEP_TC:
3055                         ret = cxd2841er_sleep_tc_to_active_t2(priv,
3056                                 p->bandwidth_hz);
3057                         break;
3058                 case STATE_ACTIVE_TC:
3059                         ret = cxd2841er_retune_active(priv, p);
3060                         break;
3061                 default:
3062                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3063                                 __func__, priv->state);
3064                         ret = -EINVAL;
3065                 }
3066         } else if (p->delivery_system == SYS_ISDBT) {
3067                 priv->system = SYS_ISDBT;
3068                 switch (priv->state) {
3069                 case STATE_SLEEP_TC:
3070                         ret = cxd2841er_sleep_tc_to_active_i(
3071                                         priv, p->bandwidth_hz);
3072                         break;
3073                 case STATE_ACTIVE_TC:
3074                         ret = cxd2841er_retune_active(priv, p);
3075                         break;
3076                 default:
3077                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3078                                         __func__, priv->state);
3079                         ret = -EINVAL;
3080                 }
3081         } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3082                         p->delivery_system == SYS_DVBC_ANNEX_C) {
3083                 priv->system = SYS_DVBC_ANNEX_A;
3084                 switch (priv->state) {
3085                 case STATE_SLEEP_TC:
3086                         ret = cxd2841er_sleep_tc_to_active_c(
3087                                 priv, p->bandwidth_hz);
3088                         break;
3089                 case STATE_ACTIVE_TC:
3090                         ret = cxd2841er_retune_active(priv, p);
3091                         break;
3092                 default:
3093                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3094                                 __func__, priv->state);
3095                         ret = -EINVAL;
3096                 }
3097         } else {
3098                 dev_dbg(&priv->i2c->dev,
3099                         "%s(): invalid delivery system %d\n",
3100                         __func__, p->delivery_system);
3101                 ret = -EINVAL;
3102         }
3103         if (ret)
3104                 goto done;
3105         if (fe->ops.i2c_gate_ctrl)
3106                 fe->ops.i2c_gate_ctrl(fe, 1);
3107         if (fe->ops.tuner_ops.set_params)
3108                 fe->ops.tuner_ops.set_params(fe);
3109         if (fe->ops.i2c_gate_ctrl)
3110                 fe->ops.i2c_gate_ctrl(fe, 0);
3111         cxd2841er_tune_done(priv);
3112         timeout = 2500;
3113         while (timeout > 0) {
3114                 ret = cxd2841er_read_status_tc(fe, &status);
3115                 if (ret)
3116                         goto done;
3117                 if (status & FE_HAS_LOCK)
3118                         break;
3119                 msleep(20);
3120                 timeout -= 20;
3121         }
3122         if (timeout < 0)
3123                 dev_dbg(&priv->i2c->dev,
3124                         "%s(): LOCK wait timeout\n", __func__);
3125 done:
3126         return ret;
3127 }
3128
3129 static int cxd2841er_tune_s(struct dvb_frontend *fe,
3130                             bool re_tune,
3131                             unsigned int mode_flags,
3132                             unsigned int *delay,
3133                             enum fe_status *status)
3134 {
3135         int ret, carrier_offset;
3136         struct cxd2841er_priv *priv = fe->demodulator_priv;
3137         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3138
3139         dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3140         if (re_tune) {
3141                 ret = cxd2841er_set_frontend_s(fe);
3142                 if (ret)
3143                         return ret;
3144                 cxd2841er_read_status_s(fe, status);
3145                 if (*status & FE_HAS_LOCK) {
3146                         if (cxd2841er_get_carrier_offset_s_s2(
3147                                         priv, &carrier_offset))
3148                                 return -EINVAL;
3149                         p->frequency += carrier_offset;
3150                         ret = cxd2841er_set_frontend_s(fe);
3151                         if (ret)
3152                                 return ret;
3153                 }
3154         }
3155         *delay = HZ / 5;
3156         return cxd2841er_read_status_s(fe, status);
3157 }
3158
3159 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3160                              bool re_tune,
3161                              unsigned int mode_flags,
3162                              unsigned int *delay,
3163                              enum fe_status *status)
3164 {
3165         int ret, carrier_offset;
3166         struct cxd2841er_priv *priv = fe->demodulator_priv;
3167         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3168
3169         dev_dbg(&priv->i2c->dev, "%s(): re_tune %d\n", __func__, re_tune);
3170         if (re_tune) {
3171                 ret = cxd2841er_set_frontend_tc(fe);
3172                 if (ret)
3173                         return ret;
3174                 cxd2841er_read_status_tc(fe, status);
3175                 if (*status & FE_HAS_LOCK) {
3176                         switch (priv->system) {
3177                         case SYS_ISDBT:
3178                                 ret = cxd2841er_get_carrier_offset_i(
3179                                                 priv, p->bandwidth_hz,
3180                                                 &carrier_offset);
3181                                 break;
3182                         case SYS_DVBT:
3183                                 ret = cxd2841er_get_carrier_offset_t(
3184                                         priv, p->bandwidth_hz,
3185                                         &carrier_offset);
3186                                 break;
3187                         case SYS_DVBT2:
3188                                 ret = cxd2841er_get_carrier_offset_t2(
3189                                         priv, p->bandwidth_hz,
3190                                         &carrier_offset);
3191                                 break;
3192                         case SYS_DVBC_ANNEX_A:
3193                                 ret = cxd2841er_get_carrier_offset_c(
3194                                         priv, &carrier_offset);
3195                                 break;
3196                         default:
3197                                 dev_dbg(&priv->i2c->dev,
3198                                         "%s(): invalid delivery system %d\n",
3199                                         __func__, priv->system);
3200                                 return -EINVAL;
3201                         }
3202                         if (ret)
3203                                 return ret;
3204                         dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3205                                 __func__, carrier_offset);
3206                         p->frequency += carrier_offset;
3207                         ret = cxd2841er_set_frontend_tc(fe);
3208                         if (ret)
3209                                 return ret;
3210                 }
3211         }
3212         *delay = HZ / 5;
3213         return cxd2841er_read_status_tc(fe, status);
3214 }
3215
3216 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3217 {
3218         struct cxd2841er_priv *priv = fe->demodulator_priv;
3219
3220         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3221         cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3222         cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3223         return 0;
3224 }
3225
3226 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3227 {
3228         struct cxd2841er_priv *priv = fe->demodulator_priv;
3229
3230         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3231         if (priv->state == STATE_ACTIVE_TC) {
3232                 switch (priv->system) {
3233                 case SYS_DVBT:
3234                         cxd2841er_active_t_to_sleep_tc(priv);
3235                         break;
3236                 case SYS_DVBT2:
3237                         cxd2841er_active_t2_to_sleep_tc(priv);
3238                         break;
3239                 case SYS_ISDBT:
3240                         cxd2841er_active_i_to_sleep_tc(priv);
3241                         break;
3242                 case SYS_DVBC_ANNEX_A:
3243                         cxd2841er_active_c_to_sleep_tc(priv);
3244                         break;
3245                 default:
3246                         dev_warn(&priv->i2c->dev,
3247                                 "%s(): unknown delivery system %d\n",
3248                                 __func__, priv->system);
3249                 }
3250         }
3251         if (priv->state != STATE_SLEEP_TC) {
3252                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3253                         __func__, priv->state);
3254                 return -EINVAL;
3255         }
3256         cxd2841er_sleep_tc_to_shutdown(priv);
3257         return 0;
3258 }
3259
3260 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3261                                 enum fe_sec_mini_cmd burst)
3262 {
3263         u8 data;
3264         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3265
3266         dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3267                 (burst == SEC_MINI_A ? "A" : "B"));
3268         if (priv->state != STATE_SLEEP_S &&
3269                         priv->state != STATE_ACTIVE_S) {
3270                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3271                         __func__, priv->state);
3272                 return -EINVAL;
3273         }
3274         data = (burst == SEC_MINI_A ? 0 : 1);
3275         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3276         cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3277         cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3278         return 0;
3279 }
3280
3281 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3282                               enum fe_sec_tone_mode tone)
3283 {
3284         u8 data;
3285         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3286
3287         dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3288                 (tone == SEC_TONE_ON ? "On" : "Off"));
3289         if (priv->state != STATE_SLEEP_S &&
3290                         priv->state != STATE_ACTIVE_S) {
3291                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3292                         __func__, priv->state);
3293                 return -EINVAL;
3294         }
3295         data = (tone == SEC_TONE_ON ? 1 : 0);
3296         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3297         cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3298         return 0;
3299 }
3300
3301 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3302                                      struct dvb_diseqc_master_cmd *cmd)
3303 {
3304         int i;
3305         u8 data[12];
3306         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3307
3308         if (priv->state != STATE_SLEEP_S &&
3309                         priv->state != STATE_ACTIVE_S) {
3310                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3311                         __func__, priv->state);
3312                 return -EINVAL;
3313         }
3314         dev_dbg(&priv->i2c->dev,
3315                 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3316         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3317         /* DiDEqC enable */
3318         cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3319         /* cmd1 length & data */
3320         cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3321         memset(data, 0, sizeof(data));
3322         for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3323                 data[i] = cmd->msg[i];
3324         cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3325         /* repeat count for cmd1 */
3326         cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3327         /* repeat count for cmd2: always 0 */
3328         cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3329         /* start transmit */
3330         cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3331         /* wait for 1 sec timeout */
3332         for (i = 0; i < 50; i++) {
3333                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3334                 if (!data[0]) {
3335                         dev_dbg(&priv->i2c->dev,
3336                                 "%s(): DiSEqC cmd has been sent\n", __func__);
3337                         return 0;
3338                 }
3339                 msleep(20);
3340         }
3341         dev_dbg(&priv->i2c->dev,
3342                 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3343         return -ETIMEDOUT;
3344 }
3345
3346 static void cxd2841er_release(struct dvb_frontend *fe)
3347 {
3348         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3349
3350         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3351         kfree(priv);
3352 }
3353
3354 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3355 {
3356         struct cxd2841er_priv *priv = fe->demodulator_priv;
3357
3358         dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3359         cxd2841er_set_reg_bits(
3360                 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3361         return 0;
3362 }
3363
3364 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3365 {
3366         struct cxd2841er_priv *priv = fe->demodulator_priv;
3367
3368         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3369         return DVBFE_ALGO_HW;
3370 }
3371
3372 static int cxd2841er_init_s(struct dvb_frontend *fe)
3373 {
3374         struct cxd2841er_priv *priv = fe->demodulator_priv;
3375
3376         /* sanity. force demod to SHUTDOWN state */
3377         if (priv->state == STATE_SLEEP_S) {
3378                 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3379                                 __func__);
3380                 cxd2841er_sleep_s_to_shutdown(priv);
3381         } else if (priv->state == STATE_ACTIVE_S) {
3382                 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3383                                 __func__);
3384                 cxd2841er_active_s_to_sleep_s(priv);
3385                 cxd2841er_sleep_s_to_shutdown(priv);
3386         }
3387
3388         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3389         cxd2841er_shutdown_to_sleep_s(priv);
3390         /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3391         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3392         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3393         return 0;
3394 }
3395
3396 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3397 {
3398         struct cxd2841er_priv *priv = fe->demodulator_priv;
3399
3400         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3401         cxd2841er_shutdown_to_sleep_tc(priv);
3402         /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3403         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3404         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3405         /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3406         cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3407         /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3408         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3409         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
3410         return 0;
3411 }
3412
3413 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3414 static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops;
3415 static struct dvb_frontend_ops cxd2841er_dvbc_ops;
3416 static struct dvb_frontend_ops cxd2841er_isdbt_ops;
3417
3418 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3419                                              struct i2c_adapter *i2c,
3420                                              u8 system)
3421 {
3422         u8 chip_id = 0;
3423         const char *type;
3424         struct cxd2841er_priv *priv = NULL;
3425
3426         /* allocate memory for the internal state */
3427         priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3428         if (!priv)
3429                 return NULL;
3430         priv->i2c = i2c;
3431         priv->config = cfg;
3432         priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3433         priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3434         priv->xtal = cfg->xtal;
3435         /* create dvb_frontend */
3436         switch (system) {
3437         case SYS_DVBS:
3438                 memcpy(&priv->frontend.ops,
3439                         &cxd2841er_dvbs_s2_ops,
3440                         sizeof(struct dvb_frontend_ops));
3441                 type = "S/S2";
3442                 break;
3443         case SYS_DVBT:
3444                 memcpy(&priv->frontend.ops,
3445                         &cxd2841er_dvbt_t2_ops,
3446                         sizeof(struct dvb_frontend_ops));
3447                 type = "T/T2";
3448                 break;
3449         case SYS_ISDBT:
3450                 memcpy(&priv->frontend.ops,
3451                                 &cxd2841er_isdbt_ops,
3452                                 sizeof(struct dvb_frontend_ops));
3453                 type = "ISDBT";
3454                 break;
3455         case SYS_DVBC_ANNEX_A:
3456                 memcpy(&priv->frontend.ops,
3457                         &cxd2841er_dvbc_ops,
3458                         sizeof(struct dvb_frontend_ops));
3459                 type = "C/C2";
3460                 break;
3461         default:
3462                 kfree(priv);
3463                 return NULL;
3464         }
3465         priv->frontend.demodulator_priv = priv;
3466         dev_info(&priv->i2c->dev,
3467                 "%s(): attaching CXD2841ER DVB-%s frontend\n",
3468                 __func__, type);
3469         dev_info(&priv->i2c->dev,
3470                 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3471                 __func__, priv->i2c,
3472                 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3473         chip_id = cxd2841er_chip_id(priv);
3474         if (chip_id != CXD2841ER_CHIP_ID && chip_id != CXD2854ER_CHIP_ID) {
3475                 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3476                         __func__, chip_id);
3477                 priv->frontend.demodulator_priv = NULL;
3478                 kfree(priv);
3479                 return NULL;
3480         }
3481         dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3482                 __func__, chip_id);
3483         return &priv->frontend;
3484 }
3485
3486 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3487                                         struct i2c_adapter *i2c)
3488 {
3489         return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3490 }
3491 EXPORT_SYMBOL(cxd2841er_attach_s);
3492
3493 struct dvb_frontend *cxd2841er_attach_t(struct cxd2841er_config *cfg,
3494                                         struct i2c_adapter *i2c)
3495 {
3496         return cxd2841er_attach(cfg, i2c, SYS_DVBT);
3497 }
3498 EXPORT_SYMBOL(cxd2841er_attach_t);
3499
3500 struct dvb_frontend *cxd2841er_attach_i(struct cxd2841er_config *cfg,
3501                 struct i2c_adapter *i2c)
3502 {
3503         return cxd2841er_attach(cfg, i2c, SYS_ISDBT);
3504 }
3505 EXPORT_SYMBOL(cxd2841er_attach_i);
3506
3507 struct dvb_frontend *cxd2841er_attach_c(struct cxd2841er_config *cfg,
3508                                         struct i2c_adapter *i2c)
3509 {
3510         return cxd2841er_attach(cfg, i2c, SYS_DVBC_ANNEX_A);
3511 }
3512 EXPORT_SYMBOL(cxd2841er_attach_c);
3513
3514 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3515         .delsys = { SYS_DVBS, SYS_DVBS2 },
3516         .info = {
3517                 .name           = "Sony CXD2841ER DVB-S/S2 demodulator",
3518                 .frequency_min  = 500000,
3519                 .frequency_max  = 2500000,
3520                 .frequency_stepsize     = 0,
3521                 .symbol_rate_min = 1000000,
3522                 .symbol_rate_max = 45000000,
3523                 .symbol_rate_tolerance = 500,
3524                 .caps = FE_CAN_INVERSION_AUTO |
3525                         FE_CAN_FEC_AUTO |
3526                         FE_CAN_QPSK,
3527         },
3528         .init = cxd2841er_init_s,
3529         .sleep = cxd2841er_sleep_s,
3530         .release = cxd2841er_release,
3531         .set_frontend = cxd2841er_set_frontend_s,
3532         .get_frontend = cxd2841er_get_frontend,
3533         .read_status = cxd2841er_read_status_s,
3534         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3535         .get_frontend_algo = cxd2841er_get_algo,
3536         .set_tone = cxd2841er_set_tone,
3537         .diseqc_send_burst = cxd2841er_send_burst,
3538         .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3539         .tune = cxd2841er_tune_s
3540 };
3541
3542 static struct  dvb_frontend_ops cxd2841er_dvbt_t2_ops = {
3543         .delsys = { SYS_DVBT, SYS_DVBT2 },
3544         .info = {
3545                 .name   = "Sony CXD2841ER DVB-T/T2 demodulator",
3546                 .caps = FE_CAN_FEC_1_2 |
3547                         FE_CAN_FEC_2_3 |
3548                         FE_CAN_FEC_3_4 |
3549                         FE_CAN_FEC_5_6 |
3550                         FE_CAN_FEC_7_8 |
3551                         FE_CAN_FEC_AUTO |
3552                         FE_CAN_QPSK |
3553                         FE_CAN_QAM_16 |
3554                         FE_CAN_QAM_32 |
3555                         FE_CAN_QAM_64 |
3556                         FE_CAN_QAM_128 |
3557                         FE_CAN_QAM_256 |
3558                         FE_CAN_QAM_AUTO |
3559                         FE_CAN_TRANSMISSION_MODE_AUTO |
3560                         FE_CAN_GUARD_INTERVAL_AUTO |
3561                         FE_CAN_HIERARCHY_AUTO |
3562                         FE_CAN_MUTE_TS |
3563                         FE_CAN_2G_MODULATION,
3564                 .frequency_min = 42000000,
3565                 .frequency_max = 1002000000
3566         },
3567         .init = cxd2841er_init_tc,
3568         .sleep = cxd2841er_sleep_tc,
3569         .release = cxd2841er_release,
3570         .set_frontend = cxd2841er_set_frontend_tc,
3571         .get_frontend = cxd2841er_get_frontend,
3572         .read_status = cxd2841er_read_status_tc,
3573         .tune = cxd2841er_tune_tc,
3574         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3575         .get_frontend_algo = cxd2841er_get_algo
3576 };
3577
3578 static struct  dvb_frontend_ops cxd2841er_isdbt_ops = {
3579         .delsys = { SYS_ISDBT },
3580         .info = {
3581                 .name   = "Sony CXD2854ER ISDBT demodulator",
3582                 .caps = FE_CAN_FEC_1_2 |
3583                         FE_CAN_FEC_2_3 |
3584                         FE_CAN_FEC_3_4 |
3585                         FE_CAN_FEC_5_6 |
3586                         FE_CAN_FEC_7_8 |
3587                         FE_CAN_FEC_AUTO |
3588                         FE_CAN_QPSK |
3589                         FE_CAN_QAM_16 |
3590                         FE_CAN_QAM_32 |
3591                         FE_CAN_QAM_64 |
3592                         FE_CAN_QAM_128 |
3593                         FE_CAN_QAM_256 |
3594                         FE_CAN_QAM_AUTO |
3595                         FE_CAN_TRANSMISSION_MODE_AUTO |
3596                         FE_CAN_GUARD_INTERVAL_AUTO |
3597                         FE_CAN_HIERARCHY_AUTO |
3598                         FE_CAN_MUTE_TS |
3599                         FE_CAN_2G_MODULATION,
3600                 .frequency_min = 42000000,
3601                 .frequency_max = 1002000000
3602         },
3603         .init = cxd2841er_init_tc,
3604         .sleep = cxd2841er_sleep_tc,
3605         .release = cxd2841er_release,
3606         .set_frontend = cxd2841er_set_frontend_tc,
3607         .get_frontend = cxd2841er_get_frontend,
3608         .read_status = cxd2841er_read_status_tc,
3609         .tune = cxd2841er_tune_tc,
3610         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3611         .get_frontend_algo = cxd2841er_get_algo
3612 };
3613
3614 static struct  dvb_frontend_ops cxd2841er_dvbc_ops = {
3615         .delsys = { SYS_DVBC_ANNEX_A },
3616         .info = {
3617                 .name   = "Sony CXD2841ER DVB-C demodulator",
3618                 .caps = FE_CAN_FEC_1_2 |
3619                         FE_CAN_FEC_2_3 |
3620                         FE_CAN_FEC_3_4 |
3621                         FE_CAN_FEC_5_6 |
3622                         FE_CAN_FEC_7_8 |
3623                         FE_CAN_FEC_AUTO |
3624                         FE_CAN_QAM_16 |
3625                         FE_CAN_QAM_32 |
3626                         FE_CAN_QAM_64 |
3627                         FE_CAN_QAM_128 |
3628                         FE_CAN_QAM_256 |
3629                         FE_CAN_QAM_AUTO |
3630                         FE_CAN_INVERSION_AUTO,
3631                 .frequency_min = 42000000,
3632                 .frequency_max = 1002000000
3633         },
3634         .init = cxd2841er_init_tc,
3635         .sleep = cxd2841er_sleep_tc,
3636         .release = cxd2841er_release,
3637         .set_frontend = cxd2841er_set_frontend_tc,
3638         .get_frontend = cxd2841er_get_frontend,
3639         .read_status = cxd2841er_read_status_tc,
3640         .tune = cxd2841er_tune_tc,
3641         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3642         .get_frontend_algo = cxd2841er_get_algo,
3643 };
3644
3645 MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3646 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
3647 MODULE_LICENSE("GPL");