1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
4 * Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com>
8 #include <linux/firmware/imx/ipc.h>
9 #include <linux/firmware/imx/s4.h>
10 #include <linux/interrupt.h>
12 #include <linux/iopoll.h>
13 #include <linux/jiffies.h>
14 #include <linux/kernel.h>
15 #include <linux/mailbox_controller.h>
16 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/suspend.h>
21 #include <linux/slab.h>
25 #define IMX_MU_CHANS 24
26 /* TX0/RX0/RXDB[0-3] */
27 #define IMX_MU_SCU_CHANS 6
29 #define IMX_MU_S4_CHANS 2
30 #define IMX_MU_CHAN_NAME_SIZE 20
32 #define IMX_MU_NUM_RR 4
34 #define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
35 #define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
37 /* Please not change TX & RX */
38 enum imx_mu_chan_type {
39 IMX_MU_TYPE_TX = 0, /* Tx */
40 IMX_MU_TYPE_RX = 1, /* Rx */
41 IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */
42 IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */
43 IMX_MU_TYPE_RST = 4, /* Reset */
44 IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */
64 struct imx_sc_rpc_msg_max {
65 struct imx_sc_rpc_msg hdr;
69 struct imx_s4_rpc_msg_max {
70 struct imx_s4_rpc_msg hdr;
74 struct imx_mu_con_priv {
76 char irq_desc[IMX_MU_CHAN_NAME_SIZE];
77 enum imx_mu_chan_type type;
78 struct mbox_chan *chan;
79 struct tasklet_struct txdb_tasklet;
86 spinlock_t xcr_lock; /* control register lock */
88 struct mbox_controller mbox;
89 struct mbox_chan mbox_chans[IMX_MU_CHANS];
91 struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
92 const struct imx_mu_dcfg *dcfg;
94 int irq[IMX_MU_CHANS];
97 u32 xcr[IMX_MU_xCR_MAX];
105 IMX_MU_V2_S4 = BIT(15),
106 IMX_MU_V2_IRQ = BIT(16),
110 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
111 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
112 int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
113 void (*init)(struct imx_mu_priv *priv);
114 enum imx_mu_type type;
115 u32 xTR; /* Transmit Register0 */
116 u32 xRR; /* Receive Register0 */
117 u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */
118 u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */
121 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
122 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
123 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
125 /* General Purpose Interrupt Enable */
126 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
127 /* Receive Interrupt Enable */
128 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
129 /* Transmit Interrupt Enable */
130 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
131 /* General Purpose Interrupt Request */
132 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
134 #define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5))
135 #define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7))
138 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
140 return container_of(mbox, struct imx_mu_priv, mbox);
143 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
145 iowrite32(val, priv->base + offs);
148 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
150 return ioread32(priv->base + offs);
153 static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx)
155 u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT;
159 dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx);
162 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
163 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
164 } while (!can_write && time_is_after_jiffies64(timeout_time));
167 dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n",
172 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);
177 static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx)
179 u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT;
183 dev_dbg(priv->dev, "Trying to read from idx %d\n", idx);
186 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
187 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
188 } while (!can_read && time_is_after_jiffies64(timeout_time));
191 dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n",
196 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);
197 dev_dbg(priv->dev, "Read %.8x\n", *val);
202 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
207 spin_lock_irqsave(&priv->xcr_lock, flags);
208 val = imx_mu_read(priv, priv->dcfg->xCR[type]);
211 imx_mu_write(priv, val, priv->dcfg->xCR[type]);
212 spin_unlock_irqrestore(&priv->xcr_lock, flags);
217 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
218 struct imx_mu_con_priv *cp,
225 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
226 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
228 case IMX_MU_TYPE_TXDB:
229 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
230 tasklet_schedule(&cp->txdb_tasklet);
232 case IMX_MU_TYPE_TXDB_V2:
233 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
236 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
243 static int imx_mu_generic_rx(struct imx_mu_priv *priv,
244 struct imx_mu_con_priv *cp)
248 dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
249 mbox_chan_received_data(cp->chan, (void *)&dat);
254 static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
255 struct imx_mu_con_priv *cp)
257 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
258 priv->dcfg->xSR[IMX_MU_GSR]);
259 mbox_chan_received_data(cp->chan, NULL);
264 static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
269 u32 size, max_size, num_tr;
271 if (priv->dcfg->type & IMX_MU_V2_S4) {
272 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
273 max_size = sizeof(struct imx_s4_rpc_msg_max);
276 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
277 max_size = sizeof(struct imx_sc_rpc_msg_max);
284 * msg->hdr.size specifies the number of u32 words while
285 * sizeof yields bytes.
288 if (size > max_size / 4) {
290 * The real message size can be different to
291 * struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size
293 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2);
297 for (i = 0; i < num_tr && i < size; i++)
298 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
299 for (; i < size; i++) {
300 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
302 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
303 0, 5 * USEC_PER_SEC);
305 dev_err(priv->dev, "Send data index: %d timeout\n", i);
308 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
311 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
314 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
321 static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
328 data = (u32 *)priv->msg;
330 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
331 *data++ = imx_mu_read(priv, priv->dcfg->xRR);
333 if (priv->dcfg->type & IMX_MU_V2_S4) {
334 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size;
335 max_size = sizeof(struct imx_s4_rpc_msg_max);
337 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size;
338 max_size = sizeof(struct imx_sc_rpc_msg_max);
341 if (size > max_size / 4) {
342 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2);
346 for (i = 1; i < size; i++) {
347 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
348 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,
351 dev_err(priv->dev, "timeout read idx %d\n", i);
354 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
357 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
358 mbox_chan_received_data(cp->chan, (void *)priv->msg);
363 static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
366 struct imx_sc_rpc_msg_max *msg = data;
372 dev_dbg(priv->dev, "Sending message\n");
375 case IMX_MU_TYPE_TXDB:
376 byte_size = msg->hdr.size * sizeof(u32);
377 if (byte_size > sizeof(*msg)) {
379 * The real message size can be different to
380 * struct imx_sc_rpc_msg_max size
383 "Exceed max msg size (%zu) on TX, got: %i\n",
384 sizeof(*msg), byte_size);
388 print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4,
389 data, byte_size, false);
391 /* Send first word */
392 dev_dbg(priv->dev, "Sending header\n");
393 imx_mu_write(priv, *arg++, priv->dcfg->xTR);
396 dev_dbg(priv->dev, "Sending signaling\n");
397 imx_mu_xcr_rmw(priv, IMX_MU_GCR,
398 IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
400 /* Send words to fill the mailbox */
401 for (i = 1; i < 4 && i < msg->hdr.size; i++) {
402 dev_dbg(priv->dev, "Sending word %d\n", i);
403 imx_mu_write(priv, *arg++,
404 priv->dcfg->xTR + (i % 4) * 4);
407 /* Send rest of message waiting for remote read */
408 for (; i < msg->hdr.size; i++) {
409 dev_dbg(priv->dev, "Sending word %d\n", i);
410 err = imx_mu_tx_waiting_write(priv, *arg++, i);
412 dev_err(priv->dev, "Timeout tx %d\n", i);
417 /* Simulate hack for mbox framework */
418 tasklet_schedule(&cp->txdb_tasklet);
422 dev_warn_ratelimited(priv->dev,
423 "Send data on wrong channel type: %d\n",
431 static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
433 struct imx_sc_rpc_msg_max msg;
434 u32 *data = (u32 *)&msg;
439 dev_dbg(priv->dev, "Receiving message\n");
442 dev_dbg(priv->dev, "Receiving header\n");
443 *data++ = imx_mu_read(priv, priv->dcfg->xRR);
444 byte_size = msg.hdr.size * sizeof(u32);
445 if (byte_size > sizeof(msg)) {
446 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",
447 sizeof(msg), byte_size);
452 /* Read message waiting they are written */
453 for (i = 1; i < msg.hdr.size; i++) {
454 dev_dbg(priv->dev, "Receiving word %d\n", i);
455 err = imx_mu_rx_waiting_read(priv, data++, i);
457 dev_err(priv->dev, "Timeout rx %d\n", i);
463 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
464 priv->dcfg->xSR[IMX_MU_GSR]);
466 print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4,
467 &msg, byte_size, false);
469 /* send data to client */
470 dev_dbg(priv->dev, "Sending message to client\n");
471 mbox_chan_received_data(cp->chan, (void *)&msg);
476 mbox_chan_received_data(cp->chan, ERR_PTR(err));
482 static void imx_mu_txdb_tasklet(unsigned long data)
484 struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
486 mbox_chan_txdone(cp->chan, 0);
489 static irqreturn_t imx_mu_isr(int irq, void *p)
491 struct mbox_chan *chan = p;
492 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
493 struct imx_mu_con_priv *cp = chan->con_priv;
498 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
499 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
500 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
501 (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
504 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
505 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
506 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
507 (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
509 case IMX_MU_TYPE_RXDB:
510 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);
511 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
512 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
513 (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
515 case IMX_MU_TYPE_RST:
518 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",
526 if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
527 (cp->type == IMX_MU_TYPE_TX)) {
528 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
529 mbox_chan_txdone(chan, 0);
530 } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
531 (cp->type == IMX_MU_TYPE_RX)) {
532 priv->dcfg->rx(priv, cp);
533 } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
534 (cp->type == IMX_MU_TYPE_RXDB)) {
535 priv->dcfg->rxdb(priv, cp);
537 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
547 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
549 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
550 struct imx_mu_con_priv *cp = chan->con_priv;
552 return priv->dcfg->tx(priv, cp, data);
555 static int imx_mu_startup(struct mbox_chan *chan)
557 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
558 struct imx_mu_con_priv *cp = chan->con_priv;
559 unsigned long irq_flag = 0;
562 pm_runtime_get_sync(priv->dev);
563 if (cp->type == IMX_MU_TYPE_TXDB_V2)
566 if (cp->type == IMX_MU_TYPE_TXDB) {
567 /* Tx doorbell don't have ACK support */
568 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
573 /* IPC MU should be with IRQF_NO_SUSPEND set */
574 if (!priv->dev->pm_domain)
575 irq_flag |= IRQF_NO_SUSPEND;
577 if (!(priv->dcfg->type & IMX_MU_V2_IRQ))
578 irq_flag |= IRQF_SHARED;
580 ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan);
582 dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]);
588 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
590 case IMX_MU_TYPE_RXDB:
591 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
600 static void imx_mu_shutdown(struct mbox_chan *chan)
602 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
603 struct imx_mu_con_priv *cp = chan->con_priv;
607 if (cp->type == IMX_MU_TYPE_TXDB_V2) {
608 pm_runtime_put_sync(priv->dev);
612 if (cp->type == IMX_MU_TYPE_TXDB) {
613 tasklet_kill(&cp->txdb_tasklet);
614 pm_runtime_put_sync(priv->dev);
620 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
623 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
625 case IMX_MU_TYPE_RXDB:
626 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
628 case IMX_MU_TYPE_RST:
629 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);
630 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr,
631 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);
633 dev_warn(priv->dev, "RST channel timeout\n");
639 free_irq(priv->irq[cp->type], chan);
640 pm_runtime_put_sync(priv->dev);
643 static const struct mbox_chan_ops imx_mu_ops = {
644 .send_data = imx_mu_send_data,
645 .startup = imx_mu_startup,
646 .shutdown = imx_mu_shutdown,
649 static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox,
650 const struct of_phandle_args *sp)
654 if (sp->args_count != 2) {
655 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
656 return ERR_PTR(-EINVAL);
659 type = sp->args[0]; /* channel type */
660 idx = sp->args[1]; /* index */
666 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
669 case IMX_MU_TYPE_RXDB:
673 dev_err(mbox->dev, "Invalid chan type: %d\n", type);
674 return ERR_PTR(-EINVAL);
677 if (chan >= mbox->num_chans) {
678 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
679 return ERR_PTR(-EINVAL);
682 return &mbox->chans[chan];
685 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
686 const struct of_phandle_args *sp)
688 struct mbox_chan *p_chan;
691 if (sp->args_count != 2) {
692 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
693 return ERR_PTR(-EINVAL);
696 type = sp->args[0]; /* channel type */
697 idx = sp->args[1]; /* index */
699 /* RST only supports 1 channel */
700 if ((type == IMX_MU_TYPE_RST) && idx) {
701 dev_err(mbox->dev, "Invalid RST channel %d\n", idx);
702 return ERR_PTR(-EINVAL);
705 chan = type * 4 + idx;
706 if (chan >= mbox->num_chans) {
707 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
708 return ERR_PTR(-EINVAL);
711 p_chan = &mbox->chans[chan];
713 if (type == IMX_MU_TYPE_TXDB_V2)
714 p_chan->txdone_method = TXDONE_BY_ACK;
719 static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
720 const struct of_phandle_args *sp)
724 if (sp->args_count < 1) {
725 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
726 return ERR_PTR(-EINVAL);
729 type = sp->args[0]; /* channel type */
731 /* Only supports TXDB and RXDB */
732 if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) {
733 dev_err(mbox->dev, "Invalid type: %d\n", type);
734 return ERR_PTR(-EINVAL);
737 return imx_mu_xlate(mbox, sp);
740 static void imx_mu_init_generic(struct imx_mu_priv *priv)
745 for (i = 0; i < IMX_MU_CHANS; i++) {
746 struct imx_mu_con_priv *cp = &priv->con_priv[i];
750 cp->chan = &priv->mbox_chans[i];
751 priv->mbox_chans[i].con_priv = cp;
752 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
753 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
756 priv->mbox.num_chans = IMX_MU_CHANS;
757 priv->mbox.of_xlate = imx_mu_xlate;
762 /* Set default MU configuration */
763 for (i = 0; i < IMX_MU_xCR_MAX; i++)
764 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
766 /* Clear any pending GIP */
767 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
768 imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
770 /* Clear any pending RSR */
771 for (i = 0; i < IMX_MU_NUM_RR; i++)
772 imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
775 static void imx_mu_init_specific(struct imx_mu_priv *priv)
778 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
780 for (i = 0; i < num_chans; i++) {
781 struct imx_mu_con_priv *cp = &priv->con_priv[i];
783 cp->idx = i < 2 ? 0 : i - 2;
784 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
785 cp->chan = &priv->mbox_chans[i];
786 priv->mbox_chans[i].con_priv = cp;
787 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
788 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
791 priv->mbox.num_chans = num_chans;
792 priv->mbox.of_xlate = imx_mu_specific_xlate;
794 /* Set default MU configuration */
795 for (i = 0; i < IMX_MU_xCR_MAX; i++)
796 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
799 static void imx_mu_init_seco(struct imx_mu_priv *priv)
801 imx_mu_init_generic(priv);
802 priv->mbox.of_xlate = imx_mu_seco_xlate;
805 static int imx_mu_probe(struct platform_device *pdev)
807 struct device *dev = &pdev->dev;
808 struct device_node *np = dev->of_node;
809 struct imx_mu_priv *priv;
810 const struct imx_mu_dcfg *dcfg;
814 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
820 priv->base = devm_platform_ioremap_resource(pdev, 0);
821 if (IS_ERR(priv->base))
822 return PTR_ERR(priv->base);
824 dcfg = of_device_get_match_data(dev);
828 if (priv->dcfg->type & IMX_MU_V2_IRQ) {
829 priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx");
830 if (priv->irq[IMX_MU_TYPE_TX] < 0)
831 return priv->irq[IMX_MU_TYPE_TX];
832 priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx");
833 if (priv->irq[IMX_MU_TYPE_RX] < 0)
834 return priv->irq[IMX_MU_TYPE_RX];
836 ret = platform_get_irq(pdev, 0);
840 for (i = 0; i < IMX_MU_CHANS; i++)
844 if (priv->dcfg->type & IMX_MU_V2_S4)
845 size = sizeof(struct imx_s4_rpc_msg_max);
847 size = sizeof(struct imx_sc_rpc_msg_max);
849 priv->msg = devm_kzalloc(dev, size, GFP_KERNEL);
853 priv->clk = devm_clk_get(dev, NULL);
854 if (IS_ERR(priv->clk)) {
855 if (PTR_ERR(priv->clk) != -ENOENT)
856 return PTR_ERR(priv->clk);
861 ret = clk_prepare_enable(priv->clk);
863 dev_err(dev, "Failed to enable clock\n");
867 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
869 priv->dcfg->init(priv);
871 spin_lock_init(&priv->xcr_lock);
873 priv->mbox.dev = dev;
874 priv->mbox.ops = &imx_mu_ops;
875 priv->mbox.chans = priv->mbox_chans;
876 priv->mbox.txdone_irq = true;
878 platform_set_drvdata(pdev, priv);
880 ret = devm_mbox_controller_register(dev, &priv->mbox);
882 clk_disable_unprepare(priv->clk);
886 pm_runtime_enable(dev);
888 ret = pm_runtime_resume_and_get(dev);
890 goto disable_runtime_pm;
892 ret = pm_runtime_put_sync(dev);
894 goto disable_runtime_pm;
896 clk_disable_unprepare(priv->clk);
901 pm_runtime_disable(dev);
902 clk_disable_unprepare(priv->clk);
906 static int imx_mu_remove(struct platform_device *pdev)
908 struct imx_mu_priv *priv = platform_get_drvdata(pdev);
910 pm_runtime_disable(priv->dev);
915 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
916 .tx = imx_mu_generic_tx,
917 .rx = imx_mu_generic_rx,
918 .rxdb = imx_mu_generic_rxdb,
919 .init = imx_mu_init_generic,
922 .xSR = {0x20, 0x20, 0x20, 0x20},
923 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
926 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
927 .tx = imx_mu_generic_tx,
928 .rx = imx_mu_generic_rx,
929 .rxdb = imx_mu_generic_rxdb,
930 .init = imx_mu_init_generic,
933 .xSR = {0x60, 0x60, 0x60, 0x60},
934 .xCR = {0x64, 0x64, 0x64, 0x64, 0x64},
937 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
938 .tx = imx_mu_generic_tx,
939 .rx = imx_mu_generic_rx,
940 .rxdb = imx_mu_generic_rxdb,
941 .init = imx_mu_init_generic,
945 .xSR = {0xC, 0x118, 0x124, 0x12C},
946 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
949 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
950 .tx = imx_mu_specific_tx,
951 .rx = imx_mu_specific_rx,
952 .init = imx_mu_init_specific,
953 .type = IMX_MU_V2 | IMX_MU_V2_S4,
956 .xSR = {0xC, 0x118, 0x124, 0x12C},
957 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
960 static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
961 .tx = imx_mu_specific_tx,
962 .rx = imx_mu_specific_rx,
963 .init = imx_mu_init_specific,
964 .type = IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ,
967 .xSR = {0xC, 0x118, 0x124, 0x12C},
968 .xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
971 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
972 .tx = imx_mu_specific_tx,
973 .rx = imx_mu_specific_rx,
974 .init = imx_mu_init_specific,
975 .rxdb = imx_mu_generic_rxdb,
978 .xSR = {0x20, 0x20, 0x20, 0x20},
979 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
982 static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
983 .tx = imx_mu_seco_tx,
984 .rx = imx_mu_generic_rx,
985 .rxdb = imx_mu_seco_rxdb,
986 .init = imx_mu_init_seco,
989 .xSR = {0x20, 0x20, 0x20, 0x20},
990 .xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
993 static const struct of_device_id imx_mu_dt_ids[] = {
994 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
995 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
996 { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
997 { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
998 { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
999 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
1000 { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
1003 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
1005 static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
1007 struct imx_mu_priv *priv = dev_get_drvdata(dev);
1011 for (i = 0; i < IMX_MU_xCR_MAX; i++)
1012 priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
1015 priv->suspend = true;
1020 static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
1022 struct imx_mu_priv *priv = dev_get_drvdata(dev);
1026 * ONLY restore MU when context lost, the TIE could
1027 * be set during noirq resume as there is MU data
1028 * communication going on, and restore the saved
1029 * value will overwrite the TIE and cause MU data
1030 * send failed, may lead to system freeze. This issue
1031 * is observed by testing freeze mode suspend.
1033 if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) {
1034 for (i = 0; i < IMX_MU_xCR_MAX; i++)
1035 imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
1038 priv->suspend = false;
1043 static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
1045 struct imx_mu_priv *priv = dev_get_drvdata(dev);
1047 clk_disable_unprepare(priv->clk);
1052 static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
1054 struct imx_mu_priv *priv = dev_get_drvdata(dev);
1057 ret = clk_prepare_enable(priv->clk);
1059 dev_err(dev, "failed to enable clock\n");
1064 static const struct dev_pm_ops imx_mu_pm_ops = {
1065 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
1066 imx_mu_resume_noirq)
1067 SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
1068 imx_mu_runtime_resume, NULL)
1071 static struct platform_driver imx_mu_driver = {
1072 .probe = imx_mu_probe,
1073 .remove = imx_mu_remove,
1076 .of_match_table = imx_mu_dt_ids,
1077 .pm = &imx_mu_pm_ops,
1080 module_platform_driver(imx_mu_driver);
1082 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
1083 MODULE_DESCRIPTION("Message Unit driver for i.MX");
1084 MODULE_LICENSE("GPL v2");