2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
19 #include "x86_emulate.h"
22 #include "segment_descriptor.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/profile.h>
29 #include <linux/sched.h>
34 MODULE_AUTHOR("Qumranet");
35 MODULE_LICENSE("GPL");
46 struct kvm_msr_entry *guest_msrs;
47 struct kvm_msr_entry *host_msrs;
52 int msr_offset_kernel_gs_base;
57 u16 fs_sel, gs_sel, ldt_sel;
58 int gs_ldt_reload_needed;
64 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
66 return container_of(vcpu, struct vcpu_vmx, vcpu);
69 static int init_rmode_tss(struct kvm *kvm);
71 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
72 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
74 static struct page *vmx_io_bitmap_a;
75 static struct page *vmx_io_bitmap_b;
77 #define EFER_SAVE_RESTORE_BITS ((u64)EFER_SCE)
79 static struct vmcs_config {
83 u32 pin_based_exec_ctrl;
84 u32 cpu_based_exec_ctrl;
89 #define VMX_SEGMENT_FIELD(seg) \
90 [VCPU_SREG_##seg] = { \
91 .selector = GUEST_##seg##_SELECTOR, \
92 .base = GUEST_##seg##_BASE, \
93 .limit = GUEST_##seg##_LIMIT, \
94 .ar_bytes = GUEST_##seg##_AR_BYTES, \
97 static struct kvm_vmx_segment_field {
102 } kvm_vmx_segment_fields[] = {
103 VMX_SEGMENT_FIELD(CS),
104 VMX_SEGMENT_FIELD(DS),
105 VMX_SEGMENT_FIELD(ES),
106 VMX_SEGMENT_FIELD(FS),
107 VMX_SEGMENT_FIELD(GS),
108 VMX_SEGMENT_FIELD(SS),
109 VMX_SEGMENT_FIELD(TR),
110 VMX_SEGMENT_FIELD(LDTR),
114 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
115 * away by decrementing the array size.
117 static const u32 vmx_msr_index[] = {
119 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
121 MSR_EFER, MSR_K6_STAR,
123 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
125 static void load_msrs(struct kvm_msr_entry *e, int n)
129 for (i = 0; i < n; ++i)
130 wrmsrl(e[i].index, e[i].data);
133 static void save_msrs(struct kvm_msr_entry *e, int n)
137 for (i = 0; i < n; ++i)
138 rdmsrl(e[i].index, e[i].data);
141 static inline u64 msr_efer_save_restore_bits(struct kvm_msr_entry msr)
143 return (u64)msr.data & EFER_SAVE_RESTORE_BITS;
146 static inline int msr_efer_need_save_restore(struct vcpu_vmx *vmx)
148 int efer_offset = vmx->msr_offset_efer;
149 return msr_efer_save_restore_bits(vmx->host_msrs[efer_offset]) !=
150 msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
153 static inline int is_page_fault(u32 intr_info)
155 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
156 INTR_INFO_VALID_MASK)) ==
157 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
160 static inline int is_no_device(u32 intr_info)
162 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
163 INTR_INFO_VALID_MASK)) ==
164 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
167 static inline int is_external_interrupt(u32 intr_info)
169 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
170 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
173 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
177 for (i = 0; i < vmx->nmsrs; ++i)
178 if (vmx->guest_msrs[i].index == msr)
183 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
187 i = __find_msr_index(vmx, msr);
189 return &vmx->guest_msrs[i];
193 static void vmcs_clear(struct vmcs *vmcs)
195 u64 phys_addr = __pa(vmcs);
198 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
199 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
202 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
206 static void __vcpu_clear(void *arg)
208 struct vcpu_vmx *vmx = arg;
209 int cpu = raw_smp_processor_id();
211 if (vmx->vcpu.cpu == cpu)
212 vmcs_clear(vmx->vmcs);
213 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
214 per_cpu(current_vmcs, cpu) = NULL;
215 rdtscll(vmx->vcpu.host_tsc);
218 static void vcpu_clear(struct vcpu_vmx *vmx)
220 if (vmx->vcpu.cpu != raw_smp_processor_id() && vmx->vcpu.cpu != -1)
221 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear,
228 static unsigned long vmcs_readl(unsigned long field)
232 asm volatile (ASM_VMX_VMREAD_RDX_RAX
233 : "=a"(value) : "d"(field) : "cc");
237 static u16 vmcs_read16(unsigned long field)
239 return vmcs_readl(field);
242 static u32 vmcs_read32(unsigned long field)
244 return vmcs_readl(field);
247 static u64 vmcs_read64(unsigned long field)
250 return vmcs_readl(field);
252 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
256 static noinline void vmwrite_error(unsigned long field, unsigned long value)
258 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
259 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
263 static void vmcs_writel(unsigned long field, unsigned long value)
267 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
268 : "=q"(error) : "a"(value), "d"(field) : "cc" );
270 vmwrite_error(field, value);
273 static void vmcs_write16(unsigned long field, u16 value)
275 vmcs_writel(field, value);
278 static void vmcs_write32(unsigned long field, u32 value)
280 vmcs_writel(field, value);
283 static void vmcs_write64(unsigned long field, u64 value)
286 vmcs_writel(field, value);
288 vmcs_writel(field, value);
290 vmcs_writel(field+1, value >> 32);
294 static void vmcs_clear_bits(unsigned long field, u32 mask)
296 vmcs_writel(field, vmcs_readl(field) & ~mask);
299 static void vmcs_set_bits(unsigned long field, u32 mask)
301 vmcs_writel(field, vmcs_readl(field) | mask);
304 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
308 eb = 1u << PF_VECTOR;
309 if (!vcpu->fpu_active)
310 eb |= 1u << NM_VECTOR;
311 if (vcpu->guest_debug.enabled)
313 if (vcpu->rmode.active)
315 vmcs_write32(EXCEPTION_BITMAP, eb);
318 static void reload_tss(void)
320 #ifndef CONFIG_X86_64
323 * VT restores TR but not its size. Useless.
325 struct descriptor_table gdt;
326 struct segment_descriptor *descs;
329 descs = (void *)gdt.base;
330 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
335 static void load_transition_efer(struct vcpu_vmx *vmx)
338 int efer_offset = vmx->msr_offset_efer;
340 trans_efer = vmx->host_msrs[efer_offset].data;
341 trans_efer &= ~EFER_SAVE_RESTORE_BITS;
342 trans_efer |= msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
343 wrmsrl(MSR_EFER, trans_efer);
344 vmx->vcpu.stat.efer_reload++;
347 static void vmx_save_host_state(struct vcpu_vmx *vmx)
349 if (vmx->host_state.loaded)
352 vmx->host_state.loaded = 1;
354 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
355 * allow segment selectors with cpl > 0 or ti == 1.
357 vmx->host_state.ldt_sel = read_ldt();
358 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
359 vmx->host_state.fs_sel = read_fs();
360 if (!(vmx->host_state.fs_sel & 7)) {
361 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
362 vmx->host_state.fs_reload_needed = 0;
364 vmcs_write16(HOST_FS_SELECTOR, 0);
365 vmx->host_state.fs_reload_needed = 1;
367 vmx->host_state.gs_sel = read_gs();
368 if (!(vmx->host_state.gs_sel & 7))
369 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
371 vmcs_write16(HOST_GS_SELECTOR, 0);
372 vmx->host_state.gs_ldt_reload_needed = 1;
376 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
377 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
379 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
380 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
384 if (is_long_mode(&vmx->vcpu)) {
385 save_msrs(vmx->host_msrs +
386 vmx->msr_offset_kernel_gs_base, 1);
389 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
390 if (msr_efer_need_save_restore(vmx))
391 load_transition_efer(vmx);
394 static void vmx_load_host_state(struct vcpu_vmx *vmx)
398 if (!vmx->host_state.loaded)
401 vmx->host_state.loaded = 0;
402 if (vmx->host_state.fs_reload_needed)
403 load_fs(vmx->host_state.fs_sel);
404 if (vmx->host_state.gs_ldt_reload_needed) {
405 load_ldt(vmx->host_state.ldt_sel);
407 * If we have to reload gs, we must take care to
408 * preserve our gs base.
410 local_irq_save(flags);
411 load_gs(vmx->host_state.gs_sel);
413 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
415 local_irq_restore(flags);
418 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
419 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
420 if (msr_efer_need_save_restore(vmx))
421 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
425 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
426 * vcpu mutex is already taken.
428 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
430 struct vcpu_vmx *vmx = to_vmx(vcpu);
431 u64 phys_addr = __pa(vmx->vmcs);
434 if (vcpu->cpu != cpu)
437 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
440 per_cpu(current_vmcs, cpu) = vmx->vmcs;
441 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
442 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
445 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
446 vmx->vmcs, phys_addr);
449 if (vcpu->cpu != cpu) {
450 struct descriptor_table dt;
451 unsigned long sysenter_esp;
455 * Linux uses per-cpu TSS and GDT, so set these when switching
458 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
460 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
462 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
463 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
466 * Make sure the time stamp counter is monotonous.
469 delta = vcpu->host_tsc - tsc_this;
470 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
474 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
476 vmx_load_host_state(to_vmx(vcpu));
477 kvm_put_guest_fpu(vcpu);
480 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
482 if (vcpu->fpu_active)
484 vcpu->fpu_active = 1;
485 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
486 if (vcpu->cr0 & X86_CR0_TS)
487 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
488 update_exception_bitmap(vcpu);
491 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
493 if (!vcpu->fpu_active)
495 vcpu->fpu_active = 0;
496 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
497 update_exception_bitmap(vcpu);
500 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
502 vcpu_clear(to_vmx(vcpu));
505 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
507 return vmcs_readl(GUEST_RFLAGS);
510 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
512 vmcs_writel(GUEST_RFLAGS, rflags);
515 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
518 u32 interruptibility;
520 rip = vmcs_readl(GUEST_RIP);
521 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
522 vmcs_writel(GUEST_RIP, rip);
525 * We emulated an instruction, so temporary interrupt blocking
526 * should be removed, if set.
528 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
529 if (interruptibility & 3)
530 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
531 interruptibility & ~3);
532 vcpu->interrupt_window_open = 1;
535 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
537 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
538 vmcs_readl(GUEST_RIP));
539 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
540 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
542 INTR_TYPE_EXCEPTION |
543 INTR_INFO_DELIEVER_CODE_MASK |
544 INTR_INFO_VALID_MASK);
548 * Swap MSR entry in host/guest MSR entry array.
551 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
553 struct kvm_msr_entry tmp;
555 tmp = vmx->guest_msrs[to];
556 vmx->guest_msrs[to] = vmx->guest_msrs[from];
557 vmx->guest_msrs[from] = tmp;
558 tmp = vmx->host_msrs[to];
559 vmx->host_msrs[to] = vmx->host_msrs[from];
560 vmx->host_msrs[from] = tmp;
565 * Set up the vmcs to automatically save and restore system
566 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
567 * mode, as fiddling with msrs is very expensive.
569 static void setup_msrs(struct vcpu_vmx *vmx)
575 if (is_long_mode(&vmx->vcpu)) {
578 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
580 move_msr_up(vmx, index, save_nmsrs++);
581 index = __find_msr_index(vmx, MSR_LSTAR);
583 move_msr_up(vmx, index, save_nmsrs++);
584 index = __find_msr_index(vmx, MSR_CSTAR);
586 move_msr_up(vmx, index, save_nmsrs++);
587 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
589 move_msr_up(vmx, index, save_nmsrs++);
591 * MSR_K6_STAR is only needed on long mode guests, and only
592 * if efer.sce is enabled.
594 index = __find_msr_index(vmx, MSR_K6_STAR);
595 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
596 move_msr_up(vmx, index, save_nmsrs++);
599 vmx->save_nmsrs = save_nmsrs;
602 vmx->msr_offset_kernel_gs_base =
603 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
605 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
609 * reads and returns guest's timestamp counter "register"
610 * guest_tsc = host_tsc + tsc_offset -- 21.3
612 static u64 guest_read_tsc(void)
614 u64 host_tsc, tsc_offset;
617 tsc_offset = vmcs_read64(TSC_OFFSET);
618 return host_tsc + tsc_offset;
622 * writes 'guest_tsc' into guest's timestamp counter "register"
623 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
625 static void guest_write_tsc(u64 guest_tsc)
630 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
634 * Reads an msr value (of 'msr_index') into 'pdata'.
635 * Returns 0 on success, non-0 otherwise.
636 * Assumes vcpu_load() was already called.
638 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
641 struct kvm_msr_entry *msr;
644 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
651 data = vmcs_readl(GUEST_FS_BASE);
654 data = vmcs_readl(GUEST_GS_BASE);
657 return kvm_get_msr_common(vcpu, msr_index, pdata);
659 case MSR_IA32_TIME_STAMP_COUNTER:
660 data = guest_read_tsc();
662 case MSR_IA32_SYSENTER_CS:
663 data = vmcs_read32(GUEST_SYSENTER_CS);
665 case MSR_IA32_SYSENTER_EIP:
666 data = vmcs_readl(GUEST_SYSENTER_EIP);
668 case MSR_IA32_SYSENTER_ESP:
669 data = vmcs_readl(GUEST_SYSENTER_ESP);
672 msr = find_msr_entry(to_vmx(vcpu), msr_index);
677 return kvm_get_msr_common(vcpu, msr_index, pdata);
685 * Writes msr value into into the appropriate "register".
686 * Returns 0 on success, non-0 otherwise.
687 * Assumes vcpu_load() was already called.
689 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
691 struct vcpu_vmx *vmx = to_vmx(vcpu);
692 struct kvm_msr_entry *msr;
698 ret = kvm_set_msr_common(vcpu, msr_index, data);
699 if (vmx->host_state.loaded)
700 load_transition_efer(vmx);
703 vmcs_writel(GUEST_FS_BASE, data);
706 vmcs_writel(GUEST_GS_BASE, data);
709 case MSR_IA32_SYSENTER_CS:
710 vmcs_write32(GUEST_SYSENTER_CS, data);
712 case MSR_IA32_SYSENTER_EIP:
713 vmcs_writel(GUEST_SYSENTER_EIP, data);
715 case MSR_IA32_SYSENTER_ESP:
716 vmcs_writel(GUEST_SYSENTER_ESP, data);
718 case MSR_IA32_TIME_STAMP_COUNTER:
719 guest_write_tsc(data);
722 msr = find_msr_entry(vmx, msr_index);
725 if (vmx->host_state.loaded)
726 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
729 ret = kvm_set_msr_common(vcpu, msr_index, data);
736 * Sync the rsp and rip registers into the vcpu structure. This allows
737 * registers to be accessed by indexing vcpu->regs.
739 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
741 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
742 vcpu->rip = vmcs_readl(GUEST_RIP);
746 * Syncs rsp and rip back into the vmcs. Should be called after possible
749 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
751 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
752 vmcs_writel(GUEST_RIP, vcpu->rip);
755 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
757 unsigned long dr7 = 0x400;
760 old_singlestep = vcpu->guest_debug.singlestep;
762 vcpu->guest_debug.enabled = dbg->enabled;
763 if (vcpu->guest_debug.enabled) {
766 dr7 |= 0x200; /* exact */
767 for (i = 0; i < 4; ++i) {
768 if (!dbg->breakpoints[i].enabled)
770 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
771 dr7 |= 2 << (i*2); /* global enable */
772 dr7 |= 0 << (i*4+16); /* execution breakpoint */
775 vcpu->guest_debug.singlestep = dbg->singlestep;
777 vcpu->guest_debug.singlestep = 0;
779 if (old_singlestep && !vcpu->guest_debug.singlestep) {
782 flags = vmcs_readl(GUEST_RFLAGS);
783 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
784 vmcs_writel(GUEST_RFLAGS, flags);
787 update_exception_bitmap(vcpu);
788 vmcs_writel(GUEST_DR7, dr7);
793 static __init int cpu_has_kvm_support(void)
795 unsigned long ecx = cpuid_ecx(1);
796 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
799 static __init int vmx_disabled_by_bios(void)
803 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
804 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
805 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
806 == MSR_IA32_FEATURE_CONTROL_LOCKED;
807 /* locked but not enabled */
810 static void hardware_enable(void *garbage)
812 int cpu = raw_smp_processor_id();
813 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
816 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
817 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
818 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
819 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
820 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
821 /* enable and lock */
822 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
823 MSR_IA32_FEATURE_CONTROL_LOCKED |
824 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
825 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
826 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
830 static void hardware_disable(void *garbage)
832 asm volatile (ASM_VMX_VMXOFF : : : "cc");
835 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
836 u32 msr, u32* result)
838 u32 vmx_msr_low, vmx_msr_high;
839 u32 ctl = ctl_min | ctl_opt;
841 rdmsr(msr, vmx_msr_low, vmx_msr_high);
843 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
844 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
846 /* Ensure minimum (required) set of control bits are supported. */
854 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
856 u32 vmx_msr_low, vmx_msr_high;
858 u32 _pin_based_exec_control = 0;
859 u32 _cpu_based_exec_control = 0;
860 u32 _vmexit_control = 0;
861 u32 _vmentry_control = 0;
863 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
865 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
866 &_pin_based_exec_control) < 0)
869 min = CPU_BASED_HLT_EXITING |
871 CPU_BASED_CR8_LOAD_EXITING |
872 CPU_BASED_CR8_STORE_EXITING |
874 CPU_BASED_USE_IO_BITMAPS |
875 CPU_BASED_MOV_DR_EXITING |
876 CPU_BASED_USE_TSC_OFFSETING;
878 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
879 &_cpu_based_exec_control) < 0)
884 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
887 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
888 &_vmexit_control) < 0)
892 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
893 &_vmentry_control) < 0)
896 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
898 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
899 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
903 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
904 if (vmx_msr_high & (1u<<16))
908 /* Require Write-Back (WB) memory type for VMCS accesses. */
909 if (((vmx_msr_high >> 18) & 15) != 6)
912 vmcs_conf->size = vmx_msr_high & 0x1fff;
913 vmcs_conf->order = get_order(vmcs_config.size);
914 vmcs_conf->revision_id = vmx_msr_low;
916 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
917 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
918 vmcs_conf->vmexit_ctrl = _vmexit_control;
919 vmcs_conf->vmentry_ctrl = _vmentry_control;
924 static struct vmcs *alloc_vmcs_cpu(int cpu)
926 int node = cpu_to_node(cpu);
930 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
933 vmcs = page_address(pages);
934 memset(vmcs, 0, vmcs_config.size);
935 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
939 static struct vmcs *alloc_vmcs(void)
941 return alloc_vmcs_cpu(raw_smp_processor_id());
944 static void free_vmcs(struct vmcs *vmcs)
946 free_pages((unsigned long)vmcs, vmcs_config.order);
949 static void free_kvm_area(void)
953 for_each_online_cpu(cpu)
954 free_vmcs(per_cpu(vmxarea, cpu));
957 static __init int alloc_kvm_area(void)
961 for_each_online_cpu(cpu) {
964 vmcs = alloc_vmcs_cpu(cpu);
970 per_cpu(vmxarea, cpu) = vmcs;
975 static __init int hardware_setup(void)
977 if (setup_vmcs_config(&vmcs_config) < 0)
979 return alloc_kvm_area();
982 static __exit void hardware_unsetup(void)
987 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
989 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
991 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
992 vmcs_write16(sf->selector, save->selector);
993 vmcs_writel(sf->base, save->base);
994 vmcs_write32(sf->limit, save->limit);
995 vmcs_write32(sf->ar_bytes, save->ar);
997 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
999 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1003 static void enter_pmode(struct kvm_vcpu *vcpu)
1005 unsigned long flags;
1007 vcpu->rmode.active = 0;
1009 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1010 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1011 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1013 flags = vmcs_readl(GUEST_RFLAGS);
1014 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
1015 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1016 vmcs_writel(GUEST_RFLAGS, flags);
1018 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1019 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1021 update_exception_bitmap(vcpu);
1023 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1024 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1025 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1026 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1028 vmcs_write16(GUEST_SS_SELECTOR, 0);
1029 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1031 vmcs_write16(GUEST_CS_SELECTOR,
1032 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1033 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1036 static gva_t rmode_tss_base(struct kvm* kvm)
1038 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
1039 return base_gfn << PAGE_SHIFT;
1042 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1044 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1046 save->selector = vmcs_read16(sf->selector);
1047 save->base = vmcs_readl(sf->base);
1048 save->limit = vmcs_read32(sf->limit);
1049 save->ar = vmcs_read32(sf->ar_bytes);
1050 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1051 vmcs_write32(sf->limit, 0xffff);
1052 vmcs_write32(sf->ar_bytes, 0xf3);
1055 static void enter_rmode(struct kvm_vcpu *vcpu)
1057 unsigned long flags;
1059 vcpu->rmode.active = 1;
1061 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1062 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1064 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1065 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1067 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1068 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1070 flags = vmcs_readl(GUEST_RFLAGS);
1071 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
1073 flags |= IOPL_MASK | X86_EFLAGS_VM;
1075 vmcs_writel(GUEST_RFLAGS, flags);
1076 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1077 update_exception_bitmap(vcpu);
1079 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1080 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1081 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1083 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1084 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1085 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1086 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1087 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1089 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1090 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1091 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1092 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1094 init_rmode_tss(vcpu->kvm);
1097 #ifdef CONFIG_X86_64
1099 static void enter_lmode(struct kvm_vcpu *vcpu)
1103 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1104 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1105 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1107 vmcs_write32(GUEST_TR_AR_BYTES,
1108 (guest_tr_ar & ~AR_TYPE_MASK)
1109 | AR_TYPE_BUSY_64_TSS);
1112 vcpu->shadow_efer |= EFER_LMA;
1114 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1115 vmcs_write32(VM_ENTRY_CONTROLS,
1116 vmcs_read32(VM_ENTRY_CONTROLS)
1117 | VM_ENTRY_IA32E_MODE);
1120 static void exit_lmode(struct kvm_vcpu *vcpu)
1122 vcpu->shadow_efer &= ~EFER_LMA;
1124 vmcs_write32(VM_ENTRY_CONTROLS,
1125 vmcs_read32(VM_ENTRY_CONTROLS)
1126 & ~VM_ENTRY_IA32E_MODE);
1131 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1133 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1134 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1137 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1139 vmx_fpu_deactivate(vcpu);
1141 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1144 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1147 #ifdef CONFIG_X86_64
1148 if (vcpu->shadow_efer & EFER_LME) {
1149 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1151 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1156 vmcs_writel(CR0_READ_SHADOW, cr0);
1157 vmcs_writel(GUEST_CR0,
1158 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1161 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1162 vmx_fpu_activate(vcpu);
1165 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1167 vmcs_writel(GUEST_CR3, cr3);
1168 if (vcpu->cr0 & X86_CR0_PE)
1169 vmx_fpu_deactivate(vcpu);
1172 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1174 vmcs_writel(CR4_READ_SHADOW, cr4);
1175 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1176 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1180 #ifdef CONFIG_X86_64
1182 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1184 struct vcpu_vmx *vmx = to_vmx(vcpu);
1185 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1187 vcpu->shadow_efer = efer;
1188 if (efer & EFER_LMA) {
1189 vmcs_write32(VM_ENTRY_CONTROLS,
1190 vmcs_read32(VM_ENTRY_CONTROLS) |
1191 VM_ENTRY_IA32E_MODE);
1195 vmcs_write32(VM_ENTRY_CONTROLS,
1196 vmcs_read32(VM_ENTRY_CONTROLS) &
1197 ~VM_ENTRY_IA32E_MODE);
1199 msr->data = efer & ~EFER_LME;
1206 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1208 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1210 return vmcs_readl(sf->base);
1213 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1214 struct kvm_segment *var, int seg)
1216 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1219 var->base = vmcs_readl(sf->base);
1220 var->limit = vmcs_read32(sf->limit);
1221 var->selector = vmcs_read16(sf->selector);
1222 ar = vmcs_read32(sf->ar_bytes);
1223 if (ar & AR_UNUSABLE_MASK)
1225 var->type = ar & 15;
1226 var->s = (ar >> 4) & 1;
1227 var->dpl = (ar >> 5) & 3;
1228 var->present = (ar >> 7) & 1;
1229 var->avl = (ar >> 12) & 1;
1230 var->l = (ar >> 13) & 1;
1231 var->db = (ar >> 14) & 1;
1232 var->g = (ar >> 15) & 1;
1233 var->unusable = (ar >> 16) & 1;
1236 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1243 ar = var->type & 15;
1244 ar |= (var->s & 1) << 4;
1245 ar |= (var->dpl & 3) << 5;
1246 ar |= (var->present & 1) << 7;
1247 ar |= (var->avl & 1) << 12;
1248 ar |= (var->l & 1) << 13;
1249 ar |= (var->db & 1) << 14;
1250 ar |= (var->g & 1) << 15;
1252 if (ar == 0) /* a 0 value means unusable */
1253 ar = AR_UNUSABLE_MASK;
1258 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1259 struct kvm_segment *var, int seg)
1261 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1264 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1265 vcpu->rmode.tr.selector = var->selector;
1266 vcpu->rmode.tr.base = var->base;
1267 vcpu->rmode.tr.limit = var->limit;
1268 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1271 vmcs_writel(sf->base, var->base);
1272 vmcs_write32(sf->limit, var->limit);
1273 vmcs_write16(sf->selector, var->selector);
1274 if (vcpu->rmode.active && var->s) {
1276 * Hack real-mode segments into vm86 compatibility.
1278 if (var->base == 0xffff0000 && var->selector == 0xf000)
1279 vmcs_writel(sf->base, 0xf0000);
1282 ar = vmx_segment_access_rights(var);
1283 vmcs_write32(sf->ar_bytes, ar);
1286 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1288 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1290 *db = (ar >> 14) & 1;
1291 *l = (ar >> 13) & 1;
1294 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1296 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1297 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1300 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1302 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1303 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1306 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1308 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1309 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1312 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1314 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1315 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1318 static int init_rmode_tss(struct kvm* kvm)
1320 struct page *p1, *p2, *p3;
1321 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1324 p1 = gfn_to_page(kvm, fn++);
1325 p2 = gfn_to_page(kvm, fn++);
1326 p3 = gfn_to_page(kvm, fn);
1328 if (!p1 || !p2 || !p3) {
1329 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1333 page = kmap_atomic(p1, KM_USER0);
1335 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1336 kunmap_atomic(page, KM_USER0);
1338 page = kmap_atomic(p2, KM_USER0);
1340 kunmap_atomic(page, KM_USER0);
1342 page = kmap_atomic(p3, KM_USER0);
1344 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1345 kunmap_atomic(page, KM_USER0);
1350 static void seg_setup(int seg)
1352 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1354 vmcs_write16(sf->selector, 0);
1355 vmcs_writel(sf->base, 0);
1356 vmcs_write32(sf->limit, 0xffff);
1357 vmcs_write32(sf->ar_bytes, 0x93);
1361 * Sets up the vmcs for emulated real mode.
1363 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1365 u32 host_sysenter_cs;
1368 struct descriptor_table dt;
1371 unsigned long kvm_vmx_return;
1374 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1379 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1380 set_cr8(&vmx->vcpu, 0);
1381 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1382 if (vmx->vcpu.vcpu_id == 0)
1383 msr |= MSR_IA32_APICBASE_BSP;
1384 kvm_set_apic_base(&vmx->vcpu, msr);
1386 fx_init(&vmx->vcpu);
1389 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1390 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1392 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1393 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1394 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1395 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1397 seg_setup(VCPU_SREG_DS);
1398 seg_setup(VCPU_SREG_ES);
1399 seg_setup(VCPU_SREG_FS);
1400 seg_setup(VCPU_SREG_GS);
1401 seg_setup(VCPU_SREG_SS);
1403 vmcs_write16(GUEST_TR_SELECTOR, 0);
1404 vmcs_writel(GUEST_TR_BASE, 0);
1405 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1406 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1408 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1409 vmcs_writel(GUEST_LDTR_BASE, 0);
1410 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1411 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1413 vmcs_write32(GUEST_SYSENTER_CS, 0);
1414 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1415 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1417 vmcs_writel(GUEST_RFLAGS, 0x02);
1418 vmcs_writel(GUEST_RIP, 0xfff0);
1419 vmcs_writel(GUEST_RSP, 0);
1421 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1422 vmcs_writel(GUEST_DR7, 0x400);
1424 vmcs_writel(GUEST_GDTR_BASE, 0);
1425 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1427 vmcs_writel(GUEST_IDTR_BASE, 0);
1428 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1430 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1431 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1432 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1435 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1436 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1440 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1442 /* Special registers */
1443 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1446 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1447 vmcs_config.pin_based_exec_ctrl);
1448 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1449 vmcs_config.cpu_based_exec_ctrl);
1451 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1452 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1453 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1455 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1456 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1457 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1459 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1460 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1461 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1462 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1463 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1464 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1465 #ifdef CONFIG_X86_64
1466 rdmsrl(MSR_FS_BASE, a);
1467 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1468 rdmsrl(MSR_GS_BASE, a);
1469 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1471 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1472 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1475 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1478 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1480 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1481 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1482 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1483 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1484 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1486 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1487 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1488 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1489 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1490 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1491 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1493 for (i = 0; i < NR_VMX_MSR; ++i) {
1494 u32 index = vmx_msr_index[i];
1495 u32 data_low, data_high;
1499 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1501 if (wrmsr_safe(index, data_low, data_high) < 0)
1503 data = data_low | ((u64)data_high << 32);
1504 vmx->host_msrs[j].index = index;
1505 vmx->host_msrs[j].reserved = 0;
1506 vmx->host_msrs[j].data = data;
1507 vmx->guest_msrs[j] = vmx->host_msrs[j];
1513 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1515 /* 22.2.1, 20.8.1 */
1516 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1518 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1520 #ifdef CONFIG_X86_64
1521 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1522 vmcs_writel(TPR_THRESHOLD, 0);
1525 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1526 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1528 vmx->vcpu.cr0 = 0x60000010;
1529 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); // enter rmode
1530 vmx_set_cr4(&vmx->vcpu, 0);
1531 #ifdef CONFIG_X86_64
1532 vmx_set_efer(&vmx->vcpu, 0);
1534 vmx_fpu_activate(&vmx->vcpu);
1535 update_exception_bitmap(&vmx->vcpu);
1543 static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1548 unsigned long flags;
1549 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1550 u16 sp = vmcs_readl(GUEST_RSP);
1551 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1553 if (sp > ss_limit || sp < 6 ) {
1554 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1556 vmcs_readl(GUEST_RSP),
1557 vmcs_readl(GUEST_SS_BASE),
1558 vmcs_read32(GUEST_SS_LIMIT));
1562 if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) !=
1564 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1568 flags = vmcs_readl(GUEST_RFLAGS);
1569 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1570 ip = vmcs_readl(GUEST_RIP);
1573 if (emulator_write_emulated(ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE ||
1574 emulator_write_emulated(ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE ||
1575 emulator_write_emulated(ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) {
1576 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1580 vmcs_writel(GUEST_RFLAGS, flags &
1581 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1582 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1583 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1584 vmcs_writel(GUEST_RIP, ent[0]);
1585 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1588 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1590 if (vcpu->rmode.active) {
1591 inject_rmode_irq(vcpu, irq);
1594 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1595 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1598 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1600 int word_index = __ffs(vcpu->irq_summary);
1601 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1602 int irq = word_index * BITS_PER_LONG + bit_index;
1604 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1605 if (!vcpu->irq_pending[word_index])
1606 clear_bit(word_index, &vcpu->irq_summary);
1607 vmx_inject_irq(vcpu, irq);
1611 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1612 struct kvm_run *kvm_run)
1614 u32 cpu_based_vm_exec_control;
1616 vcpu->interrupt_window_open =
1617 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1618 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1620 if (vcpu->interrupt_window_open &&
1621 vcpu->irq_summary &&
1622 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1624 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1626 kvm_do_inject_irq(vcpu);
1628 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1629 if (!vcpu->interrupt_window_open &&
1630 (vcpu->irq_summary || kvm_run->request_interrupt_window))
1632 * Interrupts blocked. Wait for unblock.
1634 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1636 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1637 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1640 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1642 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1644 set_debugreg(dbg->bp[0], 0);
1645 set_debugreg(dbg->bp[1], 1);
1646 set_debugreg(dbg->bp[2], 2);
1647 set_debugreg(dbg->bp[3], 3);
1649 if (dbg->singlestep) {
1650 unsigned long flags;
1652 flags = vmcs_readl(GUEST_RFLAGS);
1653 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1654 vmcs_writel(GUEST_RFLAGS, flags);
1658 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1659 int vec, u32 err_code)
1661 if (!vcpu->rmode.active)
1665 * Instruction with address size override prefix opcode 0x67
1666 * Cause the #SS fault with 0 error code in VM86 mode.
1668 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1669 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1674 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1676 u32 intr_info, error_code;
1677 unsigned long cr2, rip;
1679 enum emulation_result er;
1682 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1683 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1685 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1686 !is_page_fault(intr_info)) {
1687 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1688 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1691 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1692 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1693 set_bit(irq, vcpu->irq_pending);
1694 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1697 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1702 if (is_no_device(intr_info)) {
1703 vmx_fpu_activate(vcpu);
1708 rip = vmcs_readl(GUEST_RIP);
1709 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1710 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1711 if (is_page_fault(intr_info)) {
1712 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1714 mutex_lock(&vcpu->kvm->lock);
1715 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1717 mutex_unlock(&vcpu->kvm->lock);
1721 mutex_unlock(&vcpu->kvm->lock);
1725 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1726 mutex_unlock(&vcpu->kvm->lock);
1731 case EMULATE_DO_MMIO:
1732 ++vcpu->stat.mmio_exits;
1735 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1742 if (vcpu->rmode.active &&
1743 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1745 if (vcpu->halt_request) {
1746 vcpu->halt_request = 0;
1747 return kvm_emulate_halt(vcpu);
1752 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1753 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1756 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1757 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1758 kvm_run->ex.error_code = error_code;
1762 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1763 struct kvm_run *kvm_run)
1765 ++vcpu->stat.irq_exits;
1769 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1771 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1775 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1777 u64 exit_qualification;
1778 int size, down, in, string, rep;
1781 ++vcpu->stat.io_exits;
1782 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1783 string = (exit_qualification & 16) != 0;
1786 if (emulate_instruction(vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO)
1791 size = (exit_qualification & 7) + 1;
1792 in = (exit_qualification & 8) != 0;
1793 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1794 rep = (exit_qualification & 32) != 0;
1795 port = exit_qualification >> 16;
1797 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1801 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1804 * Patch in the VMCALL instruction:
1806 hypercall[0] = 0x0f;
1807 hypercall[1] = 0x01;
1808 hypercall[2] = 0xc1;
1809 hypercall[3] = 0xc3;
1812 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1814 u64 exit_qualification;
1818 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1819 cr = exit_qualification & 15;
1820 reg = (exit_qualification >> 8) & 15;
1821 switch ((exit_qualification >> 4) & 3) {
1822 case 0: /* mov to cr */
1825 vcpu_load_rsp_rip(vcpu);
1826 set_cr0(vcpu, vcpu->regs[reg]);
1827 skip_emulated_instruction(vcpu);
1830 vcpu_load_rsp_rip(vcpu);
1831 set_cr3(vcpu, vcpu->regs[reg]);
1832 skip_emulated_instruction(vcpu);
1835 vcpu_load_rsp_rip(vcpu);
1836 set_cr4(vcpu, vcpu->regs[reg]);
1837 skip_emulated_instruction(vcpu);
1840 vcpu_load_rsp_rip(vcpu);
1841 set_cr8(vcpu, vcpu->regs[reg]);
1842 skip_emulated_instruction(vcpu);
1843 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1848 vcpu_load_rsp_rip(vcpu);
1849 vmx_fpu_deactivate(vcpu);
1850 vcpu->cr0 &= ~X86_CR0_TS;
1851 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1852 vmx_fpu_activate(vcpu);
1853 skip_emulated_instruction(vcpu);
1855 case 1: /*mov from cr*/
1858 vcpu_load_rsp_rip(vcpu);
1859 vcpu->regs[reg] = vcpu->cr3;
1860 vcpu_put_rsp_rip(vcpu);
1861 skip_emulated_instruction(vcpu);
1864 vcpu_load_rsp_rip(vcpu);
1865 vcpu->regs[reg] = get_cr8(vcpu);
1866 vcpu_put_rsp_rip(vcpu);
1867 skip_emulated_instruction(vcpu);
1872 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1874 skip_emulated_instruction(vcpu);
1879 kvm_run->exit_reason = 0;
1880 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
1881 (int)(exit_qualification >> 4) & 3, cr);
1885 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1887 u64 exit_qualification;
1892 * FIXME: this code assumes the host is debugging the guest.
1893 * need to deal with guest debugging itself too.
1895 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1896 dr = exit_qualification & 7;
1897 reg = (exit_qualification >> 8) & 15;
1898 vcpu_load_rsp_rip(vcpu);
1899 if (exit_qualification & 16) {
1911 vcpu->regs[reg] = val;
1915 vcpu_put_rsp_rip(vcpu);
1916 skip_emulated_instruction(vcpu);
1920 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1922 kvm_emulate_cpuid(vcpu);
1926 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1928 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1931 if (vmx_get_msr(vcpu, ecx, &data)) {
1932 vmx_inject_gp(vcpu, 0);
1936 /* FIXME: handling of bits 32:63 of rax, rdx */
1937 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1938 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1939 skip_emulated_instruction(vcpu);
1943 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1945 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1946 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1947 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1949 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1950 vmx_inject_gp(vcpu, 0);
1954 skip_emulated_instruction(vcpu);
1958 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1959 struct kvm_run *kvm_run)
1961 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1962 kvm_run->cr8 = get_cr8(vcpu);
1963 kvm_run->apic_base = kvm_get_apic_base(vcpu);
1964 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1965 vcpu->irq_summary == 0);
1968 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1969 struct kvm_run *kvm_run)
1971 u32 cpu_based_vm_exec_control;
1973 /* clear pending irq */
1974 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1975 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1976 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1978 * If the user space waits to inject interrupts, exit as soon as
1981 if (kvm_run->request_interrupt_window &&
1982 !vcpu->irq_summary) {
1983 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1984 ++vcpu->stat.irq_window_exits;
1990 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1992 skip_emulated_instruction(vcpu);
1993 return kvm_emulate_halt(vcpu);
1996 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1998 skip_emulated_instruction(vcpu);
1999 return kvm_hypercall(vcpu, kvm_run);
2003 * The exit handlers return 1 if the exit was handled fully and guest execution
2004 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2005 * to be done to userspace and return 0.
2007 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2008 struct kvm_run *kvm_run) = {
2009 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2010 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2011 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2012 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2013 [EXIT_REASON_CR_ACCESS] = handle_cr,
2014 [EXIT_REASON_DR_ACCESS] = handle_dr,
2015 [EXIT_REASON_CPUID] = handle_cpuid,
2016 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2017 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2018 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2019 [EXIT_REASON_HLT] = handle_halt,
2020 [EXIT_REASON_VMCALL] = handle_vmcall,
2023 static const int kvm_vmx_max_exit_handlers =
2024 ARRAY_SIZE(kvm_vmx_exit_handlers);
2027 * The guest has exited. See if we can fix it or if we need userspace
2030 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2032 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2033 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2035 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
2036 exit_reason != EXIT_REASON_EXCEPTION_NMI )
2037 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2038 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2039 if (exit_reason < kvm_vmx_max_exit_handlers
2040 && kvm_vmx_exit_handlers[exit_reason])
2041 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2043 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2044 kvm_run->hw.hardware_exit_reason = exit_reason;
2050 * Check if userspace requested an interrupt window, and that the
2051 * interrupt window is open.
2053 * No need to exit to userspace if we already have an interrupt queued.
2055 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2056 struct kvm_run *kvm_run)
2058 return (!vcpu->irq_summary &&
2059 kvm_run->request_interrupt_window &&
2060 vcpu->interrupt_window_open &&
2061 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
2064 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2068 static void enable_irq_window(struct kvm_vcpu *vcpu)
2070 u32 cpu_based_vm_exec_control;
2072 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2073 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2074 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2077 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2079 u32 idtv_info_field, intr_info_field;
2080 int has_ext_irq, interrupt_window_open;
2082 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2083 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2084 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2085 if (intr_info_field & INTR_INFO_VALID_MASK) {
2086 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2087 /* TODO: fault when IDT_Vectoring */
2088 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2091 enable_irq_window(vcpu);
2094 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2095 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2096 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2097 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2099 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2100 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2101 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2102 if (unlikely(has_ext_irq))
2103 enable_irq_window(vcpu);
2108 interrupt_window_open =
2109 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2110 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2111 if (interrupt_window_open)
2112 vmx_inject_irq(vcpu, kvm_cpu_get_interrupt(vcpu));
2114 enable_irq_window(vcpu);
2117 static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2119 struct vcpu_vmx *vmx = to_vmx(vcpu);
2124 if (vcpu->guest_debug.enabled)
2125 kvm_guest_debug_pre(vcpu);
2128 r = kvm_mmu_reload(vcpu);
2134 vmx_save_host_state(vmx);
2135 kvm_load_guest_fpu(vcpu);
2138 * Loading guest fpu may have cleared host cr0.ts
2140 vmcs_writel(HOST_CR0, read_cr0());
2142 local_irq_disable();
2144 if (signal_pending(current)) {
2148 kvm_run->exit_reason = KVM_EXIT_INTR;
2149 ++vcpu->stat.signal_exits;
2153 if (irqchip_in_kernel(vcpu->kvm))
2154 vmx_intr_assist(vcpu);
2155 else if (!vcpu->mmio_read_completed)
2156 do_interrupt_requests(vcpu, kvm_run);
2158 vcpu->guest_mode = 1;
2160 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
2161 vmx_flush_tlb(vcpu);
2164 /* Store host registers */
2165 #ifdef CONFIG_X86_64
2166 "push %%rax; push %%rbx; push %%rdx;"
2167 "push %%rsi; push %%rdi; push %%rbp;"
2168 "push %%r8; push %%r9; push %%r10; push %%r11;"
2169 "push %%r12; push %%r13; push %%r14; push %%r15;"
2171 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2173 "pusha; push %%ecx \n\t"
2174 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2176 /* Check if vmlaunch of vmresume is needed */
2178 /* Load guest registers. Don't clobber flags. */
2179 #ifdef CONFIG_X86_64
2180 "mov %c[cr2](%3), %%rax \n\t"
2181 "mov %%rax, %%cr2 \n\t"
2182 "mov %c[rax](%3), %%rax \n\t"
2183 "mov %c[rbx](%3), %%rbx \n\t"
2184 "mov %c[rdx](%3), %%rdx \n\t"
2185 "mov %c[rsi](%3), %%rsi \n\t"
2186 "mov %c[rdi](%3), %%rdi \n\t"
2187 "mov %c[rbp](%3), %%rbp \n\t"
2188 "mov %c[r8](%3), %%r8 \n\t"
2189 "mov %c[r9](%3), %%r9 \n\t"
2190 "mov %c[r10](%3), %%r10 \n\t"
2191 "mov %c[r11](%3), %%r11 \n\t"
2192 "mov %c[r12](%3), %%r12 \n\t"
2193 "mov %c[r13](%3), %%r13 \n\t"
2194 "mov %c[r14](%3), %%r14 \n\t"
2195 "mov %c[r15](%3), %%r15 \n\t"
2196 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2198 "mov %c[cr2](%3), %%eax \n\t"
2199 "mov %%eax, %%cr2 \n\t"
2200 "mov %c[rax](%3), %%eax \n\t"
2201 "mov %c[rbx](%3), %%ebx \n\t"
2202 "mov %c[rdx](%3), %%edx \n\t"
2203 "mov %c[rsi](%3), %%esi \n\t"
2204 "mov %c[rdi](%3), %%edi \n\t"
2205 "mov %c[rbp](%3), %%ebp \n\t"
2206 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2208 /* Enter guest mode */
2209 "jne .Llaunched \n\t"
2210 ASM_VMX_VMLAUNCH "\n\t"
2211 "jmp .Lkvm_vmx_return \n\t"
2212 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2213 ".Lkvm_vmx_return: "
2214 /* Save guest registers, load host registers, keep flags */
2215 #ifdef CONFIG_X86_64
2216 "xchg %3, (%%rsp) \n\t"
2217 "mov %%rax, %c[rax](%3) \n\t"
2218 "mov %%rbx, %c[rbx](%3) \n\t"
2219 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
2220 "mov %%rdx, %c[rdx](%3) \n\t"
2221 "mov %%rsi, %c[rsi](%3) \n\t"
2222 "mov %%rdi, %c[rdi](%3) \n\t"
2223 "mov %%rbp, %c[rbp](%3) \n\t"
2224 "mov %%r8, %c[r8](%3) \n\t"
2225 "mov %%r9, %c[r9](%3) \n\t"
2226 "mov %%r10, %c[r10](%3) \n\t"
2227 "mov %%r11, %c[r11](%3) \n\t"
2228 "mov %%r12, %c[r12](%3) \n\t"
2229 "mov %%r13, %c[r13](%3) \n\t"
2230 "mov %%r14, %c[r14](%3) \n\t"
2231 "mov %%r15, %c[r15](%3) \n\t"
2232 "mov %%cr2, %%rax \n\t"
2233 "mov %%rax, %c[cr2](%3) \n\t"
2234 "mov (%%rsp), %3 \n\t"
2236 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2237 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2238 "pop %%rbp; pop %%rdi; pop %%rsi;"
2239 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2241 "xchg %3, (%%esp) \n\t"
2242 "mov %%eax, %c[rax](%3) \n\t"
2243 "mov %%ebx, %c[rbx](%3) \n\t"
2244 "pushl (%%esp); popl %c[rcx](%3) \n\t"
2245 "mov %%edx, %c[rdx](%3) \n\t"
2246 "mov %%esi, %c[rsi](%3) \n\t"
2247 "mov %%edi, %c[rdi](%3) \n\t"
2248 "mov %%ebp, %c[rbp](%3) \n\t"
2249 "mov %%cr2, %%eax \n\t"
2250 "mov %%eax, %c[cr2](%3) \n\t"
2251 "mov (%%esp), %3 \n\t"
2253 "pop %%ecx; popa \n\t"
2257 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
2259 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2260 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2261 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2262 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2263 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2264 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2265 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
2266 #ifdef CONFIG_X86_64
2267 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2268 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2269 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2270 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2271 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2272 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2273 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2274 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2276 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2279 vcpu->guest_mode = 0;
2284 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2286 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2291 if (unlikely(fail)) {
2292 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2293 kvm_run->fail_entry.hardware_entry_failure_reason
2294 = vmcs_read32(VM_INSTRUCTION_ERROR);
2299 * Profile KVM exit RIPs:
2301 if (unlikely(prof_on == KVM_PROFILING))
2302 profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP));
2304 r = kvm_handle_exit(kvm_run, vcpu);
2306 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2308 kvm_run->exit_reason = KVM_EXIT_INTR;
2309 ++vcpu->stat.request_irq_exits;
2312 if (!need_resched()) {
2313 ++vcpu->stat.light_exits;
2324 post_kvm_run_save(vcpu, kvm_run);
2328 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2332 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2334 ++vcpu->stat.pf_guest;
2336 if (is_page_fault(vect_info)) {
2337 printk(KERN_DEBUG "inject_page_fault: "
2338 "double fault 0x%lx @ 0x%lx\n",
2339 addr, vmcs_readl(GUEST_RIP));
2340 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2341 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2343 INTR_TYPE_EXCEPTION |
2344 INTR_INFO_DELIEVER_CODE_MASK |
2345 INTR_INFO_VALID_MASK);
2349 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2350 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2352 INTR_TYPE_EXCEPTION |
2353 INTR_INFO_DELIEVER_CODE_MASK |
2354 INTR_INFO_VALID_MASK);
2358 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2360 struct vcpu_vmx *vmx = to_vmx(vcpu);
2363 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2364 free_vmcs(vmx->vmcs);
2369 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2371 struct vcpu_vmx *vmx = to_vmx(vcpu);
2373 vmx_free_vmcs(vcpu);
2374 kfree(vmx->host_msrs);
2375 kfree(vmx->guest_msrs);
2376 kvm_vcpu_uninit(vcpu);
2377 kmem_cache_free(kvm_vcpu_cache, vmx);
2380 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2383 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2387 return ERR_PTR(-ENOMEM);
2389 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2393 if (irqchip_in_kernel(kvm)) {
2394 err = kvm_create_lapic(&vmx->vcpu);
2399 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2400 if (!vmx->guest_msrs) {
2405 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2406 if (!vmx->host_msrs)
2407 goto free_guest_msrs;
2409 vmx->vmcs = alloc_vmcs();
2413 vmcs_clear(vmx->vmcs);
2416 vmx_vcpu_load(&vmx->vcpu, cpu);
2417 err = vmx_vcpu_setup(vmx);
2418 vmx_vcpu_put(&vmx->vcpu);
2426 free_vmcs(vmx->vmcs);
2428 kfree(vmx->host_msrs);
2430 kfree(vmx->guest_msrs);
2432 kvm_vcpu_uninit(&vmx->vcpu);
2434 kmem_cache_free(kvm_vcpu_cache, vmx);
2435 return ERR_PTR(err);
2438 static void __init vmx_check_processor_compat(void *rtn)
2440 struct vmcs_config vmcs_conf;
2443 if (setup_vmcs_config(&vmcs_conf) < 0)
2445 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2446 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2447 smp_processor_id());
2452 static struct kvm_arch_ops vmx_arch_ops = {
2453 .cpu_has_kvm_support = cpu_has_kvm_support,
2454 .disabled_by_bios = vmx_disabled_by_bios,
2455 .hardware_setup = hardware_setup,
2456 .hardware_unsetup = hardware_unsetup,
2457 .check_processor_compatibility = vmx_check_processor_compat,
2458 .hardware_enable = hardware_enable,
2459 .hardware_disable = hardware_disable,
2461 .vcpu_create = vmx_create_vcpu,
2462 .vcpu_free = vmx_free_vcpu,
2464 .vcpu_load = vmx_vcpu_load,
2465 .vcpu_put = vmx_vcpu_put,
2466 .vcpu_decache = vmx_vcpu_decache,
2468 .set_guest_debug = set_guest_debug,
2469 .get_msr = vmx_get_msr,
2470 .set_msr = vmx_set_msr,
2471 .get_segment_base = vmx_get_segment_base,
2472 .get_segment = vmx_get_segment,
2473 .set_segment = vmx_set_segment,
2474 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2475 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2476 .set_cr0 = vmx_set_cr0,
2477 .set_cr3 = vmx_set_cr3,
2478 .set_cr4 = vmx_set_cr4,
2479 #ifdef CONFIG_X86_64
2480 .set_efer = vmx_set_efer,
2482 .get_idt = vmx_get_idt,
2483 .set_idt = vmx_set_idt,
2484 .get_gdt = vmx_get_gdt,
2485 .set_gdt = vmx_set_gdt,
2486 .cache_regs = vcpu_load_rsp_rip,
2487 .decache_regs = vcpu_put_rsp_rip,
2488 .get_rflags = vmx_get_rflags,
2489 .set_rflags = vmx_set_rflags,
2491 .tlb_flush = vmx_flush_tlb,
2492 .inject_page_fault = vmx_inject_page_fault,
2494 .inject_gp = vmx_inject_gp,
2496 .run = vmx_vcpu_run,
2497 .skip_emulated_instruction = skip_emulated_instruction,
2498 .patch_hypercall = vmx_patch_hypercall,
2501 static int __init vmx_init(void)
2506 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2507 if (!vmx_io_bitmap_a)
2510 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2511 if (!vmx_io_bitmap_b) {
2517 * Allow direct access to the PC debug port (it is often used for I/O
2518 * delays, but the vmexits simply slow things down).
2520 iova = kmap(vmx_io_bitmap_a);
2521 memset(iova, 0xff, PAGE_SIZE);
2522 clear_bit(0x80, iova);
2523 kunmap(vmx_io_bitmap_a);
2525 iova = kmap(vmx_io_bitmap_b);
2526 memset(iova, 0xff, PAGE_SIZE);
2527 kunmap(vmx_io_bitmap_b);
2529 r = kvm_init_arch(&vmx_arch_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2536 __free_page(vmx_io_bitmap_b);
2538 __free_page(vmx_io_bitmap_a);
2542 static void __exit vmx_exit(void)
2544 __free_page(vmx_io_bitmap_b);
2545 __free_page(vmx_io_bitmap_a);
2550 module_init(vmx_init)
2551 module_exit(vmx_exit)