1 /* $Id: w6692.c,v 1.18.2.4 2004/02/11 13:21:34 keil Exp $
3 * Winbond W6692 specific routines
6 * Copyright by Petr Novak <petr.novak@i.cz>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
13 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/pci.h>
20 /* table entry in the PCI devices list */
28 static const PCI_ENTRY id_list[] =
30 {PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_6692, "Winbond", "W6692"},
31 {PCI_VENDOR_ID_DYNALINK, PCI_DEVICE_ID_DYNALINK_IS64PH, "Dynalink/AsusCom", "IS64PH"},
32 {0, 0, "U.S.Robotics", "ISDN PCI Card TA"}
35 #define W6692_SV_USR 0x16ec
36 #define W6692_SD_USR 0x3409
37 #define W6692_WINBOND 0
38 #define W6692_DYNALINK 1
41 static const char *w6692_revision = "$Revision: 1.18.2.4 $";
43 #define DBUSY_TIMER_VALUE 80
45 static char *W6692Ver[] =
46 {"W6692 V00", "W6692 V01", "W6692 V10",
50 W6692Version(struct IsdnCardState *cs, char *s)
54 val = cs->readW6692(cs, W_D_RBCH);
55 printk(KERN_INFO "%s Winbond W6692 version (%x): %s\n", s, val, W6692Ver[(val >> 6) & 3]);
59 ph_command(struct IsdnCardState *cs, unsigned int command)
61 if (cs->debug & L1_DEB_ISAC)
62 debugl1(cs, "ph_command %x", command);
63 cs->writeisac(cs, W_CIX, command);
68 W6692_new_ph(struct IsdnCardState *cs)
70 switch (cs->dc.w6692.ph_state) {
72 ph_command(cs, W_L1CMD_DRC);
73 l1_msg(cs, HW_RESET | INDICATION, NULL);
76 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
79 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
82 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
85 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
88 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
91 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
94 l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL);
102 W6692_bh(struct work_struct *work)
104 struct IsdnCardState *cs =
105 container_of(work, struct IsdnCardState, tqueue);
106 struct PStack *stptr;
108 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
110 debugl1(cs, "D-Channel Busy cleared");
112 while (stptr != NULL) {
113 stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);
117 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
119 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
120 DChannel_proc_rcv(cs);
121 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
122 DChannel_proc_xmt(cs);
124 if (test_and_clear_bit(D_RX_MON1, &cs->event))
125 arcofi_fsm(cs, ARCOFI_RX_END, NULL);
126 if (test_and_clear_bit(D_TX_MON1, &cs->event))
127 arcofi_fsm(cs, ARCOFI_TX_END, NULL);
132 W6692_empty_fifo(struct IsdnCardState *cs, int count)
136 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
137 debugl1(cs, "W6692_empty_fifo");
139 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
140 if (cs->debug & L1_DEB_WARN)
141 debugl1(cs, "W6692_empty_fifo overrun %d",
143 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_RACK);
147 ptr = cs->rcvbuf + cs->rcvidx;
149 cs->readW6692fifo(cs, ptr, count);
150 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_RACK);
151 if (cs->debug & L1_DEB_ISAC_FIFO) {
154 t += sprintf(t, "W6692_empty_fifo cnt %d", count);
155 QuickHex(t, ptr, count);
156 debugl1(cs, cs->dlog);
161 W6692_fill_fifo(struct IsdnCardState *cs)
166 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
167 debugl1(cs, "W6692_fill_fifo");
172 count = cs->tx_skb->len;
177 if (count > W_D_FIFO_THRESH) {
179 count = W_D_FIFO_THRESH;
181 ptr = cs->tx_skb->data;
182 skb_pull(cs->tx_skb, count);
184 cs->writeW6692fifo(cs, ptr, count);
185 cs->writeW6692(cs, W_D_CMDR, more ? W_D_CMDR_XMS : (W_D_CMDR_XMS | W_D_CMDR_XME));
186 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
187 debugl1(cs, "W6692_fill_fifo dbusytimer running");
188 del_timer(&cs->dbusytimer);
190 init_timer(&cs->dbusytimer);
191 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ) / 1000);
192 add_timer(&cs->dbusytimer);
193 if (cs->debug & L1_DEB_ISAC_FIFO) {
196 t += sprintf(t, "W6692_fill_fifo cnt %d", count);
197 QuickHex(t, ptr, count);
198 debugl1(cs, cs->dlog);
203 W6692B_empty_fifo(struct BCState *bcs, int count)
206 struct IsdnCardState *cs = bcs->cs;
208 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
209 debugl1(cs, "W6692B_empty_fifo");
211 if (bcs->hw.w6692.rcvidx + count > HSCX_BUFMAX) {
212 if (cs->debug & L1_DEB_WARN)
213 debugl1(cs, "W6692B_empty_fifo: incoming packet too large");
214 cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
215 bcs->hw.w6692.rcvidx = 0;
218 ptr = bcs->hw.w6692.rcvbuf + bcs->hw.w6692.rcvidx;
219 bcs->hw.w6692.rcvidx += count;
220 READW6692BFIFO(cs, bcs->channel, ptr, count);
221 cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT);
222 if (cs->debug & L1_DEB_HSCX_FIFO) {
225 t += sprintf(t, "W6692B_empty_fifo %c cnt %d",
226 bcs->channel + '1', count);
227 QuickHex(t, ptr, count);
228 debugl1(cs, bcs->blog);
233 W6692B_fill_fifo(struct BCState *bcs)
235 struct IsdnCardState *cs = bcs->cs;
241 if (bcs->tx_skb->len <= 0)
244 more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;
245 if (bcs->tx_skb->len > W_B_FIFO_THRESH) {
247 count = W_B_FIFO_THRESH;
249 count = bcs->tx_skb->len;
251 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
252 debugl1(cs, "W6692B_fill_fifo%s%d", (more ? " ": " last "), count);
254 ptr = bcs->tx_skb->data;
255 skb_pull(bcs->tx_skb, count);
256 bcs->tx_cnt -= count;
257 bcs->hw.w6692.count += count;
258 WRITEW6692BFIFO(cs, bcs->channel, ptr, count);
259 cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACT | W_B_CMDR_XMS | (more ? 0 : W_B_CMDR_XME));
260 if (cs->debug & L1_DEB_HSCX_FIFO) {
263 t += sprintf(t, "W6692B_fill_fifo %c cnt %d",
264 bcs->channel + '1', count);
265 QuickHex(t, ptr, count);
266 debugl1(cs, bcs->blog);
271 W6692B_interrupt(struct IsdnCardState *cs, u_char bchan)
279 bcs = (cs->bcs->channel == bchan) ? cs->bcs : (cs->bcs+1);
280 val = cs->BC_Read_Reg(cs, bchan, W_B_EXIR);
281 debugl1(cs, "W6692B chan %d B_EXIR 0x%02X", bchan, val);
283 if (!test_bit(BC_FLG_INIT, &bcs->Flag)) {
284 debugl1(cs, "W6692B not INIT yet");
287 if (val & W_B_EXI_RME) { /* RME */
288 r = cs->BC_Read_Reg(cs, bchan, W_B_STAR);
289 if (r & (W_B_STAR_RDOV | W_B_STAR_CRCE | W_B_STAR_RMB)) {
290 if (cs->debug & L1_DEB_WARN)
291 debugl1(cs, "W6692 B STAR %x", r);
292 if ((r & W_B_STAR_RDOV) && bcs->mode)
293 if (cs->debug & L1_DEB_WARN)
294 debugl1(cs, "W6692 B RDOV mode=%d",
296 if (r & W_B_STAR_CRCE)
297 if (cs->debug & L1_DEB_WARN)
298 debugl1(cs, "W6692 B CRC error");
299 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RRST | W_B_CMDR_RACT);
301 count = cs->BC_Read_Reg(cs, bchan, W_B_RBCL) & (W_B_FIFO_THRESH - 1);
303 count = W_B_FIFO_THRESH;
304 W6692B_empty_fifo(bcs, count);
305 if ((count = bcs->hw.w6692.rcvidx) > 0) {
306 if (cs->debug & L1_DEB_HSCX_FIFO)
307 debugl1(cs, "W6692 Bchan Frame %d", count);
308 if (!(skb = dev_alloc_skb(count)))
309 printk(KERN_WARNING "W6692: Bchan receive out of memory\n");
311 memcpy(skb_put(skb, count), bcs->hw.w6692.rcvbuf, count);
312 skb_queue_tail(&bcs->rqueue, skb);
316 bcs->hw.w6692.rcvidx = 0;
317 schedule_event(bcs, B_RCVBUFREADY);
319 if (val & W_B_EXI_RMR) { /* RMR */
320 W6692B_empty_fifo(bcs, W_B_FIFO_THRESH);
321 r = cs->BC_Read_Reg(cs, bchan, W_B_STAR);
322 if (r & W_B_STAR_RDOV) {
323 if (cs->debug & L1_DEB_WARN)
324 debugl1(cs, "W6692 B RDOV(RMR) mode=%d",bcs->mode);
325 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RRST | W_B_CMDR_RACT);
326 if (bcs->mode != L1_MODE_TRANS)
327 bcs->hw.w6692.rcvidx = 0;
329 if (bcs->mode == L1_MODE_TRANS) {
330 /* receive audio data */
331 if (!(skb = dev_alloc_skb(W_B_FIFO_THRESH)))
332 printk(KERN_WARNING "HiSax: receive out of memory\n");
334 memcpy(skb_put(skb, W_B_FIFO_THRESH), bcs->hw.w6692.rcvbuf, W_B_FIFO_THRESH);
335 skb_queue_tail(&bcs->rqueue, skb);
337 bcs->hw.w6692.rcvidx = 0;
338 schedule_event(bcs, B_RCVBUFREADY);
341 if (val & W_B_EXI_XDUN) { /* XDUN */
342 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_XRST | W_B_CMDR_RACT);
343 if (cs->debug & L1_DEB_WARN)
344 debugl1(cs, "W6692 B EXIR %x Lost TX", val);
346 W6692B_fill_fifo(bcs);
348 /* Here we lost an TX interrupt, so
349 * restart transmitting the whole frame.
352 skb_push(bcs->tx_skb, bcs->hw.w6692.count);
353 bcs->tx_cnt += bcs->hw.w6692.count;
354 bcs->hw.w6692.count = 0;
359 if (val & W_B_EXI_XFR) { /* XFR */
360 r = cs->BC_Read_Reg(cs, bchan, W_B_STAR);
361 if (r & W_B_STAR_XDOW) {
362 if (cs->debug & L1_DEB_WARN)
363 debugl1(cs, "W6692 B STAR %x XDOW", r);
364 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_XRST | W_B_CMDR_RACT);
365 if (bcs->tx_skb && (bcs->mode != 1)) {
366 skb_push(bcs->tx_skb, bcs->hw.w6692.count);
367 bcs->tx_cnt += bcs->hw.w6692.count;
368 bcs->hw.w6692.count = 0;
372 if (bcs->tx_skb->len) {
373 W6692B_fill_fifo(bcs);
376 if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
377 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
379 spin_lock_irqsave(&bcs->aclock, flags);
380 bcs->ackcnt += bcs->hw.w6692.count;
381 spin_unlock_irqrestore(&bcs->aclock, flags);
382 schedule_event(bcs, B_ACKPENDING);
384 dev_kfree_skb_irq(bcs->tx_skb);
385 bcs->hw.w6692.count = 0;
389 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
390 bcs->hw.w6692.count = 0;
391 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
392 W6692B_fill_fifo(bcs);
394 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
395 schedule_event(bcs, B_XMTBUFREADY);
401 W6692_interrupt(int intno, void *dev_id)
403 struct IsdnCardState *cs = dev_id;
404 u_char val, exval, v1;
410 spin_lock_irqsave(&cs->lock, flags);
411 val = cs->readW6692(cs, W_ISTA);
413 spin_unlock_irqrestore(&cs->lock, flags);
417 if (cs->debug & L1_DEB_ISAC)
418 debugl1(cs, "W6692 ISTA %x", val);
420 if (val & W_INT_D_RME) { /* RME */
421 exval = cs->readW6692(cs, W_D_RSTA);
422 if (exval & (W_D_RSTA_RDOV | W_D_RSTA_CRCE | W_D_RSTA_RMB)) {
423 if (exval & W_D_RSTA_RDOV)
424 if (cs->debug & L1_DEB_WARN)
425 debugl1(cs, "W6692 RDOV");
426 if (exval & W_D_RSTA_CRCE)
427 if (cs->debug & L1_DEB_WARN)
428 debugl1(cs, "W6692 D-channel CRC error");
429 if (exval & W_D_RSTA_RMB)
430 if (cs->debug & L1_DEB_WARN)
431 debugl1(cs, "W6692 D-channel ABORT");
432 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_RACK | W_D_CMDR_RRST);
434 count = cs->readW6692(cs, W_D_RBCL) & (W_D_FIFO_THRESH - 1);
436 count = W_D_FIFO_THRESH;
437 W6692_empty_fifo(cs, count);
438 if ((count = cs->rcvidx) > 0) {
440 if (!(skb = alloc_skb(count, GFP_ATOMIC)))
441 printk(KERN_WARNING "HiSax: D receive out of memory\n");
443 memcpy(skb_put(skb, count), cs->rcvbuf, count);
444 skb_queue_tail(&cs->rq, skb);
449 schedule_event(cs, D_RCVBUFREADY);
451 if (val & W_INT_D_RMR) { /* RMR */
452 W6692_empty_fifo(cs, W_D_FIFO_THRESH);
454 if (val & W_INT_D_XFR) { /* XFR */
455 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
456 del_timer(&cs->dbusytimer);
457 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
458 schedule_event(cs, D_CLEARBUSY);
460 if (cs->tx_skb->len) {
464 dev_kfree_skb_irq(cs->tx_skb);
469 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
473 schedule_event(cs, D_XMTBUFREADY);
476 if (val & (W_INT_XINT0 | W_INT_XINT1)) { /* XINT0/1 - never */
477 if (cs->debug & L1_DEB_ISAC)
478 debugl1(cs, "W6692 spurious XINT!");
480 if (val & W_INT_D_EXI) { /* EXI */
481 exval = cs->readW6692(cs, W_D_EXIR);
482 if (cs->debug & L1_DEB_WARN)
483 debugl1(cs, "W6692 D_EXIR %02x", exval);
484 if (exval & (W_D_EXI_XDUN | W_D_EXI_XCOL)) { /* Transmit underrun/collision */
485 debugl1(cs, "W6692 D-chan underrun/collision");
486 printk(KERN_WARNING "HiSax: W6692 XDUN/XCOL\n");
487 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
488 del_timer(&cs->dbusytimer);
489 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
490 schedule_event(cs, D_CLEARBUSY);
491 if (cs->tx_skb) { /* Restart frame */
492 skb_push(cs->tx_skb, cs->tx_cnt);
496 printk(KERN_WARNING "HiSax: W6692 XDUN/XCOL no skb\n");
497 debugl1(cs, "W6692 XDUN/XCOL no skb");
498 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_XRST);
501 if (exval & W_D_EXI_RDOV) { /* RDOV */
502 debugl1(cs, "W6692 D-channel RDOV");
503 printk(KERN_WARNING "HiSax: W6692 D-RDOV\n");
504 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_RRST);
506 if (exval & W_D_EXI_TIN2) { /* TIN2 - never */
507 debugl1(cs, "W6692 spurious TIN2 interrupt");
509 if (exval & W_D_EXI_MOC) { /* MOC - not supported */
510 debugl1(cs, "W6692 spurious MOC interrupt");
511 v1 = cs->readW6692(cs, W_MOSR);
512 debugl1(cs, "W6692 MOSR %02x", v1);
514 if (exval & W_D_EXI_ISC) { /* ISC - Level1 change */
515 v1 = cs->readW6692(cs, W_CIR);
516 if (cs->debug & L1_DEB_ISAC)
517 debugl1(cs, "W6692 ISC CIR=0x%02X", v1);
518 if (v1 & W_CIR_ICC) {
519 cs->dc.w6692.ph_state = v1 & W_CIR_COD_MASK;
520 if (cs->debug & L1_DEB_ISAC)
521 debugl1(cs, "ph_state_change %x", cs->dc.w6692.ph_state);
522 schedule_event(cs, D_L1STATECHANGE);
524 if (v1 & W_CIR_SCC) {
525 v1 = cs->readW6692(cs, W_SQR);
526 debugl1(cs, "W6692 SCC SQR=0x%02X", v1);
529 if (exval & W_D_EXI_WEXP) {
530 debugl1(cs, "W6692 spurious WEXP interrupt!");
532 if (exval & W_D_EXI_TEXP) {
533 debugl1(cs, "W6692 spurious TEXP interrupt!");
536 if (val & W_INT_B1_EXI) {
537 debugl1(cs, "W6692 B channel 1 interrupt");
538 W6692B_interrupt(cs, 0);
540 if (val & W_INT_B2_EXI) {
541 debugl1(cs, "W6692 B channel 2 interrupt");
542 W6692B_interrupt(cs, 1);
544 val = cs->readW6692(cs, W_ISTA);
550 printk(KERN_WARNING "W6692 IRQ LOOP\n");
551 cs->writeW6692(cs, W_IMASK, 0xff);
553 spin_unlock_irqrestore(&cs->lock, flags);
558 W6692_l1hw(struct PStack *st, int pr, void *arg)
560 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
561 struct sk_buff *skb = arg;
566 case (PH_DATA | REQUEST):
567 if (cs->debug & DEB_DLOG_HEX)
568 LogFrame(cs, skb->data, skb->len);
569 if (cs->debug & DEB_DLOG_VERBOSE)
570 dlogframe(cs, skb, 0);
571 spin_lock_irqsave(&cs->lock, flags);
573 skb_queue_tail(&cs->sq, skb);
574 #ifdef L2FRAME_DEBUG /* psa */
575 if (cs->debug & L1_DEB_LAPD)
576 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
581 #ifdef L2FRAME_DEBUG /* psa */
582 if (cs->debug & L1_DEB_LAPD)
583 Logl2Frame(cs, skb, "PH_DATA", 0);
587 spin_unlock_irqrestore(&cs->lock, flags);
589 case (PH_PULL | INDICATION):
590 spin_lock_irqsave(&cs->lock, flags);
592 if (cs->debug & L1_DEB_WARN)
593 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
594 skb_queue_tail(&cs->sq, skb);
595 spin_unlock_irqrestore(&cs->lock, flags);
598 if (cs->debug & DEB_DLOG_HEX)
599 LogFrame(cs, skb->data, skb->len);
600 if (cs->debug & DEB_DLOG_VERBOSE)
601 dlogframe(cs, skb, 0);
604 #ifdef L2FRAME_DEBUG /* psa */
605 if (cs->debug & L1_DEB_LAPD)
606 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
609 spin_unlock_irqrestore(&cs->lock, flags);
611 case (PH_PULL | REQUEST):
612 #ifdef L2FRAME_DEBUG /* psa */
613 if (cs->debug & L1_DEB_LAPD)
614 debugl1(cs, "-> PH_REQUEST_PULL");
617 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
618 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
620 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
622 case (HW_RESET | REQUEST):
623 spin_lock_irqsave(&cs->lock, flags);
624 if ((cs->dc.w6692.ph_state == W_L1IND_DRD)) {
625 ph_command(cs, W_L1CMD_ECK);
626 spin_unlock_irqrestore(&cs->lock, flags);
628 ph_command(cs, W_L1CMD_RST);
629 cs->dc.w6692.ph_state = W_L1CMD_RST;
630 spin_unlock_irqrestore(&cs->lock, flags);
634 case (HW_ENABLE | REQUEST):
635 spin_lock_irqsave(&cs->lock, flags);
636 ph_command(cs, W_L1CMD_ECK);
637 spin_unlock_irqrestore(&cs->lock, flags);
639 case (HW_INFO3 | REQUEST):
640 spin_lock_irqsave(&cs->lock, flags);
641 ph_command(cs, W_L1CMD_AR8);
642 spin_unlock_irqrestore(&cs->lock, flags);
644 case (HW_TESTLOOP | REQUEST):
650 /* !!! not implemented yet */
652 case (HW_DEACTIVATE | RESPONSE):
653 skb_queue_purge(&cs->rq);
654 skb_queue_purge(&cs->sq);
656 dev_kfree_skb_any(cs->tx_skb);
659 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
660 del_timer(&cs->dbusytimer);
661 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
662 schedule_event(cs, D_CLEARBUSY);
665 if (cs->debug & L1_DEB_WARN)
666 debugl1(cs, "W6692_l1hw unknown %04x", pr);
672 setstack_W6692(struct PStack *st, struct IsdnCardState *cs)
674 st->l1.l1hw = W6692_l1hw;
678 DC_Close_W6692(struct IsdnCardState *cs)
683 dbusy_timer_handler(struct IsdnCardState *cs)
685 struct PStack *stptr;
689 spin_lock_irqsave(&cs->lock, flags);
690 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
691 rbch = cs->readW6692(cs, W_D_RBCH);
692 star = cs->readW6692(cs, W_D_STAR);
694 debugl1(cs, "D-Channel Busy D_RBCH %02x D_STAR %02x",
696 if (star & W_D_STAR_XBZ) { /* D-Channel Busy */
697 test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
699 while (stptr != NULL) {
700 stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);
704 /* discard frame; reset transceiver */
705 test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
707 dev_kfree_skb_any(cs->tx_skb);
711 printk(KERN_WARNING "HiSax: W6692 D-Channel Busy no skb\n");
712 debugl1(cs, "D-Channel Busy no skb");
714 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_XRST); /* Transmitter reset */
715 spin_unlock_irqrestore(&cs->lock, flags);
716 cs->irq_func(cs->irq, cs);
720 spin_unlock_irqrestore(&cs->lock, flags);
724 W6692Bmode(struct BCState *bcs, int mode, int bchan)
726 struct IsdnCardState *cs = bcs->cs;
728 if (cs->debug & L1_DEB_HSCX)
729 debugl1(cs, "w6692 %c mode %d ichan %d",
730 '1' + bchan, mode, bchan);
732 bcs->channel = bchan;
733 bcs->hw.w6692.bchan = bchan;
737 cs->BC_Write_Reg(cs, bchan, W_B_MODE, 0);
739 case (L1_MODE_TRANS):
740 cs->BC_Write_Reg(cs, bchan, W_B_MODE, W_B_MODE_MMS);
743 cs->BC_Write_Reg(cs, bchan, W_B_MODE, W_B_MODE_ITF);
744 cs->BC_Write_Reg(cs, bchan, W_B_ADM1, 0xff);
745 cs->BC_Write_Reg(cs, bchan, W_B_ADM2, 0xff);
749 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_RRST |
750 W_B_CMDR_RACT | W_B_CMDR_XRST);
751 cs->BC_Write_Reg(cs, bchan, W_B_EXIM, 0x00);
755 W6692_l2l1(struct PStack *st, int pr, void *arg)
757 struct sk_buff *skb = arg;
758 struct BCState *bcs = st->l1.bcs;
762 case (PH_DATA | REQUEST):
763 spin_lock_irqsave(&bcs->cs->lock, flags);
765 skb_queue_tail(&bcs->squeue, skb);
768 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
769 bcs->hw.w6692.count = 0;
770 bcs->cs->BC_Send_Data(bcs);
772 spin_unlock_irqrestore(&bcs->cs->lock, flags);
774 case (PH_PULL | INDICATION):
776 printk(KERN_WARNING "W6692_l2l1: this shouldn't happen\n");
779 spin_lock_irqsave(&bcs->cs->lock, flags);
780 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
782 bcs->hw.w6692.count = 0;
783 bcs->cs->BC_Send_Data(bcs);
784 spin_unlock_irqrestore(&bcs->cs->lock, flags);
786 case (PH_PULL | REQUEST):
788 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
789 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
791 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
793 case (PH_ACTIVATE | REQUEST):
794 spin_lock_irqsave(&bcs->cs->lock, flags);
795 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
796 W6692Bmode(bcs, st->l1.mode, st->l1.bc);
797 spin_unlock_irqrestore(&bcs->cs->lock, flags);
798 l1_msg_b(st, pr, arg);
800 case (PH_DEACTIVATE | REQUEST):
801 l1_msg_b(st, pr, arg);
803 case (PH_DEACTIVATE | CONFIRM):
804 spin_lock_irqsave(&bcs->cs->lock, flags);
805 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
806 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
807 W6692Bmode(bcs, 0, st->l1.bc);
808 spin_unlock_irqrestore(&bcs->cs->lock, flags);
809 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
815 close_w6692state(struct BCState *bcs)
817 W6692Bmode(bcs, 0, bcs->channel);
818 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
819 kfree(bcs->hw.w6692.rcvbuf);
820 bcs->hw.w6692.rcvbuf = NULL;
823 skb_queue_purge(&bcs->rqueue);
824 skb_queue_purge(&bcs->squeue);
826 dev_kfree_skb_any(bcs->tx_skb);
828 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
834 open_w6692state(struct IsdnCardState *cs, struct BCState *bcs)
836 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
837 if (!(bcs->hw.w6692.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
839 "HiSax: No memory for w6692.rcvbuf\n");
840 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
843 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
845 "HiSax: No memory for bcs->blog\n");
846 test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
847 kfree(bcs->hw.w6692.rcvbuf);
848 bcs->hw.w6692.rcvbuf = NULL;
851 skb_queue_head_init(&bcs->rqueue);
852 skb_queue_head_init(&bcs->squeue);
855 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
857 bcs->hw.w6692.rcvidx = 0;
863 setstack_w6692(struct PStack *st, struct BCState *bcs)
865 bcs->channel = st->l1.bc;
866 if (open_w6692state(st->l1.hardware, bcs))
869 st->l2.l2l1 = W6692_l2l1;
870 setstack_manager(st);
876 static void resetW6692(struct IsdnCardState *cs)
878 cs->writeW6692(cs, W_D_CTL, W_D_CTL_SRST);
880 cs->writeW6692(cs, W_D_CTL, 0x00);
882 cs->writeW6692(cs, W_IMASK, 0xff);
883 cs->writeW6692(cs, W_D_SAM, 0xff);
884 cs->writeW6692(cs, W_D_TAM, 0xff);
885 cs->writeW6692(cs, W_D_EXIM, 0x00);
886 cs->writeW6692(cs, W_D_MODE, W_D_MODE_RACT);
887 cs->writeW6692(cs, W_IMASK, 0x18);
888 if (cs->subtyp == W6692_USR) {
889 /* seems that USR implemented some power control features
890 * Pin 79 is connected to the oscilator circuit so we
891 * have to handle it here
893 cs->writeW6692(cs, W_PCTL, 0x80);
894 cs->writeW6692(cs, W_XDATA, 0x00);
898 static void initW6692(struct IsdnCardState *cs, int part)
901 cs->setstack_d = setstack_W6692;
902 cs->DC_Close = DC_Close_W6692;
903 cs->dbusytimer.function = (void *) dbusy_timer_handler;
904 cs->dbusytimer.data = (long) cs;
905 init_timer(&cs->dbusytimer);
907 ph_command(cs, W_L1CMD_RST);
908 cs->dc.w6692.ph_state = W_L1CMD_RST;
910 ph_command(cs, W_L1CMD_ECK);
912 cs->bcs[0].BC_SetStack = setstack_w6692;
913 cs->bcs[1].BC_SetStack = setstack_w6692;
914 cs->bcs[0].BC_Close = close_w6692state;
915 cs->bcs[1].BC_Close = close_w6692state;
916 W6692Bmode(cs->bcs, 0, 0);
917 W6692Bmode(cs->bcs + 1, 0, 0);
920 /* Reenable all IRQ */
921 cs->writeW6692(cs, W_IMASK, 0x18);
922 cs->writeW6692(cs, W_D_EXIM, 0x00);
923 cs->BC_Write_Reg(cs, 0, W_B_EXIM, 0x00);
924 cs->BC_Write_Reg(cs, 1, W_B_EXIM, 0x00);
925 /* Reset D-chan receiver and transmitter */
926 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_RRST | W_D_CMDR_XRST);
930 /* Interface functions */
933 ReadW6692(struct IsdnCardState *cs, u_char offset)
935 return (inb(cs->hw.w6692.iobase + offset));
939 WriteW6692(struct IsdnCardState *cs, u_char offset, u_char value)
941 outb(value, cs->hw.w6692.iobase + offset);
945 ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
947 insb(cs->hw.w6692.iobase + W_D_RFIFO, data, size);
951 WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
953 outsb(cs->hw.w6692.iobase + W_D_XFIFO, data, size);
957 ReadW6692B(struct IsdnCardState *cs, int bchan, u_char offset)
959 return (inb(cs->hw.w6692.iobase + (bchan ? 0x40 : 0) + offset));
963 WriteW6692B(struct IsdnCardState *cs, int bchan, u_char offset, u_char value)
965 outb(value, cs->hw.w6692.iobase + (bchan ? 0x40 : 0) + offset);
969 w6692_card_msg(struct IsdnCardState *cs, int mt, void *arg)
976 cs->writeW6692(cs, W_IMASK, 0xff);
977 release_region(cs->hw.w6692.iobase, 256);
978 if (cs->subtyp == W6692_USR) {
979 cs->writeW6692(cs, W_XDATA, 0x04);
993 static struct pci_dev *dev_w6692 __devinitdata = NULL;
996 setup_w6692(struct IsdnCard *card)
998 struct IsdnCardState *cs = card->cs;
1002 u_int pci_ioaddr = 0;
1004 strcpy(tmp, w6692_revision);
1005 printk(KERN_INFO "HiSax: W6692 driver Rev. %s\n", HiSax_getrev(tmp));
1006 if (cs->typ != ISDN_CTYPE_W6692)
1009 while (id_list[id_idx].vendor_id) {
1010 dev_w6692 = pci_find_device(id_list[id_idx].vendor_id,
1011 id_list[id_idx].device_id,
1014 if (pci_enable_device(dev_w6692))
1016 cs->subtyp = id_idx;
1023 pci_irq = dev_w6692->irq;
1024 /* I think address 0 is allways the configuration area */
1025 /* and address 1 is the real IO space KKe 03.09.99 */
1026 pci_ioaddr = pci_resource_start(dev_w6692, 1);
1027 /* USR ISDN PCI card TA need some special handling */
1028 if (cs->subtyp == W6692_WINBOND) {
1029 if ((W6692_SV_USR == dev_w6692->subsystem_vendor) &&
1030 (W6692_SD_USR == dev_w6692->subsystem_device)) {
1031 cs->subtyp = W6692_USR;
1036 printk(KERN_WARNING "W6692: No PCI card found\n");
1041 printk(KERN_WARNING "W6692: No IRQ for PCI card found\n");
1045 printk(KERN_WARNING "W6692: NO I/O Base Address found\n");
1048 cs->hw.w6692.iobase = pci_ioaddr;
1049 printk(KERN_INFO "Found: %s %s, I/O base: 0x%x, irq: %d\n",
1050 id_list[cs->subtyp].vendor_name, id_list[cs->subtyp].card_name,
1051 pci_ioaddr, pci_irq);
1052 if (!request_region(cs->hw.w6692.iobase, 256, id_list[cs->subtyp].card_name)) {
1054 "HiSax: %s I/O ports %x-%x already in use\n",
1055 id_list[cs->subtyp].card_name,
1056 cs->hw.w6692.iobase,
1057 cs->hw.w6692.iobase + 255);
1062 "HiSax: %s config irq:%d I/O:%x\n",
1063 id_list[cs->subtyp].card_name, cs->irq,
1064 cs->hw.w6692.iobase);
1066 INIT_WORK(&cs->tqueue, W6692_bh);
1067 cs->readW6692 = &ReadW6692;
1068 cs->writeW6692 = &WriteW6692;
1069 cs->readisacfifo = &ReadISACfifo;
1070 cs->writeisacfifo = &WriteISACfifo;
1071 cs->BC_Read_Reg = &ReadW6692B;
1072 cs->BC_Write_Reg = &WriteW6692B;
1073 cs->BC_Send_Data = &W6692B_fill_fifo;
1074 cs->cardmsg = &w6692_card_msg;
1075 cs->irq_func = &W6692_interrupt;
1076 cs->irq_flags |= IRQF_SHARED;
1077 W6692Version(cs, "W6692:");
1078 printk(KERN_INFO "W6692 ISTA=0x%X\n", ReadW6692(cs, W_ISTA));
1079 printk(KERN_INFO "W6692 IMASK=0x%X\n", ReadW6692(cs, W_IMASK));
1080 printk(KERN_INFO "W6692 D_EXIR=0x%X\n", ReadW6692(cs, W_D_EXIR));
1081 printk(KERN_INFO "W6692 D_EXIM=0x%X\n", ReadW6692(cs, W_D_EXIM));
1082 printk(KERN_INFO "W6692 D_RSTA=0x%X\n", ReadW6692(cs, W_D_RSTA));