drivers/isdn/hardware/mISDN/hfcmulti.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * hfcmulti.c  low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
   4  *
   5  * Author       Andreas Eversberg (jolly@eversberg.eu)
   6  * ported to mqueue mechanism:
   7  *              Peter Sprenger (sprengermoving-bytes.de)
   8  *
   9  * inspired by existing hfc-pci driver:
  10  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  11  * Copyright 2008  by Karsten Keil (kkeil@suse.de)
  12  * Copyright 2008  by Andreas Eversberg (jolly@eversberg.eu)
  13  *
  14  * Thanks to Cologne Chip AG for this great controller!
  15  */
  16
  17 /*
  18  * module parameters:
  19  * type:
  20  *      By default (0), the card is automatically detected.
  21  *      Or use the following combinations:
  22  *      Bit 0-7   = 0x00001 = HFC-E1 (1 port)
  23  * or   Bit 0-7   = 0x00004 = HFC-4S (4 ports)
  24  * or   Bit 0-7   = 0x00008 = HFC-8S (8 ports)
  25  *      Bit 8     = 0x00100 = uLaw (instead of aLaw)
  26  *      Bit 9     = 0x00200 = Disable DTMF detect on all B-channels via hardware
  27  *      Bit 10    = spare
  28  *      Bit 11    = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
  29  * or   Bit 12    = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
  30  *      Bit 13    = spare
  31  *      Bit 14    = 0x04000 = Use external ram (128K)
  32  *      Bit 15    = 0x08000 = Use external ram (512K)
  33  *      Bit 16    = 0x10000 = Use 64 timeslots instead of 32
  34  * or   Bit 17    = 0x20000 = Use 128 timeslots instead of anything else
  35  *      Bit 18    = spare
  36  *      Bit 19    = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
  37  * (all other bits are reserved and shall be 0)
  38  *      example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
  39  *               bus (PCM master)
  40  *
  41  * port: (optional or required for all ports on all installed cards)
  42  *      HFC-4S/HFC-8S only bits:
  43  *      Bit 0     = 0x001 = Use master clock for this S/T interface
  44  *                          (ony once per chip).
  45  *      Bit 1     = 0x002 = transmitter line setup (non capacitive mode)
  46  *                          Don't use this unless you know what you are doing!
  47  *      Bit 2     = 0x004 = Disable E-channel. (No E-channel processing)
  48  *      example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
  49  *               received from port 1
  50  *
  51  *      HFC-E1 only bits:
  52  *      Bit 0     = 0x0001 = interface: 0=copper, 1=optical
  53  *      Bit 1     = 0x0002 = reserved (later for 32 B-channels transparent mode)
  54  *      Bit 2     = 0x0004 = Report LOS
  55  *      Bit 3     = 0x0008 = Report AIS
  56  *      Bit 4     = 0x0010 = Report SLIP
  57  *      Bit 5     = 0x0020 = Report RDI
  58  *      Bit 8     = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
  59  *                           mode instead.
  60  *      Bit 9     = 0x0200 = Force get clock from interface, even in NT mode.
  61  * or   Bit 10    = 0x0400 = Force put clock to interface, even in TE mode.
  62  *      Bit 11    = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
  63  *                           (E1 only)
  64  *      Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
  65  *                           for default.
  66  * (all other bits are reserved and shall be 0)
  67  *
  68  * debug:
  69  *      NOTE: only one debug value must be given for all cards
  70  *      enable debugging (see hfc_multi.h for debug options)
  71  *
  72  * poll:
  73  *      NOTE: only one poll value must be given for all cards
  74  *      Give the number of samples for each fifo process.
  75  *      By default 128 is used. Decrease to reduce delay, increase to
  76  *      reduce cpu load. If unsure, don't mess with it!
  77  *      Valid is 8, 16, 32, 64, 128, 256.
  78  *
  79  * pcm:
  80  *      NOTE: only one pcm value must be given for every card.
  81  *      The PCM bus id tells the mISDNdsp module about the connected PCM bus.
  82  *      By default (0), the PCM bus id is 100 for the card that is PCM master.
  83  *      If multiple cards are PCM master (because they are not interconnected),
  84  *      each card with PCM master will have increasing PCM id.
  85  *      All PCM busses with the same ID are expected to be connected and have
  86  *      common time slots slots.
  87  *      Only one chip of the PCM bus must be master, the others slave.
  88  *      -1 means no support of PCM bus not even.
  89  *      Omit this value, if all cards are interconnected or none is connected.
  90  *      If unsure, don't give this parameter.
  91  *
  92  * dmask and bmask:
  93  *      NOTE: One dmask value must be given for every HFC-E1 card.
  94  *      If omitted, the E1 card has D-channel on time slot 16, which is default.
  95  *      dmask is a 32 bit mask. The bit must be set for an alternate time slot.
  96  *      If multiple bits are set, multiple virtual card fragments are created.
  97  *      For each bit set, a bmask value must be given. Each bit on the bmask
  98  *      value stands for a B-channel. The bmask may not overlap with dmask or
  99  *      with other bmask values for that card.
 100  *      Example: dmask=0x00020002 bmask=0x0000fffc,0xfffc0000
 101  *              This will create one fragment with D-channel on slot 1 with
 102  *              B-channels on slots 2..15, and a second fragment with D-channel
 103  *              on slot 17 with B-channels on slot 18..31. Slot 16 is unused.
 104  *      If bit 0 is set (dmask=0x00000001) the D-channel is on slot 0 and will
 105  *      not function.
 106  *      Example: dmask=0x00000001 bmask=0xfffffffe
 107  *              This will create a port with all 31 usable timeslots as
 108  *              B-channels.
 109  *      If no bits are set on bmask, no B-channel is created for that fragment.
 110  *      Example: dmask=0xfffffffe bmask=0,0,0,0.... (31 0-values for bmask)
 111  *              This will create 31 ports with one D-channel only.
 112  *      If you don't know how to use it, you don't need it!
 113  *
 114  * iomode:
 115  *      NOTE: only one mode value must be given for every card.
 116  *      -> See hfc_multi.h for HFC_IO_MODE_* values
 117  *      By default, the IO mode is pci memory IO (MEMIO).
 118  *      Some cards require specific IO mode, so it cannot be changed.
 119  *      It may be useful to set IO mode to register io (REGIO) to solve
 120  *      PCI bridge problems.
 121  *      If unsure, don't give this parameter.
 122  *
 123  * clockdelay_nt:
 124  *      NOTE: only one clockdelay_nt value must be given once for all cards.
 125  *      Give the value of the clock control register (A_ST_CLK_DLY)
 126  *      of the S/T interfaces in NT mode.
 127  *      This register is needed for the TBR3 certification, so don't change it.
 128  *
 129  * clockdelay_te:
 130  *      NOTE: only one clockdelay_te value must be given once
 131  *      Give the value of the clock control register (A_ST_CLK_DLY)
 132  *      of the S/T interfaces in TE mode.
 133  *      This register is needed for the TBR3 certification, so don't change it.
 134  *
 135  * clock:
 136  *      NOTE: only one clock value must be given once
 137  *      Selects interface with clock source for mISDN and applications.
 138  *      Set to card number starting with 1. Set to -1 to disable.
 139  *      By default, the first card is used as clock source.
 140  *
 141  * hwid:
 142  *      NOTE: only one hwid value must be given once
 143  *      Enable special embedded devices with XHFC controllers.
 144  */
 145
 146 /*
 147  * debug register access (never use this, it will flood your system log)
 148  * #define HFC_REGISTER_DEBUG
 149  */
 150
 151 #define HFC_MULTI_VERSION       "2.03"
 152
 153 #include <linux/interrupt.h>
 154 #include <linux/module.h>
 155 #include <linux/slab.h>
 156 #include <linux/pci.h>
 157 #include <linux/delay.h>
 158 #include <linux/mISDNhw.h>
 159 #include <linux/mISDNdsp.h>
 160
 161 /*
 162   #define IRQCOUNT_DEBUG
 163   #define IRQ_DEBUG
 164 */
 165
 166 #include "hfc_multi.h"
 167 #ifdef ECHOPREP
 168 #include "gaintab.h"
 169 #endif
 170
 171 #define MAX_CARDS       8
 172 #define MAX_PORTS       (8 * MAX_CARDS)
 173 #define MAX_FRAGS       (32 * MAX_CARDS)
 174
 175 static LIST_HEAD(HFClist);
 176 static DEFINE_SPINLOCK(HFClock); /* global hfc list lock */
 177
 178 static void ph_state_change(struct dchannel *);
 179
 180 static struct hfc_multi *syncmaster;
 181 static int plxsd_master; /* if we have a master card (yet) */
 182 static DEFINE_SPINLOCK(plx_lock); /* may not acquire other lock inside */
 183
 184 #define TYP_E1          1
 185 #define TYP_4S          4
 186 #define TYP_8S          8
 187
 188 static int poll_timer = 6;      /* default = 128 samples = 16ms */
 189 /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
 190 static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30  };
 191 #define CLKDEL_TE       0x0f    /* CLKDEL in TE mode */
 192 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode
 193                                    (0x60 MUST be included!) */
 194
 195 #define DIP_4S  0x1             /* DIP Switches for Beronet 1S/2S/4S cards */
 196 #define DIP_8S  0x2             /* DIP Switches for Beronet 8S+ cards */
 197 #define DIP_E1  0x3             /* DIP Switches for Beronet E1 cards */
 198
 199 /*
 200  * module stuff
 201  */
 202
 203 static uint     type[MAX_CARDS];
 204 static int      pcm[MAX_CARDS];
 205 static uint     dmask[MAX_CARDS];
 206 static uint     bmask[MAX_FRAGS];
 207 static uint     iomode[MAX_CARDS];
 208 static uint     port[MAX_PORTS];
 209 static uint     debug;
 210 static uint     poll;
 211 static int      clock;
 212 static uint     timer;
 213 static uint     clockdelay_te = CLKDEL_TE;
 214 static uint     clockdelay_nt = CLKDEL_NT;
 215 #define HWID_NONE       0
 216 #define HWID_MINIP4     1
 217 #define HWID_MINIP8     2
 218 #define HWID_MINIP16    3
 219 static uint     hwid = HWID_NONE;
 220
 221 static int      HFC_cnt, E1_cnt, bmask_cnt, Port_cnt, PCM_cnt = 99;
 222
 223 MODULE_AUTHOR("Andreas Eversberg");
 224 MODULE_LICENSE("GPL");
 225 MODULE_VERSION(HFC_MULTI_VERSION);
 226 module_param(debug, uint, S_IRUGO | S_IWUSR);
 227 module_param(poll, uint, S_IRUGO | S_IWUSR);
 228 module_param(clock, int, S_IRUGO | S_IWUSR);
 229 module_param(timer, uint, S_IRUGO | S_IWUSR);
 230 module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
 231 module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
 232 module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
 233 module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
 234 module_param_array(dmask, uint, NULL, S_IRUGO | S_IWUSR);
 235 module_param_array(bmask, uint, NULL, S_IRUGO | S_IWUSR);
 236 module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
 237 module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
 238 module_param(hwid, uint, S_IRUGO | S_IWUSR); /* The hardware ID */
 239
 240 #ifdef HFC_REGISTER_DEBUG
 241 #define HFC_outb(hc, reg, val)                                  \
 242         (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
 243 #define HFC_outb_nodebug(hc, reg, val)                                  \
 244         (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
 245 #define HFC_inb(hc, reg)                                \
 246         (hc->HFC_inb(hc, reg, __func__, __LINE__))
 247 #define HFC_inb_nodebug(hc, reg)                                \
 248         (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
 249 #define HFC_inw(hc, reg)                                \
 250         (hc->HFC_inw(hc, reg, __func__, __LINE__))
 251 #define HFC_inw_nodebug(hc, reg)                                \
 252         (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
 253 #define HFC_wait(hc)                            \
 254         (hc->HFC_wait(hc, __func__, __LINE__))
 255 #define HFC_wait_nodebug(hc)                            \
 256         (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
 257 #else
 258 #define HFC_outb(hc, reg, val)          (hc->HFC_outb(hc, reg, val))
 259 #define HFC_outb_nodebug(hc, reg, val)  (hc->HFC_outb_nodebug(hc, reg, val))
 260 #define HFC_inb(hc, reg)                (hc->HFC_inb(hc, reg))
 261 #define HFC_inb_nodebug(hc, reg)        (hc->HFC_inb_nodebug(hc, reg))
 262 #define HFC_inw(hc, reg)                (hc->HFC_inw(hc, reg))
 263 #define HFC_inw_nodebug(hc, reg)        (hc->HFC_inw_nodebug(hc, reg))
 264 #define HFC_wait(hc)                    (hc->HFC_wait(hc))
 265 #define HFC_wait_nodebug(hc)            (hc->HFC_wait_nodebug(hc))
 266 #endif
 267
 268 #ifdef CONFIG_MISDN_HFCMULTI_8xx
 269 #include "hfc_multi_8xx.h"
 270 #endif
 271
 272 /* HFC_IO_MODE_PCIMEM */
 273 static void
 274 #ifdef HFC_REGISTER_DEBUG
 275 HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
 276                 const char *function, int line)
 277 #else
 278         HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
 279 #endif
 280 {
 281         writeb(val, hc->pci_membase + reg);
 282 }
 283 static u_char
 284 #ifdef HFC_REGISTER_DEBUG
 285 HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 286 #else
 287         HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
 288 #endif
 289 {
 290         return readb(hc->pci_membase + reg);
 291 }
 292 static u_short
 293 #ifdef HFC_REGISTER_DEBUG
 294 HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
 295 #else
 296         HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
 297 #endif
 298 {
 299         return readw(hc->pci_membase + reg);
 300 }
 301 static void
 302 #ifdef HFC_REGISTER_DEBUG
 303 HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
 304 #else
 305         HFC_wait_pcimem(struct hfc_multi *hc)
 306 #endif
 307 {
 308         while (readb(hc->pci_membase + R_STATUS) & V_BUSY)
 309                 cpu_relax();
 310 }
 311
 312 /* HFC_IO_MODE_REGIO */
 313 static void
 314 #ifdef HFC_REGISTER_DEBUG
 315 HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
 316                const char *function, int line)
 317 #else
 318         HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
 319 #endif
 320 {
 321         outb(reg, hc->pci_iobase + 4);
 322         outb(val, hc->pci_iobase);
 323 }
 324 static u_char
 325 #ifdef HFC_REGISTER_DEBUG
 326 HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 327 #else
 328         HFC_inb_regio(struct hfc_multi *hc, u_char reg)
 329 #endif
 330 {
 331         outb(reg, hc->pci_iobase + 4);
 332         return inb(hc->pci_iobase);
 333 }
 334 static u_short
 335 #ifdef HFC_REGISTER_DEBUG
 336 HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
 337 #else
 338         HFC_inw_regio(struct hfc_multi *hc, u_char reg)
 339 #endif
 340 {
 341         outb(reg, hc->pci_iobase + 4);
 342         return inw(hc->pci_iobase);
 343 }
 344 static void
 345 #ifdef HFC_REGISTER_DEBUG
 346 HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
 347 #else
 348         HFC_wait_regio(struct hfc_multi *hc)
 349 #endif
 350 {
 351         outb(R_STATUS, hc->pci_iobase + 4);
 352         while (inb(hc->pci_iobase) & V_BUSY)
 353                 cpu_relax();
 354 }
 355
 356 #ifdef HFC_REGISTER_DEBUG
 357 static void
 358 HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
 359                const char *function, int line)
 360 {
 361         char regname[256] = "", bits[9] = "xxxxxxxx";
 362         int i;
 363
 364         i = -1;
 365         while (hfc_register_names[++i].name) {
 366                 if (hfc_register_names[i].reg == reg)
 367                         strcat(regname, hfc_register_names[i].name);
 368         }
 369         if (regname[0] == '\0')
 370                 strcpy(regname, "register");
 371
 372         bits[7] = '0' + (!!(val & 1));
 373         bits[6] = '0' + (!!(val & 2));
 374         bits[5] = '0' + (!!(val & 4));
 375         bits[4] = '0' + (!!(val & 8));
 376         bits[3] = '0' + (!!(val & 16));
 377         bits[2] = '0' + (!!(val & 32));
 378         bits[1] = '0' + (!!(val & 64));
 379         bits[0] = '0' + (!!(val & 128));
 380         printk(KERN_DEBUG
 381                "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
 382                hc->id, reg, regname, val, bits, function, line);
 383         HFC_outb_nodebug(hc, reg, val);
 384 }
 385 static u_char
 386 HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 387 {
 388         char regname[256] = "", bits[9] = "xxxxxxxx";
 389         u_char val = HFC_inb_nodebug(hc, reg);
 390         int i;
 391
 392         i = 0;
 393         while (hfc_register_names[i++].name)
 394                 ;
 395         while (hfc_register_names[++i].name) {
 396                 if (hfc_register_names[i].reg == reg)
 397                         strcat(regname, hfc_register_names[i].name);
 398         }
 399         if (regname[0] == '\0')
 400                 strcpy(regname, "register");
 401
 402         bits[7] = '0' + (!!(val & 1));
 403         bits[6] = '0' + (!!(val & 2));
 404         bits[5] = '0' + (!!(val & 4));
 405         bits[4] = '0' + (!!(val & 8));
 406         bits[3] = '0' + (!!(val & 16));
 407         bits[2] = '0' + (!!(val & 32));
 408         bits[1] = '0' + (!!(val & 64));
 409         bits[0] = '0' + (!!(val & 128));
 410         printk(KERN_DEBUG
 411                "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
 412                hc->id, reg, regname, val, bits, function, line);
 413         return val;
 414 }
 415 static u_short
 416 HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
 417 {
 418         char regname[256] = "";
 419         u_short val = HFC_inw_nodebug(hc, reg);
 420         int i;
 421
 422         i = 0;
 423         while (hfc_register_names[i++].name)
 424                 ;
 425         while (hfc_register_names[++i].name) {
 426                 if (hfc_register_names[i].reg == reg)
 427                         strcat(regname, hfc_register_names[i].name);
 428         }
 429         if (regname[0] == '\0')
 430                 strcpy(regname, "register");
 431
 432         printk(KERN_DEBUG
 433                "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
 434                hc->id, reg, regname, val, function, line);
 435         return val;
 436 }
 437 static void
 438 HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
 439 {
 440         printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
 441                hc->id, function, line);
 442         HFC_wait_nodebug(hc);
 443 }
 444 #endif
 445
 446 /* write fifo data (REGIO) */
 447 static void
 448 write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 449 {
 450         outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
 451         while (len >> 2) {
 452                 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
 453                 data += 4;
 454                 len -= 4;
 455         }
 456         while (len >> 1) {
 457                 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
 458                 data += 2;
 459                 len -= 2;
 460         }
 461         while (len) {
 462                 outb(*data, hc->pci_iobase);
 463                 data++;
 464                 len--;
 465         }
 466 }
 467 /* write fifo data (PCIMEM) */
 468 static void
 469 write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 470 {
 471         while (len >> 2) {
 472                 writel(cpu_to_le32(*(u32 *)data),
 473                        hc->pci_membase + A_FIFO_DATA0);
 474                 data += 4;
 475                 len -= 4;
 476         }
 477         while (len >> 1) {
 478                 writew(cpu_to_le16(*(u16 *)data),
 479                        hc->pci_membase + A_FIFO_DATA0);
 480                 data += 2;
 481                 len -= 2;
 482         }
 483         while (len) {
 484                 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
 485                 data++;
 486                 len--;
 487         }
 488 }
 489
 490 /* read fifo data (REGIO) */
 491 static void
 492 read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
 493 {
 494         outb(A_FIFO_DATA0, (hc->pci_iobase) + 4);
 495         while (len >> 2) {
 496                 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
 497                 data += 4;
 498                 len -= 4;
 499         }
 500         while (len >> 1) {
 501                 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
 502                 data += 2;
 503                 len -= 2;
 504         }
 505         while (len) {
 506                 *data = inb(hc->pci_iobase);
 507                 data++;
 508                 len--;
 509         }
 510 }
 511
 512 /* read fifo data (PCIMEM) */
 513 static void
 514 read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
 515 {
 516         while (len >> 2) {
 517                 *(u32 *)data =
 518                         le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
 519                 data += 4;
 520                 len -= 4;
 521         }
 522         while (len >> 1) {
 523                 *(u16 *)data =
 524                         le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
 525                 data += 2;
 526                 len -= 2;
 527         }
 528         while (len) {
 529                 *data = readb(hc->pci_membase + A_FIFO_DATA0);
 530                 data++;
 531                 len--;
 532         }
 533 }
 534
 535 static void
 536 enable_hwirq(struct hfc_multi *hc)
 537 {
 538         hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
 539         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 540 }
 541
 542 static void
 543 disable_hwirq(struct hfc_multi *hc)
 544 {
 545         hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
 546         HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
 547 }
 548
 549 #define NUM_EC 2
 550 #define MAX_TDM_CHAN 32
 551
 552
 553 static inline void
 554 enablepcibridge(struct hfc_multi *c)
 555 {
 556         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
 557 }
 558
 559 static inline void
 560 disablepcibridge(struct hfc_multi *c)
 561 {
 562         HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
 563 }
 564
 565 static inline unsigned char
 566 readpcibridge(struct hfc_multi *hc, unsigned char address)
 567 {
 568         unsigned short cipv;
 569         unsigned char data;
 570
 571         if (!hc->pci_iobase)
 572                 return 0;
 573
 574         /* slow down a PCI read access by 1 PCI clock cycle */
 575         HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
 576
 577         if (address == 0)
 578                 cipv = 0x4000;
 579         else
 580                 cipv = 0x5800;
 581
 582         /* select local bridge port address by writing to CIP port */
 583         /* data = HFC_inb(c, cipv); * was _io before */
 584         outw(cipv, hc->pci_iobase + 4);
 585         data = inb(hc->pci_iobase);
 586
 587         /* restore R_CTRL for normal PCI read cycle speed */
 588         HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
 589
 590         return data;
 591 }
 592
 593 static inline void
 594 writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
 595 {
 596         unsigned short cipv;
 597         unsigned int datav;
 598
 599         if (!hc->pci_iobase)
 600                 return;
 601
 602         if (address == 0)
 603                 cipv = 0x4000;
 604         else
 605                 cipv = 0x5800;
 606
 607         /* select local bridge port address by writing to CIP port */
 608         outw(cipv, hc->pci_iobase + 4);
 609         /* define a 32 bit dword with 4 identical bytes for write sequence */
 610         datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
 611                 ((__u32) data << 24);
 612
 613         /*
 614          * write this 32 bit dword to the bridge data port
 615          * this will initiate a write sequence of up to 4 writes to the same
 616          * address on the local bus interface the number of write accesses
 617          * is undefined but >=1 and depends on the next PCI transaction
 618          * during write sequence on the local bus
 619          */
 620         outl(datav, hc->pci_iobase);
 621 }
 622
 623 static inline void
 624 cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
 625 {
 626         /* Do data pin read low byte */
 627         HFC_outb(hc, R_GPIO_OUT1, reg);
 628 }
 629
 630 static inline void
 631 cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
 632 {
 633         cpld_set_reg(hc, reg);
 634
 635         enablepcibridge(hc);
 636         writepcibridge(hc, 1, val);
 637         disablepcibridge(hc);
 638
 639         return;
 640 }
 641
 642 static inline unsigned char
 643 cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
 644 {
 645         unsigned char bytein;
 646
 647         cpld_set_reg(hc, reg);
 648
 649         /* Do data pin read low byte */
 650         HFC_outb(hc, R_GPIO_OUT1, reg);
 651
 652         enablepcibridge(hc);
 653         bytein = readpcibridge(hc, 1);
 654         disablepcibridge(hc);
 655
 656         return bytein;
 657 }
 658
 659 static inline void
 660 vpm_write_address(struct hfc_multi *hc, unsigned short addr)
 661 {
 662         cpld_write_reg(hc, 0, 0xff & addr);
 663         cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
 664 }
 665
 666 static inline unsigned short
 667 vpm_read_address(struct hfc_multi *c)
 668 {
 669         unsigned short addr;
 670         unsigned short highbit;
 671
 672         addr = cpld_read_reg(c, 0);
 673         highbit = cpld_read_reg(c, 1);
 674
 675         addr = addr | (highbit << 8);
 676
 677         return addr & 0x1ff;
 678 }
 679
 680 static inline unsigned char
 681 vpm_in(struct hfc_multi *c, int which, unsigned short addr)
 682 {
 683         unsigned char res;
 684
 685         vpm_write_address(c, addr);
 686
 687         if (!which)
 688                 cpld_set_reg(c, 2);
 689         else
 690                 cpld_set_reg(c, 3);
 691
 692         enablepcibridge(c);
 693         res = readpcibridge(c, 1);
 694         disablepcibridge(c);
 695
 696         cpld_set_reg(c, 0);
 697
 698         return res;
 699 }
 700
 701 static inline void
 702 vpm_out(struct hfc_multi *c, int which, unsigned short addr,
 703         unsigned char data)
 704 {
 705         vpm_write_address(c, addr);
 706
 707         enablepcibridge(c);
 708
 709         if (!which)
 710                 cpld_set_reg(c, 2);
 711         else
 712                 cpld_set_reg(c, 3);
 713
 714         writepcibridge(c, 1, data);
 715
 716         cpld_set_reg(c, 0);
 717
 718         disablepcibridge(c);
 719
 720         {
 721                 unsigned char regin;
 722                 regin = vpm_in(c, which, addr);
 723                 if (regin != data)
 724                         printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
 725                                "0x%x\n", data, addr, regin);
 726         }
 727
 728 }
 729
 730
 731 static void
 732 vpm_init(struct hfc_multi *wc)
 733 {
 734         unsigned char reg;
 735         unsigned int mask;
 736         unsigned int i, x, y;
 737         unsigned int ver;
 738
 739         for (x = 0; x < NUM_EC; x++) {
 740                 /* Setup GPIO's */
 741                 if (!x) {
 742                         ver = vpm_in(wc, x, 0x1a0);
 743                         printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
 744                 }
 745
 746                 for (y = 0; y < 4; y++) {
 747                         vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
 748                         vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
 749                         vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
 750                 }
 751
 752                 /* Setup TDM path - sets fsync and tdm_clk as inputs */
 753                 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
 754                 vpm_out(wc, x, 0x1a3, reg & ~2);
 755
 756                 /* Setup Echo length (256 taps) */
 757                 vpm_out(wc, x, 0x022, 1);
 758                 vpm_out(wc, x, 0x023, 0xff);
 759
 760                 /* Setup timeslots */
 761                 vpm_out(wc, x, 0x02f, 0x00);
 762                 mask = 0x02020202 << (x * 4);
 763
 764                 /* Setup the tdm channel masks for all chips */
 765                 for (i = 0; i < 4; i++)
 766                         vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
 767
 768                 /* Setup convergence rate */
 769                 printk(KERN_DEBUG "VPM: A-law mode\n");
 770                 reg = 0x00 | 0x10 | 0x01;
 771                 vpm_out(wc, x, 0x20, reg);
 772                 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
 773                 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
 774
 775                 vpm_out(wc, x, 0x24, 0x02);
 776                 reg = vpm_in(wc, x, 0x24);
 777                 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
 778
 779                 /* Initialize echo cans */
 780                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 781                         if (mask & (0x00000001 << i))
 782                                 vpm_out(wc, x, i, 0x00);
 783                 }
 784
 785                 /*
 786                  * ARM arch at least disallows a udelay of
 787                  * more than 2ms... it gives a fake "__bad_udelay"
 788                  * reference at link-time.
 789                  * long delays in kernel code are pretty sucky anyway
 790                  * for now work around it using 5 x 2ms instead of 1 x 10ms
 791                  */
 792
 793                 udelay(2000);
 794                 udelay(2000);
 795                 udelay(2000);
 796                 udelay(2000);
 797                 udelay(2000);
 798
 799                 /* Put in bypass mode */
 800                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 801                         if (mask & (0x00000001 << i))
 802                                 vpm_out(wc, x, i, 0x01);
 803                 }
 804
 805                 /* Enable bypass */
 806                 for (i = 0; i < MAX_TDM_CHAN; i++) {
 807                         if (mask & (0x00000001 << i))
 808                                 vpm_out(wc, x, 0x78 + i, 0x01);
 809                 }
 810
 811         }
 812 }
 813
 814 #ifdef UNUSED
 815 static void
 816 vpm_check(struct hfc_multi *hctmp)
 817 {
 818         unsigned char gpi2;
 819
 820         gpi2 = HFC_inb(hctmp, R_GPI_IN2);
 821
 822         if ((gpi2 & 0x3) != 0x3)
 823                 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
 824 }
 825 #endif /* UNUSED */
 826
 827
 828 /*
 829  * Interface to enable/disable the HW Echocan
 830  *
 831  * these functions are called within a spin_lock_irqsave on
 832  * the channel instance lock, so we are not disturbed by irqs
 833  *
 834  * we can later easily change the interface to make  other
 835  * things configurable, for now we configure the taps
 836  *
 837  */
 838
 839 static void
 840 vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
 841 {
 842         unsigned int timeslot;
 843         unsigned int unit;
 844         struct bchannel *bch = hc->chan[ch].bch;
 845 #ifdef TXADJ
 846         int txadj = -4;
 847         struct sk_buff *skb;
 848 #endif
 849         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 850                 return;
 851
 852         if (!bch)
 853                 return;
 854
 855 #ifdef TXADJ
 856         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 857                                sizeof(int), &txadj, GFP_ATOMIC);
 858         if (skb)
 859                 recv_Bchannel_skb(bch, skb);
 860 #endif
 861
 862         timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
 863         unit = ch % 4;
 864
 865         printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
 866                taps, timeslot);
 867
 868         vpm_out(hc, unit, timeslot, 0x7e);
 869 }
 870
 871 static void
 872 vpm_echocan_off(struct hfc_multi *hc, int ch)
 873 {
 874         unsigned int timeslot;
 875         unsigned int unit;
 876         struct bchannel *bch = hc->chan[ch].bch;
 877 #ifdef TXADJ
 878         int txadj = 0;
 879         struct sk_buff *skb;
 880 #endif
 881
 882         if (hc->chan[ch].protocol != ISDN_P_B_RAW)
 883                 return;
 884
 885         if (!bch)
 886                 return;
 887
 888 #ifdef TXADJ
 889         skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
 890                                sizeof(int), &txadj, GFP_ATOMIC);
 891         if (skb)
 892                 recv_Bchannel_skb(bch, skb);
 893 #endif
 894
 895         timeslot = ((ch / 4) * 8) + ((ch % 4) * 4) + 1;
 896         unit = ch % 4;
 897
 898         printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
 899                timeslot);
 900         /* FILLME */
 901         vpm_out(hc, unit, timeslot, 0x01);
 902 }
 903
 904
 905 /*
 906  * Speech Design resync feature
 907  * NOTE: This is called sometimes outside interrupt handler.
 908  * We must lock irqsave, so no other interrupt (other card) will occur!
 909  * Also multiple interrupts may nest, so must lock each access (lists, card)!
 910  */
 911 static inline void
 912 hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
 913 {
 914         struct hfc_multi *hc, *next, *pcmmaster = NULL;
 915         void __iomem *plx_acc_32;
 916         u_int pv;
 917         u_long flags;
 918
 919         spin_lock_irqsave(&HFClock, flags);
 920         spin_lock(&plx_lock); /* must be locked inside other locks */
 921
 922         if (debug & DEBUG_HFCMULTI_PLXSD)
 923                 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
 924                        __func__, syncmaster);
 925
 926         /* select new master */
 927         if (newmaster) {
 928                 if (debug & DEBUG_HFCMULTI_PLXSD)
 929                         printk(KERN_DEBUG "using provided controller\n");
 930         } else {
 931                 list_for_each_entry_safe(hc, next, &HFClist, list) {
 932                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 933                                 if (hc->syncronized) {
 934                                         newmaster = hc;
 935                                         break;
 936                                 }
 937                         }
 938                 }
 939         }
 940
 941         /* Disable sync of all cards */
 942         list_for_each_entry_safe(hc, next, &HFClist, list) {
 943                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
 944                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 945                         pv = readl(plx_acc_32);
 946                         pv &= ~PLX_SYNC_O_EN;
 947                         writel(pv, plx_acc_32);
 948                         if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
 949                                 pcmmaster = hc;
 950                                 if (hc->ctype == HFC_TYPE_E1) {
 951                                         if (debug & DEBUG_HFCMULTI_PLXSD)
 952                                                 printk(KERN_DEBUG
 953                                                        "Schedule SYNC_I\n");
 954                                         hc->e1_resync |= 1; /* get SYNC_I */
 955                                 }
 956                         }
 957                 }
 958         }
 959
 960         if (newmaster) {
 961                 hc = newmaster;
 962                 if (debug & DEBUG_HFCMULTI_PLXSD)
 963                         printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
 964                                "interface.\n", hc->id, hc);
 965                 /* Enable new sync master */
 966                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 967                 pv = readl(plx_acc_32);
 968                 pv |= PLX_SYNC_O_EN;
 969                 writel(pv, plx_acc_32);
 970                 /* switch to jatt PLL, if not disabled by RX_SYNC */
 971                 if (hc->ctype == HFC_TYPE_E1
 972                     && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
 973                         if (debug & DEBUG_HFCMULTI_PLXSD)
 974                                 printk(KERN_DEBUG "Schedule jatt PLL\n");
 975                         hc->e1_resync |= 2; /* switch to jatt */
 976                 }
 977         } else {
 978                 if (pcmmaster) {
 979                         hc = pcmmaster;
 980                         if (debug & DEBUG_HFCMULTI_PLXSD)
 981                                 printk(KERN_DEBUG
 982                                        "id=%d (0x%p) = PCM master syncronized "
 983                                        "with QUARTZ\n", hc->id, hc);
 984                         if (hc->ctype == HFC_TYPE_E1) {
 985                                 /* Use the crystal clock for the PCM
 986                                    master card */
 987                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 988                                         printk(KERN_DEBUG
 989                                                "Schedule QUARTZ for HFC-E1\n");
 990                                 hc->e1_resync |= 4; /* switch quartz */
 991                         } else {
 992                                 if (debug & DEBUG_HFCMULTI_PLXSD)
 993                                         printk(KERN_DEBUG
 994                                                "QUARTZ is automatically "
 995                                                "enabled by HFC-%dS\n", hc->ctype);
 996                         }
 997                         plx_acc_32 = hc->plx_membase + PLX_GPIOC;
 998                         pv = readl(plx_acc_32);
 999                         pv |= PLX_SYNC_O_EN;
1000                         writel(pv, plx_acc_32);
1001                 } else
1002                         if (!rm)
1003                                 printk(KERN_ERR "%s no pcm master, this MUST "
1004                                        "not happen!\n", __func__);
1005         }
1006         syncmaster = newmaster;
1007
1008         spin_unlock(&plx_lock);
1009         spin_unlock_irqrestore(&HFClock, flags);
1010 }
1011
1012 /* This must be called AND hc must be locked irqsave!!! */
1013 static inline void
1014 plxsd_checksync(struct hfc_multi *hc, int rm)
1015 {
1016         if (hc->syncronized) {
1017                 if (syncmaster == NULL) {
1018                         if (debug & DEBUG_HFCMULTI_PLXSD)
1019                                 printk(KERN_DEBUG "%s: GOT sync on card %d"
1020                                        " (id=%d)\n", __func__, hc->id + 1,
1021                                        hc->id);
1022                         hfcmulti_resync(hc, hc, rm);
1023                 }
1024         } else {
1025                 if (syncmaster == hc) {
1026                         if (debug & DEBUG_HFCMULTI_PLXSD)
1027                                 printk(KERN_DEBUG "%s: LOST sync on card %d"
1028                                        " (id=%d)\n", __func__, hc->id + 1,
1029                                        hc->id);
1030                         hfcmulti_resync(hc, NULL, rm);
1031                 }
1032         }
1033 }
1034
1035
1036 /*
1037  * free hardware resources used by driver
1038  */
1039 static void
1040 release_io_hfcmulti(struct hfc_multi *hc)
1041 {
1042         void __iomem *plx_acc_32;
1043         u_int   pv;
1044         u_long  plx_flags;
1045
1046         if (debug & DEBUG_HFCMULTI_INIT)
1047                 printk(KERN_DEBUG "%s: entered\n", __func__);
1048
1049         /* soft reset also masks all interrupts */
1050         hc->hw.r_cirm |= V_SRES;
1051         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1052         udelay(1000);
1053         hc->hw.r_cirm &= ~V_SRES;
1054         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1055         udelay(1000); /* instead of 'wait' that may cause locking */
1056
1057         /* release Speech Design card, if PLX was initialized */
1058         if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1059                 if (debug & DEBUG_HFCMULTI_PLXSD)
1060                         printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1061                                __func__, hc->id + 1);
1062                 spin_lock_irqsave(&plx_lock, plx_flags);
1063                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1064                 writel(PLX_GPIOC_INIT, plx_acc_32);
1065                 pv = readl(plx_acc_32);
1066                 /* Termination off */
1067                 pv &= ~PLX_TERM_ON;
1068                 /* Disconnect the PCM */
1069                 pv |= PLX_SLAVE_EN_N;
1070                 pv &= ~PLX_MASTER_EN;
1071                 pv &= ~PLX_SYNC_O_EN;
1072                 /* Put the DSP in Reset */
1073                 pv &= ~PLX_DSP_RES_N;
1074                 writel(pv, plx_acc_32);
1075                 if (debug & DEBUG_HFCMULTI_INIT)
1076                         printk(KERN_DEBUG "%s: PCM off: PLX_GPIO=%x\n",
1077                                __func__, pv);
1078                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1079         }
1080
1081         /* disable memory mapped ports / io ports */
1082         test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1083         if (hc->pci_dev)
1084                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1085         if (hc->pci_membase)
1086                 iounmap(hc->pci_membase);
1087         if (hc->plx_membase)
1088                 iounmap(hc->plx_membase);
1089         if (hc->pci_iobase)
1090                 release_region(hc->pci_iobase, 8);
1091         if (hc->xhfc_membase)
1092                 iounmap((void *)hc->xhfc_membase);
1093
1094         if (hc->pci_dev) {
1095                 pci_disable_device(hc->pci_dev);
1096                 pci_set_drvdata(hc->pci_dev, NULL);
1097         }
1098         if (debug & DEBUG_HFCMULTI_INIT)
1099                 printk(KERN_DEBUG "%s: done\n", __func__);
1100 }
1101
1102 /*
1103  * function called to reset the HFC chip. A complete software reset of chip
1104  * and fifos is done. All configuration of the chip is done.
1105  */
1106
1107 static int
1108 init_chip(struct hfc_multi *hc)
1109 {
1110         u_long                  flags, val, val2 = 0, rev;
1111         int                     i, err = 0;
1112         u_char                  r_conf_en, rval;
1113         void __iomem            *plx_acc_32;
1114         u_int                   pv;
1115         u_long                  plx_flags, hfc_flags;
1116         int                     plx_count;
1117         struct hfc_multi        *pos, *next, *plx_last_hc;
1118
1119         spin_lock_irqsave(&hc->lock, flags);
1120         /* reset all registers */
1121         memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1122
1123         /* revision check */
1124         if (debug & DEBUG_HFCMULTI_INIT)
1125                 printk(KERN_DEBUG "%s: entered\n", __func__);
1126         val = HFC_inb(hc, R_CHIP_ID);
1127         if ((val >> 4) != 0x8 && (val >> 4) != 0xc && (val >> 4) != 0xe &&
1128             (val >> 1) != 0x31) {
1129                 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1130                 err = -EIO;
1131                 goto out;
1132         }
1133         rev = HFC_inb(hc, R_CHIP_RV);
1134         printk(KERN_INFO
1135                "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1136                val, rev, (rev == 0 && (hc->ctype != HFC_TYPE_XHFC)) ?
1137                " (old FIFO handling)" : "");
1138         if (hc->ctype != HFC_TYPE_XHFC && rev == 0) {
1139                 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1140                 printk(KERN_WARNING
1141                        "HFC_multi: NOTE: Your chip is revision 0, "
1142                        "ask Cologne Chip for update. Newer chips "
1143                        "have a better FIFO handling. Old chips "
1144                        "still work but may have slightly lower "
1145                        "HDLC transmit performance.\n");
1146         }
1147         if (rev > 1) {
1148                 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1149                        "consider chip revision = %ld. The chip / "
1150                        "bridge may not work.\n", rev);
1151         }
1152
1153         /* set s-ram size */
1154         hc->Flen = 0x10;
1155         hc->Zmin = 0x80;
1156         hc->Zlen = 384;
1157         hc->DTMFbase = 0x1000;
1158         if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1159                 if (debug & DEBUG_HFCMULTI_INIT)
1160                         printk(KERN_DEBUG "%s: changing to 128K external RAM\n",
1161                                __func__);
1162                 hc->hw.r_ctrl |= V_EXT_RAM;
1163                 hc->hw.r_ram_sz = 1;
1164                 hc->Flen = 0x20;
1165                 hc->Zmin = 0xc0;
1166                 hc->Zlen = 1856;
1167                 hc->DTMFbase = 0x2000;
1168         }
1169         if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1170                 if (debug & DEBUG_HFCMULTI_INIT)
1171                         printk(KERN_DEBUG "%s: changing to 512K external RAM\n",
1172                                __func__);
1173                 hc->hw.r_ctrl |= V_EXT_RAM;
1174                 hc->hw.r_ram_sz = 2;
1175                 hc->Flen = 0x20;
1176                 hc->Zmin = 0xc0;
1177                 hc->Zlen = 8000;
1178                 hc->DTMFbase = 0x2000;
1179         }
1180         if (hc->ctype == HFC_TYPE_XHFC) {
1181                 hc->Flen = 0x8;
1182                 hc->Zmin = 0x0;
1183                 hc->Zlen = 64;
1184                 hc->DTMFbase = 0x0;
1185         }
1186         hc->max_trans = poll << 1;
1187         if (hc->max_trans > hc->Zlen)
1188                 hc->max_trans = hc->Zlen;
1189
1190         /* Speech Design PLX bridge */
1191         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1192                 if (debug & DEBUG_HFCMULTI_PLXSD)
1193                         printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1194                                __func__, hc->id + 1);
1195                 spin_lock_irqsave(&plx_lock, plx_flags);
1196                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1197                 writel(PLX_GPIOC_INIT, plx_acc_32);
1198                 pv = readl(plx_acc_32);
1199                 /* The first and the last cards are terminating the PCM bus */
1200                 pv |= PLX_TERM_ON; /* hc is currently the last */
1201                 /* Disconnect the PCM */
1202                 pv |= PLX_SLAVE_EN_N;
1203                 pv &= ~PLX_MASTER_EN;
1204                 pv &= ~PLX_SYNC_O_EN;
1205                 /* Put the DSP in Reset */
1206                 pv &= ~PLX_DSP_RES_N;
1207                 writel(pv, plx_acc_32);
1208                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1209                 if (debug & DEBUG_HFCMULTI_INIT)
1210                         printk(KERN_DEBUG "%s: slave/term: PLX_GPIO=%x\n",
1211                                __func__, pv);
1212                 /*
1213                  * If we are the 3rd PLXSD card or higher, we must turn
1214                  * termination of last PLXSD card off.
1215                  */
1216                 spin_lock_irqsave(&HFClock, hfc_flags);
1217                 plx_count = 0;
1218                 plx_last_hc = NULL;
1219                 list_for_each_entry_safe(pos, next, &HFClist, list) {
1220                         if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1221                                 plx_count++;
1222                                 if (pos != hc)
1223                                         plx_last_hc = pos;
1224                         }
1225                 }
1226                 if (plx_count >= 3) {
1227                         if (debug & DEBUG_HFCMULTI_PLXSD)
1228                                 printk(KERN_DEBUG "%s: card %d is between, so "
1229                                        "we disable termination\n",
1230                                        __func__, plx_last_hc->id + 1);
1231                         spin_lock_irqsave(&plx_lock, plx_flags);
1232                         plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
1233                         pv = readl(plx_acc_32);
1234                         pv &= ~PLX_TERM_ON;
1235                         writel(pv, plx_acc_32);
1236                         spin_unlock_irqrestore(&plx_lock, plx_flags);
1237                         if (debug & DEBUG_HFCMULTI_INIT)
1238                                 printk(KERN_DEBUG
1239                                        "%s: term off: PLX_GPIO=%x\n",
1240                                        __func__, pv);
1241                 }
1242                 spin_unlock_irqrestore(&HFClock, hfc_flags);
1243                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1244         }
1245
1246         if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1247                 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1248
1249         /* we only want the real Z2 read-pointer for revision > 0 */
1250         if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1251                 hc->hw.r_ram_sz |= V_FZ_MD;
1252
1253         /* select pcm mode */
1254         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1255                 if (debug & DEBUG_HFCMULTI_INIT)
1256                         printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1257                                __func__);
1258         } else
1259                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1260                         if (debug & DEBUG_HFCMULTI_INIT)
1261                                 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1262                                        __func__);
1263                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1264                 } else {
1265                         if (debug & DEBUG_HFCMULTI_INIT)
1266                                 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1267                                        __func__);
1268                 }
1269
1270         /* soft reset */
1271         HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1272         if (hc->ctype == HFC_TYPE_XHFC)
1273                 HFC_outb(hc, 0x0C /* R_FIFO_THRES */,
1274                          0x11 /* 16 Bytes TX/RX */);
1275         else
1276                 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1277         HFC_outb(hc, R_FIFO_MD, 0);
1278         if (hc->ctype == HFC_TYPE_XHFC)
1279                 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
1280         else
1281                 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES
1282                         | V_RLD_EPR;
1283         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1284         udelay(100);
1285         hc->hw.r_cirm = 0;
1286         HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1287         udelay(100);
1288         if (hc->ctype != HFC_TYPE_XHFC)
1289                 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1290
1291         /* Speech Design PLX bridge pcm and sync mode */
1292         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1293                 spin_lock_irqsave(&plx_lock, plx_flags);
1294                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1295                 pv = readl(plx_acc_32);
1296                 /* Connect PCM */
1297                 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1298                         pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1299                         pv |= PLX_SYNC_O_EN;
1300                         if (debug & DEBUG_HFCMULTI_INIT)
1301                                 printk(KERN_DEBUG "%s: master: PLX_GPIO=%x\n",
1302                                        __func__, pv);
1303                 } else {
1304                         pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1305                         pv &= ~PLX_SYNC_O_EN;
1306                         if (debug & DEBUG_HFCMULTI_INIT)
1307                                 printk(KERN_DEBUG "%s: slave: PLX_GPIO=%x\n",
1308                                        __func__, pv);
1309                 }
1310                 writel(pv, plx_acc_32);
1311                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1312         }
1313
1314         /* PCM setup */
1315         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1316         if (hc->slots == 32)
1317                 HFC_outb(hc, R_PCM_MD1, 0x00);
1318         if (hc->slots == 64)
1319                 HFC_outb(hc, R_PCM_MD1, 0x10);
1320         if (hc->slots == 128)
1321                 HFC_outb(hc, R_PCM_MD1, 0x20);
1322         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1323         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1324                 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1325         else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1326                 HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
1327         else
1328                 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1329         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1330         for (i = 0; i < 256; i++) {
1331                 HFC_outb_nodebug(hc, R_SLOT, i);
1332                 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1333                 if (hc->ctype != HFC_TYPE_XHFC)
1334                         HFC_outb_nodebug(hc, A_CONF, 0);
1335                 hc->slot_owner[i] = -1;
1336         }
1337
1338         /* set clock speed */
1339         if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1340                 if (debug & DEBUG_HFCMULTI_INIT)
1341                         printk(KERN_DEBUG
1342                                "%s: setting double clock\n", __func__);
1343                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1344         }
1345
1346         if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
1347                 HFC_outb(hc, 0x02 /* R_CLK_CFG */, 0x40 /* V_CLKO_OFF */);
1348
1349         /* B410P GPIO */
1350         if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1351                 printk(KERN_NOTICE "Setting GPIOs\n");
1352                 HFC_outb(hc, R_GPIO_SEL, 0x30);
1353                 HFC_outb(hc, R_GPIO_EN1, 0x3);
1354                 udelay(1000);
1355                 printk(KERN_NOTICE "calling vpm_init\n");
1356                 vpm_init(hc);
1357         }
1358
1359         /* check if R_F0_CNT counts (8 kHz frame count) */
1360         val = HFC_inb(hc, R_F0_CNTL);
1361         val += HFC_inb(hc, R_F0_CNTH) << 8;
1362         if (debug & DEBUG_HFCMULTI_INIT)
1363                 printk(KERN_DEBUG
1364                        "HFC_multi F0_CNT %ld after reset\n", val);
1365         spin_unlock_irqrestore(&hc->lock, flags);
1366         set_current_state(TASK_UNINTERRUPTIBLE);
1367         schedule_timeout((HZ / 100) ? : 1); /* Timeout minimum 10ms */
1368         spin_lock_irqsave(&hc->lock, flags);
1369         val2 = HFC_inb(hc, R_F0_CNTL);
1370         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1371         if (debug & DEBUG_HFCMULTI_INIT)
1372                 printk(KERN_DEBUG
1373                        "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1374                        val2);
1375         if (val2 >= val + 8) { /* 1 ms */
1376                 /* it counts, so we keep the pcm mode */
1377                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1378                         printk(KERN_INFO "controller is PCM bus MASTER\n");
1379                 else
1380                         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1381                                 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1382                         else {
1383                                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1384                                 printk(KERN_INFO "controller is PCM bus SLAVE "
1385                                        "(auto detected)\n");
1386                         }
1387         } else {
1388                 /* does not count */
1389                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1390                 controller_fail:
1391                         printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1392                                "pulse. Seems that controller fails.\n");
1393                         err = -EIO;
1394                         goto out;
1395                 }
1396                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1397                         printk(KERN_INFO "controller is PCM bus SLAVE "
1398                                "(ignoring missing PCM clock)\n");
1399                 } else {
1400                         /* only one pcm master */
1401                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1402                             && plxsd_master) {
1403                                 printk(KERN_ERR "HFC_multi ERROR, no clock "
1404                                        "on another Speech Design card found. "
1405                                        "Please be sure to connect PCM cable.\n");
1406                                 err = -EIO;
1407                                 goto out;
1408                         }
1409                         /* retry with master clock */
1410                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1411                                 spin_lock_irqsave(&plx_lock, plx_flags);
1412                                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1413                                 pv = readl(plx_acc_32);
1414                                 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1415                                 pv |= PLX_SYNC_O_EN;
1416                                 writel(pv, plx_acc_32);
1417                                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1418                                 if (debug & DEBUG_HFCMULTI_INIT)
1419                                         printk(KERN_DEBUG "%s: master: "
1420                                                "PLX_GPIO=%x\n", __func__, pv);
1421                         }
1422                         hc->hw.r_pcm_md0 |= V_PCM_MD;
1423                         HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1424                         spin_unlock_irqrestore(&hc->lock, flags);
1425                         set_current_state(TASK_UNINTERRUPTIBLE);
1426                         schedule_timeout((HZ / 100) ?: 1); /* Timeout min. 10ms */
1427                         spin_lock_irqsave(&hc->lock, flags);
1428                         val2 = HFC_inb(hc, R_F0_CNTL);
1429                         val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1430                         if (debug & DEBUG_HFCMULTI_INIT)
1431                                 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1432                                        "10 ms (2nd try)\n", val2);
1433                         if (val2 >= val + 8) { /* 1 ms */
1434                                 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1435                                                  &hc->chip);
1436                                 printk(KERN_INFO "controller is PCM bus MASTER "
1437                                        "(auto detected)\n");
1438                         } else
1439                                 goto controller_fail;
1440                 }
1441         }
1442
1443         /* Release the DSP Reset */
1444         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1445                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1446                         plxsd_master = 1;
1447                 spin_lock_irqsave(&plx_lock, plx_flags);
1448                 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
1449                 pv = readl(plx_acc_32);
1450                 pv |=  PLX_DSP_RES_N;
1451                 writel(pv, plx_acc_32);
1452                 spin_unlock_irqrestore(&plx_lock, plx_flags);
1453                 if (debug & DEBUG_HFCMULTI_INIT)
1454                         printk(KERN_DEBUG "%s: reset off: PLX_GPIO=%x\n",
1455                                __func__, pv);
1456         }
1457
1458         /* pcm id */
1459         if (hc->pcm)
1460                 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1461                        hc->pcm);
1462         else {
1463                 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1464                     || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1465                         PCM_cnt++; /* SD has proprietary bridging */
1466                 }
1467                 hc->pcm = PCM_cnt;
1468                 printk(KERN_INFO "controller has PCM BUS ID %d "
1469                        "(auto selected)\n", hc->pcm);
1470         }
1471
1472         /* set up timer */
1473         HFC_outb(hc, R_TI_WD, poll_timer);
1474         hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1475
1476         /* set E1 state machine IRQ */
1477         if (hc->ctype == HFC_TYPE_E1)
1478                 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1479
1480         /* set DTMF detection */
1481         if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1482                 if (debug & DEBUG_HFCMULTI_INIT)
1483                         printk(KERN_DEBUG "%s: enabling DTMF detection "
1484                                "for all B-channel\n", __func__);
1485                 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1486                 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1487                         hc->hw.r_dtmf |= V_ULAW_SEL;
1488                 HFC_outb(hc, R_DTMF_N, 102 - 1);
1489                 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1490         }
1491
1492         /* conference engine */
1493         if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1494                 r_conf_en = V_CONF_EN | V_ULAW;
1495         else
1496                 r_conf_en = V_CONF_EN;
1497         if (hc->ctype != HFC_TYPE_XHFC)
1498                 HFC_outb(hc, R_CONF_EN, r_conf_en);
1499
1500         /* setting leds */
1501         switch (hc->leds) {
1502         case 1: /* HFC-E1 OEM */
1503                 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1504                         HFC_outb(hc, R_GPIO_SEL, 0x32);
1505                 else
1506                         HFC_outb(hc, R_GPIO_SEL, 0x30);
1507
1508                 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1509                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1510
1511                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1512                 break;
1513
1514         case 2: /* HFC-4S OEM */
1515         case 3:
1516                 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1517                 HFC_outb(hc, R_GPIO_EN1, 0xff);
1518                 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1519                 break;
1520         }
1521
1522         if (test_bit(HFC_CHIP_EMBSD, &hc->chip)) {
1523                 hc->hw.r_st_sync = 0x10; /* V_AUTO_SYNCI */
1524                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1525         }
1526
1527         /* set master clock */
1528         if (hc->masterclk >= 0) {
1529                 if (debug & DEBUG_HFCMULTI_INIT)
1530                         printk(KERN_DEBUG "%s: setting ST master clock "
1531                                "to port %d (0..%d)\n",
1532                                __func__, hc->masterclk, hc->ports - 1);
1533                 hc->hw.r_st_sync |= (hc->masterclk | V_AUTO_SYNC);
1534                 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1535         }
1536
1537
1538
1539         /* setting misc irq */
1540         HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1541         if (debug & DEBUG_HFCMULTI_INIT)
1542                 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1543                        hc->hw.r_irqmsk_misc);
1544
1545         /* RAM access test */
1546         HFC_outb(hc, R_RAM_ADDR0, 0);
1547         HFC_outb(hc, R_RAM_ADDR1, 0);
1548         HFC_outb(hc, R_RAM_ADDR2, 0);
1549         for (i = 0; i < 256; i++) {
1550                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1551                 HFC_outb_nodebug(hc, R_RAM_DATA, ((i * 3) & 0xff));
1552         }
1553         for (i = 0; i < 256; i++) {
1554                 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1555                 HFC_inb_nodebug(hc, R_RAM_DATA);
1556                 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1557                 if (rval != ((i * 3) & 0xff)) {
1558                         printk(KERN_DEBUG
1559                                "addr:%x val:%x should:%x\n", i, rval,
1560                                (i * 3) & 0xff);
1561                         err++;
1562                 }
1563         }
1564         if (err) {
1565                 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1566                 err = -EIO;
1567                 goto out;
1568         }
1569
1570         if (debug & DEBUG_HFCMULTI_INIT)
1571                 printk(KERN_DEBUG "%s: done\n", __func__);
1572 out:
1573         spin_unlock_irqrestore(&hc->lock, flags);
1574         return err;
1575 }
1576
1577
1578 /*
1579  * control the watchdog
1580  */
1581 static void
1582 hfcmulti_watchdog(struct hfc_multi *hc)
1583 {
1584         hc->wdcount++;
1585
1586         if (hc->wdcount > 10) {
1587                 hc->wdcount = 0;
1588                 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1589                         V_GPIO_OUT3 : V_GPIO_OUT2;
1590
1591                 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1592                 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1593                 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1594         }
1595 }
1596
1597
1598
1599 /*
1600  * output leds
1601  */
1602 static void
1603 hfcmulti_leds(struct hfc_multi *hc)
1604 {
1605         unsigned long lled;
1606         unsigned long leddw;
1607         int i, state, active, leds;
1608         struct dchannel *dch;
1609         int led[4];
1610
1611         switch (hc->leds) {
1612         case 1: /* HFC-E1 OEM */
1613                 /* 2 red steady:       LOS
1614                  * 1 red steady:       L1 not active
1615                  * 2 green steady:     L1 active
1616                  * 1st green flashing: activity on TX
1617                  * 2nd green flashing: activity on RX
1618                  */
1619                 led[0] = 0;
1620                 led[1] = 0;
1621                 led[2] = 0;
1622                 led[3] = 0;
1623                 dch = hc->chan[hc->dnum[0]].dch;
1624                 if (dch) {
1625                         if (hc->chan[hc->dnum[0]].los)
1626                                 led[1] = 1;
1627                         if (hc->e1_state != 1) {
1628                                 led[0] = 1;
1629                                 hc->flash[2] = 0;
1630                                 hc->flash[3] = 0;
1631                         } else {
1632                                 led[2] = 1;
1633                                 led[3] = 1;
1634                                 if (!hc->flash[2] && hc->activity_tx)
1635                                         hc->flash[2] = poll;
1636                                 if (!hc->flash[3] && hc->activity_rx)
1637                                         hc->flash[3] = poll;
1638                                 if (hc->flash[2] && hc->flash[2] < 1024)
1639                                         led[2] = 0;
1640                                 if (hc->flash[3] && hc->flash[3] < 1024)
1641                                         led[3] = 0;
1642                                 if (hc->flash[2] >= 2048)
1643                                         hc->flash[2] = 0;
1644                                 if (hc->flash[3] >= 2048)
1645                                         hc->flash[3] = 0;
1646                                 if (hc->flash[2])
1647                                         hc->flash[2] += poll;
1648                                 if (hc->flash[3])
1649                                         hc->flash[3] += poll;
1650                         }
1651                 }
1652                 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1653                 /* leds are inverted */
1654                 if (leds != (int)hc->ledstate) {
1655                         HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1656                         hc->ledstate = leds;
1657                 }
1658                 break;
1659
1660         case 2: /* HFC-4S OEM */
1661                 /* red steady:     PH_DEACTIVATE
1662                  * green steady:   PH_ACTIVATE
1663                  * green flashing: activity on TX
1664                  */
1665                 for (i = 0; i < 4; i++) {
1666                         state = 0;
1667                         active = -1;
1668                         dch = hc->chan[(i << 2) | 2].dch;
1669                         if (dch) {
1670                                 state = dch->state;
1671                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1672                                         active = 3;
1673                                 else
1674                                         active = 7;
1675                         }
1676                         if (state) {
1677                                 if (state == active) {
1678                                         led[i] = 1; /* led green */
1679                                         hc->activity_tx |= hc->activity_rx;
1680                                         if (!hc->flash[i] &&
1681                                                 (hc->activity_tx & (1 << i)))
1682                                                         hc->flash[i] = poll;
1683                                         if (hc->flash[i] && hc->flash[i] < 1024)
1684                                                 led[i] = 0; /* led off */
1685                                         if (hc->flash[i] >= 2048)
1686                                                 hc->flash[i] = 0;
1687                                         if (hc->flash[i])
1688                                                 hc->flash[i] += poll;
1689                                 } else {
1690                                         led[i] = 2; /* led red */
1691                                         hc->flash[i] = 0;
1692                                 }
1693                         } else
1694                                 led[i] = 0; /* led off */
1695                 }
1696                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1697                         leds = 0;
1698                         for (i = 0; i < 4; i++) {
1699                                 if (led[i] == 1) {
1700                                         /*green*/
1701                                         leds |= (0x2 << (i * 2));
1702                                 } else if (led[i] == 2) {
1703                                         /*red*/
1704                                         leds |= (0x1 << (i * 2));
1705                                 }
1706                         }
1707                         if (leds != (int)hc->ledstate) {
1708                                 vpm_out(hc, 0, 0x1a8 + 3, leds);
1709                                 hc->ledstate = leds;
1710                         }
1711                 } else {
1712                         leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1713                                 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1714                                 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1715                                 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1716                         if (leds != (int)hc->ledstate) {
1717                                 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1718                                 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1719                                 hc->ledstate = leds;
1720                         }
1721                 }
1722                 break;
1723
1724         case 3: /* HFC 1S/2S Beronet */
1725                 /* red steady:     PH_DEACTIVATE
1726                  * green steady:   PH_ACTIVATE
1727                  * green flashing: activity on TX
1728                  */
1729                 for (i = 0; i < 2; i++) {
1730                         state = 0;
1731                         active = -1;
1732                         dch = hc->chan[(i << 2) | 2].dch;
1733                         if (dch) {
1734                                 state = dch->state;
1735                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1736                                         active = 3;
1737                                 else
1738                                         active = 7;
1739                         }
1740                         if (state) {
1741                                 if (state == active) {
1742                                         led[i] = 1; /* led green */
1743                                         hc->activity_tx |= hc->activity_rx;
1744                                         if (!hc->flash[i] &&
1745                                                 (hc->activity_tx & (1 << i)))
1746                                                         hc->flash[i] = poll;
1747                                         if (hc->flash[i] < 1024)
1748                                                 led[i] = 0; /* led off */
1749                                         if (hc->flash[i] >= 2048)
1750                                                 hc->flash[i] = 0;
1751                                         if (hc->flash[i])
1752                                                 hc->flash[i] += poll;
1753                                 } else {
1754                                         led[i] = 2; /* led red */
1755                                         hc->flash[i] = 0;
1756                                 }
1757                         } else
1758                                 led[i] = 0; /* led off */
1759                 }
1760                 leds = (led[0] > 0) | ((led[1] > 0) << 1) | ((led[0]&1) << 2)
1761                         | ((led[1]&1) << 3);
1762                 if (leds != (int)hc->ledstate) {
1763                         HFC_outb_nodebug(hc, R_GPIO_EN1,
1764                                          ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1765                         HFC_outb_nodebug(hc, R_GPIO_OUT1,
1766                                          ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1767                         hc->ledstate = leds;
1768                 }
1769                 break;
1770         case 8: /* HFC 8S+ Beronet */
1771                 /* off:      PH_DEACTIVATE
1772                  * steady:   PH_ACTIVATE
1773                  * flashing: activity on TX
1774                  */
1775                 lled = 0xff; /* leds off */
1776                 for (i = 0; i < 8; i++) {
1777                         state = 0;
1778                         active = -1;
1779                         dch = hc->chan[(i << 2) | 2].dch;
1780                         if (dch) {
1781                                 state = dch->state;
1782                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1783                                         active = 3;
1784                                 else
1785                                         active = 7;
1786                         }
1787                         if (state) {
1788                                 if (state == active) {
1789                                         lled &= ~(1 << i); /* led on */
1790                                         hc->activity_tx |= hc->activity_rx;
1791                                         if (!hc->flash[i] &&
1792                                                 (hc->activity_tx & (1 << i)))
1793                                                         hc->flash[i] = poll;
1794                                         if (hc->flash[i] < 1024)
1795                                                 lled |= 1 << i; /* led off */
1796                                         if (hc->flash[i] >= 2048)
1797                                                 hc->flash[i] = 0;
1798                                         if (hc->flash[i])
1799                                                 hc->flash[i] += poll;
1800                                 } else
1801                                         hc->flash[i] = 0;
1802                         }
1803                 }
1804                 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1805                 if (leddw != hc->ledstate) {
1806                         /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1807                            HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1808                         /* was _io before */
1809                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1810                         outw(0x4000, hc->pci_iobase + 4);
1811                         outl(leddw, hc->pci_iobase);
1812                         HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1813                         hc->ledstate = leddw;
1814                 }
1815                 break;
1816         }
1817         hc->activity_tx = 0;
1818         hc->activity_rx = 0;
1819 }
1820 /*
1821  * read dtmf coefficients
1822  */
1823
1824 static void
1825 hfcmulti_dtmf(struct hfc_multi *hc)
1826 {
1827         s32             *coeff;
1828         u_int           mantissa;
1829         int             co, ch;
1830         struct bchannel *bch = NULL;
1831         u8              exponent;
1832         int             dtmf = 0;
1833         int             addr;
1834         u16             w_float;
1835         struct sk_buff  *skb;
1836         struct mISDNhead *hh;
1837
1838         if (debug & DEBUG_HFCMULTI_DTMF)
1839                 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1840         for (ch = 0; ch <= 31; ch++) {
1841                 /* only process enabled B-channels */
1842                 bch = hc->chan[ch].bch;
1843                 if (!bch)
1844                         continue;
1845                 if (!hc->created[hc->chan[ch].port])
1846                         continue;
1847                 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1848                         continue;
1849                 if (debug & DEBUG_HFCMULTI_DTMF)
1850                         printk(KERN_DEBUG "%s: dtmf channel %d:",
1851                                __func__, ch);
1852                 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1853                 dtmf = 1;
1854                 for (co = 0; co < 8; co++) {
1855                         /* read W(n-1) coefficient */
1856                         addr = hc->DTMFbase + ((co << 7) | (ch << 2));
1857                         HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1858                         HFC_outb_nodebug(hc, R_RAM_ADDR1, addr >> 8);
1859                         HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr >> 16)
1860                                          | V_ADDR_INC);
1861                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1862                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1863                         if (debug & DEBUG_HFCMULTI_DTMF)
1864                                 printk(" %04x", w_float);
1865
1866                         /* decode float (see chip doc) */
1867                         mantissa = w_float & 0x0fff;
1868                         if (w_float & 0x8000)
1869                                 mantissa |= 0xfffff000;
1870                         exponent = (w_float >> 12) & 0x7;
1871                         if (exponent) {
1872                                 mantissa ^= 0x1000;
1873                                 mantissa <<= (exponent - 1);
1874                         }
1875
1876                         /* store coefficient */
1877                         coeff[co << 1] = mantissa;
1878
1879                         /* read W(n) coefficient */
1880                         w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1881                         w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1882                         if (debug & DEBUG_HFCMULTI_DTMF)
1883                                 printk(" %04x", w_float);
1884
1885                         /* decode float (see chip doc) */
1886                         mantissa = w_float & 0x0fff;
1887                         if (w_float & 0x8000)
1888                                 mantissa |= 0xfffff000;
1889                         exponent = (w_float >> 12) & 0x7;
1890                         if (exponent) {
1891                                 mantissa ^= 0x1000;
1892                                 mantissa <<= (exponent - 1);
1893                         }
1894
1895                         /* store coefficient */
1896                         coeff[(co << 1) | 1] = mantissa;
1897                 }
1898                 if (debug & DEBUG_HFCMULTI_DTMF)
1899                         printk(" DTMF ready %08x %08x %08x %08x "
1900                                "%08x %08x %08x %08x\n",
1901                                coeff[0], coeff[1], coeff[2], coeff[3],
1902                                coeff[4], coeff[5], coeff[6], coeff[7]);
1903                 hc->chan[ch].coeff_count++;
1904                 if (hc->chan[ch].coeff_count == 8) {
1905                         hc->chan[ch].coeff_count = 0;
1906                         skb = mI_alloc_skb(512, GFP_ATOMIC);
1907                         if (!skb) {
1908                                 printk(KERN_DEBUG "%s: No memory for skb\n",
1909                                        __func__);
1910                                 continue;
1911                         }
1912                         hh = mISDN_HEAD_P(skb);
1913                         hh->prim = PH_CONTROL_IND;
1914                         hh->id = DTMF_HFC_COEF;
1915                         skb_put_data(skb, hc->chan[ch].coeff, 512);
1916                         recv_Bchannel_skb(bch, skb);
1917                 }
1918         }
1919
1920         /* restart DTMF processing */
1921         hc->dtmf = dtmf;
1922         if (dtmf)
1923                 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1924 }
1925
1926
1927 /*
1928  * fill fifo as much as possible
1929  */
1930
1931 static void
1932 hfcmulti_tx(struct hfc_multi *hc, int ch)
1933 {
1934         int i, ii, temp, len = 0;
1935         int Zspace, z1, z2; /* must be int for calculation */
1936         int Fspace, f1, f2;
1937         u_char *d;
1938         int *txpending, slot_tx;
1939         struct  bchannel *bch;
1940         struct  dchannel *dch;
1941         struct  sk_buff **sp = NULL;
1942         int *idxp;
1943
1944         bch = hc->chan[ch].bch;
1945         dch = hc->chan[ch].dch;
1946         if ((!dch) && (!bch))
1947                 return;
1948
1949         txpending = &hc->chan[ch].txpending;
1950         slot_tx = hc->chan[ch].slot_tx;
1951         if (dch) {
1952                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1953                         return;
1954                 sp = &dch->tx_skb;
1955                 idxp = &dch->tx_idx;
1956         } else {
1957                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1958                         return;
1959                 sp = &bch->tx_skb;
1960                 idxp = &bch->tx_idx;
1961         }
1962         if (*sp)
1963                 len = (*sp)->len;
1964
1965         if ((!len) && *txpending != 1)
1966                 return; /* no data */
1967
1968         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1969             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1970             (hc->chan[ch].slot_rx < 0) &&
1971             (hc->chan[ch].slot_tx < 0))
1972                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1973         else
1974                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1975         HFC_wait_nodebug(hc);
1976
1977         if (*txpending == 2) {
1978                 /* reset fifo */
1979                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1980                 HFC_wait_nodebug(hc);
1981                 HFC_outb(hc, A_SUBCH_CFG, 0);
1982                 *txpending = 1;
1983         }
1984 next_frame:
1985         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1986                 f1 = HFC_inb_nodebug(hc, A_F1);
1987                 f2 = HFC_inb_nodebug(hc, A_F2);
1988                 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1989                         if (debug & DEBUG_HFCMULTI_FIFO)
1990                                 printk(KERN_DEBUG
1991                                        "%s(card %d): reread f2 because %d!=%d\n",
1992                                        __func__, hc->id + 1, temp, f2);
1993                         f2 = temp; /* repeat until F2 is equal */
1994                 }
1995                 Fspace = f2 - f1 - 1;
1996                 if (Fspace < 0)
1997                         Fspace += hc->Flen;
1998                 /*
1999                  * Old FIFO handling doesn't give us the current Z2 read
2000                  * pointer, so we cannot send the next frame before the fifo
2001                  * is empty. It makes no difference except for a slightly
2002                  * lower performance.
2003                  */
2004                 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
2005                         if (f1 != f2)
2006                                 Fspace = 0;
2007                         else
2008                                 Fspace = 1;
2009                 }
2010                 /* one frame only for ST D-channels, to allow resending */
2011                 if (hc->ctype != HFC_TYPE_E1 && dch) {
2012                         if (f1 != f2)
2013                                 Fspace = 0;
2014                 }
2015                 /* F-counter full condition */
2016                 if (Fspace == 0)
2017                         return;
2018         }
2019         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2020         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2021         while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
2022                 if (debug & DEBUG_HFCMULTI_FIFO)
2023                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2024                                "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2025                 z2 = temp; /* repeat unti Z2 is equal */
2026         }
2027         hc->chan[ch].Zfill = z1 - z2;
2028         if (hc->chan[ch].Zfill < 0)
2029                 hc->chan[ch].Zfill += hc->Zlen;
2030         Zspace = z2 - z1;
2031         if (Zspace <= 0)
2032                 Zspace += hc->Zlen;
2033         Zspace -= 4; /* keep not too full, so pointers will not overrun */
2034         /* fill transparent data only to maxinum transparent load (minus 4) */
2035         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2036                 Zspace = Zspace - hc->Zlen + hc->max_trans;
2037         if (Zspace <= 0) /* no space of 4 bytes */
2038                 return;
2039
2040         /* if no data */
2041         if (!len) {
2042                 if (z1 == z2) { /* empty */
2043                         /* if done with FIFO audio data during PCM connection */
2044                         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
2045                             *txpending && slot_tx >= 0) {
2046                                 if (debug & DEBUG_HFCMULTI_MODE)
2047                                         printk(KERN_DEBUG
2048                                                "%s: reconnecting PCM due to no "
2049                                                "more FIFO data: channel %d "
2050                                                "slot_tx %d\n",
2051                                                __func__, ch, slot_tx);
2052                                 /* connect slot */
2053                                 if (hc->ctype == HFC_TYPE_XHFC)
2054                                         HFC_outb(hc, A_CON_HDLC, 0xc0
2055                                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2056                                 /* Enable FIFO, no interrupt */
2057                                 else
2058                                         HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2059                                                  V_HDLC_TRP | V_IFF);
2060                                 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2061                                 HFC_wait_nodebug(hc);
2062                                 if (hc->ctype == HFC_TYPE_XHFC)
2063                                         HFC_outb(hc, A_CON_HDLC, 0xc0
2064                                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2065                                 /* Enable FIFO, no interrupt */
2066                                 else
2067                                         HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
2068                                                  V_HDLC_TRP | V_IFF);
2069                                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2070                                 HFC_wait_nodebug(hc);
2071                         }
2072                         *txpending = 0;
2073                 }
2074                 return; /* no data */
2075         }
2076
2077         /* "fill fifo if empty" feature */
2078         if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
2079             && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
2080                 if (debug & DEBUG_HFCMULTI_FILL)
2081                         printk(KERN_DEBUG "%s: buffer empty, so we have "
2082                                "underrun\n", __func__);
2083                 /* fill buffer, to prevent future underrun */
2084                 hc->write_fifo(hc, hc->silence_data, poll >> 1);
2085                 Zspace -= (poll >> 1);
2086         }
2087
2088         /* if audio data and connected slot */
2089         if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2090             && slot_tx >= 0) {
2091                 if (debug & DEBUG_HFCMULTI_MODE)
2092                         printk(KERN_DEBUG "%s: disconnecting PCM due to "
2093                                "FIFO data: channel %d slot_tx %d\n",
2094                                __func__, ch, slot_tx);
2095                 /* disconnect slot */
2096                 if (hc->ctype == HFC_TYPE_XHFC)
2097                         HFC_outb(hc, A_CON_HDLC, 0x80
2098                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2099                 /* Enable FIFO, no interrupt */
2100                 else
2101                         HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2102                                  V_HDLC_TRP | V_IFF);
2103                 HFC_outb_nodebug(hc, R_FIFO, ch << 1 | 1);
2104                 HFC_wait_nodebug(hc);
2105                 if (hc->ctype == HFC_TYPE_XHFC)
2106                         HFC_outb(hc, A_CON_HDLC, 0x80
2107                                  | 0x07 << 2 | V_HDLC_TRP | V_IFF);
2108                 /* Enable FIFO, no interrupt */
2109                 else
2110                         HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 |
2111                                  V_HDLC_TRP | V_IFF);
2112                 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
2113                 HFC_wait_nodebug(hc);
2114         }
2115         *txpending = 1;
2116
2117         /* show activity */
2118         if (dch)
2119                 hc->activity_tx |= 1 << hc->chan[ch].port;
2120
2121         /* fill fifo to what we have left */
2122         ii = len;
2123         if (dch || test_bit(FLG_HDLC, &bch->Flags))
2124                 temp = 1;
2125         else
2126                 temp = 0;
2127         i = *idxp;
2128         d = (*sp)->data + i;
2129         if (ii - i > Zspace)
2130                 ii = Zspace + i;
2131         if (debug & DEBUG_HFCMULTI_FIFO)
2132                 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2133                        "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2134                        __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2135                        temp ? "HDLC" : "TRANS");
2136
2137         /* Have to prep the audio data */
2138         hc->write_fifo(hc, d, ii - i);
2139         hc->chan[ch].Zfill += ii - i;
2140         *idxp = ii;
2141
2142         /* if not all data has been written */
2143         if (ii != len) {
2144                 /* NOTE: fifo is started by the calling function */
2145                 return;
2146         }
2147
2148         /* if all data has been written, terminate frame */
2149         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2150                 /* increment f-counter */
2151                 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2152                 HFC_wait_nodebug(hc);
2153         }
2154
2155         dev_kfree_skb(*sp);
2156         /* check for next frame */
2157         if (bch && get_next_bframe(bch)) {
2158                 len = (*sp)->len;
2159                 goto next_frame;
2160         }
2161         if (dch && get_next_dframe(dch)) {
2162                 len = (*sp)->len;
2163                 goto next_frame;
2164         }
2165
2166         /*
2167          * now we have no more data, so in case of transparent,
2168          * we set the last byte in fifo to 'silence' in case we will get
2169          * no more data at all. this prevents sending an undefined value.
2170          */
2171         if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2172                 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
2173 }
2174
2175
2176 /* NOTE: only called if E1 card is in active state */
2177 static void
2178 hfcmulti_rx(struct hfc_multi *hc, int ch)
2179 {
2180         int temp;
2181         int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2182         int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2183         int again = 0;
2184         struct  bchannel *bch;
2185         struct  dchannel *dch = NULL;
2186         struct sk_buff  *skb, **sp = NULL;
2187         int     maxlen;
2188
2189         bch = hc->chan[ch].bch;
2190         if (bch) {
2191                 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2192                         return;
2193         } else if (hc->chan[ch].dch) {
2194                 dch = hc->chan[ch].dch;
2195                 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2196                         return;
2197         } else {
2198                 return;
2199         }
2200 next_frame:
2201         /* on first AND before getting next valid frame, R_FIFO must be written
2202            to. */
2203         if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2204             (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2205             (hc->chan[ch].slot_rx < 0) &&
2206             (hc->chan[ch].slot_tx < 0))
2207                 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2208         else
2209                 HFC_outb_nodebug(hc, R_FIFO, (ch << 1) | 1);
2210         HFC_wait_nodebug(hc);
2211
2212         /* ignore if rx is off BUT change fifo (above) to start pending TX */
2213         if (hc->chan[ch].rx_off) {
2214                 if (bch)
2215                         bch->dropcnt += poll; /* not exact but fair enough */
2216                 return;
2217         }
2218
2219         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2220                 f1 = HFC_inb_nodebug(hc, A_F1);
2221                 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2222                         if (debug & DEBUG_HFCMULTI_FIFO)
2223                                 printk(KERN_DEBUG
2224                                        "%s(card %d): reread f1 because %d!=%d\n",
2225                                        __func__, hc->id + 1, temp, f1);
2226                         f1 = temp; /* repeat until F1 is equal */
2227                 }
2228                 f2 = HFC_inb_nodebug(hc, A_F2);
2229         }
2230         z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2231         while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2232                 if (debug & DEBUG_HFCMULTI_FIFO)
2233                         printk(KERN_DEBUG "%s(card %d): reread z2 because "
2234                                "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2235                 z1 = temp; /* repeat until Z1 is equal */
2236         }
2237         z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2238         Zsize = z1 - z2;
2239         if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2240                 /* complete hdlc frame */
2241                 Zsize++;
2242         if (Zsize < 0)
2243                 Zsize += hc->Zlen;
2244         /* if buffer is empty */
2245         if (Zsize <= 0)
2246                 return;
2247
2248         if (bch) {
2249                 maxlen = bchannel_get_rxbuf(bch, Zsize);
2250                 if (maxlen < 0) {
2251                         pr_warn("card%d.B%d: No bufferspace for %d bytes\n",
2252                                 hc->id + 1, bch->nr, Zsize);
2253                         return;
2254                 }
2255                 sp = &bch->rx_skb;
2256                 maxlen = bch->maxlen;
2257         } else { /* Dchannel */
2258                 sp = &dch->rx_skb;
2259                 maxlen = dch->maxlen + 3;
2260                 if (*sp == NULL) {
2261                         *sp = mI_alloc_skb(maxlen, GFP_ATOMIC);
2262                         if (*sp == NULL) {
2263                                 pr_warn("card%d: No mem for dch rx_skb\n",
2264                                         hc->id + 1);
2265                                 return;
2266                         }
2267                 }
2268         }
2269         /* show activity */
2270         if (dch)
2271                 hc->activity_rx |= 1 << hc->chan[ch].port;
2272
2273         /* empty fifo with what we have */
2274         if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2275                 if (debug & DEBUG_HFCMULTI_FIFO)
2276                         printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2277                                "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2278                                "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2279                                Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2280                                f1, f2, Zsize + (*sp)->len, again);
2281                 /* HDLC */
2282                 if ((Zsize + (*sp)->len) > maxlen) {
2283                         if (debug & DEBUG_HFCMULTI_FIFO)
2284                                 printk(KERN_DEBUG
2285                                        "%s(card %d): hdlc-frame too large.\n",
2286                                        __func__, hc->id + 1);
2287                         skb_trim(*sp, 0);
2288                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2289                         HFC_wait_nodebug(hc);
2290                         return;
2291                 }
2292
2293                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2294
2295                 if (f1 != f2) {
2296                         /* increment Z2,F2-counter */
2297                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2298                         HFC_wait_nodebug(hc);
2299                         /* check size */
2300                         if ((*sp)->len < 4) {
2301                                 if (debug & DEBUG_HFCMULTI_FIFO)
2302                                         printk(KERN_DEBUG
2303                                                "%s(card %d): Frame below minimum "
2304                                                "size\n", __func__, hc->id + 1);
2305                                 skb_trim(*sp, 0);
2306                                 goto next_frame;
2307                         }
2308                         /* there is at least one complete frame, check crc */
2309                         if ((*sp)->data[(*sp)->len - 1]) {
2310                                 if (debug & DEBUG_HFCMULTI_CRC)
2311                                         printk(KERN_DEBUG
2312                                                "%s: CRC-error\n", __func__);
2313                                 skb_trim(*sp, 0);
2314                                 goto next_frame;
2315                         }
2316                         skb_trim(*sp, (*sp)->len - 3);
2317                         if ((*sp)->len < MISDN_COPY_SIZE) {
2318                                 skb = *sp;
2319                                 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2320                                 if (*sp) {
2321                                         skb_put_data(*sp, skb->data, skb->len);
2322                                         skb_trim(skb, 0);
2323                                 } else {
2324                                         printk(KERN_DEBUG "%s: No mem\n",
2325                                                __func__);
2326                                         *sp = skb;
2327                                         skb = NULL;
2328                                 }
2329                         } else {
2330                                 skb = NULL;
2331                         }
2332                         if (debug & DEBUG_HFCMULTI_FIFO) {
2333                                 printk(KERN_DEBUG "%s(card %d):",
2334                                        __func__, hc->id + 1);
2335                                 temp = 0;
2336                                 while (temp < (*sp)->len)
2337                                         printk(" %02x", (*sp)->data[temp++]);
2338                                 printk("\n");
2339                         }
2340                         if (dch)
2341                                 recv_Dchannel(dch);
2342                         else
2343                                 recv_Bchannel(bch, MISDN_ID_ANY, false);
2344                         *sp = skb;
2345                         again++;
2346                         goto next_frame;
2347                 }
2348                 /* there is an incomplete frame */
2349         } else {
2350                 /* transparent */
2351                 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2352                 if (debug & DEBUG_HFCMULTI_FIFO)
2353                         printk(KERN_DEBUG
2354                                "%s(card %d): fifo(%d) reading %d bytes "
2355                                "(z1=%04x, z2=%04x) TRANS\n",
2356                                __func__, hc->id + 1, ch, Zsize, z1, z2);
2357                 /* only bch is transparent */
2358                 recv_Bchannel(bch, hc->chan[ch].Zfill, false);
2359         }
2360 }
2361
2362
2363 /*
2364  * Interrupt handler
2365  */
2366 static void
2367 signal_state_up(struct dchannel *dch, int info, char *msg)
2368 {
2369         struct sk_buff  *skb;
2370         int             id, data = info;
2371
2372         if (debug & DEBUG_HFCMULTI_STATE)
2373                 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2374
2375         id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2376
2377         skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2378                                GFP_ATOMIC);
2379         if (!skb)
2380                 return;
2381         recv_Dchannel_skb(dch, skb);
2382 }
2383
2384 static inline void
2385 handle_timer_irq(struct hfc_multi *hc)
2386 {
2387         int             ch, temp;
2388         struct dchannel *dch;
2389         u_long          flags;
2390
2391         /* process queued resync jobs */
2392         if (hc->e1_resync) {
2393                 /* lock, so e1_resync gets not changed */
2394                 spin_lock_irqsave(&HFClock, flags);
2395                 if (hc->e1_resync & 1) {
2396                         if (debug & DEBUG_HFCMULTI_PLXSD)
2397                                 printk(KERN_DEBUG "Enable SYNC_I\n");
2398                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2399                         /* disable JATT, if RX_SYNC is set */
2400                         if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2401                                 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2402                 }
2403                 if (hc->e1_resync & 2) {
2404                         if (debug & DEBUG_HFCMULTI_PLXSD)
2405                                 printk(KERN_DEBUG "Enable jatt PLL\n");
2406                         HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2407                 }
2408                 if (hc->e1_resync & 4) {
2409                         if (debug & DEBUG_HFCMULTI_PLXSD)
2410                                 printk(KERN_DEBUG
2411                                        "Enable QUARTZ for HFC-E1\n");
2412                         /* set jatt to quartz */
2413                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2414                                  | V_JATT_OFF);
2415                         /* switch to JATT, in case it is not already */
2416                         HFC_outb(hc, R_SYNC_OUT, 0);
2417                 }
2418                 hc->e1_resync = 0;
2419                 spin_unlock_irqrestore(&HFClock, flags);
2420         }
2421
2422         if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
2423                 for (ch = 0; ch <= 31; ch++) {
2424                         if (hc->created[hc->chan[ch].port]) {
2425                                 hfcmulti_tx(hc, ch);
2426                                 /* fifo is started when switching to rx-fifo */
2427                                 hfcmulti_rx(hc, ch);
2428                                 if (hc->chan[ch].dch &&
2429                                     hc->chan[ch].nt_timer > -1) {
2430                                         dch = hc->chan[ch].dch;
2431                                         if (!(--hc->chan[ch].nt_timer)) {
2432                                                 schedule_event(dch,
2433                                                                FLG_PHCHANGE);
2434                                                 if (debug &
2435                                                     DEBUG_HFCMULTI_STATE)
2436                                                         printk(KERN_DEBUG
2437                                                                "%s: nt_timer at "
2438                                                                "state %x\n",
2439                                                                __func__,
2440                                                                dch->state);
2441                                         }
2442                                 }
2443                         }
2444                 }
2445         if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
2446                 dch = hc->chan[hc->dnum[0]].dch;
2447                 /* LOS */
2448                 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2449                 hc->chan[hc->dnum[0]].los = temp;
2450                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
2451                         if (!temp && hc->chan[hc->dnum[0]].los)
2452                                 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2453                                                 "LOS detected");
2454                         if (temp && !hc->chan[hc->dnum[0]].los)
2455                                 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2456                                                 "LOS gone");
2457                 }
2458                 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dnum[0]].cfg)) {
2459                         /* AIS */
2460                         temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2461                         if (!temp && hc->chan[hc->dnum[0]].ais)
2462                                 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2463                                                 "AIS detected");
2464                         if (temp && !hc->chan[hc->dnum[0]].ais)
2465                                 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2466                                                 "AIS gone");
2467                         hc->chan[hc->dnum[0]].ais = temp;
2468                 }
2469                 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dnum[0]].cfg)) {
2470                         /* SLIP */
2471                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2472                         if (!temp && hc->chan[hc->dnum[0]].slip_rx)
2473                                 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2474                                                 " bit SLIP detected RX");
2475                         hc->chan[hc->dnum[0]].slip_rx = temp;
2476                         temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2477                         if (!temp && hc->chan[hc->dnum[0]].slip_tx)
2478                                 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2479                                                 " bit SLIP detected TX");
2480                         hc->chan[hc->dnum[0]].slip_tx = temp;
2481                 }
2482                 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dnum[0]].cfg)) {
2483                         /* RDI */
2484                         temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2485                         if (!temp && hc->chan[hc->dnum[0]].rdi)
2486                                 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2487                                                 "RDI detected");
2488                         if (temp && !hc->chan[hc->dnum[0]].rdi)
2489                                 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2490                                                 "RDI gone");
2491                         hc->chan[hc->dnum[0]].rdi = temp;
2492                 }
2493                 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2494                 switch (hc->chan[hc->dnum[0]].sync) {
2495                 case 0:
2496                         if ((temp & 0x60) == 0x60) {
2497                                 if (debug & DEBUG_HFCMULTI_SYNC)
2498                                         printk(KERN_DEBUG
2499                                                "%s: (id=%d) E1 now "
2500                                                "in clock sync\n",
2501                                                __func__, hc->id);
2502                                 HFC_outb(hc, R_RX_OFF,
2503                                     hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2504                                 HFC_outb(hc, R_TX_OFF,
2505                                     hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
2506                                 hc->chan[hc->dnum[0]].sync = 1;
2507                                 goto check_framesync;
2508                         }
2509                         break;
2510                 case 1:
2511                         if ((temp & 0x60) != 0x60) {
2512                                 if (debug & DEBUG_HFCMULTI_SYNC)
2513                                         printk(KERN_DEBUG
2514                                                "%s: (id=%d) E1 "
2515                                                "lost clock sync\n",
2516                                                __func__, hc->id);
2517                                 hc->chan[hc->dnum[0]].sync = 0;
2518                                 break;
2519                         }
2520                 check_framesync:
2521                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2522                         if (temp == 0x27) {
2523                                 if (debug & DEBUG_HFCMULTI_SYNC)
2524                                         printk(KERN_DEBUG
2525                                                "%s: (id=%d) E1 "
2526                                                "now in frame sync\n",
2527                                                __func__, hc->id);
2528                                 hc->chan[hc->dnum[0]].sync = 2;
2529                         }
2530                         break;
2531                 case 2:
2532                         if ((temp & 0x60) != 0x60) {
2533                                 if (debug & DEBUG_HFCMULTI_SYNC)
2534                                         printk(KERN_DEBUG
2535                                                "%s: (id=%d) E1 lost "
2536                                                "clock & frame sync\n",
2537                                                __func__, hc->id);
2538                                 hc->chan[hc->dnum[0]].sync = 0;
2539                                 break;
2540                         }
2541                         temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2542                         if (temp != 0x27) {
2543                                 if (debug & DEBUG_HFCMULTI_SYNC)
2544                                         printk(KERN_DEBUG
2545                                                "%s: (id=%d) E1 "
2546                                                "lost frame sync\n",
2547                                                __func__, hc->id);
2548                                 hc->chan[hc->dnum[0]].sync = 1;
2549                         }
2550                         break;
2551                 }
2552         }
2553
2554         if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2555                 hfcmulti_watchdog(hc);
2556
2557         if (hc->leds)
2558                 hfcmulti_leds(hc);
2559 }
2560
2561 static void
2562 ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2563 {
2564         struct dchannel *dch;
2565         int             ch;
2566         int             active;
2567         u_char          st_status, temp;
2568
2569         /* state machine */
2570         for (ch = 0; ch <= 31; ch++) {
2571                 if (hc->chan[ch].dch) {
2572                         dch = hc->chan[ch].dch;
2573                         if (r_irq_statech & 1) {
2574                                 HFC_outb_nodebug(hc, R_ST_SEL,
2575                                                  hc->chan[ch].port);
2576                                 /* undocumented: delay after R_ST_SEL */
2577                                 udelay(1);
2578                                 /* undocumented: status changes during read */
2579                                 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2580                                 while (st_status != (temp =
2581                                                      HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2582                                         if (debug & DEBUG_HFCMULTI_STATE)
2583                                                 printk(KERN_DEBUG "%s: reread "
2584                                                        "STATE because %d!=%d\n",
2585                                                        __func__, temp,
2586                                                        st_status);
2587                                         st_status = temp; /* repeat */
2588                                 }
2589
2590                                 /* Speech Design TE-sync indication */
2591                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2592                                     dch->dev.D.protocol == ISDN_P_TE_S0) {
2593                                         if (st_status & V_FR_SYNC_ST)
2594                                                 hc->syncronized |=
2595                                                         (1 << hc->chan[ch].port);
2596                                         else
2597                                                 hc->syncronized &=
2598                                                         ~(1 << hc->chan[ch].port);
2599                                 }
2600                                 dch->state = st_status & 0x0f;
2601                                 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2602                                         active = 3;
2603                                 else
2604                                         active = 7;
2605                                 if (dch->state == active) {
2606                                         HFC_outb_nodebug(hc, R_FIFO,
2607                                                          (ch << 1) | 1);
2608                                         HFC_wait_nodebug(hc);
2609                                         HFC_outb_nodebug(hc,
2610                                                          R_INC_RES_FIFO, V_RES_F);
2611                                         HFC_wait_nodebug(hc);
2612                                         dch->tx_idx = 0;
2613                                 }
2614                                 schedule_event(dch, FLG_PHCHANGE);
2615                                 if (debug & DEBUG_HFCMULTI_STATE)
2616                                         printk(KERN_DEBUG
2617                                                "%s: S/T newstate %x port %d\n",
2618                                                __func__, dch->state,
2619                                                hc->chan[ch].port);
2620                         }
2621                         r_irq_statech >>= 1;
2622                 }
2623         }
2624         if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2625                 plxsd_checksync(hc, 0);
2626 }
2627
2628 static void
2629 fifo_irq(struct hfc_multi *hc, int block)
2630 {
2631         int     ch, j;
2632         struct dchannel *dch;
2633         struct bchannel *bch;
2634         u_char r_irq_fifo_bl;
2635
2636         r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2637         j = 0;
2638         while (j < 8) {
2639                 ch = (block << 2) + (j >> 1);
2640                 dch = hc->chan[ch].dch;
2641                 bch = hc->chan[ch].bch;
2642                 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2643                         j += 2;
2644                         continue;
2645                 }
2646                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2647                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2648                         hfcmulti_tx(hc, ch);
2649                         /* start fifo */
2650                         HFC_outb_nodebug(hc, R_FIFO, 0);
2651                         HFC_wait_nodebug(hc);
2652                 }
2653                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2654                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2655                         hfcmulti_tx(hc, ch);
2656                         /* start fifo */
2657                         HFC_outb_nodebug(hc, R_FIFO, 0);
2658                         HFC_wait_nodebug(hc);
2659                 }
2660                 j++;
2661                 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2662                     test_bit(FLG_ACTIVE, &dch->Flags)) {
2663                         hfcmulti_rx(hc, ch);
2664                 }
2665                 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2666                     test_bit(FLG_ACTIVE, &bch->Flags)) {
2667                         hfcmulti_rx(hc, ch);
2668                 }
2669                 j++;
2670         }
2671 }
2672
2673 #ifdef IRQ_DEBUG
2674 int irqsem;
2675 #endif
2676 static irqreturn_t
2677 hfcmulti_interrupt(int intno, void *dev_id)
2678 {
2679 #ifdef IRQCOUNT_DEBUG
2680         static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2681                 iq5 = 0, iq6 = 0, iqcnt = 0;
2682 #endif
2683         struct hfc_multi        *hc = dev_id;
2684         struct dchannel         *dch;
2685         u_char                  r_irq_statech, status, r_irq_misc, r_irq_oview;
2686         int                     i;
2687         void __iomem            *plx_acc;
2688         u_short                 wval;
2689         u_char                  e1_syncsta, temp, temp2;
2690         u_long                  flags;
2691
2692         if (!hc) {
2693                 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2694                 return IRQ_NONE;
2695         }
2696
2697         spin_lock(&hc->lock);
2698
2699 #ifdef IRQ_DEBUG
2700         if (irqsem)
2701                 printk(KERN_ERR "irq for card %d during irq from "
2702                        "card %d, this is no bug.\n", hc->id + 1, irqsem);
2703         irqsem = hc->id + 1;
2704 #endif
2705 #ifdef CONFIG_MISDN_HFCMULTI_8xx
2706         if (hc->immap->im_cpm.cp_pbdat & hc->pb_irqmsk)
2707                 goto irq_notforus;
2708 #endif
2709         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2710                 spin_lock_irqsave(&plx_lock, flags);
2711                 plx_acc = hc->plx_membase + PLX_INTCSR;
2712                 wval = readw(plx_acc);
2713                 spin_unlock_irqrestore(&plx_lock, flags);
2714                 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2715                         goto irq_notforus;
2716         }
2717
2718         status = HFC_inb_nodebug(hc, R_STATUS);
2719         r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2720 #ifdef IRQCOUNT_DEBUG
2721         if (r_irq_statech)
2722                 iq1++;
2723         if (status & V_DTMF_STA)
2724                 iq2++;
2725         if (status & V_LOST_STA)
2726                 iq3++;
2727         if (status & V_EXT_IRQSTA)
2728                 iq4++;
2729         if (status & V_MISC_IRQSTA)
2730                 iq5++;
2731         if (status & V_FR_IRQSTA)
2732                 iq6++;
2733         if (iqcnt++ > 5000) {
2734                 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2735                        iq1, iq2, iq3, iq4, iq5, iq6);
2736                 iqcnt = 0;
2737         }
2738 #endif
2739
2740         if (!r_irq_statech &&
2741             !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2742                         V_MISC_IRQSTA | V_FR_IRQSTA))) {
2743                 /* irq is not for us */
2744                 goto irq_notforus;
2745         }
2746         hc->irqcnt++;
2747         if (r_irq_statech) {
2748                 if (hc->ctype != HFC_TYPE_E1)
2749                         ph_state_irq(hc, r_irq_statech);
2750         }
2751         if (status & V_LOST_STA) {
2752                 /* LOST IRQ */
2753                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2754         }
2755         if (status & V_MISC_IRQSTA) {
2756                 /* misc IRQ */
2757                 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
2758                 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
2759                 if (r_irq_misc & V_STA_IRQ) {
2760                         if (hc->ctype == HFC_TYPE_E1) {
2761                                 /* state machine */
2762                                 dch = hc->chan[hc->dnum[0]].dch;
2763                                 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2764                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2765                                     && hc->e1_getclock) {
2766                                         if (e1_syncsta & V_FR_SYNC_E1)
2767                                                 hc->syncronized = 1;
2768                                         else
2769                                                 hc->syncronized = 0;
2770                                 }
2771                                 /* undocumented: status changes during read */
2772                                 temp = HFC_inb_nodebug(hc, R_E1_RD_STA);
2773                                 while (temp != (temp2 =
2774                                                       HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2775                                         if (debug & DEBUG_HFCMULTI_STATE)
2776                                                 printk(KERN_DEBUG "%s: reread "
2777                                                        "STATE because %d!=%d\n",
2778                                                     __func__, temp, temp2);
2779                                         temp = temp2; /* repeat */
2780                                 }
2781                                 /* broadcast state change to all fragments */
2782                                 if (debug & DEBUG_HFCMULTI_STATE)
2783                                         printk(KERN_DEBUG
2784                                                "%s: E1 (id=%d) newstate %x\n",
2785                                             __func__, hc->id, temp & 0x7);
2786                                 for (i = 0; i < hc->ports; i++) {
2787                                         dch = hc->chan[hc->dnum[i]].dch;
2788                                         dch->state = temp & 0x7;
2789                                         schedule_event(dch, FLG_PHCHANGE);
2790                                 }
2791
2792                                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2793                                         plxsd_checksync(hc, 0);
2794                         }
2795                 }
2796                 if (r_irq_misc & V_TI_IRQ) {
2797                         if (hc->iclock_on)
2798                                 mISDN_clock_update(hc->iclock, poll, NULL);
2799                         handle_timer_irq(hc);
2800                 }
2801
2802                 if (r_irq_misc & V_DTMF_IRQ)
2803                         hfcmulti_dtmf(hc);
2804
2805                 if (r_irq_misc & V_IRQ_PROC) {
2806                         static int irq_proc_cnt;
2807                         if (!irq_proc_cnt++)
2808                                 printk(KERN_DEBUG "%s: got V_IRQ_PROC -"
2809                                        " this should not happen\n", __func__);
2810                 }
2811
2812         }
2813         if (status & V_FR_IRQSTA) {
2814                 /* FIFO IRQ */
2815                 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2816                 for (i = 0; i < 8; i++) {
2817                         if (r_irq_oview & (1 << i))
2818                                 fifo_irq(hc, i);
2819                 }
2820         }
2821
2822 #ifdef IRQ_DEBUG
2823         irqsem = 0;
2824 #endif
2825         spin_unlock(&hc->lock);
2826         return IRQ_HANDLED;
2827
2828 irq_notforus:
2829 #ifdef IRQ_DEBUG
2830         irqsem = 0;
2831 #endif
2832         spin_unlock(&hc->lock);
2833         return IRQ_NONE;
2834 }
2835
2836
2837 /*
2838  * timer callback for D-chan busy resolution. Currently no function
2839  */
2840
2841 static void
2842 hfcmulti_dbusy_timer(struct timer_list *t)
2843 {
2844 }
2845
2846
2847 /*
2848  * activate/deactivate hardware for selected channels and mode
2849  *
2850  * configure B-channel with the given protocol
2851  * ch eqals to the HFC-channel (0-31)
2852  * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2853  * for S/T, 1-31 for E1)
2854  * the hdlc interrupts will be set/unset
2855  */
2856 static int
2857 mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2858               int bank_tx, int slot_rx, int bank_rx)
2859 {
2860         int flow_tx = 0, flow_rx = 0, routing = 0;
2861         int oslot_tx, oslot_rx;
2862         int conf;
2863
2864         if (ch < 0 || ch > 31)
2865                 return -EINVAL;
2866         oslot_tx = hc->chan[ch].slot_tx;
2867         oslot_rx = hc->chan[ch].slot_rx;
2868         conf = hc->chan[ch].conf;
2869
2870         if (debug & DEBUG_HFCMULTI_MODE)
2871                 printk(KERN_DEBUG
2872                        "%s: card %d channel %d protocol %x slot old=%d new=%d "
2873                        "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2874                        __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2875                        bank_tx, oslot_rx, slot_rx, bank_rx);
2876
2877         if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2878                 /* remove from slot */
2879                 if (debug & DEBUG_HFCMULTI_MODE)
2880                         printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2881                                __func__, oslot_tx);
2882                 if (hc->slot_owner[oslot_tx << 1] == ch) {
2883                         HFC_outb(hc, R_SLOT, oslot_tx << 1);
2884                         HFC_outb(hc, A_SL_CFG, 0);
2885                         if (hc->ctype != HFC_TYPE_XHFC)
2886                                 HFC_outb(hc, A_CONF, 0);
2887                         hc->slot_owner[oslot_tx << 1] = -1;
2888                 } else {
2889                         if (debug & DEBUG_HFCMULTI_MODE)
2890                                 printk(KERN_DEBUG
2891                                        "%s: we are not owner of this tx slot "
2892                                        "anymore, channel %d is.\n",
2893                                        __func__, hc->slot_owner[oslot_tx << 1]);
2894                 }
2895         }
2896
2897         if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2898                 /* remove from slot */
2899                 if (debug & DEBUG_HFCMULTI_MODE)
2900                         printk(KERN_DEBUG
2901                                "%s: remove from slot %d (RX)\n",
2902                                __func__, oslot_rx);
2903                 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2904                         HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2905                         HFC_outb(hc, A_SL_CFG, 0);
2906                         hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2907                 } else {
2908                         if (debug & DEBUG_HFCMULTI_MODE)
2909                                 printk(KERN_DEBUG
2910                                        "%s: we are not owner of this rx slot "
2911                                        "anymore, channel %d is.\n",
2912                                        __func__,
2913                                        hc->slot_owner[(oslot_rx << 1) | 1]);
2914                 }
2915         }
2916
2917         if (slot_tx < 0) {
2918                 flow_tx = 0x80; /* FIFO->ST */
2919                 /* disable pcm slot */
2920                 hc->chan[ch].slot_tx = -1;
2921                 hc->chan[ch].bank_tx = 0;
2922         } else {
2923                 /* set pcm slot */
2924                 if (hc->chan[ch].txpending)
2925                         flow_tx = 0x80; /* FIFO->ST */
2926                 else
2927                         flow_tx = 0xc0; /* PCM->ST */
2928                 /* put on slot */
2929                 routing = bank_tx ? 0xc0 : 0x80;
2930                 if (conf >= 0 || bank_tx > 1)
2931                         routing = 0x40; /* loop */
2932                 if (debug & DEBUG_HFCMULTI_MODE)
2933                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2934                                " %d flow %02x routing %02x conf %d (TX)\n",
2935                                __func__, ch, slot_tx, bank_tx,
2936                                flow_tx, routing, conf);
2937                 HFC_outb(hc, R_SLOT, slot_tx << 1);
2938                 HFC_outb(hc, A_SL_CFG, (ch << 1) | routing);
2939                 if (hc->ctype != HFC_TYPE_XHFC)
2940                         HFC_outb(hc, A_CONF,
2941                                  (conf < 0) ? 0 : (conf | V_CONF_SL));
2942                 hc->slot_owner[slot_tx << 1] = ch;
2943                 hc->chan[ch].slot_tx = slot_tx;
2944                 hc->chan[ch].bank_tx = bank_tx;
2945         }
2946         if (slot_rx < 0) {
2947                 /* disable pcm slot */
2948                 flow_rx = 0x80; /* ST->FIFO */
2949                 hc->chan[ch].slot_rx = -1;
2950                 hc->chan[ch].bank_rx = 0;
2951         } else {
2952                 /* set pcm slot */
2953                 if (hc->chan[ch].txpending)
2954                         flow_rx = 0x80; /* ST->FIFO */
2955                 else
2956                         flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2957                 /* put on slot */
2958                 routing = bank_rx ? 0x80 : 0xc0; /* reversed */
2959                 if (conf >= 0 || bank_rx > 1)
2960                         routing = 0x40; /* loop */
2961                 if (debug & DEBUG_HFCMULTI_MODE)
2962                         printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2963                                " %d flow %02x routing %02x conf %d (RX)\n",
2964                                __func__, ch, slot_rx, bank_rx,
2965                                flow_rx, routing, conf);
2966                 HFC_outb(hc, R_SLOT, (slot_rx << 1) | V_SL_DIR);
2967                 HFC_outb(hc, A_SL_CFG, (ch << 1) | V_CH_DIR | routing);
2968                 hc->slot_owner[(slot_rx << 1) | 1] = ch;
2969                 hc->chan[ch].slot_rx = slot_rx;
2970                 hc->chan[ch].bank_rx = bank_rx;
2971         }
2972
2973         switch (protocol) {
2974         case (ISDN_P_NONE):
2975                 /* disable TX fifo */
2976                 HFC_outb(hc, R_FIFO, ch << 1);
2977                 HFC_wait(hc);
2978                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2979                 HFC_outb(hc, A_SUBCH_CFG, 0);
2980                 HFC_outb(hc, A_IRQ_MSK, 0);
2981                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2982                 HFC_wait(hc);
2983                 /* disable RX fifo */
2984                 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2985                 HFC_wait(hc);
2986                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2987                 HFC_outb(hc, A_SUBCH_CFG, 0);
2988                 HFC_outb(hc, A_IRQ_MSK, 0);
2989                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2990                 HFC_wait(hc);
2991                 if (hc->chan[ch].bch && hc->ctype != HFC_TYPE_E1) {
2992                         hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2993                                 ((ch & 0x3) == 0) ? ~V_B1_EN : ~V_B2_EN;
2994                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2995                         /* undocumented: delay after R_ST_SEL */
2996                         udelay(1);
2997                         HFC_outb(hc, A_ST_CTRL0,
2998                                  hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2999                 }
3000                 if (hc->chan[ch].bch) {
3001                         test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3002                         test_and_clear_bit(FLG_TRANSPARENT,
3003                                            &hc->chan[ch].bch->Flags);
3004                 }
3005                 break;
3006         case (ISDN_P_B_RAW): /* B-channel */
3007
3008                 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
3009                     (hc->chan[ch].slot_rx < 0) &&
3010                     (hc->chan[ch].slot_tx < 0)) {
3011
3012                         printk(KERN_DEBUG
3013                                "Setting B-channel %d to echo cancelable "
3014                                "state on PCM slot %d\n", ch,
3015                                ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
3016                         printk(KERN_DEBUG
3017                                "Enabling pass through for channel\n");
3018                         vpm_out(hc, ch, ((ch / 4) * 8) +
3019                                 ((ch % 4) * 4) + 1, 0x01);
3020                         /* rx path */
3021                         /* S/T -> PCM */
3022                         HFC_outb(hc, R_FIFO, (ch << 1));
3023                         HFC_wait(hc);
3024                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3025                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3026                                               ((ch % 4) * 4) + 1) << 1);
3027                         HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
3028
3029                         /* PCM -> FIFO */
3030                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
3031                         HFC_wait(hc);
3032                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3033                         HFC_outb(hc, A_SUBCH_CFG, 0);
3034                         HFC_outb(hc, A_IRQ_MSK, 0);
3035                         if (hc->chan[ch].protocol != protocol) {
3036                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3037                                 HFC_wait(hc);
3038                         }
3039                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3040                                                ((ch % 4) * 4) + 1) << 1) | 1);
3041                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
3042
3043                         /* tx path */
3044                         /* PCM -> S/T */
3045                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3046                         HFC_wait(hc);
3047                         HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
3048                         HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
3049                                                ((ch % 4) * 4)) << 1) | 1);
3050                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
3051
3052                         /* FIFO -> PCM */
3053                         HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
3054                         HFC_wait(hc);
3055                         HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
3056                         HFC_outb(hc, A_SUBCH_CFG, 0);
3057                         HFC_outb(hc, A_IRQ_MSK, 0);
3058                         if (hc->chan[ch].protocol != protocol) {
3059                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3060                                 HFC_wait(hc);
3061                         }
3062                         /* tx silence */
3063                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3064                         HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
3065                                               ((ch % 4) * 4)) << 1);
3066                         HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
3067                 } else {
3068                         /* enable TX fifo */
3069                         HFC_outb(hc, R_FIFO, ch << 1);
3070                         HFC_wait(hc);
3071                         if (hc->ctype == HFC_TYPE_XHFC)
3072                                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x07 << 2 |
3073                                          V_HDLC_TRP | V_IFF);
3074                         /* Enable FIFO, no interrupt */
3075                         else
3076                                 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
3077                                          V_HDLC_TRP | V_IFF);
3078                         HFC_outb(hc, A_SUBCH_CFG, 0);
3079                         HFC_outb(hc, A_IRQ_MSK, 0);
3080                         if (hc->chan[ch].protocol != protocol) {
3081                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3082                                 HFC_wait(hc);
3083                         }
3084                         /* tx silence */
3085                         HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
3086                         /* enable RX fifo */
3087                         HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3088                         HFC_wait(hc);
3089                         if (hc->ctype == HFC_TYPE_XHFC)
3090                                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x07 << 2 |
3091                                          V_HDLC_TRP);
3092                         /* Enable FIFO, no interrupt*/
3093                         else
3094                                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 |
3095                                          V_HDLC_TRP);
3096                         HFC_outb(hc, A_SUBCH_CFG, 0);
3097                         HFC_outb(hc, A_IRQ_MSK, 0);
3098                         if (hc->chan[ch].protocol != protocol) {
3099                                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3100                                 HFC_wait(hc);
3101                         }
3102                 }
3103                 if (hc->ctype != HFC_TYPE_E1) {
3104                         hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3105                                 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3106                         HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3107                         /* undocumented: delay after R_ST_SEL */
3108                         udelay(1);
3109                         HFC_outb(hc, A_ST_CTRL0,
3110                                  hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3111                 }
3112                 if (hc->chan[ch].bch)
3113                         test_and_set_bit(FLG_TRANSPARENT,
3114                                          &hc->chan[ch].bch->Flags);
3115                 break;
3116         case (ISDN_P_B_HDLC): /* B-channel */
3117         case (ISDN_P_TE_S0): /* D-channel */
3118         case (ISDN_P_NT_S0):
3119         case (ISDN_P_TE_E1):
3120         case (ISDN_P_NT_E1):
3121                 /* enable TX fifo */
3122                 HFC_outb(hc, R_FIFO, ch << 1);
3123                 HFC_wait(hc);
3124                 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch) {
3125                         /* E1 or B-channel */
3126                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3127                         HFC_outb(hc, A_SUBCH_CFG, 0);
3128                 } else {
3129                         /* D-Channel without HDLC fill flags */
3130                         HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3131                         HFC_outb(hc, A_SUBCH_CFG, 2);
3132                 }
3133                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3134                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3135                 HFC_wait(hc);
3136                 /* enable RX fifo */
3137                 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
3138                 HFC_wait(hc);
3139                 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3140                 if (hc->ctype == HFC_TYPE_E1 || hc->chan[ch].bch)
3141                         HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3142                 else
3143                         HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3144                 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3145                 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3146                 HFC_wait(hc);
3147                 if (hc->chan[ch].bch) {
3148                         test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3149                         if (hc->ctype != HFC_TYPE_E1) {
3150                                 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3151                                         ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
3152                                 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3153                                 /* undocumented: delay after R_ST_SEL */
3154                                 udelay(1);
3155                                 HFC_outb(hc, A_ST_CTRL0,
3156                                          hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3157                         }
3158                 }
3159                 break;
3160         default:
3161                 printk(KERN_DEBUG "%s: protocol not known %x\n",
3162                        __func__, protocol);
3163                 hc->chan[ch].protocol = ISDN_P_NONE;
3164                 return -ENOPROTOOPT;
3165         }
3166         hc->chan[ch].protocol = protocol;
3167         return 0;
3168 }
3169
3170
3171 /*
3172  * connect/disconnect PCM
3173  */
3174
3175 static void
3176 hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3177              int slot_rx, int bank_rx)
3178 {
3179         if (slot_tx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3180                 /* disable PCM */
3181                 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3182                 return;
3183         }
3184
3185         /* enable pcm */
3186         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3187                       slot_rx, bank_rx);
3188 }
3189
3190 /*
3191  * set/disable conference
3192  */
3193
3194 static void
3195 hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3196 {
3197         if (num >= 0 && num <= 7)
3198                 hc->chan[ch].conf = num;
3199         else
3200                 hc->chan[ch].conf = -1;
3201         mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3202                       hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3203                       hc->chan[ch].bank_rx);
3204 }
3205
3206
3207 /*
3208  * set/disable sample loop
3209  */
3210
3211 /* NOTE: this function is experimental and therefore disabled */
3212
3213 /*
3214  * Layer 1 callback function
3215  */
3216 static int
3217 hfcm_l1callback(struct dchannel *dch, u_int cmd)
3218 {
3219         struct hfc_multi        *hc = dch->hw;
3220         struct sk_buff_head     free_queue;
3221         u_long  flags;
3222
3223         switch (cmd) {
3224         case INFO3_P8:
3225         case INFO3_P10:
3226                 break;
3227         case HW_RESET_REQ:
3228                 /* start activation */
3229                 spin_lock_irqsave(&hc->lock, flags);
3230                 if (hc->ctype == HFC_TYPE_E1) {
3231                         if (debug & DEBUG_HFCMULTI_MSG)
3232                                 printk(KERN_DEBUG
3233                                        "%s: HW_RESET_REQ no BRI\n",
3234                                        __func__);
3235                 } else {
3236                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3237                         /* undocumented: delay after R_ST_SEL */
3238                         udelay(1);
3239                         HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3240                         udelay(6); /* wait at least 5,21us */
3241                         HFC_outb(hc, A_ST_WR_STATE, 3);
3242                         HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT * 3));
3243                         /* activate */
3244                 }
3245                 spin_unlock_irqrestore(&hc->lock, flags);
3246                 l1_event(dch->l1, HW_POWERUP_IND);
3247                 break;
3248         case HW_DEACT_REQ:
3249                 __skb_queue_head_init(&free_queue);
3250                 /* start deactivation */
3251                 spin_lock_irqsave(&hc->lock, flags);
3252                 if (hc->ctype == HFC_TYPE_E1) {
3253                         if (debug & DEBUG_HFCMULTI_MSG)
3254                                 printk(KERN_DEBUG
3255                                        "%s: HW_DEACT_REQ no BRI\n",
3256                                        __func__);
3257                 } else {
3258                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3259                         /* undocumented: delay after R_ST_SEL */
3260                         udelay(1);
3261                         HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3262                         /* deactivate */
3263                         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3264                                 hc->syncronized &=
3265                                         ~(1 << hc->chan[dch->slot].port);
3266                                 plxsd_checksync(hc, 0);
3267                         }
3268                 }
3269                 skb_queue_splice_init(&dch->squeue, &free_queue);
3270                 if (dch->tx_skb) {
3271                         __skb_queue_tail(&free_queue, dch->tx_skb);
3272                         dch->tx_skb = NULL;
3273                 }
3274                 dch->tx_idx = 0;
3275                 if (dch->rx_skb) {
3276                         __skb_queue_tail(&free_queue, dch->rx_skb);
3277                         dch->rx_skb = NULL;
3278                 }
3279                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3280                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3281                         del_timer(&dch->timer);
3282                 spin_unlock_irqrestore(&hc->lock, flags);
3283                 __skb_queue_purge(&free_queue);
3284                 break;
3285         case HW_POWERUP_REQ:
3286                 spin_lock_irqsave(&hc->lock, flags);
3287                 if (hc->ctype == HFC_TYPE_E1) {
3288                         if (debug & DEBUG_HFCMULTI_MSG)
3289                                 printk(KERN_DEBUG
3290                                        "%s: HW_POWERUP_REQ no BRI\n",
3291                                        __func__);
3292                 } else {
3293                         HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3294                         /* undocumented: delay after R_ST_SEL */
3295                         udelay(1);
3296                         HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3297                         udelay(6); /* wait at least 5,21us */
3298                         HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3299                 }
3300                 spin_unlock_irqrestore(&hc->lock, flags);
3301                 break;
3302         case PH_ACTIVATE_IND:
3303                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3304                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3305                             GFP_ATOMIC);
3306                 break;
3307         case PH_DEACTIVATE_IND:
3308                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3309                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3310                             GFP_ATOMIC);
3311                 break;
3312         default:
3313                 if (dch->debug & DEBUG_HW)
3314                         printk(KERN_DEBUG "%s: unknown command %x\n",
3315                                __func__, cmd);
3316                 return -1;
3317         }
3318         return 0;
3319 }
3320
3321 /*
3322  * Layer2 -> Layer 1 Transfer
3323  */
3324
3325 static int
3326 handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3327 {
3328         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
3329         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
3330         struct hfc_multi        *hc = dch->hw;
3331         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3332         int                     ret = -EINVAL;
3333         unsigned int            id;
3334         u_long                  flags;
3335
3336         switch (hh->prim) {
3337         case PH_DATA_REQ:
3338                 if (skb->len < 1)
3339                         break;
3340                 spin_lock_irqsave(&hc->lock, flags);
3341                 ret = dchannel_senddata(dch, skb);
3342                 if (ret > 0) { /* direct TX */
3343                         id = hh->id; /* skb can be freed */
3344                         hfcmulti_tx(hc, dch->slot);
3345                         ret = 0;
3346                         /* start fifo */
3347                         HFC_outb(hc, R_FIFO, 0);
3348                         HFC_wait(hc);
3349                         spin_unlock_irqrestore(&hc->lock, flags);
3350                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3351                 } else
3352                         spin_unlock_irqrestore(&hc->lock, flags);
3353                 return ret;
3354         case PH_ACTIVATE_REQ:
3355                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3356                         spin_lock_irqsave(&hc->lock, flags);
3357                         ret = 0;
3358                         if (debug & DEBUG_HFCMULTI_MSG)
3359                                 printk(KERN_DEBUG
3360                                        "%s: PH_ACTIVATE port %d (0..%d)\n",
3361                                        __func__, hc->chan[dch->slot].port,
3362                                        hc->ports - 1);
3363                         /* start activation */
3364                         if (hc->ctype == HFC_TYPE_E1) {
3365                                 ph_state_change(dch);
3366                                 if (debug & DEBUG_HFCMULTI_STATE)
3367                                         printk(KERN_DEBUG
3368                                                "%s: E1 report state %x \n",
3369                                                __func__, dch->state);
3370                         } else {
3371                                 HFC_outb(hc, R_ST_SEL,
3372                                          hc->chan[dch->slot].port);
3373                                 /* undocumented: delay after R_ST_SEL */
3374                                 udelay(1);
3375                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3376                                 /* G1 */
3377                                 udelay(6); /* wait at least 5,21us */
3378                                 HFC_outb(hc, A_ST_WR_STATE, 1);
3379                                 HFC_outb(hc, A_ST_WR_STATE, 1 |
3380                                          (V_ST_ACT * 3)); /* activate */
3381                                 dch->state = 1;
3382                         }
3383                         spin_unlock_irqrestore(&hc->lock, flags);
3384                 } else
3385                         ret = l1_event(dch->l1, hh->prim);
3386                 break;
3387         case PH_DEACTIVATE_REQ:
3388                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3389                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3390                         struct sk_buff_head free_queue;
3391
3392                         __skb_queue_head_init(&free_queue);
3393                         spin_lock_irqsave(&hc->lock, flags);
3394                         if (debug & DEBUG_HFCMULTI_MSG)
3395                                 printk(KERN_DEBUG
3396                                        "%s: PH_DEACTIVATE port %d (0..%d)\n",
3397                                        __func__, hc->chan[dch->slot].port,
3398                                        hc->ports - 1);
3399                         /* start deactivation */
3400                         if (hc->ctype == HFC_TYPE_E1) {
3401                                 if (debug & DEBUG_HFCMULTI_MSG)
3402                                         printk(KERN_DEBUG
3403                                                "%s: PH_DEACTIVATE no BRI\n",
3404                                                __func__);
3405                         } else {
3406                                 HFC_outb(hc, R_ST_SEL,
3407                                          hc->chan[dch->slot].port);
3408                                 /* undocumented: delay after R_ST_SEL */
3409                                 udelay(1);
3410                                 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3411                                 /* deactivate */
3412                                 dch->state = 1;
3413                         }
3414                         skb_queue_splice_init(&dch->squeue, &free_queue);
3415                         if (dch->tx_skb) {
3416                                 __skb_queue_tail(&free_queue, dch->tx_skb);
3417                                 dch->tx_skb = NULL;
3418                         }
3419                         dch->tx_idx = 0;
3420                         if (dch->rx_skb) {
3421                                 __skb_queue_tail(&free_queue, dch->rx_skb);
3422                                 dch->rx_skb = NULL;
3423                         }
3424                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3425                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3426                                 del_timer(&dch->timer);
3427 #ifdef FIXME
3428                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3429                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3430 #endif
3431                         ret = 0;
3432                         spin_unlock_irqrestore(&hc->lock, flags);
3433                         __skb_queue_purge(&free_queue);
3434                 } else
3435                         ret = l1_event(dch->l1, hh->prim);
3436                 break;
3437         }
3438         if (!ret)
3439                 dev_kfree_skb(skb);
3440         return ret;
3441 }
3442
3443 static void
3444 deactivate_bchannel(struct bchannel *bch)
3445 {
3446         struct hfc_multi        *hc = bch->hw;
3447         u_long                  flags;
3448
3449         spin_lock_irqsave(&hc->lock, flags);
3450         mISDN_clear_bchannel(bch);
3451         hc->chan[bch->slot].coeff_count = 0;
3452         hc->chan[bch->slot].rx_off = 0;
3453         hc->chan[bch->slot].conf = -1;
3454         mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3455         spin_unlock_irqrestore(&hc->lock, flags);
3456 }
3457
3458 static int
3459 handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3460 {
3461         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3462         struct hfc_multi        *hc = bch->hw;
3463         int                     ret = -EINVAL;
3464         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
3465         unsigned long           flags;
3466
3467         switch (hh->prim) {
3468         case PH_DATA_REQ:
3469                 if (!skb->len)
3470                         break;
3471                 spin_lock_irqsave(&hc->lock, flags);
3472                 ret = bchannel_senddata(bch, skb);
3473                 if (ret > 0) { /* direct TX */
3474                         hfcmulti_tx(hc, bch->slot);
3475                         ret = 0;
3476                         /* start fifo */
3477                         HFC_outb_nodebug(hc, R_FIFO, 0);
3478                         HFC_wait_nodebug(hc);
3479                 }
3480                 spin_unlock_irqrestore(&hc->lock, flags);
3481                 return ret;
3482         case PH_ACTIVATE_REQ:
3483                 if (debug & DEBUG_HFCMULTI_MSG)
3484                         printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3485                                __func__, bch->slot);
3486                 spin_lock_irqsave(&hc->lock, flags);
3487                 /* activate B-channel if not already activated */
3488                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3489                         hc->chan[bch->slot].txpending = 0;
3490                         ret = mode_hfcmulti(hc, bch->slot,
3491                                             ch->protocol,
3492                                             hc->chan[bch->slot].slot_tx,
3493                                             hc->chan[bch->slot].bank_tx,
3494                                             hc->chan[bch->slot].slot_rx,
3495                                             hc->chan[bch->slot].bank_rx);
3496                         if (!ret) {
3497                                 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3498                                     && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3499                                         /* start decoder */
3500                                         hc->dtmf = 1;
3501                                         if (debug & DEBUG_HFCMULTI_DTMF)
3502                                                 printk(KERN_DEBUG
3503                                                        "%s: start dtmf decoder\n",
3504                                                        __func__);
3505                                         HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3506                                                  V_RST_DTMF);
3507                                 }
3508                         }
3509                 } else
3510                         ret = 0;
3511                 spin_unlock_irqrestore(&hc->lock, flags);
3512                 if (!ret)
3513                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3514                                     GFP_KERNEL);
3515                 break;
3516         case PH_CONTROL_REQ:
3517                 spin_lock_irqsave(&hc->lock, flags);
3518                 switch (hh->id) {
3519                 case HFC_SPL_LOOP_ON: /* set sample loop */
3520                         if (debug & DEBUG_HFCMULTI_MSG)
3521                                 printk(KERN_DEBUG
3522                                        "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3523                                        __func__, skb->len);
3524                         ret = 0;
3525                         break;
3526                 case HFC_SPL_LOOP_OFF: /* set silence */
3527                         if (debug & DEBUG_HFCMULTI_MSG)
3528                                 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3529                                        __func__);
3530                         ret = 0;
3531                         break;
3532                 default:
3533                         printk(KERN_ERR
3534                                "%s: unknown PH_CONTROL_REQ info %x\n",
3535                                __func__, hh->id);
3536                         ret = -EINVAL;
3537                 }
3538                 spin_unlock_irqrestore(&hc->lock, flags);
3539                 break;
3540         case PH_DEACTIVATE_REQ:
3541                 deactivate_bchannel(bch); /* locked there */
3542                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3543                             GFP_KERNEL);
3544                 ret = 0;
3545                 break;
3546         }
3547         if (!ret)
3548                 dev_kfree_skb(skb);
3549         return ret;
3550 }
3551
3552 /*
3553  * bchannel control function
3554  */
3555 static int
3556 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3557 {
3558         int                     ret = 0;
3559         struct dsp_features     *features =
3560                 (struct dsp_features *)(*((u_long *)&cq->p1));
3561         struct hfc_multi        *hc = bch->hw;
3562         int                     slot_tx;
3563         int                     bank_tx;
3564         int                     slot_rx;
3565         int                     bank_rx;
3566         int                     num;
3567
3568         switch (cq->op) {
3569         case MISDN_CTRL_GETOP:
3570                 ret = mISDN_ctrl_bchannel(bch, cq);
3571                 cq->op |= MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP;
3572                 break;
3573         case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3574                 ret = mISDN_ctrl_bchannel(bch, cq);
3575                 hc->chan[bch->slot].rx_off = !!cq->p1;
3576                 if (!hc->chan[bch->slot].rx_off) {
3577                         /* reset fifo on rx on */
3578                         HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3579                         HFC_wait_nodebug(hc);
3580                         HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3581                         HFC_wait_nodebug(hc);
3582                 }
3583                 if (debug & DEBUG_HFCMULTI_MSG)
3584                         printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3585                                __func__, bch->nr, hc->chan[bch->slot].rx_off);
3586                 break;
3587         case MISDN_CTRL_FILL_EMPTY:
3588                 ret = mISDN_ctrl_bchannel(bch, cq);
3589                 hc->silence = bch->fill[0];
3590                 memset(hc->silence_data, hc->silence, sizeof(hc->silence_data));
3591                 break;
3592         case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3593                 if (debug & DEBUG_HFCMULTI_MSG)
3594                         printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3595                                __func__);
3596                 /* create confirm */
3597                 features->hfc_id = hc->id;
3598                 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3599                         features->hfc_dtmf = 1;
3600                 if (test_bit(HFC_CHIP_CONF, &hc->chip))
3601                         features->hfc_conf = 1;
3602                 features->hfc_loops = 0;
3603                 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3604                         features->hfc_echocanhw = 1;
3605                 } else {
3606                         features->pcm_id = hc->pcm;
3607                         features->pcm_slots = hc->slots;
3608                         features->pcm_banks = 2;
3609                 }
3610                 break;
3611         case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3612                 slot_tx = cq->p1 & 0xff;
3613                 bank_tx = cq->p1 >> 8;
3614                 slot_rx = cq->p2 & 0xff;
3615                 bank_rx = cq->p2 >> 8;
3616                 if (debug & DEBUG_HFCMULTI_MSG)
3617                         printk(KERN_DEBUG
3618                                "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3619                                "slot %d bank %d (RX)\n",
3620                                __func__, slot_tx, bank_tx,
3621                                slot_rx, bank_rx);
3622                 if (slot_tx < hc->slots && bank_tx <= 2 &&
3623                     slot_rx < hc->slots && bank_rx <= 2)
3624                         hfcmulti_pcm(hc, bch->slot,
3625                                      slot_tx, bank_tx, slot_rx, bank_rx);
3626                 else {
3627                         printk(KERN_WARNING
3628                                "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3629                                "slot %d bank %d (RX) out of range\n",
3630                                __func__, slot_tx, bank_tx,
3631                                slot_rx, bank_rx);
3632                         ret = -EINVAL;
3633                 }
3634                 break;
3635         case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3636                 if (debug & DEBUG_HFCMULTI_MSG)
3637                         printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3638                                __func__);
3639                 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3640                 break;
3641         case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3642                 num = cq->p1 & 0xff;
3643                 if (debug & DEBUG_HFCMULTI_MSG)
3644                         printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3645                                __func__, num);
3646                 if (num <= 7)
3647                         hfcmulti_conf(hc, bch->slot, num);
3648                 else {
3649                         printk(KERN_WARNING
3650                                "%s: HW_CONF_JOIN conf %d out of range\n",
3651                                __func__, num);
3652                         ret = -EINVAL;
3653                 }
3654                 break;
3655         case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3656                 if (debug & DEBUG_HFCMULTI_MSG)
3657                         printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3658                 hfcmulti_conf(hc, bch->slot, -1);
3659                 break;
3660         case MISDN_CTRL_HFC_ECHOCAN_ON:
3661                 if (debug & DEBUG_HFCMULTI_MSG)
3662                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3663                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3664                         vpm_echocan_on(hc, bch->slot, cq->p1);
3665                 else
3666                         ret = -EINVAL;
3667                 break;
3668
3669         case MISDN_CTRL_HFC_ECHOCAN_OFF:
3670                 if (debug & DEBUG_HFCMULTI_MSG)
3671                         printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3672                                __func__);
3673                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3674                         vpm_echocan_off(hc, bch->slot);
3675                 else
3676                         ret = -EINVAL;
3677                 break;
3678         default:
3679                 ret = mISDN_ctrl_bchannel(bch, cq);
3680                 break;
3681         }
3682         return ret;
3683 }
3684
3685 static int
3686 hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3687 {
3688         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
3689         struct hfc_multi        *hc = bch->hw;
3690         int                     err = -EINVAL;
3691         u_long  flags;
3692
3693         if (bch->debug & DEBUG_HW)
3694                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3695                        __func__, cmd, arg);
3696         switch (cmd) {
3697         case CLOSE_CHANNEL:
3698                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3699                 deactivate_bchannel(bch); /* locked there */
3700                 ch->protocol = ISDN_P_NONE;
3701                 ch->peer = NULL;
3702                 module_put(THIS_MODULE);
3703                 err = 0;
3704                 break;
3705         case CONTROL_CHANNEL:
3706                 spin_lock_irqsave(&hc->lock, flags);
3707                 err = channel_bctrl(bch, arg);
3708                 spin_unlock_irqrestore(&hc->lock, flags);
3709                 break;
3710         default:
3711                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3712                        __func__, cmd);
3713         }
3714         return err;
3715 }
3716
3717 /*
3718  * handle D-channel events
3719  *
3720  * handle state change event
3721  */
3722 static void
3723 ph_state_change(struct dchannel *dch)
3724 {
3725         struct hfc_multi *hc;
3726         int ch, i;
3727
3728         if (!dch) {
3729                 printk(KERN_WARNING "%s: ERROR given dch is NULL\n", __func__);
3730                 return;
3731         }
3732         hc = dch->hw;
3733         ch = dch->slot;
3734
3735         if (hc->ctype == HFC_TYPE_E1) {
3736                 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3737                         if (debug & DEBUG_HFCMULTI_STATE)
3738                                 printk(KERN_DEBUG
3739                                        "%s: E1 TE (id=%d) newstate %x\n",
3740                                        __func__, hc->id, dch->state);
3741                 } else {
3742                         if (debug & DEBUG_HFCMULTI_STATE)
3743                                 printk(KERN_DEBUG
3744                                        "%s: E1 NT (id=%d) newstate %x\n",
3745                                        __func__, hc->id, dch->state);
3746                 }
3747                 switch (dch->state) {
3748                 case (1):
3749                         if (hc->e1_state != 1) {
3750                                 for (i = 1; i <= 31; i++) {
3751                                         /* reset fifos on e1 activation */
3752                                         HFC_outb_nodebug(hc, R_FIFO,
3753                                                          (i << 1) | 1);
3754                                         HFC_wait_nodebug(hc);
3755                                         HFC_outb_nodebug(hc, R_INC_RES_FIFO,
3756                                                          V_RES_F);
3757                                         HFC_wait_nodebug(hc);
3758                                 }
3759                         }
3760                         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3761                         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3762                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3763                         break;
3764
3765                 default:
3766                         if (hc->e1_state != 1)
3767                                 return;
3768                         test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3769                         _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3770                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3771                 }
3772                 hc->e1_state = dch->state;
3773         } else {
3774                 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3775                         if (debug & DEBUG_HFCMULTI_STATE)
3776                                 printk(KERN_DEBUG
3777                                        "%s: S/T TE newstate %x\n",
3778                                        __func__, dch->state);
3779                         switch (dch->state) {
3780                         case (0):
3781                                 l1_event(dch->l1, HW_RESET_IND);
3782                                 break;
3783                         case (3):
3784                                 l1_event(dch->l1, HW_DEACT_IND);
3785                                 break;
3786                         case (5):
3787                         case (8):
3788                                 l1_event(dch->l1, ANYSIGNAL);
3789                                 break;
3790                         case (6):
3791                                 l1_event(dch->l1, INFO2);
3792                                 break;
3793                         case (7):
3794                                 l1_event(dch->l1, INFO4_P8);
3795                                 break;
3796                         }
3797                 } else {
3798                         if (debug & DEBUG_HFCMULTI_STATE)
3799                                 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3800                                        __func__, dch->state);
3801                         switch (dch->state) {
3802                         case (2):
3803                                 if (hc->chan[ch].nt_timer == 0) {
3804                                         hc->chan[ch].nt_timer = -1;
3805                                         HFC_outb(hc, R_ST_SEL,
3806                                                  hc->chan[ch].port);
3807                                         /* undocumented: delay after R_ST_SEL */
3808                                         udelay(1);
3809                                         HFC_outb(hc, A_ST_WR_STATE, 4 |
3810                                                  V_ST_LD_STA); /* G4 */
3811                                         udelay(6); /* wait at least 5,21us */
3812                                         HFC_outb(hc, A_ST_WR_STATE, 4);
3813                                         dch->state = 4;
3814                                 } else {
3815                                         /* one extra count for the next event */
3816                                         hc->chan[ch].nt_timer =
3817                                                 nt_t1_count[poll_timer] + 1;
3818                                         HFC_outb(hc, R_ST_SEL,
3819                                                  hc->chan[ch].port);
3820                                         /* undocumented: delay after R_ST_SEL */
3821                                         udelay(1);
3822                                         /* allow G2 -> G3 transition */
3823                                         HFC_outb(hc, A_ST_WR_STATE, 2 |
3824                                                  V_SET_G2_G3);
3825                                 }
3826                                 break;
3827                         case (1):
3828                                 hc->chan[ch].nt_timer = -1;
3829                                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3830                                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3831                                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3832                                 break;
3833                         case (4):
3834                                 hc->chan[ch].nt_timer = -1;
3835                                 break;
3836                         case (3):
3837                                 hc->chan[ch].nt_timer = -1;
3838                                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3839                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3840                                             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3841                                 break;
3842                         }
3843                 }
3844         }
3845 }
3846
3847 /*
3848  * called for card mode init message
3849  */
3850
3851 static void
3852 hfcmulti_initmode(struct dchannel *dch)
3853 {
3854         struct hfc_multi *hc = dch->hw;
3855         u_char          a_st_wr_state, r_e1_wr_sta;
3856         int             i, pt;
3857
3858         if (debug & DEBUG_HFCMULTI_INIT)
3859                 printk(KERN_DEBUG "%s: entered\n", __func__);
3860
3861         i = dch->slot;
3862         pt = hc->chan[i].port;
3863         if (hc->ctype == HFC_TYPE_E1) {
3864                 /* E1 */
3865                 hc->chan[hc->dnum[pt]].slot_tx = -1;
3866                 hc->chan[hc->dnum[pt]].slot_rx = -1;
3867                 hc->chan[hc->dnum[pt]].conf = -1;
3868                 if (hc->dnum[pt]) {
3869                         mode_hfcmulti(hc, dch->slot, dch->dev.D.protocol,
3870                                       -1, 0, -1, 0);
3871                         timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
3872                 }
3873                 for (i = 1; i <= 31; i++) {
3874                         if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
3875                                 continue;
3876                         hc->chan[i].slot_tx = -1;
3877                         hc->chan[i].slot_rx = -1;
3878                         hc->chan[i].conf = -1;
3879                         mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3880                 }
3881         }
3882         if (hc->ctype == HFC_TYPE_E1 && pt == 0) {
3883                 /* E1, port 0 */
3884                 dch = hc->chan[hc->dnum[0]].dch;
3885                 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dnum[0]].cfg)) {
3886                         HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3887                         HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3888                 }
3889                 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dnum[0]].cfg)) {
3890                         HFC_outb(hc, R_RX0, 0);
3891                         hc->hw.r_tx0 = 0 | V_OUT_EN;
3892                 } else {
3893                         HFC_outb(hc, R_RX0, 1);
3894                         hc->hw.r_tx0 = 1 | V_OUT_EN;
3895                 }
3896                 hc->hw.r_tx1 = V_ATX | V_NTRI;
3897                 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3898                 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3899                 HFC_outb(hc, R_TX_FR0, 0x00);
3900                 HFC_outb(hc, R_TX_FR1, 0xf8);
3901
3902                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3903                         HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3904
3905                 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3906
3907                 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
3908                         HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3909
3910                 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3911                         if (debug & DEBUG_HFCMULTI_INIT)
3912                                 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3913                                        __func__);
3914                         r_e1_wr_sta = 0; /* G0 */
3915                         hc->e1_getclock = 0;
3916                 } else {
3917                         if (debug & DEBUG_HFCMULTI_INIT)
3918                                 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3919                                        __func__);
3920                         r_e1_wr_sta = 0; /* F0 */
3921                         hc->e1_getclock = 1;
3922                 }
3923                 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3924                         HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3925                 else
3926                         HFC_outb(hc, R_SYNC_OUT, 0);
3927                 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3928                         hc->e1_getclock = 1;
3929                 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3930                         hc->e1_getclock = 0;
3931                 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3932                         /* SLAVE (clock master) */
3933                         if (debug & DEBUG_HFCMULTI_INIT)
3934                                 printk(KERN_DEBUG
3935                                        "%s: E1 port is clock master "
3936                                        "(clock from PCM)\n", __func__);
3937                         HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3938                 } else {
3939                         if (hc->e1_getclock) {
3940                                 /* MASTER (clock slave) */
3941                                 if (debug & DEBUG_HFCMULTI_INIT)
3942                                         printk(KERN_DEBUG
3943                                                "%s: E1 port is clock slave "
3944                                                "(clock to PCM)\n", __func__);
3945                                 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3946                         } else {
3947                                 /* MASTER (clock master) */
3948                                 if (debug & DEBUG_HFCMULTI_INIT)
3949                                         printk(KERN_DEBUG "%s: E1 port is "
3950                                                "clock master "
3951                                                "(clock from QUARTZ)\n",
3952                                                __func__);
3953                                 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3954                                          V_PCM_SYNC | V_JATT_OFF);
3955                                 HFC_outb(hc, R_SYNC_OUT, 0);
3956                         }
3957                 }
3958                 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3959                 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3960                 HFC_outb(hc, R_PWM0, 0x50);
3961                 HFC_outb(hc, R_PWM1, 0xff);
3962                 /* state machine setup */
3963                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3964                 udelay(6); /* wait at least 5,21us */
3965                 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3966                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3967                         hc->syncronized = 0;
3968                         plxsd_checksync(hc, 0);
3969                 }
3970         }
3971         if (hc->ctype != HFC_TYPE_E1) {
3972                 /* ST */
3973                 hc->chan[i].slot_tx = -1;
3974                 hc->chan[i].slot_rx = -1;
3975                 hc->chan[i].conf = -1;
3976                 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3977                 timer_setup(&dch->timer, hfcmulti_dbusy_timer, 0);
3978                 hc->chan[i - 2].slot_tx = -1;
3979                 hc->chan[i - 2].slot_rx = -1;
3980                 hc->chan[i - 2].conf = -1;
3981                 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3982                 hc->chan[i - 1].slot_tx = -1;
3983                 hc->chan[i - 1].slot_rx = -1;
3984                 hc->chan[i - 1].conf = -1;
3985                 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3986                 /* select interface */
3987                 HFC_outb(hc, R_ST_SEL, pt);
3988                 /* undocumented: delay after R_ST_SEL */
3989                 udelay(1);
3990                 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3991                         if (debug & DEBUG_HFCMULTI_INIT)
3992                                 printk(KERN_DEBUG
3993                                        "%s: ST port %d is NT-mode\n",
3994                                        __func__, pt);
3995                         /* clock delay */
3996                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3997                         a_st_wr_state = 1; /* G1 */
3998                         hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3999                 } else {
4000                         if (debug & DEBUG_HFCMULTI_INIT)
4001                                 printk(KERN_DEBUG
4002                                        "%s: ST port %d is TE-mode\n",
4003                                        __func__, pt);
4004                         /* clock delay */
4005                         HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
4006                         a_st_wr_state = 2; /* F2 */
4007                         hc->hw.a_st_ctrl0[pt] = 0;
4008                 }
4009                 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
4010                         hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
4011                 if (hc->ctype == HFC_TYPE_XHFC) {
4012                         hc->hw.a_st_ctrl0[pt] |= 0x40 /* V_ST_PU_CTRL */;
4013                         HFC_outb(hc, 0x35 /* A_ST_CTRL3 */,
4014                                  0x7c << 1 /* V_ST_PULSE */);
4015                 }
4016                 /* line setup */
4017                 HFC_outb(hc, A_ST_CTRL0,  hc->hw.a_st_ctrl0[pt]);
4018                 /* disable E-channel */
4019                 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
4020                     test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
4021                         HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
4022                 else
4023                         HFC_outb(hc, A_ST_CTRL1, 0);
4024                 /* enable B-channel receive */
4025                 HFC_outb(hc, A_ST_CTRL2,  V_B1_RX_EN | V_B2_RX_EN);
4026                 /* state machine setup */
4027                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
4028                 udelay(6); /* wait at least 5,21us */
4029                 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
4030                 hc->hw.r_sci_msk |= 1 << pt;
4031                 /* state machine interrupts */
4032                 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
4033                 /* unset sync on port */
4034                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4035                         hc->syncronized &=
4036                                 ~(1 << hc->chan[dch->slot].port);
4037                         plxsd_checksync(hc, 0);
4038                 }
4039         }
4040         if (debug & DEBUG_HFCMULTI_INIT)
4041                 printk("%s: done\n", __func__);
4042 }
4043
4044
4045 static int
4046 open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
4047               struct channel_req *rq)
4048 {
4049         int     err = 0;
4050         u_long  flags;
4051
4052         if (debug & DEBUG_HW_OPEN)
4053                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
4054                        dch->dev.id, __builtin_return_address(0));
4055         if (rq->protocol == ISDN_P_NONE)
4056                 return -EINVAL;
4057         if ((dch->dev.D.protocol != ISDN_P_NONE) &&
4058             (dch->dev.D.protocol != rq->protocol)) {
4059                 if (debug & DEBUG_HFCMULTI_MODE)
4060                         printk(KERN_DEBUG "%s: change protocol %x to %x\n",
4061                                __func__, dch->dev.D.protocol, rq->protocol);
4062         }
4063         if ((dch->dev.D.protocol == ISDN_P_TE_S0) &&
4064             (rq->protocol != ISDN_P_TE_S0))
4065                 l1_event(dch->l1, CLOSE_CHANNEL);
4066         if (dch->dev.D.protocol != rq->protocol) {
4067                 if (rq->protocol == ISDN_P_TE_S0) {
4068                         err = create_l1(dch, hfcm_l1callback);
4069                         if (err)
4070                                 return err;
4071                 }
4072                 dch->dev.D.protocol = rq->protocol;
4073                 spin_lock_irqsave(&hc->lock, flags);
4074                 hfcmulti_initmode(dch);
4075                 spin_unlock_irqrestore(&hc->lock, flags);
4076         }
4077         if (test_bit(FLG_ACTIVE, &dch->Flags))
4078                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
4079                             0, NULL, GFP_KERNEL);
4080         rq->ch = &dch->dev.D;
4081         if (!try_module_get(THIS_MODULE))
4082                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4083         return 0;
4084 }
4085
4086 static int
4087 open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
4088               struct channel_req *rq)
4089 {
4090         struct bchannel *bch;
4091         int             ch;
4092
4093         if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
4094                 return -EINVAL;
4095         if (rq->protocol == ISDN_P_NONE)
4096                 return -EINVAL;
4097         if (hc->ctype == HFC_TYPE_E1)
4098                 ch = rq->adr.channel;
4099         else
4100                 ch = (rq->adr.channel - 1) + (dch->slot - 2);
4101         bch = hc->chan[ch].bch;
4102         if (!bch) {
4103                 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
4104                        __func__, ch);
4105                 return -EINVAL;
4106         }
4107         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4108                 return -EBUSY; /* b-channel can be only open once */
4109         bch->ch.protocol = rq->protocol;
4110         hc->chan[ch].rx_off = 0;
4111         rq->ch = &bch->ch;
4112         if (!try_module_get(THIS_MODULE))
4113                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4114         return 0;
4115 }
4116
4117 /*
4118  * device control function
4119  */
4120 static int
4121 channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4122 {
4123         struct hfc_multi        *hc = dch->hw;
4124         int     ret = 0;
4125         int     wd_mode, wd_cnt;
4126
4127         switch (cq->op) {
4128         case MISDN_CTRL_GETOP:
4129                 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_L1_TIMER3;
4130                 break;
4131         case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4132                 wd_cnt = cq->p1 & 0xf;
4133                 wd_mode = !!(cq->p1 >> 4);
4134                 if (debug & DEBUG_HFCMULTI_MSG)
4135                         printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_INIT mode %s"
4136                                ", counter 0x%x\n", __func__,
4137                                wd_mode ? "AUTO" : "MANUAL", wd_cnt);
4138                 /* set the watchdog timer */
4139                 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4140                 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4141                 if (hc->ctype == HFC_TYPE_XHFC)
4142                         hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4143                 /* init the watchdog register and reset the counter */
4144                 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4145                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4146                         /* enable the watchdog output for Speech-Design */
4147                         HFC_outb(hc, R_GPIO_SEL,  V_GPIO_SEL7);
4148                         HFC_outb(hc, R_GPIO_EN1,  V_GPIO_EN15);
4149                         HFC_outb(hc, R_GPIO_OUT1, 0);
4150                         HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4151                 }
4152                 break;
4153         case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4154                 if (debug & DEBUG_HFCMULTI_MSG)
4155                         printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
4156                                __func__);
4157                 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4158                 break;
4159         case MISDN_CTRL_L1_TIMER3:
4160                 ret = l1_event(dch->l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
4161                 break;
4162         default:
4163                 printk(KERN_WARNING "%s: unknown Op %x\n",
4164                        __func__, cq->op);
4165                 ret = -EINVAL;
4166                 break;
4167         }
4168         return ret;
4169 }
4170
4171 static int
4172 hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4173 {
4174         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
4175         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
4176         struct hfc_multi        *hc = dch->hw;
4177         struct channel_req      *rq;
4178         int                     err = 0;
4179         u_long                  flags;
4180
4181         if (dch->debug & DEBUG_HW)
4182                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4183                        __func__, cmd, arg);
4184         switch (cmd) {
4185         case OPEN_CHANNEL:
4186                 rq = arg;
4187                 switch (rq->protocol) {
4188                 case ISDN_P_TE_S0:
4189                 case ISDN_P_NT_S0:
4190                         if (hc->ctype == HFC_TYPE_E1) {
4191                                 err = -EINVAL;
4192                                 break;
4193                         }
4194                         err = open_dchannel(hc, dch, rq); /* locked there */
4195                         break;
4196                 case ISDN_P_TE_E1:
4197                 case ISDN_P_NT_E1:
4198                         if (hc->ctype != HFC_TYPE_E1) {
4199                                 err = -EINVAL;
4200                                 break;
4201                         }
4202                         err = open_dchannel(hc, dch, rq); /* locked there */
4203                         break;
4204                 default:
4205                         spin_lock_irqsave(&hc->lock, flags);
4206                         err = open_bchannel(hc, dch, rq);
4207                         spin_unlock_irqrestore(&hc->lock, flags);
4208                 }
4209                 break;
4210         case CLOSE_CHANNEL:
4211                 if (debug & DEBUG_HW_OPEN)
4212                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4213                                __func__, dch->dev.id,
4214                                __builtin_return_address(0));
4215                 module_put(THIS_MODULE);
4216                 break;
4217         case CONTROL_CHANNEL:
4218                 spin_lock_irqsave(&hc->lock, flags);
4219                 err = channel_dctrl(dch, arg);
4220                 spin_unlock_irqrestore(&hc->lock, flags);
4221                 break;
4222         default:
4223                 if (dch->debug & DEBUG_HW)
4224                         printk(KERN_DEBUG "%s: unknown command %x\n",
4225                                __func__, cmd);
4226                 err = -EINVAL;
4227         }
4228         return err;
4229 }
4230
4231 static int
4232 clockctl(void *priv, int enable)
4233 {
4234         struct hfc_multi *hc = priv;
4235
4236         hc->iclock_on = enable;
4237         return 0;
4238 }
4239
4240 /*
4241  * initialize the card
4242  */
4243
4244 /*
4245  * start timer irq, wait some time and check if we have interrupts.
4246  * if not, reset chip and try again.
4247  */
4248 static int
4249 init_card(struct hfc_multi *hc)
4250 {
4251         int     err = -EIO;
4252         u_long  flags;
4253         void    __iomem *plx_acc;
4254         u_long  plx_flags;
4255
4256         if (debug & DEBUG_HFCMULTI_INIT)
4257                 printk(KERN_DEBUG "%s: entered\n", __func__);
4258
4259         spin_lock_irqsave(&hc->lock, flags);
4260         /* set interrupts but leave global interrupt disabled */
4261         hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4262         disable_hwirq(hc);
4263         spin_unlock_irqrestore(&hc->lock, flags);
4264
4265         if (request_irq(hc->irq, hfcmulti_interrupt, IRQF_SHARED,
4266                         "HFC-multi", hc)) {
4267                 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4268                        hc->irq);
4269                 hc->irq = 0;
4270                 return -EIO;
4271         }
4272
4273         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4274                 spin_lock_irqsave(&plx_lock, plx_flags);
4275                 plx_acc = hc->plx_membase + PLX_INTCSR;
4276                 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4277                        plx_acc); /* enable PCI & LINT1 irq */
4278                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4279         }
4280
4281         if (debug & DEBUG_HFCMULTI_INIT)
4282                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4283                        __func__, hc->irq, hc->irqcnt);
4284         err = init_chip(hc);
4285         if (err)
4286                 goto error;
4287         /*
4288          * Finally enable IRQ output
4289          * this is only allowed, if an IRQ routine is already
4290          * established for this HFC, so don't do that earlier
4291          */
4292         spin_lock_irqsave(&hc->lock, flags);
4293         enable_hwirq(hc);
4294         spin_unlock_irqrestore(&hc->lock, flags);
4295         /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4296         set_current_state(TASK_UNINTERRUPTIBLE);
4297         schedule_timeout((100 * HZ) / 1000); /* Timeout 100ms */
4298         /* turn IRQ off until chip is completely initialized */
4299         spin_lock_irqsave(&hc->lock, flags);
4300         disable_hwirq(hc);
4301         spin_unlock_irqrestore(&hc->lock, flags);
4302         if (debug & DEBUG_HFCMULTI_INIT)
4303                 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4304                        __func__, hc->irq, hc->irqcnt);
4305         if (hc->irqcnt) {
4306                 if (debug & DEBUG_HFCMULTI_INIT)
4307                         printk(KERN_DEBUG "%s: done\n", __func__);
4308
4309                 return 0;
4310         }
4311         if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4312                 printk(KERN_INFO "ignoring missing interrupts\n");
4313                 return 0;
4314         }
4315
4316         printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4317                hc->irq);
4318
4319         err = -EIO;
4320
4321 error:
4322         if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4323                 spin_lock_irqsave(&plx_lock, plx_flags);
4324                 plx_acc = hc->plx_membase + PLX_INTCSR;
4325                 writew(0x00, plx_acc); /*disable IRQs*/
4326                 spin_unlock_irqrestore(&plx_lock, plx_flags);
4327         }
4328
4329         if (debug & DEBUG_HFCMULTI_INIT)
4330                 printk(KERN_DEBUG "%s: free irq %d\n", __func__, hc->irq);
4331         if (hc->irq) {
4332                 free_irq(hc->irq, hc);
4333                 hc->irq = 0;
4334         }
4335
4336         if (debug & DEBUG_HFCMULTI_INIT)
4337                 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4338         return err;
4339 }
4340
4341 /*
4342  * find pci device and set it up
4343  */
4344
4345 static int
4346 setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4347           const struct pci_device_id *ent)
4348 {
4349         struct hm_map   *m = (struct hm_map *)ent->driver_data;
4350
4351         printk(KERN_INFO
4352                "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4353                m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4354
4355         hc->pci_dev = pdev;
4356         if (m->clock2)
4357                 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4358
4359         if (ent->vendor == PCI_VENDOR_ID_DIGIUM &&
4360             ent->device == PCI_DEVICE_ID_DIGIUM_HFC4S) {
4361                 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4362                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4363                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4364                 hc->slots = 32;
4365         }
4366
4367         if (hc->pci_dev->irq <= 0) {
4368                 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4369                 return -EIO;
4370         }
4371         if (pci_enable_device(hc->pci_dev)) {
4372                 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4373                 return -EIO;
4374         }
4375         hc->leds = m->leds;
4376         hc->ledstate = 0xAFFEAFFE;
4377         hc->opticalsupport = m->opticalsupport;
4378
4379         hc->pci_iobase = 0;
4380         hc->pci_membase = NULL;
4381         hc->plx_membase = NULL;
4382
4383         /* set memory access methods */
4384         if (m->io_mode) /* use mode from card config */
4385                 hc->io_mode = m->io_mode;
4386         switch (hc->io_mode) {
4387         case HFC_IO_MODE_PLXSD:
4388                 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4389                 hc->slots = 128; /* required */
4390                 hc->HFC_outb = HFC_outb_pcimem;
4391                 hc->HFC_inb = HFC_inb_pcimem;
4392                 hc->HFC_inw = HFC_inw_pcimem;
4393                 hc->HFC_wait = HFC_wait_pcimem;
4394                 hc->read_fifo = read_fifo_pcimem;
4395                 hc->write_fifo = write_fifo_pcimem;
4396                 hc->plx_origmembase =  hc->pci_dev->resource[0].start;
4397                 /* MEMBASE 1 is PLX PCI Bridge */
4398
4399                 if (!hc->plx_origmembase) {
4400                         printk(KERN_WARNING
4401                                "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4402                         pci_disable_device(hc->pci_dev);
4403                         return -EIO;
4404                 }
4405
4406                 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4407                 if (!hc->plx_membase) {
4408                         printk(KERN_WARNING
4409                                "HFC-multi: failed to remap plx address space. "
4410                                "(internal error)\n");
4411                         pci_disable_device(hc->pci_dev);
4412                         return -EIO;
4413                 }
4414                 printk(KERN_INFO
4415                        "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4416                        (u_long)hc->plx_membase, hc->plx_origmembase);
4417
4418                 hc->pci_origmembase =  hc->pci_dev->resource[2].start;
4419                 /* MEMBASE 1 is PLX PCI Bridge */
4420                 if (!hc->pci_origmembase) {
4421                         printk(KERN_WARNING
4422                                "HFC-multi: No IO-Memory for PCI card found\n");
4423                         pci_disable_device(hc->pci_dev);
4424                         return -EIO;
4425                 }
4426
4427                 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4428                 if (!hc->pci_membase) {
4429                         printk(KERN_WARNING "HFC-multi: failed to remap io "
4430                                "address space. (internal error)\n");
4431                         pci_disable_device(hc->pci_dev);
4432                         return -EIO;
4433                 }
4434
4435                 printk(KERN_INFO
4436                        "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4437                        "leds-type %d\n",
4438                        hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4439                        hc->pci_dev->irq, HZ, hc->leds);
4440                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4441                 break;
4442         case HFC_IO_MODE_PCIMEM:
4443                 hc->HFC_outb = HFC_outb_pcimem;
4444                 hc->HFC_inb = HFC_inb_pcimem;
4445                 hc->HFC_inw = HFC_inw_pcimem;
4446                 hc->HFC_wait = HFC_wait_pcimem;
4447                 hc->read_fifo = read_fifo_pcimem;
4448                 hc->write_fifo = write_fifo_pcimem;
4449                 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4450                 if (!hc->pci_origmembase) {
4451                         printk(KERN_WARNING
4452                                "HFC-multi: No IO-Memory for PCI card found\n");
4453                         pci_disable_device(hc->pci_dev);
4454                         return -EIO;
4455                 }
4456
4457                 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4458                 if (!hc->pci_membase) {
4459                         printk(KERN_WARNING
4460                                "HFC-multi: failed to remap io address space. "
4461                                "(internal error)\n");
4462                         pci_disable_device(hc->pci_dev);
4463                         return -EIO;
4464                 }
4465                 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ "
4466                        "%d HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4467                        hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4468                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4469                 break;
4470         case HFC_IO_MODE_REGIO:
4471                 hc->HFC_outb = HFC_outb_regio;
4472                 hc->HFC_inb = HFC_inb_regio;
4473                 hc->HFC_inw = HFC_inw_regio;
4474                 hc->HFC_wait = HFC_wait_regio;
4475                 hc->read_fifo = read_fifo_regio;
4476                 hc->write_fifo = write_fifo_regio;
4477                 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4478                 if (!hc->pci_iobase) {
4479                         printk(KERN_WARNING
4480                                "HFC-multi: No IO for PCI card found\n");
4481                         pci_disable_device(hc->pci_dev);
4482                         return -EIO;
4483                 }
4484
4485                 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4486                         printk(KERN_WARNING "HFC-multi: failed to request "
4487                                "address space at 0x%08lx (internal error)\n",
4488                                hc->pci_iobase);
4489                         pci_disable_device(hc->pci_dev);
4490                         return -EIO;
4491                 }
4492
4493                 printk(KERN_INFO
4494                        "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4495                        m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4496                        hc->pci_dev->irq, HZ, hc->leds);
4497                 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4498                 break;
4499         default:
4500                 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4501                 pci_disable_device(hc->pci_dev);
4502                 return -EIO;
4503         }
4504
4505         pci_set_drvdata(hc->pci_dev, hc);
4506
4507         /* At this point the needed PCI config is done */
4508         /* fifos are still not enabled */
4509         return 0;
4510 }
4511
4512
4513 /*
4514  * remove port
4515  */
4516
4517 static void
4518 release_port(struct hfc_multi *hc, struct dchannel *dch)
4519 {
4520         int     pt, ci, i = 0;
4521         u_long  flags;
4522         struct bchannel *pb;
4523
4524         ci = dch->slot;
4525         pt = hc->chan[ci].port;
4526
4527         if (debug & DEBUG_HFCMULTI_INIT)
4528                 printk(KERN_DEBUG "%s: entered for port %d\n",
4529                        __func__, pt + 1);
4530
4531         if (pt >= hc->ports) {
4532                 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4533                        __func__, pt + 1);
4534                 return;
4535         }
4536
4537         if (debug & DEBUG_HFCMULTI_INIT)
4538                 printk(KERN_DEBUG "%s: releasing port=%d\n",
4539                        __func__, pt + 1);
4540
4541         if (dch->dev.D.protocol == ISDN_P_TE_S0)
4542                 l1_event(dch->l1, CLOSE_CHANNEL);
4543
4544         hc->chan[ci].dch = NULL;
4545
4546         if (hc->created[pt]) {
4547                 hc->created[pt] = 0;
4548                 mISDN_unregister_device(&dch->dev);
4549         }
4550
4551         spin_lock_irqsave(&hc->lock, flags);
4552
4553         if (dch->timer.function) {
4554                 del_timer(&dch->timer);
4555                 dch->timer.function = NULL;
4556         }
4557
4558         if (hc->ctype == HFC_TYPE_E1) { /* E1 */
4559                 /* remove sync */
4560                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4561                         hc->syncronized = 0;
4562                         plxsd_checksync(hc, 1);
4563                 }
4564                 /* free channels */
4565                 for (i = 0; i <= 31; i++) {
4566                         if (!((1 << i) & hc->bmask[pt])) /* skip unused chan */
4567                                 continue;
4568                         if (hc->chan[i].bch) {
4569                                 if (debug & DEBUG_HFCMULTI_INIT)
4570                                         printk(KERN_DEBUG
4571                                                "%s: free port %d channel %d\n",
4572                                                __func__, hc->chan[i].port + 1, i);
4573                                 pb = hc->chan[i].bch;
4574                                 hc->chan[i].bch = NULL;
4575                                 spin_unlock_irqrestore(&hc->lock, flags);
4576                                 mISDN_freebchannel(pb);
4577                                 kfree(pb);
4578                                 kfree(hc->chan[i].coeff);
4579                                 spin_lock_irqsave(&hc->lock, flags);
4580                         }
4581                 }
4582         } else {
4583                 /* remove sync */
4584                 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4585                         hc->syncronized &=
4586                                 ~(1 << hc->chan[ci].port);
4587                         plxsd_checksync(hc, 1);
4588                 }
4589                 /* free channels */
4590                 if (hc->chan[ci - 2].bch) {
4591                         if (debug & DEBUG_HFCMULTI_INIT)
4592                                 printk(KERN_DEBUG
4593                                        "%s: free port %d channel %d\n",
4594                                        __func__, hc->chan[ci - 2].port + 1,
4595                                        ci - 2);
4596                         pb = hc->chan[ci - 2].bch;
4597                         hc->chan[ci - 2].bch = NULL;
4598                         spin_unlock_irqrestore(&hc->lock, flags);
4599                         mISDN_freebchannel(pb);
4600                         kfree(pb);
4601                         kfree(hc->chan[ci - 2].coeff);
4602                         spin_lock_irqsave(&hc->lock, flags);
4603                 }
4604                 if (hc->chan[ci - 1].bch) {
4605                         if (debug & DEBUG_HFCMULTI_INIT)
4606                                 printk(KERN_DEBUG
4607                                        "%s: free port %d channel %d\n",
4608                                        __func__, hc->chan[ci - 1].port + 1,
4609                                        ci - 1);
4610                         pb = hc->chan[ci - 1].bch;
4611                         hc->chan[ci - 1].bch = NULL;
4612                         spin_unlock_irqrestore(&hc->lock, flags);
4613                         mISDN_freebchannel(pb);
4614                         kfree(pb);
4615                         kfree(hc->chan[ci - 1].coeff);
4616                         spin_lock_irqsave(&hc->lock, flags);
4617                 }
4618         }
4619
4620         spin_unlock_irqrestore(&hc->lock, flags);
4621
4622         if (debug & DEBUG_HFCMULTI_INIT)
4623                 printk(KERN_DEBUG "%s: free port %d channel D(%d)\n", __func__,
4624                         pt+1, ci);
4625         mISDN_freedchannel(dch);
4626         kfree(dch);
4627
4628         if (debug & DEBUG_HFCMULTI_INIT)
4629                 printk(KERN_DEBUG "%s: done!\n", __func__);
4630 }
4631
4632 static void
4633 release_card(struct hfc_multi *hc)
4634 {
4635         u_long  flags;
4636         int     ch;
4637
4638         if (debug & DEBUG_HFCMULTI_INIT)
4639                 printk(KERN_DEBUG "%s: release card (%d) entered\n",
4640                        __func__, hc->id);
4641
4642         /* unregister clock source */
4643         if (hc->iclock)
4644                 mISDN_unregister_clock(hc->iclock);
4645
4646         /* disable and free irq */
4647         spin_lock_irqsave(&hc->lock, flags);
4648         disable_hwirq(hc);
4649         spin_unlock_irqrestore(&hc->lock, flags);
4650         udelay(1000);
4651         if (hc->irq) {
4652                 if (debug & DEBUG_HFCMULTI_INIT)
4653                         printk(KERN_DEBUG "%s: free irq %d (hc=%p)\n",
4654                             __func__, hc->irq, hc);
4655                 free_irq(hc->irq, hc);
4656                 hc->irq = 0;
4657
4658         }
4659
4660         /* disable D-channels & B-channels */
4661         if (debug & DEBUG_HFCMULTI_INIT)
4662                 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4663                        __func__);
4664         for (ch = 0; ch <= 31; ch++) {
4665                 if (hc->chan[ch].dch)
4666                         release_port(hc, hc->chan[ch].dch);
4667         }
4668
4669         /* dimm leds */
4670         if (hc->leds)
4671                 hfcmulti_leds(hc);
4672
4673         /* release hardware */
4674         release_io_hfcmulti(hc);
4675
4676         if (debug & DEBUG_HFCMULTI_INIT)
4677                 printk(KERN_DEBUG "%s: remove instance from list\n",
4678                        __func__);
4679         list_del(&hc->list);
4680
4681         if (debug & DEBUG_HFCMULTI_INIT)
4682                 printk(KERN_DEBUG "%s: delete instance\n", __func__);
4683         if (hc == syncmaster)
4684                 syncmaster = NULL;
4685         kfree(hc);
4686         if (debug & DEBUG_HFCMULTI_INIT)
4687                 printk(KERN_DEBUG "%s: card successfully removed\n",
4688                        __func__);
4689 }
4690
4691 static void
4692 init_e1_port_hw(struct hfc_multi *hc, struct hm_map *m)
4693 {
4694         /* set optical line type */
4695         if (port[Port_cnt] & 0x001) {
4696                 if (!m->opticalsupport)  {
4697                         printk(KERN_INFO
4698                                "This board has no optical "
4699                                "support\n");
4700                 } else {
4701                         if (debug & DEBUG_HFCMULTI_INIT)
4702                                 printk(KERN_DEBUG
4703                                        "%s: PORT set optical "
4704                                        "interfacs: card(%d) "
4705                                        "port(%d)\n",
4706                                        __func__,
4707                                        HFC_cnt + 1, 1);
4708                         test_and_set_bit(HFC_CFG_OPTICAL,
4709                             &hc->chan[hc->dnum[0]].cfg);
4710                 }
4711         }
4712         /* set LOS report */
4713         if (port[Port_cnt] & 0x004) {
4714                 if (debug & DEBUG_HFCMULTI_INIT)
4715                         printk(KERN_DEBUG "%s: PORT set "
4716                                "LOS report: card(%d) port(%d)\n",
4717                                __func__, HFC_cnt + 1, 1);
4718                 test_and_set_bit(HFC_CFG_REPORT_LOS,
4719                     &hc->chan[hc->dnum[0]].cfg);
4720         }
4721         /* set AIS report */
4722         if (port[Port_cnt] & 0x008) {
4723                 if (debug & DEBUG_HFCMULTI_INIT)
4724                         printk(KERN_DEBUG "%s: PORT set "
4725                                "AIS report: card(%d) port(%d)\n",
4726                                __func__, HFC_cnt + 1, 1);
4727                 test_and_set_bit(HFC_CFG_REPORT_AIS,
4728                     &hc->chan[hc->dnum[0]].cfg);
4729         }
4730         /* set SLIP report */
4731         if (port[Port_cnt] & 0x010) {
4732                 if (debug & DEBUG_HFCMULTI_INIT)
4733                         printk(KERN_DEBUG
4734                                "%s: PORT set SLIP report: "
4735                                "card(%d) port(%d)\n",
4736                                __func__, HFC_cnt + 1, 1);
4737                 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4738                     &hc->chan[hc->dnum[0]].cfg);
4739         }
4740         /* set RDI report */
4741         if (port[Port_cnt] & 0x020) {
4742                 if (debug & DEBUG_HFCMULTI_INIT)
4743                         printk(KERN_DEBUG
4744                                "%s: PORT set RDI report: "
4745                                "card(%d) port(%d)\n",
4746                                __func__, HFC_cnt + 1, 1);
4747                 test_and_set_bit(HFC_CFG_REPORT_RDI,
4748                     &hc->chan[hc->dnum[0]].cfg);
4749         }
4750         /* set CRC-4 Mode */
4751         if (!(port[Port_cnt] & 0x100)) {
4752                 if (debug & DEBUG_HFCMULTI_INIT)
4753                         printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4754                                " card(%d) port(%d)\n",
4755                                __func__, HFC_cnt + 1, 1);
4756                 test_and_set_bit(HFC_CFG_CRC4,
4757                     &hc->chan[hc->dnum[0]].cfg);
4758         } else {
4759                 if (debug & DEBUG_HFCMULTI_INIT)
4760                         printk(KERN_DEBUG "%s: PORT turn off CRC4"
4761                                " report: card(%d) port(%d)\n",
4762                                __func__, HFC_cnt + 1, 1);
4763         }
4764         /* set forced clock */
4765         if (port[Port_cnt] & 0x0200) {
4766                 if (debug & DEBUG_HFCMULTI_INIT)
4767                         printk(KERN_DEBUG "%s: PORT force getting clock from "
4768                                "E1: card(%d) port(%d)\n",
4769                                __func__, HFC_cnt + 1, 1);
4770                 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4771         } else
4772                 if (port[Port_cnt] & 0x0400) {
4773                         if (debug & DEBUG_HFCMULTI_INIT)
4774                                 printk(KERN_DEBUG "%s: PORT force putting clock to "
4775                                        "E1: card(%d) port(%d)\n",
4776                                        __func__, HFC_cnt + 1, 1);
4777                         test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4778                 }
4779         /* set JATT PLL */
4780         if (port[Port_cnt] & 0x0800) {
4781                 if (debug & DEBUG_HFCMULTI_INIT)
4782                         printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4783                                "E1: card(%d) port(%d)\n",
4784                                __func__, HFC_cnt + 1, 1);
4785                 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4786         }
4787         /* set elastic jitter buffer */
4788         if (port[Port_cnt] & 0x3000) {
4789                 hc->chan[hc->dnum[0]].jitter = (port[Port_cnt]>>12) & 0x3;
4790                 if (debug & DEBUG_HFCMULTI_INIT)
4791                         printk(KERN_DEBUG
4792                                "%s: PORT set elastic "
4793                                "buffer to %d: card(%d) port(%d)\n",
4794                             __func__, hc->chan[hc->dnum[0]].jitter,
4795                                HFC_cnt + 1, 1);
4796         } else
4797                 hc->chan[hc->dnum[0]].jitter = 2; /* default */
4798 }
4799
4800 static int
4801 init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt)
4802 {
4803         struct dchannel *dch;
4804         struct bchannel *bch;
4805         int             ch, ret = 0;
4806         char            name[MISDN_MAX_IDLEN];
4807         int             bcount = 0;
4808
4809         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4810         if (!dch)
4811                 return -ENOMEM;
4812         dch->debug = debug;
4813         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4814         dch->hw = hc;
4815         dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4816         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4817             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4818         dch->dev.D.send = handle_dmsg;
4819         dch->dev.D.ctrl = hfcm_dctrl;
4820         dch->slot = hc->dnum[pt];
4821         hc->chan[hc->dnum[pt]].dch = dch;
4822         hc->chan[hc->dnum[pt]].port = pt;
4823         hc->chan[hc->dnum[pt]].nt_timer = -1;
4824         for (ch = 1; ch <= 31; ch++) {
4825                 if (!((1 << ch) & hc->bmask[pt])) /* skip unused channel */
4826                         continue;
4827                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4828                 if (!bch) {
4829                         printk(KERN_ERR "%s: no memory for bchannel\n",
4830                             __func__);
4831                         ret = -ENOMEM;
4832                         goto free_chan;
4833                 }
4834                 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4835                 if (!hc->chan[ch].coeff) {
4836                         printk(KERN_ERR "%s: no memory for coeffs\n",
4837                             __func__);
4838                         ret = -ENOMEM;
4839                         kfree(bch);
4840                         goto free_chan;
4841                 }
4842                 bch->nr = ch;
4843                 bch->slot = ch;
4844                 bch->debug = debug;
4845                 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4846                 bch->hw = hc;
4847                 bch->ch.send = handle_bmsg;
4848                 bch->ch.ctrl = hfcm_bctrl;
4849                 bch->ch.nr = ch;
4850                 list_add(&bch->ch.list, &dch->dev.bchannels);
4851                 hc->chan[ch].bch = bch;
4852                 hc->chan[ch].port = pt;
4853                 set_channelmap(bch->nr, dch->dev.channelmap);
4854                 bcount++;
4855         }
4856         dch->dev.nrbchan = bcount;
4857         if (pt == 0)
4858                 init_e1_port_hw(hc, m);
4859         if (hc->ports > 1)
4860                 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d-%d",
4861                                 HFC_cnt + 1, pt+1);
4862         else
4863                 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
4864         ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4865         if (ret)
4866                 goto free_chan;
4867         hc->created[pt] = 1;
4868         return ret;
4869 free_chan:
4870         release_port(hc, dch);
4871         return ret;
4872 }
4873
4874 static int
4875 init_multi_port(struct hfc_multi *hc, int pt)
4876 {
4877         struct dchannel *dch;
4878         struct bchannel *bch;
4879         int             ch, i, ret = 0;
4880         char            name[MISDN_MAX_IDLEN];
4881
4882         dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4883         if (!dch)
4884                 return -ENOMEM;
4885         dch->debug = debug;
4886         mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4887         dch->hw = hc;
4888         dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4889         dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4890                 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4891         dch->dev.D.send = handle_dmsg;
4892         dch->dev.D.ctrl = hfcm_dctrl;
4893         dch->dev.nrbchan = 2;
4894         i = pt << 2;
4895         dch->slot = i + 2;
4896         hc->chan[i + 2].dch = dch;
4897         hc->chan[i + 2].port = pt;
4898         hc->chan[i + 2].nt_timer = -1;
4899         for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4900                 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4901                 if (!bch) {
4902                         printk(KERN_ERR "%s: no memory for bchannel\n",
4903                                __func__);
4904                         ret = -ENOMEM;
4905                         goto free_chan;
4906                 }
4907                 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4908                 if (!hc->chan[i + ch].coeff) {
4909                         printk(KERN_ERR "%s: no memory for coeffs\n",
4910                                __func__);
4911                         ret = -ENOMEM;
4912                         kfree(bch);
4913                         goto free_chan;
4914                 }
4915                 bch->nr = ch + 1;
4916                 bch->slot = i + ch;
4917                 bch->debug = debug;
4918                 mISDN_initbchannel(bch, MAX_DATA_MEM, poll >> 1);
4919                 bch->hw = hc;
4920                 bch->ch.send = handle_bmsg;
4921                 bch->ch.ctrl = hfcm_bctrl;
4922                 bch->ch.nr = ch + 1;
4923                 list_add(&bch->ch.list, &dch->dev.bchannels);
4924                 hc->chan[i + ch].bch = bch;
4925                 hc->chan[i + ch].port = pt;
4926                 set_channelmap(bch->nr, dch->dev.channelmap);
4927         }
4928         /* set master clock */
4929         if (port[Port_cnt] & 0x001) {
4930                 if (debug & DEBUG_HFCMULTI_INIT)
4931                         printk(KERN_DEBUG
4932                                "%s: PROTOCOL set master clock: "
4933                                "card(%d) port(%d)\n",
4934                                __func__, HFC_cnt + 1, pt + 1);
4935                 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4936                         printk(KERN_ERR "Error: Master clock "
4937                                "for port(%d) of card(%d) is only"
4938                                " possible with TE-mode\n",
4939                                pt + 1, HFC_cnt + 1);
4940                         ret = -EINVAL;
4941                         goto free_chan;
4942                 }
4943                 if (hc->masterclk >= 0) {
4944                         printk(KERN_ERR "Error: Master clock "
4945                                "for port(%d) of card(%d) already "
4946                                "defined for port(%d)\n",
4947                                pt + 1, HFC_cnt + 1, hc->masterclk + 1);
4948                         ret = -EINVAL;
4949                         goto free_chan;
4950                 }
4951                 hc->masterclk = pt;
4952         }
4953         /* set transmitter line to non capacitive */
4954         if (port[Port_cnt] & 0x002) {
4955                 if (debug & DEBUG_HFCMULTI_INIT)
4956                         printk(KERN_DEBUG
4957                                "%s: PROTOCOL set non capacitive "
4958                                "transmitter: card(%d) port(%d)\n",
4959                                __func__, HFC_cnt + 1, pt + 1);
4960                 test_and_set_bit(HFC_CFG_NONCAP_TX,
4961                                  &hc->chan[i + 2].cfg);
4962         }
4963         /* disable E-channel */
4964         if (port[Port_cnt] & 0x004) {
4965                 if (debug & DEBUG_HFCMULTI_INIT)
4966                         printk(KERN_DEBUG
4967                                "%s: PROTOCOL disable E-channel: "
4968                                "card(%d) port(%d)\n",
4969                                __func__, HFC_cnt + 1, pt + 1);
4970                 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4971                                  &hc->chan[i + 2].cfg);
4972         }
4973         if (hc->ctype == HFC_TYPE_XHFC) {
4974                 snprintf(name, MISDN_MAX_IDLEN - 1, "xhfc.%d-%d",
4975                          HFC_cnt + 1, pt + 1);
4976                 ret = mISDN_register_device(&dch->dev, NULL, name);
4977         } else {
4978                 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
4979                          hc->ctype, HFC_cnt + 1, pt + 1);
4980                 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
4981         }
4982         if (ret)
4983                 goto free_chan;
4984         hc->created[pt] = 1;
4985         return ret;
4986 free_chan:
4987         release_port(hc, dch);
4988         return ret;
4989 }
4990
4991 static int
4992 hfcmulti_init(struct hm_map *m, struct pci_dev *pdev,
4993               const struct pci_device_id *ent)
4994 {
4995         int             ret_err = 0;
4996         int             pt;
4997         struct hfc_multi        *hc;
4998         u_long          flags;
4999         u_char          dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
5000         int             i, ch;
5001         u_int           maskcheck;
5002
5003         if (HFC_cnt >= MAX_CARDS) {
5004                 printk(KERN_ERR "too many cards (max=%d).\n",
5005                        MAX_CARDS);
5006                 return -EINVAL;
5007         }
5008         if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
5009                 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
5010                        "type[%d] %d was supplied as module parameter\n",
5011                        m->vendor_name, m->card_name, m->type, HFC_cnt,
5012                        type[HFC_cnt] & 0xff);
5013                 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
5014                        "first, to see cards and their types.");
5015                 return -EINVAL;
5016         }
5017         if (debug & DEBUG_HFCMULTI_INIT)
5018                 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
5019                        __func__, m->vendor_name, m->card_name, m->type,
5020                        type[HFC_cnt]);
5021
5022         /* allocate card+fifo structure */
5023         hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
5024         if (!hc) {
5025                 printk(KERN_ERR "No kmem for HFC-Multi card\n");
5026                 return -ENOMEM;
5027         }
5028         spin_lock_init(&hc->lock);
5029         hc->mtyp = m;
5030         hc->ctype =  m->type;
5031         hc->ports = m->ports;
5032         hc->id = HFC_cnt;
5033         hc->pcm = pcm[HFC_cnt];
5034         hc->io_mode = iomode[HFC_cnt];
5035         if (hc->ctype == HFC_TYPE_E1 && dmask[E1_cnt]) {
5036                 /* fragment card */
5037                 pt = 0;
5038                 maskcheck = 0;
5039                 for (ch = 0; ch <= 31; ch++) {
5040                         if (!((1 << ch) & dmask[E1_cnt]))
5041                                 continue;
5042                         hc->dnum[pt] = ch;
5043                         hc->bmask[pt] = bmask[bmask_cnt++];
5044                         if ((maskcheck & hc->bmask[pt])
5045                          || (dmask[E1_cnt] & hc->bmask[pt])) {
5046                                 printk(KERN_INFO
5047                                        "HFC-E1 #%d has overlapping B-channels on fragment #%d\n",
5048                                        E1_cnt + 1, pt);
5049                                 kfree(hc);
5050                                 return -EINVAL;
5051                         }
5052                         maskcheck |= hc->bmask[pt];
5053                         printk(KERN_INFO
5054                                "HFC-E1 #%d uses D-channel on slot %d and a B-channel map of 0x%08x\n",
5055                                 E1_cnt + 1, ch, hc->bmask[pt]);
5056                         pt++;
5057                 }
5058                 hc->ports = pt;
5059         }
5060         if (hc->ctype == HFC_TYPE_E1 && !dmask[E1_cnt]) {
5061                 /* default card layout */
5062                 hc->dnum[0] = 16;
5063                 hc->bmask[0] = 0xfffefffe;
5064                 hc->ports = 1;
5065         }
5066
5067         /* set chip specific features */
5068         hc->masterclk = -1;
5069         if (type[HFC_cnt] & 0x100) {
5070                 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
5071                 hc->silence = 0xff; /* ulaw silence */
5072         } else
5073                 hc->silence = 0x2a; /* alaw silence */
5074         if ((poll >> 1) > sizeof(hc->silence_data)) {
5075                 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
5076                        "please fix\n");
5077                 kfree(hc);
5078                 return -EINVAL;
5079         }
5080         for (i = 0; i < (poll >> 1); i++)
5081                 hc->silence_data[i] = hc->silence;
5082
5083         if (hc->ctype != HFC_TYPE_XHFC) {
5084                 if (!(type[HFC_cnt] & 0x200))
5085                         test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
5086                 test_and_set_bit(HFC_CHIP_CONF, &hc->chip);
5087         }
5088
5089         if (type[HFC_cnt] & 0x800)
5090                 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5091         if (type[HFC_cnt] & 0x1000) {
5092                 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
5093                 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
5094         }
5095         if (type[HFC_cnt] & 0x4000)
5096                 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
5097         if (type[HFC_cnt] & 0x8000)
5098                 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
5099         hc->slots = 32;
5100         if (type[HFC_cnt] & 0x10000)
5101                 hc->slots = 64;
5102         if (type[HFC_cnt] & 0x20000)
5103                 hc->slots = 128;
5104         if (type[HFC_cnt] & 0x80000) {
5105                 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
5106                 hc->wdcount = 0;
5107                 hc->wdbyte = V_GPIO_OUT2;
5108                 printk(KERN_NOTICE "Watchdog enabled\n");
5109         }
5110
5111         if (pdev && ent)
5112                 /* setup pci, hc->slots may change due to PLXSD */
5113                 ret_err = setup_pci(hc, pdev, ent);
5114         else
5115 #ifdef CONFIG_MISDN_HFCMULTI_8xx
5116                 ret_err = setup_embedded(hc, m);
5117 #else
5118         {
5119                 printk(KERN_WARNING "Embedded IO Mode not selected\n");
5120                 ret_err = -EIO;
5121         }
5122 #endif
5123         if (ret_err) {
5124                 if (hc == syncmaster)
5125                         syncmaster = NULL;
5126                 kfree(hc);
5127                 return ret_err;
5128         }
5129
5130         hc->HFC_outb_nodebug = hc->HFC_outb;
5131         hc->HFC_inb_nodebug = hc->HFC_inb;
5132         hc->HFC_inw_nodebug = hc->HFC_inw;
5133         hc->HFC_wait_nodebug = hc->HFC_wait;
5134 #ifdef HFC_REGISTER_DEBUG
5135         hc->HFC_outb = HFC_outb_debug;
5136         hc->HFC_inb = HFC_inb_debug;
5137         hc->HFC_inw = HFC_inw_debug;
5138         hc->HFC_wait = HFC_wait_debug;
5139 #endif
5140         /* create channels */
5141         for (pt = 0; pt < hc->ports; pt++) {
5142                 if (Port_cnt >= MAX_PORTS) {
5143                         printk(KERN_ERR "too many ports (max=%d).\n",
5144                                MAX_PORTS);
5145                         ret_err = -EINVAL;
5146                         goto free_card;
5147                 }
5148                 if (hc->ctype == HFC_TYPE_E1)
5149                         ret_err = init_e1_port(hc, m, pt);
5150                 else
5151                         ret_err = init_multi_port(hc, pt);
5152                 if (debug & DEBUG_HFCMULTI_INIT)
5153                         printk(KERN_DEBUG
5154                             "%s: Registering D-channel, card(%d) port(%d) "
5155                                "result %d\n",
5156                             __func__, HFC_cnt + 1, pt + 1, ret_err);
5157
5158                 if (ret_err) {
5159                         while (pt) { /* release already registered ports */
5160                                 pt--;
5161                                 if (hc->ctype == HFC_TYPE_E1)
5162                                         release_port(hc,
5163                                                 hc->chan[hc->dnum[pt]].dch);
5164                                 else
5165                                         release_port(hc,
5166                                                 hc->chan[(pt << 2) + 2].dch);
5167                         }
5168                         goto free_card;
5169                 }
5170                 if (hc->ctype != HFC_TYPE_E1)
5171                         Port_cnt++; /* for each S0 port */
5172         }
5173         if (hc->ctype == HFC_TYPE_E1) {
5174                 Port_cnt++; /* for each E1 port */
5175                 E1_cnt++;
5176         }
5177
5178         /* disp switches */
5179         switch (m->dip_type) {
5180         case DIP_4S:
5181                 /*
5182                  * Get DIP setting for beroNet 1S/2S/4S cards
5183                  * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5184                  * GPI 19/23 (R_GPI_IN2))
5185                  */
5186                 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5187                         ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5188                         (~HFC_inb(hc, R_GPI_IN2) & 0x08);
5189
5190                 /* Port mode (TE/NT) jumpers */
5191                 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4)  & 0xf);
5192
5193                 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5194                         pmj = ~pmj & 0xf;
5195
5196                 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
5197                        m->vendor_name, m->card_name, dips, pmj);
5198                 break;
5199         case DIP_8S:
5200                 /*
5201                  * Get DIP Setting for beroNet 8S0+ cards
5202                  * Enable PCI auxbridge function
5203                  */
5204                 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5205                 /* prepare access to auxport */
5206                 outw(0x4000, hc->pci_iobase + 4);
5207                 /*
5208                  * some dummy reads are required to
5209                  * read valid DIP switch data
5210                  */
5211                 dips = inb(hc->pci_iobase);
5212                 dips = inb(hc->pci_iobase);
5213                 dips = inb(hc->pci_iobase);
5214                 dips = ~inb(hc->pci_iobase) & 0x3F;
5215                 outw(0x0, hc->pci_iobase + 4);
5216                 /* disable PCI auxbridge function */
5217                 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5218                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5219                        m->vendor_name, m->card_name, dips);
5220                 break;
5221         case DIP_E1:
5222                 /*
5223                  * get DIP Setting for beroNet E1 cards
5224                  * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5225                  */
5226                 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0) >> 4;
5227                 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5228                        m->vendor_name, m->card_name, dips);
5229                 break;
5230         }
5231
5232         /* add to list */
5233         spin_lock_irqsave(&HFClock, flags);
5234         list_add_tail(&hc->list, &HFClist);
5235         spin_unlock_irqrestore(&HFClock, flags);
5236
5237         /* use as clock source */
5238         if (clock == HFC_cnt + 1)
5239                 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5240
5241         /* initialize hardware */
5242         hc->irq = (m->irq) ? : hc->pci_dev->irq;
5243         ret_err = init_card(hc);
5244         if (ret_err) {
5245                 printk(KERN_ERR "init card returns %d\n", ret_err);
5246                 release_card(hc);
5247                 return ret_err;
5248         }
5249
5250         /* start IRQ and return */
5251         spin_lock_irqsave(&hc->lock, flags);
5252         enable_hwirq(hc);
5253         spin_unlock_irqrestore(&hc->lock, flags);
5254         return 0;
5255
5256 free_card:
5257         release_io_hfcmulti(hc);
5258         if (hc == syncmaster)
5259                 syncmaster = NULL;
5260         kfree(hc);
5261         return ret_err;
5262 }
5263
5264 static void hfc_remove_pci(struct pci_dev *pdev)
5265 {
5266         struct hfc_multi        *card = pci_get_drvdata(pdev);
5267         u_long                  flags;
5268
5269         if (debug)
5270                 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5271                        "device:%x subvendor:%x subdevice:%x\n",
5272                        pdev->vendor, pdev->device,
5273                        pdev->subsystem_vendor, pdev->subsystem_device);
5274
5275         if (card) {
5276                 spin_lock_irqsave(&HFClock, flags);
5277                 release_card(card);
5278                 spin_unlock_irqrestore(&HFClock, flags);
5279         }  else {
5280                 if (debug)
5281                         printk(KERN_DEBUG "%s: drvdata already removed\n",
5282                                __func__);
5283         }
5284 }
5285
5286 #define VENDOR_CCD      "Cologne Chip AG"
5287 #define VENDOR_BN       "beroNet GmbH"
5288 #define VENDOR_DIG      "Digium Inc."
5289 #define VENDOR_JH       "Junghanns.NET GmbH"
5290 #define VENDOR_PRIM     "PrimuX"
5291
5292 static const struct hm_map hfcm_map[] = {
5293         /*0*/   {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0, 0},
5294         /*1*/   {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5295         /*2*/   {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5296         /*3*/   {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5297         /*4*/   {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0, 0},
5298         /*5*/   {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0, 0},
5299         /*6*/   {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5300         /*7*/   {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0, 0},
5301         /*8*/   {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO, 0},
5302         /*9*/   {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0, 0},
5303         /*10*/  {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0, 0},
5304         /*11*/  {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0, 0},
5305
5306         /*12*/  {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0, 0},
5307         /*13*/  {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5308                  HFC_IO_MODE_REGIO, 0},
5309         /*14*/  {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0, 0},
5310         /*15*/  {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0, 0},
5311
5312         /*16*/  {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0, 0},
5313         /*17*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5314         /*18*/  {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0, 0},
5315
5316         /*19*/  {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5317         /*20*/  {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0, 0},
5318         /*21*/  {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5319         /*22*/  {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0, 0},
5320
5321         /*23*/  {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0, 0},
5322         /*24*/  {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0, 0},
5323         /*25*/  {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0, 0},
5324
5325         /*26*/  {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5326                  HFC_IO_MODE_PLXSD, 0},
5327         /*27*/  {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5328                  HFC_IO_MODE_PLXSD, 0},
5329         /*28*/  {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0, 0},
5330         /*29*/  {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0, 0},
5331         /*30*/  {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0, 0},
5332         /*31*/  {VENDOR_CCD, "XHFC-4S Speech Design", 5, 4, 0, 0, 0, 0,
5333                  HFC_IO_MODE_EMBSD, XHFC_IRQ},
5334         /*32*/  {VENDOR_JH, "HFC-8S (junghanns)", 8, 8, 1, 0, 0, 0, 0, 0},
5335         /*33*/  {VENDOR_BN, "HFC-2S Beronet Card PCIe", 4, 2, 1, 3, 0, DIP_4S, 0, 0},
5336         /*34*/  {VENDOR_BN, "HFC-4S Beronet Card PCIe", 4, 4, 1, 2, 0, DIP_4S, 0, 0},
5337 };
5338
5339 #undef H
5340 #define H(x)    ((unsigned long)&hfcm_map[x])
5341 static const struct pci_device_id hfmultipci_ids[] = {
5342
5343         /* Cards with HFC-4S Chip */
5344         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5345           PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5346         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5347           PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5348         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5349           PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5350         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5351           PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5352         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5353           PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5354         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5355           PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5356         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5357           PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5358         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5359           PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5360         { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5361           PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5362         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5363           PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5364         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5365           PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5366         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5367           PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5368         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5369           PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5370         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5371           PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5372         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5373           0xb761, 0, 0, H(33)}, /* BN2S PCIe */
5374         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5375           0xb762, 0, 0, H(34)}, /* BN4S PCIe */
5376
5377         /* Cards with HFC-8S Chip */
5378         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5379           PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5380         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5381           PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5382         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5383           PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5384         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5385           PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
5386         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5387           PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST  */
5388         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5389           PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST  */
5390         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5391           PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5392         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5393           PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5394         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5395           PCI_SUBDEVICE_ID_CCD_JH8S, 0, 0, H(32)}, /* Junganns 8S  */
5396
5397
5398         /* Cards with HFC-E1 Chip */
5399         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5400           PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5401         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5402           PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5403         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5404           PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5405         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5406           PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5407
5408         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5409           PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5410         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5411           PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5412         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5413           PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5414
5415         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5416           PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5417         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5418           PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5419
5420         { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5421           PCI_SUBDEVICE_ID_CCD_JHSE1, 0, 0, H(25)}, /* Junghanns E1 */
5422
5423         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC4S), 0 },
5424         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFC8S), 0 },
5425         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_HFCE1), 0 },
5426         {0, }
5427 };
5428 #undef H
5429
5430 MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5431
5432 static int
5433 hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5434 {
5435         struct hm_map   *m = (struct hm_map *)ent->driver_data;
5436         int             ret;
5437
5438         if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5439                     ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5440                     ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5441                     ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5442                 printk(KERN_ERR
5443                        "Unknown HFC multiport controller (vendor:%04x device:%04x "
5444                        "subvendor:%04x subdevice:%04x)\n", pdev->vendor,
5445                        pdev->device, pdev->subsystem_vendor,
5446                        pdev->subsystem_device);
5447                 printk(KERN_ERR
5448                        "Please contact the driver maintainer for support.\n");
5449                 return -ENODEV;
5450         }
5451         ret = hfcmulti_init(m, pdev, ent);
5452         if (ret)
5453                 return ret;
5454         HFC_cnt++;
5455         printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5456         return 0;
5457 }
5458
5459 static struct pci_driver hfcmultipci_driver = {
5460         .name           = "hfc_multi",
5461         .probe          = hfcmulti_probe,
5462         .remove         = hfc_remove_pci,
5463         .id_table       = hfmultipci_ids,
5464 };
5465
5466 static void __exit
5467 HFCmulti_cleanup(void)
5468 {
5469         struct hfc_multi *card, *next;
5470
5471         /* get rid of all devices of this driver */
5472         list_for_each_entry_safe(card, next, &HFClist, list)
5473                 release_card(card);
5474         pci_unregister_driver(&hfcmultipci_driver);
5475 }
5476
5477 static int __init
5478 HFCmulti_init(void)
5479 {
5480         int err;
5481         int i, xhfc = 0;
5482         struct hm_map m;
5483
5484         printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5485
5486 #ifdef IRQ_DEBUG
5487         printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
5488 #endif
5489
5490         if (debug & DEBUG_HFCMULTI_INIT)
5491                 printk(KERN_DEBUG "%s: init entered\n", __func__);
5492
5493         switch (poll) {
5494         case 0:
5495                 poll_timer = 6;
5496                 poll = 128;
5497                 break;
5498         case 8:
5499                 poll_timer = 2;
5500                 break;
5501         case 16:
5502                 poll_timer = 3;
5503                 break;
5504         case 32:
5505                 poll_timer = 4;
5506                 break;
5507         case 64:
5508                 poll_timer = 5;
5509                 break;
5510         case 128:
5511                 poll_timer = 6;
5512                 break;
5513         case 256:
5514                 poll_timer = 7;
5515                 break;
5516         default:
5517                 printk(KERN_ERR
5518                        "%s: Wrong poll value (%d).\n", __func__, poll);
5519                 err = -EINVAL;
5520                 return err;
5521
5522         }
5523
5524         if (!clock)
5525                 clock = 1;
5526
5527         /* Register the embedded devices.
5528          * This should be done before the PCI cards registration */
5529         switch (hwid) {
5530         case HWID_MINIP4:
5531                 xhfc = 1;
5532                 m = hfcm_map[31];
5533                 break;
5534         case HWID_MINIP8:
5535                 xhfc = 2;
5536                 m = hfcm_map[31];
5537                 break;
5538         case HWID_MINIP16:
5539                 xhfc = 4;
5540                 m = hfcm_map[31];
5541                 break;
5542         default:
5543                 xhfc = 0;
5544         }
5545
5546         for (i = 0; i < xhfc; ++i) {
5547                 err = hfcmulti_init(&m, NULL, NULL);
5548                 if (err) {
5549                         printk(KERN_ERR "error registering embedded driver: "
5550                                "%x\n", err);
5551                         return err;
5552                 }
5553                 HFC_cnt++;
5554                 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5555         }
5556
5557         /* Register the PCI cards */
5558         err = pci_register_driver(&hfcmultipci_driver);
5559         if (err < 0) {
5560                 printk(KERN_ERR "error registering pci driver: %x\n", err);
5561                 return err;
5562         }
5563
5564         return 0;
5565 }
5566
5567
5568 module_init(HFCmulti_init);
5569 module_exit(HFCmulti_cleanup);