1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 * Interrupt architecture for the GIC:
7 * o There is one Interrupt Distributor, which receives interrupts
8 * from system devices and sends them to the Interrupt Controllers.
10 * o There is one CPU Interface per CPU, which sends interrupts sent
11 * by the Distributor, and interrupts generated locally, to the
12 * associated CPU. The base address of the CPU interface is usually
13 * aliased so that the same address points to different chips depending
14 * on the CPU it is accessed from.
16 * Note that IRQs 0-31 are special - they are local to each CPU.
17 * As such, the enable set/clear, pending set/clear and active bit
18 * registers are banked per-cpu for these sources.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/smp.h>
26 #include <linux/cpu.h>
27 #include <linux/cpu_pm.h>
28 #include <linux/cpumask.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/acpi.h>
34 #include <linux/irqdomain.h>
35 #include <linux/interrupt.h>
36 #include <linux/percpu.h>
37 #include <linux/slab.h>
38 #include <linux/irqchip.h>
39 #include <linux/irqchip/chained_irq.h>
40 #include <linux/irqchip/arm-gic.h>
42 #include <asm/cputype.h>
44 #include <asm/exception.h>
45 #include <asm/smp_plat.h>
48 #include "irq-gic-common.h"
51 #include <asm/cpufeature.h>
53 static void gic_check_cpu_features(void)
55 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
56 TAINT_CPU_OUT_OF_SPEC,
57 "GICv3 system registers enabled, broken firmware!\n");
60 #define gic_check_cpu_features() do { } while(0)
64 void __iomem *common_base;
65 void __percpu * __iomem *percpu_base;
68 struct gic_chip_data {
70 union gic_base dist_base;
71 union gic_base cpu_base;
72 void __iomem *raw_dist_base;
73 void __iomem *raw_cpu_base;
75 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
76 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
77 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
78 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
79 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
80 u32 __percpu *saved_ppi_enable;
81 u32 __percpu *saved_ppi_active;
82 u32 __percpu *saved_ppi_conf;
84 struct irq_domain *domain;
85 unsigned int gic_irqs;
88 #ifdef CONFIG_BL_SWITCHER
90 static DEFINE_RAW_SPINLOCK(cpu_map_lock);
92 #define gic_lock_irqsave(f) \
93 raw_spin_lock_irqsave(&cpu_map_lock, (f))
94 #define gic_unlock_irqrestore(f) \
95 raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
97 #define gic_lock() raw_spin_lock(&cpu_map_lock)
98 #define gic_unlock() raw_spin_unlock(&cpu_map_lock)
102 #define gic_lock_irqsave(f) do { (void)(f); } while(0)
103 #define gic_unlock_irqrestore(f) do { (void)(f); } while(0)
105 #define gic_lock() do { } while(0)
106 #define gic_unlock() do { } while(0)
111 * The GIC mapping of CPU interfaces does not necessarily match
112 * the logical CPU numbering. Let's use a mapping as returned
115 #define NR_GIC_CPU_IF 8
116 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
118 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
120 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
122 static struct gic_kvm_info gic_v2_kvm_info;
124 static DEFINE_PER_CPU(u32, sgi_intid);
126 #ifdef CONFIG_GIC_NON_BANKED
127 static DEFINE_STATIC_KEY_FALSE(frankengic_key);
129 static void enable_frankengic(void)
131 static_branch_enable(&frankengic_key);
134 static inline void __iomem *__get_base(union gic_base *base)
136 if (static_branch_unlikely(&frankengic_key))
137 return raw_cpu_read(*base->percpu_base);
139 return base->common_base;
142 #define gic_data_dist_base(d) __get_base(&(d)->dist_base)
143 #define gic_data_cpu_base(d) __get_base(&(d)->cpu_base)
145 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
146 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
147 #define enable_frankengic() do { } while(0)
150 static inline void __iomem *gic_dist_base(struct irq_data *d)
152 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
153 return gic_data_dist_base(gic_data);
156 static inline void __iomem *gic_cpu_base(struct irq_data *d)
158 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
159 return gic_data_cpu_base(gic_data);
162 static inline unsigned int gic_irq(struct irq_data *d)
167 static inline bool cascading_gic_irq(struct irq_data *d)
169 void *data = irq_data_get_irq_handler_data(d);
172 * If handler_data is set, this is a cascading interrupt, and
173 * it cannot possibly be forwarded.
179 * Routines to acknowledge, disable and enable interrupts
181 static void gic_poke_irq(struct irq_data *d, u32 offset)
183 u32 mask = 1 << (gic_irq(d) % 32);
184 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
187 static int gic_peek_irq(struct irq_data *d, u32 offset)
189 u32 mask = 1 << (gic_irq(d) % 32);
190 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
193 static void gic_mask_irq(struct irq_data *d)
195 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
198 static void gic_eoimode1_mask_irq(struct irq_data *d)
202 * When masking a forwarded interrupt, make sure it is
203 * deactivated as well.
205 * This ensures that an interrupt that is getting
206 * disabled/masked will not get "stuck", because there is
207 * noone to deactivate it (guest is being terminated).
209 if (irqd_is_forwarded_to_vcpu(d))
210 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
213 static void gic_unmask_irq(struct irq_data *d)
215 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
218 static void gic_eoi_irq(struct irq_data *d)
220 u32 hwirq = gic_irq(d);
223 hwirq = this_cpu_read(sgi_intid);
225 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
228 static void gic_eoimode1_eoi_irq(struct irq_data *d)
230 u32 hwirq = gic_irq(d);
232 /* Do not deactivate an IRQ forwarded to a vcpu. */
233 if (irqd_is_forwarded_to_vcpu(d))
237 hwirq = this_cpu_read(sgi_intid);
239 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
242 static int gic_irq_set_irqchip_state(struct irq_data *d,
243 enum irqchip_irq_state which, bool val)
248 case IRQCHIP_STATE_PENDING:
249 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
252 case IRQCHIP_STATE_ACTIVE:
253 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
256 case IRQCHIP_STATE_MASKED:
257 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
264 gic_poke_irq(d, reg);
268 static int gic_irq_get_irqchip_state(struct irq_data *d,
269 enum irqchip_irq_state which, bool *val)
272 case IRQCHIP_STATE_PENDING:
273 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
276 case IRQCHIP_STATE_ACTIVE:
277 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
280 case IRQCHIP_STATE_MASKED:
281 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
291 static int gic_set_type(struct irq_data *d, unsigned int type)
293 void __iomem *base = gic_dist_base(d);
294 unsigned int gicirq = gic_irq(d);
297 /* Interrupt configuration for SGIs can't be changed */
299 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
301 /* SPIs have restrictions on the supported types */
302 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
303 type != IRQ_TYPE_EDGE_RISING)
306 ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
307 if (ret && gicirq < 32) {
308 /* Misconfigured PPIs are usually not fatal */
309 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
316 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
318 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
319 if (cascading_gic_irq(d) || gic_irq(d) < 16)
323 irqd_set_forwarded_to_vcpu(d);
325 irqd_clr_forwarded_to_vcpu(d);
329 static int gic_retrigger(struct irq_data *data)
331 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
334 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
337 struct gic_chip_data *gic = &gic_data[0];
338 void __iomem *cpu_base = gic_data_cpu_base(gic);
341 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
342 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
344 if (unlikely(irqnr >= 1020))
347 if (static_branch_likely(&supports_deactivate_key))
348 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
352 * Ensure any shared data written by the CPU sending the IPI
353 * is read after we've read the ACK register on the GIC.
355 * Pairs with the write barrier in gic_ipi_send_mask
361 * The GIC encodes the source CPU in GICC_IAR,
362 * leading to the deactivation to fail if not
363 * written back as is to GICC_EOI. Stash the INTID
364 * away for gic_eoi_irq() to write back. This only
365 * works because we don't nest SGIs...
367 this_cpu_write(sgi_intid, irqstat);
370 handle_domain_irq(gic->domain, irqnr, regs);
374 static void gic_handle_cascade_irq(struct irq_desc *desc)
376 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
377 struct irq_chip *chip = irq_desc_get_chip(desc);
378 unsigned int cascade_irq, gic_irq;
379 unsigned long status;
381 chained_irq_enter(chip, desc);
383 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
385 gic_irq = (status & GICC_IAR_INT_ID_MASK);
386 if (gic_irq == GICC_INT_SPURIOUS)
389 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
390 if (unlikely(gic_irq < 32 || gic_irq > 1020)) {
391 handle_bad_irq(desc);
394 generic_handle_irq(cascade_irq);
398 chained_irq_exit(chip, desc);
401 static const struct irq_chip gic_chip = {
402 .irq_mask = gic_mask_irq,
403 .irq_unmask = gic_unmask_irq,
404 .irq_eoi = gic_eoi_irq,
405 .irq_set_type = gic_set_type,
406 .irq_retrigger = gic_retrigger,
407 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
408 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
409 .flags = IRQCHIP_SET_TYPE_MASKED |
410 IRQCHIP_SKIP_SET_WAKE |
411 IRQCHIP_MASK_ON_SUSPEND,
414 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
416 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
417 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
421 static u8 gic_get_cpumask(struct gic_chip_data *gic)
423 void __iomem *base = gic_data_dist_base(gic);
426 for (i = mask = 0; i < 32; i += 4) {
427 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
434 if (!mask && num_possible_cpus() > 1)
435 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
440 static bool gic_check_gicv2(void __iomem *base)
442 u32 val = readl_relaxed(base + GIC_CPU_IDENT);
443 return (val & 0xff0fff) == 0x02043B;
446 static void gic_cpu_if_up(struct gic_chip_data *gic)
448 void __iomem *cpu_base = gic_data_cpu_base(gic);
453 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
454 mode = GIC_CPU_CTRL_EOImodeNS;
456 if (gic_check_gicv2(cpu_base))
457 for (i = 0; i < 4; i++)
458 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
461 * Preserve bypass disable bits to be written back later
463 bypass = readl(cpu_base + GIC_CPU_CTRL);
464 bypass &= GICC_DIS_BYPASS_MASK;
466 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
470 static void gic_dist_init(struct gic_chip_data *gic)
474 unsigned int gic_irqs = gic->gic_irqs;
475 void __iomem *base = gic_data_dist_base(gic);
477 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
480 * Set all global interrupts to this CPU only.
482 cpumask = gic_get_cpumask(gic);
483 cpumask |= cpumask << 8;
484 cpumask |= cpumask << 16;
485 for (i = 32; i < gic_irqs; i += 4)
486 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
488 gic_dist_config(base, gic_irqs, NULL);
490 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
493 static int gic_cpu_init(struct gic_chip_data *gic)
495 void __iomem *dist_base = gic_data_dist_base(gic);
496 void __iomem *base = gic_data_cpu_base(gic);
497 unsigned int cpu_mask, cpu = smp_processor_id();
501 * Setting up the CPU map is only relevant for the primary GIC
502 * because any nested/secondary GICs do not directly interface
505 if (gic == &gic_data[0]) {
507 * Get what the GIC says our CPU mask is.
509 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
512 gic_check_cpu_features();
513 cpu_mask = gic_get_cpumask(gic);
514 gic_cpu_map[cpu] = cpu_mask;
517 * Clear our mask from the other map entries in case they're
520 for (i = 0; i < NR_GIC_CPU_IF; i++)
522 gic_cpu_map[i] &= ~cpu_mask;
525 gic_cpu_config(dist_base, 32, NULL);
527 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
533 int gic_cpu_if_down(unsigned int gic_nr)
535 void __iomem *cpu_base;
538 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
541 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
542 val = readl(cpu_base + GIC_CPU_CTRL);
544 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
549 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
551 * Saves the GIC distributor registers during suspend or idle. Must be called
552 * with interrupts disabled but before powering down the GIC. After calling
553 * this function, no interrupts will be delivered by the GIC, and another
554 * platform-specific wakeup source must be enabled.
556 void gic_dist_save(struct gic_chip_data *gic)
558 unsigned int gic_irqs;
559 void __iomem *dist_base;
565 gic_irqs = gic->gic_irqs;
566 dist_base = gic_data_dist_base(gic);
571 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
572 gic->saved_spi_conf[i] =
573 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
575 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
576 gic->saved_spi_target[i] =
577 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
579 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
580 gic->saved_spi_enable[i] =
581 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
583 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
584 gic->saved_spi_active[i] =
585 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
589 * Restores the GIC distributor registers during resume or when coming out of
590 * idle. Must be called before enabling interrupts. If a level interrupt
591 * that occurred while the GIC was suspended is still present, it will be
592 * handled normally, but any edge interrupts that occurred will not be seen by
593 * the GIC and need to be handled by the platform-specific wakeup source.
595 void gic_dist_restore(struct gic_chip_data *gic)
597 unsigned int gic_irqs;
599 void __iomem *dist_base;
604 gic_irqs = gic->gic_irqs;
605 dist_base = gic_data_dist_base(gic);
610 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
612 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
613 writel_relaxed(gic->saved_spi_conf[i],
614 dist_base + GIC_DIST_CONFIG + i * 4);
616 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
617 writel_relaxed(GICD_INT_DEF_PRI_X4,
618 dist_base + GIC_DIST_PRI + i * 4);
620 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
621 writel_relaxed(gic->saved_spi_target[i],
622 dist_base + GIC_DIST_TARGET + i * 4);
624 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
625 writel_relaxed(GICD_INT_EN_CLR_X32,
626 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
627 writel_relaxed(gic->saved_spi_enable[i],
628 dist_base + GIC_DIST_ENABLE_SET + i * 4);
631 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
632 writel_relaxed(GICD_INT_EN_CLR_X32,
633 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
634 writel_relaxed(gic->saved_spi_active[i],
635 dist_base + GIC_DIST_ACTIVE_SET + i * 4);
638 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
641 void gic_cpu_save(struct gic_chip_data *gic)
645 void __iomem *dist_base;
646 void __iomem *cpu_base;
651 dist_base = gic_data_dist_base(gic);
652 cpu_base = gic_data_cpu_base(gic);
654 if (!dist_base || !cpu_base)
657 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
658 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
659 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
661 ptr = raw_cpu_ptr(gic->saved_ppi_active);
662 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
663 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
665 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
666 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
667 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
671 void gic_cpu_restore(struct gic_chip_data *gic)
675 void __iomem *dist_base;
676 void __iomem *cpu_base;
681 dist_base = gic_data_dist_base(gic);
682 cpu_base = gic_data_cpu_base(gic);
684 if (!dist_base || !cpu_base)
687 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
688 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
689 writel_relaxed(GICD_INT_EN_CLR_X32,
690 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
691 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
694 ptr = raw_cpu_ptr(gic->saved_ppi_active);
695 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
696 writel_relaxed(GICD_INT_EN_CLR_X32,
697 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
698 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
701 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
702 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
703 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
705 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
706 writel_relaxed(GICD_INT_DEF_PRI_X4,
707 dist_base + GIC_DIST_PRI + i * 4);
709 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
713 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
717 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
720 gic_cpu_save(&gic_data[i]);
722 case CPU_PM_ENTER_FAILED:
724 gic_cpu_restore(&gic_data[i]);
726 case CPU_CLUSTER_PM_ENTER:
727 gic_dist_save(&gic_data[i]);
729 case CPU_CLUSTER_PM_ENTER_FAILED:
730 case CPU_CLUSTER_PM_EXIT:
731 gic_dist_restore(&gic_data[i]);
739 static struct notifier_block gic_notifier_block = {
740 .notifier_call = gic_notifier,
743 static int gic_pm_init(struct gic_chip_data *gic)
745 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
747 if (WARN_ON(!gic->saved_ppi_enable))
750 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
752 if (WARN_ON(!gic->saved_ppi_active))
753 goto free_ppi_enable;
755 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
757 if (WARN_ON(!gic->saved_ppi_conf))
758 goto free_ppi_active;
760 if (gic == &gic_data[0])
761 cpu_pm_register_notifier(&gic_notifier_block);
766 free_percpu(gic->saved_ppi_active);
768 free_percpu(gic->saved_ppi_enable);
773 static int gic_pm_init(struct gic_chip_data *gic)
780 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
783 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
787 cpu = cpumask_any_and(mask_val, cpu_online_mask);
789 cpu = cpumask_first(mask_val);
791 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
794 writeb_relaxed(gic_cpu_map[cpu], reg);
795 irq_data_update_effective_affinity(d, cpumask_of(cpu));
797 return IRQ_SET_MASK_OK_DONE;
800 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
803 unsigned long flags, map = 0;
805 if (unlikely(nr_cpu_ids == 1)) {
806 /* Only one CPU? let's do a self-IPI... */
807 writel_relaxed(2 << 24 | d->hwirq,
808 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
812 gic_lock_irqsave(flags);
814 /* Convert our logical CPU mask into a physical one. */
815 for_each_cpu(cpu, mask)
816 map |= gic_cpu_map[cpu];
819 * Ensure that stores to Normal memory are visible to the
820 * other CPUs before they observe us issuing the IPI.
824 /* this always happens on GIC0 */
825 writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
827 gic_unlock_irqrestore(flags);
830 static int gic_starting_cpu(unsigned int cpu)
832 gic_cpu_init(&gic_data[0]);
836 static __init void gic_smp_init(void)
838 struct irq_fwspec sgi_fwspec = {
839 .fwnode = gic_data[0].domain->fwnode,
844 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
845 "irqchip/arm/gic:starting",
846 gic_starting_cpu, NULL);
848 base_sgi = __irq_domain_alloc_irqs(gic_data[0].domain, -1, 8,
849 NUMA_NO_NODE, &sgi_fwspec,
851 if (WARN_ON(base_sgi <= 0))
854 set_smp_ipi_range(base_sgi, 8);
857 #define gic_smp_init() do { } while(0)
858 #define gic_set_affinity NULL
859 #define gic_ipi_send_mask NULL
862 #ifdef CONFIG_BL_SWITCHER
864 * gic_send_sgi - send a SGI directly to given CPU interface number
866 * cpu_id: the ID for the destination CPU interface
867 * irq: the IPI number to send a SGI for
869 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
871 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
872 cpu_id = 1 << cpu_id;
873 /* this always happens on GIC0 */
874 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
878 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
880 * @cpu: the logical CPU number to get the GIC ID for.
882 * Return the CPU interface ID for the given logical CPU number,
883 * or -1 if the CPU number is too large or the interface ID is
884 * unknown (more than one bit set).
886 int gic_get_cpu_id(unsigned int cpu)
888 unsigned int cpu_bit;
890 if (cpu >= NR_GIC_CPU_IF)
892 cpu_bit = gic_cpu_map[cpu];
893 if (cpu_bit & (cpu_bit - 1))
895 return __ffs(cpu_bit);
899 * gic_migrate_target - migrate IRQs to another CPU interface
901 * @new_cpu_id: the CPU target ID to migrate IRQs to
903 * Migrate all peripheral interrupts with a target matching the current CPU
904 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
905 * is also updated. Targets to other CPU interfaces are unchanged.
906 * This must be called with IRQs locally disabled.
908 void gic_migrate_target(unsigned int new_cpu_id)
910 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
911 void __iomem *dist_base;
912 int i, ror_val, cpu = smp_processor_id();
913 u32 val, cur_target_mask, active_mask;
915 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
917 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
920 gic_irqs = gic_data[gic_nr].gic_irqs;
922 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
923 cur_target_mask = 0x01010101 << cur_cpu_id;
924 ror_val = (cur_cpu_id - new_cpu_id) & 31;
928 /* Update the target interface for this logical CPU */
929 gic_cpu_map[cpu] = 1 << new_cpu_id;
932 * Find all the peripheral interrupts targeting the current
933 * CPU interface and migrate them to the new CPU interface.
934 * We skip DIST_TARGET 0 to 7 as they are read-only.
936 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
937 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
938 active_mask = val & cur_target_mask;
941 val |= ror32(active_mask, ror_val);
942 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
949 * Now let's migrate and clear any potential SGIs that might be
950 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
951 * is a banked register, we can only forward the SGI using
952 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
953 * doesn't use that information anyway.
955 * For the same reason we do not adjust SGI source information
956 * for previously sent SGIs by us to other CPUs either.
958 for (i = 0; i < 16; i += 4) {
960 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
963 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
964 for (j = i; j < i + 4; j++) {
966 writel_relaxed((1 << (new_cpu_id + 16)) | j,
967 dist_base + GIC_DIST_SOFTINT);
974 * gic_get_sgir_physaddr - get the physical address for the SGI register
976 * Return the physical address of the SGI register to be used
977 * by some early assembly code when the kernel is not yet available.
979 static unsigned long gic_dist_physaddr;
981 unsigned long gic_get_sgir_physaddr(void)
983 if (!gic_dist_physaddr)
985 return gic_dist_physaddr + GIC_DIST_SOFTINT;
988 static void __init gic_init_physaddr(struct device_node *node)
991 if (of_address_to_resource(node, 0, &res) == 0) {
992 gic_dist_physaddr = res.start;
993 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
998 #define gic_init_physaddr(node) do { } while (0)
1001 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1004 struct gic_chip_data *gic = d->host_data;
1005 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1009 irq_set_percpu_devid(irq);
1010 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1011 handle_percpu_devid_irq, NULL, NULL);
1014 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
1015 handle_fasteoi_irq, NULL, NULL);
1017 irqd_set_single_target(irqd);
1021 /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1022 irqd_set_handle_enforce_irqctx(irqd);
1026 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
1030 static int gic_irq_domain_translate(struct irq_domain *d,
1031 struct irq_fwspec *fwspec,
1032 unsigned long *hwirq,
1035 if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1036 *hwirq = fwspec->param[0];
1037 *type = IRQ_TYPE_EDGE_RISING;
1041 if (is_of_node(fwspec->fwnode)) {
1042 if (fwspec->param_count < 3)
1045 switch (fwspec->param[0]) {
1047 *hwirq = fwspec->param[1] + 32;
1050 *hwirq = fwspec->param[1] + 16;
1056 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1058 /* Make it clear that broken DTs are... broken */
1059 WARN_ON(*type == IRQ_TYPE_NONE);
1063 if (is_fwnode_irqchip(fwspec->fwnode)) {
1064 if(fwspec->param_count != 2)
1067 *hwirq = fwspec->param[0];
1068 *type = fwspec->param[1];
1070 WARN_ON(*type == IRQ_TYPE_NONE);
1077 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1078 unsigned int nr_irqs, void *arg)
1081 irq_hw_number_t hwirq;
1082 unsigned int type = IRQ_TYPE_NONE;
1083 struct irq_fwspec *fwspec = arg;
1085 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1089 for (i = 0; i < nr_irqs; i++) {
1090 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1098 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1099 .translate = gic_irq_domain_translate,
1100 .alloc = gic_irq_domain_alloc,
1101 .free = irq_domain_free_irqs_top,
1104 static const struct irq_domain_ops gic_irq_domain_ops = {
1105 .map = gic_irq_domain_map,
1106 .unmap = gic_irq_domain_unmap,
1109 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1110 const char *name, bool use_eoimode1)
1112 /* Initialize irq_chip */
1113 gic->chip = gic_chip;
1114 gic->chip.name = name;
1115 gic->chip.parent_device = dev;
1118 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1119 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1120 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1123 if (gic == &gic_data[0]) {
1124 gic->chip.irq_set_affinity = gic_set_affinity;
1125 gic->chip.ipi_send_mask = gic_ipi_send_mask;
1129 static int gic_init_bases(struct gic_chip_data *gic,
1130 struct fwnode_handle *handle)
1134 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1135 /* Frankein-GIC without banked registers... */
1138 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1139 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1140 if (WARN_ON(!gic->dist_base.percpu_base ||
1141 !gic->cpu_base.percpu_base)) {
1146 for_each_possible_cpu(cpu) {
1147 u32 mpidr = cpu_logical_map(cpu);
1148 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1149 unsigned long offset = gic->percpu_offset * core_id;
1150 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1151 gic->raw_dist_base + offset;
1152 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1153 gic->raw_cpu_base + offset;
1156 enable_frankengic();
1158 /* Normal, sane GIC... */
1159 WARN(gic->percpu_offset,
1160 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1161 gic->percpu_offset);
1162 gic->dist_base.common_base = gic->raw_dist_base;
1163 gic->cpu_base.common_base = gic->raw_cpu_base;
1167 * Find out how many interrupts are supported.
1168 * The GIC only supports up to 1020 interrupt sources.
1170 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1171 gic_irqs = (gic_irqs + 1) * 32;
1172 if (gic_irqs > 1020)
1174 gic->gic_irqs = gic_irqs;
1176 if (handle) { /* DT/ACPI */
1177 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1178 &gic_irq_domain_hierarchy_ops,
1180 } else { /* Legacy support */
1182 * For primary GICs, skip over SGIs.
1183 * No secondary GIC support whatsoever.
1187 gic_irqs -= 16; /* calculate # of irqs to allocate */
1189 irq_base = irq_alloc_descs(16, 16, gic_irqs,
1192 WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
1196 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1197 16, &gic_irq_domain_ops, gic);
1200 if (WARN_ON(!gic->domain)) {
1206 ret = gic_cpu_init(gic);
1210 ret = gic_pm_init(gic);
1217 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1218 free_percpu(gic->dist_base.percpu_base);
1219 free_percpu(gic->cpu_base.percpu_base);
1225 static int __init __gic_init_bases(struct gic_chip_data *gic,
1226 struct fwnode_handle *handle)
1231 if (WARN_ON(!gic || gic->domain))
1234 if (gic == &gic_data[0]) {
1236 * Initialize the CPU interface map to all CPUs.
1237 * It will be refined as each CPU probes its ID.
1238 * This is only necessary for the primary GIC.
1240 for (i = 0; i < NR_GIC_CPU_IF; i++)
1241 gic_cpu_map[i] = 0xff;
1243 set_handle_irq(gic_handle_irq);
1244 if (static_branch_likely(&supports_deactivate_key))
1245 pr_info("GIC: Using split EOI/Deactivate mode\n");
1248 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {
1249 name = kasprintf(GFP_KERNEL, "GICv2");
1250 gic_init_chip(gic, NULL, name, true);
1252 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1253 gic_init_chip(gic, NULL, name, false);
1256 ret = gic_init_bases(gic, handle);
1259 else if (gic == &gic_data[0])
1265 void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
1267 struct gic_chip_data *gic;
1270 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1271 * bother with these...
1273 static_branch_disable(&supports_deactivate_key);
1276 gic->raw_dist_base = dist_base;
1277 gic->raw_cpu_base = cpu_base;
1279 __gic_init_bases(gic, NULL);
1282 static void gic_teardown(struct gic_chip_data *gic)
1287 if (gic->raw_dist_base)
1288 iounmap(gic->raw_dist_base);
1289 if (gic->raw_cpu_base)
1290 iounmap(gic->raw_cpu_base);
1294 static int gic_cnt __initdata;
1295 static bool gicv2_force_probe;
1297 static int __init gicv2_force_probe_cfg(char *buf)
1299 return strtobool(buf, &gicv2_force_probe);
1301 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
1303 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1305 struct resource cpuif_res;
1307 of_address_to_resource(node, 1, &cpuif_res);
1309 if (!is_hyp_mode_available())
1311 if (resource_size(&cpuif_res) < SZ_8K) {
1314 * Check for a stupid firmware that only exposes the
1315 * first page of a GICv2.
1317 if (!gic_check_gicv2(*base))
1320 if (!gicv2_force_probe) {
1321 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
1325 alt = ioremap(cpuif_res.start, SZ_8K);
1328 if (!gic_check_gicv2(alt + SZ_4K)) {
1330 * The first page was that of a GICv2, and
1331 * the second was *something*. Let's trust it
1332 * to be a GICv2, and update the mapping.
1334 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
1342 * We detected *two* initial GICv2 pages in a
1343 * row. Could be a GICv2 aliased over two 64kB
1344 * pages. Update the resource, map the iospace, and
1348 alt = ioremap(cpuif_res.start, SZ_128K);
1351 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
1353 cpuif_res.end = cpuif_res.start + SZ_128K -1;
1357 if (resource_size(&cpuif_res) == SZ_128K) {
1359 * Verify that we have the first 4kB of a GICv2
1360 * aliased over the first 64kB by checking the
1361 * GICC_IIDR register on both ends.
1363 if (!gic_check_gicv2(*base) ||
1364 !gic_check_gicv2(*base + 0xf000))
1368 * Move the base up by 60kB, so that we have a 8kB
1369 * contiguous region, which allows us to use GICC_DIR
1370 * at its normal offset. Please pass me that bucket.
1373 cpuif_res.start += 0xf000;
1374 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1381 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1386 gic->raw_dist_base = of_iomap(node, 0);
1387 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1390 gic->raw_cpu_base = of_iomap(node, 1);
1391 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1394 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1395 gic->percpu_offset = 0;
1405 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1409 if (!dev || !dev->of_node || !gic || !irq)
1412 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1416 gic_init_chip(*gic, dev, dev->of_node->name, false);
1418 ret = gic_of_setup(*gic, dev->of_node);
1422 ret = gic_init_bases(*gic, &dev->of_node->fwnode);
1428 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1433 static void __init gic_of_setup_kvm_info(struct device_node *node)
1436 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1437 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1439 gic_v2_kvm_info.type = GIC_V2;
1441 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1442 if (!gic_v2_kvm_info.maint_irq)
1445 ret = of_address_to_resource(node, 2, vctrl_res);
1449 ret = of_address_to_resource(node, 3, vcpu_res);
1453 if (static_branch_likely(&supports_deactivate_key))
1454 gic_set_kvm_info(&gic_v2_kvm_info);
1458 gic_of_init(struct device_node *node, struct device_node *parent)
1460 struct gic_chip_data *gic;
1466 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1469 gic = &gic_data[gic_cnt];
1471 ret = gic_of_setup(gic, node);
1476 * Disable split EOI/Deactivate if either HYP is not available
1477 * or the CPU interface is too small.
1479 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1480 static_branch_disable(&supports_deactivate_key);
1482 ret = __gic_init_bases(gic, &node->fwnode);
1489 gic_init_physaddr(node);
1490 gic_of_setup_kvm_info(node);
1494 irq = irq_of_parse_and_map(node, 0);
1495 gic_cascade_irq(gic_cnt, irq);
1498 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1499 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1504 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1505 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1506 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1507 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1508 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1509 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1510 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1511 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1512 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1514 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1523 phys_addr_t cpu_phys_base;
1526 phys_addr_t vctrl_base;
1527 phys_addr_t vcpu_base;
1528 } acpi_data __initdata;
1531 gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header,
1532 const unsigned long end)
1534 struct acpi_madt_generic_interrupt *processor;
1535 phys_addr_t gic_cpu_base;
1536 static int cpu_base_assigned;
1538 processor = (struct acpi_madt_generic_interrupt *)header;
1540 if (BAD_MADT_GICC_ENTRY(processor, end))
1544 * There is no support for non-banked GICv1/2 register in ACPI spec.
1545 * All CPU interface addresses have to be the same.
1547 gic_cpu_base = processor->base_address;
1548 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1551 acpi_data.cpu_phys_base = gic_cpu_base;
1552 acpi_data.maint_irq = processor->vgic_interrupt;
1553 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1554 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1555 acpi_data.vctrl_base = processor->gich_base_address;
1556 acpi_data.vcpu_base = processor->gicv_base_address;
1558 cpu_base_assigned = 1;
1562 /* The things you have to do to just *count* something... */
1563 static int __init acpi_dummy_func(union acpi_subtable_headers *header,
1564 const unsigned long end)
1569 static bool __init acpi_gic_redist_is_present(void)
1571 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1572 acpi_dummy_func, 0) > 0;
1575 static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1576 struct acpi_probe_entry *ape)
1578 struct acpi_madt_generic_distributor *dist;
1579 dist = (struct acpi_madt_generic_distributor *)header;
1581 return (dist->version == ape->driver_data &&
1582 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1583 !acpi_gic_redist_is_present()));
1586 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1587 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
1588 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1589 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1591 static void __init gic_acpi_setup_kvm_info(void)
1594 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1595 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1597 gic_v2_kvm_info.type = GIC_V2;
1599 if (!acpi_data.vctrl_base)
1602 vctrl_res->flags = IORESOURCE_MEM;
1603 vctrl_res->start = acpi_data.vctrl_base;
1604 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1606 if (!acpi_data.vcpu_base)
1609 vcpu_res->flags = IORESOURCE_MEM;
1610 vcpu_res->start = acpi_data.vcpu_base;
1611 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1613 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1614 acpi_data.maint_irq_mode,
1619 gic_v2_kvm_info.maint_irq = irq;
1621 gic_set_kvm_info(&gic_v2_kvm_info);
1624 static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
1625 const unsigned long end)
1627 struct acpi_madt_generic_distributor *dist;
1628 struct fwnode_handle *domain_handle;
1629 struct gic_chip_data *gic = &gic_data[0];
1632 /* Collect CPU base addresses */
1633 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1634 gic_acpi_parse_madt_cpu, 0);
1636 pr_err("No valid GICC entries exist\n");
1640 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1641 if (!gic->raw_cpu_base) {
1642 pr_err("Unable to map GICC registers\n");
1646 dist = (struct acpi_madt_generic_distributor *)header;
1647 gic->raw_dist_base = ioremap(dist->base_address,
1648 ACPI_GICV2_DIST_MEM_SIZE);
1649 if (!gic->raw_dist_base) {
1650 pr_err("Unable to map GICD registers\n");
1656 * Disable split EOI/Deactivate if HYP is not available. ACPI
1657 * guarantees that we'll always have a GICv2, so the CPU
1658 * interface will always be the right size.
1660 if (!is_hyp_mode_available())
1661 static_branch_disable(&supports_deactivate_key);
1664 * Initialize GIC instance zero (no multi-GIC support).
1666 domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
1667 if (!domain_handle) {
1668 pr_err("Unable to allocate domain handle\n");
1673 ret = __gic_init_bases(gic, domain_handle);
1675 pr_err("Failed to initialise GIC\n");
1676 irq_domain_free_fwnode(domain_handle);
1681 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1683 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1684 gicv2m_init(NULL, gic_data[0].domain);
1686 if (static_branch_likely(&supports_deactivate_key))
1687 gic_acpi_setup_kvm_info();
1691 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1692 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1694 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1695 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,