1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 #define pr_fmt(fmt) "GICv3: " fmt
9 #include <linux/acpi.h>
10 #include <linux/cpu.h>
11 #include <linux/cpu_pm.h>
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqdomain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/percpu.h>
19 #include <linux/refcount.h>
20 #include <linux/slab.h>
22 #include <linux/irqchip.h>
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
27 #include <asm/cputype.h>
28 #include <asm/exception.h>
29 #include <asm/smp_plat.h>
32 #include "irq-gic-common.h"
34 #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
36 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
37 #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
39 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
41 struct redist_region {
42 void __iomem *redist_base;
43 phys_addr_t phys_base;
47 struct gic_chip_data {
48 struct fwnode_handle *fwnode;
49 void __iomem *dist_base;
50 struct redist_region *redist_regions;
52 struct irq_domain *domain;
54 u32 nr_redist_regions;
58 struct partition_desc **ppi_descs;
61 static struct gic_chip_data gic_data __read_mostly;
62 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
64 #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
65 #define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
66 #define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
69 * The behaviours of RPR and PMR registers differ depending on the value of
70 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
71 * distributor and redistributors depends on whether security is enabled in the
74 * When security is enabled, non-secure priority values from the (re)distributor
75 * are presented to the GIC CPUIF as follow:
76 * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80;
78 * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure
79 * EL1 are subject to a similar operation thus matching the priorities presented
80 * from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0,
81 * these values are unchanged by the GIC.
83 * see GICv3/GICv4 Architecture Specification (IHI0069D):
84 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
86 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
89 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
92 * Global static key controlling whether an update to PMR allowing more
93 * interrupts requires to be propagated to the redistributor (DSB SY).
94 * And this needs to be exported for modules to be able to enable
97 DEFINE_STATIC_KEY_FALSE(gic_pmr_sync);
98 EXPORT_SYMBOL(gic_pmr_sync);
100 DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
101 EXPORT_SYMBOL(gic_nonsecure_priorities);
104 * When the Non-secure world has access to group 0 interrupts (as a
105 * consequence of SCR_EL3.FIQ == 0), reading the ICC_RPR_EL1 register will
106 * return the Distributor's view of the interrupt priority.
108 * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority
109 * written by software is moved to the Non-secure range by the Distributor.
111 * If both are true (which is when gic_nonsecure_priorities gets enabled),
112 * we need to shift down the priority programmed by software to match it
113 * against the value returned by ICC_RPR_EL1.
115 #define GICD_INT_RPR_PRI(priority) \
117 u32 __priority = (priority); \
118 if (static_branch_unlikely(&gic_nonsecure_priorities)) \
119 __priority = 0x80 | (__priority >> 1); \
124 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
125 static refcount_t *ppi_nmi_refs;
127 static struct gic_kvm_info gic_v3_kvm_info __initdata;
128 static DEFINE_PER_CPU(bool, has_rss);
130 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4)
131 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
132 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
133 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
135 /* Our default, arbitrary priority value. Linux only uses one anyway. */
136 #define DEFAULT_PMR_VALUE 0xf0
138 enum gic_intid_range {
148 static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
157 case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63):
159 case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
161 case 8192 ... GENMASK(23, 0):
164 return __INVALID_RANGE__;
168 static enum gic_intid_range get_intid_range(struct irq_data *d)
170 return __get_intid_range(d->hwirq);
173 static inline unsigned int gic_irq(struct irq_data *d)
178 static inline bool gic_irq_in_rdist(struct irq_data *d)
180 switch (get_intid_range(d)) {
190 static inline void __iomem *gic_dist_base(struct irq_data *d)
192 switch (get_intid_range(d)) {
196 /* SGI+PPI -> SGI_base for this CPU */
197 return gic_data_rdist_sgi_base();
201 /* SPI -> dist_base */
202 return gic_data.dist_base;
209 static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
211 u32 count = 1000000; /* 1s! */
213 while (readl_relaxed(base + GICD_CTLR) & bit) {
216 pr_err_ratelimited("RWP timeout, gone fishing\n");
224 /* Wait for completion of a distributor change */
225 static void gic_dist_wait_for_rwp(void)
227 gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
230 /* Wait for completion of a redistributor change */
231 static void gic_redist_wait_for_rwp(void)
233 gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
238 static u64 __maybe_unused gic_read_iar(void)
240 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
241 return gic_read_iar_cavium_thunderx();
243 return gic_read_iar_common();
247 static void gic_enable_redist(bool enable)
250 u32 count = 1000000; /* 1s! */
253 if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
256 rbase = gic_data_rdist_rd_base();
258 val = readl_relaxed(rbase + GICR_WAKER);
260 /* Wake up this CPU redistributor */
261 val &= ~GICR_WAKER_ProcessorSleep;
263 val |= GICR_WAKER_ProcessorSleep;
264 writel_relaxed(val, rbase + GICR_WAKER);
266 if (!enable) { /* Check that GICR_WAKER is writeable */
267 val = readl_relaxed(rbase + GICR_WAKER);
268 if (!(val & GICR_WAKER_ProcessorSleep))
269 return; /* No PM support in this redistributor */
273 val = readl_relaxed(rbase + GICR_WAKER);
274 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
280 pr_err_ratelimited("redistributor failed to %s...\n",
281 enable ? "wakeup" : "sleep");
285 * Routines to disable, enable, EOI and route interrupts
287 static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
289 switch (get_intid_range(d)) {
297 * Contrary to the ESPI range, the EPPI range is contiguous
298 * to the PPI range in the registers, so let's adjust the
299 * displacement accordingly. Consistency is overrated.
301 *index = d->hwirq - EPPI_BASE_INTID + 32;
304 *index = d->hwirq - ESPI_BASE_INTID;
307 return GICD_ISENABLERnE;
309 return GICD_ICENABLERnE;
311 return GICD_ISPENDRnE;
313 return GICD_ICPENDRnE;
315 return GICD_ISACTIVERnE;
317 return GICD_ICACTIVERnE;
318 case GICD_IPRIORITYR:
319 return GICD_IPRIORITYRnE;
323 return GICD_IROUTERnE;
337 static int gic_peek_irq(struct irq_data *d, u32 offset)
342 offset = convert_offset_index(d, offset, &index);
343 mask = 1 << (index % 32);
345 if (gic_irq_in_rdist(d))
346 base = gic_data_rdist_sgi_base();
348 base = gic_data.dist_base;
350 return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
353 static void gic_poke_irq(struct irq_data *d, u32 offset)
358 offset = convert_offset_index(d, offset, &index);
359 mask = 1 << (index % 32);
361 if (gic_irq_in_rdist(d))
362 base = gic_data_rdist_sgi_base();
364 base = gic_data.dist_base;
366 writel_relaxed(mask, base + offset + (index / 32) * 4);
369 static void gic_mask_irq(struct irq_data *d)
371 gic_poke_irq(d, GICD_ICENABLER);
372 if (gic_irq_in_rdist(d))
373 gic_redist_wait_for_rwp();
375 gic_dist_wait_for_rwp();
378 static void gic_eoimode1_mask_irq(struct irq_data *d)
382 * When masking a forwarded interrupt, make sure it is
383 * deactivated as well.
385 * This ensures that an interrupt that is getting
386 * disabled/masked will not get "stuck", because there is
387 * noone to deactivate it (guest is being terminated).
389 if (irqd_is_forwarded_to_vcpu(d))
390 gic_poke_irq(d, GICD_ICACTIVER);
393 static void gic_unmask_irq(struct irq_data *d)
395 gic_poke_irq(d, GICD_ISENABLER);
398 static inline bool gic_supports_nmi(void)
400 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
401 static_branch_likely(&supports_pseudo_nmis);
404 static int gic_irq_set_irqchip_state(struct irq_data *d,
405 enum irqchip_irq_state which, bool val)
409 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */
413 case IRQCHIP_STATE_PENDING:
414 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
417 case IRQCHIP_STATE_ACTIVE:
418 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
421 case IRQCHIP_STATE_MASKED:
426 reg = GICD_ISENABLER;
433 gic_poke_irq(d, reg);
437 static int gic_irq_get_irqchip_state(struct irq_data *d,
438 enum irqchip_irq_state which, bool *val)
440 if (d->hwirq >= 8192) /* PPI/SPI only */
444 case IRQCHIP_STATE_PENDING:
445 *val = gic_peek_irq(d, GICD_ISPENDR);
448 case IRQCHIP_STATE_ACTIVE:
449 *val = gic_peek_irq(d, GICD_ISACTIVER);
452 case IRQCHIP_STATE_MASKED:
453 *val = !gic_peek_irq(d, GICD_ISENABLER);
463 static void gic_irq_set_prio(struct irq_data *d, u8 prio)
465 void __iomem *base = gic_dist_base(d);
468 offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
470 writeb_relaxed(prio, base + offset + index);
473 static u32 __gic_get_ppi_index(irq_hw_number_t hwirq)
475 switch (__get_intid_range(hwirq)) {
479 return hwirq - EPPI_BASE_INTID + 16;
485 static u32 gic_get_ppi_index(struct irq_data *d)
487 return __gic_get_ppi_index(d->hwirq);
490 static int gic_irq_nmi_setup(struct irq_data *d)
492 struct irq_desc *desc = irq_to_desc(d->irq);
494 if (!gic_supports_nmi())
497 if (gic_peek_irq(d, GICD_ISENABLER)) {
498 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
503 * A secondary irq_chip should be in charge of LPI request,
504 * it should not be possible to get there
506 if (WARN_ON(gic_irq(d) >= 8192))
509 /* desc lock should already be held */
510 if (gic_irq_in_rdist(d)) {
511 u32 idx = gic_get_ppi_index(d);
513 /* Setting up PPI as NMI, only switch handler for first NMI */
514 if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
515 refcount_set(&ppi_nmi_refs[idx], 1);
516 desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
519 desc->handle_irq = handle_fasteoi_nmi;
522 gic_irq_set_prio(d, GICD_INT_NMI_PRI);
527 static void gic_irq_nmi_teardown(struct irq_data *d)
529 struct irq_desc *desc = irq_to_desc(d->irq);
531 if (WARN_ON(!gic_supports_nmi()))
534 if (gic_peek_irq(d, GICD_ISENABLER)) {
535 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
540 * A secondary irq_chip should be in charge of LPI request,
541 * it should not be possible to get there
543 if (WARN_ON(gic_irq(d) >= 8192))
546 /* desc lock should already be held */
547 if (gic_irq_in_rdist(d)) {
548 u32 idx = gic_get_ppi_index(d);
550 /* Tearing down NMI, only switch handler for last NMI */
551 if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
552 desc->handle_irq = handle_percpu_devid_irq;
554 desc->handle_irq = handle_fasteoi_irq;
557 gic_irq_set_prio(d, GICD_INT_DEF_PRI);
560 static void gic_eoi_irq(struct irq_data *d)
562 write_gicreg(gic_irq(d), ICC_EOIR1_EL1);
566 static void gic_eoimode1_eoi_irq(struct irq_data *d)
569 * No need to deactivate an LPI, or an interrupt that
570 * is is getting forwarded to a vcpu.
572 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
574 gic_write_dir(gic_irq(d));
577 static int gic_set_type(struct irq_data *d, unsigned int type)
579 enum gic_intid_range range;
580 unsigned int irq = gic_irq(d);
585 range = get_intid_range(d);
587 /* Interrupt configuration for SGIs can't be changed */
588 if (range == SGI_RANGE)
589 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
591 /* SPIs have restrictions on the supported types */
592 if ((range == SPI_RANGE || range == ESPI_RANGE) &&
593 type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
596 if (gic_irq_in_rdist(d))
597 base = gic_data_rdist_sgi_base();
599 base = gic_data.dist_base;
601 offset = convert_offset_index(d, GICD_ICFGR, &index);
603 ret = gic_configure_irq(index, type, base + offset, NULL);
604 if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
605 /* Misconfigured PPIs are usually not fatal */
606 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
613 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
615 if (get_intid_range(d) == SGI_RANGE)
619 irqd_set_forwarded_to_vcpu(d);
621 irqd_clr_forwarded_to_vcpu(d);
625 static u64 gic_mpidr_to_affinity(unsigned long mpidr)
629 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
630 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
631 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
632 MPIDR_AFFINITY_LEVEL(mpidr, 0));
637 static void gic_deactivate_unhandled(u32 irqnr)
639 if (static_branch_likely(&supports_deactivate_key)) {
641 gic_write_dir(irqnr);
643 write_gicreg(irqnr, ICC_EOIR1_EL1);
649 * Follow a read of the IAR with any HW maintenance that needs to happen prior
650 * to invoking the relevant IRQ handler. We must do two things:
652 * (1) Ensure instruction ordering between a read of IAR and subsequent
653 * instructions in the IRQ handler using an ISB.
655 * It is possible for the IAR to report an IRQ which was signalled *after*
656 * the CPU took an IRQ exception as multiple interrupts can race to be
657 * recognized by the GIC, earlier interrupts could be withdrawn, and/or
658 * later interrupts could be prioritized by the GIC.
660 * For devices which are tightly coupled to the CPU, such as PMUs, a
661 * context synchronization event is necessary to ensure that system
662 * register state is not stale, as these may have been indirectly written
663 * *after* exception entry.
665 * (2) Deactivate the interrupt when EOI mode 1 is in use.
667 static inline void gic_complete_ack(u32 irqnr)
669 if (static_branch_likely(&supports_deactivate_key))
670 write_gicreg(irqnr, ICC_EOIR1_EL1);
675 static bool gic_rpr_is_nmi_prio(void)
677 if (!gic_supports_nmi())
680 return unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI));
683 static bool gic_irqnr_is_special(u32 irqnr)
685 return irqnr >= 1020 && irqnr <= 1023;
688 static void __gic_handle_irq(u32 irqnr, struct pt_regs *regs)
690 if (gic_irqnr_is_special(irqnr))
693 gic_complete_ack(irqnr);
695 if (generic_handle_domain_irq(gic_data.domain, irqnr)) {
696 WARN_ONCE(true, "Unexpected interrupt (irqnr %u)\n", irqnr);
697 gic_deactivate_unhandled(irqnr);
701 static void __gic_handle_nmi(u32 irqnr, struct pt_regs *regs)
703 if (gic_irqnr_is_special(irqnr))
706 gic_complete_ack(irqnr);
708 if (generic_handle_domain_nmi(gic_data.domain, irqnr)) {
709 WARN_ONCE(true, "Unexpected pseudo-NMI (irqnr %u)\n", irqnr);
710 gic_deactivate_unhandled(irqnr);
715 * An exception has been taken from a context with IRQs enabled, and this could
716 * be an IRQ or an NMI.
718 * The entry code called us with DAIF.IF set to keep NMIs masked. We must clear
719 * DAIF.IF (and update ICC_PMR_EL1 to mask regular IRQs) prior to returning,
720 * after handling any NMI but before handling any IRQ.
722 * The entry code has performed IRQ entry, and if an NMI is detected we must
723 * perform NMI entry/exit around invoking the handler.
725 static void __gic_handle_irq_from_irqson(struct pt_regs *regs)
730 irqnr = gic_read_iar();
732 is_nmi = gic_rpr_is_nmi_prio();
736 __gic_handle_nmi(irqnr, regs);
740 if (gic_prio_masking_enabled()) {
742 gic_arch_enable_irqs();
746 __gic_handle_irq(irqnr, regs);
750 * An exception has been taken from a context with IRQs disabled, which can only
753 * The entry code called us with DAIF.IF set to keep NMIs masked. We must leave
754 * DAIF.IF (and ICC_PMR_EL1) unchanged.
756 * The entry code has performed NMI entry.
758 static void __gic_handle_irq_from_irqsoff(struct pt_regs *regs)
764 * We were in a context with IRQs disabled. However, the
765 * entry code has set PMR to a value that allows any
766 * interrupt to be acknowledged, and not just NMIs. This can
767 * lead to surprising effects if the NMI has been retired in
768 * the meantime, and that there is an IRQ pending. The IRQ
769 * would then be taken in NMI context, something that nobody
770 * wants to debug twice.
772 * Until we sort this, drop PMR again to a level that will
773 * actually only allow NMIs before reading IAR, and then
774 * restore it to what it was.
776 pmr = gic_read_pmr();
779 irqnr = gic_read_iar();
782 __gic_handle_nmi(irqnr, regs);
785 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
787 if (unlikely(gic_supports_nmi() && !interrupts_enabled(regs)))
788 __gic_handle_irq_from_irqsoff(regs);
790 __gic_handle_irq_from_irqson(regs);
793 static u32 gic_get_pribits(void)
797 pribits = gic_read_ctlr();
798 pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
799 pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
805 static bool gic_has_group0(void)
810 old_pmr = gic_read_pmr();
813 * Let's find out if Group0 is under control of EL3 or not by
814 * setting the highest possible, non-zero priority in PMR.
816 * If SCR_EL3.FIQ is set, the priority gets shifted down in
817 * order for the CPU interface to set bit 7, and keep the
818 * actual priority in the non-secure range. In the process, it
819 * looses the least significant bit and the actual priority
820 * becomes 0x80. Reading it back returns 0, indicating that
821 * we're don't have access to Group0.
823 gic_write_pmr(BIT(8 - gic_get_pribits()));
824 val = gic_read_pmr();
826 gic_write_pmr(old_pmr);
831 static void __init gic_dist_init(void)
835 void __iomem *base = gic_data.dist_base;
838 /* Disable the distributor */
839 writel_relaxed(0, base + GICD_CTLR);
840 gic_dist_wait_for_rwp();
843 * Configure SPIs as non-secure Group-1. This will only matter
844 * if the GIC only has a single security state. This will not
845 * do the right thing if the kernel is running in secure mode,
846 * but that's not the intended use case anyway.
848 for (i = 32; i < GIC_LINE_NR; i += 32)
849 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
851 /* Extended SPI range, not handled by the GICv2/GICv3 common code */
852 for (i = 0; i < GIC_ESPI_NR; i += 32) {
853 writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
854 writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
857 for (i = 0; i < GIC_ESPI_NR; i += 32)
858 writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
860 for (i = 0; i < GIC_ESPI_NR; i += 16)
861 writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
863 for (i = 0; i < GIC_ESPI_NR; i += 4)
864 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
866 /* Now do the common stuff */
867 gic_dist_config(base, GIC_LINE_NR, NULL);
869 val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1;
870 if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) {
871 pr_info("Enabling SGIs without active state\n");
872 val |= GICD_CTLR_nASSGIreq;
875 /* Enable distributor with ARE, Group1, and wait for it to drain */
876 writel_relaxed(val, base + GICD_CTLR);
877 gic_dist_wait_for_rwp();
880 * Set all global interrupts to the boot CPU only. ARE must be
883 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
884 for (i = 32; i < GIC_LINE_NR; i++)
885 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
887 for (i = 0; i < GIC_ESPI_NR; i++)
888 gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
891 static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
896 for (i = 0; i < gic_data.nr_redist_regions; i++) {
897 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
901 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
902 if (reg != GIC_PIDR2_ARCH_GICv3 &&
903 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
904 pr_warn("No redistributor present @%p\n", ptr);
909 typer = gic_read_typer(ptr + GICR_TYPER);
910 ret = fn(gic_data.redist_regions + i, ptr);
914 if (gic_data.redist_regions[i].single_redist)
917 if (gic_data.redist_stride) {
918 ptr += gic_data.redist_stride;
920 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
921 if (typer & GICR_TYPER_VLPIS)
922 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
924 } while (!(typer & GICR_TYPER_LAST));
927 return ret ? -ENODEV : 0;
930 static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
932 unsigned long mpidr = cpu_logical_map(smp_processor_id());
937 * Convert affinity to a 32bit value that can be matched to
938 * GICR_TYPER bits [63:32].
940 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
941 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
942 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
943 MPIDR_AFFINITY_LEVEL(mpidr, 0));
945 typer = gic_read_typer(ptr + GICR_TYPER);
946 if ((typer >> 32) == aff) {
947 u64 offset = ptr - region->redist_base;
948 raw_spin_lock_init(&gic_data_rdist()->rd_lock);
949 gic_data_rdist_rd_base() = ptr;
950 gic_data_rdist()->phys_base = region->phys_base + offset;
952 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
953 smp_processor_id(), mpidr,
954 (int)(region - gic_data.redist_regions),
955 &gic_data_rdist()->phys_base);
963 static int gic_populate_rdist(void)
965 if (gic_iterate_rdists(__gic_populate_rdist) == 0)
968 /* We couldn't even deal with ourselves... */
969 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
971 (unsigned long)cpu_logical_map(smp_processor_id()));
975 static int __gic_update_rdist_properties(struct redist_region *region,
978 u64 typer = gic_read_typer(ptr + GICR_TYPER);
979 u32 ctlr = readl_relaxed(ptr + GICR_CTLR);
981 /* Boot-time cleanip */
982 if ((typer & GICR_TYPER_VLPIS) && (typer & GICR_TYPER_RVPEID)) {
985 /* Deactivate any present vPE */
986 val = gicr_read_vpendbaser(ptr + SZ_128K + GICR_VPENDBASER);
987 if (val & GICR_VPENDBASER_Valid)
988 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
989 ptr + SZ_128K + GICR_VPENDBASER);
991 /* Mark the VPE table as invalid */
992 val = gicr_read_vpropbaser(ptr + SZ_128K + GICR_VPROPBASER);
993 val &= ~GICR_VPROPBASER_4_1_VALID;
994 gicr_write_vpropbaser(val, ptr + SZ_128K + GICR_VPROPBASER);
997 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
1000 * TYPER.RVPEID implies some form of DirectLPI, no matter what the
1001 * doc says... :-/ And CTLR.IR implies another subset of DirectLPI
1002 * that the ITS driver can make use of for LPIs (and not VLPIs).
1004 * These are 3 different ways to express the same thing, depending
1005 * on the revision of the architecture and its relaxations over
1006 * time. Just group them under the 'direct_lpi' banner.
1008 gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID);
1009 gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) |
1010 !!(ctlr & GICR_CTLR_IR) |
1011 gic_data.rdists.has_rvpeid);
1012 gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY);
1014 /* Detect non-sensical configurations */
1015 if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) {
1016 gic_data.rdists.has_direct_lpi = false;
1017 gic_data.rdists.has_vlpis = false;
1018 gic_data.rdists.has_rvpeid = false;
1021 gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr);
1026 static void gic_update_rdist_properties(void)
1028 gic_data.ppi_nr = UINT_MAX;
1029 gic_iterate_rdists(__gic_update_rdist_properties);
1030 if (WARN_ON(gic_data.ppi_nr == UINT_MAX))
1031 gic_data.ppi_nr = 0;
1032 pr_info("GICv3 features: %d PPIs%s%s\n",
1034 gic_data.has_rss ? ", RSS" : "",
1035 gic_data.rdists.has_direct_lpi ? ", DirectLPI" : "");
1037 if (gic_data.rdists.has_vlpis)
1038 pr_info("GICv4 features: %s%s%s\n",
1039 gic_data.rdists.has_direct_lpi ? "DirectLPI " : "",
1040 gic_data.rdists.has_rvpeid ? "RVPEID " : "",
1041 gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : "");
1044 /* Check whether it's single security state view */
1045 static inline bool gic_dist_security_disabled(void)
1047 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
1050 static void gic_cpu_sys_reg_init(void)
1052 int i, cpu = smp_processor_id();
1053 u64 mpidr = cpu_logical_map(cpu);
1054 u64 need_rss = MPIDR_RS(mpidr);
1059 * Need to check that the SRE bit has actually been set. If
1060 * not, it means that SRE is disabled at EL2. We're going to
1061 * die painfully, and there is nothing we can do about it.
1063 * Kindly inform the luser.
1065 if (!gic_enable_sre())
1066 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
1068 pribits = gic_get_pribits();
1070 group0 = gic_has_group0();
1072 /* Set priority mask register */
1073 if (!gic_prio_masking_enabled()) {
1074 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
1075 } else if (gic_supports_nmi()) {
1077 * Mismatch configuration with boot CPU, the system is likely
1078 * to die as interrupt masking will not work properly on all
1081 * The boot CPU calls this function before enabling NMI support,
1082 * and as a result we'll never see this warning in the boot path
1085 if (static_branch_unlikely(&gic_nonsecure_priorities))
1086 WARN_ON(!group0 || gic_dist_security_disabled());
1088 WARN_ON(group0 && !gic_dist_security_disabled());
1092 * Some firmwares hand over to the kernel with the BPR changed from
1093 * its reset value (and with a value large enough to prevent
1094 * any pre-emptive interrupts from working at all). Writing a zero
1095 * to BPR restores is reset value.
1099 if (static_branch_likely(&supports_deactivate_key)) {
1100 /* EOI drops priority only (mode 1) */
1101 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
1103 /* EOI deactivates interrupt too (mode 0) */
1104 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
1107 /* Always whack Group0 before Group1 */
1112 write_gicreg(0, ICC_AP0R3_EL1);
1113 write_gicreg(0, ICC_AP0R2_EL1);
1116 write_gicreg(0, ICC_AP0R1_EL1);
1120 write_gicreg(0, ICC_AP0R0_EL1);
1129 write_gicreg(0, ICC_AP1R3_EL1);
1130 write_gicreg(0, ICC_AP1R2_EL1);
1133 write_gicreg(0, ICC_AP1R1_EL1);
1137 write_gicreg(0, ICC_AP1R0_EL1);
1142 /* ... and let's hit the road... */
1143 gic_write_grpen1(1);
1145 /* Keep the RSS capability status in per_cpu variable */
1146 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
1148 /* Check all the CPUs have capable of sending SGIs to other CPUs */
1149 for_each_online_cpu(i) {
1150 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
1152 need_rss |= MPIDR_RS(cpu_logical_map(i));
1153 if (need_rss && (!have_rss))
1154 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
1155 cpu, (unsigned long)mpidr,
1156 i, (unsigned long)cpu_logical_map(i));
1160 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
1161 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
1162 * UNPREDICTABLE choice of :
1163 * - The write is ignored.
1164 * - The RS field is treated as 0.
1166 if (need_rss && (!gic_data.has_rss))
1167 pr_crit_once("RSS is required but GICD doesn't support it\n");
1170 static bool gicv3_nolpi;
1172 static int __init gicv3_nolpi_cfg(char *buf)
1174 return strtobool(buf, &gicv3_nolpi);
1176 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
1178 static int gic_dist_supports_lpis(void)
1180 return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
1181 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
1185 static void gic_cpu_init(void)
1187 void __iomem *rbase;
1190 /* Register ourselves with the rest of the world */
1191 if (gic_populate_rdist())
1194 gic_enable_redist(true);
1196 WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
1197 !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
1198 "Distributor has extended ranges, but CPU%d doesn't\n",
1199 smp_processor_id());
1201 rbase = gic_data_rdist_sgi_base();
1203 /* Configure SGIs/PPIs as non-secure Group-1 */
1204 for (i = 0; i < gic_data.ppi_nr + 16; i += 32)
1205 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
1207 gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp);
1209 /* initialise system registers */
1210 gic_cpu_sys_reg_init();
1215 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
1216 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL)
1218 static int gic_starting_cpu(unsigned int cpu)
1222 if (gic_dist_supports_lpis())
1228 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
1229 unsigned long cluster_id)
1231 int next_cpu, cpu = *base_cpu;
1232 unsigned long mpidr = cpu_logical_map(cpu);
1235 while (cpu < nr_cpu_ids) {
1236 tlist |= 1 << (mpidr & 0xf);
1238 next_cpu = cpumask_next(cpu, mask);
1239 if (next_cpu >= nr_cpu_ids)
1243 mpidr = cpu_logical_map(cpu);
1245 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
1255 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
1256 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
1257 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
1259 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
1263 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
1264 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
1265 irq << ICC_SGI1R_SGI_ID_SHIFT |
1266 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
1267 MPIDR_TO_SGI_RS(cluster_id) |
1268 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
1270 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
1271 gic_write_sgi1r(val);
1274 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
1278 if (WARN_ON(d->hwirq >= 16))
1282 * Ensure that stores to Normal memory are visible to the
1283 * other CPUs before issuing the IPI.
1287 for_each_cpu(cpu, mask) {
1288 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
1291 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
1292 gic_send_sgi(cluster_id, tlist, d->hwirq);
1295 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
1299 static void __init gic_smp_init(void)
1301 struct irq_fwspec sgi_fwspec = {
1302 .fwnode = gic_data.fwnode,
1307 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
1308 "irqchip/arm/gicv3:starting",
1309 gic_starting_cpu, NULL);
1311 /* Register all 8 non-secure SGIs */
1312 base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8,
1313 NUMA_NO_NODE, &sgi_fwspec,
1315 if (WARN_ON(base_sgi <= 0))
1318 set_smp_ipi_range(base_sgi, 8);
1321 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1331 cpu = cpumask_first(mask_val);
1333 cpu = cpumask_any_and(mask_val, cpu_online_mask);
1335 if (cpu >= nr_cpu_ids)
1338 if (gic_irq_in_rdist(d))
1341 /* If interrupt was enabled, disable it first */
1342 enabled = gic_peek_irq(d, GICD_ISENABLER);
1346 offset = convert_offset_index(d, GICD_IROUTER, &index);
1347 reg = gic_dist_base(d) + offset + (index * 8);
1348 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
1350 gic_write_irouter(val, reg);
1353 * If the interrupt was enabled, enabled it again. Otherwise,
1354 * just wait for the distributor to have digested our changes.
1359 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1361 return IRQ_SET_MASK_OK_DONE;
1364 #define gic_set_affinity NULL
1365 #define gic_ipi_send_mask NULL
1366 #define gic_smp_init() do { } while(0)
1369 static int gic_retrigger(struct irq_data *data)
1371 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
1374 #ifdef CONFIG_CPU_PM
1375 static int gic_cpu_pm_notifier(struct notifier_block *self,
1376 unsigned long cmd, void *v)
1378 if (cmd == CPU_PM_EXIT) {
1379 if (gic_dist_security_disabled())
1380 gic_enable_redist(true);
1381 gic_cpu_sys_reg_init();
1382 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
1383 gic_write_grpen1(0);
1384 gic_enable_redist(false);
1389 static struct notifier_block gic_cpu_pm_notifier_block = {
1390 .notifier_call = gic_cpu_pm_notifier,
1393 static void gic_cpu_pm_init(void)
1395 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
1399 static inline void gic_cpu_pm_init(void) { }
1400 #endif /* CONFIG_CPU_PM */
1402 static struct irq_chip gic_chip = {
1404 .irq_mask = gic_mask_irq,
1405 .irq_unmask = gic_unmask_irq,
1406 .irq_eoi = gic_eoi_irq,
1407 .irq_set_type = gic_set_type,
1408 .irq_set_affinity = gic_set_affinity,
1409 .irq_retrigger = gic_retrigger,
1410 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1411 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1412 .irq_nmi_setup = gic_irq_nmi_setup,
1413 .irq_nmi_teardown = gic_irq_nmi_teardown,
1414 .ipi_send_mask = gic_ipi_send_mask,
1415 .flags = IRQCHIP_SET_TYPE_MASKED |
1416 IRQCHIP_SKIP_SET_WAKE |
1417 IRQCHIP_MASK_ON_SUSPEND,
1420 static struct irq_chip gic_eoimode1_chip = {
1422 .irq_mask = gic_eoimode1_mask_irq,
1423 .irq_unmask = gic_unmask_irq,
1424 .irq_eoi = gic_eoimode1_eoi_irq,
1425 .irq_set_type = gic_set_type,
1426 .irq_set_affinity = gic_set_affinity,
1427 .irq_retrigger = gic_retrigger,
1428 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1429 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
1430 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
1431 .irq_nmi_setup = gic_irq_nmi_setup,
1432 .irq_nmi_teardown = gic_irq_nmi_teardown,
1433 .ipi_send_mask = gic_ipi_send_mask,
1434 .flags = IRQCHIP_SET_TYPE_MASKED |
1435 IRQCHIP_SKIP_SET_WAKE |
1436 IRQCHIP_MASK_ON_SUSPEND,
1439 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1442 struct irq_chip *chip = &gic_chip;
1443 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1445 if (static_branch_likely(&supports_deactivate_key))
1446 chip = &gic_eoimode1_chip;
1448 switch (__get_intid_range(hw)) {
1452 irq_set_percpu_devid(irq);
1453 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1454 handle_percpu_devid_irq, NULL, NULL);
1459 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1460 handle_fasteoi_irq, NULL, NULL);
1462 irqd_set_single_target(irqd);
1466 if (!gic_dist_supports_lpis())
1468 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1469 handle_fasteoi_irq, NULL, NULL);
1476 /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1477 irqd_set_handle_enforce_irqctx(irqd);
1481 static int gic_irq_domain_translate(struct irq_domain *d,
1482 struct irq_fwspec *fwspec,
1483 unsigned long *hwirq,
1486 if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1487 *hwirq = fwspec->param[0];
1488 *type = IRQ_TYPE_EDGE_RISING;
1492 if (is_of_node(fwspec->fwnode)) {
1493 if (fwspec->param_count < 3)
1496 switch (fwspec->param[0]) {
1498 *hwirq = fwspec->param[1] + 32;
1501 *hwirq = fwspec->param[1] + 16;
1504 *hwirq = fwspec->param[1] + ESPI_BASE_INTID;
1507 *hwirq = fwspec->param[1] + EPPI_BASE_INTID;
1509 case GIC_IRQ_TYPE_LPI: /* LPI */
1510 *hwirq = fwspec->param[1];
1512 case GIC_IRQ_TYPE_PARTITION:
1513 *hwirq = fwspec->param[1];
1514 if (fwspec->param[1] >= 16)
1515 *hwirq += EPPI_BASE_INTID - 16;
1523 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1526 * Make it clear that broken DTs are... broken.
1527 * Partitioned PPIs are an unfortunate exception.
1529 WARN_ON(*type == IRQ_TYPE_NONE &&
1530 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
1534 if (is_fwnode_irqchip(fwspec->fwnode)) {
1535 if(fwspec->param_count != 2)
1538 if (fwspec->param[0] < 16) {
1539 pr_err(FW_BUG "Illegal GSI%d translation request\n",
1544 *hwirq = fwspec->param[0];
1545 *type = fwspec->param[1];
1547 WARN_ON(*type == IRQ_TYPE_NONE);
1554 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1555 unsigned int nr_irqs, void *arg)
1558 irq_hw_number_t hwirq;
1559 unsigned int type = IRQ_TYPE_NONE;
1560 struct irq_fwspec *fwspec = arg;
1562 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1566 for (i = 0; i < nr_irqs; i++) {
1567 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1575 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1576 unsigned int nr_irqs)
1580 for (i = 0; i < nr_irqs; i++) {
1581 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1582 irq_set_handler(virq + i, NULL);
1583 irq_domain_reset_irq_data(d);
1587 static bool fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec,
1588 irq_hw_number_t hwirq)
1590 enum gic_intid_range range;
1592 if (!gic_data.ppi_descs)
1595 if (!is_of_node(fwspec->fwnode))
1598 if (fwspec->param_count < 4 || !fwspec->param[3])
1601 range = __get_intid_range(hwirq);
1602 if (range != PPI_RANGE && range != EPPI_RANGE)
1608 static int gic_irq_domain_select(struct irq_domain *d,
1609 struct irq_fwspec *fwspec,
1610 enum irq_domain_bus_token bus_token)
1612 unsigned int type, ret, ppi_idx;
1613 irq_hw_number_t hwirq;
1616 if (fwspec->fwnode != d->fwnode)
1619 /* If this is not DT, then we have a single domain */
1620 if (!is_of_node(fwspec->fwnode))
1623 ret = gic_irq_domain_translate(d, fwspec, &hwirq, &type);
1624 if (WARN_ON_ONCE(ret))
1627 if (!fwspec_is_partitioned_ppi(fwspec, hwirq))
1628 return d == gic_data.domain;
1631 * If this is a PPI and we have a 4th (non-null) parameter,
1632 * then we need to match the partition domain.
1634 ppi_idx = __gic_get_ppi_index(hwirq);
1635 return d == partition_get_domain(gic_data.ppi_descs[ppi_idx]);
1638 static const struct irq_domain_ops gic_irq_domain_ops = {
1639 .translate = gic_irq_domain_translate,
1640 .alloc = gic_irq_domain_alloc,
1641 .free = gic_irq_domain_free,
1642 .select = gic_irq_domain_select,
1645 static int partition_domain_translate(struct irq_domain *d,
1646 struct irq_fwspec *fwspec,
1647 unsigned long *hwirq,
1650 unsigned long ppi_intid;
1651 struct device_node *np;
1652 unsigned int ppi_idx;
1655 if (!gic_data.ppi_descs)
1658 np = of_find_node_by_phandle(fwspec->param[3]);
1662 ret = gic_irq_domain_translate(d, fwspec, &ppi_intid, type);
1663 if (WARN_ON_ONCE(ret))
1666 ppi_idx = __gic_get_ppi_index(ppi_intid);
1667 ret = partition_translate_id(gic_data.ppi_descs[ppi_idx],
1668 of_node_to_fwnode(np));
1673 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1678 static const struct irq_domain_ops partition_domain_ops = {
1679 .translate = partition_domain_translate,
1680 .select = gic_irq_domain_select,
1683 static bool gic_enable_quirk_msm8996(void *data)
1685 struct gic_chip_data *d = data;
1687 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;
1692 static bool gic_enable_quirk_cavium_38539(void *data)
1694 struct gic_chip_data *d = data;
1696 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
1701 static bool gic_enable_quirk_hip06_07(void *data)
1703 struct gic_chip_data *d = data;
1706 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite
1707 * not being an actual ARM implementation). The saving grace is
1708 * that GIC-600 doesn't have ESPI, so nothing to do in that case.
1709 * HIP07 doesn't even have a proper IIDR, and still pretends to
1710 * have ESPI. In both cases, put them right.
1712 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {
1713 /* Zero both ESPI and the RES0 field next to it... */
1714 d->rdists.gicd_typer &= ~GENMASK(9, 8);
1721 static const struct gic_quirk gic_quirks[] = {
1723 .desc = "GICv3: Qualcomm MSM8996 broken firmware",
1724 .compatible = "qcom,msm8996-gic-v3",
1725 .init = gic_enable_quirk_msm8996,
1728 .desc = "GICv3: HIP06 erratum 161010803",
1731 .init = gic_enable_quirk_hip06_07,
1734 .desc = "GICv3: HIP07 erratum 161010803",
1737 .init = gic_enable_quirk_hip06_07,
1741 * Reserved register accesses generate a Synchronous
1742 * External Abort. This erratum applies to:
1743 * - ThunderX: CN88xx
1744 * - OCTEON TX: CN83xx, CN81xx
1745 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1747 .desc = "GICv3: Cavium erratum 38539",
1750 .init = gic_enable_quirk_cavium_38539,
1756 static void gic_enable_nmi_support(void)
1760 if (!gic_prio_masking_enabled())
1763 ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
1767 for (i = 0; i < gic_data.ppi_nr; i++)
1768 refcount_set(&ppi_nmi_refs[i], 0);
1771 * Linux itself doesn't use 1:N distribution, so has no need to
1772 * set PMHE. The only reason to have it set is if EL3 requires it
1773 * (and we can't change it).
1775 if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK)
1776 static_branch_enable(&gic_pmr_sync);
1778 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",
1779 static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed");
1782 * How priority values are used by the GIC depends on two things:
1783 * the security state of the GIC (controlled by the GICD_CTRL.DS bit)
1784 * and if Group 0 interrupts can be delivered to Linux in the non-secure
1785 * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the
1786 * ICC_PMR_EL1 register and the priority that software assigns to
1789 * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority
1790 * -----------------------------------------------------------
1791 * 1 | - | unchanged | unchanged
1792 * -----------------------------------------------------------
1793 * 0 | 1 | non-secure | non-secure
1794 * -----------------------------------------------------------
1795 * 0 | 0 | unchanged | non-secure
1797 * where non-secure means that the value is right-shifted by one and the
1798 * MSB bit set, to make it fit in the non-secure priority range.
1800 * In the first two cases, where ICC_PMR_EL1 and the interrupt priority
1801 * are both either modified or unchanged, we can use the same set of
1804 * In the last case, where only the interrupt priorities are modified to
1805 * be in the non-secure range, we use a different PMR value to mask IRQs
1806 * and the rest of the values that we use remain unchanged.
1808 if (gic_has_group0() && !gic_dist_security_disabled())
1809 static_branch_enable(&gic_nonsecure_priorities);
1811 static_branch_enable(&supports_pseudo_nmis);
1813 if (static_branch_likely(&supports_deactivate_key))
1814 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1816 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1819 static int __init gic_init_bases(void __iomem *dist_base,
1820 struct redist_region *rdist_regs,
1821 u32 nr_redist_regions,
1823 struct fwnode_handle *handle)
1828 if (!is_hyp_mode_available())
1829 static_branch_disable(&supports_deactivate_key);
1831 if (static_branch_likely(&supports_deactivate_key))
1832 pr_info("GIC: Using split EOI/Deactivate mode\n");
1834 gic_data.fwnode = handle;
1835 gic_data.dist_base = dist_base;
1836 gic_data.redist_regions = rdist_regs;
1837 gic_data.nr_redist_regions = nr_redist_regions;
1838 gic_data.redist_stride = redist_stride;
1841 * Find out how many interrupts are supported.
1843 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
1844 gic_data.rdists.gicd_typer = typer;
1846 gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR),
1847 gic_quirks, &gic_data);
1849 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
1850 pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
1853 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
1854 * architecture spec (which says that reserved registers are RES0).
1856 if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
1857 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
1859 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1861 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
1862 gic_data.rdists.has_rvpeid = true;
1863 gic_data.rdists.has_vlpis = true;
1864 gic_data.rdists.has_direct_lpi = true;
1865 gic_data.rdists.has_vpend_valid_dirty = true;
1867 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1872 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1874 gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1876 if (typer & GICD_TYPER_MBIS) {
1877 err = mbi_init(handle, gic_data.domain);
1879 pr_err("Failed to initialize MBIs\n");
1882 set_handle_irq(gic_handle_irq);
1884 gic_update_rdist_properties();
1891 if (gic_dist_supports_lpis()) {
1892 its_init(handle, &gic_data.rdists, gic_data.domain);
1894 its_lpi_memreserve_init();
1896 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1897 gicv2m_init(handle, gic_data.domain);
1900 gic_enable_nmi_support();
1905 if (gic_data.domain)
1906 irq_domain_remove(gic_data.domain);
1907 free_percpu(gic_data.rdists.rdist);
1911 static int __init gic_validate_dist_version(void __iomem *dist_base)
1913 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1915 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1921 /* Create all possible partitions at boot time */
1922 static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
1924 struct device_node *parts_node, *child_part;
1925 int part_idx = 0, i;
1927 struct partition_affinity *parts;
1929 parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
1933 gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
1934 if (!gic_data.ppi_descs)
1937 nr_parts = of_get_child_count(parts_node);
1942 parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
1943 if (WARN_ON(!parts))
1946 for_each_child_of_node(parts_node, child_part) {
1947 struct partition_affinity *part;
1950 part = &parts[part_idx];
1952 part->partition_id = of_node_to_fwnode(child_part);
1954 pr_info("GIC: PPI partition %pOFn[%d] { ",
1955 child_part, part_idx);
1957 n = of_property_count_elems_of_size(child_part, "affinity",
1961 for (i = 0; i < n; i++) {
1964 struct device_node *cpu_node;
1966 err = of_property_read_u32_index(child_part, "affinity",
1971 cpu_node = of_find_node_by_phandle(cpu_phandle);
1972 if (WARN_ON(!cpu_node))
1975 cpu = of_cpu_node_to_id(cpu_node);
1976 if (WARN_ON(cpu < 0)) {
1977 of_node_put(cpu_node);
1981 pr_cont("%pOF[%d] ", cpu_node, cpu);
1983 cpumask_set_cpu(cpu, &part->mask);
1984 of_node_put(cpu_node);
1991 for (i = 0; i < gic_data.ppi_nr; i++) {
1993 struct partition_desc *desc;
1994 struct irq_fwspec ppi_fwspec = {
1995 .fwnode = gic_data.fwnode,
1998 [0] = GIC_IRQ_TYPE_PARTITION,
2000 [2] = IRQ_TYPE_NONE,
2004 irq = irq_create_fwspec_mapping(&ppi_fwspec);
2007 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
2008 irq, &partition_domain_ops);
2012 gic_data.ppi_descs[i] = desc;
2016 of_node_put(parts_node);
2019 static void __init gic_of_setup_kvm_info(struct device_node *node)
2025 gic_v3_kvm_info.type = GIC_V3;
2027 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
2028 if (!gic_v3_kvm_info.maint_irq)
2031 if (of_property_read_u32(node, "#redistributor-regions",
2035 gicv_idx += 3; /* Also skip GICD, GICC, GICH */
2036 ret = of_address_to_resource(node, gicv_idx, &r);
2038 gic_v3_kvm_info.vcpu = r;
2040 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
2041 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
2042 vgic_set_kvm_info(&gic_v3_kvm_info);
2045 static int __init gic_of_init(struct device_node *node, struct device_node *parent)
2047 void __iomem *dist_base;
2048 struct redist_region *rdist_regs;
2050 u32 nr_redist_regions;
2053 dist_base = of_io_request_and_map(node, 0, "GICD");
2054 if (IS_ERR(dist_base)) {
2055 pr_err("%pOF: unable to map gic dist registers\n", node);
2056 return PTR_ERR(dist_base);
2059 err = gic_validate_dist_version(dist_base);
2061 pr_err("%pOF: no distributor detected, giving up\n", node);
2062 goto out_unmap_dist;
2065 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
2066 nr_redist_regions = 1;
2068 rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
2072 goto out_unmap_dist;
2075 for (i = 0; i < nr_redist_regions; i++) {
2076 struct resource res;
2079 ret = of_address_to_resource(node, 1 + i, &res);
2080 rdist_regs[i].redist_base = of_io_request_and_map(node, 1 + i, "GICR");
2081 if (ret || IS_ERR(rdist_regs[i].redist_base)) {
2082 pr_err("%pOF: couldn't map region %d\n", node, i);
2084 goto out_unmap_rdist;
2086 rdist_regs[i].phys_base = res.start;
2089 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
2092 gic_enable_of_quirks(node, gic_quirks, &gic_data);
2094 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
2095 redist_stride, &node->fwnode);
2097 goto out_unmap_rdist;
2099 gic_populate_ppi_partitions(node);
2101 if (static_branch_likely(&supports_deactivate_key))
2102 gic_of_setup_kvm_info(node);
2106 for (i = 0; i < nr_redist_regions; i++)
2107 if (rdist_regs[i].redist_base && !IS_ERR(rdist_regs[i].redist_base))
2108 iounmap(rdist_regs[i].redist_base);
2115 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2120 void __iomem *dist_base;
2121 struct redist_region *redist_regs;
2122 u32 nr_redist_regions;
2127 phys_addr_t vcpu_base;
2128 } acpi_data __initdata;
2131 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
2133 static int count = 0;
2135 acpi_data.redist_regs[count].phys_base = phys_base;
2136 acpi_data.redist_regs[count].redist_base = redist_base;
2137 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
2142 gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
2143 const unsigned long end)
2145 struct acpi_madt_generic_redistributor *redist =
2146 (struct acpi_madt_generic_redistributor *)header;
2147 void __iomem *redist_base;
2149 redist_base = ioremap(redist->base_address, redist->length);
2151 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
2154 request_mem_region(redist->base_address, redist->length, "GICR");
2156 gic_acpi_register_redist(redist->base_address, redist_base);
2161 gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
2162 const unsigned long end)
2164 struct acpi_madt_generic_interrupt *gicc =
2165 (struct acpi_madt_generic_interrupt *)header;
2166 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
2167 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
2168 void __iomem *redist_base;
2170 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
2171 if (!(gicc->flags & ACPI_MADT_ENABLED))
2174 redist_base = ioremap(gicc->gicr_base_address, size);
2177 request_mem_region(gicc->gicr_base_address, size, "GICR");
2179 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
2183 static int __init gic_acpi_collect_gicr_base(void)
2185 acpi_tbl_entry_handler redist_parser;
2186 enum acpi_madt_type type;
2188 if (acpi_data.single_redist) {
2189 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
2190 redist_parser = gic_acpi_parse_madt_gicc;
2192 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
2193 redist_parser = gic_acpi_parse_madt_redist;
2196 /* Collect redistributor base addresses in GICR entries */
2197 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
2200 pr_info("No valid GICR entries exist\n");
2204 static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header,
2205 const unsigned long end)
2207 /* Subtable presence means that redist exists, that's it */
2211 static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
2212 const unsigned long end)
2214 struct acpi_madt_generic_interrupt *gicc =
2215 (struct acpi_madt_generic_interrupt *)header;
2218 * If GICC is enabled and has valid gicr base address, then it means
2219 * GICR base is presented via GICC
2221 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {
2222 acpi_data.enabled_rdists++;
2227 * It's perfectly valid firmware can pass disabled GICC entry, driver
2228 * should not treat as errors, skip the entry instead of probe fail.
2230 if (!(gicc->flags & ACPI_MADT_ENABLED))
2236 static int __init gic_acpi_count_gicr_regions(void)
2241 * Count how many redistributor regions we have. It is not allowed
2242 * to mix redistributor description, GICR and GICC subtables have to be
2243 * mutually exclusive.
2245 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
2246 gic_acpi_match_gicr, 0);
2248 acpi_data.single_redist = false;
2252 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2253 gic_acpi_match_gicc, 0);
2255 acpi_data.single_redist = true;
2256 count = acpi_data.enabled_rdists;
2262 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
2263 struct acpi_probe_entry *ape)
2265 struct acpi_madt_generic_distributor *dist;
2268 dist = (struct acpi_madt_generic_distributor *)header;
2269 if (dist->version != ape->driver_data)
2272 /* We need to do that exercise anyway, the sooner the better */
2273 count = gic_acpi_count_gicr_regions();
2277 acpi_data.nr_redist_regions = count;
2281 static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header,
2282 const unsigned long end)
2284 struct acpi_madt_generic_interrupt *gicc =
2285 (struct acpi_madt_generic_interrupt *)header;
2287 static int first_madt = true;
2289 /* Skip unusable CPUs */
2290 if (!(gicc->flags & ACPI_MADT_ENABLED))
2293 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
2294 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
2299 acpi_data.maint_irq = gicc->vgic_interrupt;
2300 acpi_data.maint_irq_mode = maint_irq_mode;
2301 acpi_data.vcpu_base = gicc->gicv_base_address;
2307 * The maintenance interrupt and GICV should be the same for every CPU
2309 if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
2310 (acpi_data.maint_irq_mode != maint_irq_mode) ||
2311 (acpi_data.vcpu_base != gicc->gicv_base_address))
2317 static bool __init gic_acpi_collect_virt_info(void)
2321 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2322 gic_acpi_parse_virt_madt_gicc, 0);
2327 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
2328 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
2329 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
2331 static void __init gic_acpi_setup_kvm_info(void)
2335 if (!gic_acpi_collect_virt_info()) {
2336 pr_warn("Unable to get hardware information used for virtualization\n");
2340 gic_v3_kvm_info.type = GIC_V3;
2342 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
2343 acpi_data.maint_irq_mode,
2348 gic_v3_kvm_info.maint_irq = irq;
2350 if (acpi_data.vcpu_base) {
2351 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
2353 vcpu->flags = IORESOURCE_MEM;
2354 vcpu->start = acpi_data.vcpu_base;
2355 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
2358 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
2359 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
2360 vgic_set_kvm_info(&gic_v3_kvm_info);
2364 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
2366 struct acpi_madt_generic_distributor *dist;
2367 struct fwnode_handle *domain_handle;
2371 /* Get distributor base address */
2372 dist = (struct acpi_madt_generic_distributor *)header;
2373 acpi_data.dist_base = ioremap(dist->base_address,
2374 ACPI_GICV3_DIST_MEM_SIZE);
2375 if (!acpi_data.dist_base) {
2376 pr_err("Unable to map GICD registers\n");
2379 request_mem_region(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE, "GICD");
2381 err = gic_validate_dist_version(acpi_data.dist_base);
2383 pr_err("No distributor detected at @%p, giving up\n",
2384 acpi_data.dist_base);
2385 goto out_dist_unmap;
2388 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
2389 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
2390 if (!acpi_data.redist_regs) {
2392 goto out_dist_unmap;
2395 err = gic_acpi_collect_gicr_base();
2397 goto out_redist_unmap;
2399 domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
2400 if (!domain_handle) {
2402 goto out_redist_unmap;
2405 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
2406 acpi_data.nr_redist_regions, 0, domain_handle);
2408 goto out_fwhandle_free;
2410 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
2412 if (static_branch_likely(&supports_deactivate_key))
2413 gic_acpi_setup_kvm_info();
2418 irq_domain_free_fwnode(domain_handle);
2420 for (i = 0; i < acpi_data.nr_redist_regions; i++)
2421 if (acpi_data.redist_regs[i].redist_base)
2422 iounmap(acpi_data.redist_regs[i].redist_base);
2423 kfree(acpi_data.redist_regs);
2425 iounmap(acpi_data.dist_base);
2428 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2429 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
2431 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2432 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
2434 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2435 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,