2 * drivers/irqchip/irq-crossbar.c
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sricharan R <r.sricharan@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/err.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqdomain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/slab.h>
21 #define IRQ_RESERVED -2
23 #define GIC_IRQ_START 32
26 * struct crossbar_device - crossbar device description
27 * @lock: spinlock serializing access to @irq_map
28 * @int_max: maximum number of supported interrupts
29 * @safe_map: safe default value to initialize the crossbar
30 * @max_crossbar_sources: Maximum number of crossbar sources
31 * @irq_map: array of interrupts to crossbar number mapping
32 * @crossbar_base: crossbar base address
33 * @register_offsets: offsets for each irq number
34 * @write: register write function pointer
36 struct crossbar_device {
40 uint max_crossbar_sources;
42 void __iomem *crossbar_base;
43 int *register_offsets;
44 void (*write)(int, int);
47 static struct crossbar_device *cb;
49 static void crossbar_writel(int irq_no, int cb_no)
51 writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
54 static void crossbar_writew(int irq_no, int cb_no)
56 writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
59 static void crossbar_writeb(int irq_no, int cb_no)
61 writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
64 static struct irq_chip crossbar_chip = {
66 .irq_eoi = irq_chip_eoi_parent,
67 .irq_mask = irq_chip_mask_parent,
68 .irq_unmask = irq_chip_unmask_parent,
69 .irq_retrigger = irq_chip_retrigger_hierarchy,
70 .irq_set_wake = irq_chip_set_wake_parent,
72 .irq_set_affinity = irq_chip_set_affinity_parent,
76 static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
77 irq_hw_number_t hwirq)
79 struct of_phandle_args args;
83 raw_spin_lock(&cb->lock);
84 for (i = cb->int_max - 1; i >= 0; i--) {
85 if (cb->irq_map[i] == IRQ_FREE) {
86 cb->irq_map[i] = hwirq;
90 raw_spin_unlock(&cb->lock);
95 args.np = domain->parent->of_node;
97 args.args[0] = 0; /* SPI */
99 args.args[2] = IRQ_TYPE_LEVEL_HIGH;
101 err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
103 cb->irq_map[i] = IRQ_FREE;
110 static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
111 unsigned int nr_irqs, void *data)
113 struct of_phandle_args *args = data;
114 irq_hw_number_t hwirq;
117 if (args->args_count != 3)
118 return -EINVAL; /* Not GIC compliant */
119 if (args->args[0] != 0)
120 return -EINVAL; /* No PPI should point to this domain */
122 hwirq = args->args[1];
123 if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
124 return -EINVAL; /* Can't deal with this */
126 for (i = 0; i < nr_irqs; i++) {
127 int err = allocate_gic_irq(d, virq + i, hwirq + i);
132 irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
133 &crossbar_chip, NULL);
140 * crossbar_domain_free - unmap/free a crossbar<->irq connection
141 * @domain: domain of irq to unmap
143 * @nr_irqs: number of irqs to free
145 * We do not maintain a use count of total number of map/unmap
146 * calls for a particular irq to find out if a irq can be really
147 * unmapped. This is because unmap is called during irq_dispose_mapping(irq),
148 * after which irq is anyways unusable. So an explicit map has to be called
151 static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
152 unsigned int nr_irqs)
156 raw_spin_lock(&cb->lock);
157 for (i = 0; i < nr_irqs; i++) {
158 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
160 irq_domain_reset_irq_data(d);
161 cb->irq_map[d->hwirq] = IRQ_FREE;
162 cb->write(d->hwirq, cb->safe_map);
164 raw_spin_unlock(&cb->lock);
167 static int crossbar_domain_xlate(struct irq_domain *d,
168 struct device_node *controller,
169 const u32 *intspec, unsigned int intsize,
170 unsigned long *out_hwirq,
171 unsigned int *out_type)
173 if (d->of_node != controller)
174 return -EINVAL; /* Shouldn't happen, really... */
176 return -EINVAL; /* Not GIC compliant */
178 return -EINVAL; /* No PPI should point to this domain */
180 *out_hwirq = intspec[1];
181 *out_type = intspec[2];
185 static const struct irq_domain_ops crossbar_domain_ops = {
186 .alloc = crossbar_domain_alloc,
187 .free = crossbar_domain_free,
188 .xlate = crossbar_domain_xlate,
191 static int __init crossbar_of_init(struct device_node *node)
193 int i, size, max = 0, reserved = 0, entry;
197 cb = kzalloc(sizeof(*cb), GFP_KERNEL);
202 cb->crossbar_base = of_iomap(node, 0);
203 if (!cb->crossbar_base)
206 of_property_read_u32(node, "ti,max-crossbar-sources",
207 &cb->max_crossbar_sources);
208 if (!cb->max_crossbar_sources) {
209 pr_err("missing 'ti,max-crossbar-sources' property\n");
214 of_property_read_u32(node, "ti,max-irqs", &max);
216 pr_err("missing 'ti,max-irqs' property\n");
220 cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
226 for (i = 0; i < max; i++)
227 cb->irq_map[i] = IRQ_FREE;
229 /* Get and mark reserved irqs */
230 irqsr = of_get_property(node, "ti,irqs-reserved", &size);
232 size /= sizeof(__be32);
234 for (i = 0; i < size; i++) {
235 of_property_read_u32_index(node,
239 pr_err("Invalid reserved entry\n");
243 cb->irq_map[entry] = IRQ_RESERVED;
247 /* Skip irqs hardwired to bypass the crossbar */
248 irqsr = of_get_property(node, "ti,irqs-skip", &size);
250 size /= sizeof(__be32);
252 for (i = 0; i < size; i++) {
253 of_property_read_u32_index(node,
257 pr_err("Invalid skip entry\n");
261 cb->irq_map[entry] = IRQ_SKIP;
266 cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
267 if (!cb->register_offsets)
270 of_property_read_u32(node, "ti,reg-size", &size);
274 cb->write = crossbar_writeb;
277 cb->write = crossbar_writew;
280 cb->write = crossbar_writel;
283 pr_err("Invalid reg-size property\n");
290 * Register offsets are not linear because of the
291 * reserved irqs. so find and store the offsets once.
293 for (i = 0; i < max; i++) {
294 if (cb->irq_map[i] == IRQ_RESERVED)
297 cb->register_offsets[i] = reserved;
301 of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
302 /* Initialize the crossbar with safe map to start with */
303 for (i = 0; i < max; i++) {
304 if (cb->irq_map[i] == IRQ_RESERVED ||
305 cb->irq_map[i] == IRQ_SKIP)
308 cb->write(i, cb->safe_map);
311 raw_spin_lock_init(&cb->lock);
316 kfree(cb->register_offsets);
320 iounmap(cb->crossbar_base);
328 static int __init irqcrossbar_init(struct device_node *node,
329 struct device_node *parent)
331 struct irq_domain *parent_domain, *domain;
335 pr_err("%s: no parent, giving up\n", node->full_name);
339 parent_domain = irq_find_host(parent);
340 if (!parent_domain) {
341 pr_err("%s: unable to obtain parent domain\n", node->full_name);
345 err = crossbar_of_init(node);
349 domain = irq_domain_add_hierarchy(parent_domain, 0,
350 cb->max_crossbar_sources,
351 node, &crossbar_domain_ops,
354 pr_err("%s: failed to allocated domain\n", node->full_name);
361 IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);