8 select MULTI_IRQ_HANDLER
16 select MULTI_IRQ_HANDLER
21 select GENERIC_IRQ_CHIP
26 select MULTI_IRQ_HANDLER
30 default 4 if ARCH_S5PV210
34 The maximum number of VICs available in the system, for
39 select GENERIC_IRQ_CHIP
41 select MULTI_IRQ_HANDLER
46 select GENERIC_IRQ_CHIP
48 select MULTI_IRQ_HANDLER
53 select GENERIC_IRQ_CHIP
58 select GENERIC_IRQ_CHIP
63 select GENERIC_IRQ_CHIP
68 select GENERIC_IRQ_CHIP
71 config CLPS711X_IRQCHIP
73 depends on ARCH_CLPS711X
75 select MULTI_IRQ_HANDLER
85 select GENERIC_IRQ_CHIP
91 select MULTI_IRQ_HANDLER
93 config RENESAS_INTC_IRQPIN
104 select GENERIC_IRQ_CHIP
106 config VERSATILE_FPGA_IRQ
110 config VERSATILE_FPGA_IRQ_NR
113 depends on VERSATILE_FPGA_IRQ
122 Support for a CROSSBAR ip that precedes the main interrupt controller.
123 The primary irqchip invokes the crossbar's callback which inturn allocates
124 a free irq and configures the IP. Thus the peripheral interrupts are
125 routed to one of the free irqchip interrupt lines.
128 tristate "Keystone 2 IRQ controller IP"
129 depends on ARCH_KEYSTONE
131 Support for Texas Instruments Keystone 2 IRQ controller IP which
132 is part of the Keystone 2 IPC mechanism