1 menu "IRQ chip support"
10 select IRQ_DOMAIN_HIERARCHY
11 select MULTI_IRQ_HANDLER
12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
22 default 2 if ARCH_REALVIEW
37 select MULTI_IRQ_HANDLER
38 select IRQ_DOMAIN_HIERARCHY
39 select PARTITION_PERCPU
40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
50 select IRQ_DOMAIN_HIERARCHY
51 select GENERIC_IRQ_CHIP
56 select MULTI_IRQ_HANDLER
60 default 4 if ARCH_S5PV210
64 The maximum number of VICs available in the system, for
67 config ARMADA_370_XP_IRQ
69 select GENERIC_IRQ_CHIP
71 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
77 select GENERIC_IRQ_CHIP
81 select GENERIC_IRQ_CHIP
83 select MULTI_IRQ_HANDLER
88 select GENERIC_IRQ_CHIP
90 select MULTI_IRQ_HANDLER
99 select GENERIC_IRQ_CHIP
101 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
103 config BCM7038_L1_IRQ
105 select GENERIC_IRQ_CHIP
107 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
109 config BCM7120_L2_IRQ
111 select GENERIC_IRQ_CHIP
114 config BRCMSTB_L2_IRQ
116 select GENERIC_IRQ_CHIP
121 select GENERIC_IRQ_CHIP
124 config FARADAY_FTINTC010
127 select MULTI_IRQ_HANDLER
130 config HISILICON_IRQ_MBIGEN
133 select ARM_GIC_V3_ITS
137 select GENERIC_IRQ_CHIP
142 select GENERIC_IRQ_CHIP
143 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
145 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
146 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
148 config CLPS711X_IRQCHIP
150 depends on ARCH_CLPS711X
152 select MULTI_IRQ_HANDLER
165 select GENERIC_IRQ_CHIP
171 select MULTI_IRQ_HANDLER
175 select GENERIC_IRQ_CHIP
179 bool "J-Core integrated AIC" if COMPILE_TEST
183 Support for the J-Core integrated AIC.
185 config RENESAS_INTC_IRQPIN
191 select GENERIC_IRQ_CHIP
199 Enables SysCfg Controlled IRQs on STi based platforms.
204 select GENERIC_IRQ_CHIP
209 select GENERIC_IRQ_CHIP
212 tristate "TS-4800 IRQ controller"
215 depends on SOC_IMX51 || COMPILE_TEST
217 Support for the TS-4800 FPGA IRQ controller
219 config VERSATILE_FPGA_IRQ
223 config VERSATILE_FPGA_IRQ_NR
226 depends on VERSATILE_FPGA_IRQ
231 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
240 Support for a CROSSBAR ip that precedes the main interrupt controller.
241 The primary irqchip invokes the crossbar's callback which inturn allocates
242 a free irq and configures the IP. Thus the peripheral interrupts are
243 routed to one of the free irqchip interrupt lines.
246 tristate "Keystone 2 IRQ controller IP"
247 depends on ARCH_KEYSTONE
249 Support for Texas Instruments Keystone 2 IRQ controller IP which
250 is part of the Keystone 2 IPC mechanism
254 select GENERIC_IRQ_IPI
255 select IRQ_DOMAIN_HIERARCHY
260 depends on MACH_INGENIC
263 config RENESAS_H8300H_INTC
267 config RENESAS_H8S_INTC
275 Enables the wakeup IRQs for IMX platforms with GPCv2 block
278 def_bool y if MACH_ASM9260 || ARCH_MXS
290 select GENERIC_MSI_IRQ_DOMAIN
296 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
297 depends on PCI && PCI_MSI
299 config PARTITION_PERCPU
303 bool "NPS400 Global Interrupt Manager (GIM)"
304 depends on ARC || (COMPILE_TEST && !64BIT)
307 Support the EZchip NPS400 global interrupt controller
312 select GENERIC_IRQ_CHIP
314 config QCOM_IRQ_COMBINER
315 bool "QCOM IRQ combiner support"
316 depends on ARCH_QCOM && ACPI
318 select IRQ_DOMAIN_HIERARCHY
320 Say yes here to add support for the IRQ combiner devices embedded
321 in Qualcomm Technologies chips.
323 config IRQ_UNIPHIER_AIDET
324 bool "UniPhier AIDET support" if COMPILE_TEST
325 depends on ARCH_UNIPHIER || COMPILE_TEST
326 default ARCH_UNIPHIER
327 select IRQ_DOMAIN_HIERARCHY
329 Support for the UniPhier AIDET (ARM Interrupt Detector).
331 config MESON_IRQ_GPIO
332 bool "Meson GPIO Interrupt Multiplexer"
333 depends on ARCH_MESON
335 select IRQ_DOMAIN_HIERARCHY
337 Support Meson SoC Family GPIO Interrupt Multiplexer