drivers/iommu/tegra-gart.c

   1 /*
   2  * IOMMU API for GART in Tegra20
   3  *
   4  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Author: Hiroshi DOYU <hdoyu@nvidia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  20  */
  21
  22 #define dev_fmt(fmt)    "gart: " fmt
  23
  24 #include <linux/io.h>
  25 #include <linux/iommu.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/slab.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/vmalloc.h>
  31
  32 #include <soc/tegra/mc.h>
  33
  34 /* bitmap of the page sizes currently supported */
  35 #define GART_IOMMU_PGSIZES      (SZ_4K)
  36
  37 #define GART_REG_BASE           0x24
  38 #define GART_CONFIG             (0x24 - GART_REG_BASE)
  39 #define GART_ENTRY_ADDR         (0x28 - GART_REG_BASE)
  40 #define GART_ENTRY_DATA         (0x2c - GART_REG_BASE)
  41 #define GART_ENTRY_PHYS_ADDR_VALID      (1 << 31)
  42
  43 #define GART_PAGE_SHIFT         12
  44 #define GART_PAGE_SIZE          (1 << GART_PAGE_SHIFT)
  45 #define GART_PAGE_MASK                                          \
  46         (~(GART_PAGE_SIZE - 1) & ~GART_ENTRY_PHYS_ADDR_VALID)
  47
  48 struct gart_device {
  49         void __iomem            *regs;
  50         u32                     *savedata;
  51         u32                     page_count;     /* total remappable size */
  52         dma_addr_t              iovmm_base;     /* offset to vmm_area */
  53         spinlock_t              pte_lock;       /* for pagetable */
  54         spinlock_t              dom_lock;       /* for active domain */
  55         unsigned int            active_devices; /* number of active devices */
  56         struct iommu_domain     *active_domain; /* current active domain */
  57         struct device           *dev;
  58
  59         struct iommu_device     iommu;          /* IOMMU Core handle */
  60 };
  61
  62 static struct gart_device *gart_handle; /* unique for a system */
  63
  64 static bool gart_debug;
  65
  66 #define GART_PTE(_pfn)                                          \
  67         (GART_ENTRY_PHYS_ADDR_VALID | ((_pfn) << PAGE_SHIFT))
  68
  69 /*
  70  * Any interaction between any block on PPSB and a block on APB or AHB
  71  * must have these read-back to ensure the APB/AHB bus transaction is
  72  * complete before initiating activity on the PPSB block.
  73  */
  74 #define FLUSH_GART_REGS(gart)   ((void)readl((gart)->regs + GART_CONFIG))
  75
  76 #define for_each_gart_pte(gart, iova)                                   \
  77         for (iova = gart->iovmm_base;                                   \
  78              iova < gart->iovmm_base + GART_PAGE_SIZE * gart->page_count; \
  79              iova += GART_PAGE_SIZE)
  80
  81 static inline void gart_set_pte(struct gart_device *gart,
  82                                 unsigned long offs, u32 pte)
  83 {
  84         writel(offs, gart->regs + GART_ENTRY_ADDR);
  85         writel(pte, gart->regs + GART_ENTRY_DATA);
  86
  87         dev_dbg(gart->dev, "%s %08lx:%08x\n",
  88                  pte ? "map" : "unmap", offs, pte & GART_PAGE_MASK);
  89 }
  90
  91 static inline unsigned long gart_read_pte(struct gart_device *gart,
  92                                           unsigned long offs)
  93 {
  94         unsigned long pte;
  95
  96         writel(offs, gart->regs + GART_ENTRY_ADDR);
  97         pte = readl(gart->regs + GART_ENTRY_DATA);
  98
  99         return pte;
 100 }
 101
 102 static void do_gart_setup(struct gart_device *gart, const u32 *data)
 103 {
 104         unsigned long iova;
 105
 106         for_each_gart_pte(gart, iova)
 107                 gart_set_pte(gart, iova, data ? *(data++) : 0);
 108
 109         writel(1, gart->regs + GART_CONFIG);
 110         FLUSH_GART_REGS(gart);
 111 }
 112
 113 #ifdef DEBUG
 114 static void gart_dump_table(struct gart_device *gart)
 115 {
 116         unsigned long iova;
 117         unsigned long flags;
 118
 119         spin_lock_irqsave(&gart->pte_lock, flags);
 120         for_each_gart_pte(gart, iova) {
 121                 unsigned long pte;
 122
 123                 pte = gart_read_pte(gart, iova);
 124
 125                 dev_dbg(gart->dev, "%s %08lx:%08lx\n",
 126                         (GART_ENTRY_PHYS_ADDR_VALID & pte) ? "v" : " ",
 127                         iova, pte & GART_PAGE_MASK);
 128         }
 129         spin_unlock_irqrestore(&gart->pte_lock, flags);
 130 }
 131 #else
 132 static inline void gart_dump_table(struct gart_device *gart)
 133 {
 134 }
 135 #endif
 136
 137 static inline bool gart_iova_range_valid(struct gart_device *gart,
 138                                          unsigned long iova, size_t bytes)
 139 {
 140         unsigned long iova_start, iova_end, gart_start, gart_end;
 141
 142         iova_start = iova;
 143         iova_end = iova_start + bytes - 1;
 144         gart_start = gart->iovmm_base;
 145         gart_end = gart_start + gart->page_count * GART_PAGE_SIZE - 1;
 146
 147         if (iova_start < gart_start)
 148                 return false;
 149         if (iova_end > gart_end)
 150                 return false;
 151         return true;
 152 }
 153
 154 static int gart_iommu_attach_dev(struct iommu_domain *domain,
 155                                  struct device *dev)
 156 {
 157         struct gart_device *gart = gart_handle;
 158         int ret = 0;
 159
 160         spin_lock(&gart->dom_lock);
 161
 162         if (gart->active_domain && gart->active_domain != domain) {
 163                 ret = -EBUSY;
 164         } else if (dev->archdata.iommu != domain) {
 165                 dev->archdata.iommu = domain;
 166                 gart->active_domain = domain;
 167                 gart->active_devices++;
 168         }
 169
 170         spin_unlock(&gart->dom_lock);
 171
 172         return ret;
 173 }
 174
 175 static void gart_iommu_detach_dev(struct iommu_domain *domain,
 176                                   struct device *dev)
 177 {
 178         struct gart_device *gart = gart_handle;
 179
 180         spin_lock(&gart->dom_lock);
 181
 182         if (dev->archdata.iommu == domain) {
 183                 dev->archdata.iommu = NULL;
 184
 185                 if (--gart->active_devices == 0)
 186                         gart->active_domain = NULL;
 187         }
 188
 189         spin_unlock(&gart->dom_lock);
 190 }
 191
 192 static struct iommu_domain *gart_iommu_domain_alloc(unsigned type)
 193 {
 194         struct gart_device *gart = gart_handle;
 195         struct iommu_domain *domain;
 196
 197         if (type != IOMMU_DOMAIN_UNMANAGED)
 198                 return NULL;
 199
 200         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 201         if (domain) {
 202                 domain->geometry.aperture_start = gart->iovmm_base;
 203                 domain->geometry.aperture_end = gart->iovmm_base +
 204                                         gart->page_count * GART_PAGE_SIZE - 1;
 205                 domain->geometry.force_aperture = true;
 206         }
 207
 208         return domain;
 209 }
 210
 211 static void gart_iommu_domain_free(struct iommu_domain *domain)
 212 {
 213         WARN_ON(gart_handle->active_domain == domain);
 214         kfree(domain);
 215 }
 216
 217 static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova,
 218                           phys_addr_t pa, size_t bytes, int prot)
 219 {
 220         struct gart_device *gart = gart_handle;
 221         unsigned long flags;
 222         unsigned long pfn;
 223         unsigned long pte;
 224
 225         if (!gart_iova_range_valid(gart, iova, bytes))
 226                 return -EINVAL;
 227
 228         spin_lock_irqsave(&gart->pte_lock, flags);
 229         pfn = __phys_to_pfn(pa);
 230         if (!pfn_valid(pfn)) {
 231                 dev_err(gart->dev, "Invalid page: %pa\n", &pa);
 232                 spin_unlock_irqrestore(&gart->pte_lock, flags);
 233                 return -EINVAL;
 234         }
 235         if (gart_debug) {
 236                 pte = gart_read_pte(gart, iova);
 237                 if (pte & GART_ENTRY_PHYS_ADDR_VALID) {
 238                         spin_unlock_irqrestore(&gart->pte_lock, flags);
 239                         dev_err(gart->dev, "Page entry is in-use\n");
 240                         return -EBUSY;
 241                 }
 242         }
 243         gart_set_pte(gart, iova, GART_PTE(pfn));
 244         spin_unlock_irqrestore(&gart->pte_lock, flags);
 245         return 0;
 246 }
 247
 248 static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
 249                                size_t bytes)
 250 {
 251         struct gart_device *gart = gart_handle;
 252         unsigned long flags;
 253
 254         if (!gart_iova_range_valid(gart, iova, bytes))
 255                 return 0;
 256
 257         spin_lock_irqsave(&gart->pte_lock, flags);
 258         gart_set_pte(gart, iova, 0);
 259         spin_unlock_irqrestore(&gart->pte_lock, flags);
 260         return bytes;
 261 }
 262
 263 static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
 264                                            dma_addr_t iova)
 265 {
 266         struct gart_device *gart = gart_handle;
 267         unsigned long pte;
 268         phys_addr_t pa;
 269         unsigned long flags;
 270
 271         if (!gart_iova_range_valid(gart, iova, 0))
 272                 return -EINVAL;
 273
 274         spin_lock_irqsave(&gart->pte_lock, flags);
 275         pte = gart_read_pte(gart, iova);
 276         spin_unlock_irqrestore(&gart->pte_lock, flags);
 277
 278         pa = (pte & GART_PAGE_MASK);
 279         if (!pfn_valid(__phys_to_pfn(pa))) {
 280                 dev_err(gart->dev, "No entry for %08llx:%pa\n",
 281                          (unsigned long long)iova, &pa);
 282                 gart_dump_table(gart);
 283                 return -EINVAL;
 284         }
 285         return pa;
 286 }
 287
 288 static bool gart_iommu_capable(enum iommu_cap cap)
 289 {
 290         return false;
 291 }
 292
 293 static int gart_iommu_add_device(struct device *dev)
 294 {
 295         struct iommu_group *group;
 296
 297         if (!dev->iommu_fwspec)
 298                 return -ENODEV;
 299
 300         group = iommu_group_get_for_dev(dev);
 301         if (IS_ERR(group))
 302                 return PTR_ERR(group);
 303
 304         iommu_group_put(group);
 305
 306         iommu_device_link(&gart_handle->iommu, dev);
 307
 308         return 0;
 309 }
 310
 311 static void gart_iommu_remove_device(struct device *dev)
 312 {
 313         iommu_group_remove_device(dev);
 314         iommu_device_unlink(&gart_handle->iommu, dev);
 315 }
 316
 317 static int gart_iommu_of_xlate(struct device *dev,
 318                                struct of_phandle_args *args)
 319 {
 320         return 0;
 321 }
 322
 323 static void gart_iommu_sync(struct iommu_domain *domain)
 324 {
 325         struct gart_device *gart = gart_handle;
 326
 327         FLUSH_GART_REGS(gart);
 328 }
 329
 330 static const struct iommu_ops gart_iommu_ops = {
 331         .capable        = gart_iommu_capable,
 332         .domain_alloc   = gart_iommu_domain_alloc,
 333         .domain_free    = gart_iommu_domain_free,
 334         .attach_dev     = gart_iommu_attach_dev,
 335         .detach_dev     = gart_iommu_detach_dev,
 336         .add_device     = gart_iommu_add_device,
 337         .remove_device  = gart_iommu_remove_device,
 338         .device_group   = generic_device_group,
 339         .map            = gart_iommu_map,
 340         .unmap          = gart_iommu_unmap,
 341         .iova_to_phys   = gart_iommu_iova_to_phys,
 342         .pgsize_bitmap  = GART_IOMMU_PGSIZES,
 343         .of_xlate       = gart_iommu_of_xlate,
 344         .iotlb_sync_map = gart_iommu_sync,
 345         .iotlb_sync     = gart_iommu_sync,
 346 };
 347
 348 int tegra_gart_suspend(struct gart_device *gart)
 349 {
 350         unsigned long iova;
 351         u32 *data = gart->savedata;
 352         unsigned long flags;
 353
 354         spin_lock_irqsave(&gart->pte_lock, flags);
 355         for_each_gart_pte(gart, iova)
 356                 *(data++) = gart_read_pte(gart, iova);
 357         spin_unlock_irqrestore(&gart->pte_lock, flags);
 358         return 0;
 359 }
 360
 361 int tegra_gart_resume(struct gart_device *gart)
 362 {
 363         unsigned long flags;
 364
 365         spin_lock_irqsave(&gart->pte_lock, flags);
 366         do_gart_setup(gart, gart->savedata);
 367         spin_unlock_irqrestore(&gart->pte_lock, flags);
 368         return 0;
 369 }
 370
 371 struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc)
 372 {
 373         struct gart_device *gart;
 374         struct resource *res_remap;
 375         void __iomem *gart_regs;
 376         int ret;
 377
 378         BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT);
 379
 380         /* the GART memory aperture is required */
 381         res_remap = platform_get_resource(to_platform_device(dev),
 382                                           IORESOURCE_MEM, 1);
 383         if (!res_remap) {
 384                 dev_err(dev, "GART memory aperture expected\n");
 385                 return ERR_PTR(-ENXIO);
 386         }
 387
 388         gart = kzalloc(sizeof(*gart), GFP_KERNEL);
 389         if (!gart) {
 390                 dev_err(dev, "failed to allocate gart_device\n");
 391                 return ERR_PTR(-ENOMEM);
 392         }
 393
 394         ret = iommu_device_sysfs_add(&gart->iommu, dev, NULL, "gart");
 395         if (ret) {
 396                 dev_err(dev, "Failed to register IOMMU in sysfs\n");
 397                 goto free_gart;
 398         }
 399
 400         iommu_device_set_ops(&gart->iommu, &gart_iommu_ops);
 401         iommu_device_set_fwnode(&gart->iommu, dev->fwnode);
 402
 403         ret = iommu_device_register(&gart->iommu);
 404         if (ret) {
 405                 dev_err(dev, "Failed to register IOMMU\n");
 406                 goto remove_sysfs;
 407         }
 408
 409         gart->dev = dev;
 410         gart_regs = mc->regs + GART_REG_BASE;
 411         spin_lock_init(&gart->pte_lock);
 412         spin_lock_init(&gart->dom_lock);
 413         gart->regs = gart_regs;
 414         gart->iovmm_base = (dma_addr_t)res_remap->start;
 415         gart->page_count = (resource_size(res_remap) >> GART_PAGE_SHIFT);
 416
 417         gart->savedata = vmalloc(array_size(sizeof(u32), gart->page_count));
 418         if (!gart->savedata) {
 419                 dev_err(dev, "failed to allocate context save area\n");
 420                 ret = -ENOMEM;
 421                 goto unregister_iommu;
 422         }
 423
 424         do_gart_setup(gart, NULL);
 425
 426         gart_handle = gart;
 427
 428         return gart;
 429
 430 unregister_iommu:
 431         iommu_device_unregister(&gart->iommu);
 432 remove_sysfs:
 433         iommu_device_sysfs_remove(&gart->iommu);
 434 free_gart:
 435         kfree(gart);
 436
 437         return ERR_PTR(ret);
 438 }
 439
 440 module_param(gart_debug, bool, 0644);
 441 MODULE_PARM_DESC(gart_debug, "Enable GART debugging");