drivers/iommu/tegra-gart.c

   1 /*
   2  * IOMMU API for GART in Tegra20
   3  *
   4  * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #define pr_fmt(fmt)     "%s(): " fmt, __func__
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/slab.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/mm.h>
  28 #include <linux/list.h>
  29 #include <linux/device.h>
  30 #include <linux/io.h>
  31 #include <linux/iommu.h>
  32 #include <linux/of.h>
  33
  34 #include <asm/cacheflush.h>
  35
  36 /* bitmap of the page sizes currently supported */
  37 #define GART_IOMMU_PGSIZES      (SZ_4K)
  38
  39 #define GART_REG_BASE           0x24
  40 #define GART_CONFIG             (0x24 - GART_REG_BASE)
  41 #define GART_ENTRY_ADDR         (0x28 - GART_REG_BASE)
  42 #define GART_ENTRY_DATA         (0x2c - GART_REG_BASE)
  43 #define GART_ENTRY_PHYS_ADDR_VALID      (1 << 31)
  44
  45 #define GART_PAGE_SHIFT         12
  46 #define GART_PAGE_SIZE          (1 << GART_PAGE_SHIFT)
  47 #define GART_PAGE_MASK                                          \
  48         (~(GART_PAGE_SIZE - 1) & ~GART_ENTRY_PHYS_ADDR_VALID)
  49
  50 struct gart_client {
  51         struct device           *dev;
  52         struct list_head        list;
  53 };
  54
  55 struct gart_device {
  56         void __iomem            *regs;
  57         u32                     *savedata;
  58         u32                     page_count;     /* total remappable size */
  59         dma_addr_t              iovmm_base;     /* offset to vmm_area */
  60         spinlock_t              pte_lock;       /* for pagetable */
  61         struct list_head        client;
  62         spinlock_t              client_lock;    /* for client list */
  63         struct device           *dev;
  64 };
  65
  66 static struct gart_device *gart_handle; /* unique for a system */
  67
  68 #define GART_PTE(_pfn)                                          \
  69         (GART_ENTRY_PHYS_ADDR_VALID | ((_pfn) << PAGE_SHIFT))
  70
  71 /*
  72  * Any interaction between any block on PPSB and a block on APB or AHB
  73  * must have these read-back to ensure the APB/AHB bus transaction is
  74  * complete before initiating activity on the PPSB block.
  75  */
  76 #define FLUSH_GART_REGS(gart)   ((void)readl((gart)->regs + GART_CONFIG))
  77
  78 #define for_each_gart_pte(gart, iova)                                   \
  79         for (iova = gart->iovmm_base;                                   \
  80              iova < gart->iovmm_base + GART_PAGE_SIZE * gart->page_count; \
  81              iova += GART_PAGE_SIZE)
  82
  83 static inline void gart_set_pte(struct gart_device *gart,
  84                                 unsigned long offs, u32 pte)
  85 {
  86         writel(offs, gart->regs + GART_ENTRY_ADDR);
  87         writel(pte, gart->regs + GART_ENTRY_DATA);
  88
  89         dev_dbg(gart->dev, "%s %08lx:%08x\n",
  90                  pte ? "map" : "unmap", offs, pte & GART_PAGE_MASK);
  91 }
  92
  93 static inline unsigned long gart_read_pte(struct gart_device *gart,
  94                                           unsigned long offs)
  95 {
  96         unsigned long pte;
  97
  98         writel(offs, gart->regs + GART_ENTRY_ADDR);
  99         pte = readl(gart->regs + GART_ENTRY_DATA);
 100
 101         return pte;
 102 }
 103
 104 static void do_gart_setup(struct gart_device *gart, const u32 *data)
 105 {
 106         unsigned long iova;
 107
 108         for_each_gart_pte(gart, iova)
 109                 gart_set_pte(gart, iova, data ? *(data++) : 0);
 110
 111         writel(1, gart->regs + GART_CONFIG);
 112         FLUSH_GART_REGS(gart);
 113 }
 114
 115 #ifdef DEBUG
 116 static void gart_dump_table(struct gart_device *gart)
 117 {
 118         unsigned long iova;
 119         unsigned long flags;
 120
 121         spin_lock_irqsave(&gart->pte_lock, flags);
 122         for_each_gart_pte(gart, iova) {
 123                 unsigned long pte;
 124
 125                 pte = gart_read_pte(gart, iova);
 126
 127                 dev_dbg(gart->dev, "%s %08lx:%08lx\n",
 128                         (GART_ENTRY_PHYS_ADDR_VALID & pte) ? "v" : " ",
 129                         iova, pte & GART_PAGE_MASK);
 130         }
 131         spin_unlock_irqrestore(&gart->pte_lock, flags);
 132 }
 133 #else
 134 static inline void gart_dump_table(struct gart_device *gart)
 135 {
 136 }
 137 #endif
 138
 139 static inline bool gart_iova_range_valid(struct gart_device *gart,
 140                                          unsigned long iova, size_t bytes)
 141 {
 142         unsigned long iova_start, iova_end, gart_start, gart_end;
 143
 144         iova_start = iova;
 145         iova_end = iova_start + bytes - 1;
 146         gart_start = gart->iovmm_base;
 147         gart_end = gart_start + gart->page_count * GART_PAGE_SIZE - 1;
 148
 149         if (iova_start < gart_start)
 150                 return false;
 151         if (iova_end > gart_end)
 152                 return false;
 153         return true;
 154 }
 155
 156 static int gart_iommu_attach_dev(struct iommu_domain *domain,
 157                                  struct device *dev)
 158 {
 159         struct gart_device *gart = domain->priv;
 160         struct gart_client *client, *c;
 161         int err = 0;
 162
 163         client = devm_kzalloc(gart->dev, sizeof(*c), GFP_KERNEL);
 164         if (!client)
 165                 return -ENOMEM;
 166         client->dev = dev;
 167
 168         spin_lock(&gart->client_lock);
 169         list_for_each_entry(c, &gart->client, list) {
 170                 if (c->dev == dev) {
 171                         dev_err(gart->dev,
 172                                 "%s is already attached\n", dev_name(dev));
 173                         err = -EINVAL;
 174                         goto fail;
 175                 }
 176         }
 177         list_add(&client->list, &gart->client);
 178         spin_unlock(&gart->client_lock);
 179         dev_dbg(gart->dev, "Attached %s\n", dev_name(dev));
 180         return 0;
 181
 182 fail:
 183         devm_kfree(gart->dev, client);
 184         spin_unlock(&gart->client_lock);
 185         return err;
 186 }
 187
 188 static void gart_iommu_detach_dev(struct iommu_domain *domain,
 189                                   struct device *dev)
 190 {
 191         struct gart_device *gart = domain->priv;
 192         struct gart_client *c;
 193
 194         spin_lock(&gart->client_lock);
 195
 196         list_for_each_entry(c, &gart->client, list) {
 197                 if (c->dev == dev) {
 198                         list_del(&c->list);
 199                         devm_kfree(gart->dev, c);
 200                         dev_dbg(gart->dev, "Detached %s\n", dev_name(dev));
 201                         goto out;
 202                 }
 203         }
 204         dev_err(gart->dev, "Couldn't find\n");
 205 out:
 206         spin_unlock(&gart->client_lock);
 207 }
 208
 209 static int gart_iommu_domain_init(struct iommu_domain *domain)
 210 {
 211         struct gart_device *gart;
 212
 213         gart = gart_handle;
 214         if (!gart)
 215                 return -EINVAL;
 216
 217         domain->priv = gart;
 218
 219         domain->geometry.aperture_start = gart->iovmm_base;
 220         domain->geometry.aperture_end = gart->iovmm_base +
 221                                         gart->page_count * GART_PAGE_SIZE - 1;
 222         domain->geometry.force_aperture = true;
 223
 224         return 0;
 225 }
 226
 227 static void gart_iommu_domain_destroy(struct iommu_domain *domain)
 228 {
 229         struct gart_device *gart = domain->priv;
 230
 231         if (!gart)
 232                 return;
 233
 234         spin_lock(&gart->client_lock);
 235         if (!list_empty(&gart->client)) {
 236                 struct gart_client *c;
 237
 238                 list_for_each_entry(c, &gart->client, list)
 239                         gart_iommu_detach_dev(domain, c->dev);
 240         }
 241         spin_unlock(&gart->client_lock);
 242         domain->priv = NULL;
 243 }
 244
 245 static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova,
 246                           phys_addr_t pa, size_t bytes, int prot)
 247 {
 248         struct gart_device *gart = domain->priv;
 249         unsigned long flags;
 250         unsigned long pfn;
 251
 252         if (!gart_iova_range_valid(gart, iova, bytes))
 253                 return -EINVAL;
 254
 255         spin_lock_irqsave(&gart->pte_lock, flags);
 256         pfn = __phys_to_pfn(pa);
 257         if (!pfn_valid(pfn)) {
 258                 dev_err(gart->dev, "Invalid page: %pa\n", &pa);
 259                 spin_unlock_irqrestore(&gart->pte_lock, flags);
 260                 return -EINVAL;
 261         }
 262         gart_set_pte(gart, iova, GART_PTE(pfn));
 263         FLUSH_GART_REGS(gart);
 264         spin_unlock_irqrestore(&gart->pte_lock, flags);
 265         return 0;
 266 }
 267
 268 static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
 269                                size_t bytes)
 270 {
 271         struct gart_device *gart = domain->priv;
 272         unsigned long flags;
 273
 274         if (!gart_iova_range_valid(gart, iova, bytes))
 275                 return 0;
 276
 277         spin_lock_irqsave(&gart->pte_lock, flags);
 278         gart_set_pte(gart, iova, 0);
 279         FLUSH_GART_REGS(gart);
 280         spin_unlock_irqrestore(&gart->pte_lock, flags);
 281         return 0;
 282 }
 283
 284 static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
 285                                            dma_addr_t iova)
 286 {
 287         struct gart_device *gart = domain->priv;
 288         unsigned long pte;
 289         phys_addr_t pa;
 290         unsigned long flags;
 291
 292         if (!gart_iova_range_valid(gart, iova, 0))
 293                 return -EINVAL;
 294
 295         spin_lock_irqsave(&gart->pte_lock, flags);
 296         pte = gart_read_pte(gart, iova);
 297         spin_unlock_irqrestore(&gart->pte_lock, flags);
 298
 299         pa = (pte & GART_PAGE_MASK);
 300         if (!pfn_valid(__phys_to_pfn(pa))) {
 301                 dev_err(gart->dev, "No entry for %08llx:%pa\n",
 302                          (unsigned long long)iova, &pa);
 303                 gart_dump_table(gart);
 304                 return -EINVAL;
 305         }
 306         return pa;
 307 }
 308
 309 static bool gart_iommu_capable(enum iommu_cap cap)
 310 {
 311         return false;
 312 }
 313
 314 static const struct iommu_ops gart_iommu_ops = {
 315         .capable        = gart_iommu_capable,
 316         .domain_init    = gart_iommu_domain_init,
 317         .domain_destroy = gart_iommu_domain_destroy,
 318         .attach_dev     = gart_iommu_attach_dev,
 319         .detach_dev     = gart_iommu_detach_dev,
 320         .map            = gart_iommu_map,
 321         .map_sg         = default_iommu_map_sg,
 322         .unmap          = gart_iommu_unmap,
 323         .iova_to_phys   = gart_iommu_iova_to_phys,
 324         .pgsize_bitmap  = GART_IOMMU_PGSIZES,
 325 };
 326
 327 static int tegra_gart_suspend(struct device *dev)
 328 {
 329         struct gart_device *gart = dev_get_drvdata(dev);
 330         unsigned long iova;
 331         u32 *data = gart->savedata;
 332         unsigned long flags;
 333
 334         spin_lock_irqsave(&gart->pte_lock, flags);
 335         for_each_gart_pte(gart, iova)
 336                 *(data++) = gart_read_pte(gart, iova);
 337         spin_unlock_irqrestore(&gart->pte_lock, flags);
 338         return 0;
 339 }
 340
 341 static int tegra_gart_resume(struct device *dev)
 342 {
 343         struct gart_device *gart = dev_get_drvdata(dev);
 344         unsigned long flags;
 345
 346         spin_lock_irqsave(&gart->pte_lock, flags);
 347         do_gart_setup(gart, gart->savedata);
 348         spin_unlock_irqrestore(&gart->pte_lock, flags);
 349         return 0;
 350 }
 351
 352 static int tegra_gart_probe(struct platform_device *pdev)
 353 {
 354         struct gart_device *gart;
 355         struct resource *res, *res_remap;
 356         void __iomem *gart_regs;
 357         struct device *dev = &pdev->dev;
 358
 359         if (gart_handle)
 360                 return -EIO;
 361
 362         BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT);
 363
 364         /* the GART memory aperture is required */
 365         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 366         res_remap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 367         if (!res || !res_remap) {
 368                 dev_err(dev, "GART memory aperture expected\n");
 369                 return -ENXIO;
 370         }
 371
 372         gart = devm_kzalloc(dev, sizeof(*gart), GFP_KERNEL);
 373         if (!gart) {
 374                 dev_err(dev, "failed to allocate gart_device\n");
 375                 return -ENOMEM;
 376         }
 377
 378         gart_regs = devm_ioremap(dev, res->start, resource_size(res));
 379         if (!gart_regs) {
 380                 dev_err(dev, "failed to remap GART registers\n");
 381                 return -ENXIO;
 382         }
 383
 384         gart->dev = &pdev->dev;
 385         spin_lock_init(&gart->pte_lock);
 386         spin_lock_init(&gart->client_lock);
 387         INIT_LIST_HEAD(&gart->client);
 388         gart->regs = gart_regs;
 389         gart->iovmm_base = (dma_addr_t)res_remap->start;
 390         gart->page_count = (resource_size(res_remap) >> GART_PAGE_SHIFT);
 391
 392         gart->savedata = vmalloc(sizeof(u32) * gart->page_count);
 393         if (!gart->savedata) {
 394                 dev_err(dev, "failed to allocate context save area\n");
 395                 return -ENOMEM;
 396         }
 397
 398         platform_set_drvdata(pdev, gart);
 399         do_gart_setup(gart, NULL);
 400
 401         gart_handle = gart;
 402
 403         return 0;
 404 }
 405
 406 static int tegra_gart_remove(struct platform_device *pdev)
 407 {
 408         struct gart_device *gart = platform_get_drvdata(pdev);
 409
 410         writel(0, gart->regs + GART_CONFIG);
 411         if (gart->savedata)
 412                 vfree(gart->savedata);
 413         gart_handle = NULL;
 414         return 0;
 415 }
 416
 417 static const struct dev_pm_ops tegra_gart_pm_ops = {
 418         .suspend        = tegra_gart_suspend,
 419         .resume         = tegra_gart_resume,
 420 };
 421
 422 static const struct of_device_id tegra_gart_of_match[] = {
 423         { .compatible = "nvidia,tegra20-gart", },
 424         { },
 425 };
 426 MODULE_DEVICE_TABLE(of, tegra_gart_of_match);
 427
 428 static struct platform_driver tegra_gart_driver = {
 429         .probe          = tegra_gart_probe,
 430         .remove         = tegra_gart_remove,
 431         .driver = {
 432                 .name   = "tegra-gart",
 433                 .pm     = &tegra_gart_pm_ops,
 434                 .of_match_table = tegra_gart_of_match,
 435         },
 436 };
 437
 438 static int tegra_gart_init(void)
 439 {
 440         return platform_driver_register(&tegra_gart_driver);
 441 }
 442
 443 static void __exit tegra_gart_exit(void)
 444 {
 445         platform_driver_unregister(&tegra_gart_driver);
 446 }
 447
 448 subsys_initcall(tegra_gart_init);
 449 module_exit(tegra_gart_exit);
 450
 451 MODULE_DESCRIPTION("IOMMU API for GART in Tegra20");
 452 MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
 453 MODULE_ALIAS("platform:tegra-gart");
 454 MODULE_LICENSE("GPL v2");