2 * omap iommu: main structures
4 * Copyright (C) 2008-2009 Nokia Corporation
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
19 u32 pgsz, prsvd, valid;
23 u32 endian, elsz, mixed;
30 void __iomem *regbase;
32 struct iommu_domain *domain;
34 spinlock_t iommu_lock; /* global for this whole object */
37 * We don't change iopgd for a situation like pgd for a task,
38 * but share it globally for each iommu.
41 spinlock_t page_table_lock; /* protect iopgd */
45 void *ctx; /* iommu context: registres saved area */
68 * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
69 * @dev: iommu client device
71 static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
73 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
75 return arch_data->iommu_dev;
79 * MMU Register offsets
81 #define MMU_REVISION 0x00
82 #define MMU_IRQSTATUS 0x18
83 #define MMU_IRQENABLE 0x1c
84 #define MMU_WALKING_ST 0x40
86 #define MMU_FAULT_AD 0x48
89 #define MMU_LD_TLB 0x54
92 #define MMU_GFLUSH 0x60
93 #define MMU_FLUSH_ENTRY 0x64
94 #define MMU_READ_CAM 0x68
95 #define MMU_READ_RAM 0x6c
96 #define MMU_EMU_FAULT_AD 0x70
97 #define MMU_GP_REG 0x88
99 #define MMU_REG_SIZE 256
102 * MMU Register bit definitions
104 /* IRQSTATUS & IRQENABLE */
105 #define MMU_IRQ_MULTIHITFAULT (1 << 4)
106 #define MMU_IRQ_TABLEWALKFAULT (1 << 3)
107 #define MMU_IRQ_EMUMISS (1 << 2)
108 #define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
109 #define MMU_IRQ_TLBMISS (1 << 0)
111 #define __MMU_IRQ_FAULT \
112 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
113 #define MMU_IRQ_MASK \
114 (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
115 #define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
116 #define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
119 #define MMU_CNTL_SHIFT 1
120 #define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
121 #define MMU_CNTL_EML_TLB (1 << 3)
122 #define MMU_CNTL_TWL_EN (1 << 2)
123 #define MMU_CNTL_MMU_EN (1 << 1)
126 #define MMU_CAM_VATAG_SHIFT 12
127 #define MMU_CAM_VATAG_MASK \
128 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
129 #define MMU_CAM_P (1 << 3)
130 #define MMU_CAM_V (1 << 2)
131 #define MMU_CAM_PGSZ_MASK 3
132 #define MMU_CAM_PGSZ_1M (0 << 0)
133 #define MMU_CAM_PGSZ_64K (1 << 0)
134 #define MMU_CAM_PGSZ_4K (2 << 0)
135 #define MMU_CAM_PGSZ_16M (3 << 0)
138 #define MMU_RAM_PADDR_SHIFT 12
139 #define MMU_RAM_PADDR_MASK \
140 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
142 #define MMU_RAM_ENDIAN_SHIFT 9
143 #define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
144 #define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
145 #define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
147 #define MMU_RAM_ELSZ_SHIFT 7
148 #define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
149 #define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
150 #define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
151 #define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
152 #define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
153 #define MMU_RAM_MIXED_SHIFT 6
154 #define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
155 #define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
157 #define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
159 #define get_cam_va_mask(pgsz) \
160 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
161 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
162 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
163 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
166 * utilities for super page(16MB, 1MB, 64KB and 4KB)
169 #define iopgsz_max(bytes) \
170 (((bytes) >= SZ_16M) ? SZ_16M : \
171 ((bytes) >= SZ_1M) ? SZ_1M : \
172 ((bytes) >= SZ_64K) ? SZ_64K : \
173 ((bytes) >= SZ_4K) ? SZ_4K : 0)
175 #define bytes_to_iopgsz(bytes) \
176 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
177 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
178 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
179 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
181 #define iopgsz_to_bytes(iopgsz) \
182 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
183 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
184 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
185 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
187 #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
192 extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
195 omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
197 extern int omap_foreach_iommu_device(void *data,
198 int (*fn)(struct device *, void *));
201 omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
203 omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
208 static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
210 return __raw_readl(obj->regbase + offs);
213 static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
215 __raw_writel(val, obj->regbase + offs);
218 #endif /* _OMAP_IOMMU_H */