drivers/iommu/ipmmu-vmsa.c

   1 /*
   2  * IPMMU VMSA
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  */
  10
  11 #include <linux/bitmap.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-iommu.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/err.h>
  16 #include <linux/export.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iommu.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_iommu.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/sizes.h>
  27 #include <linux/slab.h>
  28
  29 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
  30 #include <asm/dma-iommu.h>
  31 #include <asm/pgalloc.h>
  32 #else
  33 #define arm_iommu_create_mapping(...)   NULL
  34 #define arm_iommu_attach_device(...)    -ENODEV
  35 #define arm_iommu_release_mapping(...)  do {} while (0)
  36 #define arm_iommu_detach_device(...)    do {} while (0)
  37 #endif
  38
  39 #include "io-pgtable.h"
  40
  41 #define IPMMU_CTX_MAX 8
  42
  43 struct ipmmu_features {
  44         bool use_ns_alias_offset;
  45         bool has_cache_leaf_nodes;
  46         unsigned int number_of_contexts;
  47         bool setup_imbuscr;
  48 };
  49
  50 struct ipmmu_vmsa_device {
  51         struct device *dev;
  52         void __iomem *base;
  53         struct iommu_device iommu;
  54         struct ipmmu_vmsa_device *root;
  55         const struct ipmmu_features *features;
  56         unsigned int num_utlbs;
  57         unsigned int num_ctx;
  58         spinlock_t lock;                        /* Protects ctx and domains[] */
  59         DECLARE_BITMAP(ctx, IPMMU_CTX_MAX);
  60         struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
  61
  62         struct iommu_group *group;
  63         struct dma_iommu_mapping *mapping;
  64 };
  65
  66 struct ipmmu_vmsa_domain {
  67         struct ipmmu_vmsa_device *mmu;
  68         struct iommu_domain io_domain;
  69
  70         struct io_pgtable_cfg cfg;
  71         struct io_pgtable_ops *iop;
  72
  73         unsigned int context_id;
  74         spinlock_t lock;                        /* Protects mappings */
  75 };
  76
  77 static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom)
  78 {
  79         return container_of(dom, struct ipmmu_vmsa_domain, io_domain);
  80 }
  81
  82 static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
  83 {
  84         return dev->iommu_fwspec ? dev->iommu_fwspec->iommu_priv : NULL;
  85 }
  86
  87 #define TLB_LOOP_TIMEOUT                100     /* 100us */
  88
  89 /* -----------------------------------------------------------------------------
  90  * Registers Definition
  91  */
  92
  93 #define IM_NS_ALIAS_OFFSET              0x800
  94
  95 #define IM_CTX_SIZE                     0x40
  96
  97 #define IMCTR                           0x0000
  98 #define IMCTR_TRE                       (1 << 17)
  99 #define IMCTR_AFE                       (1 << 16)
 100 #define IMCTR_RTSEL_MASK                (3 << 4)
 101 #define IMCTR_RTSEL_SHIFT               4
 102 #define IMCTR_TREN                      (1 << 3)
 103 #define IMCTR_INTEN                     (1 << 2)
 104 #define IMCTR_FLUSH                     (1 << 1)
 105 #define IMCTR_MMUEN                     (1 << 0)
 106
 107 #define IMCAAR                          0x0004
 108
 109 #define IMTTBCR                         0x0008
 110 #define IMTTBCR_EAE                     (1 << 31)
 111 #define IMTTBCR_PMB                     (1 << 30)
 112 #define IMTTBCR_SH1_NON_SHAREABLE       (0 << 28)
 113 #define IMTTBCR_SH1_OUTER_SHAREABLE     (2 << 28)
 114 #define IMTTBCR_SH1_INNER_SHAREABLE     (3 << 28)
 115 #define IMTTBCR_SH1_MASK                (3 << 28)
 116 #define IMTTBCR_ORGN1_NC                (0 << 26)
 117 #define IMTTBCR_ORGN1_WB_WA             (1 << 26)
 118 #define IMTTBCR_ORGN1_WT                (2 << 26)
 119 #define IMTTBCR_ORGN1_WB                (3 << 26)
 120 #define IMTTBCR_ORGN1_MASK              (3 << 26)
 121 #define IMTTBCR_IRGN1_NC                (0 << 24)
 122 #define IMTTBCR_IRGN1_WB_WA             (1 << 24)
 123 #define IMTTBCR_IRGN1_WT                (2 << 24)
 124 #define IMTTBCR_IRGN1_WB                (3 << 24)
 125 #define IMTTBCR_IRGN1_MASK              (3 << 24)
 126 #define IMTTBCR_TSZ1_MASK               (7 << 16)
 127 #define IMTTBCR_TSZ1_SHIFT              16
 128 #define IMTTBCR_SH0_NON_SHAREABLE       (0 << 12)
 129 #define IMTTBCR_SH0_OUTER_SHAREABLE     (2 << 12)
 130 #define IMTTBCR_SH0_INNER_SHAREABLE     (3 << 12)
 131 #define IMTTBCR_SH0_MASK                (3 << 12)
 132 #define IMTTBCR_ORGN0_NC                (0 << 10)
 133 #define IMTTBCR_ORGN0_WB_WA             (1 << 10)
 134 #define IMTTBCR_ORGN0_WT                (2 << 10)
 135 #define IMTTBCR_ORGN0_WB                (3 << 10)
 136 #define IMTTBCR_ORGN0_MASK              (3 << 10)
 137 #define IMTTBCR_IRGN0_NC                (0 << 8)
 138 #define IMTTBCR_IRGN0_WB_WA             (1 << 8)
 139 #define IMTTBCR_IRGN0_WT                (2 << 8)
 140 #define IMTTBCR_IRGN0_WB                (3 << 8)
 141 #define IMTTBCR_IRGN0_MASK              (3 << 8)
 142 #define IMTTBCR_SL0_LVL_2               (0 << 4)
 143 #define IMTTBCR_SL0_LVL_1               (1 << 4)
 144 #define IMTTBCR_TSZ0_MASK               (7 << 0)
 145 #define IMTTBCR_TSZ0_SHIFT              O
 146
 147 #define IMBUSCR                         0x000c
 148 #define IMBUSCR_DVM                     (1 << 2)
 149 #define IMBUSCR_BUSSEL_SYS              (0 << 0)
 150 #define IMBUSCR_BUSSEL_CCI              (1 << 0)
 151 #define IMBUSCR_BUSSEL_IMCAAR           (2 << 0)
 152 #define IMBUSCR_BUSSEL_CCI_IMCAAR       (3 << 0)
 153 #define IMBUSCR_BUSSEL_MASK             (3 << 0)
 154
 155 #define IMTTLBR0                        0x0010
 156 #define IMTTUBR0                        0x0014
 157 #define IMTTLBR1                        0x0018
 158 #define IMTTUBR1                        0x001c
 159
 160 #define IMSTR                           0x0020
 161 #define IMSTR_ERRLVL_MASK               (3 << 12)
 162 #define IMSTR_ERRLVL_SHIFT              12
 163 #define IMSTR_ERRCODE_TLB_FORMAT        (1 << 8)
 164 #define IMSTR_ERRCODE_ACCESS_PERM       (4 << 8)
 165 #define IMSTR_ERRCODE_SECURE_ACCESS     (5 << 8)
 166 #define IMSTR_ERRCODE_MASK              (7 << 8)
 167 #define IMSTR_MHIT                      (1 << 4)
 168 #define IMSTR_ABORT                     (1 << 2)
 169 #define IMSTR_PF                        (1 << 1)
 170 #define IMSTR_TF                        (1 << 0)
 171
 172 #define IMMAIR0                         0x0028
 173 #define IMMAIR1                         0x002c
 174 #define IMMAIR_ATTR_MASK                0xff
 175 #define IMMAIR_ATTR_DEVICE              0x04
 176 #define IMMAIR_ATTR_NC                  0x44
 177 #define IMMAIR_ATTR_WBRWA               0xff
 178 #define IMMAIR_ATTR_SHIFT(n)            ((n) << 3)
 179 #define IMMAIR_ATTR_IDX_NC              0
 180 #define IMMAIR_ATTR_IDX_WBRWA           1
 181 #define IMMAIR_ATTR_IDX_DEV             2
 182
 183 #define IMEAR                           0x0030
 184
 185 #define IMPCTR                          0x0200
 186 #define IMPSTR                          0x0208
 187 #define IMPEAR                          0x020c
 188 #define IMPMBA(n)                       (0x0280 + ((n) * 4))
 189 #define IMPMBD(n)                       (0x02c0 + ((n) * 4))
 190
 191 #define IMUCTR(n)                       (0x0300 + ((n) * 16))
 192 #define IMUCTR_FIXADDEN                 (1 << 31)
 193 #define IMUCTR_FIXADD_MASK              (0xff << 16)
 194 #define IMUCTR_FIXADD_SHIFT             16
 195 #define IMUCTR_TTSEL_MMU(n)             ((n) << 4)
 196 #define IMUCTR_TTSEL_PMB                (8 << 4)
 197 #define IMUCTR_TTSEL_MASK               (15 << 4)
 198 #define IMUCTR_FLUSH                    (1 << 1)
 199 #define IMUCTR_MMUEN                    (1 << 0)
 200
 201 #define IMUASID(n)                      (0x0308 + ((n) * 16))
 202 #define IMUASID_ASID8_MASK              (0xff << 8)
 203 #define IMUASID_ASID8_SHIFT             8
 204 #define IMUASID_ASID0_MASK              (0xff << 0)
 205 #define IMUASID_ASID0_SHIFT             0
 206
 207 /* -----------------------------------------------------------------------------
 208  * Root device handling
 209  */
 210
 211 static struct platform_driver ipmmu_driver;
 212
 213 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu)
 214 {
 215         return mmu->root == mmu;
 216 }
 217
 218 static int __ipmmu_check_device(struct device *dev, void *data)
 219 {
 220         struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
 221         struct ipmmu_vmsa_device **rootp = data;
 222
 223         if (ipmmu_is_root(mmu))
 224                 *rootp = mmu;
 225
 226         return 0;
 227 }
 228
 229 static struct ipmmu_vmsa_device *ipmmu_find_root(void)
 230 {
 231         struct ipmmu_vmsa_device *root = NULL;
 232
 233         return driver_for_each_device(&ipmmu_driver.driver, NULL, &root,
 234                                       __ipmmu_check_device) == 0 ? root : NULL;
 235 }
 236
 237 /* -----------------------------------------------------------------------------
 238  * Read/Write Access
 239  */
 240
 241 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset)
 242 {
 243         return ioread32(mmu->base + offset);
 244 }
 245
 246 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
 247                         u32 data)
 248 {
 249         iowrite32(data, mmu->base + offset);
 250 }
 251
 252 static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain,
 253                                unsigned int reg)
 254 {
 255         return ipmmu_read(domain->mmu->root,
 256                           domain->context_id * IM_CTX_SIZE + reg);
 257 }
 258
 259 static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain,
 260                                  unsigned int reg, u32 data)
 261 {
 262         ipmmu_write(domain->mmu->root,
 263                     domain->context_id * IM_CTX_SIZE + reg, data);
 264 }
 265
 266 static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain,
 267                                 unsigned int reg, u32 data)
 268 {
 269         if (domain->mmu != domain->mmu->root)
 270                 ipmmu_write(domain->mmu,
 271                             domain->context_id * IM_CTX_SIZE + reg, data);
 272
 273         ipmmu_write(domain->mmu->root,
 274                     domain->context_id * IM_CTX_SIZE + reg, data);
 275 }
 276
 277 /* -----------------------------------------------------------------------------
 278  * TLB and microTLB Management
 279  */
 280
 281 /* Wait for any pending TLB invalidations to complete */
 282 static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain)
 283 {
 284         unsigned int count = 0;
 285
 286         while (ipmmu_ctx_read_root(domain, IMCTR) & IMCTR_FLUSH) {
 287                 cpu_relax();
 288                 if (++count == TLB_LOOP_TIMEOUT) {
 289                         dev_err_ratelimited(domain->mmu->dev,
 290                         "TLB sync timed out -- MMU may be deadlocked\n");
 291                         return;
 292                 }
 293                 udelay(1);
 294         }
 295 }
 296
 297 static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain)
 298 {
 299         u32 reg;
 300
 301         reg = ipmmu_ctx_read_root(domain, IMCTR);
 302         reg |= IMCTR_FLUSH;
 303         ipmmu_ctx_write_all(domain, IMCTR, reg);
 304
 305         ipmmu_tlb_sync(domain);
 306 }
 307
 308 /*
 309  * Enable MMU translation for the microTLB.
 310  */
 311 static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain,
 312                               unsigned int utlb)
 313 {
 314         struct ipmmu_vmsa_device *mmu = domain->mmu;
 315
 316         /*
 317          * TODO: Reference-count the microTLB as several bus masters can be
 318          * connected to the same microTLB.
 319          */
 320
 321         /* TODO: What should we set the ASID to ? */
 322         ipmmu_write(mmu, IMUASID(utlb), 0);
 323         /* TODO: Do we need to flush the microTLB ? */
 324         ipmmu_write(mmu, IMUCTR(utlb),
 325                     IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_FLUSH |
 326                     IMUCTR_MMUEN);
 327 }
 328
 329 /*
 330  * Disable MMU translation for the microTLB.
 331  */
 332 static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain,
 333                                unsigned int utlb)
 334 {
 335         struct ipmmu_vmsa_device *mmu = domain->mmu;
 336
 337         ipmmu_write(mmu, IMUCTR(utlb), 0);
 338 }
 339
 340 static void ipmmu_tlb_flush_all(void *cookie)
 341 {
 342         struct ipmmu_vmsa_domain *domain = cookie;
 343
 344         ipmmu_tlb_invalidate(domain);
 345 }
 346
 347 static void ipmmu_tlb_add_flush(unsigned long iova, size_t size,
 348                                 size_t granule, bool leaf, void *cookie)
 349 {
 350         /* The hardware doesn't support selective TLB flush. */
 351 }
 352
 353 static const struct iommu_gather_ops ipmmu_gather_ops = {
 354         .tlb_flush_all = ipmmu_tlb_flush_all,
 355         .tlb_add_flush = ipmmu_tlb_add_flush,
 356         .tlb_sync = ipmmu_tlb_flush_all,
 357 };
 358
 359 /* -----------------------------------------------------------------------------
 360  * Domain/Context Management
 361  */
 362
 363 static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu,
 364                                          struct ipmmu_vmsa_domain *domain)
 365 {
 366         unsigned long flags;
 367         int ret;
 368
 369         spin_lock_irqsave(&mmu->lock, flags);
 370
 371         ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx);
 372         if (ret != mmu->num_ctx) {
 373                 mmu->domains[ret] = domain;
 374                 set_bit(ret, mmu->ctx);
 375         } else
 376                 ret = -EBUSY;
 377
 378         spin_unlock_irqrestore(&mmu->lock, flags);
 379
 380         return ret;
 381 }
 382
 383 static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu,
 384                                       unsigned int context_id)
 385 {
 386         unsigned long flags;
 387
 388         spin_lock_irqsave(&mmu->lock, flags);
 389
 390         clear_bit(context_id, mmu->ctx);
 391         mmu->domains[context_id] = NULL;
 392
 393         spin_unlock_irqrestore(&mmu->lock, flags);
 394 }
 395
 396 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
 397 {
 398         u64 ttbr;
 399         int ret;
 400
 401         /*
 402          * Allocate the page table operations.
 403          *
 404          * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
 405          * access, Long-descriptor format" that the NStable bit being set in a
 406          * table descriptor will result in the NStable and NS bits of all child
 407          * entries being ignored and considered as being set. The IPMMU seems
 408          * not to comply with this, as it generates a secure access page fault
 409          * if any of the NStable and NS bits isn't set when running in
 410          * non-secure mode.
 411          */
 412         domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
 413         domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;
 414         domain->cfg.ias = 32;
 415         domain->cfg.oas = 40;
 416         domain->cfg.tlb = &ipmmu_gather_ops;
 417         domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32);
 418         domain->io_domain.geometry.force_aperture = true;
 419         /*
 420          * TODO: Add support for coherent walk through CCI with DVM and remove
 421          * cache handling. For now, delegate it to the io-pgtable code.
 422          */
 423         domain->cfg.iommu_dev = domain->mmu->root->dev;
 424
 425         /*
 426          * Find an unused context.
 427          */
 428         ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
 429         if (ret < 0)
 430                 return ret;
 431
 432         domain->context_id = ret;
 433
 434         domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
 435                                            domain);
 436         if (!domain->iop) {
 437                 ipmmu_domain_free_context(domain->mmu->root,
 438                                           domain->context_id);
 439                 return -EINVAL;
 440         }
 441
 442         /* TTBR0 */
 443         ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0];
 444         ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr);
 445         ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32);
 446
 447         /*
 448          * TTBCR
 449          * We use long descriptors with inner-shareable WBWA tables and allocate
 450          * the whole 32-bit VA space to TTBR0.
 451          */
 452         ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE |
 453                              IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
 454                              IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1);
 455
 456         /* MAIR0 */
 457         ipmmu_ctx_write_root(domain, IMMAIR0,
 458                              domain->cfg.arm_lpae_s1_cfg.mair[0]);
 459
 460         /* IMBUSCR */
 461         if (domain->mmu->features->setup_imbuscr)
 462                 ipmmu_ctx_write_root(domain, IMBUSCR,
 463                                      ipmmu_ctx_read_root(domain, IMBUSCR) &
 464                                      ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
 465
 466         /*
 467          * IMSTR
 468          * Clear all interrupt flags.
 469          */
 470         ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR));
 471
 472         /*
 473          * IMCTR
 474          * Enable the MMU and interrupt generation. The long-descriptor
 475          * translation table format doesn't use TEX remapping. Don't enable AF
 476          * software management as we have no use for it. Flush the TLB as
 477          * required when modifying the context registers.
 478          */
 479         ipmmu_ctx_write_all(domain, IMCTR,
 480                             IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
 481
 482         return 0;
 483 }
 484
 485 static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
 486 {
 487         /*
 488          * Disable the context. Flush the TLB as required when modifying the
 489          * context registers.
 490          *
 491          * TODO: Is TLB flush really needed ?
 492          */
 493         ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH);
 494         ipmmu_tlb_sync(domain);
 495         ipmmu_domain_free_context(domain->mmu->root, domain->context_id);
 496 }
 497
 498 /* -----------------------------------------------------------------------------
 499  * Fault Handling
 500  */
 501
 502 static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
 503 {
 504         const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF;
 505         struct ipmmu_vmsa_device *mmu = domain->mmu;
 506         u32 status;
 507         u32 iova;
 508
 509         status = ipmmu_ctx_read_root(domain, IMSTR);
 510         if (!(status & err_mask))
 511                 return IRQ_NONE;
 512
 513         iova = ipmmu_ctx_read_root(domain, IMEAR);
 514
 515         /*
 516          * Clear the error status flags. Unlike traditional interrupt flag
 517          * registers that must be cleared by writing 1, this status register
 518          * seems to require 0. The error address register must be read before,
 519          * otherwise its value will be 0.
 520          */
 521         ipmmu_ctx_write_root(domain, IMSTR, 0);
 522
 523         /* Log fatal errors. */
 524         if (status & IMSTR_MHIT)
 525                 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%08x\n",
 526                                     iova);
 527         if (status & IMSTR_ABORT)
 528                 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%08x\n",
 529                                     iova);
 530
 531         if (!(status & (IMSTR_PF | IMSTR_TF)))
 532                 return IRQ_NONE;
 533
 534         /*
 535          * Try to handle page faults and translation faults.
 536          *
 537          * TODO: We need to look up the faulty device based on the I/O VA. Use
 538          * the IOMMU device for now.
 539          */
 540         if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0))
 541                 return IRQ_HANDLED;
 542
 543         dev_err_ratelimited(mmu->dev,
 544                             "Unhandled fault: status 0x%08x iova 0x%08x\n",
 545                             status, iova);
 546
 547         return IRQ_HANDLED;
 548 }
 549
 550 static irqreturn_t ipmmu_irq(int irq, void *dev)
 551 {
 552         struct ipmmu_vmsa_device *mmu = dev;
 553         irqreturn_t status = IRQ_NONE;
 554         unsigned int i;
 555         unsigned long flags;
 556
 557         spin_lock_irqsave(&mmu->lock, flags);
 558
 559         /*
 560          * Check interrupts for all active contexts.
 561          */
 562         for (i = 0; i < mmu->num_ctx; i++) {
 563                 if (!mmu->domains[i])
 564                         continue;
 565                 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED)
 566                         status = IRQ_HANDLED;
 567         }
 568
 569         spin_unlock_irqrestore(&mmu->lock, flags);
 570
 571         return status;
 572 }
 573
 574 /* -----------------------------------------------------------------------------
 575  * IOMMU Operations
 576  */
 577
 578 static struct iommu_domain *__ipmmu_domain_alloc(unsigned type)
 579 {
 580         struct ipmmu_vmsa_domain *domain;
 581
 582         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 583         if (!domain)
 584                 return NULL;
 585
 586         spin_lock_init(&domain->lock);
 587
 588         return &domain->io_domain;
 589 }
 590
 591 static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
 592 {
 593         struct iommu_domain *io_domain = NULL;
 594
 595         switch (type) {
 596         case IOMMU_DOMAIN_UNMANAGED:
 597                 io_domain = __ipmmu_domain_alloc(type);
 598                 break;
 599
 600         case IOMMU_DOMAIN_DMA:
 601                 io_domain = __ipmmu_domain_alloc(type);
 602                 if (io_domain && iommu_get_dma_cookie(io_domain)) {
 603                         kfree(io_domain);
 604                         io_domain = NULL;
 605                 }
 606                 break;
 607         }
 608
 609         return io_domain;
 610 }
 611
 612 static void ipmmu_domain_free(struct iommu_domain *io_domain)
 613 {
 614         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 615
 616         /*
 617          * Free the domain resources. We assume that all devices have already
 618          * been detached.
 619          */
 620         iommu_put_dma_cookie(io_domain);
 621         ipmmu_domain_destroy_context(domain);
 622         free_io_pgtable_ops(domain->iop);
 623         kfree(domain);
 624 }
 625
 626 static int ipmmu_attach_device(struct iommu_domain *io_domain,
 627                                struct device *dev)
 628 {
 629         struct iommu_fwspec *fwspec = dev->iommu_fwspec;
 630         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 631         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 632         unsigned long flags;
 633         unsigned int i;
 634         int ret = 0;
 635
 636         if (!mmu) {
 637                 dev_err(dev, "Cannot attach to IPMMU\n");
 638                 return -ENXIO;
 639         }
 640
 641         spin_lock_irqsave(&domain->lock, flags);
 642
 643         if (!domain->mmu) {
 644                 /* The domain hasn't been used yet, initialize it. */
 645                 domain->mmu = mmu;
 646                 ret = ipmmu_domain_init_context(domain);
 647                 if (ret < 0) {
 648                         dev_err(dev, "Unable to initialize IPMMU context\n");
 649                         domain->mmu = NULL;
 650                 } else {
 651                         dev_info(dev, "Using IPMMU context %u\n",
 652                                  domain->context_id);
 653                 }
 654         } else if (domain->mmu != mmu) {
 655                 /*
 656                  * Something is wrong, we can't attach two devices using
 657                  * different IOMMUs to the same domain.
 658                  */
 659                 dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n",
 660                         dev_name(mmu->dev), dev_name(domain->mmu->dev));
 661                 ret = -EINVAL;
 662         } else
 663                 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id);
 664
 665         spin_unlock_irqrestore(&domain->lock, flags);
 666
 667         if (ret < 0)
 668                 return ret;
 669
 670         for (i = 0; i < fwspec->num_ids; ++i)
 671                 ipmmu_utlb_enable(domain, fwspec->ids[i]);
 672
 673         return 0;
 674 }
 675
 676 static void ipmmu_detach_device(struct iommu_domain *io_domain,
 677                                 struct device *dev)
 678 {
 679         struct iommu_fwspec *fwspec = dev->iommu_fwspec;
 680         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 681         unsigned int i;
 682
 683         for (i = 0; i < fwspec->num_ids; ++i)
 684                 ipmmu_utlb_disable(domain, fwspec->ids[i]);
 685
 686         /*
 687          * TODO: Optimize by disabling the context when no device is attached.
 688          */
 689 }
 690
 691 static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
 692                      phys_addr_t paddr, size_t size, int prot)
 693 {
 694         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 695
 696         if (!domain)
 697                 return -ENODEV;
 698
 699         return domain->iop->map(domain->iop, iova, paddr, size, prot);
 700 }
 701
 702 static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
 703                           size_t size)
 704 {
 705         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 706
 707         return domain->iop->unmap(domain->iop, iova, size);
 708 }
 709
 710 static void ipmmu_iotlb_sync(struct iommu_domain *io_domain)
 711 {
 712         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 713
 714         if (domain->mmu)
 715                 ipmmu_tlb_flush_all(domain);
 716 }
 717
 718 static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
 719                                       dma_addr_t iova)
 720 {
 721         struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
 722
 723         /* TODO: Is locking needed ? */
 724
 725         return domain->iop->iova_to_phys(domain->iop, iova);
 726 }
 727
 728 static int ipmmu_init_platform_device(struct device *dev,
 729                                       struct of_phandle_args *args)
 730 {
 731         struct platform_device *ipmmu_pdev;
 732
 733         ipmmu_pdev = of_find_device_by_node(args->np);
 734         if (!ipmmu_pdev)
 735                 return -ENODEV;
 736
 737         dev->iommu_fwspec->iommu_priv = platform_get_drvdata(ipmmu_pdev);
 738         return 0;
 739 }
 740
 741 static int ipmmu_of_xlate(struct device *dev,
 742                           struct of_phandle_args *spec)
 743 {
 744         iommu_fwspec_add_ids(dev, spec->args, 1);
 745
 746         /* Initialize once - xlate() will call multiple times */
 747         if (to_ipmmu(dev))
 748                 return 0;
 749
 750         return ipmmu_init_platform_device(dev, spec);
 751 }
 752
 753 static int ipmmu_init_arm_mapping(struct device *dev)
 754 {
 755         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 756         struct iommu_group *group;
 757         int ret;
 758
 759         /* Create a device group and add the device to it. */
 760         group = iommu_group_alloc();
 761         if (IS_ERR(group)) {
 762                 dev_err(dev, "Failed to allocate IOMMU group\n");
 763                 return PTR_ERR(group);
 764         }
 765
 766         ret = iommu_group_add_device(group, dev);
 767         iommu_group_put(group);
 768
 769         if (ret < 0) {
 770                 dev_err(dev, "Failed to add device to IPMMU group\n");
 771                 return ret;
 772         }
 773
 774         /*
 775          * Create the ARM mapping, used by the ARM DMA mapping core to allocate
 776          * VAs. This will allocate a corresponding IOMMU domain.
 777          *
 778          * TODO:
 779          * - Create one mapping per context (TLB).
 780          * - Make the mapping size configurable ? We currently use a 2GB mapping
 781          *   at a 1GB offset to ensure that NULL VAs will fault.
 782          */
 783         if (!mmu->mapping) {
 784                 struct dma_iommu_mapping *mapping;
 785
 786                 mapping = arm_iommu_create_mapping(&platform_bus_type,
 787                                                    SZ_1G, SZ_2G);
 788                 if (IS_ERR(mapping)) {
 789                         dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n");
 790                         ret = PTR_ERR(mapping);
 791                         goto error;
 792                 }
 793
 794                 mmu->mapping = mapping;
 795         }
 796
 797         /* Attach the ARM VA mapping to the device. */
 798         ret = arm_iommu_attach_device(dev, mmu->mapping);
 799         if (ret < 0) {
 800                 dev_err(dev, "Failed to attach device to VA mapping\n");
 801                 goto error;
 802         }
 803
 804         return 0;
 805
 806 error:
 807         iommu_group_remove_device(dev);
 808         if (mmu->mapping)
 809                 arm_iommu_release_mapping(mmu->mapping);
 810
 811         return ret;
 812 }
 813
 814 static int ipmmu_add_device(struct device *dev)
 815 {
 816         struct iommu_group *group;
 817
 818         /*
 819          * Only let through devices that have been verified in xlate()
 820          */
 821         if (!to_ipmmu(dev))
 822                 return -ENODEV;
 823
 824         if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA))
 825                 return ipmmu_init_arm_mapping(dev);
 826
 827         group = iommu_group_get_for_dev(dev);
 828         if (IS_ERR(group))
 829                 return PTR_ERR(group);
 830
 831         iommu_group_put(group);
 832         return 0;
 833 }
 834
 835 static void ipmmu_remove_device(struct device *dev)
 836 {
 837         arm_iommu_detach_device(dev);
 838         iommu_group_remove_device(dev);
 839 }
 840
 841 static struct iommu_group *ipmmu_find_group(struct device *dev)
 842 {
 843         struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
 844         struct iommu_group *group;
 845
 846         if (mmu->group)
 847                 return iommu_group_ref_get(mmu->group);
 848
 849         group = iommu_group_alloc();
 850         if (!IS_ERR(group))
 851                 mmu->group = group;
 852
 853         return group;
 854 }
 855
 856 static const struct iommu_ops ipmmu_ops = {
 857         .domain_alloc = ipmmu_domain_alloc,
 858         .domain_free = ipmmu_domain_free,
 859         .attach_dev = ipmmu_attach_device,
 860         .detach_dev = ipmmu_detach_device,
 861         .map = ipmmu_map,
 862         .unmap = ipmmu_unmap,
 863         .flush_iotlb_all = ipmmu_iotlb_sync,
 864         .iotlb_sync = ipmmu_iotlb_sync,
 865         .map_sg = default_iommu_map_sg,
 866         .iova_to_phys = ipmmu_iova_to_phys,
 867         .add_device = ipmmu_add_device,
 868         .remove_device = ipmmu_remove_device,
 869         .device_group = ipmmu_find_group,
 870         .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
 871         .of_xlate = ipmmu_of_xlate,
 872 };
 873
 874 /* -----------------------------------------------------------------------------
 875  * Probe/remove and init
 876  */
 877
 878 static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
 879 {
 880         unsigned int i;
 881
 882         /* Disable all contexts. */
 883         for (i = 0; i < mmu->num_ctx; ++i)
 884                 ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0);
 885 }
 886
 887 static const struct ipmmu_features ipmmu_features_default = {
 888         .use_ns_alias_offset = true,
 889         .has_cache_leaf_nodes = false,
 890         .number_of_contexts = 1, /* software only tested with one context */
 891         .setup_imbuscr = true,
 892 };
 893
 894 static const struct of_device_id ipmmu_of_ids[] = {
 895         {
 896                 .compatible = "renesas,ipmmu-vmsa",
 897                 .data = &ipmmu_features_default,
 898         }, {
 899                 /* Terminator */
 900         },
 901 };
 902
 903 MODULE_DEVICE_TABLE(of, ipmmu_of_ids);
 904
 905 static int ipmmu_probe(struct platform_device *pdev)
 906 {
 907         struct ipmmu_vmsa_device *mmu;
 908         struct resource *res;
 909         int irq;
 910         int ret;
 911
 912         mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL);
 913         if (!mmu) {
 914                 dev_err(&pdev->dev, "cannot allocate device data\n");
 915                 return -ENOMEM;
 916         }
 917
 918         mmu->dev = &pdev->dev;
 919         mmu->num_utlbs = 32;
 920         spin_lock_init(&mmu->lock);
 921         bitmap_zero(mmu->ctx, IPMMU_CTX_MAX);
 922         mmu->features = of_device_get_match_data(&pdev->dev);
 923         dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
 924
 925         /* Map I/O memory and request IRQ. */
 926         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 927         mmu->base = devm_ioremap_resource(&pdev->dev, res);
 928         if (IS_ERR(mmu->base))
 929                 return PTR_ERR(mmu->base);
 930
 931         /*
 932          * The IPMMU has two register banks, for secure and non-secure modes.
 933          * The bank mapped at the beginning of the IPMMU address space
 934          * corresponds to the running mode of the CPU. When running in secure
 935          * mode the non-secure register bank is also available at an offset.
 936          *
 937          * Secure mode operation isn't clearly documented and is thus currently
 938          * not implemented in the driver. Furthermore, preliminary tests of
 939          * non-secure operation with the main register bank were not successful.
 940          * Offset the registers base unconditionally to point to the non-secure
 941          * alias space for now.
 942          */
 943         if (mmu->features->use_ns_alias_offset)
 944                 mmu->base += IM_NS_ALIAS_OFFSET;
 945
 946         mmu->num_ctx = min_t(unsigned int, IPMMU_CTX_MAX,
 947                              mmu->features->number_of_contexts);
 948
 949         irq = platform_get_irq(pdev, 0);
 950
 951         /*
 952          * Determine if this IPMMU instance is a root device by checking for
 953          * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property.
 954          */
 955         if (!mmu->features->has_cache_leaf_nodes ||
 956             !of_find_property(pdev->dev.of_node, "renesas,ipmmu-main", NULL))
 957                 mmu->root = mmu;
 958         else
 959                 mmu->root = ipmmu_find_root();
 960
 961         /*
 962          * Wait until the root device has been registered for sure.
 963          */
 964         if (!mmu->root)
 965                 return -EPROBE_DEFER;
 966
 967         /* Root devices have mandatory IRQs */
 968         if (ipmmu_is_root(mmu)) {
 969                 if (irq < 0) {
 970                         dev_err(&pdev->dev, "no IRQ found\n");
 971                         return irq;
 972                 }
 973
 974                 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
 975                                        dev_name(&pdev->dev), mmu);
 976                 if (ret < 0) {
 977                         dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
 978                         return ret;
 979                 }
 980
 981                 ipmmu_device_reset(mmu);
 982         }
 983
 984         /*
 985          * Register the IPMMU to the IOMMU subsystem in the following cases:
 986          * - R-Car Gen2 IPMMU (all devices registered)
 987          * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device)
 988          */
 989         if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) {
 990                 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL,
 991                                              dev_name(&pdev->dev));
 992                 if (ret)
 993                         return ret;
 994
 995                 iommu_device_set_ops(&mmu->iommu, &ipmmu_ops);
 996                 iommu_device_set_fwnode(&mmu->iommu,
 997                                         &pdev->dev.of_node->fwnode);
 998
 999                 ret = iommu_device_register(&mmu->iommu);
1000                 if (ret)
1001                         return ret;
1002
1003 #if defined(CONFIG_IOMMU_DMA)
1004                 if (!iommu_present(&platform_bus_type))
1005                         bus_set_iommu(&platform_bus_type, &ipmmu_ops);
1006 #endif
1007         }
1008
1009         /*
1010          * We can't create the ARM mapping here as it requires the bus to have
1011          * an IOMMU, which only happens when bus_set_iommu() is called in
1012          * ipmmu_init() after the probe function returns.
1013          */
1014
1015         platform_set_drvdata(pdev, mmu);
1016
1017         return 0;
1018 }
1019
1020 static int ipmmu_remove(struct platform_device *pdev)
1021 {
1022         struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev);
1023
1024         iommu_device_sysfs_remove(&mmu->iommu);
1025         iommu_device_unregister(&mmu->iommu);
1026
1027         arm_iommu_release_mapping(mmu->mapping);
1028
1029         ipmmu_device_reset(mmu);
1030
1031         return 0;
1032 }
1033
1034 static struct platform_driver ipmmu_driver = {
1035         .driver = {
1036                 .name = "ipmmu-vmsa",
1037                 .of_match_table = of_match_ptr(ipmmu_of_ids),
1038         },
1039         .probe = ipmmu_probe,
1040         .remove = ipmmu_remove,
1041 };
1042
1043 static int __init ipmmu_init(void)
1044 {
1045         static bool setup_done;
1046         int ret;
1047
1048         if (setup_done)
1049                 return 0;
1050
1051         ret = platform_driver_register(&ipmmu_driver);
1052         if (ret < 0)
1053                 return ret;
1054
1055 #if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
1056         if (!iommu_present(&platform_bus_type))
1057                 bus_set_iommu(&platform_bus_type, &ipmmu_ops);
1058 #endif
1059
1060         setup_done = true;
1061         return 0;
1062 }
1063
1064 static void __exit ipmmu_exit(void)
1065 {
1066         return platform_driver_unregister(&ipmmu_driver);
1067 }
1068
1069 subsys_initcall(ipmmu_init);
1070 module_exit(ipmmu_exit);
1071
1072 #ifdef CONFIG_IOMMU_DMA
1073 static int __init ipmmu_vmsa_iommu_of_setup(struct device_node *np)
1074 {
1075         ipmmu_init();
1076         return 0;
1077 }
1078
1079 IOMMU_OF_DECLARE(ipmmu_vmsa_iommu_of, "renesas,ipmmu-vmsa",
1080                  ipmmu_vmsa_iommu_of_setup);
1081 #endif
1082
1083 MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU");
1084 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1085 MODULE_LICENSE("GPL v2");