2 * CPU-agnostic ARM page table allocator.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * Copyright (C) 2014 ARM Limited
18 * Author: Will Deacon <will.deacon@arm.com>
21 #define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt
23 #include <linux/iommu.h>
24 #include <linux/kernel.h>
25 #include <linux/sizes.h>
26 #include <linux/slab.h>
27 #include <linux/types.h>
29 #include <asm/barrier.h>
31 #include "io-pgtable.h"
33 #define ARM_LPAE_MAX_ADDR_BITS 48
34 #define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
35 #define ARM_LPAE_MAX_LEVELS 4
37 /* Struct accessors */
38 #define io_pgtable_to_data(x) \
39 container_of((x), struct arm_lpae_io_pgtable, iop)
41 #define io_pgtable_ops_to_pgtable(x) \
42 container_of((x), struct io_pgtable, ops)
44 #define io_pgtable_ops_to_data(x) \
45 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
48 * For consistency with the architecture, we always consider
49 * ARM_LPAE_MAX_LEVELS levels, with the walk starting at level n >=0
51 #define ARM_LPAE_START_LVL(d) (ARM_LPAE_MAX_LEVELS - (d)->levels)
54 * Calculate the right shift amount to get to the portion describing level l
55 * in a virtual address mapped by the pagetable in d.
57 #define ARM_LPAE_LVL_SHIFT(l,d) \
58 ((((d)->levels - ((l) - ARM_LPAE_START_LVL(d) + 1)) \
59 * (d)->bits_per_level) + (d)->pg_shift)
61 #define ARM_LPAE_PAGES_PER_PGD(d) \
62 DIV_ROUND_UP((d)->pgd_size, 1UL << (d)->pg_shift)
65 * Calculate the index at level l used to map virtual address a using the
68 #define ARM_LPAE_PGD_IDX(l,d) \
69 ((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0)
71 #define ARM_LPAE_LVL_IDX(a,l,d) \
72 (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
73 ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
75 /* Calculate the block/page mapping size at level l for pagetable in d. */
76 #define ARM_LPAE_BLOCK_SIZE(l,d) \
77 (1 << (ilog2(sizeof(arm_lpae_iopte)) + \
78 ((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level)))
81 #define ARM_LPAE_PTE_TYPE_SHIFT 0
82 #define ARM_LPAE_PTE_TYPE_MASK 0x3
84 #define ARM_LPAE_PTE_TYPE_BLOCK 1
85 #define ARM_LPAE_PTE_TYPE_TABLE 3
86 #define ARM_LPAE_PTE_TYPE_PAGE 3
88 #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
89 #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
90 #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
91 #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8)
92 #define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8)
93 #define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8)
94 #define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5)
95 #define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0)
97 #define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2)
98 /* Ignore the contiguous bit for block splitting */
99 #define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52)
100 #define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \
101 ARM_LPAE_PTE_ATTR_HI_MASK)
104 #define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6)
105 #define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6)
106 #define ARM_LPAE_PTE_ATTRINDX_SHIFT 2
107 #define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11)
110 #define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
111 #define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
112 #define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
113 #define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2)
114 #define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2)
115 #define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
118 #define ARM_32_LPAE_TCR_EAE (1 << 31)
119 #define ARM_64_LPAE_S2_TCR_RES1 (1 << 31)
121 #define ARM_LPAE_TCR_EPD1 (1 << 23)
123 #define ARM_LPAE_TCR_TG0_4K (0 << 14)
124 #define ARM_LPAE_TCR_TG0_64K (1 << 14)
125 #define ARM_LPAE_TCR_TG0_16K (2 << 14)
127 #define ARM_LPAE_TCR_SH0_SHIFT 12
128 #define ARM_LPAE_TCR_SH0_MASK 0x3
129 #define ARM_LPAE_TCR_SH_NS 0
130 #define ARM_LPAE_TCR_SH_OS 2
131 #define ARM_LPAE_TCR_SH_IS 3
133 #define ARM_LPAE_TCR_ORGN0_SHIFT 10
134 #define ARM_LPAE_TCR_IRGN0_SHIFT 8
135 #define ARM_LPAE_TCR_RGN_MASK 0x3
136 #define ARM_LPAE_TCR_RGN_NC 0
137 #define ARM_LPAE_TCR_RGN_WBWA 1
138 #define ARM_LPAE_TCR_RGN_WT 2
139 #define ARM_LPAE_TCR_RGN_WB 3
141 #define ARM_LPAE_TCR_SL0_SHIFT 6
142 #define ARM_LPAE_TCR_SL0_MASK 0x3
144 #define ARM_LPAE_TCR_T0SZ_SHIFT 0
145 #define ARM_LPAE_TCR_SZ_MASK 0xf
147 #define ARM_LPAE_TCR_PS_SHIFT 16
148 #define ARM_LPAE_TCR_PS_MASK 0x7
150 #define ARM_LPAE_TCR_IPS_SHIFT 32
151 #define ARM_LPAE_TCR_IPS_MASK 0x7
153 #define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
154 #define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
155 #define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
156 #define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
157 #define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
158 #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
160 #define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
161 #define ARM_LPAE_MAIR_ATTR_MASK 0xff
162 #define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
163 #define ARM_LPAE_MAIR_ATTR_NC 0x44
164 #define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
165 #define ARM_LPAE_MAIR_ATTR_IDX_NC 0
166 #define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
167 #define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
169 /* IOPTE accessors */
170 #define iopte_deref(pte,d) \
171 (__va((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1) \
172 & ~((1ULL << (d)->pg_shift) - 1)))
174 #define iopte_type(pte,l) \
175 (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
177 #define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
179 #define iopte_leaf(pte,l) \
180 (l == (ARM_LPAE_MAX_LEVELS - 1) ? \
181 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_PAGE) : \
182 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_BLOCK))
184 #define iopte_to_pfn(pte,d) \
185 (((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1)) >> (d)->pg_shift)
187 #define pfn_to_iopte(pfn,d) \
188 (((pfn) << (d)->pg_shift) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1))
190 struct arm_lpae_io_pgtable {
191 struct io_pgtable iop;
195 unsigned long pg_shift;
196 unsigned long bits_per_level;
201 typedef u64 arm_lpae_iopte;
203 static bool selftest_running = false;
205 static dma_addr_t __arm_lpae_dma_addr(struct device *dev, void *pages)
207 return phys_to_dma(dev, virt_to_phys(pages));
210 static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
211 struct io_pgtable_cfg *cfg)
213 struct device *dev = cfg->iommu_dev;
215 void *pages = alloc_pages_exact(size, gfp | __GFP_ZERO);
220 if (!selftest_running) {
221 dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE);
222 if (dma_mapping_error(dev, dma))
225 * We depend on the IOMMU being able to work with any physical
226 * address directly, so if the DMA layer suggests it can't by
227 * giving us back some translation, that bodes very badly...
229 if (dma != __arm_lpae_dma_addr(dev, pages))
236 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
237 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
239 free_pages_exact(pages, size);
243 static void __arm_lpae_free_pages(void *pages, size_t size,
244 struct io_pgtable_cfg *cfg)
246 struct device *dev = cfg->iommu_dev;
248 if (!selftest_running)
249 dma_unmap_single(dev, __arm_lpae_dma_addr(dev, pages),
250 size, DMA_TO_DEVICE);
251 free_pages_exact(pages, size);
254 static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte,
255 struct io_pgtable_cfg *cfg)
257 struct device *dev = cfg->iommu_dev;
261 if (!selftest_running)
262 dma_sync_single_for_device(dev, __arm_lpae_dma_addr(dev, ptep),
263 sizeof(pte), DMA_TO_DEVICE);
266 static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
267 unsigned long iova, phys_addr_t paddr,
268 arm_lpae_iopte prot, int lvl,
269 arm_lpae_iopte *ptep)
271 arm_lpae_iopte pte = prot;
272 struct io_pgtable_cfg *cfg = &data->iop.cfg;
274 /* We require an unmap first */
275 if (iopte_leaf(*ptep, lvl)) {
276 WARN_ON(!selftest_running);
280 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
281 pte |= ARM_LPAE_PTE_NS;
283 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
284 pte |= ARM_LPAE_PTE_TYPE_PAGE;
286 pte |= ARM_LPAE_PTE_TYPE_BLOCK;
288 pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_IS;
289 pte |= pfn_to_iopte(paddr >> data->pg_shift, data);
291 __arm_lpae_set_pte(ptep, pte, cfg);
295 static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
296 phys_addr_t paddr, size_t size, arm_lpae_iopte prot,
297 int lvl, arm_lpae_iopte *ptep)
299 arm_lpae_iopte *cptep, pte;
300 size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
301 struct io_pgtable_cfg *cfg = &data->iop.cfg;
303 /* Find our entry at the current level */
304 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
306 /* If we can install a leaf entry at this level, then do so */
307 if (size == block_size && (size & cfg->pgsize_bitmap))
308 return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep);
310 /* We can't allocate tables at the final level */
311 if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1))
314 /* Grab a pointer to the next level */
317 cptep = __arm_lpae_alloc_pages(1UL << data->pg_shift,
322 pte = __pa(cptep) | ARM_LPAE_PTE_TYPE_TABLE;
323 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
324 pte |= ARM_LPAE_PTE_NSTABLE;
325 __arm_lpae_set_pte(ptep, pte, cfg);
327 cptep = iopte_deref(pte, data);
331 return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep);
334 static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
339 if (data->iop.fmt == ARM_64_LPAE_S1 ||
340 data->iop.fmt == ARM_32_LPAE_S1) {
341 pte = ARM_LPAE_PTE_AP_UNPRIV | ARM_LPAE_PTE_nG;
343 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
344 pte |= ARM_LPAE_PTE_AP_RDONLY;
346 if (prot & IOMMU_CACHE)
347 pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
348 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
350 pte = ARM_LPAE_PTE_HAP_FAULT;
351 if (prot & IOMMU_READ)
352 pte |= ARM_LPAE_PTE_HAP_READ;
353 if (prot & IOMMU_WRITE)
354 pte |= ARM_LPAE_PTE_HAP_WRITE;
355 if (prot & IOMMU_CACHE)
356 pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
358 pte |= ARM_LPAE_PTE_MEMATTR_NC;
361 if (prot & IOMMU_NOEXEC)
362 pte |= ARM_LPAE_PTE_XN;
367 static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
368 phys_addr_t paddr, size_t size, int iommu_prot)
370 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
371 arm_lpae_iopte *ptep = data->pgd;
372 int ret, lvl = ARM_LPAE_START_LVL(data);
375 /* If no access, then nothing to do */
376 if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
379 prot = arm_lpae_prot_to_pte(data, iommu_prot);
380 ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep);
382 * Synchronise all PTE updates for the new mapping before there's
383 * a chance for anything to kick off a table walk for the new iova.
390 static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
391 arm_lpae_iopte *ptep)
393 arm_lpae_iopte *start, *end;
394 unsigned long table_size;
396 /* Only leaf entries at the last level */
397 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
400 if (lvl == ARM_LPAE_START_LVL(data))
401 table_size = data->pgd_size;
403 table_size = 1UL << data->pg_shift;
406 end = (void *)ptep + table_size;
408 while (ptep != end) {
409 arm_lpae_iopte pte = *ptep++;
411 if (!pte || iopte_leaf(pte, lvl))
414 __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
417 __arm_lpae_free_pages(start, table_size, &data->iop.cfg);
420 static void arm_lpae_free_pgtable(struct io_pgtable *iop)
422 struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop);
424 __arm_lpae_free_pgtable(data, ARM_LPAE_START_LVL(data), data->pgd);
428 static int arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
429 unsigned long iova, size_t size,
430 arm_lpae_iopte prot, int lvl,
431 arm_lpae_iopte *ptep, size_t blk_size)
433 unsigned long blk_start, blk_end;
434 phys_addr_t blk_paddr;
435 arm_lpae_iopte table = 0;
436 struct io_pgtable_cfg *cfg = &data->iop.cfg;
438 blk_start = iova & ~(blk_size - 1);
439 blk_end = blk_start + blk_size;
440 blk_paddr = iopte_to_pfn(*ptep, data) << data->pg_shift;
442 for (; blk_start < blk_end; blk_start += size, blk_paddr += size) {
443 arm_lpae_iopte *tablep;
446 if (blk_start == iova)
449 /* __arm_lpae_map expects a pointer to the start of the table */
450 tablep = &table - ARM_LPAE_LVL_IDX(blk_start, lvl, data);
451 if (__arm_lpae_map(data, blk_start, blk_paddr, size, prot, lvl,
454 /* Free the table we allocated */
455 tablep = iopte_deref(table, data);
456 __arm_lpae_free_pgtable(data, lvl + 1, tablep);
458 return 0; /* Bytes unmapped */
462 __arm_lpae_set_pte(ptep, table, cfg);
463 iova &= ~(blk_size - 1);
464 cfg->tlb->tlb_add_flush(iova, blk_size, true, data->iop.cookie);
468 static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
469 unsigned long iova, size_t size, int lvl,
470 arm_lpae_iopte *ptep)
473 const struct iommu_gather_ops *tlb = data->iop.cfg.tlb;
474 void *cookie = data->iop.cookie;
475 size_t blk_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
477 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
480 /* Something went horribly wrong and we ran out of page table */
481 if (WARN_ON(!pte || (lvl == ARM_LPAE_MAX_LEVELS)))
484 /* If the size matches this level, we're in the right place */
485 if (size == blk_size) {
486 __arm_lpae_set_pte(ptep, 0, &data->iop.cfg);
488 if (!iopte_leaf(pte, lvl)) {
489 /* Also flush any partial walks */
490 tlb->tlb_add_flush(iova, size, false, cookie);
491 tlb->tlb_sync(cookie);
492 ptep = iopte_deref(pte, data);
493 __arm_lpae_free_pgtable(data, lvl + 1, ptep);
495 tlb->tlb_add_flush(iova, size, true, cookie);
499 } else if (iopte_leaf(pte, lvl)) {
501 * Insert a table at the next level to map the old region,
502 * minus the part we want to unmap
504 return arm_lpae_split_blk_unmap(data, iova, size,
505 iopte_prot(pte), lvl, ptep,
509 /* Keep on walkin' */
510 ptep = iopte_deref(pte, data);
511 return __arm_lpae_unmap(data, iova, size, lvl + 1, ptep);
514 static int arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
518 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
519 struct io_pgtable *iop = &data->iop;
520 arm_lpae_iopte *ptep = data->pgd;
521 int lvl = ARM_LPAE_START_LVL(data);
523 unmapped = __arm_lpae_unmap(data, iova, size, lvl, ptep);
525 iop->cfg.tlb->tlb_sync(iop->cookie);
530 static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
533 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
534 arm_lpae_iopte pte, *ptep = data->pgd;
535 int lvl = ARM_LPAE_START_LVL(data);
538 /* Valid IOPTE pointer? */
542 /* Grab the IOPTE we're interested in */
543 pte = *(ptep + ARM_LPAE_LVL_IDX(iova, lvl, data));
550 if (iopte_leaf(pte,lvl))
551 goto found_translation;
553 /* Take it to the next level */
554 ptep = iopte_deref(pte, data);
555 } while (++lvl < ARM_LPAE_MAX_LEVELS);
557 /* Ran out of page tables to walk */
561 iova &= ((1 << data->pg_shift) - 1);
562 return ((phys_addr_t)iopte_to_pfn(pte,data) << data->pg_shift) | iova;
565 static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
567 unsigned long granule;
570 * We need to restrict the supported page sizes to match the
571 * translation regime for a particular granule. Aim to match
572 * the CPU page size if possible, otherwise prefer smaller sizes.
573 * While we're at it, restrict the block sizes to match the
576 if (cfg->pgsize_bitmap & PAGE_SIZE)
578 else if (cfg->pgsize_bitmap & ~PAGE_MASK)
579 granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK);
580 else if (cfg->pgsize_bitmap & PAGE_MASK)
581 granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK);
587 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
590 cfg->pgsize_bitmap &= (SZ_16K | SZ_32M);
593 cfg->pgsize_bitmap &= (SZ_64K | SZ_512M);
596 cfg->pgsize_bitmap = 0;
600 static struct arm_lpae_io_pgtable *
601 arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
603 unsigned long va_bits, pgd_bits;
604 struct arm_lpae_io_pgtable *data;
606 arm_lpae_restrict_pgsizes(cfg);
608 if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K)))
611 if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS)
614 if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS)
617 data = kmalloc(sizeof(*data), GFP_KERNEL);
621 data->pg_shift = __ffs(cfg->pgsize_bitmap);
622 data->bits_per_level = data->pg_shift - ilog2(sizeof(arm_lpae_iopte));
624 va_bits = cfg->ias - data->pg_shift;
625 data->levels = DIV_ROUND_UP(va_bits, data->bits_per_level);
627 /* Calculate the actual size of our pgd (without concatenation) */
628 pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1));
629 data->pgd_size = 1UL << (pgd_bits + ilog2(sizeof(arm_lpae_iopte)));
631 data->iop.ops = (struct io_pgtable_ops) {
633 .unmap = arm_lpae_unmap,
634 .iova_to_phys = arm_lpae_iova_to_phys,
640 static struct io_pgtable *
641 arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
644 struct arm_lpae_io_pgtable *data = arm_lpae_alloc_pgtable(cfg);
650 reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
651 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
652 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
654 switch (1 << data->pg_shift) {
656 reg |= ARM_LPAE_TCR_TG0_4K;
659 reg |= ARM_LPAE_TCR_TG0_16K;
662 reg |= ARM_LPAE_TCR_TG0_64K;
668 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_IPS_SHIFT);
671 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_IPS_SHIFT);
674 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_IPS_SHIFT);
677 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_IPS_SHIFT);
680 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_IPS_SHIFT);
683 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_IPS_SHIFT);
689 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
691 /* Disable speculative walks through TTBR1 */
692 reg |= ARM_LPAE_TCR_EPD1;
693 cfg->arm_lpae_s1_cfg.tcr = reg;
696 reg = (ARM_LPAE_MAIR_ATTR_NC
697 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
698 (ARM_LPAE_MAIR_ATTR_WBRWA
699 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
700 (ARM_LPAE_MAIR_ATTR_DEVICE
701 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
703 cfg->arm_lpae_s1_cfg.mair[0] = reg;
704 cfg->arm_lpae_s1_cfg.mair[1] = 0;
706 /* Looking good; allocate a pgd */
707 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
711 /* Ensure the empty pgd is visible before any actual TTBR write */
715 cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd);
716 cfg->arm_lpae_s1_cfg.ttbr[1] = 0;
724 static struct io_pgtable *
725 arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
728 struct arm_lpae_io_pgtable *data = arm_lpae_alloc_pgtable(cfg);
734 * Concatenate PGDs at level 1 if possible in order to reduce
735 * the depth of the stage-2 walk.
737 if (data->levels == ARM_LPAE_MAX_LEVELS) {
738 unsigned long pgd_pages;
740 pgd_pages = data->pgd_size >> ilog2(sizeof(arm_lpae_iopte));
741 if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) {
742 data->pgd_size = pgd_pages << data->pg_shift;
748 reg = ARM_64_LPAE_S2_TCR_RES1 |
749 (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
750 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
751 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
753 sl = ARM_LPAE_START_LVL(data);
755 switch (1 << data->pg_shift) {
757 reg |= ARM_LPAE_TCR_TG0_4K;
758 sl++; /* SL0 format is different for 4K granule size */
761 reg |= ARM_LPAE_TCR_TG0_16K;
764 reg |= ARM_LPAE_TCR_TG0_64K;
770 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_PS_SHIFT);
773 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_PS_SHIFT);
776 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_PS_SHIFT);
779 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_PS_SHIFT);
782 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_PS_SHIFT);
785 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT);
791 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
792 reg |= (~sl & ARM_LPAE_TCR_SL0_MASK) << ARM_LPAE_TCR_SL0_SHIFT;
793 cfg->arm_lpae_s2_cfg.vtcr = reg;
795 /* Allocate pgd pages */
796 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
800 /* Ensure the empty pgd is visible before any actual TTBR write */
804 cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd);
812 static struct io_pgtable *
813 arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
815 struct io_pgtable *iop;
817 if (cfg->ias > 32 || cfg->oas > 40)
820 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
821 iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
823 cfg->arm_lpae_s1_cfg.tcr |= ARM_32_LPAE_TCR_EAE;
824 cfg->arm_lpae_s1_cfg.tcr &= 0xffffffff;
830 static struct io_pgtable *
831 arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
833 struct io_pgtable *iop;
835 if (cfg->ias > 40 || cfg->oas > 40)
838 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
839 iop = arm_64_lpae_alloc_pgtable_s2(cfg, cookie);
841 cfg->arm_lpae_s2_cfg.vtcr &= 0xffffffff;
846 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
847 .alloc = arm_64_lpae_alloc_pgtable_s1,
848 .free = arm_lpae_free_pgtable,
851 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = {
852 .alloc = arm_64_lpae_alloc_pgtable_s2,
853 .free = arm_lpae_free_pgtable,
856 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = {
857 .alloc = arm_32_lpae_alloc_pgtable_s1,
858 .free = arm_lpae_free_pgtable,
861 struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = {
862 .alloc = arm_32_lpae_alloc_pgtable_s2,
863 .free = arm_lpae_free_pgtable,
866 #ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST
868 static struct io_pgtable_cfg *cfg_cookie;
870 static void dummy_tlb_flush_all(void *cookie)
872 WARN_ON(cookie != cfg_cookie);
875 static void dummy_tlb_add_flush(unsigned long iova, size_t size, bool leaf,
878 WARN_ON(cookie != cfg_cookie);
879 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
882 static void dummy_tlb_sync(void *cookie)
884 WARN_ON(cookie != cfg_cookie);
887 static struct iommu_gather_ops dummy_tlb_ops __initdata = {
888 .tlb_flush_all = dummy_tlb_flush_all,
889 .tlb_add_flush = dummy_tlb_add_flush,
890 .tlb_sync = dummy_tlb_sync,
893 static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops)
895 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
896 struct io_pgtable_cfg *cfg = &data->iop.cfg;
898 pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n",
899 cfg->pgsize_bitmap, cfg->ias);
900 pr_err("data: %d levels, 0x%zx pgd_size, %lu pg_shift, %lu bits_per_level, pgd @ %p\n",
901 data->levels, data->pgd_size, data->pg_shift,
902 data->bits_per_level, data->pgd);
905 #define __FAIL(ops, i) ({ \
906 WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \
907 arm_lpae_dump_ops(ops); \
908 selftest_running = false; \
912 static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
914 static const enum io_pgtable_fmt fmts[] = {
922 struct io_pgtable_ops *ops;
924 selftest_running = true;
926 for (i = 0; i < ARRAY_SIZE(fmts); ++i) {
928 ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg);
930 pr_err("selftest: failed to allocate io pgtable ops\n");
935 * Initial sanity checks.
936 * Empty page tables shouldn't provide any translations.
938 if (ops->iova_to_phys(ops, 42))
939 return __FAIL(ops, i);
941 if (ops->iova_to_phys(ops, SZ_1G + 42))
942 return __FAIL(ops, i);
944 if (ops->iova_to_phys(ops, SZ_2G + 42))
945 return __FAIL(ops, i);
948 * Distinct mappings of different granule sizes.
951 j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG);
952 while (j != BITS_PER_LONG) {
955 if (ops->map(ops, iova, iova, size, IOMMU_READ |
959 return __FAIL(ops, i);
961 /* Overlapping mappings */
962 if (!ops->map(ops, iova, iova + size, size,
963 IOMMU_READ | IOMMU_NOEXEC))
964 return __FAIL(ops, i);
966 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
967 return __FAIL(ops, i);
971 j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j);
975 size = 1UL << __ffs(cfg->pgsize_bitmap);
976 if (ops->unmap(ops, SZ_1G + size, size) != size)
977 return __FAIL(ops, i);
979 /* Remap of partial unmap */
980 if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ))
981 return __FAIL(ops, i);
983 if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42))
984 return __FAIL(ops, i);
988 j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG);
989 while (j != BITS_PER_LONG) {
992 if (ops->unmap(ops, iova, size) != size)
993 return __FAIL(ops, i);
995 if (ops->iova_to_phys(ops, iova + 42))
996 return __FAIL(ops, i);
998 /* Remap full block */
999 if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
1000 return __FAIL(ops, i);
1002 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1003 return __FAIL(ops, i);
1007 j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j);
1010 free_io_pgtable_ops(ops);
1013 selftest_running = false;
1017 static int __init arm_lpae_do_selftests(void)
1019 static const unsigned long pgsize[] = {
1020 SZ_4K | SZ_2M | SZ_1G,
1025 static const unsigned int ias[] = {
1026 32, 36, 40, 42, 44, 48,
1029 int i, j, pass = 0, fail = 0;
1030 struct io_pgtable_cfg cfg = {
1031 .tlb = &dummy_tlb_ops,
1035 for (i = 0; i < ARRAY_SIZE(pgsize); ++i) {
1036 for (j = 0; j < ARRAY_SIZE(ias); ++j) {
1037 cfg.pgsize_bitmap = pgsize[i];
1039 pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n",
1041 if (arm_lpae_run_tests(&cfg))
1048 pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail);
1049 return fail ? -EFAULT : 0;
1051 subsys_initcall(arm_lpae_do_selftests);