drivers/iommu/intel-svm.c

   1 /*
   2  * Copyright © 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * Authors: David Woodhouse <dwmw2@infradead.org>
  14  */
  15
  16 #include <linux/intel-iommu.h>
  17 #include <linux/mmu_notifier.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/mm.h>
  20 #include <linux/slab.h>
  21 #include <linux/intel-svm.h>
  22 #include <linux/rculist.h>
  23 #include <linux/pci.h>
  24 #include <linux/pci-ats.h>
  25 #include <linux/dmar.h>
  26 #include <linux/interrupt.h>
  27 #include <asm/page.h>
  28
  29 #include "intel-pasid.h"
  30
  31 #define PASID_ENTRY_P           BIT_ULL(0)
  32 #define PASID_ENTRY_FLPM_5LP    BIT_ULL(9)
  33 #define PASID_ENTRY_SRE         BIT_ULL(11)
  34
  35 static irqreturn_t prq_event_thread(int irq, void *d);
  36
  37 struct pasid_state_entry {
  38         u64 val;
  39 };
  40
  41 int intel_svm_init(struct intel_iommu *iommu)
  42 {
  43         struct page *pages;
  44         int order;
  45
  46         if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
  47                         !cap_fl1gp_support(iommu->cap))
  48                 return -EINVAL;
  49
  50         if (cpu_feature_enabled(X86_FEATURE_LA57) &&
  51                         !cap_5lp_support(iommu->cap))
  52                 return -EINVAL;
  53
  54         /* Start at 2 because it's defined as 2^(1+PSS) */
  55         iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
  56
  57         /* Eventually I'm promised we will get a multi-level PASID table
  58          * and it won't have to be physically contiguous. Until then,
  59          * limit the size because 8MiB contiguous allocations can be hard
  60          * to come by. The limit of 0x20000, which is 1MiB for each of
  61          * the PASID and PASID-state tables, is somewhat arbitrary. */
  62         if (iommu->pasid_max > 0x20000)
  63                 iommu->pasid_max = 0x20000;
  64
  65         order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
  66         if (ecap_dis(iommu->ecap)) {
  67                 /* Just making it explicit... */
  68                 BUILD_BUG_ON(sizeof(struct pasid_entry) != sizeof(struct pasid_state_entry));
  69                 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
  70                 if (pages)
  71                         iommu->pasid_state_table = page_address(pages);
  72                 else
  73                         pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
  74                                 iommu->name);
  75         }
  76
  77         return 0;
  78 }
  79
  80 int intel_svm_exit(struct intel_iommu *iommu)
  81 {
  82         int order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
  83
  84         if (iommu->pasid_state_table) {
  85                 free_pages((unsigned long)iommu->pasid_state_table, order);
  86                 iommu->pasid_state_table = NULL;
  87         }
  88
  89         return 0;
  90 }
  91
  92 #define PRQ_ORDER 0
  93
  94 int intel_svm_enable_prq(struct intel_iommu *iommu)
  95 {
  96         struct page *pages;
  97         int irq, ret;
  98
  99         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
 100         if (!pages) {
 101                 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
 102                         iommu->name);
 103                 return -ENOMEM;
 104         }
 105         iommu->prq = page_address(pages);
 106
 107         irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
 108         if (irq <= 0) {
 109                 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
 110                        iommu->name);
 111                 ret = -EINVAL;
 112         err:
 113                 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 114                 iommu->prq = NULL;
 115                 return ret;
 116         }
 117         iommu->pr_irq = irq;
 118
 119         snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
 120
 121         ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
 122                                    iommu->prq_name, iommu);
 123         if (ret) {
 124                 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
 125                        iommu->name);
 126                 dmar_free_hwirq(irq);
 127                 iommu->pr_irq = 0;
 128                 goto err;
 129         }
 130         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
 131         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
 132         dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
 133
 134         return 0;
 135 }
 136
 137 int intel_svm_finish_prq(struct intel_iommu *iommu)
 138 {
 139         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
 140         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
 141         dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
 142
 143         if (iommu->pr_irq) {
 144                 free_irq(iommu->pr_irq, iommu);
 145                 dmar_free_hwirq(iommu->pr_irq);
 146                 iommu->pr_irq = 0;
 147         }
 148
 149         free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 150         iommu->prq = NULL;
 151
 152         return 0;
 153 }
 154
 155 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
 156                                        unsigned long address, unsigned long pages, int ih, int gl)
 157 {
 158         struct qi_desc desc;
 159
 160         if (pages == -1) {
 161                 /* For global kernel pages we have to flush them in *all* PASIDs
 162                  * because that's the only option the hardware gives us. Despite
 163                  * the fact that they are actually only accessible through one. */
 164                 if (gl)
 165                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 166                                 QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | QI_EIOTLB_TYPE;
 167                 else
 168                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 169                                 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
 170                 desc.high = 0;
 171         } else {
 172                 int mask = ilog2(__roundup_pow_of_two(pages));
 173
 174                 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 175                         QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
 176                 desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) |
 177                         QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
 178         }
 179         qi_submit_sync(&desc, svm->iommu);
 180
 181         if (sdev->dev_iotlb) {
 182                 desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
 183                         QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
 184                 if (pages == -1) {
 185                         desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE;
 186                 } else if (pages > 1) {
 187                         /* The least significant zero bit indicates the size. So,
 188                          * for example, an "address" value of 0x12345f000 will
 189                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
 190                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
 191                         unsigned long mask = __rounddown_pow_of_two(address ^ last);
 192
 193                         desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
 194                 } else {
 195                         desc.high = QI_DEV_EIOTLB_ADDR(address);
 196                 }
 197                 qi_submit_sync(&desc, svm->iommu);
 198         }
 199 }
 200
 201 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
 202                                   unsigned long pages, int ih, int gl)
 203 {
 204         struct intel_svm_dev *sdev;
 205
 206         /* Try deferred invalidate if available */
 207         if (svm->iommu->pasid_state_table &&
 208             !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
 209                 return;
 210
 211         rcu_read_lock();
 212         list_for_each_entry_rcu(sdev, &svm->devs, list)
 213                 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
 214         rcu_read_unlock();
 215 }
 216
 217 static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
 218                              unsigned long address, pte_t pte)
 219 {
 220         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 221
 222         intel_flush_svm_range(svm, address, 1, 1, 0);
 223 }
 224
 225 /* Pages have been freed at this point */
 226 static void intel_invalidate_range(struct mmu_notifier *mn,
 227                                    struct mm_struct *mm,
 228                                    unsigned long start, unsigned long end)
 229 {
 230         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 231
 232         intel_flush_svm_range(svm, start,
 233                               (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
 234 }
 235
 236
 237 static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev, int pasid)
 238 {
 239         struct qi_desc desc;
 240
 241         desc.high = 0;
 242         desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
 243
 244         qi_submit_sync(&desc, svm->iommu);
 245 }
 246
 247 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
 248 {
 249         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 250         struct intel_svm_dev *sdev;
 251
 252         /* This might end up being called from exit_mmap(), *before* the page
 253          * tables are cleared. And __mmu_notifier_release() will delete us from
 254          * the list of notifiers so that our invalidate_range() callback doesn't
 255          * get called when the page tables are cleared. So we need to protect
 256          * against hardware accessing those page tables.
 257          *
 258          * We do it by clearing the entry in the PASID table and then flushing
 259          * the IOTLB and the PASID table caches. This might upset hardware;
 260          * perhaps we'll want to point the PASID to a dummy PGD (like the zero
 261          * page) so that we end up taking a fault that the hardware really
 262          * *has* to handle gracefully without affecting other processes.
 263          */
 264         rcu_read_lock();
 265         list_for_each_entry_rcu(sdev, &svm->devs, list) {
 266                 intel_pasid_clear_entry(sdev->dev, svm->pasid);
 267                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
 268                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 269         }
 270         rcu_read_unlock();
 271
 272 }
 273
 274 static const struct mmu_notifier_ops intel_mmuops = {
 275         .flags = MMU_INVALIDATE_DOES_NOT_BLOCK,
 276         .release = intel_mm_release,
 277         .change_pte = intel_change_pte,
 278         .invalidate_range = intel_invalidate_range,
 279 };
 280
 281 static DEFINE_MUTEX(pasid_mutex);
 282 static LIST_HEAD(global_svm_list);
 283
 284 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
 285 {
 286         struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
 287         struct pasid_entry *entry;
 288         struct intel_svm_dev *sdev;
 289         struct intel_svm *svm = NULL;
 290         struct mm_struct *mm = NULL;
 291         u64 pasid_entry_val;
 292         int pasid_max;
 293         int ret;
 294
 295         if (!iommu)
 296                 return -EINVAL;
 297
 298         if (dev_is_pci(dev)) {
 299                 pasid_max = pci_max_pasids(to_pci_dev(dev));
 300                 if (pasid_max < 0)
 301                         return -EINVAL;
 302         } else
 303                 pasid_max = 1 << 20;
 304
 305         if (flags & SVM_FLAG_SUPERVISOR_MODE) {
 306                 if (!ecap_srs(iommu->ecap))
 307                         return -EINVAL;
 308         } else if (pasid) {
 309                 mm = get_task_mm(current);
 310                 BUG_ON(!mm);
 311         }
 312
 313         mutex_lock(&pasid_mutex);
 314         if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
 315                 struct intel_svm *t;
 316
 317                 list_for_each_entry(t, &global_svm_list, list) {
 318                         if (t->mm != mm || (t->flags & SVM_FLAG_PRIVATE_PASID))
 319                                 continue;
 320
 321                         svm = t;
 322                         if (svm->pasid >= pasid_max) {
 323                                 dev_warn(dev,
 324                                          "Limited PASID width. Cannot use existing PASID %d\n",
 325                                          svm->pasid);
 326                                 ret = -ENOSPC;
 327                                 goto out;
 328                         }
 329
 330                         list_for_each_entry(sdev, &svm->devs, list) {
 331                                 if (dev == sdev->dev) {
 332                                         if (sdev->ops != ops) {
 333                                                 ret = -EBUSY;
 334                                                 goto out;
 335                                         }
 336                                         sdev->users++;
 337                                         goto success;
 338                                 }
 339                         }
 340
 341                         break;
 342                 }
 343         }
 344
 345         sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
 346         if (!sdev) {
 347                 ret = -ENOMEM;
 348                 goto out;
 349         }
 350         sdev->dev = dev;
 351
 352         ret = intel_iommu_enable_pasid(iommu, sdev);
 353         if (ret || !pasid) {
 354                 /* If they don't actually want to assign a PASID, this is
 355                  * just an enabling check/preparation. */
 356                 kfree(sdev);
 357                 goto out;
 358         }
 359         /* Finish the setup now we know we're keeping it */
 360         sdev->users = 1;
 361         sdev->ops = ops;
 362         init_rcu_head(&sdev->rcu);
 363
 364         if (!svm) {
 365                 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
 366                 if (!svm) {
 367                         ret = -ENOMEM;
 368                         kfree(sdev);
 369                         goto out;
 370                 }
 371                 svm->iommu = iommu;
 372
 373                 if (pasid_max > intel_pasid_max_id)
 374                         pasid_max = intel_pasid_max_id;
 375
 376                 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
 377                 ret = intel_pasid_alloc_id(svm,
 378                                            !!cap_caching_mode(iommu->cap),
 379                                            pasid_max - 1, GFP_KERNEL);
 380                 if (ret < 0) {
 381                         kfree(svm);
 382                         kfree(sdev);
 383                         goto out;
 384                 }
 385                 svm->pasid = ret;
 386                 svm->notifier.ops = &intel_mmuops;
 387                 svm->mm = mm;
 388                 svm->flags = flags;
 389                 INIT_LIST_HEAD_RCU(&svm->devs);
 390                 INIT_LIST_HEAD(&svm->list);
 391                 ret = -ENOMEM;
 392                 if (mm) {
 393                         ret = mmu_notifier_register(&svm->notifier, mm);
 394                         if (ret) {
 395                                 intel_pasid_free_id(svm->pasid);
 396                                 kfree(svm);
 397                                 kfree(sdev);
 398                                 goto out;
 399                         }
 400                         pasid_entry_val = (u64)__pa(mm->pgd) | PASID_ENTRY_P;
 401                 } else
 402                         pasid_entry_val = (u64)__pa(init_mm.pgd) |
 403                                           PASID_ENTRY_P | PASID_ENTRY_SRE;
 404                 if (cpu_feature_enabled(X86_FEATURE_LA57))
 405                         pasid_entry_val |= PASID_ENTRY_FLPM_5LP;
 406
 407                 entry = intel_pasid_get_entry(dev, svm->pasid);
 408                 entry->val = pasid_entry_val;
 409
 410                 wmb();
 411
 412                 /*
 413                  * Flush PASID cache when a PASID table entry becomes
 414                  * present.
 415                  */
 416                 if (cap_caching_mode(iommu->cap))
 417                         intel_flush_pasid_dev(svm, sdev, svm->pasid);
 418
 419                 list_add_tail(&svm->list, &global_svm_list);
 420         }
 421         list_add_rcu(&sdev->list, &svm->devs);
 422
 423  success:
 424         *pasid = svm->pasid;
 425         ret = 0;
 426  out:
 427         mutex_unlock(&pasid_mutex);
 428         if (mm)
 429                 mmput(mm);
 430         return ret;
 431 }
 432 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
 433
 434 int intel_svm_unbind_mm(struct device *dev, int pasid)
 435 {
 436         struct intel_svm_dev *sdev;
 437         struct intel_iommu *iommu;
 438         struct intel_svm *svm;
 439         int ret = -EINVAL;
 440
 441         mutex_lock(&pasid_mutex);
 442         iommu = intel_svm_device_to_iommu(dev);
 443         if (!iommu)
 444                 goto out;
 445
 446         svm = intel_pasid_lookup_id(pasid);
 447         if (!svm)
 448                 goto out;
 449
 450         list_for_each_entry(sdev, &svm->devs, list) {
 451                 if (dev == sdev->dev) {
 452                         ret = 0;
 453                         sdev->users--;
 454                         if (!sdev->users) {
 455                                 list_del_rcu(&sdev->list);
 456                                 /* Flush the PASID cache and IOTLB for this device.
 457                                  * Note that we do depend on the hardware *not* using
 458                                  * the PASID any more. Just as we depend on other
 459                                  * devices never using PASIDs that they have no right
 460                                  * to use. We have a *shared* PASID table, because it's
 461                                  * large and has to be physically contiguous. So it's
 462                                  * hard to be as defensive as we might like. */
 463                                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
 464                                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 465                                 kfree_rcu(sdev, rcu);
 466                                 intel_pasid_clear_entry(dev, svm->pasid);
 467
 468                                 if (list_empty(&svm->devs)) {
 469                                         intel_pasid_free_id(svm->pasid);
 470                                         if (svm->mm)
 471                                                 mmu_notifier_unregister(&svm->notifier, svm->mm);
 472
 473                                         list_del(&svm->list);
 474
 475                                         /* We mandate that no page faults may be outstanding
 476                                          * for the PASID when intel_svm_unbind_mm() is called.
 477                                          * If that is not obeyed, subtle errors will happen.
 478                                          * Let's make them less subtle... */
 479                                         memset(svm, 0x6b, sizeof(*svm));
 480                                         kfree(svm);
 481                                 }
 482                         }
 483                         break;
 484                 }
 485         }
 486  out:
 487         mutex_unlock(&pasid_mutex);
 488
 489         return ret;
 490 }
 491 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
 492
 493 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
 494 {
 495         struct intel_iommu *iommu;
 496         struct intel_svm *svm;
 497         int ret = -EINVAL;
 498
 499         mutex_lock(&pasid_mutex);
 500         iommu = intel_svm_device_to_iommu(dev);
 501         if (!iommu)
 502                 goto out;
 503
 504         svm = intel_pasid_lookup_id(pasid);
 505         if (!svm)
 506                 goto out;
 507
 508         /* init_mm is used in this case */
 509         if (!svm->mm)
 510                 ret = 1;
 511         else if (atomic_read(&svm->mm->mm_users) > 0)
 512                 ret = 1;
 513         else
 514                 ret = 0;
 515
 516  out:
 517         mutex_unlock(&pasid_mutex);
 518
 519         return ret;
 520 }
 521 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
 522
 523 /* Page request queue descriptor */
 524 struct page_req_dsc {
 525         u64 srr:1;
 526         u64 bof:1;
 527         u64 pasid_present:1;
 528         u64 lpig:1;
 529         u64 pasid:20;
 530         u64 bus:8;
 531         u64 private:23;
 532         u64 prg_index:9;
 533         u64 rd_req:1;
 534         u64 wr_req:1;
 535         u64 exe_req:1;
 536         u64 priv_req:1;
 537         u64 devfn:8;
 538         u64 addr:52;
 539 };
 540
 541 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
 542
 543 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
 544 {
 545         unsigned long requested = 0;
 546
 547         if (req->exe_req)
 548                 requested |= VM_EXEC;
 549
 550         if (req->rd_req)
 551                 requested |= VM_READ;
 552
 553         if (req->wr_req)
 554                 requested |= VM_WRITE;
 555
 556         return (requested & ~vma->vm_flags) != 0;
 557 }
 558
 559 static bool is_canonical_address(u64 addr)
 560 {
 561         int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
 562         long saddr = (long) addr;
 563
 564         return (((saddr << shift) >> shift) == saddr);
 565 }
 566
 567 static irqreturn_t prq_event_thread(int irq, void *d)
 568 {
 569         struct intel_iommu *iommu = d;
 570         struct intel_svm *svm = NULL;
 571         int head, tail, handled = 0;
 572
 573         /* Clear PPR bit before reading head/tail registers, to
 574          * ensure that we get a new interrupt if needed. */
 575         writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
 576
 577         tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
 578         head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
 579         while (head != tail) {
 580                 struct intel_svm_dev *sdev;
 581                 struct vm_area_struct *vma;
 582                 struct page_req_dsc *req;
 583                 struct qi_desc resp;
 584                 int ret, result;
 585                 u64 address;
 586
 587                 handled = 1;
 588
 589                 req = &iommu->prq[head / sizeof(*req)];
 590
 591                 result = QI_RESP_FAILURE;
 592                 address = (u64)req->addr << VTD_PAGE_SHIFT;
 593                 if (!req->pasid_present) {
 594                         pr_err("%s: Page request without PASID: %08llx %08llx\n",
 595                                iommu->name, ((unsigned long long *)req)[0],
 596                                ((unsigned long long *)req)[1]);
 597                         goto bad_req;
 598                 }
 599
 600                 if (!svm || svm->pasid != req->pasid) {
 601                         rcu_read_lock();
 602                         svm = intel_pasid_lookup_id(req->pasid);
 603                         /* It *can't* go away, because the driver is not permitted
 604                          * to unbind the mm while any page faults are outstanding.
 605                          * So we only need RCU to protect the internal idr code. */
 606                         rcu_read_unlock();
 607
 608                         if (!svm) {
 609                                 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
 610                                        iommu->name, req->pasid, ((unsigned long long *)req)[0],
 611                                        ((unsigned long long *)req)[1]);
 612                                 goto no_pasid;
 613                         }
 614                 }
 615
 616                 result = QI_RESP_INVALID;
 617                 /* Since we're using init_mm.pgd directly, we should never take
 618                  * any faults on kernel addresses. */
 619                 if (!svm->mm)
 620                         goto bad_req;
 621                 /* If the mm is already defunct, don't handle faults. */
 622                 if (!mmget_not_zero(svm->mm))
 623                         goto bad_req;
 624
 625                 /* If address is not canonical, return invalid response */
 626                 if (!is_canonical_address(address))
 627                         goto bad_req;
 628
 629                 down_read(&svm->mm->mmap_sem);
 630                 vma = find_extend_vma(svm->mm, address);
 631                 if (!vma || address < vma->vm_start)
 632                         goto invalid;
 633
 634                 if (access_error(vma, req))
 635                         goto invalid;
 636
 637                 ret = handle_mm_fault(vma, address,
 638                                       req->wr_req ? FAULT_FLAG_WRITE : 0);
 639                 if (ret & VM_FAULT_ERROR)
 640                         goto invalid;
 641
 642                 result = QI_RESP_SUCCESS;
 643         invalid:
 644                 up_read(&svm->mm->mmap_sem);
 645                 mmput(svm->mm);
 646         bad_req:
 647                 /* Accounting for major/minor faults? */
 648                 rcu_read_lock();
 649                 list_for_each_entry_rcu(sdev, &svm->devs, list) {
 650                         if (sdev->sid == PCI_DEVID(req->bus, req->devfn))
 651                                 break;
 652                 }
 653                 /* Other devices can go away, but the drivers are not permitted
 654                  * to unbind while any page faults might be in flight. So it's
 655                  * OK to drop the 'lock' here now we have it. */
 656                 rcu_read_unlock();
 657
 658                 if (WARN_ON(&sdev->list == &svm->devs))
 659                         sdev = NULL;
 660
 661                 if (sdev && sdev->ops && sdev->ops->fault_cb) {
 662                         int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
 663                                 (req->exe_req << 1) | (req->priv_req);
 664                         sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
 665                 }
 666                 /* We get here in the error case where the PASID lookup failed,
 667                    and these can be NULL. Do not use them below this point! */
 668                 sdev = NULL;
 669                 svm = NULL;
 670         no_pasid:
 671                 if (req->lpig) {
 672                         /* Page Group Response */
 673                         resp.low = QI_PGRP_PASID(req->pasid) |
 674                                 QI_PGRP_DID((req->bus << 8) | req->devfn) |
 675                                 QI_PGRP_PASID_P(req->pasid_present) |
 676                                 QI_PGRP_RESP_TYPE;
 677                         resp.high = QI_PGRP_IDX(req->prg_index) |
 678                                 QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
 679
 680                         qi_submit_sync(&resp, iommu);
 681                 } else if (req->srr) {
 682                         /* Page Stream Response */
 683                         resp.low = QI_PSTRM_IDX(req->prg_index) |
 684                                 QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
 685                                 QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
 686                         resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
 687                                 QI_PSTRM_RESP_CODE(result);
 688
 689                         qi_submit_sync(&resp, iommu);
 690                 }
 691
 692                 head = (head + sizeof(*req)) & PRQ_RING_MASK;
 693         }
 694
 695         dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
 696
 697         return IRQ_RETVAL(handled);
 698 }