drivers/iommu/exynos-iommu.c

   1 /*
   2  * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #ifdef CONFIG_EXYNOS_IOMMU_DEBUG
  11 #define DEBUG
  12 #endif
  13
  14 #include <linux/clk.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/iommu.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/list.h>
  21 #include <linux/of.h>
  22 #include <linux/of_iommu.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/slab.h>
  27 #include <linux/dma-iommu.h>
  28
  29 typedef u32 sysmmu_iova_t;
  30 typedef u32 sysmmu_pte_t;
  31
  32 /* We do not consider super section mapping (16MB) */
  33 #define SECT_ORDER 20
  34 #define LPAGE_ORDER 16
  35 #define SPAGE_ORDER 12
  36
  37 #define SECT_SIZE (1 << SECT_ORDER)
  38 #define LPAGE_SIZE (1 << LPAGE_ORDER)
  39 #define SPAGE_SIZE (1 << SPAGE_ORDER)
  40
  41 #define SECT_MASK (~(SECT_SIZE - 1))
  42 #define LPAGE_MASK (~(LPAGE_SIZE - 1))
  43 #define SPAGE_MASK (~(SPAGE_SIZE - 1))
  44
  45 #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
  46                            ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
  47 #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
  48 #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
  49 #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
  50                           ((*(sent) & 3) == 1))
  51 #define lv1ent_section(sent) ((*(sent) & 3) == 2)
  52
  53 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
  54 #define lv2ent_small(pent) ((*(pent) & 2) == 2)
  55 #define lv2ent_large(pent) ((*(pent) & 3) == 1)
  56
  57 /*
  58  * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
  59  * v5.0 introduced support for 36bit physical address space by shifting
  60  * all page entry values by 4 bits.
  61  * All SYSMMU controllers in the system support the address spaces of the same
  62  * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
  63  * value (0 or 4).
  64  */
  65 static short PG_ENT_SHIFT = -1;
  66 #define SYSMMU_PG_ENT_SHIFT 0
  67 #define SYSMMU_V5_PG_ENT_SHIFT 4
  68
  69 #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
  70 #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
  71 #define section_offs(iova) (iova & (SECT_SIZE - 1))
  72 #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
  73 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
  74 #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
  75 #define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
  76
  77 #define NUM_LV1ENTRIES 4096
  78 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
  79
  80 static u32 lv1ent_offset(sysmmu_iova_t iova)
  81 {
  82         return iova >> SECT_ORDER;
  83 }
  84
  85 static u32 lv2ent_offset(sysmmu_iova_t iova)
  86 {
  87         return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
  88 }
  89
  90 #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t))
  91 #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
  92
  93 #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
  94 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
  95
  96 #define mk_lv1ent_sect(pa) ((pa >> PG_ENT_SHIFT) | 2)
  97 #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
  98 #define mk_lv2ent_lpage(pa) ((pa >> PG_ENT_SHIFT) | 1)
  99 #define mk_lv2ent_spage(pa) ((pa >> PG_ENT_SHIFT) | 2)
 100
 101 #define CTRL_ENABLE     0x5
 102 #define CTRL_BLOCK      0x7
 103 #define CTRL_DISABLE    0x0
 104
 105 #define CFG_LRU         0x1
 106 #define CFG_QOS(n)      ((n & 0xF) << 7)
 107 #define CFG_ACGEN       (1 << 24) /* System MMU 3.3 only */
 108 #define CFG_SYSSEL      (1 << 22) /* System MMU 3.2 only */
 109 #define CFG_FLPDCACHE   (1 << 20) /* System MMU 3.2+ only */
 110
 111 /* common registers */
 112 #define REG_MMU_CTRL            0x000
 113 #define REG_MMU_CFG             0x004
 114 #define REG_MMU_STATUS          0x008
 115 #define REG_MMU_VERSION         0x034
 116
 117 #define MMU_MAJ_VER(val)        ((val) >> 7)
 118 #define MMU_MIN_VER(val)        ((val) & 0x7F)
 119 #define MMU_RAW_VER(reg)        (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
 120
 121 #define MAKE_MMU_VER(maj, min)  ((((maj) & 0xF) << 7) | ((min) & 0x7F))
 122
 123 /* v1.x - v3.x registers */
 124 #define REG_MMU_FLUSH           0x00C
 125 #define REG_MMU_FLUSH_ENTRY     0x010
 126 #define REG_PT_BASE_ADDR        0x014
 127 #define REG_INT_STATUS          0x018
 128 #define REG_INT_CLEAR           0x01C
 129
 130 #define REG_PAGE_FAULT_ADDR     0x024
 131 #define REG_AW_FAULT_ADDR       0x028
 132 #define REG_AR_FAULT_ADDR       0x02C
 133 #define REG_DEFAULT_SLAVE_ADDR  0x030
 134
 135 /* v5.x registers */
 136 #define REG_V5_PT_BASE_PFN      0x00C
 137 #define REG_V5_MMU_FLUSH_ALL    0x010
 138 #define REG_V5_MMU_FLUSH_ENTRY  0x014
 139 #define REG_V5_INT_STATUS       0x060
 140 #define REG_V5_INT_CLEAR        0x064
 141 #define REG_V5_FAULT_AR_VA      0x070
 142 #define REG_V5_FAULT_AW_VA      0x080
 143
 144 #define has_sysmmu(dev)         (dev->archdata.iommu != NULL)
 145
 146 static struct device *dma_dev;
 147 static struct kmem_cache *lv2table_kmem_cache;
 148 static sysmmu_pte_t *zero_lv2_table;
 149 #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
 150
 151 static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
 152 {
 153         return pgtable + lv1ent_offset(iova);
 154 }
 155
 156 static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
 157 {
 158         return (sysmmu_pte_t *)phys_to_virt(
 159                                 lv2table_base(sent)) + lv2ent_offset(iova);
 160 }
 161
 162 /*
 163  * IOMMU fault information register
 164  */
 165 struct sysmmu_fault_info {
 166         unsigned int bit;       /* bit number in STATUS register */
 167         unsigned short addr_reg; /* register to read VA fault address */
 168         const char *name;       /* human readable fault name */
 169         unsigned int type;      /* fault type for report_iommu_fault */
 170 };
 171
 172 static const struct sysmmu_fault_info sysmmu_faults[] = {
 173         { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
 174         { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ },
 175         { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 176         { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ },
 177         { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 178         { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 179         { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 180         { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 181 };
 182
 183 static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
 184         { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
 185         { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
 186         { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
 187         { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
 188         { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
 189         { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
 190         { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
 191         { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
 192         { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
 193         { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
 194 };
 195
 196 /*
 197  * This structure is attached to dev.archdata.iommu of the master device
 198  * on device add, contains a list of SYSMMU controllers defined by device tree,
 199  * which are bound to given master device. It is usually referenced by 'owner'
 200  * pointer.
 201 */
 202 struct exynos_iommu_owner {
 203         struct list_head controllers;   /* list of sysmmu_drvdata.owner_node */
 204         struct iommu_domain *domain;    /* domain this device is attached */
 205 };
 206
 207 /*
 208  * This structure exynos specific generalization of struct iommu_domain.
 209  * It contains list of SYSMMU controllers from all master devices, which has
 210  * been attached to this domain and page tables of IO address space defined by
 211  * it. It is usually referenced by 'domain' pointer.
 212  */
 213 struct exynos_iommu_domain {
 214         struct list_head clients; /* list of sysmmu_drvdata.domain_node */
 215         sysmmu_pte_t *pgtable;  /* lv1 page table, 16KB */
 216         short *lv2entcnt;       /* free lv2 entry counter for each section */
 217         spinlock_t lock;        /* lock for modyfying list of clients */
 218         spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
 219         struct iommu_domain domain; /* generic domain data structure */
 220 };
 221
 222 /*
 223  * This structure hold all data of a single SYSMMU controller, this includes
 224  * hw resources like registers and clocks, pointers and list nodes to connect
 225  * it to all other structures, internal state and parameters read from device
 226  * tree. It is usually referenced by 'data' pointer.
 227  */
 228 struct sysmmu_drvdata {
 229         struct device *sysmmu;          /* SYSMMU controller device */
 230         struct device *master;          /* master device (owner) */
 231         void __iomem *sfrbase;          /* our registers */
 232         struct clk *clk;                /* SYSMMU's clock */
 233         struct clk *aclk;               /* SYSMMU's aclk clock */
 234         struct clk *pclk;               /* SYSMMU's pclk clock */
 235         struct clk *clk_master;         /* master's device clock */
 236         int activations;                /* number of calls to sysmmu_enable */
 237         spinlock_t lock;                /* lock for modyfying state */
 238         struct exynos_iommu_domain *domain; /* domain we belong to */
 239         struct list_head domain_node;   /* node for domain clients list */
 240         struct list_head owner_node;    /* node for owner controllers list */
 241         phys_addr_t pgtable;            /* assigned page table structure */
 242         unsigned int version;           /* our version */
 243 };
 244
 245 static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom)
 246 {
 247         return container_of(dom, struct exynos_iommu_domain, domain);
 248 }
 249
 250 static bool set_sysmmu_active(struct sysmmu_drvdata *data)
 251 {
 252         /* return true if the System MMU was not active previously
 253            and it needs to be initialized */
 254         return ++data->activations == 1;
 255 }
 256
 257 static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
 258 {
 259         /* return true if the System MMU is needed to be disabled */
 260         BUG_ON(data->activations < 1);
 261         return --data->activations == 0;
 262 }
 263
 264 static bool is_sysmmu_active(struct sysmmu_drvdata *data)
 265 {
 266         return data->activations > 0;
 267 }
 268
 269 static void sysmmu_unblock(struct sysmmu_drvdata *data)
 270 {
 271         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 272 }
 273
 274 static bool sysmmu_block(struct sysmmu_drvdata *data)
 275 {
 276         int i = 120;
 277
 278         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 279         while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))
 280                 --i;
 281
 282         if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) {
 283                 sysmmu_unblock(data);
 284                 return false;
 285         }
 286
 287         return true;
 288 }
 289
 290 static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
 291 {
 292         if (MMU_MAJ_VER(data->version) < 5)
 293                 writel(0x1, data->sfrbase + REG_MMU_FLUSH);
 294         else
 295                 writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
 296 }
 297
 298 static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 299                                 sysmmu_iova_t iova, unsigned int num_inv)
 300 {
 301         unsigned int i;
 302
 303         for (i = 0; i < num_inv; i++) {
 304                 if (MMU_MAJ_VER(data->version) < 5)
 305                         writel((iova & SPAGE_MASK) | 1,
 306                                      data->sfrbase + REG_MMU_FLUSH_ENTRY);
 307                 else
 308                         writel((iova & SPAGE_MASK) | 1,
 309                                      data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
 310                 iova += SPAGE_SIZE;
 311         }
 312 }
 313
 314 static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
 315 {
 316         if (MMU_MAJ_VER(data->version) < 5)
 317                 writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
 318         else
 319                 writel(pgd >> PAGE_SHIFT,
 320                              data->sfrbase + REG_V5_PT_BASE_PFN);
 321
 322         __sysmmu_tlb_invalidate(data);
 323 }
 324
 325 static void __sysmmu_get_version(struct sysmmu_drvdata *data)
 326 {
 327         u32 ver;
 328
 329         clk_enable(data->clk_master);
 330         clk_enable(data->clk);
 331         clk_enable(data->pclk);
 332         clk_enable(data->aclk);
 333
 334         ver = readl(data->sfrbase + REG_MMU_VERSION);
 335
 336         /* controllers on some SoCs don't report proper version */
 337         if (ver == 0x80000001u)
 338                 data->version = MAKE_MMU_VER(1, 0);
 339         else
 340                 data->version = MMU_RAW_VER(ver);
 341
 342         dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
 343                 MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));
 344
 345         clk_disable(data->aclk);
 346         clk_disable(data->pclk);
 347         clk_disable(data->clk);
 348         clk_disable(data->clk_master);
 349 }
 350
 351 static void show_fault_information(struct sysmmu_drvdata *data,
 352                                    const struct sysmmu_fault_info *finfo,
 353                                    sysmmu_iova_t fault_addr)
 354 {
 355         sysmmu_pte_t *ent;
 356
 357         dev_err(data->sysmmu, "%s FAULT occurred at %#x (page table base: %pa)\n",
 358                 finfo->name, fault_addr, &data->pgtable);
 359         ent = section_entry(phys_to_virt(data->pgtable), fault_addr);
 360         dev_err(data->sysmmu, "\tLv1 entry: %#x\n", *ent);
 361         if (lv1ent_page(ent)) {
 362                 ent = page_entry(ent, fault_addr);
 363                 dev_err(data->sysmmu, "\t Lv2 entry: %#x\n", *ent);
 364         }
 365 }
 366
 367 static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
 368 {
 369         /* SYSMMU is in blocked state when interrupt occurred. */
 370         struct sysmmu_drvdata *data = dev_id;
 371         const struct sysmmu_fault_info *finfo;
 372         unsigned int i, n, itype;
 373         sysmmu_iova_t fault_addr = -1;
 374         unsigned short reg_status, reg_clear;
 375         int ret = -ENOSYS;
 376
 377         WARN_ON(!is_sysmmu_active(data));
 378
 379         if (MMU_MAJ_VER(data->version) < 5) {
 380                 reg_status = REG_INT_STATUS;
 381                 reg_clear = REG_INT_CLEAR;
 382                 finfo = sysmmu_faults;
 383                 n = ARRAY_SIZE(sysmmu_faults);
 384         } else {
 385                 reg_status = REG_V5_INT_STATUS;
 386                 reg_clear = REG_V5_INT_CLEAR;
 387                 finfo = sysmmu_v5_faults;
 388                 n = ARRAY_SIZE(sysmmu_v5_faults);
 389         }
 390
 391         spin_lock(&data->lock);
 392
 393         clk_enable(data->clk_master);
 394
 395         itype = __ffs(readl(data->sfrbase + reg_status));
 396         for (i = 0; i < n; i++, finfo++)
 397                 if (finfo->bit == itype)
 398                         break;
 399         /* unknown/unsupported fault */
 400         BUG_ON(i == n);
 401
 402         /* print debug message */
 403         fault_addr = readl(data->sfrbase + finfo->addr_reg);
 404         show_fault_information(data, finfo, fault_addr);
 405
 406         if (data->domain)
 407                 ret = report_iommu_fault(&data->domain->domain,
 408                                         data->master, fault_addr, finfo->type);
 409         /* fault is not recovered by fault handler */
 410         BUG_ON(ret != 0);
 411
 412         writel(1 << itype, data->sfrbase + reg_clear);
 413
 414         sysmmu_unblock(data);
 415
 416         clk_disable(data->clk_master);
 417
 418         spin_unlock(&data->lock);
 419
 420         return IRQ_HANDLED;
 421 }
 422
 423 static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
 424 {
 425         clk_enable(data->clk_master);
 426
 427         writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
 428         writel(0, data->sfrbase + REG_MMU_CFG);
 429
 430         clk_disable(data->aclk);
 431         clk_disable(data->pclk);
 432         clk_disable(data->clk);
 433         clk_disable(data->clk_master);
 434 }
 435
 436 static bool __sysmmu_disable(struct sysmmu_drvdata *data)
 437 {
 438         bool disabled;
 439         unsigned long flags;
 440
 441         spin_lock_irqsave(&data->lock, flags);
 442
 443         disabled = set_sysmmu_inactive(data);
 444
 445         if (disabled) {
 446                 data->pgtable = 0;
 447                 data->domain = NULL;
 448
 449                 __sysmmu_disable_nocount(data);
 450
 451                 dev_dbg(data->sysmmu, "Disabled\n");
 452         } else  {
 453                 dev_dbg(data->sysmmu, "%d times left to disable\n",
 454                                         data->activations);
 455         }
 456
 457         spin_unlock_irqrestore(&data->lock, flags);
 458
 459         return disabled;
 460 }
 461
 462 static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 463 {
 464         unsigned int cfg;
 465
 466         if (data->version <= MAKE_MMU_VER(3, 1))
 467                 cfg = CFG_LRU | CFG_QOS(15);
 468         else if (data->version <= MAKE_MMU_VER(3, 2))
 469                 cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL;
 470         else
 471                 cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN;
 472
 473         writel(cfg, data->sfrbase + REG_MMU_CFG);
 474 }
 475
 476 static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
 477 {
 478         clk_enable(data->clk_master);
 479         clk_enable(data->clk);
 480         clk_enable(data->pclk);
 481         clk_enable(data->aclk);
 482
 483         writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
 484
 485         __sysmmu_init_config(data);
 486
 487         __sysmmu_set_ptbase(data, data->pgtable);
 488
 489         writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
 490
 491         clk_disable(data->clk_master);
 492 }
 493
 494 static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable,
 495                            struct exynos_iommu_domain *domain)
 496 {
 497         int ret = 0;
 498         unsigned long flags;
 499
 500         spin_lock_irqsave(&data->lock, flags);
 501         if (set_sysmmu_active(data)) {
 502                 data->pgtable = pgtable;
 503                 data->domain = domain;
 504
 505                 __sysmmu_enable_nocount(data);
 506
 507                 dev_dbg(data->sysmmu, "Enabled\n");
 508         } else {
 509                 ret = (pgtable == data->pgtable) ? 1 : -EBUSY;
 510
 511                 dev_dbg(data->sysmmu, "already enabled\n");
 512         }
 513
 514         if (WARN_ON(ret < 0))
 515                 set_sysmmu_inactive(data); /* decrement count */
 516
 517         spin_unlock_irqrestore(&data->lock, flags);
 518
 519         return ret;
 520 }
 521
 522 static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
 523                                             sysmmu_iova_t iova)
 524 {
 525         unsigned long flags;
 526
 527         clk_enable(data->clk_master);
 528
 529         spin_lock_irqsave(&data->lock, flags);
 530         if (is_sysmmu_active(data)) {
 531                 if (data->version >= MAKE_MMU_VER(3, 3))
 532                         __sysmmu_tlb_invalidate_entry(data, iova, 1);
 533         }
 534         spin_unlock_irqrestore(&data->lock, flags);
 535
 536         clk_disable(data->clk_master);
 537 }
 538
 539 static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
 540                                         sysmmu_iova_t iova, size_t size)
 541 {
 542         unsigned long flags;
 543
 544         spin_lock_irqsave(&data->lock, flags);
 545         if (is_sysmmu_active(data)) {
 546                 unsigned int num_inv = 1;
 547
 548                 clk_enable(data->clk_master);
 549
 550                 /*
 551                  * L2TLB invalidation required
 552                  * 4KB page: 1 invalidation
 553                  * 64KB page: 16 invalidations
 554                  * 1MB page: 64 invalidations
 555                  * because it is set-associative TLB
 556                  * with 8-way and 64 sets.
 557                  * 1MB page can be cached in one of all sets.
 558                  * 64KB page can be one of 16 consecutive sets.
 559                  */
 560                 if (MMU_MAJ_VER(data->version) == 2)
 561                         num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
 562
 563                 if (sysmmu_block(data)) {
 564                         __sysmmu_tlb_invalidate_entry(data, iova, num_inv);
 565                         sysmmu_unblock(data);
 566                 }
 567                 clk_disable(data->clk_master);
 568         } else {
 569                 dev_dbg(data->master,
 570                         "disabled. Skipping TLB invalidation @ %#x\n", iova);
 571         }
 572         spin_unlock_irqrestore(&data->lock, flags);
 573 }
 574
 575 static int __init exynos_sysmmu_probe(struct platform_device *pdev)
 576 {
 577         int irq, ret;
 578         struct device *dev = &pdev->dev;
 579         struct sysmmu_drvdata *data;
 580         struct resource *res;
 581
 582         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 583         if (!data)
 584                 return -ENOMEM;
 585
 586         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 587         data->sfrbase = devm_ioremap_resource(dev, res);
 588         if (IS_ERR(data->sfrbase))
 589                 return PTR_ERR(data->sfrbase);
 590
 591         irq = platform_get_irq(pdev, 0);
 592         if (irq <= 0) {
 593                 dev_err(dev, "Unable to find IRQ resource\n");
 594                 return irq;
 595         }
 596
 597         ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
 598                                 dev_name(dev), data);
 599         if (ret) {
 600                 dev_err(dev, "Unabled to register handler of irq %d\n", irq);
 601                 return ret;
 602         }
 603
 604         data->clk = devm_clk_get(dev, "sysmmu");
 605         if (!IS_ERR(data->clk)) {
 606                 ret = clk_prepare(data->clk);
 607                 if (ret) {
 608                         dev_err(dev, "Failed to prepare clk\n");
 609                         return ret;
 610                 }
 611         } else {
 612                 data->clk = NULL;
 613         }
 614
 615         data->aclk = devm_clk_get(dev, "aclk");
 616         if (!IS_ERR(data->aclk)) {
 617                 ret = clk_prepare(data->aclk);
 618                 if (ret) {
 619                         dev_err(dev, "Failed to prepare aclk\n");
 620                         return ret;
 621                 }
 622         } else {
 623                 data->aclk = NULL;
 624         }
 625
 626         data->pclk = devm_clk_get(dev, "pclk");
 627         if (!IS_ERR(data->pclk)) {
 628                 ret = clk_prepare(data->pclk);
 629                 if (ret) {
 630                         dev_err(dev, "Failed to prepare pclk\n");
 631                         return ret;
 632                 }
 633         } else {
 634                 data->pclk = NULL;
 635         }
 636
 637         if (!data->clk && (!data->aclk || !data->pclk)) {
 638                 dev_err(dev, "Failed to get device clock(s)!\n");
 639                 return -ENOSYS;
 640         }
 641
 642         data->clk_master = devm_clk_get(dev, "master");
 643         if (!IS_ERR(data->clk_master)) {
 644                 ret = clk_prepare(data->clk_master);
 645                 if (ret) {
 646                         dev_err(dev, "Failed to prepare master's clk\n");
 647                         return ret;
 648                 }
 649         } else {
 650                 data->clk_master = NULL;
 651         }
 652
 653         data->sysmmu = dev;
 654         spin_lock_init(&data->lock);
 655
 656         platform_set_drvdata(pdev, data);
 657
 658         __sysmmu_get_version(data);
 659         if (PG_ENT_SHIFT < 0) {
 660                 if (MMU_MAJ_VER(data->version) < 5)
 661                         PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
 662                 else
 663                         PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
 664         }
 665
 666         pm_runtime_enable(dev);
 667
 668         return 0;
 669 }
 670
 671 #ifdef CONFIG_PM_SLEEP
 672 static int exynos_sysmmu_suspend(struct device *dev)
 673 {
 674         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 675
 676         dev_dbg(dev, "suspend\n");
 677         if (is_sysmmu_active(data)) {
 678                 __sysmmu_disable_nocount(data);
 679                 pm_runtime_put(dev);
 680         }
 681         return 0;
 682 }
 683
 684 static int exynos_sysmmu_resume(struct device *dev)
 685 {
 686         struct sysmmu_drvdata *data = dev_get_drvdata(dev);
 687
 688         dev_dbg(dev, "resume\n");
 689         if (is_sysmmu_active(data)) {
 690                 pm_runtime_get_sync(dev);
 691                 __sysmmu_enable_nocount(data);
 692         }
 693         return 0;
 694 }
 695 #endif
 696
 697 static const struct dev_pm_ops sysmmu_pm_ops = {
 698         SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume)
 699 };
 700
 701 static const struct of_device_id sysmmu_of_match[] __initconst = {
 702         { .compatible   = "samsung,exynos-sysmmu", },
 703         { },
 704 };
 705
 706 static struct platform_driver exynos_sysmmu_driver __refdata = {
 707         .probe  = exynos_sysmmu_probe,
 708         .driver = {
 709                 .name           = "exynos-sysmmu",
 710                 .of_match_table = sysmmu_of_match,
 711                 .pm             = &sysmmu_pm_ops,
 712                 .suppress_bind_attrs = true,
 713         }
 714 };
 715
 716 static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val)
 717 {
 718         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent),
 719                                 DMA_TO_DEVICE);
 720         *ent = val;
 721         dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent),
 722                                    DMA_TO_DEVICE);
 723 }
 724
 725 static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
 726 {
 727         struct exynos_iommu_domain *domain;
 728         dma_addr_t handle;
 729         int i;
 730
 731         /* Check if correct PTE offsets are initialized */
 732         BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
 733
 734         domain = kzalloc(sizeof(*domain), GFP_KERNEL);
 735         if (!domain)
 736                 return NULL;
 737
 738         if (type == IOMMU_DOMAIN_DMA) {
 739                 if (iommu_get_dma_cookie(&domain->domain) != 0)
 740                         goto err_pgtable;
 741         } else if (type != IOMMU_DOMAIN_UNMANAGED) {
 742                 goto err_pgtable;
 743         }
 744
 745         domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
 746         if (!domain->pgtable)
 747                 goto err_dma_cookie;
 748
 749         domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
 750         if (!domain->lv2entcnt)
 751                 goto err_counter;
 752
 753         /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
 754         for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
 755                 domain->pgtable[i + 0] = ZERO_LV2LINK;
 756                 domain->pgtable[i + 1] = ZERO_LV2LINK;
 757                 domain->pgtable[i + 2] = ZERO_LV2LINK;
 758                 domain->pgtable[i + 3] = ZERO_LV2LINK;
 759                 domain->pgtable[i + 4] = ZERO_LV2LINK;
 760                 domain->pgtable[i + 5] = ZERO_LV2LINK;
 761                 domain->pgtable[i + 6] = ZERO_LV2LINK;
 762                 domain->pgtable[i + 7] = ZERO_LV2LINK;
 763         }
 764
 765         handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE,
 766                                 DMA_TO_DEVICE);
 767         /* For mapping page table entries we rely on dma == phys */
 768         BUG_ON(handle != virt_to_phys(domain->pgtable));
 769
 770         spin_lock_init(&domain->lock);
 771         spin_lock_init(&domain->pgtablelock);
 772         INIT_LIST_HEAD(&domain->clients);
 773
 774         domain->domain.geometry.aperture_start = 0;
 775         domain->domain.geometry.aperture_end   = ~0UL;
 776         domain->domain.geometry.force_aperture = true;
 777
 778         return &domain->domain;
 779
 780 err_counter:
 781         free_pages((unsigned long)domain->pgtable, 2);
 782 err_dma_cookie:
 783         if (type == IOMMU_DOMAIN_DMA)
 784                 iommu_put_dma_cookie(&domain->domain);
 785 err_pgtable:
 786         kfree(domain);
 787         return NULL;
 788 }
 789
 790 static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain)
 791 {
 792         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 793         struct sysmmu_drvdata *data, *next;
 794         unsigned long flags;
 795         int i;
 796
 797         WARN_ON(!list_empty(&domain->clients));
 798
 799         spin_lock_irqsave(&domain->lock, flags);
 800
 801         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 802                 if (__sysmmu_disable(data))
 803                         data->master = NULL;
 804                 list_del_init(&data->domain_node);
 805         }
 806
 807         spin_unlock_irqrestore(&domain->lock, flags);
 808
 809         if (iommu_domain->type == IOMMU_DOMAIN_DMA)
 810                 iommu_put_dma_cookie(iommu_domain);
 811
 812         dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE,
 813                          DMA_TO_DEVICE);
 814
 815         for (i = 0; i < NUM_LV1ENTRIES; i++)
 816                 if (lv1ent_page(domain->pgtable + i)) {
 817                         phys_addr_t base = lv2table_base(domain->pgtable + i);
 818
 819                         dma_unmap_single(dma_dev, base, LV2TABLE_SIZE,
 820                                          DMA_TO_DEVICE);
 821                         kmem_cache_free(lv2table_kmem_cache,
 822                                         phys_to_virt(base));
 823                 }
 824
 825         free_pages((unsigned long)domain->pgtable, 2);
 826         free_pages((unsigned long)domain->lv2entcnt, 1);
 827         kfree(domain);
 828 }
 829
 830 static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain,
 831                                     struct device *dev)
 832 {
 833         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 834         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 835         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 836         struct sysmmu_drvdata *data, *next;
 837         unsigned long flags;
 838         bool found = false;
 839
 840         if (!has_sysmmu(dev) || owner->domain != iommu_domain)
 841                 return;
 842
 843         spin_lock_irqsave(&domain->lock, flags);
 844         list_for_each_entry_safe(data, next, &domain->clients, domain_node) {
 845                 if (data->master == dev) {
 846                         if (__sysmmu_disable(data)) {
 847                                 data->master = NULL;
 848                                 list_del_init(&data->domain_node);
 849                         }
 850                         pm_runtime_put(data->sysmmu);
 851                         found = true;
 852                 }
 853         }
 854         spin_unlock_irqrestore(&domain->lock, flags);
 855
 856         owner->domain = NULL;
 857
 858         if (found)
 859                 dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
 860                                         __func__, &pagetable);
 861         else
 862                 dev_err(dev, "%s: No IOMMU is attached\n", __func__);
 863 }
 864
 865 static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain,
 866                                    struct device *dev)
 867 {
 868         struct exynos_iommu_owner *owner = dev->archdata.iommu;
 869         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
 870         struct sysmmu_drvdata *data;
 871         phys_addr_t pagetable = virt_to_phys(domain->pgtable);
 872         unsigned long flags;
 873         int ret = -ENODEV;
 874
 875         if (!has_sysmmu(dev))
 876                 return -ENODEV;
 877
 878         if (owner->domain)
 879                 exynos_iommu_detach_device(owner->domain, dev);
 880
 881         list_for_each_entry(data, &owner->controllers, owner_node) {
 882                 pm_runtime_get_sync(data->sysmmu);
 883                 ret = __sysmmu_enable(data, pagetable, domain);
 884                 if (ret >= 0) {
 885                         data->master = dev;
 886
 887                         spin_lock_irqsave(&domain->lock, flags);
 888                         list_add_tail(&data->domain_node, &domain->clients);
 889                         spin_unlock_irqrestore(&domain->lock, flags);
 890                 }
 891         }
 892
 893         if (ret < 0) {
 894                 dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
 895                                         __func__, &pagetable);
 896                 return ret;
 897         }
 898
 899         owner->domain = iommu_domain;
 900         dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
 901                 __func__, &pagetable, (ret == 0) ? "" : ", again");
 902
 903         return ret;
 904 }
 905
 906 static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
 907                 sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
 908 {
 909         if (lv1ent_section(sent)) {
 910                 WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
 911                 return ERR_PTR(-EADDRINUSE);
 912         }
 913
 914         if (lv1ent_fault(sent)) {
 915                 sysmmu_pte_t *pent;
 916                 bool need_flush_flpd_cache = lv1ent_zero(sent);
 917
 918                 pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
 919                 BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1));
 920                 if (!pent)
 921                         return ERR_PTR(-ENOMEM);
 922
 923                 update_pte(sent, mk_lv1ent_page(virt_to_phys(pent)));
 924                 kmemleak_ignore(pent);
 925                 *pgcounter = NUM_LV2ENTRIES;
 926                 dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE);
 927
 928                 /*
 929                  * If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
 930                  * FLPD cache may cache the address of zero_l2_table. This
 931                  * function replaces the zero_l2_table with new L2 page table
 932                  * to write valid mappings.
 933                  * Accessing the valid area may cause page fault since FLPD
 934                  * cache may still cache zero_l2_table for the valid area
 935                  * instead of new L2 page table that has the mapping
 936                  * information of the valid area.
 937                  * Thus any replacement of zero_l2_table with other valid L2
 938                  * page table must involve FLPD cache invalidation for System
 939                  * MMU v3.3.
 940                  * FLPD cache invalidation is performed with TLB invalidation
 941                  * by VPN without blocking. It is safe to invalidate TLB without
 942                  * blocking because the target address of TLB invalidation is
 943                  * not currently mapped.
 944                  */
 945                 if (need_flush_flpd_cache) {
 946                         struct sysmmu_drvdata *data;
 947
 948                         spin_lock(&domain->lock);
 949                         list_for_each_entry(data, &domain->clients, domain_node)
 950                                 sysmmu_tlb_invalidate_flpdcache(data, iova);
 951                         spin_unlock(&domain->lock);
 952                 }
 953         }
 954
 955         return page_entry(sent, iova);
 956 }
 957
 958 static int lv1set_section(struct exynos_iommu_domain *domain,
 959                           sysmmu_pte_t *sent, sysmmu_iova_t iova,
 960                           phys_addr_t paddr, short *pgcnt)
 961 {
 962         if (lv1ent_section(sent)) {
 963                 WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 964                         iova);
 965                 return -EADDRINUSE;
 966         }
 967
 968         if (lv1ent_page(sent)) {
 969                 if (*pgcnt != NUM_LV2ENTRIES) {
 970                         WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
 971                                 iova);
 972                         return -EADDRINUSE;
 973                 }
 974
 975                 kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
 976                 *pgcnt = 0;
 977         }
 978
 979         update_pte(sent, mk_lv1ent_sect(paddr));
 980
 981         spin_lock(&domain->lock);
 982         if (lv1ent_page_zero(sent)) {
 983                 struct sysmmu_drvdata *data;
 984                 /*
 985                  * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
 986                  * entry by speculative prefetch of SLPD which has no mapping.
 987                  */
 988                 list_for_each_entry(data, &domain->clients, domain_node)
 989                         sysmmu_tlb_invalidate_flpdcache(data, iova);
 990         }
 991         spin_unlock(&domain->lock);
 992
 993         return 0;
 994 }
 995
 996 static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
 997                                                                 short *pgcnt)
 998 {
 999         if (size == SPAGE_SIZE) {
1000                 if (WARN_ON(!lv2ent_fault(pent)))
1001                         return -EADDRINUSE;
1002
1003                 update_pte(pent, mk_lv2ent_spage(paddr));
1004                 *pgcnt -= 1;
1005         } else { /* size == LPAGE_SIZE */
1006                 int i;
1007                 dma_addr_t pent_base = virt_to_phys(pent);
1008
1009                 dma_sync_single_for_cpu(dma_dev, pent_base,
1010                                         sizeof(*pent) * SPAGES_PER_LPAGE,
1011                                         DMA_TO_DEVICE);
1012                 for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
1013                         if (WARN_ON(!lv2ent_fault(pent))) {
1014                                 if (i > 0)
1015                                         memset(pent - i, 0, sizeof(*pent) * i);
1016                                 return -EADDRINUSE;
1017                         }
1018
1019                         *pent = mk_lv2ent_lpage(paddr);
1020                 }
1021                 dma_sync_single_for_device(dma_dev, pent_base,
1022                                            sizeof(*pent) * SPAGES_PER_LPAGE,
1023                                            DMA_TO_DEVICE);
1024                 *pgcnt -= SPAGES_PER_LPAGE;
1025         }
1026
1027         return 0;
1028 }
1029
1030 /*
1031  * *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
1032  *
1033  * System MMU v3.x has advanced logic to improve address translation
1034  * performance with caching more page table entries by a page table walk.
1035  * However, the logic has a bug that while caching faulty page table entries,
1036  * System MMU reports page fault if the cached fault entry is hit even though
1037  * the fault entry is updated to a valid entry after the entry is cached.
1038  * To prevent caching faulty page table entries which may be updated to valid
1039  * entries later, the virtual memory manager should care about the workaround
1040  * for the problem. The following describes the workaround.
1041  *
1042  * Any two consecutive I/O virtual address regions must have a hole of 128KiB
1043  * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
1044  *
1045  * Precisely, any start address of I/O virtual region must be aligned with
1046  * the following sizes for System MMU v3.1 and v3.2.
1047  * System MMU v3.1: 128KiB
1048  * System MMU v3.2: 256KiB
1049  *
1050  * Because System MMU v3.3 caches page table entries more aggressively, it needs
1051  * more workarounds.
1052  * - Any two consecutive I/O virtual regions must have a hole of size larger
1053  *   than or equal to 128KiB.
1054  * - Start address of an I/O virtual region must be aligned by 128KiB.
1055  */
1056 static int exynos_iommu_map(struct iommu_domain *iommu_domain,
1057                             unsigned long l_iova, phys_addr_t paddr, size_t size,
1058                             int prot)
1059 {
1060         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1061         sysmmu_pte_t *entry;
1062         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1063         unsigned long flags;
1064         int ret = -ENOMEM;
1065
1066         BUG_ON(domain->pgtable == NULL);
1067
1068         spin_lock_irqsave(&domain->pgtablelock, flags);
1069
1070         entry = section_entry(domain->pgtable, iova);
1071
1072         if (size == SECT_SIZE) {
1073                 ret = lv1set_section(domain, entry, iova, paddr,
1074                                      &domain->lv2entcnt[lv1ent_offset(iova)]);
1075         } else {
1076                 sysmmu_pte_t *pent;
1077
1078                 pent = alloc_lv2entry(domain, entry, iova,
1079                                       &domain->lv2entcnt[lv1ent_offset(iova)]);
1080
1081                 if (IS_ERR(pent))
1082                         ret = PTR_ERR(pent);
1083                 else
1084                         ret = lv2set_page(pent, paddr, size,
1085                                        &domain->lv2entcnt[lv1ent_offset(iova)]);
1086         }
1087
1088         if (ret)
1089                 pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
1090                         __func__, ret, size, iova);
1091
1092         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1093
1094         return ret;
1095 }
1096
1097 static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain,
1098                                               sysmmu_iova_t iova, size_t size)
1099 {
1100         struct sysmmu_drvdata *data;
1101         unsigned long flags;
1102
1103         spin_lock_irqsave(&domain->lock, flags);
1104
1105         list_for_each_entry(data, &domain->clients, domain_node)
1106                 sysmmu_tlb_invalidate_entry(data, iova, size);
1107
1108         spin_unlock_irqrestore(&domain->lock, flags);
1109 }
1110
1111 static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain,
1112                                  unsigned long l_iova, size_t size)
1113 {
1114         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1115         sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
1116         sysmmu_pte_t *ent;
1117         size_t err_pgsize;
1118         unsigned long flags;
1119
1120         BUG_ON(domain->pgtable == NULL);
1121
1122         spin_lock_irqsave(&domain->pgtablelock, flags);
1123
1124         ent = section_entry(domain->pgtable, iova);
1125
1126         if (lv1ent_section(ent)) {
1127                 if (WARN_ON(size < SECT_SIZE)) {
1128                         err_pgsize = SECT_SIZE;
1129                         goto err;
1130                 }
1131
1132                 /* workaround for h/w bug in System MMU v3.3 */
1133                 update_pte(ent, ZERO_LV2LINK);
1134                 size = SECT_SIZE;
1135                 goto done;
1136         }
1137
1138         if (unlikely(lv1ent_fault(ent))) {
1139                 if (size > SECT_SIZE)
1140                         size = SECT_SIZE;
1141                 goto done;
1142         }
1143
1144         /* lv1ent_page(sent) == true here */
1145
1146         ent = page_entry(ent, iova);
1147
1148         if (unlikely(lv2ent_fault(ent))) {
1149                 size = SPAGE_SIZE;
1150                 goto done;
1151         }
1152
1153         if (lv2ent_small(ent)) {
1154                 update_pte(ent, 0);
1155                 size = SPAGE_SIZE;
1156                 domain->lv2entcnt[lv1ent_offset(iova)] += 1;
1157                 goto done;
1158         }
1159
1160         /* lv1ent_large(ent) == true here */
1161         if (WARN_ON(size < LPAGE_SIZE)) {
1162                 err_pgsize = LPAGE_SIZE;
1163                 goto err;
1164         }
1165
1166         dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent),
1167                                 sizeof(*ent) * SPAGES_PER_LPAGE,
1168                                 DMA_TO_DEVICE);
1169         memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
1170         dma_sync_single_for_device(dma_dev, virt_to_phys(ent),
1171                                    sizeof(*ent) * SPAGES_PER_LPAGE,
1172                                    DMA_TO_DEVICE);
1173         size = LPAGE_SIZE;
1174         domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
1175 done:
1176         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1177
1178         exynos_iommu_tlb_invalidate_entry(domain, iova, size);
1179
1180         return size;
1181 err:
1182         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1183
1184         pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
1185                 __func__, size, iova, err_pgsize);
1186
1187         return 0;
1188 }
1189
1190 static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain,
1191                                           dma_addr_t iova)
1192 {
1193         struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain);
1194         sysmmu_pte_t *entry;
1195         unsigned long flags;
1196         phys_addr_t phys = 0;
1197
1198         spin_lock_irqsave(&domain->pgtablelock, flags);
1199
1200         entry = section_entry(domain->pgtable, iova);
1201
1202         if (lv1ent_section(entry)) {
1203                 phys = section_phys(entry) + section_offs(iova);
1204         } else if (lv1ent_page(entry)) {
1205                 entry = page_entry(entry, iova);
1206
1207                 if (lv2ent_large(entry))
1208                         phys = lpage_phys(entry) + lpage_offs(iova);
1209                 else if (lv2ent_small(entry))
1210                         phys = spage_phys(entry) + spage_offs(iova);
1211         }
1212
1213         spin_unlock_irqrestore(&domain->pgtablelock, flags);
1214
1215         return phys;
1216 }
1217
1218 static struct iommu_group *get_device_iommu_group(struct device *dev)
1219 {
1220         struct iommu_group *group;
1221
1222         group = iommu_group_get(dev);
1223         if (!group)
1224                 group = iommu_group_alloc();
1225
1226         return group;
1227 }
1228
1229 static int exynos_iommu_add_device(struct device *dev)
1230 {
1231         struct iommu_group *group;
1232
1233         if (!has_sysmmu(dev))
1234                 return -ENODEV;
1235
1236         group = iommu_group_get_for_dev(dev);
1237
1238         if (IS_ERR(group))
1239                 return PTR_ERR(group);
1240
1241         iommu_group_put(group);
1242
1243         return 0;
1244 }
1245
1246 static void exynos_iommu_remove_device(struct device *dev)
1247 {
1248         if (!has_sysmmu(dev))
1249                 return;
1250
1251         iommu_group_remove_device(dev);
1252 }
1253
1254 static int exynos_iommu_of_xlate(struct device *dev,
1255                                  struct of_phandle_args *spec)
1256 {
1257         struct exynos_iommu_owner *owner = dev->archdata.iommu;
1258         struct platform_device *sysmmu = of_find_device_by_node(spec->np);
1259         struct sysmmu_drvdata *data;
1260
1261         if (!sysmmu)
1262                 return -ENODEV;
1263
1264         data = platform_get_drvdata(sysmmu);
1265         if (!data)
1266                 return -ENODEV;
1267
1268         if (!owner) {
1269                 owner = kzalloc(sizeof(*owner), GFP_KERNEL);
1270                 if (!owner)
1271                         return -ENOMEM;
1272
1273                 INIT_LIST_HEAD(&owner->controllers);
1274                 dev->archdata.iommu = owner;
1275         }
1276
1277         list_add_tail(&data->owner_node, &owner->controllers);
1278         return 0;
1279 }
1280
1281 static struct iommu_ops exynos_iommu_ops = {
1282         .domain_alloc = exynos_iommu_domain_alloc,
1283         .domain_free = exynos_iommu_domain_free,
1284         .attach_dev = exynos_iommu_attach_device,
1285         .detach_dev = exynos_iommu_detach_device,
1286         .map = exynos_iommu_map,
1287         .unmap = exynos_iommu_unmap,
1288         .map_sg = default_iommu_map_sg,
1289         .iova_to_phys = exynos_iommu_iova_to_phys,
1290         .device_group = get_device_iommu_group,
1291         .add_device = exynos_iommu_add_device,
1292         .remove_device = exynos_iommu_remove_device,
1293         .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
1294         .of_xlate = exynos_iommu_of_xlate,
1295 };
1296
1297 static bool init_done;
1298
1299 static int __init exynos_iommu_init(void)
1300 {
1301         int ret;
1302
1303         lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
1304                                 LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
1305         if (!lv2table_kmem_cache) {
1306                 pr_err("%s: Failed to create kmem cache\n", __func__);
1307                 return -ENOMEM;
1308         }
1309
1310         ret = platform_driver_register(&exynos_sysmmu_driver);
1311         if (ret) {
1312                 pr_err("%s: Failed to register driver\n", __func__);
1313                 goto err_reg_driver;
1314         }
1315
1316         zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
1317         if (zero_lv2_table == NULL) {
1318                 pr_err("%s: Failed to allocate zero level2 page table\n",
1319                         __func__);
1320                 ret = -ENOMEM;
1321                 goto err_zero_lv2;
1322         }
1323
1324         ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
1325         if (ret) {
1326                 pr_err("%s: Failed to register exynos-iommu driver.\n",
1327                                                                 __func__);
1328                 goto err_set_iommu;
1329         }
1330
1331         init_done = true;
1332
1333         return 0;
1334 err_set_iommu:
1335         kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
1336 err_zero_lv2:
1337         platform_driver_unregister(&exynos_sysmmu_driver);
1338 err_reg_driver:
1339         kmem_cache_destroy(lv2table_kmem_cache);
1340         return ret;
1341 }
1342
1343 static int __init exynos_iommu_of_setup(struct device_node *np)
1344 {
1345         struct platform_device *pdev;
1346
1347         if (!init_done)
1348                 exynos_iommu_init();
1349
1350         pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
1351         if (IS_ERR(pdev))
1352                 return PTR_ERR(pdev);
1353
1354         /*
1355          * use the first registered sysmmu device for performing
1356          * dma mapping operations on iommu page tables (cpu cache flush)
1357          */
1358         if (!dma_dev)
1359                 dma_dev = &pdev->dev;
1360
1361         of_iommu_set_ops(np, &exynos_iommu_ops);
1362         return 0;
1363 }
1364
1365 IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu",
1366                  exynos_iommu_of_setup);