1 // SPDX-License-Identifier: GPL-2.0-only
3 * A fairly generic DMA-API to IOMMU-API glue layer.
5 * Copyright (C) 2014-2015 ARM Ltd.
7 * based in part on arch/arm/mm/dma-mapping.c:
8 * Copyright (C) 2000-2004 Russell King
11 #include <linux/acpi_iort.h>
12 #include <linux/device.h>
13 #include <linux/dma-map-ops.h>
14 #include <linux/dma-contiguous.h>
15 #include <linux/dma-iommu.h>
16 #include <linux/dma-noncoherent.h>
17 #include <linux/gfp.h>
18 #include <linux/huge_mm.h>
19 #include <linux/iommu.h>
20 #include <linux/iova.h>
21 #include <linux/irq.h>
23 #include <linux/mutex.h>
24 #include <linux/pci.h>
25 #include <linux/scatterlist.h>
26 #include <linux/vmalloc.h>
27 #include <linux/crash_dump.h>
29 struct iommu_dma_msi_page {
30 struct list_head list;
35 enum iommu_dma_cookie_type {
36 IOMMU_DMA_IOVA_COOKIE,
40 struct iommu_dma_cookie {
41 enum iommu_dma_cookie_type type;
43 /* Full allocator for IOMMU_DMA_IOVA_COOKIE */
44 struct iova_domain iovad;
45 /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */
48 struct list_head msi_page_list;
50 /* Domain for flush queue callback; NULL if flush queue not in use */
51 struct iommu_domain *fq_domain;
54 static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie)
56 if (cookie->type == IOMMU_DMA_IOVA_COOKIE)
57 return cookie->iovad.granule;
61 static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type)
63 struct iommu_dma_cookie *cookie;
65 cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
67 INIT_LIST_HEAD(&cookie->msi_page_list);
74 * iommu_get_dma_cookie - Acquire DMA-API resources for a domain
75 * @domain: IOMMU domain to prepare for DMA-API usage
77 * IOMMU drivers should normally call this from their domain_alloc
78 * callback when domain->type == IOMMU_DOMAIN_DMA.
80 int iommu_get_dma_cookie(struct iommu_domain *domain)
82 if (domain->iova_cookie)
85 domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE);
86 if (!domain->iova_cookie)
91 EXPORT_SYMBOL(iommu_get_dma_cookie);
94 * iommu_get_msi_cookie - Acquire just MSI remapping resources
95 * @domain: IOMMU domain to prepare
96 * @base: Start address of IOVA region for MSI mappings
98 * Users who manage their own IOVA allocation and do not want DMA API support,
99 * but would still like to take advantage of automatic MSI remapping, can use
100 * this to initialise their own domain appropriately. Users should reserve a
101 * contiguous IOVA region, starting at @base, large enough to accommodate the
102 * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address
103 * used by the devices attached to @domain.
105 int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
107 struct iommu_dma_cookie *cookie;
109 if (domain->type != IOMMU_DOMAIN_UNMANAGED)
112 if (domain->iova_cookie)
115 cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE);
119 cookie->msi_iova = base;
120 domain->iova_cookie = cookie;
123 EXPORT_SYMBOL(iommu_get_msi_cookie);
126 * iommu_put_dma_cookie - Release a domain's DMA mapping resources
127 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or
128 * iommu_get_msi_cookie()
130 * IOMMU drivers should normally call this from their domain_free callback.
132 void iommu_put_dma_cookie(struct iommu_domain *domain)
134 struct iommu_dma_cookie *cookie = domain->iova_cookie;
135 struct iommu_dma_msi_page *msi, *tmp;
140 if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule)
141 put_iova_domain(&cookie->iovad);
143 list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) {
144 list_del(&msi->list);
148 domain->iova_cookie = NULL;
150 EXPORT_SYMBOL(iommu_put_dma_cookie);
153 * iommu_dma_get_resv_regions - Reserved region driver helper
154 * @dev: Device from iommu_get_resv_regions()
155 * @list: Reserved region list from iommu_get_resv_regions()
157 * IOMMU drivers can use this to implement their .get_resv_regions callback
158 * for general non-IOMMU-specific reservations. Currently, this covers GICv3
159 * ITS region reservation on ACPI based ARM platforms that may require HW MSI
162 void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
165 if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode))
166 iort_iommu_msi_get_resv_regions(dev, list);
169 EXPORT_SYMBOL(iommu_dma_get_resv_regions);
171 static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie,
172 phys_addr_t start, phys_addr_t end)
174 struct iova_domain *iovad = &cookie->iovad;
175 struct iommu_dma_msi_page *msi_page;
178 start -= iova_offset(iovad, start);
179 num_pages = iova_align(iovad, end - start) >> iova_shift(iovad);
181 for (i = 0; i < num_pages; i++) {
182 msi_page = kmalloc(sizeof(*msi_page), GFP_KERNEL);
186 msi_page->phys = start;
187 msi_page->iova = start;
188 INIT_LIST_HEAD(&msi_page->list);
189 list_add(&msi_page->list, &cookie->msi_page_list);
190 start += iovad->granule;
196 static int iova_reserve_pci_windows(struct pci_dev *dev,
197 struct iova_domain *iovad)
199 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
200 struct resource_entry *window;
201 unsigned long lo, hi;
202 phys_addr_t start = 0, end;
204 resource_list_for_each_entry(window, &bridge->windows) {
205 if (resource_type(window->res) != IORESOURCE_MEM)
208 lo = iova_pfn(iovad, window->res->start - window->offset);
209 hi = iova_pfn(iovad, window->res->end - window->offset);
210 reserve_iova(iovad, lo, hi);
213 /* Get reserved DMA windows from host bridge */
214 resource_list_for_each_entry(window, &bridge->dma_ranges) {
215 end = window->res->start - window->offset;
218 lo = iova_pfn(iovad, start);
219 hi = iova_pfn(iovad, end);
220 reserve_iova(iovad, lo, hi);
222 /* dma_ranges list should be sorted */
223 dev_err(&dev->dev, "Failed to reserve IOVA\n");
227 start = window->res->end - window->offset + 1;
228 /* If window is last entry */
229 if (window->node.next == &bridge->dma_ranges &&
230 end != ~(phys_addr_t)0) {
231 end = ~(phys_addr_t)0;
239 static int iova_reserve_iommu_regions(struct device *dev,
240 struct iommu_domain *domain)
242 struct iommu_dma_cookie *cookie = domain->iova_cookie;
243 struct iova_domain *iovad = &cookie->iovad;
244 struct iommu_resv_region *region;
245 LIST_HEAD(resv_regions);
248 if (dev_is_pci(dev)) {
249 ret = iova_reserve_pci_windows(to_pci_dev(dev), iovad);
254 iommu_get_resv_regions(dev, &resv_regions);
255 list_for_each_entry(region, &resv_regions, list) {
256 unsigned long lo, hi;
258 /* We ARE the software that manages these! */
259 if (region->type == IOMMU_RESV_SW_MSI)
262 lo = iova_pfn(iovad, region->start);
263 hi = iova_pfn(iovad, region->start + region->length - 1);
264 reserve_iova(iovad, lo, hi);
266 if (region->type == IOMMU_RESV_MSI)
267 ret = cookie_init_hw_msi_region(cookie, region->start,
268 region->start + region->length);
272 iommu_put_resv_regions(dev, &resv_regions);
277 static void iommu_dma_flush_iotlb_all(struct iova_domain *iovad)
279 struct iommu_dma_cookie *cookie;
280 struct iommu_domain *domain;
282 cookie = container_of(iovad, struct iommu_dma_cookie, iovad);
283 domain = cookie->fq_domain;
285 * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE
286 * implies that ops->flush_iotlb_all must be non-NULL.
288 domain->ops->flush_iotlb_all(domain);
292 * iommu_dma_init_domain - Initialise a DMA mapping domain
293 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
294 * @base: IOVA at which the mappable address space starts
295 * @size: Size of IOVA space
296 * @dev: Device the domain is being initialised for
298 * @base and @size should be exact multiples of IOMMU page granularity to
299 * avoid rounding surprises. If necessary, we reserve the page at address 0
300 * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but
301 * any change which could make prior IOVAs invalid will fail.
303 static int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,
304 u64 size, struct device *dev)
306 struct iommu_dma_cookie *cookie = domain->iova_cookie;
307 unsigned long order, base_pfn;
308 struct iova_domain *iovad;
311 if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE)
314 iovad = &cookie->iovad;
316 /* Use the smallest supported page size for IOVA granularity */
317 order = __ffs(domain->pgsize_bitmap);
318 base_pfn = max_t(unsigned long, 1, base >> order);
320 /* Check the domain allows at least some access to the device... */
321 if (domain->geometry.force_aperture) {
322 if (base > domain->geometry.aperture_end ||
323 base + size <= domain->geometry.aperture_start) {
324 pr_warn("specified DMA range outside IOMMU capability\n");
327 /* ...then finally give it a kicking to make sure it fits */
328 base_pfn = max_t(unsigned long, base_pfn,
329 domain->geometry.aperture_start >> order);
332 /* start_pfn is always nonzero for an already-initialised domain */
333 if (iovad->start_pfn) {
334 if (1UL << order != iovad->granule ||
335 base_pfn != iovad->start_pfn) {
336 pr_warn("Incompatible range for DMA domain\n");
343 init_iova_domain(iovad, 1UL << order, base_pfn);
345 if (!cookie->fq_domain && !iommu_domain_get_attr(domain,
346 DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, &attr) && attr) {
347 cookie->fq_domain = domain;
348 init_iova_flush_queue(iovad, iommu_dma_flush_iotlb_all, NULL);
354 return iova_reserve_iommu_regions(dev, domain);
357 static int iommu_dma_deferred_attach(struct device *dev,
358 struct iommu_domain *domain)
360 const struct iommu_ops *ops = domain->ops;
362 if (!is_kdump_kernel())
365 if (unlikely(ops->is_attach_deferred &&
366 ops->is_attach_deferred(domain, dev)))
367 return iommu_attach_device(domain, dev);
373 * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API
375 * @dir: Direction of DMA transfer
376 * @coherent: Is the DMA master cache-coherent?
377 * @attrs: DMA attributes for the mapping
379 * Return: corresponding IOMMU API page protection flags
381 static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
384 int prot = coherent ? IOMMU_CACHE : 0;
386 if (attrs & DMA_ATTR_PRIVILEGED)
390 case DMA_BIDIRECTIONAL:
391 return prot | IOMMU_READ | IOMMU_WRITE;
393 return prot | IOMMU_READ;
394 case DMA_FROM_DEVICE:
395 return prot | IOMMU_WRITE;
401 static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain,
402 size_t size, u64 dma_limit, struct device *dev)
404 struct iommu_dma_cookie *cookie = domain->iova_cookie;
405 struct iova_domain *iovad = &cookie->iovad;
406 unsigned long shift, iova_len, iova = 0;
408 if (cookie->type == IOMMU_DMA_MSI_COOKIE) {
409 cookie->msi_iova += size;
410 return cookie->msi_iova - size;
413 shift = iova_shift(iovad);
414 iova_len = size >> shift;
416 * Freeing non-power-of-two-sized allocations back into the IOVA caches
417 * will come back to bite us badly, so we have to waste a bit of space
418 * rounding up anything cacheable to make sure that can't happen. The
419 * order of the unadjusted size will still match upon freeing.
421 if (iova_len < (1 << (IOVA_RANGE_CACHE_MAX_SIZE - 1)))
422 iova_len = roundup_pow_of_two(iova_len);
424 dma_limit = min_not_zero(dma_limit, dev->bus_dma_limit);
426 if (domain->geometry.force_aperture)
427 dma_limit = min(dma_limit, (u64)domain->geometry.aperture_end);
429 /* Try to get PCI devices a SAC address */
430 if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev))
431 iova = alloc_iova_fast(iovad, iova_len,
432 DMA_BIT_MASK(32) >> shift, false);
435 iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift,
438 return (dma_addr_t)iova << shift;
441 static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie,
442 dma_addr_t iova, size_t size)
444 struct iova_domain *iovad = &cookie->iovad;
446 /* The MSI case is only ever cleaning up its most recent allocation */
447 if (cookie->type == IOMMU_DMA_MSI_COOKIE)
448 cookie->msi_iova -= size;
449 else if (cookie->fq_domain) /* non-strict mode */
450 queue_iova(iovad, iova_pfn(iovad, iova),
451 size >> iova_shift(iovad), 0);
453 free_iova_fast(iovad, iova_pfn(iovad, iova),
454 size >> iova_shift(iovad));
457 static void __iommu_dma_unmap(struct device *dev, dma_addr_t dma_addr,
460 struct iommu_domain *domain = iommu_get_dma_domain(dev);
461 struct iommu_dma_cookie *cookie = domain->iova_cookie;
462 struct iova_domain *iovad = &cookie->iovad;
463 size_t iova_off = iova_offset(iovad, dma_addr);
464 struct iommu_iotlb_gather iotlb_gather;
467 dma_addr -= iova_off;
468 size = iova_align(iovad, size + iova_off);
469 iommu_iotlb_gather_init(&iotlb_gather);
471 unmapped = iommu_unmap_fast(domain, dma_addr, size, &iotlb_gather);
472 WARN_ON(unmapped != size);
474 if (!cookie->fq_domain)
475 iommu_tlb_sync(domain, &iotlb_gather);
476 iommu_dma_free_iova(cookie, dma_addr, size);
479 static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys,
480 size_t size, int prot, u64 dma_mask)
482 struct iommu_domain *domain = iommu_get_dma_domain(dev);
483 struct iommu_dma_cookie *cookie = domain->iova_cookie;
484 struct iova_domain *iovad = &cookie->iovad;
485 size_t iova_off = iova_offset(iovad, phys);
488 if (unlikely(iommu_dma_deferred_attach(dev, domain)))
489 return DMA_MAPPING_ERROR;
491 size = iova_align(iovad, size + iova_off);
493 iova = iommu_dma_alloc_iova(domain, size, dma_mask, dev);
495 return DMA_MAPPING_ERROR;
497 if (iommu_map_atomic(domain, iova, phys - iova_off, size, prot)) {
498 iommu_dma_free_iova(cookie, iova, size);
499 return DMA_MAPPING_ERROR;
501 return iova + iova_off;
504 static void __iommu_dma_free_pages(struct page **pages, int count)
507 __free_page(pages[count]);
511 static struct page **__iommu_dma_alloc_pages(struct device *dev,
512 unsigned int count, unsigned long order_mask, gfp_t gfp)
515 unsigned int i = 0, nid = dev_to_node(dev);
517 order_mask &= (2U << MAX_ORDER) - 1;
521 pages = kvzalloc(count * sizeof(*pages), GFP_KERNEL);
525 /* IOMMU can map any pages, so himem can also be used here */
526 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
529 struct page *page = NULL;
530 unsigned int order_size;
533 * Higher-order allocations are a convenience rather
534 * than a necessity, hence using __GFP_NORETRY until
535 * falling back to minimum-order allocations.
537 for (order_mask &= (2U << __fls(count)) - 1;
538 order_mask; order_mask &= ~order_size) {
539 unsigned int order = __fls(order_mask);
540 gfp_t alloc_flags = gfp;
542 order_size = 1U << order;
543 if (order_mask > order_size)
544 alloc_flags |= __GFP_NORETRY;
545 page = alloc_pages_node(nid, alloc_flags, order);
550 if (!PageCompound(page)) {
551 split_page(page, order);
553 } else if (!split_huge_page(page)) {
556 __free_pages(page, order);
559 __iommu_dma_free_pages(pages, i);
570 * iommu_dma_alloc_remap - Allocate and map a buffer contiguous in IOVA space
571 * @dev: Device to allocate memory for. Must be a real device
572 * attached to an iommu_dma_domain
573 * @size: Size of buffer in bytes
574 * @dma_handle: Out argument for allocated DMA handle
575 * @gfp: Allocation flags
576 * @prot: pgprot_t to use for the remapped mapping
577 * @attrs: DMA attributes for this allocation
579 * If @size is less than PAGE_SIZE, then a full CPU page will be allocated,
580 * but an IOMMU which supports smaller pages might not map the whole thing.
582 * Return: Mapped virtual address, or NULL on failure.
584 static void *iommu_dma_alloc_remap(struct device *dev, size_t size,
585 dma_addr_t *dma_handle, gfp_t gfp, pgprot_t prot,
588 struct iommu_domain *domain = iommu_get_dma_domain(dev);
589 struct iommu_dma_cookie *cookie = domain->iova_cookie;
590 struct iova_domain *iovad = &cookie->iovad;
591 bool coherent = dev_is_dma_coherent(dev);
592 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
593 unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap;
599 *dma_handle = DMA_MAPPING_ERROR;
601 if (unlikely(iommu_dma_deferred_attach(dev, domain)))
604 min_size = alloc_sizes & -alloc_sizes;
605 if (min_size < PAGE_SIZE) {
606 min_size = PAGE_SIZE;
607 alloc_sizes |= PAGE_SIZE;
609 size = ALIGN(size, min_size);
611 if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES)
612 alloc_sizes = min_size;
614 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
615 pages = __iommu_dma_alloc_pages(dev, count, alloc_sizes >> PAGE_SHIFT,
620 size = iova_align(iovad, size);
621 iova = iommu_dma_alloc_iova(domain, size, dev->coherent_dma_mask, dev);
625 if (sg_alloc_table_from_pages(&sgt, pages, count, 0, size, GFP_KERNEL))
628 if (!(ioprot & IOMMU_CACHE)) {
629 struct scatterlist *sg;
632 for_each_sg(sgt.sgl, sg, sgt.orig_nents, i)
633 arch_dma_prep_coherent(sg_page(sg), sg->length);
636 if (iommu_map_sg_atomic(domain, iova, sgt.sgl, sgt.orig_nents, ioprot)
640 vaddr = dma_common_pages_remap(pages, size, prot,
641 __builtin_return_address(0));
650 __iommu_dma_unmap(dev, iova, size);
654 iommu_dma_free_iova(cookie, iova, size);
656 __iommu_dma_free_pages(pages, count);
661 * __iommu_dma_mmap - Map a buffer into provided user VMA
662 * @pages: Array representing buffer from __iommu_dma_alloc()
663 * @size: Size of buffer in bytes
664 * @vma: VMA describing requested userspace mapping
666 * Maps the pages of the buffer in @pages into @vma. The caller is responsible
667 * for verifying the correct size and protection of @vma beforehand.
669 static int __iommu_dma_mmap(struct page **pages, size_t size,
670 struct vm_area_struct *vma)
672 return vm_map_pages(vma, pages, PAGE_ALIGN(size) >> PAGE_SHIFT);
675 static void iommu_dma_sync_single_for_cpu(struct device *dev,
676 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
680 if (dev_is_dma_coherent(dev))
683 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
684 arch_sync_dma_for_cpu(phys, size, dir);
687 static void iommu_dma_sync_single_for_device(struct device *dev,
688 dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
692 if (dev_is_dma_coherent(dev))
695 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
696 arch_sync_dma_for_device(phys, size, dir);
699 static void iommu_dma_sync_sg_for_cpu(struct device *dev,
700 struct scatterlist *sgl, int nelems,
701 enum dma_data_direction dir)
703 struct scatterlist *sg;
706 if (dev_is_dma_coherent(dev))
709 for_each_sg(sgl, sg, nelems, i)
710 arch_sync_dma_for_cpu(sg_phys(sg), sg->length, dir);
713 static void iommu_dma_sync_sg_for_device(struct device *dev,
714 struct scatterlist *sgl, int nelems,
715 enum dma_data_direction dir)
717 struct scatterlist *sg;
720 if (dev_is_dma_coherent(dev))
723 for_each_sg(sgl, sg, nelems, i)
724 arch_sync_dma_for_device(sg_phys(sg), sg->length, dir);
727 static dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
728 unsigned long offset, size_t size, enum dma_data_direction dir,
731 phys_addr_t phys = page_to_phys(page) + offset;
732 bool coherent = dev_is_dma_coherent(dev);
733 int prot = dma_info_to_prot(dir, coherent, attrs);
734 dma_addr_t dma_handle;
736 dma_handle = __iommu_dma_map(dev, phys, size, prot, dma_get_mask(dev));
737 if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
738 dma_handle != DMA_MAPPING_ERROR)
739 arch_sync_dma_for_device(phys, size, dir);
743 static void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
744 size_t size, enum dma_data_direction dir, unsigned long attrs)
746 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
747 iommu_dma_sync_single_for_cpu(dev, dma_handle, size, dir);
748 __iommu_dma_unmap(dev, dma_handle, size);
752 * Prepare a successfully-mapped scatterlist to give back to the caller.
754 * At this point the segments are already laid out by iommu_dma_map_sg() to
755 * avoid individually crossing any boundaries, so we merely need to check a
756 * segment's start address to avoid concatenating across one.
758 static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents,
761 struct scatterlist *s, *cur = sg;
762 unsigned long seg_mask = dma_get_seg_boundary(dev);
763 unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev);
766 for_each_sg(sg, s, nents, i) {
767 /* Restore this segment's original unaligned fields first */
768 unsigned int s_iova_off = sg_dma_address(s);
769 unsigned int s_length = sg_dma_len(s);
770 unsigned int s_iova_len = s->length;
772 s->offset += s_iova_off;
773 s->length = s_length;
774 sg_dma_address(s) = DMA_MAPPING_ERROR;
778 * Now fill in the real DMA data. If...
779 * - there is a valid output segment to append to
780 * - and this segment starts on an IOVA page boundary
781 * - but doesn't fall at a segment boundary
782 * - and wouldn't make the resulting output segment too long
784 if (cur_len && !s_iova_off && (dma_addr & seg_mask) &&
785 (max_len - cur_len >= s_length)) {
786 /* ...then concatenate it with the previous one */
789 /* Otherwise start the next output segment */
795 sg_dma_address(cur) = dma_addr + s_iova_off;
798 sg_dma_len(cur) = cur_len;
799 dma_addr += s_iova_len;
801 if (s_length + s_iova_off < s_iova_len)
808 * If mapping failed, then just restore the original list,
809 * but making sure the DMA fields are invalidated.
811 static void __invalidate_sg(struct scatterlist *sg, int nents)
813 struct scatterlist *s;
816 for_each_sg(sg, s, nents, i) {
817 if (sg_dma_address(s) != DMA_MAPPING_ERROR)
818 s->offset += sg_dma_address(s);
820 s->length = sg_dma_len(s);
821 sg_dma_address(s) = DMA_MAPPING_ERROR;
827 * The DMA API client is passing in a scatterlist which could describe
828 * any old buffer layout, but the IOMMU API requires everything to be
829 * aligned to IOMMU pages. Hence the need for this complicated bit of
830 * impedance-matching, to be able to hand off a suitably-aligned list,
831 * but still preserve the original offsets and sizes for the caller.
833 static int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg,
834 int nents, enum dma_data_direction dir, unsigned long attrs)
836 struct iommu_domain *domain = iommu_get_dma_domain(dev);
837 struct iommu_dma_cookie *cookie = domain->iova_cookie;
838 struct iova_domain *iovad = &cookie->iovad;
839 struct scatterlist *s, *prev = NULL;
840 int prot = dma_info_to_prot(dir, dev_is_dma_coherent(dev), attrs);
843 unsigned long mask = dma_get_seg_boundary(dev);
846 if (unlikely(iommu_dma_deferred_attach(dev, domain)))
849 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
850 iommu_dma_sync_sg_for_device(dev, sg, nents, dir);
853 * Work out how much IOVA space we need, and align the segments to
854 * IOVA granules for the IOMMU driver to handle. With some clever
855 * trickery we can modify the list in-place, but reversibly, by
856 * stashing the unaligned parts in the as-yet-unused DMA fields.
858 for_each_sg(sg, s, nents, i) {
859 size_t s_iova_off = iova_offset(iovad, s->offset);
860 size_t s_length = s->length;
861 size_t pad_len = (mask - iova_len + 1) & mask;
863 sg_dma_address(s) = s_iova_off;
864 sg_dma_len(s) = s_length;
865 s->offset -= s_iova_off;
866 s_length = iova_align(iovad, s_length + s_iova_off);
867 s->length = s_length;
870 * Due to the alignment of our single IOVA allocation, we can
871 * depend on these assumptions about the segment boundary mask:
872 * - If mask size >= IOVA size, then the IOVA range cannot
873 * possibly fall across a boundary, so we don't care.
874 * - If mask size < IOVA size, then the IOVA range must start
875 * exactly on a boundary, therefore we can lay things out
876 * based purely on segment lengths without needing to know
877 * the actual addresses beforehand.
878 * - The mask must be a power of 2, so pad_len == 0 if
879 * iova_len == 0, thus we cannot dereference prev the first
880 * time through here (i.e. before it has a meaningful value).
882 if (pad_len && pad_len < s_length - 1) {
883 prev->length += pad_len;
887 iova_len += s_length;
891 iova = iommu_dma_alloc_iova(domain, iova_len, dma_get_mask(dev), dev);
896 * We'll leave any physical concatenation to the IOMMU driver's
897 * implementation - it knows better than we do.
899 if (iommu_map_sg_atomic(domain, iova, sg, nents, prot) < iova_len)
902 return __finalise_sg(dev, sg, nents, iova);
905 iommu_dma_free_iova(cookie, iova, iova_len);
907 __invalidate_sg(sg, nents);
911 static void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
912 int nents, enum dma_data_direction dir, unsigned long attrs)
914 dma_addr_t start, end;
915 struct scatterlist *tmp;
918 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
919 iommu_dma_sync_sg_for_cpu(dev, sg, nents, dir);
922 * The scatterlist segments are mapped into a single
923 * contiguous IOVA allocation, so this is incredibly easy.
925 start = sg_dma_address(sg);
926 for_each_sg(sg_next(sg), tmp, nents - 1, i) {
927 if (sg_dma_len(tmp) == 0)
931 end = sg_dma_address(sg) + sg_dma_len(sg);
932 __iommu_dma_unmap(dev, start, end - start);
935 static dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
936 size_t size, enum dma_data_direction dir, unsigned long attrs)
938 return __iommu_dma_map(dev, phys, size,
939 dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO,
943 static void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
944 size_t size, enum dma_data_direction dir, unsigned long attrs)
946 __iommu_dma_unmap(dev, handle, size);
949 static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr)
951 size_t alloc_size = PAGE_ALIGN(size);
952 int count = alloc_size >> PAGE_SHIFT;
953 struct page *page = NULL, **pages = NULL;
955 /* Non-coherent atomic allocation? Easy */
956 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
957 dma_free_from_pool(dev, cpu_addr, alloc_size))
960 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
962 * If it the address is remapped, then it's either non-coherent
963 * or highmem CMA, or an iommu_dma_alloc_remap() construction.
965 pages = dma_common_find_pages(cpu_addr);
967 page = vmalloc_to_page(cpu_addr);
968 dma_common_free_remap(cpu_addr, alloc_size);
970 /* Lowmem means a coherent atomic or CMA allocation */
971 page = virt_to_page(cpu_addr);
975 __iommu_dma_free_pages(pages, count);
977 dma_free_contiguous(dev, page, alloc_size);
980 static void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr,
981 dma_addr_t handle, unsigned long attrs)
983 __iommu_dma_unmap(dev, handle, size);
984 __iommu_dma_free(dev, size, cpu_addr);
987 static void *iommu_dma_alloc_pages(struct device *dev, size_t size,
988 struct page **pagep, gfp_t gfp, unsigned long attrs)
990 bool coherent = dev_is_dma_coherent(dev);
991 size_t alloc_size = PAGE_ALIGN(size);
992 int node = dev_to_node(dev);
993 struct page *page = NULL;
996 page = dma_alloc_contiguous(dev, alloc_size, gfp);
998 page = alloc_pages_node(node, gfp, get_order(alloc_size));
1002 if (IS_ENABLED(CONFIG_DMA_REMAP) && (!coherent || PageHighMem(page))) {
1003 pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
1005 cpu_addr = dma_common_contiguous_remap(page, alloc_size,
1006 prot, __builtin_return_address(0));
1008 goto out_free_pages;
1011 arch_dma_prep_coherent(page, size);
1013 cpu_addr = page_address(page);
1017 memset(cpu_addr, 0, alloc_size);
1020 dma_free_contiguous(dev, page, alloc_size);
1024 static void *iommu_dma_alloc(struct device *dev, size_t size,
1025 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
1027 bool coherent = dev_is_dma_coherent(dev);
1028 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
1029 struct page *page = NULL;
1034 if (IS_ENABLED(CONFIG_DMA_REMAP) && gfpflags_allow_blocking(gfp) &&
1035 !(attrs & DMA_ATTR_FORCE_CONTIGUOUS)) {
1036 return iommu_dma_alloc_remap(dev, size, handle, gfp,
1037 dma_pgprot(dev, PAGE_KERNEL, attrs), attrs);
1040 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
1041 !gfpflags_allow_blocking(gfp) && !coherent)
1042 page = dma_alloc_from_pool(dev, PAGE_ALIGN(size), &cpu_addr,
1045 cpu_addr = iommu_dma_alloc_pages(dev, size, &page, gfp, attrs);
1049 *handle = __iommu_dma_map(dev, page_to_phys(page), size, ioprot,
1050 dev->coherent_dma_mask);
1051 if (*handle == DMA_MAPPING_ERROR) {
1052 __iommu_dma_free(dev, size, cpu_addr);
1059 #ifdef CONFIG_DMA_REMAP
1060 static void *iommu_dma_alloc_noncoherent(struct device *dev, size_t size,
1061 dma_addr_t *handle, enum dma_data_direction dir, gfp_t gfp)
1063 if (!gfpflags_allow_blocking(gfp)) {
1066 page = dma_common_alloc_pages(dev, size, handle, dir, gfp);
1069 return page_address(page);
1072 return iommu_dma_alloc_remap(dev, size, handle, gfp | __GFP_ZERO,
1076 static void iommu_dma_free_noncoherent(struct device *dev, size_t size,
1077 void *cpu_addr, dma_addr_t handle, enum dma_data_direction dir)
1079 __iommu_dma_unmap(dev, handle, size);
1080 __iommu_dma_free(dev, size, cpu_addr);
1083 #define iommu_dma_alloc_noncoherent NULL
1084 #define iommu_dma_free_noncoherent NULL
1085 #endif /* CONFIG_DMA_REMAP */
1087 static int iommu_dma_mmap(struct device *dev, struct vm_area_struct *vma,
1088 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1089 unsigned long attrs)
1091 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1092 unsigned long pfn, off = vma->vm_pgoff;
1095 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
1097 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
1100 if (off >= nr_pages || vma_pages(vma) > nr_pages - off)
1103 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
1104 struct page **pages = dma_common_find_pages(cpu_addr);
1107 return __iommu_dma_mmap(pages, size, vma);
1108 pfn = vmalloc_to_pfn(cpu_addr);
1110 pfn = page_to_pfn(virt_to_page(cpu_addr));
1113 return remap_pfn_range(vma, vma->vm_start, pfn + off,
1114 vma->vm_end - vma->vm_start,
1118 static int iommu_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
1119 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1120 unsigned long attrs)
1125 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) {
1126 struct page **pages = dma_common_find_pages(cpu_addr);
1129 return sg_alloc_table_from_pages(sgt, pages,
1130 PAGE_ALIGN(size) >> PAGE_SHIFT,
1131 0, size, GFP_KERNEL);
1134 page = vmalloc_to_page(cpu_addr);
1136 page = virt_to_page(cpu_addr);
1139 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
1141 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
1145 static unsigned long iommu_dma_get_merge_boundary(struct device *dev)
1147 struct iommu_domain *domain = iommu_get_dma_domain(dev);
1149 return (1UL << __ffs(domain->pgsize_bitmap)) - 1;
1152 static const struct dma_map_ops iommu_dma_ops = {
1153 .alloc = iommu_dma_alloc,
1154 .free = iommu_dma_free,
1155 .alloc_pages = dma_common_alloc_pages,
1156 .free_pages = dma_common_free_pages,
1157 .alloc_noncoherent = iommu_dma_alloc_noncoherent,
1158 .free_noncoherent = iommu_dma_free_noncoherent,
1159 .mmap = iommu_dma_mmap,
1160 .get_sgtable = iommu_dma_get_sgtable,
1161 .map_page = iommu_dma_map_page,
1162 .unmap_page = iommu_dma_unmap_page,
1163 .map_sg = iommu_dma_map_sg,
1164 .unmap_sg = iommu_dma_unmap_sg,
1165 .sync_single_for_cpu = iommu_dma_sync_single_for_cpu,
1166 .sync_single_for_device = iommu_dma_sync_single_for_device,
1167 .sync_sg_for_cpu = iommu_dma_sync_sg_for_cpu,
1168 .sync_sg_for_device = iommu_dma_sync_sg_for_device,
1169 .map_resource = iommu_dma_map_resource,
1170 .unmap_resource = iommu_dma_unmap_resource,
1171 .get_merge_boundary = iommu_dma_get_merge_boundary,
1175 * The IOMMU core code allocates the default DMA domain, which the underlying
1176 * IOMMU driver needs to support via the dma-iommu layer.
1178 void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size)
1180 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1186 * The IOMMU core code allocates the default DMA domain, which the
1187 * underlying IOMMU driver needs to support via the dma-iommu layer.
1189 if (domain->type == IOMMU_DOMAIN_DMA) {
1190 if (iommu_dma_init_domain(domain, dma_base, size, dev))
1192 dev->dma_ops = &iommu_dma_ops;
1197 pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n",
1201 static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
1202 phys_addr_t msi_addr, struct iommu_domain *domain)
1204 struct iommu_dma_cookie *cookie = domain->iova_cookie;
1205 struct iommu_dma_msi_page *msi_page;
1207 int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
1208 size_t size = cookie_msi_granule(cookie);
1210 msi_addr &= ~(phys_addr_t)(size - 1);
1211 list_for_each_entry(msi_page, &cookie->msi_page_list, list)
1212 if (msi_page->phys == msi_addr)
1215 msi_page = kzalloc(sizeof(*msi_page), GFP_KERNEL);
1219 iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev);
1223 if (iommu_map(domain, iova, msi_addr, size, prot))
1226 INIT_LIST_HEAD(&msi_page->list);
1227 msi_page->phys = msi_addr;
1228 msi_page->iova = iova;
1229 list_add(&msi_page->list, &cookie->msi_page_list);
1233 iommu_dma_free_iova(cookie, iova, size);
1239 int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
1241 struct device *dev = msi_desc_to_dev(desc);
1242 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1243 struct iommu_dma_msi_page *msi_page;
1244 static DEFINE_MUTEX(msi_prepare_lock); /* see below */
1246 if (!domain || !domain->iova_cookie) {
1247 desc->iommu_cookie = NULL;
1252 * In fact the whole prepare operation should already be serialised by
1253 * irq_domain_mutex further up the callchain, but that's pretty subtle
1254 * on its own, so consider this locking as failsafe documentation...
1256 mutex_lock(&msi_prepare_lock);
1257 msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain);
1258 mutex_unlock(&msi_prepare_lock);
1260 msi_desc_set_iommu_cookie(desc, msi_page);
1267 void iommu_dma_compose_msi_msg(struct msi_desc *desc,
1268 struct msi_msg *msg)
1270 struct device *dev = msi_desc_to_dev(desc);
1271 const struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
1272 const struct iommu_dma_msi_page *msi_page;
1274 msi_page = msi_desc_get_iommu_cookie(desc);
1276 if (!domain || !domain->iova_cookie || WARN_ON(!msi_page))
1279 msg->address_hi = upper_32_bits(msi_page->iova);
1280 msg->address_lo &= cookie_msi_granule(domain->iova_cookie) - 1;
1281 msg->address_lo += lower_32_bits(msi_page->iova);
1284 static int iommu_dma_init(void)
1286 return iova_cache_get();
1288 arch_initcall(iommu_dma_init);