2 * IOMMU API for ARM architected SMMUv3 implementations.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * Copyright (C) 2015 ARM Limited
18 * Author: Will Deacon <will.deacon@arm.com>
20 * This driver is powered by bad coffee and bombay mix.
23 #include <linux/acpi.h>
24 #include <linux/acpi_iort.h>
25 #include <linux/delay.h>
26 #include <linux/dma-iommu.h>
27 #include <linux/err.h>
28 #include <linux/interrupt.h>
29 #include <linux/iommu.h>
30 #include <linux/iopoll.h>
31 #include <linux/module.h>
32 #include <linux/msi.h>
34 #include <linux/of_address.h>
35 #include <linux/of_iommu.h>
36 #include <linux/of_platform.h>
37 #include <linux/pci.h>
38 #include <linux/platform_device.h>
40 #include <linux/amba/bus.h>
42 #include "io-pgtable.h"
45 #define ARM_SMMU_IDR0 0x0
46 #define IDR0_ST_LVL_SHIFT 27
47 #define IDR0_ST_LVL_MASK 0x3
48 #define IDR0_ST_LVL_2LVL (1 << IDR0_ST_LVL_SHIFT)
49 #define IDR0_STALL_MODEL_SHIFT 24
50 #define IDR0_STALL_MODEL_MASK 0x3
51 #define IDR0_STALL_MODEL_STALL (0 << IDR0_STALL_MODEL_SHIFT)
52 #define IDR0_STALL_MODEL_FORCE (2 << IDR0_STALL_MODEL_SHIFT)
53 #define IDR0_TTENDIAN_SHIFT 21
54 #define IDR0_TTENDIAN_MASK 0x3
55 #define IDR0_TTENDIAN_LE (2 << IDR0_TTENDIAN_SHIFT)
56 #define IDR0_TTENDIAN_BE (3 << IDR0_TTENDIAN_SHIFT)
57 #define IDR0_TTENDIAN_MIXED (0 << IDR0_TTENDIAN_SHIFT)
58 #define IDR0_CD2L (1 << 19)
59 #define IDR0_VMID16 (1 << 18)
60 #define IDR0_PRI (1 << 16)
61 #define IDR0_SEV (1 << 14)
62 #define IDR0_MSI (1 << 13)
63 #define IDR0_ASID16 (1 << 12)
64 #define IDR0_ATS (1 << 10)
65 #define IDR0_HYP (1 << 9)
66 #define IDR0_COHACC (1 << 4)
67 #define IDR0_TTF_SHIFT 2
68 #define IDR0_TTF_MASK 0x3
69 #define IDR0_TTF_AARCH64 (2 << IDR0_TTF_SHIFT)
70 #define IDR0_TTF_AARCH32_64 (3 << IDR0_TTF_SHIFT)
71 #define IDR0_S1P (1 << 1)
72 #define IDR0_S2P (1 << 0)
74 #define ARM_SMMU_IDR1 0x4
75 #define IDR1_TABLES_PRESET (1 << 30)
76 #define IDR1_QUEUES_PRESET (1 << 29)
77 #define IDR1_REL (1 << 28)
78 #define IDR1_CMDQ_SHIFT 21
79 #define IDR1_CMDQ_MASK 0x1f
80 #define IDR1_EVTQ_SHIFT 16
81 #define IDR1_EVTQ_MASK 0x1f
82 #define IDR1_PRIQ_SHIFT 11
83 #define IDR1_PRIQ_MASK 0x1f
84 #define IDR1_SSID_SHIFT 6
85 #define IDR1_SSID_MASK 0x1f
86 #define IDR1_SID_SHIFT 0
87 #define IDR1_SID_MASK 0x3f
89 #define ARM_SMMU_IDR5 0x14
90 #define IDR5_STALL_MAX_SHIFT 16
91 #define IDR5_STALL_MAX_MASK 0xffff
92 #define IDR5_GRAN64K (1 << 6)
93 #define IDR5_GRAN16K (1 << 5)
94 #define IDR5_GRAN4K (1 << 4)
95 #define IDR5_OAS_SHIFT 0
96 #define IDR5_OAS_MASK 0x7
97 #define IDR5_OAS_32_BIT (0 << IDR5_OAS_SHIFT)
98 #define IDR5_OAS_36_BIT (1 << IDR5_OAS_SHIFT)
99 #define IDR5_OAS_40_BIT (2 << IDR5_OAS_SHIFT)
100 #define IDR5_OAS_42_BIT (3 << IDR5_OAS_SHIFT)
101 #define IDR5_OAS_44_BIT (4 << IDR5_OAS_SHIFT)
102 #define IDR5_OAS_48_BIT (5 << IDR5_OAS_SHIFT)
104 #define ARM_SMMU_CR0 0x20
105 #define CR0_CMDQEN (1 << 3)
106 #define CR0_EVTQEN (1 << 2)
107 #define CR0_PRIQEN (1 << 1)
108 #define CR0_SMMUEN (1 << 0)
110 #define ARM_SMMU_CR0ACK 0x24
112 #define ARM_SMMU_CR1 0x28
116 #define CR1_CACHE_NC 0
117 #define CR1_CACHE_WB 1
118 #define CR1_CACHE_WT 2
119 #define CR1_TABLE_SH_SHIFT 10
120 #define CR1_TABLE_OC_SHIFT 8
121 #define CR1_TABLE_IC_SHIFT 6
122 #define CR1_QUEUE_SH_SHIFT 4
123 #define CR1_QUEUE_OC_SHIFT 2
124 #define CR1_QUEUE_IC_SHIFT 0
126 #define ARM_SMMU_CR2 0x2c
127 #define CR2_PTM (1 << 2)
128 #define CR2_RECINVSID (1 << 1)
129 #define CR2_E2H (1 << 0)
131 #define ARM_SMMU_GBPA 0x44
132 #define GBPA_ABORT (1 << 20)
133 #define GBPA_UPDATE (1 << 31)
135 #define ARM_SMMU_IRQ_CTRL 0x50
136 #define IRQ_CTRL_EVTQ_IRQEN (1 << 2)
137 #define IRQ_CTRL_PRIQ_IRQEN (1 << 1)
138 #define IRQ_CTRL_GERROR_IRQEN (1 << 0)
140 #define ARM_SMMU_IRQ_CTRLACK 0x54
142 #define ARM_SMMU_GERROR 0x60
143 #define GERROR_SFM_ERR (1 << 8)
144 #define GERROR_MSI_GERROR_ABT_ERR (1 << 7)
145 #define GERROR_MSI_PRIQ_ABT_ERR (1 << 6)
146 #define GERROR_MSI_EVTQ_ABT_ERR (1 << 5)
147 #define GERROR_MSI_CMDQ_ABT_ERR (1 << 4)
148 #define GERROR_PRIQ_ABT_ERR (1 << 3)
149 #define GERROR_EVTQ_ABT_ERR (1 << 2)
150 #define GERROR_CMDQ_ERR (1 << 0)
151 #define GERROR_ERR_MASK 0xfd
153 #define ARM_SMMU_GERRORN 0x64
155 #define ARM_SMMU_GERROR_IRQ_CFG0 0x68
156 #define ARM_SMMU_GERROR_IRQ_CFG1 0x70
157 #define ARM_SMMU_GERROR_IRQ_CFG2 0x74
159 #define ARM_SMMU_STRTAB_BASE 0x80
160 #define STRTAB_BASE_RA (1UL << 62)
161 #define STRTAB_BASE_ADDR_SHIFT 6
162 #define STRTAB_BASE_ADDR_MASK 0x3ffffffffffUL
164 #define ARM_SMMU_STRTAB_BASE_CFG 0x88
165 #define STRTAB_BASE_CFG_LOG2SIZE_SHIFT 0
166 #define STRTAB_BASE_CFG_LOG2SIZE_MASK 0x3f
167 #define STRTAB_BASE_CFG_SPLIT_SHIFT 6
168 #define STRTAB_BASE_CFG_SPLIT_MASK 0x1f
169 #define STRTAB_BASE_CFG_FMT_SHIFT 16
170 #define STRTAB_BASE_CFG_FMT_MASK 0x3
171 #define STRTAB_BASE_CFG_FMT_LINEAR (0 << STRTAB_BASE_CFG_FMT_SHIFT)
172 #define STRTAB_BASE_CFG_FMT_2LVL (1 << STRTAB_BASE_CFG_FMT_SHIFT)
174 #define ARM_SMMU_CMDQ_BASE 0x90
175 #define ARM_SMMU_CMDQ_PROD 0x98
176 #define ARM_SMMU_CMDQ_CONS 0x9c
178 #define ARM_SMMU_EVTQ_BASE 0xa0
179 #define ARM_SMMU_EVTQ_PROD 0x100a8
180 #define ARM_SMMU_EVTQ_CONS 0x100ac
181 #define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0
182 #define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8
183 #define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc
185 #define ARM_SMMU_PRIQ_BASE 0xc0
186 #define ARM_SMMU_PRIQ_PROD 0x100c8
187 #define ARM_SMMU_PRIQ_CONS 0x100cc
188 #define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0
189 #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8
190 #define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc
192 /* Common MSI config fields */
193 #define MSI_CFG0_ADDR_SHIFT 2
194 #define MSI_CFG0_ADDR_MASK 0x3fffffffffffUL
195 #define MSI_CFG2_SH_SHIFT 4
196 #define MSI_CFG2_SH_NSH (0UL << MSI_CFG2_SH_SHIFT)
197 #define MSI_CFG2_SH_OSH (2UL << MSI_CFG2_SH_SHIFT)
198 #define MSI_CFG2_SH_ISH (3UL << MSI_CFG2_SH_SHIFT)
199 #define MSI_CFG2_MEMATTR_SHIFT 0
200 #define MSI_CFG2_MEMATTR_DEVICE_nGnRE (0x1 << MSI_CFG2_MEMATTR_SHIFT)
202 #define Q_IDX(q, p) ((p) & ((1 << (q)->max_n_shift) - 1))
203 #define Q_WRP(q, p) ((p) & (1 << (q)->max_n_shift))
204 #define Q_OVERFLOW_FLAG (1 << 31)
205 #define Q_OVF(q, p) ((p) & Q_OVERFLOW_FLAG)
206 #define Q_ENT(q, p) ((q)->base + \
207 Q_IDX(q, p) * (q)->ent_dwords)
209 #define Q_BASE_RWA (1UL << 62)
210 #define Q_BASE_ADDR_SHIFT 5
211 #define Q_BASE_ADDR_MASK 0xfffffffffffUL
212 #define Q_BASE_LOG2SIZE_SHIFT 0
213 #define Q_BASE_LOG2SIZE_MASK 0x1fUL
218 * Linear: Enough to cover 1 << IDR1.SIDSIZE entries
219 * 2lvl: 128k L1 entries,
220 * 256 lazy entries per table (each table covers a PCI bus)
222 #define STRTAB_L1_SZ_SHIFT 20
223 #define STRTAB_SPLIT 8
225 #define STRTAB_L1_DESC_DWORDS 1
226 #define STRTAB_L1_DESC_SPAN_SHIFT 0
227 #define STRTAB_L1_DESC_SPAN_MASK 0x1fUL
228 #define STRTAB_L1_DESC_L2PTR_SHIFT 6
229 #define STRTAB_L1_DESC_L2PTR_MASK 0x3ffffffffffUL
231 #define STRTAB_STE_DWORDS 8
232 #define STRTAB_STE_0_V (1UL << 0)
233 #define STRTAB_STE_0_CFG_SHIFT 1
234 #define STRTAB_STE_0_CFG_MASK 0x7UL
235 #define STRTAB_STE_0_CFG_ABORT (0UL << STRTAB_STE_0_CFG_SHIFT)
236 #define STRTAB_STE_0_CFG_BYPASS (4UL << STRTAB_STE_0_CFG_SHIFT)
237 #define STRTAB_STE_0_CFG_S1_TRANS (5UL << STRTAB_STE_0_CFG_SHIFT)
238 #define STRTAB_STE_0_CFG_S2_TRANS (6UL << STRTAB_STE_0_CFG_SHIFT)
240 #define STRTAB_STE_0_S1FMT_SHIFT 4
241 #define STRTAB_STE_0_S1FMT_LINEAR (0UL << STRTAB_STE_0_S1FMT_SHIFT)
242 #define STRTAB_STE_0_S1CTXPTR_SHIFT 6
243 #define STRTAB_STE_0_S1CTXPTR_MASK 0x3ffffffffffUL
244 #define STRTAB_STE_0_S1CDMAX_SHIFT 59
245 #define STRTAB_STE_0_S1CDMAX_MASK 0x1fUL
247 #define STRTAB_STE_1_S1C_CACHE_NC 0UL
248 #define STRTAB_STE_1_S1C_CACHE_WBRA 1UL
249 #define STRTAB_STE_1_S1C_CACHE_WT 2UL
250 #define STRTAB_STE_1_S1C_CACHE_WB 3UL
251 #define STRTAB_STE_1_S1C_SH_NSH 0UL
252 #define STRTAB_STE_1_S1C_SH_OSH 2UL
253 #define STRTAB_STE_1_S1C_SH_ISH 3UL
254 #define STRTAB_STE_1_S1CIR_SHIFT 2
255 #define STRTAB_STE_1_S1COR_SHIFT 4
256 #define STRTAB_STE_1_S1CSH_SHIFT 6
258 #define STRTAB_STE_1_S1STALLD (1UL << 27)
260 #define STRTAB_STE_1_EATS_ABT 0UL
261 #define STRTAB_STE_1_EATS_TRANS 1UL
262 #define STRTAB_STE_1_EATS_S1CHK 2UL
263 #define STRTAB_STE_1_EATS_SHIFT 28
265 #define STRTAB_STE_1_STRW_NSEL1 0UL
266 #define STRTAB_STE_1_STRW_EL2 2UL
267 #define STRTAB_STE_1_STRW_SHIFT 30
269 #define STRTAB_STE_1_SHCFG_INCOMING 1UL
270 #define STRTAB_STE_1_SHCFG_SHIFT 44
272 #define STRTAB_STE_2_S2VMID_SHIFT 0
273 #define STRTAB_STE_2_S2VMID_MASK 0xffffUL
274 #define STRTAB_STE_2_VTCR_SHIFT 32
275 #define STRTAB_STE_2_VTCR_MASK 0x7ffffUL
276 #define STRTAB_STE_2_S2AA64 (1UL << 51)
277 #define STRTAB_STE_2_S2ENDI (1UL << 52)
278 #define STRTAB_STE_2_S2PTW (1UL << 54)
279 #define STRTAB_STE_2_S2R (1UL << 58)
281 #define STRTAB_STE_3_S2TTB_SHIFT 4
282 #define STRTAB_STE_3_S2TTB_MASK 0xfffffffffffUL
284 /* Context descriptor (stage-1 only) */
285 #define CTXDESC_CD_DWORDS 8
286 #define CTXDESC_CD_0_TCR_T0SZ_SHIFT 0
287 #define ARM64_TCR_T0SZ_SHIFT 0
288 #define ARM64_TCR_T0SZ_MASK 0x1fUL
289 #define CTXDESC_CD_0_TCR_TG0_SHIFT 6
290 #define ARM64_TCR_TG0_SHIFT 14
291 #define ARM64_TCR_TG0_MASK 0x3UL
292 #define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8
293 #define ARM64_TCR_IRGN0_SHIFT 8
294 #define ARM64_TCR_IRGN0_MASK 0x3UL
295 #define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10
296 #define ARM64_TCR_ORGN0_SHIFT 10
297 #define ARM64_TCR_ORGN0_MASK 0x3UL
298 #define CTXDESC_CD_0_TCR_SH0_SHIFT 12
299 #define ARM64_TCR_SH0_SHIFT 12
300 #define ARM64_TCR_SH0_MASK 0x3UL
301 #define CTXDESC_CD_0_TCR_EPD0_SHIFT 14
302 #define ARM64_TCR_EPD0_SHIFT 7
303 #define ARM64_TCR_EPD0_MASK 0x1UL
304 #define CTXDESC_CD_0_TCR_EPD1_SHIFT 30
305 #define ARM64_TCR_EPD1_SHIFT 23
306 #define ARM64_TCR_EPD1_MASK 0x1UL
308 #define CTXDESC_CD_0_ENDI (1UL << 15)
309 #define CTXDESC_CD_0_V (1UL << 31)
311 #define CTXDESC_CD_0_TCR_IPS_SHIFT 32
312 #define ARM64_TCR_IPS_SHIFT 32
313 #define ARM64_TCR_IPS_MASK 0x7UL
314 #define CTXDESC_CD_0_TCR_TBI0_SHIFT 38
315 #define ARM64_TCR_TBI0_SHIFT 37
316 #define ARM64_TCR_TBI0_MASK 0x1UL
318 #define CTXDESC_CD_0_AA64 (1UL << 41)
319 #define CTXDESC_CD_0_R (1UL << 45)
320 #define CTXDESC_CD_0_A (1UL << 46)
321 #define CTXDESC_CD_0_ASET_SHIFT 47
322 #define CTXDESC_CD_0_ASET_SHARED (0UL << CTXDESC_CD_0_ASET_SHIFT)
323 #define CTXDESC_CD_0_ASET_PRIVATE (1UL << CTXDESC_CD_0_ASET_SHIFT)
324 #define CTXDESC_CD_0_ASID_SHIFT 48
325 #define CTXDESC_CD_0_ASID_MASK 0xffffUL
327 #define CTXDESC_CD_1_TTB0_SHIFT 4
328 #define CTXDESC_CD_1_TTB0_MASK 0xfffffffffffUL
330 #define CTXDESC_CD_3_MAIR_SHIFT 0
332 /* Convert between AArch64 (CPU) TCR format and SMMU CD format */
333 #define ARM_SMMU_TCR2CD(tcr, fld) \
334 (((tcr) >> ARM64_TCR_##fld##_SHIFT & ARM64_TCR_##fld##_MASK) \
335 << CTXDESC_CD_0_TCR_##fld##_SHIFT)
338 #define CMDQ_ENT_DWORDS 2
339 #define CMDQ_MAX_SZ_SHIFT 8
341 #define CMDQ_ERR_SHIFT 24
342 #define CMDQ_ERR_MASK 0x7f
343 #define CMDQ_ERR_CERROR_NONE_IDX 0
344 #define CMDQ_ERR_CERROR_ILL_IDX 1
345 #define CMDQ_ERR_CERROR_ABT_IDX 2
347 #define CMDQ_0_OP_SHIFT 0
348 #define CMDQ_0_OP_MASK 0xffUL
349 #define CMDQ_0_SSV (1UL << 11)
351 #define CMDQ_PREFETCH_0_SID_SHIFT 32
352 #define CMDQ_PREFETCH_1_SIZE_SHIFT 0
353 #define CMDQ_PREFETCH_1_ADDR_MASK ~0xfffUL
355 #define CMDQ_CFGI_0_SID_SHIFT 32
356 #define CMDQ_CFGI_0_SID_MASK 0xffffffffUL
357 #define CMDQ_CFGI_1_LEAF (1UL << 0)
358 #define CMDQ_CFGI_1_RANGE_SHIFT 0
359 #define CMDQ_CFGI_1_RANGE_MASK 0x1fUL
361 #define CMDQ_TLBI_0_VMID_SHIFT 32
362 #define CMDQ_TLBI_0_ASID_SHIFT 48
363 #define CMDQ_TLBI_1_LEAF (1UL << 0)
364 #define CMDQ_TLBI_1_VA_MASK ~0xfffUL
365 #define CMDQ_TLBI_1_IPA_MASK 0xfffffffff000UL
367 #define CMDQ_PRI_0_SSID_SHIFT 12
368 #define CMDQ_PRI_0_SSID_MASK 0xfffffUL
369 #define CMDQ_PRI_0_SID_SHIFT 32
370 #define CMDQ_PRI_0_SID_MASK 0xffffffffUL
371 #define CMDQ_PRI_1_GRPID_SHIFT 0
372 #define CMDQ_PRI_1_GRPID_MASK 0x1ffUL
373 #define CMDQ_PRI_1_RESP_SHIFT 12
374 #define CMDQ_PRI_1_RESP_DENY (0UL << CMDQ_PRI_1_RESP_SHIFT)
375 #define CMDQ_PRI_1_RESP_FAIL (1UL << CMDQ_PRI_1_RESP_SHIFT)
376 #define CMDQ_PRI_1_RESP_SUCC (2UL << CMDQ_PRI_1_RESP_SHIFT)
378 #define CMDQ_SYNC_0_CS_SHIFT 12
379 #define CMDQ_SYNC_0_CS_NONE (0UL << CMDQ_SYNC_0_CS_SHIFT)
380 #define CMDQ_SYNC_0_CS_SEV (2UL << CMDQ_SYNC_0_CS_SHIFT)
383 #define EVTQ_ENT_DWORDS 4
384 #define EVTQ_MAX_SZ_SHIFT 7
386 #define EVTQ_0_ID_SHIFT 0
387 #define EVTQ_0_ID_MASK 0xffUL
390 #define PRIQ_ENT_DWORDS 2
391 #define PRIQ_MAX_SZ_SHIFT 8
393 #define PRIQ_0_SID_SHIFT 0
394 #define PRIQ_0_SID_MASK 0xffffffffUL
395 #define PRIQ_0_SSID_SHIFT 32
396 #define PRIQ_0_SSID_MASK 0xfffffUL
397 #define PRIQ_0_PERM_PRIV (1UL << 58)
398 #define PRIQ_0_PERM_EXEC (1UL << 59)
399 #define PRIQ_0_PERM_READ (1UL << 60)
400 #define PRIQ_0_PERM_WRITE (1UL << 61)
401 #define PRIQ_0_PRG_LAST (1UL << 62)
402 #define PRIQ_0_SSID_V (1UL << 63)
404 #define PRIQ_1_PRG_IDX_SHIFT 0
405 #define PRIQ_1_PRG_IDX_MASK 0x1ffUL
406 #define PRIQ_1_ADDR_SHIFT 12
407 #define PRIQ_1_ADDR_MASK 0xfffffffffffffUL
409 /* High-level queue structures */
410 #define ARM_SMMU_POLL_TIMEOUT_US 100
412 #define MSI_IOVA_BASE 0x8000000
413 #define MSI_IOVA_LENGTH 0x100000
415 static bool disable_bypass;
416 module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO);
417 MODULE_PARM_DESC(disable_bypass,
418 "Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
426 enum arm_smmu_msi_index {
433 static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
435 ARM_SMMU_EVTQ_IRQ_CFG0,
436 ARM_SMMU_EVTQ_IRQ_CFG1,
437 ARM_SMMU_EVTQ_IRQ_CFG2,
439 [GERROR_MSI_INDEX] = {
440 ARM_SMMU_GERROR_IRQ_CFG0,
441 ARM_SMMU_GERROR_IRQ_CFG1,
442 ARM_SMMU_GERROR_IRQ_CFG2,
445 ARM_SMMU_PRIQ_IRQ_CFG0,
446 ARM_SMMU_PRIQ_IRQ_CFG1,
447 ARM_SMMU_PRIQ_IRQ_CFG2,
451 struct arm_smmu_cmdq_ent {
454 bool substream_valid;
456 /* Command-specific fields */
458 #define CMDQ_OP_PREFETCH_CFG 0x1
465 #define CMDQ_OP_CFGI_STE 0x3
466 #define CMDQ_OP_CFGI_ALL 0x4
475 #define CMDQ_OP_TLBI_NH_ASID 0x11
476 #define CMDQ_OP_TLBI_NH_VA 0x12
477 #define CMDQ_OP_TLBI_EL2_ALL 0x20
478 #define CMDQ_OP_TLBI_S12_VMALL 0x28
479 #define CMDQ_OP_TLBI_S2_IPA 0x2a
480 #define CMDQ_OP_TLBI_NSNH_ALL 0x30
488 #define CMDQ_OP_PRI_RESP 0x41
496 #define CMDQ_OP_CMD_SYNC 0x46
500 struct arm_smmu_queue {
501 int irq; /* Wired interrupt */
512 u32 __iomem *prod_reg;
513 u32 __iomem *cons_reg;
516 struct arm_smmu_cmdq {
517 struct arm_smmu_queue q;
521 struct arm_smmu_evtq {
522 struct arm_smmu_queue q;
526 struct arm_smmu_priq {
527 struct arm_smmu_queue q;
530 /* High-level stream table and context descriptor structures */
531 struct arm_smmu_strtab_l1_desc {
535 dma_addr_t l2ptr_dma;
538 struct arm_smmu_s1_cfg {
540 dma_addr_t cdptr_dma;
542 struct arm_smmu_ctx_desc {
550 struct arm_smmu_s2_cfg {
556 struct arm_smmu_strtab_ent {
558 * An STE is "assigned" if the master emitting the corresponding SID
559 * is attached to a domain. The behaviour of an unassigned STE is
560 * determined by the disable_bypass parameter, whereas an assigned
561 * STE behaves according to s1_cfg/s2_cfg, which themselves are
562 * configured according to the domain type.
565 struct arm_smmu_s1_cfg *s1_cfg;
566 struct arm_smmu_s2_cfg *s2_cfg;
569 struct arm_smmu_strtab_cfg {
571 dma_addr_t strtab_dma;
572 struct arm_smmu_strtab_l1_desc *l1_desc;
573 unsigned int num_l1_ents;
579 /* An SMMUv3 instance */
580 struct arm_smmu_device {
584 #define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0)
585 #define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1)
586 #define ARM_SMMU_FEAT_TT_LE (1 << 2)
587 #define ARM_SMMU_FEAT_TT_BE (1 << 3)
588 #define ARM_SMMU_FEAT_PRI (1 << 4)
589 #define ARM_SMMU_FEAT_ATS (1 << 5)
590 #define ARM_SMMU_FEAT_SEV (1 << 6)
591 #define ARM_SMMU_FEAT_MSI (1 << 7)
592 #define ARM_SMMU_FEAT_COHERENCY (1 << 8)
593 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 9)
594 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 10)
595 #define ARM_SMMU_FEAT_STALLS (1 << 11)
596 #define ARM_SMMU_FEAT_HYP (1 << 12)
599 #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0)
602 struct arm_smmu_cmdq cmdq;
603 struct arm_smmu_evtq evtq;
604 struct arm_smmu_priq priq;
608 unsigned long ias; /* IPA */
609 unsigned long oas; /* PA */
610 unsigned long pgsize_bitmap;
612 #define ARM_SMMU_MAX_ASIDS (1 << 16)
613 unsigned int asid_bits;
614 DECLARE_BITMAP(asid_map, ARM_SMMU_MAX_ASIDS);
616 #define ARM_SMMU_MAX_VMIDS (1 << 16)
617 unsigned int vmid_bits;
618 DECLARE_BITMAP(vmid_map, ARM_SMMU_MAX_VMIDS);
620 unsigned int ssid_bits;
621 unsigned int sid_bits;
623 struct arm_smmu_strtab_cfg strtab_cfg;
625 /* IOMMU core code handle */
626 struct iommu_device iommu;
629 /* SMMU private data for each master */
630 struct arm_smmu_master_data {
631 struct arm_smmu_device *smmu;
632 struct arm_smmu_strtab_ent ste;
635 /* SMMU private data for an IOMMU domain */
636 enum arm_smmu_domain_stage {
637 ARM_SMMU_DOMAIN_S1 = 0,
639 ARM_SMMU_DOMAIN_NESTED,
640 ARM_SMMU_DOMAIN_BYPASS,
643 struct arm_smmu_domain {
644 struct arm_smmu_device *smmu;
645 struct mutex init_mutex; /* Protects smmu pointer */
647 struct io_pgtable_ops *pgtbl_ops;
648 spinlock_t pgtbl_lock;
650 enum arm_smmu_domain_stage stage;
652 struct arm_smmu_s1_cfg s1_cfg;
653 struct arm_smmu_s2_cfg s2_cfg;
656 struct iommu_domain domain;
659 struct arm_smmu_option_prop {
664 static struct arm_smmu_option_prop arm_smmu_options[] = {
665 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
669 static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
671 return container_of(dom, struct arm_smmu_domain, domain);
674 static void parse_driver_options(struct arm_smmu_device *smmu)
679 if (of_property_read_bool(smmu->dev->of_node,
680 arm_smmu_options[i].prop)) {
681 smmu->options |= arm_smmu_options[i].opt;
682 dev_notice(smmu->dev, "option %s\n",
683 arm_smmu_options[i].prop);
685 } while (arm_smmu_options[++i].opt);
688 /* Low-level queue manipulation functions */
689 static bool queue_full(struct arm_smmu_queue *q)
691 return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) &&
692 Q_WRP(q, q->prod) != Q_WRP(q, q->cons);
695 static bool queue_empty(struct arm_smmu_queue *q)
697 return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) &&
698 Q_WRP(q, q->prod) == Q_WRP(q, q->cons);
701 static void queue_sync_cons(struct arm_smmu_queue *q)
703 q->cons = readl_relaxed(q->cons_reg);
706 static void queue_inc_cons(struct arm_smmu_queue *q)
708 u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1;
710 q->cons = Q_OVF(q, q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons);
711 writel(q->cons, q->cons_reg);
714 static int queue_sync_prod(struct arm_smmu_queue *q)
717 u32 prod = readl_relaxed(q->prod_reg);
719 if (Q_OVF(q, prod) != Q_OVF(q, q->prod))
726 static void queue_inc_prod(struct arm_smmu_queue *q)
728 u32 prod = (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + 1;
730 q->prod = Q_OVF(q, q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod);
731 writel(q->prod, q->prod_reg);
735 * Wait for the SMMU to consume items. If drain is true, wait until the queue
736 * is empty. Otherwise, wait until there is at least one free slot.
738 static int queue_poll_cons(struct arm_smmu_queue *q, bool drain, bool wfe)
740 ktime_t timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US);
742 while (queue_sync_cons(q), (drain ? !queue_empty(q) : queue_full(q))) {
743 if (ktime_compare(ktime_get(), timeout) > 0)
757 static void queue_write(__le64 *dst, u64 *src, size_t n_dwords)
761 for (i = 0; i < n_dwords; ++i)
762 *dst++ = cpu_to_le64(*src++);
765 static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent)
770 queue_write(Q_ENT(q, q->prod), ent, q->ent_dwords);
775 static void queue_read(__le64 *dst, u64 *src, size_t n_dwords)
779 for (i = 0; i < n_dwords; ++i)
780 *dst++ = le64_to_cpu(*src++);
783 static int queue_remove_raw(struct arm_smmu_queue *q, u64 *ent)
788 queue_read(ent, Q_ENT(q, q->cons), q->ent_dwords);
793 /* High-level queue accessors */
794 static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent)
796 memset(cmd, 0, CMDQ_ENT_DWORDS << 3);
797 cmd[0] |= (ent->opcode & CMDQ_0_OP_MASK) << CMDQ_0_OP_SHIFT;
799 switch (ent->opcode) {
800 case CMDQ_OP_TLBI_EL2_ALL:
801 case CMDQ_OP_TLBI_NSNH_ALL:
803 case CMDQ_OP_PREFETCH_CFG:
804 cmd[0] |= (u64)ent->prefetch.sid << CMDQ_PREFETCH_0_SID_SHIFT;
805 cmd[1] |= ent->prefetch.size << CMDQ_PREFETCH_1_SIZE_SHIFT;
806 cmd[1] |= ent->prefetch.addr & CMDQ_PREFETCH_1_ADDR_MASK;
808 case CMDQ_OP_CFGI_STE:
809 cmd[0] |= (u64)ent->cfgi.sid << CMDQ_CFGI_0_SID_SHIFT;
810 cmd[1] |= ent->cfgi.leaf ? CMDQ_CFGI_1_LEAF : 0;
812 case CMDQ_OP_CFGI_ALL:
813 /* Cover the entire SID range */
814 cmd[1] |= CMDQ_CFGI_1_RANGE_MASK << CMDQ_CFGI_1_RANGE_SHIFT;
816 case CMDQ_OP_TLBI_NH_VA:
817 cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;
818 cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;
819 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK;
821 case CMDQ_OP_TLBI_S2_IPA:
822 cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT;
823 cmd[1] |= ent->tlbi.leaf ? CMDQ_TLBI_1_LEAF : 0;
824 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK;
826 case CMDQ_OP_TLBI_NH_ASID:
827 cmd[0] |= (u64)ent->tlbi.asid << CMDQ_TLBI_0_ASID_SHIFT;
829 case CMDQ_OP_TLBI_S12_VMALL:
830 cmd[0] |= (u64)ent->tlbi.vmid << CMDQ_TLBI_0_VMID_SHIFT;
832 case CMDQ_OP_PRI_RESP:
833 cmd[0] |= ent->substream_valid ? CMDQ_0_SSV : 0;
834 cmd[0] |= ent->pri.ssid << CMDQ_PRI_0_SSID_SHIFT;
835 cmd[0] |= (u64)ent->pri.sid << CMDQ_PRI_0_SID_SHIFT;
836 cmd[1] |= ent->pri.grpid << CMDQ_PRI_1_GRPID_SHIFT;
837 switch (ent->pri.resp) {
839 cmd[1] |= CMDQ_PRI_1_RESP_DENY;
842 cmd[1] |= CMDQ_PRI_1_RESP_FAIL;
845 cmd[1] |= CMDQ_PRI_1_RESP_SUCC;
851 case CMDQ_OP_CMD_SYNC:
852 cmd[0] |= CMDQ_SYNC_0_CS_SEV;
861 static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu)
863 static const char *cerror_str[] = {
864 [CMDQ_ERR_CERROR_NONE_IDX] = "No error",
865 [CMDQ_ERR_CERROR_ILL_IDX] = "Illegal command",
866 [CMDQ_ERR_CERROR_ABT_IDX] = "Abort on command fetch",
870 u64 cmd[CMDQ_ENT_DWORDS];
871 struct arm_smmu_queue *q = &smmu->cmdq.q;
872 u32 cons = readl_relaxed(q->cons_reg);
873 u32 idx = cons >> CMDQ_ERR_SHIFT & CMDQ_ERR_MASK;
874 struct arm_smmu_cmdq_ent cmd_sync = {
875 .opcode = CMDQ_OP_CMD_SYNC,
878 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons,
879 idx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : "Unknown");
882 case CMDQ_ERR_CERROR_ABT_IDX:
883 dev_err(smmu->dev, "retrying command fetch\n");
884 case CMDQ_ERR_CERROR_NONE_IDX:
886 case CMDQ_ERR_CERROR_ILL_IDX:
893 * We may have concurrent producers, so we need to be careful
894 * not to touch any of the shadow cmdq state.
896 queue_read(cmd, Q_ENT(q, cons), q->ent_dwords);
897 dev_err(smmu->dev, "skipping command in error state:\n");
898 for (i = 0; i < ARRAY_SIZE(cmd); ++i)
899 dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]);
901 /* Convert the erroneous command into a CMD_SYNC */
902 if (arm_smmu_cmdq_build_cmd(cmd, &cmd_sync)) {
903 dev_err(smmu->dev, "failed to convert to CMD_SYNC\n");
907 queue_write(Q_ENT(q, cons), cmd, q->ent_dwords);
910 static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu,
911 struct arm_smmu_cmdq_ent *ent)
913 u64 cmd[CMDQ_ENT_DWORDS];
915 bool wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV);
916 struct arm_smmu_queue *q = &smmu->cmdq.q;
918 if (arm_smmu_cmdq_build_cmd(cmd, ent)) {
919 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n",
924 spin_lock_irqsave(&smmu->cmdq.lock, flags);
925 while (queue_insert_raw(q, cmd) == -ENOSPC) {
926 if (queue_poll_cons(q, false, wfe))
927 dev_err_ratelimited(smmu->dev, "CMDQ timeout\n");
930 if (ent->opcode == CMDQ_OP_CMD_SYNC && queue_poll_cons(q, true, wfe))
931 dev_err_ratelimited(smmu->dev, "CMD_SYNC timeout\n");
932 spin_unlock_irqrestore(&smmu->cmdq.lock, flags);
935 /* Context descriptor manipulation functions */
936 static u64 arm_smmu_cpu_tcr_to_cd(u64 tcr)
940 /* Repack the TCR. Just care about TTBR0 for now */
941 val |= ARM_SMMU_TCR2CD(tcr, T0SZ);
942 val |= ARM_SMMU_TCR2CD(tcr, TG0);
943 val |= ARM_SMMU_TCR2CD(tcr, IRGN0);
944 val |= ARM_SMMU_TCR2CD(tcr, ORGN0);
945 val |= ARM_SMMU_TCR2CD(tcr, SH0);
946 val |= ARM_SMMU_TCR2CD(tcr, EPD0);
947 val |= ARM_SMMU_TCR2CD(tcr, EPD1);
948 val |= ARM_SMMU_TCR2CD(tcr, IPS);
949 val |= ARM_SMMU_TCR2CD(tcr, TBI0);
954 static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu,
955 struct arm_smmu_s1_cfg *cfg)
960 * We don't need to issue any invalidation here, as we'll invalidate
961 * the STE when installing the new entry anyway.
963 val = arm_smmu_cpu_tcr_to_cd(cfg->cd.tcr) |
967 CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET_PRIVATE |
968 CTXDESC_CD_0_AA64 | (u64)cfg->cd.asid << CTXDESC_CD_0_ASID_SHIFT |
970 cfg->cdptr[0] = cpu_to_le64(val);
972 val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK << CTXDESC_CD_1_TTB0_SHIFT;
973 cfg->cdptr[1] = cpu_to_le64(val);
975 cfg->cdptr[3] = cpu_to_le64(cfg->cd.mair << CTXDESC_CD_3_MAIR_SHIFT);
978 /* Stream table manipulation functions */
980 arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc)
984 val |= (desc->span & STRTAB_L1_DESC_SPAN_MASK)
985 << STRTAB_L1_DESC_SPAN_SHIFT;
986 val |= desc->l2ptr_dma &
987 STRTAB_L1_DESC_L2PTR_MASK << STRTAB_L1_DESC_L2PTR_SHIFT;
989 *dst = cpu_to_le64(val);
992 static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
994 struct arm_smmu_cmdq_ent cmd = {
995 .opcode = CMDQ_OP_CFGI_STE,
1002 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1003 cmd.opcode = CMDQ_OP_CMD_SYNC;
1004 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1007 static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
1008 __le64 *dst, struct arm_smmu_strtab_ent *ste)
1011 * This is hideously complicated, but we only really care about
1012 * three cases at the moment:
1014 * 1. Invalid (all zero) -> bypass/fault (init)
1015 * 2. Bypass/fault -> translation/bypass (attach)
1016 * 3. Translation/bypass -> bypass/fault (detach)
1018 * Given that we can't update the STE atomically and the SMMU
1019 * doesn't read the thing in a defined order, that leaves us
1020 * with the following maintenance requirements:
1022 * 1. Update Config, return (init time STEs aren't live)
1023 * 2. Write everything apart from dword 0, sync, write dword 0, sync
1024 * 3. Update Config, sync
1026 u64 val = le64_to_cpu(dst[0]);
1027 bool ste_live = false;
1028 struct arm_smmu_cmdq_ent prefetch_cmd = {
1029 .opcode = CMDQ_OP_PREFETCH_CFG,
1035 if (val & STRTAB_STE_0_V) {
1038 cfg = val & STRTAB_STE_0_CFG_MASK << STRTAB_STE_0_CFG_SHIFT;
1040 case STRTAB_STE_0_CFG_BYPASS:
1042 case STRTAB_STE_0_CFG_S1_TRANS:
1043 case STRTAB_STE_0_CFG_S2_TRANS:
1046 case STRTAB_STE_0_CFG_ABORT:
1050 BUG(); /* STE corruption */
1054 /* Nuke the existing STE_0 value, as we're going to rewrite it */
1055 val = STRTAB_STE_0_V;
1058 if (!ste->assigned || !(ste->s1_cfg || ste->s2_cfg)) {
1059 if (!ste->assigned && disable_bypass)
1060 val |= STRTAB_STE_0_CFG_ABORT;
1062 val |= STRTAB_STE_0_CFG_BYPASS;
1064 dst[0] = cpu_to_le64(val);
1065 dst[1] = cpu_to_le64(STRTAB_STE_1_SHCFG_INCOMING
1066 << STRTAB_STE_1_SHCFG_SHIFT);
1067 dst[2] = 0; /* Nuke the VMID */
1069 arm_smmu_sync_ste_for_sid(smmu, sid);
1075 dst[1] = cpu_to_le64(
1076 STRTAB_STE_1_S1C_CACHE_WBRA
1077 << STRTAB_STE_1_S1CIR_SHIFT |
1078 STRTAB_STE_1_S1C_CACHE_WBRA
1079 << STRTAB_STE_1_S1COR_SHIFT |
1080 STRTAB_STE_1_S1C_SH_ISH << STRTAB_STE_1_S1CSH_SHIFT |
1081 #ifdef CONFIG_PCI_ATS
1082 STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT |
1084 STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT);
1086 if (smmu->features & ARM_SMMU_FEAT_STALLS)
1087 dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
1089 val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK
1090 << STRTAB_STE_0_S1CTXPTR_SHIFT) |
1091 STRTAB_STE_0_CFG_S1_TRANS;
1096 dst[2] = cpu_to_le64(
1097 ste->s2_cfg->vmid << STRTAB_STE_2_S2VMID_SHIFT |
1098 (ste->s2_cfg->vtcr & STRTAB_STE_2_VTCR_MASK)
1099 << STRTAB_STE_2_VTCR_SHIFT |
1101 STRTAB_STE_2_S2ENDI |
1103 STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 |
1106 dst[3] = cpu_to_le64(ste->s2_cfg->vttbr &
1107 STRTAB_STE_3_S2TTB_MASK << STRTAB_STE_3_S2TTB_SHIFT);
1109 val |= STRTAB_STE_0_CFG_S2_TRANS;
1112 arm_smmu_sync_ste_for_sid(smmu, sid);
1113 dst[0] = cpu_to_le64(val);
1114 arm_smmu_sync_ste_for_sid(smmu, sid);
1116 /* It's likely that we'll want to use the new STE soon */
1117 if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH))
1118 arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);
1121 static void arm_smmu_init_bypass_stes(u64 *strtab, unsigned int nent)
1124 struct arm_smmu_strtab_ent ste = { .assigned = false };
1126 for (i = 0; i < nent; ++i) {
1127 arm_smmu_write_strtab_ent(NULL, -1, strtab, &ste);
1128 strtab += STRTAB_STE_DWORDS;
1132 static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid)
1136 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
1137 struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[sid >> STRTAB_SPLIT];
1142 size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3);
1143 strtab = &cfg->strtab[(sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS];
1145 desc->span = STRTAB_SPLIT + 1;
1146 desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, &desc->l2ptr_dma,
1147 GFP_KERNEL | __GFP_ZERO);
1150 "failed to allocate l2 stream table for SID %u\n",
1155 arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT);
1156 arm_smmu_write_strtab_l1_desc(strtab, desc);
1160 /* IRQ and event handlers */
1161 static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev)
1164 struct arm_smmu_device *smmu = dev;
1165 struct arm_smmu_queue *q = &smmu->evtq.q;
1166 u64 evt[EVTQ_ENT_DWORDS];
1169 while (!queue_remove_raw(q, evt)) {
1170 u8 id = evt[0] >> EVTQ_0_ID_SHIFT & EVTQ_0_ID_MASK;
1172 dev_info(smmu->dev, "event 0x%02x received:\n", id);
1173 for (i = 0; i < ARRAY_SIZE(evt); ++i)
1174 dev_info(smmu->dev, "\t0x%016llx\n",
1175 (unsigned long long)evt[i]);
1180 * Not much we can do on overflow, so scream and pretend we're
1183 if (queue_sync_prod(q) == -EOVERFLOW)
1184 dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n");
1185 } while (!queue_empty(q));
1187 /* Sync our overflow flag, as we believe we're up to speed */
1188 q->cons = Q_OVF(q, q->prod) | Q_WRP(q, q->cons) | Q_IDX(q, q->cons);
1192 static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)
1198 sid = evt[0] >> PRIQ_0_SID_SHIFT & PRIQ_0_SID_MASK;
1199 ssv = evt[0] & PRIQ_0_SSID_V;
1200 ssid = ssv ? evt[0] >> PRIQ_0_SSID_SHIFT & PRIQ_0_SSID_MASK : 0;
1201 last = evt[0] & PRIQ_0_PRG_LAST;
1202 grpid = evt[1] >> PRIQ_1_PRG_IDX_SHIFT & PRIQ_1_PRG_IDX_MASK;
1204 dev_info(smmu->dev, "unexpected PRI request received:\n");
1206 "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n",
1207 sid, ssid, grpid, last ? "L" : "",
1208 evt[0] & PRIQ_0_PERM_PRIV ? "" : "un",
1209 evt[0] & PRIQ_0_PERM_READ ? "R" : "",
1210 evt[0] & PRIQ_0_PERM_WRITE ? "W" : "",
1211 evt[0] & PRIQ_0_PERM_EXEC ? "X" : "",
1212 evt[1] & PRIQ_1_ADDR_MASK << PRIQ_1_ADDR_SHIFT);
1215 struct arm_smmu_cmdq_ent cmd = {
1216 .opcode = CMDQ_OP_PRI_RESP,
1217 .substream_valid = ssv,
1222 .resp = PRI_RESP_DENY,
1226 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1230 static irqreturn_t arm_smmu_priq_thread(int irq, void *dev)
1232 struct arm_smmu_device *smmu = dev;
1233 struct arm_smmu_queue *q = &smmu->priq.q;
1234 u64 evt[PRIQ_ENT_DWORDS];
1237 while (!queue_remove_raw(q, evt))
1238 arm_smmu_handle_ppr(smmu, evt);
1240 if (queue_sync_prod(q) == -EOVERFLOW)
1241 dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n");
1242 } while (!queue_empty(q));
1244 /* Sync our overflow flag, as we believe we're up to speed */
1245 q->cons = Q_OVF(q, q->prod) | Q_WRP(q, q->cons) | Q_IDX(q, q->cons);
1249 static irqreturn_t arm_smmu_cmdq_sync_handler(int irq, void *dev)
1251 /* We don't actually use CMD_SYNC interrupts for anything */
1255 static int arm_smmu_device_disable(struct arm_smmu_device *smmu);
1257 static irqreturn_t arm_smmu_gerror_handler(int irq, void *dev)
1259 u32 gerror, gerrorn, active;
1260 struct arm_smmu_device *smmu = dev;
1262 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR);
1263 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN);
1265 active = gerror ^ gerrorn;
1266 if (!(active & GERROR_ERR_MASK))
1267 return IRQ_NONE; /* No errors pending */
1270 "unexpected global error reported (0x%08x), this could be serious\n",
1273 if (active & GERROR_SFM_ERR) {
1274 dev_err(smmu->dev, "device has entered Service Failure Mode!\n");
1275 arm_smmu_device_disable(smmu);
1278 if (active & GERROR_MSI_GERROR_ABT_ERR)
1279 dev_warn(smmu->dev, "GERROR MSI write aborted\n");
1281 if (active & GERROR_MSI_PRIQ_ABT_ERR)
1282 dev_warn(smmu->dev, "PRIQ MSI write aborted\n");
1284 if (active & GERROR_MSI_EVTQ_ABT_ERR)
1285 dev_warn(smmu->dev, "EVTQ MSI write aborted\n");
1287 if (active & GERROR_MSI_CMDQ_ABT_ERR) {
1288 dev_warn(smmu->dev, "CMDQ MSI write aborted\n");
1289 arm_smmu_cmdq_sync_handler(irq, smmu->dev);
1292 if (active & GERROR_PRIQ_ABT_ERR)
1293 dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n");
1295 if (active & GERROR_EVTQ_ABT_ERR)
1296 dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n");
1298 if (active & GERROR_CMDQ_ERR)
1299 arm_smmu_cmdq_skip_err(smmu);
1301 writel(gerror, smmu->base + ARM_SMMU_GERRORN);
1305 /* IO_PGTABLE API */
1306 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
1308 struct arm_smmu_cmdq_ent cmd;
1310 cmd.opcode = CMDQ_OP_CMD_SYNC;
1311 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1314 static void arm_smmu_tlb_sync(void *cookie)
1316 struct arm_smmu_domain *smmu_domain = cookie;
1317 __arm_smmu_tlb_sync(smmu_domain->smmu);
1320 static void arm_smmu_tlb_inv_context(void *cookie)
1322 struct arm_smmu_domain *smmu_domain = cookie;
1323 struct arm_smmu_device *smmu = smmu_domain->smmu;
1324 struct arm_smmu_cmdq_ent cmd;
1326 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1327 cmd.opcode = CMDQ_OP_TLBI_NH_ASID;
1328 cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid;
1331 cmd.opcode = CMDQ_OP_TLBI_S12_VMALL;
1332 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid;
1335 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1336 __arm_smmu_tlb_sync(smmu);
1339 static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
1340 size_t granule, bool leaf, void *cookie)
1342 struct arm_smmu_domain *smmu_domain = cookie;
1343 struct arm_smmu_device *smmu = smmu_domain->smmu;
1344 struct arm_smmu_cmdq_ent cmd = {
1351 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1352 cmd.opcode = CMDQ_OP_TLBI_NH_VA;
1353 cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid;
1355 cmd.opcode = CMDQ_OP_TLBI_S2_IPA;
1356 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid;
1360 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
1361 cmd.tlbi.addr += granule;
1362 } while (size -= granule);
1365 static const struct iommu_gather_ops arm_smmu_gather_ops = {
1366 .tlb_flush_all = arm_smmu_tlb_inv_context,
1367 .tlb_add_flush = arm_smmu_tlb_inv_range_nosync,
1368 .tlb_sync = arm_smmu_tlb_sync,
1372 static bool arm_smmu_capable(enum iommu_cap cap)
1375 case IOMMU_CAP_CACHE_COHERENCY:
1377 case IOMMU_CAP_NOEXEC:
1384 static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
1386 struct arm_smmu_domain *smmu_domain;
1388 if (type != IOMMU_DOMAIN_UNMANAGED &&
1389 type != IOMMU_DOMAIN_DMA &&
1390 type != IOMMU_DOMAIN_IDENTITY)
1394 * Allocate the domain and initialise some of its data structures.
1395 * We can't really do anything meaningful until we've added a
1398 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
1402 if (type == IOMMU_DOMAIN_DMA &&
1403 iommu_get_dma_cookie(&smmu_domain->domain)) {
1408 mutex_init(&smmu_domain->init_mutex);
1409 spin_lock_init(&smmu_domain->pgtbl_lock);
1410 return &smmu_domain->domain;
1413 static int arm_smmu_bitmap_alloc(unsigned long *map, int span)
1415 int idx, size = 1 << span;
1418 idx = find_first_zero_bit(map, size);
1421 } while (test_and_set_bit(idx, map));
1426 static void arm_smmu_bitmap_free(unsigned long *map, int idx)
1428 clear_bit(idx, map);
1431 static void arm_smmu_domain_free(struct iommu_domain *domain)
1433 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1434 struct arm_smmu_device *smmu = smmu_domain->smmu;
1436 iommu_put_dma_cookie(domain);
1437 free_io_pgtable_ops(smmu_domain->pgtbl_ops);
1439 /* Free the CD and ASID, if we allocated them */
1440 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1441 struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
1444 dmam_free_coherent(smmu_domain->smmu->dev,
1445 CTXDESC_CD_DWORDS << 3,
1449 arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid);
1452 struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;
1454 arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid);
1460 static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain,
1461 struct io_pgtable_cfg *pgtbl_cfg)
1465 struct arm_smmu_device *smmu = smmu_domain->smmu;
1466 struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
1468 asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits);
1472 cfg->cdptr = dmam_alloc_coherent(smmu->dev, CTXDESC_CD_DWORDS << 3,
1474 GFP_KERNEL | __GFP_ZERO);
1476 dev_warn(smmu->dev, "failed to allocate context descriptor\n");
1481 cfg->cd.asid = (u16)asid;
1482 cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
1483 cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
1484 cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
1488 arm_smmu_bitmap_free(smmu->asid_map, asid);
1492 static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain,
1493 struct io_pgtable_cfg *pgtbl_cfg)
1496 struct arm_smmu_device *smmu = smmu_domain->smmu;
1497 struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;
1499 vmid = arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits);
1503 cfg->vmid = (u16)vmid;
1504 cfg->vttbr = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
1505 cfg->vtcr = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
1509 static int arm_smmu_domain_finalise(struct iommu_domain *domain)
1512 unsigned long ias, oas;
1513 enum io_pgtable_fmt fmt;
1514 struct io_pgtable_cfg pgtbl_cfg;
1515 struct io_pgtable_ops *pgtbl_ops;
1516 int (*finalise_stage_fn)(struct arm_smmu_domain *,
1517 struct io_pgtable_cfg *);
1518 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1519 struct arm_smmu_device *smmu = smmu_domain->smmu;
1521 if (domain->type == IOMMU_DOMAIN_IDENTITY) {
1522 smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS;
1526 /* Restrict the stage to what we can actually support */
1527 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
1528 smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
1529 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
1530 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
1532 switch (smmu_domain->stage) {
1533 case ARM_SMMU_DOMAIN_S1:
1536 fmt = ARM_64_LPAE_S1;
1537 finalise_stage_fn = arm_smmu_domain_finalise_s1;
1539 case ARM_SMMU_DOMAIN_NESTED:
1540 case ARM_SMMU_DOMAIN_S2:
1543 fmt = ARM_64_LPAE_S2;
1544 finalise_stage_fn = arm_smmu_domain_finalise_s2;
1550 pgtbl_cfg = (struct io_pgtable_cfg) {
1551 .pgsize_bitmap = smmu->pgsize_bitmap,
1554 .tlb = &arm_smmu_gather_ops,
1555 .iommu_dev = smmu->dev,
1558 pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
1562 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
1563 domain->geometry.aperture_end = (1UL << ias) - 1;
1564 domain->geometry.force_aperture = true;
1565 smmu_domain->pgtbl_ops = pgtbl_ops;
1567 ret = finalise_stage_fn(smmu_domain, &pgtbl_cfg);
1569 free_io_pgtable_ops(pgtbl_ops);
1574 static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid)
1577 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
1579 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
1580 struct arm_smmu_strtab_l1_desc *l1_desc;
1583 /* Two-level walk */
1584 idx = (sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS;
1585 l1_desc = &cfg->l1_desc[idx];
1586 idx = (sid & ((1 << STRTAB_SPLIT) - 1)) * STRTAB_STE_DWORDS;
1587 step = &l1_desc->l2ptr[idx];
1589 /* Simple linear lookup */
1590 step = &cfg->strtab[sid * STRTAB_STE_DWORDS];
1596 static void arm_smmu_install_ste_for_dev(struct iommu_fwspec *fwspec)
1599 struct arm_smmu_master_data *master = fwspec->iommu_priv;
1600 struct arm_smmu_device *smmu = master->smmu;
1602 for (i = 0; i < fwspec->num_ids; ++i) {
1603 u32 sid = fwspec->ids[i];
1604 __le64 *step = arm_smmu_get_step_for_sid(smmu, sid);
1606 arm_smmu_write_strtab_ent(smmu, sid, step, &master->ste);
1610 static void arm_smmu_detach_dev(struct device *dev)
1612 struct arm_smmu_master_data *master = dev->iommu_fwspec->iommu_priv;
1614 master->ste.assigned = false;
1615 arm_smmu_install_ste_for_dev(dev->iommu_fwspec);
1618 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1621 struct arm_smmu_device *smmu;
1622 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1623 struct arm_smmu_master_data *master;
1624 struct arm_smmu_strtab_ent *ste;
1626 if (!dev->iommu_fwspec)
1629 master = dev->iommu_fwspec->iommu_priv;
1630 smmu = master->smmu;
1633 /* Already attached to a different domain? */
1635 arm_smmu_detach_dev(dev);
1637 mutex_lock(&smmu_domain->init_mutex);
1639 if (!smmu_domain->smmu) {
1640 smmu_domain->smmu = smmu;
1641 ret = arm_smmu_domain_finalise(domain);
1643 smmu_domain->smmu = NULL;
1646 } else if (smmu_domain->smmu != smmu) {
1648 "cannot attach to SMMU %s (upstream of %s)\n",
1649 dev_name(smmu_domain->smmu->dev),
1650 dev_name(smmu->dev));
1655 ste->assigned = true;
1657 if (smmu_domain->stage == ARM_SMMU_DOMAIN_BYPASS) {
1660 } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1661 ste->s1_cfg = &smmu_domain->s1_cfg;
1663 arm_smmu_write_ctx_desc(smmu, ste->s1_cfg);
1666 ste->s2_cfg = &smmu_domain->s2_cfg;
1669 arm_smmu_install_ste_for_dev(dev->iommu_fwspec);
1671 mutex_unlock(&smmu_domain->init_mutex);
1675 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1676 phys_addr_t paddr, size_t size, int prot)
1679 unsigned long flags;
1680 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1681 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
1686 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1687 ret = ops->map(ops, iova, paddr, size, prot);
1688 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1693 arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size)
1696 unsigned long flags;
1697 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1698 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
1703 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1704 ret = ops->unmap(ops, iova, size);
1705 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1710 arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
1713 unsigned long flags;
1714 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1715 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
1717 if (domain->type == IOMMU_DOMAIN_IDENTITY)
1723 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1724 ret = ops->iova_to_phys(ops, iova);
1725 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1730 static struct platform_driver arm_smmu_driver;
1732 static int arm_smmu_match_node(struct device *dev, void *data)
1734 return dev->fwnode == data;
1738 struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode)
1740 struct device *dev = driver_find_device(&arm_smmu_driver.driver, NULL,
1741 fwnode, arm_smmu_match_node);
1743 return dev ? dev_get_drvdata(dev) : NULL;
1746 static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid)
1748 unsigned long limit = smmu->strtab_cfg.num_l1_ents;
1750 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB)
1751 limit *= 1UL << STRTAB_SPLIT;
1756 static struct iommu_ops arm_smmu_ops;
1758 static int arm_smmu_add_device(struct device *dev)
1761 struct arm_smmu_device *smmu;
1762 struct arm_smmu_master_data *master;
1763 struct iommu_fwspec *fwspec = dev->iommu_fwspec;
1764 struct iommu_group *group;
1766 if (!fwspec || fwspec->ops != &arm_smmu_ops)
1769 * We _can_ actually withstand dodgy bus code re-calling add_device()
1770 * without an intervening remove_device()/of_xlate() sequence, but
1771 * we're not going to do so quietly...
1773 if (WARN_ON_ONCE(fwspec->iommu_priv)) {
1774 master = fwspec->iommu_priv;
1775 smmu = master->smmu;
1777 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode);
1780 master = kzalloc(sizeof(*master), GFP_KERNEL);
1784 master->smmu = smmu;
1785 fwspec->iommu_priv = master;
1788 /* Check the SIDs are in range of the SMMU and our stream table */
1789 for (i = 0; i < fwspec->num_ids; i++) {
1790 u32 sid = fwspec->ids[i];
1792 if (!arm_smmu_sid_in_range(smmu, sid))
1795 /* Ensure l2 strtab is initialised */
1796 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
1797 ret = arm_smmu_init_l2_strtab(smmu, sid);
1803 group = iommu_group_get_for_dev(dev);
1804 if (!IS_ERR(group)) {
1805 iommu_group_put(group);
1806 iommu_device_link(&smmu->iommu, dev);
1809 return PTR_ERR_OR_ZERO(group);
1812 static void arm_smmu_remove_device(struct device *dev)
1814 struct iommu_fwspec *fwspec = dev->iommu_fwspec;
1815 struct arm_smmu_master_data *master;
1816 struct arm_smmu_device *smmu;
1818 if (!fwspec || fwspec->ops != &arm_smmu_ops)
1821 master = fwspec->iommu_priv;
1822 smmu = master->smmu;
1823 if (master && master->ste.assigned)
1824 arm_smmu_detach_dev(dev);
1825 iommu_group_remove_device(dev);
1826 iommu_device_unlink(&smmu->iommu, dev);
1828 iommu_fwspec_free(dev);
1831 static struct iommu_group *arm_smmu_device_group(struct device *dev)
1833 struct iommu_group *group;
1836 * We don't support devices sharing stream IDs other than PCI RID
1837 * aliases, since the necessary ID-to-device lookup becomes rather
1838 * impractical given a potential sparse 32-bit stream ID space.
1840 if (dev_is_pci(dev))
1841 group = pci_device_group(dev);
1843 group = generic_device_group(dev);
1848 static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
1849 enum iommu_attr attr, void *data)
1851 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1853 if (domain->type != IOMMU_DOMAIN_UNMANAGED)
1857 case DOMAIN_ATTR_NESTING:
1858 *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
1865 static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
1866 enum iommu_attr attr, void *data)
1869 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1871 if (domain->type != IOMMU_DOMAIN_UNMANAGED)
1874 mutex_lock(&smmu_domain->init_mutex);
1877 case DOMAIN_ATTR_NESTING:
1878 if (smmu_domain->smmu) {
1884 smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
1886 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
1894 mutex_unlock(&smmu_domain->init_mutex);
1898 static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args)
1900 return iommu_fwspec_add_ids(dev, args->args, 1);
1903 static void arm_smmu_get_resv_regions(struct device *dev,
1904 struct list_head *head)
1906 struct iommu_resv_region *region;
1907 int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
1909 region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH,
1910 prot, IOMMU_RESV_SW_MSI);
1914 list_add_tail(®ion->list, head);
1916 iommu_dma_get_resv_regions(dev, head);
1919 static void arm_smmu_put_resv_regions(struct device *dev,
1920 struct list_head *head)
1922 struct iommu_resv_region *entry, *next;
1924 list_for_each_entry_safe(entry, next, head, list)
1928 static struct iommu_ops arm_smmu_ops = {
1929 .capable = arm_smmu_capable,
1930 .domain_alloc = arm_smmu_domain_alloc,
1931 .domain_free = arm_smmu_domain_free,
1932 .attach_dev = arm_smmu_attach_dev,
1933 .map = arm_smmu_map,
1934 .unmap = arm_smmu_unmap,
1935 .map_sg = default_iommu_map_sg,
1936 .iova_to_phys = arm_smmu_iova_to_phys,
1937 .add_device = arm_smmu_add_device,
1938 .remove_device = arm_smmu_remove_device,
1939 .device_group = arm_smmu_device_group,
1940 .domain_get_attr = arm_smmu_domain_get_attr,
1941 .domain_set_attr = arm_smmu_domain_set_attr,
1942 .of_xlate = arm_smmu_of_xlate,
1943 .get_resv_regions = arm_smmu_get_resv_regions,
1944 .put_resv_regions = arm_smmu_put_resv_regions,
1945 .pgsize_bitmap = -1UL, /* Restricted during device attach */
1948 /* Probing and initialisation functions */
1949 static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
1950 struct arm_smmu_queue *q,
1951 unsigned long prod_off,
1952 unsigned long cons_off,
1955 size_t qsz = ((1 << q->max_n_shift) * dwords) << 3;
1957 q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma, GFP_KERNEL);
1959 dev_err(smmu->dev, "failed to allocate queue (0x%zx bytes)\n",
1964 q->prod_reg = smmu->base + prod_off;
1965 q->cons_reg = smmu->base + cons_off;
1966 q->ent_dwords = dwords;
1968 q->q_base = Q_BASE_RWA;
1969 q->q_base |= q->base_dma & Q_BASE_ADDR_MASK << Q_BASE_ADDR_SHIFT;
1970 q->q_base |= (q->max_n_shift & Q_BASE_LOG2SIZE_MASK)
1971 << Q_BASE_LOG2SIZE_SHIFT;
1973 q->prod = q->cons = 0;
1977 static int arm_smmu_init_queues(struct arm_smmu_device *smmu)
1982 spin_lock_init(&smmu->cmdq.lock);
1983 ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, ARM_SMMU_CMDQ_PROD,
1984 ARM_SMMU_CMDQ_CONS, CMDQ_ENT_DWORDS);
1989 ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, ARM_SMMU_EVTQ_PROD,
1990 ARM_SMMU_EVTQ_CONS, EVTQ_ENT_DWORDS);
1995 if (!(smmu->features & ARM_SMMU_FEAT_PRI))
1998 return arm_smmu_init_one_queue(smmu, &smmu->priq.q, ARM_SMMU_PRIQ_PROD,
1999 ARM_SMMU_PRIQ_CONS, PRIQ_ENT_DWORDS);
2002 static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu)
2005 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
2006 size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_ents;
2007 void *strtab = smmu->strtab_cfg.strtab;
2009 cfg->l1_desc = devm_kzalloc(smmu->dev, size, GFP_KERNEL);
2010 if (!cfg->l1_desc) {
2011 dev_err(smmu->dev, "failed to allocate l1 stream table desc\n");
2015 for (i = 0; i < cfg->num_l1_ents; ++i) {
2016 arm_smmu_write_strtab_l1_desc(strtab, &cfg->l1_desc[i]);
2017 strtab += STRTAB_L1_DESC_DWORDS << 3;
2023 static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu)
2028 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
2030 /* Calculate the L1 size, capped to the SIDSIZE. */
2031 size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3);
2032 size = min(size, smmu->sid_bits - STRTAB_SPLIT);
2033 cfg->num_l1_ents = 1 << size;
2035 size += STRTAB_SPLIT;
2036 if (size < smmu->sid_bits)
2038 "2-level strtab only covers %u/%u bits of SID\n",
2039 size, smmu->sid_bits);
2041 l1size = cfg->num_l1_ents * (STRTAB_L1_DESC_DWORDS << 3);
2042 strtab = dmam_alloc_coherent(smmu->dev, l1size, &cfg->strtab_dma,
2043 GFP_KERNEL | __GFP_ZERO);
2046 "failed to allocate l1 stream table (%u bytes)\n",
2050 cfg->strtab = strtab;
2052 /* Configure strtab_base_cfg for 2 levels */
2053 reg = STRTAB_BASE_CFG_FMT_2LVL;
2054 reg |= (size & STRTAB_BASE_CFG_LOG2SIZE_MASK)
2055 << STRTAB_BASE_CFG_LOG2SIZE_SHIFT;
2056 reg |= (STRTAB_SPLIT & STRTAB_BASE_CFG_SPLIT_MASK)
2057 << STRTAB_BASE_CFG_SPLIT_SHIFT;
2058 cfg->strtab_base_cfg = reg;
2060 return arm_smmu_init_l1_strtab(smmu);
2063 static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu)
2068 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
2070 size = (1 << smmu->sid_bits) * (STRTAB_STE_DWORDS << 3);
2071 strtab = dmam_alloc_coherent(smmu->dev, size, &cfg->strtab_dma,
2072 GFP_KERNEL | __GFP_ZERO);
2075 "failed to allocate linear stream table (%u bytes)\n",
2079 cfg->strtab = strtab;
2080 cfg->num_l1_ents = 1 << smmu->sid_bits;
2082 /* Configure strtab_base_cfg for a linear table covering all SIDs */
2083 reg = STRTAB_BASE_CFG_FMT_LINEAR;
2084 reg |= (smmu->sid_bits & STRTAB_BASE_CFG_LOG2SIZE_MASK)
2085 << STRTAB_BASE_CFG_LOG2SIZE_SHIFT;
2086 cfg->strtab_base_cfg = reg;
2088 arm_smmu_init_bypass_stes(strtab, cfg->num_l1_ents);
2092 static int arm_smmu_init_strtab(struct arm_smmu_device *smmu)
2097 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB)
2098 ret = arm_smmu_init_strtab_2lvl(smmu);
2100 ret = arm_smmu_init_strtab_linear(smmu);
2105 /* Set the strtab base address */
2106 reg = smmu->strtab_cfg.strtab_dma &
2107 STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT;
2108 reg |= STRTAB_BASE_RA;
2109 smmu->strtab_cfg.strtab_base = reg;
2111 /* Allocate the first VMID for stage-2 bypass STEs */
2112 set_bit(0, smmu->vmid_map);
2116 static int arm_smmu_init_structures(struct arm_smmu_device *smmu)
2120 ret = arm_smmu_init_queues(smmu);
2124 return arm_smmu_init_strtab(smmu);
2127 static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val,
2128 unsigned int reg_off, unsigned int ack_off)
2132 writel_relaxed(val, smmu->base + reg_off);
2133 return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val,
2134 1, ARM_SMMU_POLL_TIMEOUT_US);
2137 /* GBPA is "special" */
2138 static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr)
2141 u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA;
2143 ret = readl_relaxed_poll_timeout(gbpa, reg, !(reg & GBPA_UPDATE),
2144 1, ARM_SMMU_POLL_TIMEOUT_US);
2150 writel_relaxed(reg | GBPA_UPDATE, gbpa);
2151 return readl_relaxed_poll_timeout(gbpa, reg, !(reg & GBPA_UPDATE),
2152 1, ARM_SMMU_POLL_TIMEOUT_US);
2155 static void arm_smmu_free_msis(void *data)
2157 struct device *dev = data;
2158 platform_msi_domain_free_irqs(dev);
2161 static void arm_smmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
2163 phys_addr_t doorbell;
2164 struct device *dev = msi_desc_to_dev(desc);
2165 struct arm_smmu_device *smmu = dev_get_drvdata(dev);
2166 phys_addr_t *cfg = arm_smmu_msi_cfg[desc->platform.msi_index];
2168 doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
2169 doorbell &= MSI_CFG0_ADDR_MASK << MSI_CFG0_ADDR_SHIFT;
2171 writeq_relaxed(doorbell, smmu->base + cfg[0]);
2172 writel_relaxed(msg->data, smmu->base + cfg[1]);
2173 writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]);
2176 static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
2178 struct msi_desc *desc;
2179 int ret, nvec = ARM_SMMU_MAX_MSIS;
2180 struct device *dev = smmu->dev;
2182 /* Clear the MSI address regs */
2183 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0);
2184 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0);
2186 if (smmu->features & ARM_SMMU_FEAT_PRI)
2187 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0);
2191 if (!(smmu->features & ARM_SMMU_FEAT_MSI))
2194 /* Allocate MSIs for evtq, gerror and priq. Ignore cmdq */
2195 ret = platform_msi_domain_alloc_irqs(dev, nvec, arm_smmu_write_msi_msg);
2197 dev_warn(dev, "failed to allocate MSIs\n");
2201 for_each_msi_entry(desc, dev) {
2202 switch (desc->platform.msi_index) {
2203 case EVTQ_MSI_INDEX:
2204 smmu->evtq.q.irq = desc->irq;
2206 case GERROR_MSI_INDEX:
2207 smmu->gerr_irq = desc->irq;
2209 case PRIQ_MSI_INDEX:
2210 smmu->priq.q.irq = desc->irq;
2212 default: /* Unknown */
2217 /* Add callback to free MSIs on teardown */
2218 devm_add_action(dev, arm_smmu_free_msis, dev);
2221 static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
2224 u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN;
2226 /* Disable IRQs first */
2227 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL,
2228 ARM_SMMU_IRQ_CTRLACK);
2230 dev_err(smmu->dev, "failed to disable irqs\n");
2234 arm_smmu_setup_msis(smmu);
2236 /* Request interrupt lines */
2237 irq = smmu->evtq.q.irq;
2239 ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
2240 arm_smmu_evtq_thread,
2242 "arm-smmu-v3-evtq", smmu);
2244 dev_warn(smmu->dev, "failed to enable evtq irq\n");
2247 irq = smmu->cmdq.q.irq;
2249 ret = devm_request_irq(smmu->dev, irq,
2250 arm_smmu_cmdq_sync_handler, 0,
2251 "arm-smmu-v3-cmdq-sync", smmu);
2253 dev_warn(smmu->dev, "failed to enable cmdq-sync irq\n");
2256 irq = smmu->gerr_irq;
2258 ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler,
2259 0, "arm-smmu-v3-gerror", smmu);
2261 dev_warn(smmu->dev, "failed to enable gerror irq\n");
2264 if (smmu->features & ARM_SMMU_FEAT_PRI) {
2265 irq = smmu->priq.q.irq;
2267 ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
2268 arm_smmu_priq_thread,
2274 "failed to enable priq irq\n");
2276 irqen_flags |= IRQ_CTRL_PRIQ_IRQEN;
2280 /* Enable interrupt generation on the SMMU */
2281 ret = arm_smmu_write_reg_sync(smmu, irqen_flags,
2282 ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK);
2284 dev_warn(smmu->dev, "failed to enable irqs\n");
2289 static int arm_smmu_device_disable(struct arm_smmu_device *smmu)
2293 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_CR0, ARM_SMMU_CR0ACK);
2295 dev_err(smmu->dev, "failed to clear cr0\n");
2300 static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
2304 struct arm_smmu_cmdq_ent cmd;
2306 /* Clear CR0 and sync (disables SMMU and queue processing) */
2307 reg = readl_relaxed(smmu->base + ARM_SMMU_CR0);
2308 if (reg & CR0_SMMUEN)
2309 dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n");
2311 ret = arm_smmu_device_disable(smmu);
2315 /* CR1 (table and queue memory attributes) */
2316 reg = (CR1_SH_ISH << CR1_TABLE_SH_SHIFT) |
2317 (CR1_CACHE_WB << CR1_TABLE_OC_SHIFT) |
2318 (CR1_CACHE_WB << CR1_TABLE_IC_SHIFT) |
2319 (CR1_SH_ISH << CR1_QUEUE_SH_SHIFT) |
2320 (CR1_CACHE_WB << CR1_QUEUE_OC_SHIFT) |
2321 (CR1_CACHE_WB << CR1_QUEUE_IC_SHIFT);
2322 writel_relaxed(reg, smmu->base + ARM_SMMU_CR1);
2324 /* CR2 (random crap) */
2325 reg = CR2_PTM | CR2_RECINVSID | CR2_E2H;
2326 writel_relaxed(reg, smmu->base + ARM_SMMU_CR2);
2329 writeq_relaxed(smmu->strtab_cfg.strtab_base,
2330 smmu->base + ARM_SMMU_STRTAB_BASE);
2331 writel_relaxed(smmu->strtab_cfg.strtab_base_cfg,
2332 smmu->base + ARM_SMMU_STRTAB_BASE_CFG);
2335 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE);
2336 writel_relaxed(smmu->cmdq.q.prod, smmu->base + ARM_SMMU_CMDQ_PROD);
2337 writel_relaxed(smmu->cmdq.q.cons, smmu->base + ARM_SMMU_CMDQ_CONS);
2339 enables = CR0_CMDQEN;
2340 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
2343 dev_err(smmu->dev, "failed to enable command queue\n");
2347 /* Invalidate any cached configuration */
2348 cmd.opcode = CMDQ_OP_CFGI_ALL;
2349 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
2350 cmd.opcode = CMDQ_OP_CMD_SYNC;
2351 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
2353 /* Invalidate any stale TLB entries */
2354 if (smmu->features & ARM_SMMU_FEAT_HYP) {
2355 cmd.opcode = CMDQ_OP_TLBI_EL2_ALL;
2356 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
2359 cmd.opcode = CMDQ_OP_TLBI_NSNH_ALL;
2360 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
2361 cmd.opcode = CMDQ_OP_CMD_SYNC;
2362 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
2365 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE);
2366 writel_relaxed(smmu->evtq.q.prod, smmu->base + ARM_SMMU_EVTQ_PROD);
2367 writel_relaxed(smmu->evtq.q.cons, smmu->base + ARM_SMMU_EVTQ_CONS);
2369 enables |= CR0_EVTQEN;
2370 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
2373 dev_err(smmu->dev, "failed to enable event queue\n");
2378 if (smmu->features & ARM_SMMU_FEAT_PRI) {
2379 writeq_relaxed(smmu->priq.q.q_base,
2380 smmu->base + ARM_SMMU_PRIQ_BASE);
2381 writel_relaxed(smmu->priq.q.prod,
2382 smmu->base + ARM_SMMU_PRIQ_PROD);
2383 writel_relaxed(smmu->priq.q.cons,
2384 smmu->base + ARM_SMMU_PRIQ_CONS);
2386 enables |= CR0_PRIQEN;
2387 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
2390 dev_err(smmu->dev, "failed to enable PRI queue\n");
2395 ret = arm_smmu_setup_irqs(smmu);
2397 dev_err(smmu->dev, "failed to setup irqs\n");
2402 /* Enable the SMMU interface, or ensure bypass */
2403 if (!bypass || disable_bypass) {
2404 enables |= CR0_SMMUEN;
2406 ret = arm_smmu_update_gbpa(smmu, 0, GBPA_ABORT);
2408 dev_err(smmu->dev, "GBPA not responding to update\n");
2412 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
2415 dev_err(smmu->dev, "failed to enable SMMU interface\n");
2422 static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
2425 bool coherent = smmu->features & ARM_SMMU_FEAT_COHERENCY;
2428 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0);
2430 /* 2-level structures */
2431 if ((reg & IDR0_ST_LVL_MASK << IDR0_ST_LVL_SHIFT) == IDR0_ST_LVL_2LVL)
2432 smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB;
2434 if (reg & IDR0_CD2L)
2435 smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB;
2438 * Translation table endianness.
2439 * We currently require the same endianness as the CPU, but this
2440 * could be changed later by adding a new IO_PGTABLE_QUIRK.
2442 switch (reg & IDR0_TTENDIAN_MASK << IDR0_TTENDIAN_SHIFT) {
2443 case IDR0_TTENDIAN_MIXED:
2444 smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE;
2447 case IDR0_TTENDIAN_BE:
2448 smmu->features |= ARM_SMMU_FEAT_TT_BE;
2451 case IDR0_TTENDIAN_LE:
2452 smmu->features |= ARM_SMMU_FEAT_TT_LE;
2456 dev_err(smmu->dev, "unknown/unsupported TT endianness!\n");
2460 /* Boolean feature flags */
2461 if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI)
2462 smmu->features |= ARM_SMMU_FEAT_PRI;
2464 if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS)
2465 smmu->features |= ARM_SMMU_FEAT_ATS;
2468 smmu->features |= ARM_SMMU_FEAT_SEV;
2471 smmu->features |= ARM_SMMU_FEAT_MSI;
2474 smmu->features |= ARM_SMMU_FEAT_HYP;
2477 * The coherency feature as set by FW is used in preference to the ID
2478 * register, but warn on mismatch.
2480 if (!!(reg & IDR0_COHACC) != coherent)
2481 dev_warn(smmu->dev, "IDR0.COHACC overridden by dma-coherent property (%s)\n",
2482 coherent ? "true" : "false");
2484 switch (reg & IDR0_STALL_MODEL_MASK << IDR0_STALL_MODEL_SHIFT) {
2485 case IDR0_STALL_MODEL_STALL:
2487 case IDR0_STALL_MODEL_FORCE:
2488 smmu->features |= ARM_SMMU_FEAT_STALLS;
2492 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
2495 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
2497 if (!(reg & (IDR0_S1P | IDR0_S2P))) {
2498 dev_err(smmu->dev, "no translation support!\n");
2502 /* We only support the AArch64 table format at present */
2503 switch (reg & IDR0_TTF_MASK << IDR0_TTF_SHIFT) {
2504 case IDR0_TTF_AARCH32_64:
2507 case IDR0_TTF_AARCH64:
2510 dev_err(smmu->dev, "AArch64 table format not supported!\n");
2514 /* ASID/VMID sizes */
2515 smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8;
2516 smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8;
2519 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1);
2520 if (reg & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET | IDR1_REL)) {
2521 dev_err(smmu->dev, "embedded implementation not supported\n");
2525 /* Queue sizes, capped at 4k */
2526 smmu->cmdq.q.max_n_shift = min((u32)CMDQ_MAX_SZ_SHIFT,
2527 reg >> IDR1_CMDQ_SHIFT & IDR1_CMDQ_MASK);
2528 if (!smmu->cmdq.q.max_n_shift) {
2529 /* Odd alignment restrictions on the base, so ignore for now */
2530 dev_err(smmu->dev, "unit-length command queue not supported\n");
2534 smmu->evtq.q.max_n_shift = min((u32)EVTQ_MAX_SZ_SHIFT,
2535 reg >> IDR1_EVTQ_SHIFT & IDR1_EVTQ_MASK);
2536 smmu->priq.q.max_n_shift = min((u32)PRIQ_MAX_SZ_SHIFT,
2537 reg >> IDR1_PRIQ_SHIFT & IDR1_PRIQ_MASK);
2539 /* SID/SSID sizes */
2540 smmu->ssid_bits = reg >> IDR1_SSID_SHIFT & IDR1_SSID_MASK;
2541 smmu->sid_bits = reg >> IDR1_SID_SHIFT & IDR1_SID_MASK;
2544 * If the SMMU supports fewer bits than would fill a single L2 stream
2545 * table, use a linear table instead.
2547 if (smmu->sid_bits <= STRTAB_SPLIT)
2548 smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB;
2551 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5);
2553 /* Maximum number of outstanding stalls */
2554 smmu->evtq.max_stalls = reg >> IDR5_STALL_MAX_SHIFT
2555 & IDR5_STALL_MAX_MASK;
2558 if (reg & IDR5_GRAN64K)
2559 smmu->pgsize_bitmap |= SZ_64K | SZ_512M;
2560 if (reg & IDR5_GRAN16K)
2561 smmu->pgsize_bitmap |= SZ_16K | SZ_32M;
2562 if (reg & IDR5_GRAN4K)
2563 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
2565 if (arm_smmu_ops.pgsize_bitmap == -1UL)
2566 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
2568 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
2570 /* Output address size */
2571 switch (reg & IDR5_OAS_MASK << IDR5_OAS_SHIFT) {
2572 case IDR5_OAS_32_BIT:
2575 case IDR5_OAS_36_BIT:
2578 case IDR5_OAS_40_BIT:
2581 case IDR5_OAS_42_BIT:
2584 case IDR5_OAS_44_BIT:
2589 "unknown output address size. Truncating to 48-bit\n");
2591 case IDR5_OAS_48_BIT:
2595 /* Set the DMA mask for our table walker */
2596 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas)))
2598 "failed to set DMA mask for table walker\n");
2600 smmu->ias = max(smmu->ias, smmu->oas);
2602 dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n",
2603 smmu->ias, smmu->oas, smmu->features);
2608 static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
2609 struct arm_smmu_device *smmu)
2611 struct acpi_iort_smmu_v3 *iort_smmu;
2612 struct device *dev = smmu->dev;
2613 struct acpi_iort_node *node;
2615 node = *(struct acpi_iort_node **)dev_get_platdata(dev);
2617 /* Retrieve SMMUv3 specific data */
2618 iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
2620 if (iort_smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE)
2621 smmu->features |= ARM_SMMU_FEAT_COHERENCY;
2626 static inline int arm_smmu_device_acpi_probe(struct platform_device *pdev,
2627 struct arm_smmu_device *smmu)
2633 static int arm_smmu_device_dt_probe(struct platform_device *pdev,
2634 struct arm_smmu_device *smmu)
2636 struct device *dev = &pdev->dev;
2640 if (of_property_read_u32(dev->of_node, "#iommu-cells", &cells))
2641 dev_err(dev, "missing #iommu-cells property\n");
2642 else if (cells != 1)
2643 dev_err(dev, "invalid #iommu-cells value (%d)\n", cells);
2647 parse_driver_options(smmu);
2649 if (of_dma_is_coherent(dev->of_node))
2650 smmu->features |= ARM_SMMU_FEAT_COHERENCY;
2655 static int arm_smmu_device_probe(struct platform_device *pdev)
2658 struct resource *res;
2659 resource_size_t ioaddr;
2660 struct arm_smmu_device *smmu;
2661 struct device *dev = &pdev->dev;
2664 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
2666 dev_err(dev, "failed to allocate arm_smmu_device\n");
2672 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2673 if (resource_size(res) + 1 < SZ_128K) {
2674 dev_err(dev, "MMIO region too small (%pr)\n", res);
2677 ioaddr = res->start;
2679 smmu->base = devm_ioremap_resource(dev, res);
2680 if (IS_ERR(smmu->base))
2681 return PTR_ERR(smmu->base);
2683 /* Interrupt lines */
2684 irq = platform_get_irq_byname(pdev, "eventq");
2686 smmu->evtq.q.irq = irq;
2688 irq = platform_get_irq_byname(pdev, "priq");
2690 smmu->priq.q.irq = irq;
2692 irq = platform_get_irq_byname(pdev, "cmdq-sync");
2694 smmu->cmdq.q.irq = irq;
2696 irq = platform_get_irq_byname(pdev, "gerror");
2698 smmu->gerr_irq = irq;
2701 ret = arm_smmu_device_dt_probe(pdev, smmu);
2703 ret = arm_smmu_device_acpi_probe(pdev, smmu);
2708 /* Set bypass mode according to firmware probing result */
2712 ret = arm_smmu_device_hw_probe(smmu);
2716 /* Initialise in-memory data structures */
2717 ret = arm_smmu_init_structures(smmu);
2721 /* Record our private device structure */
2722 platform_set_drvdata(pdev, smmu);
2724 /* Reset the device */
2725 ret = arm_smmu_device_reset(smmu, bypass);
2729 /* And we're up. Go go go! */
2730 ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL,
2731 "smmu3.%pa", &ioaddr);
2735 iommu_device_set_ops(&smmu->iommu, &arm_smmu_ops);
2736 iommu_device_set_fwnode(&smmu->iommu, dev->fwnode);
2738 ret = iommu_device_register(&smmu->iommu);
2741 if (pci_bus_type.iommu_ops != &arm_smmu_ops) {
2743 ret = bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
2748 #ifdef CONFIG_ARM_AMBA
2749 if (amba_bustype.iommu_ops != &arm_smmu_ops) {
2750 ret = bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2755 if (platform_bus_type.iommu_ops != &arm_smmu_ops) {
2756 ret = bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2763 static int arm_smmu_device_remove(struct platform_device *pdev)
2765 struct arm_smmu_device *smmu = platform_get_drvdata(pdev);
2767 arm_smmu_device_disable(smmu);
2771 static struct of_device_id arm_smmu_of_match[] = {
2772 { .compatible = "arm,smmu-v3", },
2775 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
2777 static struct platform_driver arm_smmu_driver = {
2779 .name = "arm-smmu-v3",
2780 .of_match_table = of_match_ptr(arm_smmu_of_match),
2782 .probe = arm_smmu_device_probe,
2783 .remove = arm_smmu_device_remove,
2785 module_platform_driver(arm_smmu_driver);
2787 IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3", NULL);
2789 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
2790 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2791 MODULE_LICENSE("GPL v2");