2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dma-direct.h>
32 #include <linux/iommu-helper.h>
33 #include <linux/iommu.h>
34 #include <linux/delay.h>
35 #include <linux/amd-iommu.h>
36 #include <linux/notifier.h>
37 #include <linux/export.h>
38 #include <linux/irq.h>
39 #include <linux/msi.h>
40 #include <linux/dma-contiguous.h>
41 #include <linux/irqdomain.h>
42 #include <linux/percpu.h>
43 #include <linux/iova.h>
44 #include <asm/irq_remapping.h>
45 #include <asm/io_apic.h>
47 #include <asm/hw_irq.h>
48 #include <asm/msidef.h>
49 #include <asm/proto.h>
50 #include <asm/iommu.h>
54 #include "amd_iommu_proto.h"
55 #include "amd_iommu_types.h"
56 #include "irq_remapping.h"
58 #define AMD_IOMMU_MAPPING_ERROR 0
60 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
62 #define LOOP_TIMEOUT 100000
64 /* IO virtual address start page frame number */
65 #define IOVA_START_PFN (1)
66 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
80 * 512GB Pages are not supported due to a hardware bug
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
84 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
85 static DEFINE_SPINLOCK(pd_bitmap_lock);
87 /* List of all available dev_data structures */
88 static LLIST_HEAD(dev_data_list);
90 LIST_HEAD(ioapic_map);
92 LIST_HEAD(acpihid_map);
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
98 const struct iommu_ops amd_iommu_ops;
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
103 static const struct dma_map_ops amd_iommu_dma_ops;
106 * general struct to manage commands send to an IOMMU
112 struct kmem_cache *amd_iommu_irq_cache;
114 static void update_domain(struct protection_domain *domain);
115 static int protection_domain_init(struct protection_domain *domain);
116 static void detach_device(struct device *dev);
117 static void iova_domain_flush_tlb(struct iova_domain *iovad);
120 * Data container for a dma_ops specific protection domain
122 struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
127 struct iova_domain iovad;
130 static struct iova_domain reserved_iova_ranges;
131 static struct lock_class_key reserved_rbtree_key;
133 /****************************************************************************
137 ****************************************************************************/
139 static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
142 const char *hid, *uid;
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
151 return strcmp(hid, entry->hid);
154 return strcmp(hid, entry->hid);
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
159 static inline u16 get_pci_device_id(struct device *dev)
161 struct pci_dev *pdev = to_pci_dev(dev);
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
166 static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
169 struct acpihid_map_entry *p;
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
181 static inline int get_device_id(struct device *dev)
186 devid = get_pci_device_id(dev);
188 devid = get_acpihid_device_id(dev, NULL);
193 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
195 return container_of(dom, struct protection_domain, domain);
198 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
204 static struct iommu_dev_data *alloc_dev_data(u16 devid)
206 struct iommu_dev_data *dev_data;
208 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
212 dev_data->devid = devid;
213 ratelimit_default_init(&dev_data->rs);
215 llist_add(&dev_data->dev_data_list, &dev_data_list);
219 static struct iommu_dev_data *search_dev_data(u16 devid)
221 struct iommu_dev_data *dev_data;
222 struct llist_node *node;
224 if (llist_empty(&dev_data_list))
227 node = dev_data_list.first;
228 llist_for_each_entry(dev_data, node, dev_data_list) {
229 if (dev_data->devid == devid)
236 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
238 *(u16 *)data = alias;
242 static u16 get_alias(struct device *dev)
244 struct pci_dev *pdev = to_pci_dev(dev);
245 u16 devid, ivrs_alias, pci_alias;
247 /* The callers make sure that get_device_id() does not fail here */
248 devid = get_device_id(dev);
249 ivrs_alias = amd_iommu_alias_table[devid];
250 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
252 if (ivrs_alias == pci_alias)
258 * The IVRS is fairly reliable in telling us about aliases, but it
259 * can't know about every screwy device. If we don't have an IVRS
260 * reported alias, use the PCI reported alias. In that case we may
261 * still need to initialize the rlookup and dev_table entries if the
262 * alias is to a non-existent device.
264 if (ivrs_alias == devid) {
265 if (!amd_iommu_rlookup_table[pci_alias]) {
266 amd_iommu_rlookup_table[pci_alias] =
267 amd_iommu_rlookup_table[devid];
268 memcpy(amd_iommu_dev_table[pci_alias].data,
269 amd_iommu_dev_table[devid].data,
270 sizeof(amd_iommu_dev_table[pci_alias].data));
276 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
277 "for device %s[%04x:%04x], kernel reported alias "
278 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
279 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
280 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
281 PCI_FUNC(pci_alias));
284 * If we don't have a PCI DMA alias and the IVRS alias is on the same
285 * bus, then the IVRS table may know about a quirk that we don't.
287 if (pci_alias == devid &&
288 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
289 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
290 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
291 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
298 static struct iommu_dev_data *find_dev_data(u16 devid)
300 struct iommu_dev_data *dev_data;
301 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
303 dev_data = search_dev_data(devid);
305 if (dev_data == NULL) {
306 dev_data = alloc_dev_data(devid);
310 if (translation_pre_enabled(iommu))
311 dev_data->defer_attach = true;
317 struct iommu_dev_data *get_dev_data(struct device *dev)
319 return dev->archdata.iommu;
321 EXPORT_SYMBOL(get_dev_data);
324 * Find or create an IOMMU group for a acpihid device.
326 static struct iommu_group *acpihid_device_group(struct device *dev)
328 struct acpihid_map_entry *p, *entry = NULL;
331 devid = get_acpihid_device_id(dev, &entry);
333 return ERR_PTR(devid);
335 list_for_each_entry(p, &acpihid_map, list) {
336 if ((devid == p->devid) && p->group)
337 entry->group = p->group;
341 entry->group = generic_device_group(dev);
343 iommu_group_ref_get(entry->group);
348 static bool pci_iommuv2_capable(struct pci_dev *pdev)
350 static const int caps[] = {
353 PCI_EXT_CAP_ID_PASID,
357 if (pci_ats_disabled())
360 for (i = 0; i < 3; ++i) {
361 pos = pci_find_ext_capability(pdev, caps[i]);
369 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
371 struct iommu_dev_data *dev_data;
373 dev_data = get_dev_data(&pdev->dev);
375 return dev_data->errata & (1 << erratum) ? true : false;
379 * This function checks if the driver got a valid device from the caller to
380 * avoid dereferencing invalid pointers.
382 static bool check_device(struct device *dev)
386 if (!dev || !dev->dma_mask)
389 devid = get_device_id(dev);
393 /* Out of our scope? */
394 if (devid > amd_iommu_last_bdf)
397 if (amd_iommu_rlookup_table[devid] == NULL)
403 static void init_iommu_group(struct device *dev)
405 struct iommu_group *group;
407 group = iommu_group_get_for_dev(dev);
411 iommu_group_put(group);
414 static int iommu_init_device(struct device *dev)
416 struct iommu_dev_data *dev_data;
417 struct amd_iommu *iommu;
420 if (dev->archdata.iommu)
423 devid = get_device_id(dev);
427 iommu = amd_iommu_rlookup_table[devid];
429 dev_data = find_dev_data(devid);
433 dev_data->alias = get_alias(dev);
435 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
436 struct amd_iommu *iommu;
438 iommu = amd_iommu_rlookup_table[dev_data->devid];
439 dev_data->iommu_v2 = iommu->is_iommu_v2;
442 dev->archdata.iommu = dev_data;
444 iommu_device_link(&iommu->iommu, dev);
449 static void iommu_ignore_device(struct device *dev)
454 devid = get_device_id(dev);
458 alias = get_alias(dev);
460 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
461 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
463 amd_iommu_rlookup_table[devid] = NULL;
464 amd_iommu_rlookup_table[alias] = NULL;
467 static void iommu_uninit_device(struct device *dev)
469 struct iommu_dev_data *dev_data;
470 struct amd_iommu *iommu;
473 devid = get_device_id(dev);
477 iommu = amd_iommu_rlookup_table[devid];
479 dev_data = search_dev_data(devid);
483 if (dev_data->domain)
486 iommu_device_unlink(&iommu->iommu, dev);
488 iommu_group_remove_device(dev);
494 * We keep dev_data around for unplugged devices and reuse it when the
495 * device is re-plugged - not doing so would introduce a ton of races.
499 /****************************************************************************
501 * Interrupt handling functions
503 ****************************************************************************/
505 static void dump_dte_entry(u16 devid)
509 for (i = 0; i < 4; ++i)
510 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
511 amd_iommu_dev_table[devid].data[i]);
514 static void dump_command(unsigned long phys_addr)
516 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
519 for (i = 0; i < 4; ++i)
520 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
523 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
524 u64 address, int flags)
526 struct iommu_dev_data *dev_data = NULL;
527 struct pci_dev *pdev;
529 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
532 dev_data = get_dev_data(&pdev->dev);
534 if (dev_data && __ratelimit(&dev_data->rs)) {
535 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
536 domain_id, address, flags);
537 } else if (printk_ratelimit()) {
538 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
539 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
540 domain_id, address, flags);
547 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
549 struct device *dev = iommu->iommu.dev;
550 int type, devid, domid, flags;
551 volatile u32 *event = __evt;
556 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
557 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
558 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
559 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
560 address = (u64)(((u64)event[3]) << 32) | event[2];
563 /* Did we hit the erratum? */
564 if (++count == LOOP_TIMEOUT) {
565 pr_err("AMD-Vi: No event written to event log\n");
572 if (type == EVENT_TYPE_IO_FAULT) {
573 amd_iommu_report_page_fault(devid, domid, address, flags);
576 dev_err(dev, "AMD-Vi: Event logged [");
580 case EVENT_TYPE_ILL_DEV:
581 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
582 "address=0x%016llx flags=0x%04x]\n",
583 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
585 dump_dte_entry(devid);
587 case EVENT_TYPE_DEV_TAB_ERR:
588 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
589 "address=0x%016llx flags=0x%04x]\n",
590 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
593 case EVENT_TYPE_PAGE_TAB_ERR:
594 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
595 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
596 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
597 domid, address, flags);
599 case EVENT_TYPE_ILL_CMD:
600 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
601 dump_command(address);
603 case EVENT_TYPE_CMD_HARD_ERR:
604 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx "
605 "flags=0x%04x]\n", address, flags);
607 case EVENT_TYPE_IOTLB_INV_TO:
608 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
609 "address=0x%016llx]\n",
610 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
613 case EVENT_TYPE_INV_DEV_REQ:
614 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
615 "address=0x%016llx flags=0x%04x]\n",
616 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
620 dev_err(dev, KERN_ERR "UNKNOWN event[0]=0x%08x event[1]=0x%08x "
621 "event[2]=0x%08x event[3]=0x%08x\n",
622 event[0], event[1], event[2], event[3]);
625 memset(__evt, 0, 4 * sizeof(u32));
628 static void iommu_poll_events(struct amd_iommu *iommu)
632 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
633 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
635 while (head != tail) {
636 iommu_print_event(iommu, iommu->evt_buf + head);
637 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
640 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
643 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
645 struct amd_iommu_fault fault;
647 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
648 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
652 fault.address = raw[1];
653 fault.pasid = PPR_PASID(raw[0]);
654 fault.device_id = PPR_DEVID(raw[0]);
655 fault.tag = PPR_TAG(raw[0]);
656 fault.flags = PPR_FLAGS(raw[0]);
658 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
661 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
665 if (iommu->ppr_log == NULL)
668 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
669 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
671 while (head != tail) {
676 raw = (u64 *)(iommu->ppr_log + head);
679 * Hardware bug: Interrupt may arrive before the entry is
680 * written to memory. If this happens we need to wait for the
683 for (i = 0; i < LOOP_TIMEOUT; ++i) {
684 if (PPR_REQ_TYPE(raw[0]) != 0)
689 /* Avoid memcpy function-call overhead */
694 * To detect the hardware bug we need to clear the entry
697 raw[0] = raw[1] = 0UL;
699 /* Update head pointer of hardware ring-buffer */
700 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
701 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
703 /* Handle PPR entry */
704 iommu_handle_ppr_entry(iommu, entry);
706 /* Refresh ring-buffer information */
707 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
708 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
712 #ifdef CONFIG_IRQ_REMAP
713 static int (*iommu_ga_log_notifier)(u32);
715 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
717 iommu_ga_log_notifier = notifier;
721 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
723 static void iommu_poll_ga_log(struct amd_iommu *iommu)
725 u32 head, tail, cnt = 0;
727 if (iommu->ga_log == NULL)
730 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
731 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
733 while (head != tail) {
737 raw = (u64 *)(iommu->ga_log + head);
740 /* Avoid memcpy function-call overhead */
743 /* Update head pointer of hardware ring-buffer */
744 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
745 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
747 /* Handle GA entry */
748 switch (GA_REQ_TYPE(log_entry)) {
750 if (!iommu_ga_log_notifier)
753 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
754 __func__, GA_DEVID(log_entry),
757 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
758 pr_err("AMD-Vi: GA log notifier failed.\n");
765 #endif /* CONFIG_IRQ_REMAP */
767 #define AMD_IOMMU_INT_MASK \
768 (MMIO_STATUS_EVT_INT_MASK | \
769 MMIO_STATUS_PPR_INT_MASK | \
770 MMIO_STATUS_GALOG_INT_MASK)
772 irqreturn_t amd_iommu_int_thread(int irq, void *data)
774 struct amd_iommu *iommu = (struct amd_iommu *) data;
775 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
777 while (status & AMD_IOMMU_INT_MASK) {
778 /* Enable EVT and PPR and GA interrupts again */
779 writel(AMD_IOMMU_INT_MASK,
780 iommu->mmio_base + MMIO_STATUS_OFFSET);
782 if (status & MMIO_STATUS_EVT_INT_MASK) {
783 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
784 iommu_poll_events(iommu);
787 if (status & MMIO_STATUS_PPR_INT_MASK) {
788 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
789 iommu_poll_ppr_log(iommu);
792 #ifdef CONFIG_IRQ_REMAP
793 if (status & MMIO_STATUS_GALOG_INT_MASK) {
794 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
795 iommu_poll_ga_log(iommu);
800 * Hardware bug: ERBT1312
801 * When re-enabling interrupt (by writing 1
802 * to clear the bit), the hardware might also try to set
803 * the interrupt bit in the event status register.
804 * In this scenario, the bit will be set, and disable
805 * subsequent interrupts.
807 * Workaround: The IOMMU driver should read back the
808 * status register and check if the interrupt bits are cleared.
809 * If not, driver will need to go through the interrupt handler
810 * again and re-clear the bits
812 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
817 irqreturn_t amd_iommu_int_handler(int irq, void *data)
819 return IRQ_WAKE_THREAD;
822 /****************************************************************************
824 * IOMMU command queuing functions
826 ****************************************************************************/
828 static int wait_on_sem(volatile u64 *sem)
832 while (*sem == 0 && i < LOOP_TIMEOUT) {
837 if (i == LOOP_TIMEOUT) {
838 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
845 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
846 struct iommu_cmd *cmd)
850 target = iommu->cmd_buf + iommu->cmd_buf_tail;
852 iommu->cmd_buf_tail += sizeof(*cmd);
853 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
855 /* Copy command to buffer */
856 memcpy(target, cmd, sizeof(*cmd));
858 /* Tell the IOMMU about it */
859 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
862 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
864 u64 paddr = iommu_virt_to_phys((void *)address);
866 WARN_ON(address & 0x7ULL);
868 memset(cmd, 0, sizeof(*cmd));
869 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
870 cmd->data[1] = upper_32_bits(paddr);
872 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
875 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
877 memset(cmd, 0, sizeof(*cmd));
878 cmd->data[0] = devid;
879 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
882 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
883 size_t size, u16 domid, int pde)
888 pages = iommu_num_pages(address, size, PAGE_SIZE);
893 * If we have to flush more than one page, flush all
894 * TLB entries for this domain
896 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
900 address &= PAGE_MASK;
902 memset(cmd, 0, sizeof(*cmd));
903 cmd->data[1] |= domid;
904 cmd->data[2] = lower_32_bits(address);
905 cmd->data[3] = upper_32_bits(address);
906 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
907 if (s) /* size bit - we flush more than one 4kb page */
908 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
909 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
910 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
913 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
914 u64 address, size_t size)
919 pages = iommu_num_pages(address, size, PAGE_SIZE);
924 * If we have to flush more than one page, flush all
925 * TLB entries for this domain
927 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
931 address &= PAGE_MASK;
933 memset(cmd, 0, sizeof(*cmd));
934 cmd->data[0] = devid;
935 cmd->data[0] |= (qdep & 0xff) << 24;
936 cmd->data[1] = devid;
937 cmd->data[2] = lower_32_bits(address);
938 cmd->data[3] = upper_32_bits(address);
939 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
941 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
944 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
945 u64 address, bool size)
947 memset(cmd, 0, sizeof(*cmd));
949 address &= ~(0xfffULL);
951 cmd->data[0] = pasid;
952 cmd->data[1] = domid;
953 cmd->data[2] = lower_32_bits(address);
954 cmd->data[3] = upper_32_bits(address);
955 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
956 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
958 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
959 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
962 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
963 int qdep, u64 address, bool size)
965 memset(cmd, 0, sizeof(*cmd));
967 address &= ~(0xfffULL);
969 cmd->data[0] = devid;
970 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
971 cmd->data[0] |= (qdep & 0xff) << 24;
972 cmd->data[1] = devid;
973 cmd->data[1] |= (pasid & 0xff) << 16;
974 cmd->data[2] = lower_32_bits(address);
975 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
976 cmd->data[3] = upper_32_bits(address);
978 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
979 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
982 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
983 int status, int tag, bool gn)
985 memset(cmd, 0, sizeof(*cmd));
987 cmd->data[0] = devid;
989 cmd->data[1] = pasid;
990 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
992 cmd->data[3] = tag & 0x1ff;
993 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
995 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
998 static void build_inv_all(struct iommu_cmd *cmd)
1000 memset(cmd, 0, sizeof(*cmd));
1001 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1004 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1006 memset(cmd, 0, sizeof(*cmd));
1007 cmd->data[0] = devid;
1008 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1012 * Writes the command to the IOMMUs command buffer and informs the
1013 * hardware about the new command.
1015 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1016 struct iommu_cmd *cmd,
1019 unsigned int count = 0;
1020 u32 left, next_tail;
1022 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1024 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1027 /* Skip udelay() the first time around */
1029 if (count == LOOP_TIMEOUT) {
1030 pr_err("AMD-Vi: Command buffer timeout\n");
1037 /* Update head and recheck remaining space */
1038 iommu->cmd_buf_head = readl(iommu->mmio_base +
1039 MMIO_CMD_HEAD_OFFSET);
1044 copy_cmd_to_buffer(iommu, cmd);
1046 /* Do we need to make sure all commands are processed? */
1047 iommu->need_sync = sync;
1052 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1053 struct iommu_cmd *cmd,
1056 unsigned long flags;
1059 raw_spin_lock_irqsave(&iommu->lock, flags);
1060 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1061 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1066 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1068 return iommu_queue_command_sync(iommu, cmd, true);
1072 * This function queues a completion wait command into the command
1073 * buffer of an IOMMU
1075 static int iommu_completion_wait(struct amd_iommu *iommu)
1077 struct iommu_cmd cmd;
1078 unsigned long flags;
1081 if (!iommu->need_sync)
1085 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1087 raw_spin_lock_irqsave(&iommu->lock, flags);
1091 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1095 ret = wait_on_sem(&iommu->cmd_sem);
1098 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1103 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1105 struct iommu_cmd cmd;
1107 build_inv_dte(&cmd, devid);
1109 return iommu_queue_command(iommu, &cmd);
1112 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1116 for (devid = 0; devid <= 0xffff; ++devid)
1117 iommu_flush_dte(iommu, devid);
1119 iommu_completion_wait(iommu);
1123 * This function uses heavy locking and may disable irqs for some time. But
1124 * this is no issue because it is only called during resume.
1126 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1130 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1131 struct iommu_cmd cmd;
1132 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1134 iommu_queue_command(iommu, &cmd);
1137 iommu_completion_wait(iommu);
1140 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1142 struct iommu_cmd cmd;
1144 build_inv_all(&cmd);
1146 iommu_queue_command(iommu, &cmd);
1147 iommu_completion_wait(iommu);
1150 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1152 struct iommu_cmd cmd;
1154 build_inv_irt(&cmd, devid);
1156 iommu_queue_command(iommu, &cmd);
1159 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1163 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1164 iommu_flush_irt(iommu, devid);
1166 iommu_completion_wait(iommu);
1169 void iommu_flush_all_caches(struct amd_iommu *iommu)
1171 if (iommu_feature(iommu, FEATURE_IA)) {
1172 amd_iommu_flush_all(iommu);
1174 amd_iommu_flush_dte_all(iommu);
1175 amd_iommu_flush_irt_all(iommu);
1176 amd_iommu_flush_tlb_all(iommu);
1181 * Command send function for flushing on-device TLB
1183 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1184 u64 address, size_t size)
1186 struct amd_iommu *iommu;
1187 struct iommu_cmd cmd;
1190 qdep = dev_data->ats.qdep;
1191 iommu = amd_iommu_rlookup_table[dev_data->devid];
1193 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1195 return iommu_queue_command(iommu, &cmd);
1199 * Command send function for invalidating a device table entry
1201 static int device_flush_dte(struct iommu_dev_data *dev_data)
1203 struct amd_iommu *iommu;
1207 iommu = amd_iommu_rlookup_table[dev_data->devid];
1208 alias = dev_data->alias;
1210 ret = iommu_flush_dte(iommu, dev_data->devid);
1211 if (!ret && alias != dev_data->devid)
1212 ret = iommu_flush_dte(iommu, alias);
1216 if (dev_data->ats.enabled)
1217 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1223 * TLB invalidation function which is called from the mapping functions.
1224 * It invalidates a single PTE if the range to flush is within a single
1225 * page. Otherwise it flushes the whole TLB of the IOMMU.
1227 static void __domain_flush_pages(struct protection_domain *domain,
1228 u64 address, size_t size, int pde)
1230 struct iommu_dev_data *dev_data;
1231 struct iommu_cmd cmd;
1234 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1236 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1237 if (!domain->dev_iommu[i])
1241 * Devices of this domain are behind this IOMMU
1242 * We need a TLB flush
1244 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1247 list_for_each_entry(dev_data, &domain->dev_list, list) {
1249 if (!dev_data->ats.enabled)
1252 ret |= device_flush_iotlb(dev_data, address, size);
1258 static void domain_flush_pages(struct protection_domain *domain,
1259 u64 address, size_t size)
1261 __domain_flush_pages(domain, address, size, 0);
1264 /* Flush the whole IO/TLB for a given protection domain */
1265 static void domain_flush_tlb(struct protection_domain *domain)
1267 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1270 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1271 static void domain_flush_tlb_pde(struct protection_domain *domain)
1273 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1276 static void domain_flush_complete(struct protection_domain *domain)
1280 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1281 if (domain && !domain->dev_iommu[i])
1285 * Devices of this domain are behind this IOMMU
1286 * We need to wait for completion of all commands.
1288 iommu_completion_wait(amd_iommus[i]);
1294 * This function flushes the DTEs for all devices in domain
1296 static void domain_flush_devices(struct protection_domain *domain)
1298 struct iommu_dev_data *dev_data;
1300 list_for_each_entry(dev_data, &domain->dev_list, list)
1301 device_flush_dte(dev_data);
1304 /****************************************************************************
1306 * The functions below are used the create the page table mappings for
1307 * unity mapped regions.
1309 ****************************************************************************/
1312 * This function is used to add another level to an IO page table. Adding
1313 * another level increases the size of the address space by 9 bits to a size up
1316 static bool increase_address_space(struct protection_domain *domain,
1321 if (domain->mode == PAGE_MODE_6_LEVEL)
1322 /* address space already 64 bit large */
1325 pte = (void *)get_zeroed_page(gfp);
1329 *pte = PM_LEVEL_PDE(domain->mode,
1330 iommu_virt_to_phys(domain->pt_root));
1331 domain->pt_root = pte;
1333 domain->updated = true;
1338 static u64 *alloc_pte(struct protection_domain *domain,
1339 unsigned long address,
1340 unsigned long page_size,
1347 BUG_ON(!is_power_of_2(page_size));
1349 while (address > PM_LEVEL_SIZE(domain->mode))
1350 increase_address_space(domain, gfp);
1352 level = domain->mode - 1;
1353 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1354 address = PAGE_SIZE_ALIGN(address, page_size);
1355 end_lvl = PAGE_SIZE_LEVEL(page_size);
1357 while (level > end_lvl) {
1362 if (!IOMMU_PTE_PRESENT(__pte)) {
1363 page = (u64 *)get_zeroed_page(gfp);
1367 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1369 /* pte could have been changed somewhere. */
1370 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1371 free_page((unsigned long)page);
1376 /* No level skipping support yet */
1377 if (PM_PTE_LEVEL(*pte) != level)
1382 pte = IOMMU_PTE_PAGE(*pte);
1384 if (pte_page && level == end_lvl)
1387 pte = &pte[PM_LEVEL_INDEX(level, address)];
1394 * This function checks if there is a PTE for a given dma address. If
1395 * there is one, it returns the pointer to it.
1397 static u64 *fetch_pte(struct protection_domain *domain,
1398 unsigned long address,
1399 unsigned long *page_size)
1404 if (address > PM_LEVEL_SIZE(domain->mode))
1407 level = domain->mode - 1;
1408 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1409 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1414 if (!IOMMU_PTE_PRESENT(*pte))
1418 if (PM_PTE_LEVEL(*pte) == 7 ||
1419 PM_PTE_LEVEL(*pte) == 0)
1422 /* No level skipping support yet */
1423 if (PM_PTE_LEVEL(*pte) != level)
1428 /* Walk to the next level */
1429 pte = IOMMU_PTE_PAGE(*pte);
1430 pte = &pte[PM_LEVEL_INDEX(level, address)];
1431 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1434 if (PM_PTE_LEVEL(*pte) == 0x07) {
1435 unsigned long pte_mask;
1438 * If we have a series of large PTEs, make
1439 * sure to return a pointer to the first one.
1441 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1442 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1443 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1450 * Generic mapping functions. It maps a physical address into a DMA
1451 * address space. It allocates the page table pages if necessary.
1452 * In the future it can be extended to a generic mapping function
1453 * supporting all features of AMD IOMMU page tables like level skipping
1454 * and full 64 bit address spaces.
1456 static int iommu_map_page(struct protection_domain *dom,
1457 unsigned long bus_addr,
1458 unsigned long phys_addr,
1459 unsigned long page_size,
1466 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1467 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1469 if (!(prot & IOMMU_PROT_MASK))
1472 count = PAGE_SIZE_PTE_COUNT(page_size);
1473 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1478 for (i = 0; i < count; ++i)
1479 if (IOMMU_PTE_PRESENT(pte[i]))
1483 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1484 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1486 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1488 if (prot & IOMMU_PROT_IR)
1489 __pte |= IOMMU_PTE_IR;
1490 if (prot & IOMMU_PROT_IW)
1491 __pte |= IOMMU_PTE_IW;
1493 for (i = 0; i < count; ++i)
1501 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1502 unsigned long bus_addr,
1503 unsigned long page_size)
1505 unsigned long long unmapped;
1506 unsigned long unmap_size;
1509 BUG_ON(!is_power_of_2(page_size));
1513 while (unmapped < page_size) {
1515 pte = fetch_pte(dom, bus_addr, &unmap_size);
1520 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1521 for (i = 0; i < count; i++)
1525 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1526 unmapped += unmap_size;
1529 BUG_ON(unmapped && !is_power_of_2(unmapped));
1534 /****************************************************************************
1536 * The next functions belong to the address allocator for the dma_ops
1537 * interface functions.
1539 ****************************************************************************/
1542 static unsigned long dma_ops_alloc_iova(struct device *dev,
1543 struct dma_ops_domain *dma_dom,
1544 unsigned int pages, u64 dma_mask)
1546 unsigned long pfn = 0;
1548 pages = __roundup_pow_of_two(pages);
1550 if (dma_mask > DMA_BIT_MASK(32))
1551 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1552 IOVA_PFN(DMA_BIT_MASK(32)), false);
1555 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1556 IOVA_PFN(dma_mask), true);
1558 return (pfn << PAGE_SHIFT);
1561 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1562 unsigned long address,
1565 pages = __roundup_pow_of_two(pages);
1566 address >>= PAGE_SHIFT;
1568 free_iova_fast(&dma_dom->iovad, address, pages);
1571 /****************************************************************************
1573 * The next functions belong to the domain allocation. A domain is
1574 * allocated for every IOMMU as the default domain. If device isolation
1575 * is enabled, every device get its own domain. The most important thing
1576 * about domains is the page table mapping the DMA address space they
1579 ****************************************************************************/
1582 * This function adds a protection domain to the global protection domain list
1584 static void add_domain_to_list(struct protection_domain *domain)
1586 unsigned long flags;
1588 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1589 list_add(&domain->list, &amd_iommu_pd_list);
1590 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1594 * This function removes a protection domain to the global
1595 * protection domain list
1597 static void del_domain_from_list(struct protection_domain *domain)
1599 unsigned long flags;
1601 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1602 list_del(&domain->list);
1603 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1606 static u16 domain_id_alloc(void)
1610 spin_lock(&pd_bitmap_lock);
1611 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1613 if (id > 0 && id < MAX_DOMAIN_ID)
1614 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1617 spin_unlock(&pd_bitmap_lock);
1622 static void domain_id_free(int id)
1624 spin_lock(&pd_bitmap_lock);
1625 if (id > 0 && id < MAX_DOMAIN_ID)
1626 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1627 spin_unlock(&pd_bitmap_lock);
1630 #define DEFINE_FREE_PT_FN(LVL, FN) \
1631 static void free_pt_##LVL (unsigned long __pt) \
1639 for (i = 0; i < 512; ++i) { \
1640 /* PTE present? */ \
1641 if (!IOMMU_PTE_PRESENT(pt[i])) \
1645 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1646 PM_PTE_LEVEL(pt[i]) == 7) \
1649 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1652 free_page((unsigned long)pt); \
1655 DEFINE_FREE_PT_FN(l2, free_page)
1656 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1657 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1658 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1659 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1661 static void free_pagetable(struct protection_domain *domain)
1663 unsigned long root = (unsigned long)domain->pt_root;
1665 switch (domain->mode) {
1666 case PAGE_MODE_NONE:
1668 case PAGE_MODE_1_LEVEL:
1671 case PAGE_MODE_2_LEVEL:
1674 case PAGE_MODE_3_LEVEL:
1677 case PAGE_MODE_4_LEVEL:
1680 case PAGE_MODE_5_LEVEL:
1683 case PAGE_MODE_6_LEVEL:
1691 static void free_gcr3_tbl_level1(u64 *tbl)
1696 for (i = 0; i < 512; ++i) {
1697 if (!(tbl[i] & GCR3_VALID))
1700 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1702 free_page((unsigned long)ptr);
1706 static void free_gcr3_tbl_level2(u64 *tbl)
1711 for (i = 0; i < 512; ++i) {
1712 if (!(tbl[i] & GCR3_VALID))
1715 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1717 free_gcr3_tbl_level1(ptr);
1721 static void free_gcr3_table(struct protection_domain *domain)
1723 if (domain->glx == 2)
1724 free_gcr3_tbl_level2(domain->gcr3_tbl);
1725 else if (domain->glx == 1)
1726 free_gcr3_tbl_level1(domain->gcr3_tbl);
1728 BUG_ON(domain->glx != 0);
1730 free_page((unsigned long)domain->gcr3_tbl);
1733 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1735 domain_flush_tlb(&dom->domain);
1736 domain_flush_complete(&dom->domain);
1739 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1741 struct dma_ops_domain *dom;
1743 dom = container_of(iovad, struct dma_ops_domain, iovad);
1745 dma_ops_domain_flush_tlb(dom);
1749 * Free a domain, only used if something went wrong in the
1750 * allocation path and we need to free an already allocated page table
1752 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1757 del_domain_from_list(&dom->domain);
1759 put_iova_domain(&dom->iovad);
1761 free_pagetable(&dom->domain);
1764 domain_id_free(dom->domain.id);
1770 * Allocates a new protection domain usable for the dma_ops functions.
1771 * It also initializes the page table and the address allocator data
1772 * structures required for the dma_ops interface
1774 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1776 struct dma_ops_domain *dma_dom;
1778 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1782 if (protection_domain_init(&dma_dom->domain))
1785 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1786 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1787 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1788 if (!dma_dom->domain.pt_root)
1791 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1793 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1796 /* Initialize reserved ranges */
1797 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1799 add_domain_to_list(&dma_dom->domain);
1804 dma_ops_domain_free(dma_dom);
1810 * little helper function to check whether a given protection domain is a
1813 static bool dma_ops_domain(struct protection_domain *domain)
1815 return domain->flags & PD_DMA_OPS_MASK;
1818 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1824 if (domain->mode != PAGE_MODE_NONE)
1825 pte_root = iommu_virt_to_phys(domain->pt_root);
1827 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1828 << DEV_ENTRY_MODE_SHIFT;
1829 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1831 flags = amd_iommu_dev_table[devid].data[1];
1834 flags |= DTE_FLAG_IOTLB;
1837 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1839 if (iommu_feature(iommu, FEATURE_EPHSUP))
1840 pte_root |= 1ULL << DEV_ENTRY_PPR;
1843 if (domain->flags & PD_IOMMUV2_MASK) {
1844 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1845 u64 glx = domain->glx;
1848 pte_root |= DTE_FLAG_GV;
1849 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1851 /* First mask out possible old values for GCR3 table */
1852 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1855 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1858 /* Encode GCR3 table into DTE */
1859 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1862 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1865 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1869 flags &= ~DEV_DOMID_MASK;
1870 flags |= domain->id;
1872 amd_iommu_dev_table[devid].data[1] = flags;
1873 amd_iommu_dev_table[devid].data[0] = pte_root;
1876 static void clear_dte_entry(u16 devid)
1878 /* remove entry from the device table seen by the hardware */
1879 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1880 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1882 amd_iommu_apply_erratum_63(devid);
1885 static void do_attach(struct iommu_dev_data *dev_data,
1886 struct protection_domain *domain)
1888 struct amd_iommu *iommu;
1892 iommu = amd_iommu_rlookup_table[dev_data->devid];
1893 alias = dev_data->alias;
1894 ats = dev_data->ats.enabled;
1896 /* Update data structures */
1897 dev_data->domain = domain;
1898 list_add(&dev_data->list, &domain->dev_list);
1900 /* Do reference counting */
1901 domain->dev_iommu[iommu->index] += 1;
1902 domain->dev_cnt += 1;
1904 /* Update device table */
1905 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1906 if (alias != dev_data->devid)
1907 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1909 device_flush_dte(dev_data);
1912 static void do_detach(struct iommu_dev_data *dev_data)
1914 struct amd_iommu *iommu;
1918 * First check if the device is still attached. It might already
1919 * be detached from its domain because the generic
1920 * iommu_detach_group code detached it and we try again here in
1921 * our alias handling.
1923 if (!dev_data->domain)
1926 iommu = amd_iommu_rlookup_table[dev_data->devid];
1927 alias = dev_data->alias;
1929 /* decrease reference counters */
1930 dev_data->domain->dev_iommu[iommu->index] -= 1;
1931 dev_data->domain->dev_cnt -= 1;
1933 /* Update data structures */
1934 dev_data->domain = NULL;
1935 list_del(&dev_data->list);
1936 clear_dte_entry(dev_data->devid);
1937 if (alias != dev_data->devid)
1938 clear_dte_entry(alias);
1940 /* Flush the DTE entry */
1941 device_flush_dte(dev_data);
1945 * If a device is not yet associated with a domain, this function does
1946 * assigns it visible for the hardware
1948 static int __attach_device(struct iommu_dev_data *dev_data,
1949 struct protection_domain *domain)
1954 * Must be called with IRQs disabled. Warn here to detect early
1957 WARN_ON(!irqs_disabled());
1960 spin_lock(&domain->lock);
1963 if (dev_data->domain != NULL)
1966 /* Attach alias group root */
1967 do_attach(dev_data, domain);
1974 spin_unlock(&domain->lock);
1980 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1982 pci_disable_ats(pdev);
1983 pci_disable_pri(pdev);
1984 pci_disable_pasid(pdev);
1987 /* FIXME: Change generic reset-function to do the same */
1988 static int pri_reset_while_enabled(struct pci_dev *pdev)
1993 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1997 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1998 control |= PCI_PRI_CTRL_RESET;
1999 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2004 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2009 /* FIXME: Hardcode number of outstanding requests for now */
2011 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2013 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2015 /* Only allow access to user-accessible pages */
2016 ret = pci_enable_pasid(pdev, 0);
2020 /* First reset the PRI state of the device */
2021 ret = pci_reset_pri(pdev);
2026 ret = pci_enable_pri(pdev, reqs);
2031 ret = pri_reset_while_enabled(pdev);
2036 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2043 pci_disable_pri(pdev);
2044 pci_disable_pasid(pdev);
2049 /* FIXME: Move this to PCI code */
2050 #define PCI_PRI_TLP_OFF (1 << 15)
2052 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2057 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2061 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2063 return (status & PCI_PRI_TLP_OFF) ? true : false;
2067 * If a device is not yet associated with a domain, this function
2068 * assigns it visible for the hardware
2070 static int attach_device(struct device *dev,
2071 struct protection_domain *domain)
2073 struct pci_dev *pdev;
2074 struct iommu_dev_data *dev_data;
2075 unsigned long flags;
2078 dev_data = get_dev_data(dev);
2080 if (!dev_is_pci(dev))
2081 goto skip_ats_check;
2083 pdev = to_pci_dev(dev);
2084 if (domain->flags & PD_IOMMUV2_MASK) {
2085 if (!dev_data->passthrough)
2088 if (dev_data->iommu_v2) {
2089 if (pdev_iommuv2_enable(pdev) != 0)
2092 dev_data->ats.enabled = true;
2093 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2094 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2096 } else if (amd_iommu_iotlb_sup &&
2097 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2098 dev_data->ats.enabled = true;
2099 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2103 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2104 ret = __attach_device(dev_data, domain);
2105 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2108 * We might boot into a crash-kernel here. The crashed kernel
2109 * left the caches in the IOMMU dirty. So we have to flush
2110 * here to evict all dirty stuff.
2112 domain_flush_tlb_pde(domain);
2118 * Removes a device from a protection domain (unlocked)
2120 static void __detach_device(struct iommu_dev_data *dev_data)
2122 struct protection_domain *domain;
2125 * Must be called with IRQs disabled. Warn here to detect early
2128 WARN_ON(!irqs_disabled());
2130 if (WARN_ON(!dev_data->domain))
2133 domain = dev_data->domain;
2135 spin_lock(&domain->lock);
2137 do_detach(dev_data);
2139 spin_unlock(&domain->lock);
2143 * Removes a device from a protection domain (with devtable_lock held)
2145 static void detach_device(struct device *dev)
2147 struct protection_domain *domain;
2148 struct iommu_dev_data *dev_data;
2149 unsigned long flags;
2151 dev_data = get_dev_data(dev);
2152 domain = dev_data->domain;
2154 /* lock device table */
2155 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2156 __detach_device(dev_data);
2157 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2159 if (!dev_is_pci(dev))
2162 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2163 pdev_iommuv2_disable(to_pci_dev(dev));
2164 else if (dev_data->ats.enabled)
2165 pci_disable_ats(to_pci_dev(dev));
2167 dev_data->ats.enabled = false;
2170 static int amd_iommu_add_device(struct device *dev)
2172 struct iommu_dev_data *dev_data;
2173 struct iommu_domain *domain;
2174 struct amd_iommu *iommu;
2177 if (!check_device(dev) || get_dev_data(dev))
2180 devid = get_device_id(dev);
2184 iommu = amd_iommu_rlookup_table[devid];
2186 ret = iommu_init_device(dev);
2188 if (ret != -ENOTSUPP)
2189 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2192 iommu_ignore_device(dev);
2193 dev->dma_ops = &dma_direct_ops;
2196 init_iommu_group(dev);
2198 dev_data = get_dev_data(dev);
2202 if (iommu_pass_through || dev_data->iommu_v2)
2203 iommu_request_dm_for_dev(dev);
2205 /* Domains are initialized for this device - have a look what we ended up with */
2206 domain = iommu_get_domain_for_dev(dev);
2207 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2208 dev_data->passthrough = true;
2210 dev->dma_ops = &amd_iommu_dma_ops;
2213 iommu_completion_wait(iommu);
2218 static void amd_iommu_remove_device(struct device *dev)
2220 struct amd_iommu *iommu;
2223 if (!check_device(dev))
2226 devid = get_device_id(dev);
2230 iommu = amd_iommu_rlookup_table[devid];
2232 iommu_uninit_device(dev);
2233 iommu_completion_wait(iommu);
2236 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2238 if (dev_is_pci(dev))
2239 return pci_device_group(dev);
2241 return acpihid_device_group(dev);
2244 /*****************************************************************************
2246 * The next functions belong to the dma_ops mapping/unmapping code.
2248 *****************************************************************************/
2251 * In the dma_ops path we only have the struct device. This function
2252 * finds the corresponding IOMMU, the protection domain and the
2253 * requestor id for a given device.
2254 * If the device is not yet associated with a domain this is also done
2257 static struct protection_domain *get_domain(struct device *dev)
2259 struct protection_domain *domain;
2260 struct iommu_domain *io_domain;
2262 if (!check_device(dev))
2263 return ERR_PTR(-EINVAL);
2265 domain = get_dev_data(dev)->domain;
2266 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2267 get_dev_data(dev)->defer_attach = false;
2268 io_domain = iommu_get_domain_for_dev(dev);
2269 domain = to_pdomain(io_domain);
2270 attach_device(dev, domain);
2273 return ERR_PTR(-EBUSY);
2275 if (!dma_ops_domain(domain))
2276 return ERR_PTR(-EBUSY);
2281 static void update_device_table(struct protection_domain *domain)
2283 struct iommu_dev_data *dev_data;
2285 list_for_each_entry(dev_data, &domain->dev_list, list) {
2286 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2287 dev_data->iommu_v2);
2289 if (dev_data->devid == dev_data->alias)
2292 /* There is an alias, update device table entry for it */
2293 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2294 dev_data->iommu_v2);
2298 static void update_domain(struct protection_domain *domain)
2300 if (!domain->updated)
2303 update_device_table(domain);
2305 domain_flush_devices(domain);
2306 domain_flush_tlb_pde(domain);
2308 domain->updated = false;
2311 static int dir2prot(enum dma_data_direction direction)
2313 if (direction == DMA_TO_DEVICE)
2314 return IOMMU_PROT_IR;
2315 else if (direction == DMA_FROM_DEVICE)
2316 return IOMMU_PROT_IW;
2317 else if (direction == DMA_BIDIRECTIONAL)
2318 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2324 * This function contains common code for mapping of a physically
2325 * contiguous memory region into DMA address space. It is used by all
2326 * mapping functions provided with this IOMMU driver.
2327 * Must be called with the domain lock held.
2329 static dma_addr_t __map_single(struct device *dev,
2330 struct dma_ops_domain *dma_dom,
2333 enum dma_data_direction direction,
2336 dma_addr_t offset = paddr & ~PAGE_MASK;
2337 dma_addr_t address, start, ret;
2342 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2345 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2346 if (address == AMD_IOMMU_MAPPING_ERROR)
2349 prot = dir2prot(direction);
2352 for (i = 0; i < pages; ++i) {
2353 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2354 PAGE_SIZE, prot, GFP_ATOMIC);
2363 if (unlikely(amd_iommu_np_cache)) {
2364 domain_flush_pages(&dma_dom->domain, address, size);
2365 domain_flush_complete(&dma_dom->domain);
2373 for (--i; i >= 0; --i) {
2375 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2378 domain_flush_tlb(&dma_dom->domain);
2379 domain_flush_complete(&dma_dom->domain);
2381 dma_ops_free_iova(dma_dom, address, pages);
2383 return AMD_IOMMU_MAPPING_ERROR;
2387 * Does the reverse of the __map_single function. Must be called with
2388 * the domain lock held too
2390 static void __unmap_single(struct dma_ops_domain *dma_dom,
2391 dma_addr_t dma_addr,
2395 dma_addr_t i, start;
2398 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2399 dma_addr &= PAGE_MASK;
2402 for (i = 0; i < pages; ++i) {
2403 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2407 if (amd_iommu_unmap_flush) {
2408 dma_ops_free_iova(dma_dom, dma_addr, pages);
2409 domain_flush_tlb(&dma_dom->domain);
2410 domain_flush_complete(&dma_dom->domain);
2412 pages = __roundup_pow_of_two(pages);
2413 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2418 * The exported map_single function for dma_ops.
2420 static dma_addr_t map_page(struct device *dev, struct page *page,
2421 unsigned long offset, size_t size,
2422 enum dma_data_direction dir,
2423 unsigned long attrs)
2425 phys_addr_t paddr = page_to_phys(page) + offset;
2426 struct protection_domain *domain;
2427 struct dma_ops_domain *dma_dom;
2430 domain = get_domain(dev);
2431 if (PTR_ERR(domain) == -EINVAL)
2432 return (dma_addr_t)paddr;
2433 else if (IS_ERR(domain))
2434 return AMD_IOMMU_MAPPING_ERROR;
2436 dma_mask = *dev->dma_mask;
2437 dma_dom = to_dma_ops_domain(domain);
2439 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2443 * The exported unmap_single function for dma_ops.
2445 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2446 enum dma_data_direction dir, unsigned long attrs)
2448 struct protection_domain *domain;
2449 struct dma_ops_domain *dma_dom;
2451 domain = get_domain(dev);
2455 dma_dom = to_dma_ops_domain(domain);
2457 __unmap_single(dma_dom, dma_addr, size, dir);
2460 static int sg_num_pages(struct device *dev,
2461 struct scatterlist *sglist,
2464 unsigned long mask, boundary_size;
2465 struct scatterlist *s;
2468 mask = dma_get_seg_boundary(dev);
2469 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2470 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2472 for_each_sg(sglist, s, nelems, i) {
2475 s->dma_address = npages << PAGE_SHIFT;
2476 p = npages % boundary_size;
2477 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2478 if (p + n > boundary_size)
2479 npages += boundary_size - p;
2487 * The exported map_sg function for dma_ops (handles scatter-gather
2490 static int map_sg(struct device *dev, struct scatterlist *sglist,
2491 int nelems, enum dma_data_direction direction,
2492 unsigned long attrs)
2494 int mapped_pages = 0, npages = 0, prot = 0, i;
2495 struct protection_domain *domain;
2496 struct dma_ops_domain *dma_dom;
2497 struct scatterlist *s;
2498 unsigned long address;
2501 domain = get_domain(dev);
2505 dma_dom = to_dma_ops_domain(domain);
2506 dma_mask = *dev->dma_mask;
2508 npages = sg_num_pages(dev, sglist, nelems);
2510 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2511 if (address == AMD_IOMMU_MAPPING_ERROR)
2514 prot = dir2prot(direction);
2516 /* Map all sg entries */
2517 for_each_sg(sglist, s, nelems, i) {
2518 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2520 for (j = 0; j < pages; ++j) {
2521 unsigned long bus_addr, phys_addr;
2524 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2525 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2526 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2534 /* Everything is mapped - write the right values into s->dma_address */
2535 for_each_sg(sglist, s, nelems, i) {
2536 s->dma_address += address + s->offset;
2537 s->dma_length = s->length;
2543 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2544 dev_name(dev), npages);
2546 for_each_sg(sglist, s, nelems, i) {
2547 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2549 for (j = 0; j < pages; ++j) {
2550 unsigned long bus_addr;
2552 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2553 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2561 free_iova_fast(&dma_dom->iovad, address, npages);
2568 * The exported map_sg function for dma_ops (handles scatter-gather
2571 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2572 int nelems, enum dma_data_direction dir,
2573 unsigned long attrs)
2575 struct protection_domain *domain;
2576 struct dma_ops_domain *dma_dom;
2577 unsigned long startaddr;
2580 domain = get_domain(dev);
2584 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2585 dma_dom = to_dma_ops_domain(domain);
2586 npages = sg_num_pages(dev, sglist, nelems);
2588 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2592 * The exported alloc_coherent function for dma_ops.
2594 static void *alloc_coherent(struct device *dev, size_t size,
2595 dma_addr_t *dma_addr, gfp_t flag,
2596 unsigned long attrs)
2598 u64 dma_mask = dev->coherent_dma_mask;
2599 struct protection_domain *domain = get_domain(dev);
2600 bool is_direct = false;
2603 if (IS_ERR(domain)) {
2604 if (PTR_ERR(domain) != -EINVAL)
2609 virt_addr = dma_direct_alloc(dev, size, dma_addr, flag, attrs);
2610 if (!virt_addr || is_direct)
2614 dma_mask = *dev->dma_mask;
2616 *dma_addr = __map_single(dev, to_dma_ops_domain(domain),
2617 virt_to_phys(virt_addr), PAGE_ALIGN(size),
2618 DMA_BIDIRECTIONAL, dma_mask);
2619 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2624 dma_direct_free(dev, size, virt_addr, *dma_addr, attrs);
2629 * The exported free_coherent function for dma_ops.
2631 static void free_coherent(struct device *dev, size_t size,
2632 void *virt_addr, dma_addr_t dma_addr,
2633 unsigned long attrs)
2635 struct protection_domain *domain = get_domain(dev);
2637 size = PAGE_ALIGN(size);
2639 if (!IS_ERR(domain)) {
2640 struct dma_ops_domain *dma_dom = to_dma_ops_domain(domain);
2642 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2645 dma_direct_free(dev, size, virt_addr, dma_addr, attrs);
2649 * This function is called by the DMA layer to find out if we can handle a
2650 * particular device. It is part of the dma_ops.
2652 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2654 if (!dma_direct_supported(dev, mask))
2656 return check_device(dev);
2659 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2661 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2664 static const struct dma_map_ops amd_iommu_dma_ops = {
2665 .alloc = alloc_coherent,
2666 .free = free_coherent,
2667 .map_page = map_page,
2668 .unmap_page = unmap_page,
2670 .unmap_sg = unmap_sg,
2671 .dma_supported = amd_iommu_dma_supported,
2672 .mapping_error = amd_iommu_mapping_error,
2675 static int init_reserved_iova_ranges(void)
2677 struct pci_dev *pdev = NULL;
2680 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2682 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2683 &reserved_rbtree_key);
2685 /* MSI memory range */
2686 val = reserve_iova(&reserved_iova_ranges,
2687 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2689 pr_err("Reserving MSI range failed\n");
2693 /* HT memory range */
2694 val = reserve_iova(&reserved_iova_ranges,
2695 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2697 pr_err("Reserving HT range failed\n");
2702 * Memory used for PCI resources
2703 * FIXME: Check whether we can reserve the PCI-hole completly
2705 for_each_pci_dev(pdev) {
2708 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2709 struct resource *r = &pdev->resource[i];
2711 if (!(r->flags & IORESOURCE_MEM))
2714 val = reserve_iova(&reserved_iova_ranges,
2718 pr_err("Reserve pci-resource range failed\n");
2727 int __init amd_iommu_init_api(void)
2731 ret = iova_cache_get();
2735 ret = init_reserved_iova_ranges();
2739 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2742 #ifdef CONFIG_ARM_AMBA
2743 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2747 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2754 int __init amd_iommu_init_dma_ops(void)
2756 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2760 * In case we don't initialize SWIOTLB (actually the common case
2761 * when AMD IOMMU is enabled and SME is not active), make sure there
2762 * are global dma_ops set as a fall-back for devices not handled by
2763 * this driver (for example non-PCI devices). When SME is active,
2764 * make sure that swiotlb variable remains set so the global dma_ops
2765 * continue to be SWIOTLB.
2768 dma_ops = &dma_direct_ops;
2770 if (amd_iommu_unmap_flush)
2771 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2773 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2779 /*****************************************************************************
2781 * The following functions belong to the exported interface of AMD IOMMU
2783 * This interface allows access to lower level functions of the IOMMU
2784 * like protection domain handling and assignement of devices to domains
2785 * which is not possible with the dma_ops interface.
2787 *****************************************************************************/
2789 static void cleanup_domain(struct protection_domain *domain)
2791 struct iommu_dev_data *entry;
2792 unsigned long flags;
2794 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2796 while (!list_empty(&domain->dev_list)) {
2797 entry = list_first_entry(&domain->dev_list,
2798 struct iommu_dev_data, list);
2799 __detach_device(entry);
2802 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2805 static void protection_domain_free(struct protection_domain *domain)
2810 del_domain_from_list(domain);
2813 domain_id_free(domain->id);
2818 static int protection_domain_init(struct protection_domain *domain)
2820 spin_lock_init(&domain->lock);
2821 mutex_init(&domain->api_lock);
2822 domain->id = domain_id_alloc();
2825 INIT_LIST_HEAD(&domain->dev_list);
2830 static struct protection_domain *protection_domain_alloc(void)
2832 struct protection_domain *domain;
2834 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2838 if (protection_domain_init(domain))
2841 add_domain_to_list(domain);
2851 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2853 struct protection_domain *pdomain;
2854 struct dma_ops_domain *dma_domain;
2857 case IOMMU_DOMAIN_UNMANAGED:
2858 pdomain = protection_domain_alloc();
2862 pdomain->mode = PAGE_MODE_3_LEVEL;
2863 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2864 if (!pdomain->pt_root) {
2865 protection_domain_free(pdomain);
2869 pdomain->domain.geometry.aperture_start = 0;
2870 pdomain->domain.geometry.aperture_end = ~0ULL;
2871 pdomain->domain.geometry.force_aperture = true;
2874 case IOMMU_DOMAIN_DMA:
2875 dma_domain = dma_ops_domain_alloc();
2877 pr_err("AMD-Vi: Failed to allocate\n");
2880 pdomain = &dma_domain->domain;
2882 case IOMMU_DOMAIN_IDENTITY:
2883 pdomain = protection_domain_alloc();
2887 pdomain->mode = PAGE_MODE_NONE;
2893 return &pdomain->domain;
2896 static void amd_iommu_domain_free(struct iommu_domain *dom)
2898 struct protection_domain *domain;
2899 struct dma_ops_domain *dma_dom;
2901 domain = to_pdomain(dom);
2903 if (domain->dev_cnt > 0)
2904 cleanup_domain(domain);
2906 BUG_ON(domain->dev_cnt != 0);
2911 switch (dom->type) {
2912 case IOMMU_DOMAIN_DMA:
2913 /* Now release the domain */
2914 dma_dom = to_dma_ops_domain(domain);
2915 dma_ops_domain_free(dma_dom);
2918 if (domain->mode != PAGE_MODE_NONE)
2919 free_pagetable(domain);
2921 if (domain->flags & PD_IOMMUV2_MASK)
2922 free_gcr3_table(domain);
2924 protection_domain_free(domain);
2929 static void amd_iommu_detach_device(struct iommu_domain *dom,
2932 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2933 struct amd_iommu *iommu;
2936 if (!check_device(dev))
2939 devid = get_device_id(dev);
2943 if (dev_data->domain != NULL)
2946 iommu = amd_iommu_rlookup_table[devid];
2950 #ifdef CONFIG_IRQ_REMAP
2951 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2952 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2953 dev_data->use_vapic = 0;
2956 iommu_completion_wait(iommu);
2959 static int amd_iommu_attach_device(struct iommu_domain *dom,
2962 struct protection_domain *domain = to_pdomain(dom);
2963 struct iommu_dev_data *dev_data;
2964 struct amd_iommu *iommu;
2967 if (!check_device(dev))
2970 dev_data = dev->archdata.iommu;
2972 iommu = amd_iommu_rlookup_table[dev_data->devid];
2976 if (dev_data->domain)
2979 ret = attach_device(dev, domain);
2981 #ifdef CONFIG_IRQ_REMAP
2982 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2983 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2984 dev_data->use_vapic = 1;
2986 dev_data->use_vapic = 0;
2990 iommu_completion_wait(iommu);
2995 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2996 phys_addr_t paddr, size_t page_size, int iommu_prot)
2998 struct protection_domain *domain = to_pdomain(dom);
3002 if (domain->mode == PAGE_MODE_NONE)
3005 if (iommu_prot & IOMMU_READ)
3006 prot |= IOMMU_PROT_IR;
3007 if (iommu_prot & IOMMU_WRITE)
3008 prot |= IOMMU_PROT_IW;
3010 mutex_lock(&domain->api_lock);
3011 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3012 mutex_unlock(&domain->api_lock);
3017 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3020 struct protection_domain *domain = to_pdomain(dom);
3023 if (domain->mode == PAGE_MODE_NONE)
3026 mutex_lock(&domain->api_lock);
3027 unmap_size = iommu_unmap_page(domain, iova, page_size);
3028 mutex_unlock(&domain->api_lock);
3033 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3036 struct protection_domain *domain = to_pdomain(dom);
3037 unsigned long offset_mask, pte_pgsize;
3040 if (domain->mode == PAGE_MODE_NONE)
3043 pte = fetch_pte(domain, iova, &pte_pgsize);
3045 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3048 offset_mask = pte_pgsize - 1;
3049 __pte = *pte & PM_ADDR_MASK;
3051 return (__pte & ~offset_mask) | (iova & offset_mask);
3054 static bool amd_iommu_capable(enum iommu_cap cap)
3057 case IOMMU_CAP_CACHE_COHERENCY:
3059 case IOMMU_CAP_INTR_REMAP:
3060 return (irq_remapping_enabled == 1);
3061 case IOMMU_CAP_NOEXEC:
3068 static void amd_iommu_get_resv_regions(struct device *dev,
3069 struct list_head *head)
3071 struct iommu_resv_region *region;
3072 struct unity_map_entry *entry;
3075 devid = get_device_id(dev);
3079 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3083 if (devid < entry->devid_start || devid > entry->devid_end)
3086 length = entry->address_end - entry->address_start;
3087 if (entry->prot & IOMMU_PROT_IR)
3089 if (entry->prot & IOMMU_PROT_IW)
3090 prot |= IOMMU_WRITE;
3092 region = iommu_alloc_resv_region(entry->address_start,
3096 pr_err("Out of memory allocating dm-regions for %s\n",
3100 list_add_tail(®ion->list, head);
3103 region = iommu_alloc_resv_region(MSI_RANGE_START,
3104 MSI_RANGE_END - MSI_RANGE_START + 1,
3108 list_add_tail(®ion->list, head);
3110 region = iommu_alloc_resv_region(HT_RANGE_START,
3111 HT_RANGE_END - HT_RANGE_START + 1,
3112 0, IOMMU_RESV_RESERVED);
3115 list_add_tail(®ion->list, head);
3118 static void amd_iommu_put_resv_regions(struct device *dev,
3119 struct list_head *head)
3121 struct iommu_resv_region *entry, *next;
3123 list_for_each_entry_safe(entry, next, head, list)
3127 static void amd_iommu_apply_resv_region(struct device *dev,
3128 struct iommu_domain *domain,
3129 struct iommu_resv_region *region)
3131 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3132 unsigned long start, end;
3134 start = IOVA_PFN(region->start);
3135 end = IOVA_PFN(region->start + region->length - 1);
3137 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3140 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3143 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3144 return dev_data->defer_attach;
3147 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3149 struct protection_domain *dom = to_pdomain(domain);
3151 domain_flush_tlb_pde(dom);
3152 domain_flush_complete(dom);
3155 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3156 unsigned long iova, size_t size)
3160 const struct iommu_ops amd_iommu_ops = {
3161 .capable = amd_iommu_capable,
3162 .domain_alloc = amd_iommu_domain_alloc,
3163 .domain_free = amd_iommu_domain_free,
3164 .attach_dev = amd_iommu_attach_device,
3165 .detach_dev = amd_iommu_detach_device,
3166 .map = amd_iommu_map,
3167 .unmap = amd_iommu_unmap,
3168 .map_sg = default_iommu_map_sg,
3169 .iova_to_phys = amd_iommu_iova_to_phys,
3170 .add_device = amd_iommu_add_device,
3171 .remove_device = amd_iommu_remove_device,
3172 .device_group = amd_iommu_device_group,
3173 .get_resv_regions = amd_iommu_get_resv_regions,
3174 .put_resv_regions = amd_iommu_put_resv_regions,
3175 .apply_resv_region = amd_iommu_apply_resv_region,
3176 .is_attach_deferred = amd_iommu_is_attach_deferred,
3177 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3178 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3179 .iotlb_range_add = amd_iommu_iotlb_range_add,
3180 .iotlb_sync = amd_iommu_flush_iotlb_all,
3183 /*****************************************************************************
3185 * The next functions do a basic initialization of IOMMU for pass through
3188 * In passthrough mode the IOMMU is initialized and enabled but not used for
3189 * DMA-API translation.
3191 *****************************************************************************/
3193 /* IOMMUv2 specific functions */
3194 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3196 return atomic_notifier_chain_register(&ppr_notifier, nb);
3198 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3200 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3202 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3204 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3206 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3208 struct protection_domain *domain = to_pdomain(dom);
3209 unsigned long flags;
3211 spin_lock_irqsave(&domain->lock, flags);
3213 /* Update data structure */
3214 domain->mode = PAGE_MODE_NONE;
3215 domain->updated = true;
3217 /* Make changes visible to IOMMUs */
3218 update_domain(domain);
3220 /* Page-table is not visible to IOMMU anymore, so free it */
3221 free_pagetable(domain);
3223 spin_unlock_irqrestore(&domain->lock, flags);
3225 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3227 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3229 struct protection_domain *domain = to_pdomain(dom);
3230 unsigned long flags;
3233 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3236 /* Number of GCR3 table levels required */
3237 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3240 if (levels > amd_iommu_max_glx_val)
3243 spin_lock_irqsave(&domain->lock, flags);
3246 * Save us all sanity checks whether devices already in the
3247 * domain support IOMMUv2. Just force that the domain has no
3248 * devices attached when it is switched into IOMMUv2 mode.
3251 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3255 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3256 if (domain->gcr3_tbl == NULL)
3259 domain->glx = levels;
3260 domain->flags |= PD_IOMMUV2_MASK;
3261 domain->updated = true;
3263 update_domain(domain);
3268 spin_unlock_irqrestore(&domain->lock, flags);
3272 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3274 static int __flush_pasid(struct protection_domain *domain, int pasid,
3275 u64 address, bool size)
3277 struct iommu_dev_data *dev_data;
3278 struct iommu_cmd cmd;
3281 if (!(domain->flags & PD_IOMMUV2_MASK))
3284 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3287 * IOMMU TLB needs to be flushed before Device TLB to
3288 * prevent device TLB refill from IOMMU TLB
3290 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3291 if (domain->dev_iommu[i] == 0)
3294 ret = iommu_queue_command(amd_iommus[i], &cmd);
3299 /* Wait until IOMMU TLB flushes are complete */
3300 domain_flush_complete(domain);
3302 /* Now flush device TLBs */
3303 list_for_each_entry(dev_data, &domain->dev_list, list) {
3304 struct amd_iommu *iommu;
3308 There might be non-IOMMUv2 capable devices in an IOMMUv2
3311 if (!dev_data->ats.enabled)
3314 qdep = dev_data->ats.qdep;
3315 iommu = amd_iommu_rlookup_table[dev_data->devid];
3317 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3318 qdep, address, size);
3320 ret = iommu_queue_command(iommu, &cmd);
3325 /* Wait until all device TLBs are flushed */
3326 domain_flush_complete(domain);
3335 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3338 return __flush_pasid(domain, pasid, address, false);
3341 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3344 struct protection_domain *domain = to_pdomain(dom);
3345 unsigned long flags;
3348 spin_lock_irqsave(&domain->lock, flags);
3349 ret = __amd_iommu_flush_page(domain, pasid, address);
3350 spin_unlock_irqrestore(&domain->lock, flags);
3354 EXPORT_SYMBOL(amd_iommu_flush_page);
3356 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3358 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3362 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3364 struct protection_domain *domain = to_pdomain(dom);
3365 unsigned long flags;
3368 spin_lock_irqsave(&domain->lock, flags);
3369 ret = __amd_iommu_flush_tlb(domain, pasid);
3370 spin_unlock_irqrestore(&domain->lock, flags);
3374 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3376 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3383 index = (pasid >> (9 * level)) & 0x1ff;
3389 if (!(*pte & GCR3_VALID)) {
3393 root = (void *)get_zeroed_page(GFP_ATOMIC);
3397 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3400 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3408 static int __set_gcr3(struct protection_domain *domain, int pasid,
3413 if (domain->mode != PAGE_MODE_NONE)
3416 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3420 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3422 return __amd_iommu_flush_tlb(domain, pasid);
3425 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3429 if (domain->mode != PAGE_MODE_NONE)
3432 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3438 return __amd_iommu_flush_tlb(domain, pasid);
3441 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3444 struct protection_domain *domain = to_pdomain(dom);
3445 unsigned long flags;
3448 spin_lock_irqsave(&domain->lock, flags);
3449 ret = __set_gcr3(domain, pasid, cr3);
3450 spin_unlock_irqrestore(&domain->lock, flags);
3454 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3456 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3458 struct protection_domain *domain = to_pdomain(dom);
3459 unsigned long flags;
3462 spin_lock_irqsave(&domain->lock, flags);
3463 ret = __clear_gcr3(domain, pasid);
3464 spin_unlock_irqrestore(&domain->lock, flags);
3468 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3470 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3471 int status, int tag)
3473 struct iommu_dev_data *dev_data;
3474 struct amd_iommu *iommu;
3475 struct iommu_cmd cmd;
3477 dev_data = get_dev_data(&pdev->dev);
3478 iommu = amd_iommu_rlookup_table[dev_data->devid];
3480 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3481 tag, dev_data->pri_tlp);
3483 return iommu_queue_command(iommu, &cmd);
3485 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3487 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3489 struct protection_domain *pdomain;
3491 pdomain = get_domain(&pdev->dev);
3492 if (IS_ERR(pdomain))
3495 /* Only return IOMMUv2 domains */
3496 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3499 return &pdomain->domain;
3501 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3503 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3505 struct iommu_dev_data *dev_data;
3507 if (!amd_iommu_v2_supported())
3510 dev_data = get_dev_data(&pdev->dev);
3511 dev_data->errata |= (1 << erratum);
3513 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3515 int amd_iommu_device_info(struct pci_dev *pdev,
3516 struct amd_iommu_device_info *info)
3521 if (pdev == NULL || info == NULL)
3524 if (!amd_iommu_v2_supported())
3527 memset(info, 0, sizeof(*info));
3529 if (!pci_ats_disabled()) {
3530 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3532 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3535 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3537 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3539 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3543 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3544 max_pasids = min(max_pasids, (1 << 20));
3546 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3547 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3549 features = pci_pasid_features(pdev);
3550 if (features & PCI_PASID_CAP_EXEC)
3551 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3552 if (features & PCI_PASID_CAP_PRIV)
3553 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3558 EXPORT_SYMBOL(amd_iommu_device_info);
3560 #ifdef CONFIG_IRQ_REMAP
3562 /*****************************************************************************
3564 * Interrupt Remapping Implementation
3566 *****************************************************************************/
3568 static struct irq_chip amd_ir_chip;
3569 static DEFINE_SPINLOCK(iommu_table_lock);
3571 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3575 dte = amd_iommu_dev_table[devid].data[2];
3576 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3577 dte |= iommu_virt_to_phys(table->table);
3578 dte |= DTE_IRQ_REMAP_INTCTL;
3579 dte |= DTE_IRQ_TABLE_LEN;
3580 dte |= DTE_IRQ_REMAP_ENABLE;
3582 amd_iommu_dev_table[devid].data[2] = dte;
3585 static struct irq_remap_table *get_irq_table(u16 devid)
3587 struct irq_remap_table *table;
3589 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3590 "%s: no iommu for devid %x\n", __func__, devid))
3593 table = irq_lookup_table[devid];
3594 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3600 static struct irq_remap_table *__alloc_irq_table(void)
3602 struct irq_remap_table *table;
3604 table = kzalloc(sizeof(*table), GFP_KERNEL);
3608 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3609 if (!table->table) {
3613 raw_spin_lock_init(&table->lock);
3615 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3616 memset(table->table, 0,
3617 MAX_IRQS_PER_TABLE * sizeof(u32));
3619 memset(table->table, 0,
3620 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3624 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3625 struct irq_remap_table *table)
3627 irq_lookup_table[devid] = table;
3628 set_dte_irq_entry(devid, table);
3629 iommu_flush_dte(iommu, devid);
3632 static struct irq_remap_table *alloc_irq_table(u16 devid)
3634 struct irq_remap_table *table = NULL;
3635 struct irq_remap_table *new_table = NULL;
3636 struct amd_iommu *iommu;
3637 unsigned long flags;
3640 spin_lock_irqsave(&iommu_table_lock, flags);
3642 iommu = amd_iommu_rlookup_table[devid];
3646 table = irq_lookup_table[devid];
3650 alias = amd_iommu_alias_table[devid];
3651 table = irq_lookup_table[alias];
3653 set_remap_table_entry(iommu, devid, table);
3656 spin_unlock_irqrestore(&iommu_table_lock, flags);
3658 /* Nothing there yet, allocate new irq remapping table */
3659 new_table = __alloc_irq_table();
3663 spin_lock_irqsave(&iommu_table_lock, flags);
3665 table = irq_lookup_table[devid];
3669 table = irq_lookup_table[alias];
3671 set_remap_table_entry(iommu, devid, table);
3678 set_remap_table_entry(iommu, devid, table);
3680 set_remap_table_entry(iommu, alias, table);
3683 iommu_completion_wait(iommu);
3686 spin_unlock_irqrestore(&iommu_table_lock, flags);
3689 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3695 static int alloc_irq_index(u16 devid, int count, bool align)
3697 struct irq_remap_table *table;
3698 int index, c, alignment = 1;
3699 unsigned long flags;
3700 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3705 table = alloc_irq_table(devid);
3710 alignment = roundup_pow_of_two(count);
3712 raw_spin_lock_irqsave(&table->lock, flags);
3714 /* Scan table for free entries */
3715 for (index = ALIGN(table->min_index, alignment), c = 0;
3716 index < MAX_IRQS_PER_TABLE;) {
3717 if (!iommu->irte_ops->is_allocated(table, index)) {
3721 index = ALIGN(index + 1, alignment);
3727 iommu->irte_ops->set_allocated(table, index - c + 1);
3739 raw_spin_unlock_irqrestore(&table->lock, flags);
3744 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3745 struct amd_ir_data *data)
3747 struct irq_remap_table *table;
3748 struct amd_iommu *iommu;
3749 unsigned long flags;
3750 struct irte_ga *entry;
3752 iommu = amd_iommu_rlookup_table[devid];
3756 table = get_irq_table(devid);
3760 raw_spin_lock_irqsave(&table->lock, flags);
3762 entry = (struct irte_ga *)table->table;
3763 entry = &entry[index];
3764 entry->lo.fields_remap.valid = 0;
3765 entry->hi.val = irte->hi.val;
3766 entry->lo.val = irte->lo.val;
3767 entry->lo.fields_remap.valid = 1;
3771 raw_spin_unlock_irqrestore(&table->lock, flags);
3773 iommu_flush_irt(iommu, devid);
3774 iommu_completion_wait(iommu);
3779 static int modify_irte(u16 devid, int index, union irte *irte)
3781 struct irq_remap_table *table;
3782 struct amd_iommu *iommu;
3783 unsigned long flags;
3785 iommu = amd_iommu_rlookup_table[devid];
3789 table = get_irq_table(devid);
3793 raw_spin_lock_irqsave(&table->lock, flags);
3794 table->table[index] = irte->val;
3795 raw_spin_unlock_irqrestore(&table->lock, flags);
3797 iommu_flush_irt(iommu, devid);
3798 iommu_completion_wait(iommu);
3803 static void free_irte(u16 devid, int index)
3805 struct irq_remap_table *table;
3806 struct amd_iommu *iommu;
3807 unsigned long flags;
3809 iommu = amd_iommu_rlookup_table[devid];
3813 table = get_irq_table(devid);
3817 raw_spin_lock_irqsave(&table->lock, flags);
3818 iommu->irte_ops->clear_allocated(table, index);
3819 raw_spin_unlock_irqrestore(&table->lock, flags);
3821 iommu_flush_irt(iommu, devid);
3822 iommu_completion_wait(iommu);
3825 static void irte_prepare(void *entry,
3826 u32 delivery_mode, u32 dest_mode,
3827 u8 vector, u32 dest_apicid, int devid)
3829 union irte *irte = (union irte *) entry;
3832 irte->fields.vector = vector;
3833 irte->fields.int_type = delivery_mode;
3834 irte->fields.destination = dest_apicid;
3835 irte->fields.dm = dest_mode;
3836 irte->fields.valid = 1;
3839 static void irte_ga_prepare(void *entry,
3840 u32 delivery_mode, u32 dest_mode,
3841 u8 vector, u32 dest_apicid, int devid)
3843 struct irte_ga *irte = (struct irte_ga *) entry;
3847 irte->lo.fields_remap.int_type = delivery_mode;
3848 irte->lo.fields_remap.dm = dest_mode;
3849 irte->hi.fields.vector = vector;
3850 irte->lo.fields_remap.destination = dest_apicid;
3851 irte->lo.fields_remap.valid = 1;
3854 static void irte_activate(void *entry, u16 devid, u16 index)
3856 union irte *irte = (union irte *) entry;
3858 irte->fields.valid = 1;
3859 modify_irte(devid, index, irte);
3862 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3864 struct irte_ga *irte = (struct irte_ga *) entry;
3866 irte->lo.fields_remap.valid = 1;
3867 modify_irte_ga(devid, index, irte, NULL);
3870 static void irte_deactivate(void *entry, u16 devid, u16 index)
3872 union irte *irte = (union irte *) entry;
3874 irte->fields.valid = 0;
3875 modify_irte(devid, index, irte);
3878 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3880 struct irte_ga *irte = (struct irte_ga *) entry;
3882 irte->lo.fields_remap.valid = 0;
3883 modify_irte_ga(devid, index, irte, NULL);
3886 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3887 u8 vector, u32 dest_apicid)
3889 union irte *irte = (union irte *) entry;
3891 irte->fields.vector = vector;
3892 irte->fields.destination = dest_apicid;
3893 modify_irte(devid, index, irte);
3896 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3897 u8 vector, u32 dest_apicid)
3899 struct irte_ga *irte = (struct irte_ga *) entry;
3901 if (!irte->lo.fields_remap.guest_mode) {
3902 irte->hi.fields.vector = vector;
3903 irte->lo.fields_remap.destination = dest_apicid;
3904 modify_irte_ga(devid, index, irte, NULL);
3908 #define IRTE_ALLOCATED (~1U)
3909 static void irte_set_allocated(struct irq_remap_table *table, int index)
3911 table->table[index] = IRTE_ALLOCATED;
3914 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3916 struct irte_ga *ptr = (struct irte_ga *)table->table;
3917 struct irte_ga *irte = &ptr[index];
3919 memset(&irte->lo.val, 0, sizeof(u64));
3920 memset(&irte->hi.val, 0, sizeof(u64));
3921 irte->hi.fields.vector = 0xff;
3924 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3926 union irte *ptr = (union irte *)table->table;
3927 union irte *irte = &ptr[index];
3929 return irte->val != 0;
3932 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3934 struct irte_ga *ptr = (struct irte_ga *)table->table;
3935 struct irte_ga *irte = &ptr[index];
3937 return irte->hi.fields.vector != 0;
3940 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3942 table->table[index] = 0;
3945 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3947 struct irte_ga *ptr = (struct irte_ga *)table->table;
3948 struct irte_ga *irte = &ptr[index];
3950 memset(&irte->lo.val, 0, sizeof(u64));
3951 memset(&irte->hi.val, 0, sizeof(u64));
3954 static int get_devid(struct irq_alloc_info *info)
3958 switch (info->type) {
3959 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3960 devid = get_ioapic_devid(info->ioapic_id);
3962 case X86_IRQ_ALLOC_TYPE_HPET:
3963 devid = get_hpet_devid(info->hpet_id);
3965 case X86_IRQ_ALLOC_TYPE_MSI:
3966 case X86_IRQ_ALLOC_TYPE_MSIX:
3967 devid = get_device_id(&info->msi_dev->dev);
3977 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3979 struct amd_iommu *iommu;
3985 devid = get_devid(info);
3987 iommu = amd_iommu_rlookup_table[devid];
3989 return iommu->ir_domain;
3995 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3997 struct amd_iommu *iommu;
4003 switch (info->type) {
4004 case X86_IRQ_ALLOC_TYPE_MSI:
4005 case X86_IRQ_ALLOC_TYPE_MSIX:
4006 devid = get_device_id(&info->msi_dev->dev);
4010 iommu = amd_iommu_rlookup_table[devid];
4012 return iommu->msi_domain;
4021 struct irq_remap_ops amd_iommu_irq_ops = {
4022 .prepare = amd_iommu_prepare,
4023 .enable = amd_iommu_enable,
4024 .disable = amd_iommu_disable,
4025 .reenable = amd_iommu_reenable,
4026 .enable_faulting = amd_iommu_enable_faulting,
4027 .get_ir_irq_domain = get_ir_irq_domain,
4028 .get_irq_domain = get_irq_domain,
4031 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4032 struct irq_cfg *irq_cfg,
4033 struct irq_alloc_info *info,
4034 int devid, int index, int sub_handle)
4036 struct irq_2_irte *irte_info = &data->irq_2_irte;
4037 struct msi_msg *msg = &data->msi_entry;
4038 struct IO_APIC_route_entry *entry;
4039 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4044 data->irq_2_irte.devid = devid;
4045 data->irq_2_irte.index = index + sub_handle;
4046 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4047 apic->irq_dest_mode, irq_cfg->vector,
4048 irq_cfg->dest_apicid, devid);
4050 switch (info->type) {
4051 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4052 /* Setup IOAPIC entry */
4053 entry = info->ioapic_entry;
4054 info->ioapic_entry = NULL;
4055 memset(entry, 0, sizeof(*entry));
4056 entry->vector = index;
4058 entry->trigger = info->ioapic_trigger;
4059 entry->polarity = info->ioapic_polarity;
4060 /* Mask level triggered irqs. */
4061 if (info->ioapic_trigger)
4065 case X86_IRQ_ALLOC_TYPE_HPET:
4066 case X86_IRQ_ALLOC_TYPE_MSI:
4067 case X86_IRQ_ALLOC_TYPE_MSIX:
4068 msg->address_hi = MSI_ADDR_BASE_HI;
4069 msg->address_lo = MSI_ADDR_BASE_LO;
4070 msg->data = irte_info->index;
4079 struct amd_irte_ops irte_32_ops = {
4080 .prepare = irte_prepare,
4081 .activate = irte_activate,
4082 .deactivate = irte_deactivate,
4083 .set_affinity = irte_set_affinity,
4084 .set_allocated = irte_set_allocated,
4085 .is_allocated = irte_is_allocated,
4086 .clear_allocated = irte_clear_allocated,
4089 struct amd_irte_ops irte_128_ops = {
4090 .prepare = irte_ga_prepare,
4091 .activate = irte_ga_activate,
4092 .deactivate = irte_ga_deactivate,
4093 .set_affinity = irte_ga_set_affinity,
4094 .set_allocated = irte_ga_set_allocated,
4095 .is_allocated = irte_ga_is_allocated,
4096 .clear_allocated = irte_ga_clear_allocated,
4099 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4100 unsigned int nr_irqs, void *arg)
4102 struct irq_alloc_info *info = arg;
4103 struct irq_data *irq_data;
4104 struct amd_ir_data *data = NULL;
4105 struct irq_cfg *cfg;
4111 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4112 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4116 * With IRQ remapping enabled, don't need contiguous CPU vectors
4117 * to support multiple MSI interrupts.
4119 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4120 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4122 devid = get_devid(info);
4126 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4130 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4131 struct irq_remap_table *table;
4132 struct amd_iommu *iommu;
4134 table = alloc_irq_table(devid);
4136 if (!table->min_index) {
4138 * Keep the first 32 indexes free for IOAPIC
4141 table->min_index = 32;
4142 iommu = amd_iommu_rlookup_table[devid];
4143 for (i = 0; i < 32; ++i)
4144 iommu->irte_ops->set_allocated(table, i);
4146 WARN_ON(table->min_index != 32);
4147 index = info->ioapic_pin;
4152 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4154 index = alloc_irq_index(devid, nr_irqs, align);
4157 pr_warn("Failed to allocate IRTE\n");
4159 goto out_free_parent;
4162 for (i = 0; i < nr_irqs; i++) {
4163 irq_data = irq_domain_get_irq_data(domain, virq + i);
4164 cfg = irqd_cfg(irq_data);
4165 if (!irq_data || !cfg) {
4171 data = kzalloc(sizeof(*data), GFP_KERNEL);
4175 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4176 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4178 data->entry = kzalloc(sizeof(struct irte_ga),
4185 irq_data->hwirq = (devid << 16) + i;
4186 irq_data->chip_data = data;
4187 irq_data->chip = &amd_ir_chip;
4188 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4189 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4195 for (i--; i >= 0; i--) {
4196 irq_data = irq_domain_get_irq_data(domain, virq + i);
4198 kfree(irq_data->chip_data);
4200 for (i = 0; i < nr_irqs; i++)
4201 free_irte(devid, index + i);
4203 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4207 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4208 unsigned int nr_irqs)
4210 struct irq_2_irte *irte_info;
4211 struct irq_data *irq_data;
4212 struct amd_ir_data *data;
4215 for (i = 0; i < nr_irqs; i++) {
4216 irq_data = irq_domain_get_irq_data(domain, virq + i);
4217 if (irq_data && irq_data->chip_data) {
4218 data = irq_data->chip_data;
4219 irte_info = &data->irq_2_irte;
4220 free_irte(irte_info->devid, irte_info->index);
4225 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4228 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4229 struct amd_ir_data *ir_data,
4230 struct irq_2_irte *irte_info,
4231 struct irq_cfg *cfg);
4233 static int irq_remapping_activate(struct irq_domain *domain,
4234 struct irq_data *irq_data, bool reserve)
4236 struct amd_ir_data *data = irq_data->chip_data;
4237 struct irq_2_irte *irte_info = &data->irq_2_irte;
4238 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4239 struct irq_cfg *cfg = irqd_cfg(irq_data);
4244 iommu->irte_ops->activate(data->entry, irte_info->devid,
4246 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4250 static void irq_remapping_deactivate(struct irq_domain *domain,
4251 struct irq_data *irq_data)
4253 struct amd_ir_data *data = irq_data->chip_data;
4254 struct irq_2_irte *irte_info = &data->irq_2_irte;
4255 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4258 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4262 static const struct irq_domain_ops amd_ir_domain_ops = {
4263 .alloc = irq_remapping_alloc,
4264 .free = irq_remapping_free,
4265 .activate = irq_remapping_activate,
4266 .deactivate = irq_remapping_deactivate,
4269 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4271 struct amd_iommu *iommu;
4272 struct amd_iommu_pi_data *pi_data = vcpu_info;
4273 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4274 struct amd_ir_data *ir_data = data->chip_data;
4275 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4276 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4277 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4280 * This device has never been set up for guest mode.
4281 * we should not modify the IRTE
4283 if (!dev_data || !dev_data->use_vapic)
4286 pi_data->ir_data = ir_data;
4289 * SVM tries to set up for VAPIC mode, but we are in
4290 * legacy mode. So, we force legacy mode instead.
4292 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4293 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4295 pi_data->is_guest_mode = false;
4298 iommu = amd_iommu_rlookup_table[irte_info->devid];
4302 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4303 if (pi_data->is_guest_mode) {
4305 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4306 irte->hi.fields.vector = vcpu_pi_info->vector;
4307 irte->lo.fields_vapic.ga_log_intr = 1;
4308 irte->lo.fields_vapic.guest_mode = 1;
4309 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4311 ir_data->cached_ga_tag = pi_data->ga_tag;
4314 struct irq_cfg *cfg = irqd_cfg(data);
4318 irte->hi.fields.vector = cfg->vector;
4319 irte->lo.fields_remap.guest_mode = 0;
4320 irte->lo.fields_remap.destination = cfg->dest_apicid;
4321 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4322 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4325 * This communicates the ga_tag back to the caller
4326 * so that it can do all the necessary clean up.
4328 ir_data->cached_ga_tag = 0;
4331 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4335 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4336 struct amd_ir_data *ir_data,
4337 struct irq_2_irte *irte_info,
4338 struct irq_cfg *cfg)
4342 * Atomically updates the IRTE with the new destination, vector
4343 * and flushes the interrupt entry cache.
4345 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4346 irte_info->index, cfg->vector,
4350 static int amd_ir_set_affinity(struct irq_data *data,
4351 const struct cpumask *mask, bool force)
4353 struct amd_ir_data *ir_data = data->chip_data;
4354 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4355 struct irq_cfg *cfg = irqd_cfg(data);
4356 struct irq_data *parent = data->parent_data;
4357 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4363 ret = parent->chip->irq_set_affinity(parent, mask, force);
4364 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4367 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4369 * After this point, all the interrupts will start arriving
4370 * at the new destination. So, time to cleanup the previous
4371 * vector allocation.
4373 send_cleanup_vector(cfg);
4375 return IRQ_SET_MASK_OK_DONE;
4378 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4380 struct amd_ir_data *ir_data = irq_data->chip_data;
4382 *msg = ir_data->msi_entry;
4385 static struct irq_chip amd_ir_chip = {
4387 .irq_ack = ir_ack_apic_edge,
4388 .irq_set_affinity = amd_ir_set_affinity,
4389 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4390 .irq_compose_msi_msg = ir_compose_msi_msg,
4393 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4395 struct fwnode_handle *fn;
4397 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4400 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4401 irq_domain_free_fwnode(fn);
4402 if (!iommu->ir_domain)
4405 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4406 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4412 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4414 unsigned long flags;
4415 struct amd_iommu *iommu;
4416 struct irq_remap_table *table;
4417 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4418 int devid = ir_data->irq_2_irte.devid;
4419 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4420 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4422 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4423 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4426 iommu = amd_iommu_rlookup_table[devid];
4430 table = get_irq_table(devid);
4434 raw_spin_lock_irqsave(&table->lock, flags);
4436 if (ref->lo.fields_vapic.guest_mode) {
4438 ref->lo.fields_vapic.destination = cpu;
4439 ref->lo.fields_vapic.is_run = is_run;
4443 raw_spin_unlock_irqrestore(&table->lock, flags);
4445 iommu_flush_irt(iommu, devid);
4446 iommu_completion_wait(iommu);
4449 EXPORT_SYMBOL(amd_iommu_update_ga);