1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-direct.h>
23 #include <linux/iommu-helper.h>
24 #include <linux/iommu.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/dma-contiguous.h>
32 #include <linux/irqdomain.h>
33 #include <linux/percpu.h>
34 #include <linux/iova.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/io_apic.h>
38 #include <asm/hw_irq.h>
39 #include <asm/msidef.h>
40 #include <asm/proto.h>
41 #include <asm/iommu.h>
45 #include "amd_iommu_proto.h"
46 #include "amd_iommu_types.h"
47 #include "irq_remapping.h"
49 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
51 #define LOOP_TIMEOUT 100000
53 /* IO virtual address start page frame number */
54 #define IOVA_START_PFN (1)
55 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
57 /* Reserved IOVA ranges */
58 #define MSI_RANGE_START (0xfee00000)
59 #define MSI_RANGE_END (0xfeefffff)
60 #define HT_RANGE_START (0xfd00000000ULL)
61 #define HT_RANGE_END (0xffffffffffULL)
64 * This bitmap is used to advertise the page sizes our hardware support
65 * to the IOMMU core, which will then use this information to split
66 * physically contiguous memory regions it is mapping into page sizes
69 * 512GB Pages are not supported due to a hardware bug
71 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
73 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
74 static DEFINE_SPINLOCK(pd_bitmap_lock);
76 /* List of all available dev_data structures */
77 static LLIST_HEAD(dev_data_list);
79 LIST_HEAD(ioapic_map);
81 LIST_HEAD(acpihid_map);
84 * Domain for untranslated devices - only allocated
85 * if iommu=pt passed on kernel cmd line.
87 const struct iommu_ops amd_iommu_ops;
89 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
90 int amd_iommu_max_glx_val = -1;
92 static const struct dma_map_ops amd_iommu_dma_ops;
95 * general struct to manage commands send to an IOMMU
101 struct kmem_cache *amd_iommu_irq_cache;
103 static void update_domain(struct protection_domain *domain);
104 static int protection_domain_init(struct protection_domain *domain);
105 static void detach_device(struct device *dev);
106 static void iova_domain_flush_tlb(struct iova_domain *iovad);
109 * Data container for a dma_ops specific protection domain
111 struct dma_ops_domain {
112 /* generic protection domain information */
113 struct protection_domain domain;
116 struct iova_domain iovad;
119 static struct iova_domain reserved_iova_ranges;
120 static struct lock_class_key reserved_rbtree_key;
122 /****************************************************************************
126 ****************************************************************************/
128 static inline int match_hid_uid(struct device *dev,
129 struct acpihid_map_entry *entry)
131 struct acpi_device *adev = ACPI_COMPANION(dev);
132 const char *hid, *uid;
137 hid = acpi_device_hid(adev);
138 uid = acpi_device_uid(adev);
144 return strcmp(hid, entry->hid);
147 return strcmp(hid, entry->hid);
149 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
152 static inline u16 get_pci_device_id(struct device *dev)
154 struct pci_dev *pdev = to_pci_dev(dev);
156 return pci_dev_id(pdev);
159 static inline int get_acpihid_device_id(struct device *dev,
160 struct acpihid_map_entry **entry)
162 struct acpihid_map_entry *p;
164 list_for_each_entry(p, &acpihid_map, list) {
165 if (!match_hid_uid(dev, p)) {
174 static inline int get_device_id(struct device *dev)
179 devid = get_pci_device_id(dev);
181 devid = get_acpihid_device_id(dev, NULL);
186 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
188 return container_of(dom, struct protection_domain, domain);
191 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
193 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
194 return container_of(domain, struct dma_ops_domain, domain);
197 static struct iommu_dev_data *alloc_dev_data(u16 devid)
199 struct iommu_dev_data *dev_data;
201 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
205 dev_data->devid = devid;
206 ratelimit_default_init(&dev_data->rs);
208 llist_add(&dev_data->dev_data_list, &dev_data_list);
212 static struct iommu_dev_data *search_dev_data(u16 devid)
214 struct iommu_dev_data *dev_data;
215 struct llist_node *node;
217 if (llist_empty(&dev_data_list))
220 node = dev_data_list.first;
221 llist_for_each_entry(dev_data, node, dev_data_list) {
222 if (dev_data->devid == devid)
229 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
231 *(u16 *)data = alias;
235 static u16 get_alias(struct device *dev)
237 struct pci_dev *pdev = to_pci_dev(dev);
238 u16 devid, ivrs_alias, pci_alias;
240 /* The callers make sure that get_device_id() does not fail here */
241 devid = get_device_id(dev);
243 /* For ACPI HID devices, we simply return the devid as such */
244 if (!dev_is_pci(dev))
247 ivrs_alias = amd_iommu_alias_table[devid];
249 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
251 if (ivrs_alias == pci_alias)
257 * The IVRS is fairly reliable in telling us about aliases, but it
258 * can't know about every screwy device. If we don't have an IVRS
259 * reported alias, use the PCI reported alias. In that case we may
260 * still need to initialize the rlookup and dev_table entries if the
261 * alias is to a non-existent device.
263 if (ivrs_alias == devid) {
264 if (!amd_iommu_rlookup_table[pci_alias]) {
265 amd_iommu_rlookup_table[pci_alias] =
266 amd_iommu_rlookup_table[devid];
267 memcpy(amd_iommu_dev_table[pci_alias].data,
268 amd_iommu_dev_table[devid].data,
269 sizeof(amd_iommu_dev_table[pci_alias].data));
275 pci_info(pdev, "Using IVRS reported alias %02x:%02x.%d "
276 "for device [%04x:%04x], kernel reported alias "
277 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
278 PCI_FUNC(ivrs_alias), pdev->vendor, pdev->device,
279 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
280 PCI_FUNC(pci_alias));
283 * If we don't have a PCI DMA alias and the IVRS alias is on the same
284 * bus, then the IVRS table may know about a quirk that we don't.
286 if (pci_alias == devid &&
287 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
288 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
289 pci_info(pdev, "Added PCI DMA alias %02x.%d\n",
290 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias));
296 static struct iommu_dev_data *find_dev_data(u16 devid)
298 struct iommu_dev_data *dev_data;
299 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
301 dev_data = search_dev_data(devid);
303 if (dev_data == NULL) {
304 dev_data = alloc_dev_data(devid);
308 if (translation_pre_enabled(iommu))
309 dev_data->defer_attach = true;
315 struct iommu_dev_data *get_dev_data(struct device *dev)
317 return dev->archdata.iommu;
319 EXPORT_SYMBOL(get_dev_data);
322 * Find or create an IOMMU group for a acpihid device.
324 static struct iommu_group *acpihid_device_group(struct device *dev)
326 struct acpihid_map_entry *p, *entry = NULL;
329 devid = get_acpihid_device_id(dev, &entry);
331 return ERR_PTR(devid);
333 list_for_each_entry(p, &acpihid_map, list) {
334 if ((devid == p->devid) && p->group)
335 entry->group = p->group;
339 entry->group = generic_device_group(dev);
341 iommu_group_ref_get(entry->group);
346 static bool pci_iommuv2_capable(struct pci_dev *pdev)
348 static const int caps[] = {
351 PCI_EXT_CAP_ID_PASID,
355 if (pci_ats_disabled())
358 for (i = 0; i < 3; ++i) {
359 pos = pci_find_ext_capability(pdev, caps[i]);
367 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
369 struct iommu_dev_data *dev_data;
371 dev_data = get_dev_data(&pdev->dev);
373 return dev_data->errata & (1 << erratum) ? true : false;
377 * This function checks if the driver got a valid device from the caller to
378 * avoid dereferencing invalid pointers.
380 static bool check_device(struct device *dev)
384 if (!dev || !dev->dma_mask)
387 devid = get_device_id(dev);
391 /* Out of our scope? */
392 if (devid > amd_iommu_last_bdf)
395 if (amd_iommu_rlookup_table[devid] == NULL)
401 static void init_iommu_group(struct device *dev)
403 struct iommu_group *group;
405 group = iommu_group_get_for_dev(dev);
409 iommu_group_put(group);
412 static int iommu_init_device(struct device *dev)
414 struct iommu_dev_data *dev_data;
415 struct amd_iommu *iommu;
418 if (dev->archdata.iommu)
421 devid = get_device_id(dev);
425 iommu = amd_iommu_rlookup_table[devid];
427 dev_data = find_dev_data(devid);
431 dev_data->alias = get_alias(dev);
434 * By default we use passthrough mode for IOMMUv2 capable device.
435 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
436 * invalid address), we ignore the capability for the device so
437 * it'll be forced to go into translation mode.
439 if ((iommu_pass_through || !amd_iommu_force_isolation) &&
440 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
441 struct amd_iommu *iommu;
443 iommu = amd_iommu_rlookup_table[dev_data->devid];
444 dev_data->iommu_v2 = iommu->is_iommu_v2;
447 dev->archdata.iommu = dev_data;
449 iommu_device_link(&iommu->iommu, dev);
454 static void iommu_ignore_device(struct device *dev)
459 devid = get_device_id(dev);
463 alias = get_alias(dev);
465 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
466 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
468 amd_iommu_rlookup_table[devid] = NULL;
469 amd_iommu_rlookup_table[alias] = NULL;
472 static void iommu_uninit_device(struct device *dev)
474 struct iommu_dev_data *dev_data;
475 struct amd_iommu *iommu;
478 devid = get_device_id(dev);
482 iommu = amd_iommu_rlookup_table[devid];
484 dev_data = search_dev_data(devid);
488 if (dev_data->domain)
491 iommu_device_unlink(&iommu->iommu, dev);
493 iommu_group_remove_device(dev);
499 * We keep dev_data around for unplugged devices and reuse it when the
500 * device is re-plugged - not doing so would introduce a ton of races.
504 /****************************************************************************
506 * Interrupt handling functions
508 ****************************************************************************/
510 static void dump_dte_entry(u16 devid)
514 for (i = 0; i < 4; ++i)
515 pr_err("DTE[%d]: %016llx\n", i,
516 amd_iommu_dev_table[devid].data[i]);
519 static void dump_command(unsigned long phys_addr)
521 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
524 for (i = 0; i < 4; ++i)
525 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
528 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
529 u64 address, int flags)
531 struct iommu_dev_data *dev_data = NULL;
532 struct pci_dev *pdev;
534 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
537 dev_data = get_dev_data(&pdev->dev);
539 if (dev_data && __ratelimit(&dev_data->rs)) {
540 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
541 domain_id, address, flags);
542 } else if (printk_ratelimit()) {
543 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
544 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
545 domain_id, address, flags);
552 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
554 struct device *dev = iommu->iommu.dev;
555 int type, devid, pasid, flags, tag;
556 volatile u32 *event = __evt;
561 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
562 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
563 pasid = PPR_PASID(*(u64 *)&event[0]);
564 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
565 address = (u64)(((u64)event[3]) << 32) | event[2];
568 /* Did we hit the erratum? */
569 if (++count == LOOP_TIMEOUT) {
570 pr_err("No event written to event log\n");
577 if (type == EVENT_TYPE_IO_FAULT) {
578 amd_iommu_report_page_fault(devid, pasid, address, flags);
583 case EVENT_TYPE_ILL_DEV:
584 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
585 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
586 pasid, address, flags);
587 dump_dte_entry(devid);
589 case EVENT_TYPE_DEV_TAB_ERR:
590 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
591 "address=0x%llx flags=0x%04x]\n",
592 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
595 case EVENT_TYPE_PAGE_TAB_ERR:
596 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
598 pasid, address, flags);
600 case EVENT_TYPE_ILL_CMD:
601 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
602 dump_command(address);
604 case EVENT_TYPE_CMD_HARD_ERR:
605 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
608 case EVENT_TYPE_IOTLB_INV_TO:
609 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
610 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
613 case EVENT_TYPE_INV_DEV_REQ:
614 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
616 pasid, address, flags);
618 case EVENT_TYPE_INV_PPR_REQ:
619 pasid = ((event[0] >> 16) & 0xFFFF)
620 | ((event[1] << 6) & 0xF0000);
621 tag = event[1] & 0x03FF;
622 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
623 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
624 pasid, address, flags);
627 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
628 event[0], event[1], event[2], event[3]);
631 memset(__evt, 0, 4 * sizeof(u32));
634 static void iommu_poll_events(struct amd_iommu *iommu)
638 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
639 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
641 while (head != tail) {
642 iommu_print_event(iommu, iommu->evt_buf + head);
643 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
646 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
649 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
651 struct amd_iommu_fault fault;
653 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
654 pr_err_ratelimited("Unknown PPR request received\n");
658 fault.address = raw[1];
659 fault.pasid = PPR_PASID(raw[0]);
660 fault.device_id = PPR_DEVID(raw[0]);
661 fault.tag = PPR_TAG(raw[0]);
662 fault.flags = PPR_FLAGS(raw[0]);
664 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
667 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
671 if (iommu->ppr_log == NULL)
674 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
675 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
677 while (head != tail) {
682 raw = (u64 *)(iommu->ppr_log + head);
685 * Hardware bug: Interrupt may arrive before the entry is
686 * written to memory. If this happens we need to wait for the
689 for (i = 0; i < LOOP_TIMEOUT; ++i) {
690 if (PPR_REQ_TYPE(raw[0]) != 0)
695 /* Avoid memcpy function-call overhead */
700 * To detect the hardware bug we need to clear the entry
703 raw[0] = raw[1] = 0UL;
705 /* Update head pointer of hardware ring-buffer */
706 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
707 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
709 /* Handle PPR entry */
710 iommu_handle_ppr_entry(iommu, entry);
712 /* Refresh ring-buffer information */
713 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
714 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
718 #ifdef CONFIG_IRQ_REMAP
719 static int (*iommu_ga_log_notifier)(u32);
721 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
723 iommu_ga_log_notifier = notifier;
727 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
729 static void iommu_poll_ga_log(struct amd_iommu *iommu)
731 u32 head, tail, cnt = 0;
733 if (iommu->ga_log == NULL)
736 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
737 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
739 while (head != tail) {
743 raw = (u64 *)(iommu->ga_log + head);
746 /* Avoid memcpy function-call overhead */
749 /* Update head pointer of hardware ring-buffer */
750 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
751 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
753 /* Handle GA entry */
754 switch (GA_REQ_TYPE(log_entry)) {
756 if (!iommu_ga_log_notifier)
759 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
760 __func__, GA_DEVID(log_entry),
763 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
764 pr_err("GA log notifier failed.\n");
771 #endif /* CONFIG_IRQ_REMAP */
773 #define AMD_IOMMU_INT_MASK \
774 (MMIO_STATUS_EVT_INT_MASK | \
775 MMIO_STATUS_PPR_INT_MASK | \
776 MMIO_STATUS_GALOG_INT_MASK)
778 irqreturn_t amd_iommu_int_thread(int irq, void *data)
780 struct amd_iommu *iommu = (struct amd_iommu *) data;
781 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
783 while (status & AMD_IOMMU_INT_MASK) {
784 /* Enable EVT and PPR and GA interrupts again */
785 writel(AMD_IOMMU_INT_MASK,
786 iommu->mmio_base + MMIO_STATUS_OFFSET);
788 if (status & MMIO_STATUS_EVT_INT_MASK) {
789 pr_devel("Processing IOMMU Event Log\n");
790 iommu_poll_events(iommu);
793 if (status & MMIO_STATUS_PPR_INT_MASK) {
794 pr_devel("Processing IOMMU PPR Log\n");
795 iommu_poll_ppr_log(iommu);
798 #ifdef CONFIG_IRQ_REMAP
799 if (status & MMIO_STATUS_GALOG_INT_MASK) {
800 pr_devel("Processing IOMMU GA Log\n");
801 iommu_poll_ga_log(iommu);
806 * Hardware bug: ERBT1312
807 * When re-enabling interrupt (by writing 1
808 * to clear the bit), the hardware might also try to set
809 * the interrupt bit in the event status register.
810 * In this scenario, the bit will be set, and disable
811 * subsequent interrupts.
813 * Workaround: The IOMMU driver should read back the
814 * status register and check if the interrupt bits are cleared.
815 * If not, driver will need to go through the interrupt handler
816 * again and re-clear the bits
818 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
823 irqreturn_t amd_iommu_int_handler(int irq, void *data)
825 return IRQ_WAKE_THREAD;
828 /****************************************************************************
830 * IOMMU command queuing functions
832 ****************************************************************************/
834 static int wait_on_sem(volatile u64 *sem)
838 while (*sem == 0 && i < LOOP_TIMEOUT) {
843 if (i == LOOP_TIMEOUT) {
844 pr_alert("Completion-Wait loop timed out\n");
851 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
852 struct iommu_cmd *cmd)
856 target = iommu->cmd_buf + iommu->cmd_buf_tail;
858 iommu->cmd_buf_tail += sizeof(*cmd);
859 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
861 /* Copy command to buffer */
862 memcpy(target, cmd, sizeof(*cmd));
864 /* Tell the IOMMU about it */
865 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
868 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
870 u64 paddr = iommu_virt_to_phys((void *)address);
872 WARN_ON(address & 0x7ULL);
874 memset(cmd, 0, sizeof(*cmd));
875 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
876 cmd->data[1] = upper_32_bits(paddr);
878 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
881 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
883 memset(cmd, 0, sizeof(*cmd));
884 cmd->data[0] = devid;
885 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
888 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
889 size_t size, u16 domid, int pde)
894 pages = iommu_num_pages(address, size, PAGE_SIZE);
899 * If we have to flush more than one page, flush all
900 * TLB entries for this domain
902 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
906 address &= PAGE_MASK;
908 memset(cmd, 0, sizeof(*cmd));
909 cmd->data[1] |= domid;
910 cmd->data[2] = lower_32_bits(address);
911 cmd->data[3] = upper_32_bits(address);
912 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
913 if (s) /* size bit - we flush more than one 4kb page */
914 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
915 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
916 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
919 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
920 u64 address, size_t size)
925 pages = iommu_num_pages(address, size, PAGE_SIZE);
930 * If we have to flush more than one page, flush all
931 * TLB entries for this domain
933 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
937 address &= PAGE_MASK;
939 memset(cmd, 0, sizeof(*cmd));
940 cmd->data[0] = devid;
941 cmd->data[0] |= (qdep & 0xff) << 24;
942 cmd->data[1] = devid;
943 cmd->data[2] = lower_32_bits(address);
944 cmd->data[3] = upper_32_bits(address);
945 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
947 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
950 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
951 u64 address, bool size)
953 memset(cmd, 0, sizeof(*cmd));
955 address &= ~(0xfffULL);
957 cmd->data[0] = pasid;
958 cmd->data[1] = domid;
959 cmd->data[2] = lower_32_bits(address);
960 cmd->data[3] = upper_32_bits(address);
961 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
962 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
964 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
965 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
968 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
969 int qdep, u64 address, bool size)
971 memset(cmd, 0, sizeof(*cmd));
973 address &= ~(0xfffULL);
975 cmd->data[0] = devid;
976 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
977 cmd->data[0] |= (qdep & 0xff) << 24;
978 cmd->data[1] = devid;
979 cmd->data[1] |= (pasid & 0xff) << 16;
980 cmd->data[2] = lower_32_bits(address);
981 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
982 cmd->data[3] = upper_32_bits(address);
984 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
985 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
988 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
989 int status, int tag, bool gn)
991 memset(cmd, 0, sizeof(*cmd));
993 cmd->data[0] = devid;
995 cmd->data[1] = pasid;
996 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
998 cmd->data[3] = tag & 0x1ff;
999 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1001 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1004 static void build_inv_all(struct iommu_cmd *cmd)
1006 memset(cmd, 0, sizeof(*cmd));
1007 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1010 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1012 memset(cmd, 0, sizeof(*cmd));
1013 cmd->data[0] = devid;
1014 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1018 * Writes the command to the IOMMUs command buffer and informs the
1019 * hardware about the new command.
1021 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1022 struct iommu_cmd *cmd,
1025 unsigned int count = 0;
1026 u32 left, next_tail;
1028 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1030 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1033 /* Skip udelay() the first time around */
1035 if (count == LOOP_TIMEOUT) {
1036 pr_err("Command buffer timeout\n");
1043 /* Update head and recheck remaining space */
1044 iommu->cmd_buf_head = readl(iommu->mmio_base +
1045 MMIO_CMD_HEAD_OFFSET);
1050 copy_cmd_to_buffer(iommu, cmd);
1052 /* Do we need to make sure all commands are processed? */
1053 iommu->need_sync = sync;
1058 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1059 struct iommu_cmd *cmd,
1062 unsigned long flags;
1065 raw_spin_lock_irqsave(&iommu->lock, flags);
1066 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1067 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1072 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1074 return iommu_queue_command_sync(iommu, cmd, true);
1078 * This function queues a completion wait command into the command
1079 * buffer of an IOMMU
1081 static int iommu_completion_wait(struct amd_iommu *iommu)
1083 struct iommu_cmd cmd;
1084 unsigned long flags;
1087 if (!iommu->need_sync)
1091 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1093 raw_spin_lock_irqsave(&iommu->lock, flags);
1097 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1101 ret = wait_on_sem(&iommu->cmd_sem);
1104 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1109 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1111 struct iommu_cmd cmd;
1113 build_inv_dte(&cmd, devid);
1115 return iommu_queue_command(iommu, &cmd);
1118 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1122 for (devid = 0; devid <= 0xffff; ++devid)
1123 iommu_flush_dte(iommu, devid);
1125 iommu_completion_wait(iommu);
1129 * This function uses heavy locking and may disable irqs for some time. But
1130 * this is no issue because it is only called during resume.
1132 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1136 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1137 struct iommu_cmd cmd;
1138 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1140 iommu_queue_command(iommu, &cmd);
1143 iommu_completion_wait(iommu);
1146 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1148 struct iommu_cmd cmd;
1150 build_inv_all(&cmd);
1152 iommu_queue_command(iommu, &cmd);
1153 iommu_completion_wait(iommu);
1156 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1158 struct iommu_cmd cmd;
1160 build_inv_irt(&cmd, devid);
1162 iommu_queue_command(iommu, &cmd);
1165 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1169 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1170 iommu_flush_irt(iommu, devid);
1172 iommu_completion_wait(iommu);
1175 void iommu_flush_all_caches(struct amd_iommu *iommu)
1177 if (iommu_feature(iommu, FEATURE_IA)) {
1178 amd_iommu_flush_all(iommu);
1180 amd_iommu_flush_dte_all(iommu);
1181 amd_iommu_flush_irt_all(iommu);
1182 amd_iommu_flush_tlb_all(iommu);
1187 * Command send function for flushing on-device TLB
1189 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1190 u64 address, size_t size)
1192 struct amd_iommu *iommu;
1193 struct iommu_cmd cmd;
1196 qdep = dev_data->ats.qdep;
1197 iommu = amd_iommu_rlookup_table[dev_data->devid];
1199 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1201 return iommu_queue_command(iommu, &cmd);
1205 * Command send function for invalidating a device table entry
1207 static int device_flush_dte(struct iommu_dev_data *dev_data)
1209 struct amd_iommu *iommu;
1213 iommu = amd_iommu_rlookup_table[dev_data->devid];
1214 alias = dev_data->alias;
1216 ret = iommu_flush_dte(iommu, dev_data->devid);
1217 if (!ret && alias != dev_data->devid)
1218 ret = iommu_flush_dte(iommu, alias);
1222 if (dev_data->ats.enabled)
1223 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1229 * TLB invalidation function which is called from the mapping functions.
1230 * It invalidates a single PTE if the range to flush is within a single
1231 * page. Otherwise it flushes the whole TLB of the IOMMU.
1233 static void __domain_flush_pages(struct protection_domain *domain,
1234 u64 address, size_t size, int pde)
1236 struct iommu_dev_data *dev_data;
1237 struct iommu_cmd cmd;
1240 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1242 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1243 if (!domain->dev_iommu[i])
1247 * Devices of this domain are behind this IOMMU
1248 * We need a TLB flush
1250 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1253 list_for_each_entry(dev_data, &domain->dev_list, list) {
1255 if (!dev_data->ats.enabled)
1258 ret |= device_flush_iotlb(dev_data, address, size);
1264 static void domain_flush_pages(struct protection_domain *domain,
1265 u64 address, size_t size)
1267 __domain_flush_pages(domain, address, size, 0);
1270 /* Flush the whole IO/TLB for a given protection domain */
1271 static void domain_flush_tlb(struct protection_domain *domain)
1273 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1276 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1277 static void domain_flush_tlb_pde(struct protection_domain *domain)
1279 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1282 static void domain_flush_complete(struct protection_domain *domain)
1286 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1287 if (domain && !domain->dev_iommu[i])
1291 * Devices of this domain are behind this IOMMU
1292 * We need to wait for completion of all commands.
1294 iommu_completion_wait(amd_iommus[i]);
1300 * This function flushes the DTEs for all devices in domain
1302 static void domain_flush_devices(struct protection_domain *domain)
1304 struct iommu_dev_data *dev_data;
1306 list_for_each_entry(dev_data, &domain->dev_list, list)
1307 device_flush_dte(dev_data);
1310 /****************************************************************************
1312 * The functions below are used the create the page table mappings for
1313 * unity mapped regions.
1315 ****************************************************************************/
1317 static void free_page_list(struct page *freelist)
1319 while (freelist != NULL) {
1320 unsigned long p = (unsigned long)page_address(freelist);
1321 freelist = freelist->freelist;
1326 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1328 struct page *p = virt_to_page((void *)pt);
1330 p->freelist = freelist;
1335 #define DEFINE_FREE_PT_FN(LVL, FN) \
1336 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1344 for (i = 0; i < 512; ++i) { \
1345 /* PTE present? */ \
1346 if (!IOMMU_PTE_PRESENT(pt[i])) \
1350 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1351 PM_PTE_LEVEL(pt[i]) == 7) \
1354 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1355 freelist = FN(p, freelist); \
1358 return free_pt_page((unsigned long)pt, freelist); \
1361 DEFINE_FREE_PT_FN(l2, free_pt_page)
1362 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1363 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1364 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1365 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1367 static struct page *free_sub_pt(unsigned long root, int mode,
1368 struct page *freelist)
1371 case PAGE_MODE_NONE:
1372 case PAGE_MODE_7_LEVEL:
1374 case PAGE_MODE_1_LEVEL:
1375 freelist = free_pt_page(root, freelist);
1377 case PAGE_MODE_2_LEVEL:
1378 freelist = free_pt_l2(root, freelist);
1380 case PAGE_MODE_3_LEVEL:
1381 freelist = free_pt_l3(root, freelist);
1383 case PAGE_MODE_4_LEVEL:
1384 freelist = free_pt_l4(root, freelist);
1386 case PAGE_MODE_5_LEVEL:
1387 freelist = free_pt_l5(root, freelist);
1389 case PAGE_MODE_6_LEVEL:
1390 freelist = free_pt_l6(root, freelist);
1399 static void free_pagetable(struct protection_domain *domain)
1401 unsigned long root = (unsigned long)domain->pt_root;
1402 struct page *freelist = NULL;
1404 BUG_ON(domain->mode < PAGE_MODE_NONE ||
1405 domain->mode > PAGE_MODE_6_LEVEL);
1407 free_sub_pt(root, domain->mode, freelist);
1409 free_page_list(freelist);
1413 * This function is used to add another level to an IO page table. Adding
1414 * another level increases the size of the address space by 9 bits to a size up
1417 static bool increase_address_space(struct protection_domain *domain,
1422 if (domain->mode == PAGE_MODE_6_LEVEL)
1423 /* address space already 64 bit large */
1426 pte = (void *)get_zeroed_page(gfp);
1430 *pte = PM_LEVEL_PDE(domain->mode,
1431 iommu_virt_to_phys(domain->pt_root));
1432 domain->pt_root = pte;
1434 domain->updated = true;
1439 static u64 *alloc_pte(struct protection_domain *domain,
1440 unsigned long address,
1441 unsigned long page_size,
1448 BUG_ON(!is_power_of_2(page_size));
1450 while (address > PM_LEVEL_SIZE(domain->mode))
1451 increase_address_space(domain, gfp);
1453 level = domain->mode - 1;
1454 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1455 address = PAGE_SIZE_ALIGN(address, page_size);
1456 end_lvl = PAGE_SIZE_LEVEL(page_size);
1458 while (level > end_lvl) {
1463 pte_level = PM_PTE_LEVEL(__pte);
1465 if (!IOMMU_PTE_PRESENT(__pte) ||
1466 pte_level == PAGE_MODE_7_LEVEL) {
1467 page = (u64 *)get_zeroed_page(gfp);
1471 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1473 /* pte could have been changed somewhere. */
1474 if (cmpxchg64(pte, __pte, __npte) != __pte)
1475 free_page((unsigned long)page);
1476 else if (pte_level == PAGE_MODE_7_LEVEL)
1477 domain->updated = true;
1482 /* No level skipping support yet */
1483 if (pte_level != level)
1488 pte = IOMMU_PTE_PAGE(__pte);
1490 if (pte_page && level == end_lvl)
1493 pte = &pte[PM_LEVEL_INDEX(level, address)];
1500 * This function checks if there is a PTE for a given dma address. If
1501 * there is one, it returns the pointer to it.
1503 static u64 *fetch_pte(struct protection_domain *domain,
1504 unsigned long address,
1505 unsigned long *page_size)
1512 if (address > PM_LEVEL_SIZE(domain->mode))
1515 level = domain->mode - 1;
1516 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1517 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1522 if (!IOMMU_PTE_PRESENT(*pte))
1526 if (PM_PTE_LEVEL(*pte) == 7 ||
1527 PM_PTE_LEVEL(*pte) == 0)
1530 /* No level skipping support yet */
1531 if (PM_PTE_LEVEL(*pte) != level)
1536 /* Walk to the next level */
1537 pte = IOMMU_PTE_PAGE(*pte);
1538 pte = &pte[PM_LEVEL_INDEX(level, address)];
1539 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1542 if (PM_PTE_LEVEL(*pte) == 0x07) {
1543 unsigned long pte_mask;
1546 * If we have a series of large PTEs, make
1547 * sure to return a pointer to the first one.
1549 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1550 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1551 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1557 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1562 while (cmpxchg64(pte, pteval, 0) != pteval) {
1563 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1567 if (!IOMMU_PTE_PRESENT(pteval))
1570 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1571 mode = IOMMU_PTE_MODE(pteval);
1573 return free_sub_pt(pt, mode, freelist);
1577 * Generic mapping functions. It maps a physical address into a DMA
1578 * address space. It allocates the page table pages if necessary.
1579 * In the future it can be extended to a generic mapping function
1580 * supporting all features of AMD IOMMU page tables like level skipping
1581 * and full 64 bit address spaces.
1583 static int iommu_map_page(struct protection_domain *dom,
1584 unsigned long bus_addr,
1585 unsigned long phys_addr,
1586 unsigned long page_size,
1590 struct page *freelist = NULL;
1594 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1595 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1597 if (!(prot & IOMMU_PROT_MASK))
1600 count = PAGE_SIZE_PTE_COUNT(page_size);
1601 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1606 for (i = 0; i < count; ++i)
1607 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1609 if (freelist != NULL)
1610 dom->updated = true;
1613 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1614 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1616 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1618 if (prot & IOMMU_PROT_IR)
1619 __pte |= IOMMU_PTE_IR;
1620 if (prot & IOMMU_PROT_IW)
1621 __pte |= IOMMU_PTE_IW;
1623 for (i = 0; i < count; ++i)
1628 /* Everything flushed out, free pages now */
1629 free_page_list(freelist);
1634 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1635 unsigned long bus_addr,
1636 unsigned long page_size)
1638 unsigned long long unmapped;
1639 unsigned long unmap_size;
1642 BUG_ON(!is_power_of_2(page_size));
1646 while (unmapped < page_size) {
1648 pte = fetch_pte(dom, bus_addr, &unmap_size);
1653 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1654 for (i = 0; i < count; i++)
1658 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1659 unmapped += unmap_size;
1662 BUG_ON(unmapped && !is_power_of_2(unmapped));
1667 /****************************************************************************
1669 * The next functions belong to the address allocator for the dma_ops
1670 * interface functions.
1672 ****************************************************************************/
1675 static unsigned long dma_ops_alloc_iova(struct device *dev,
1676 struct dma_ops_domain *dma_dom,
1677 unsigned int pages, u64 dma_mask)
1679 unsigned long pfn = 0;
1681 pages = __roundup_pow_of_two(pages);
1683 if (dma_mask > DMA_BIT_MASK(32))
1684 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1685 IOVA_PFN(DMA_BIT_MASK(32)), false);
1688 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1689 IOVA_PFN(dma_mask), true);
1691 return (pfn << PAGE_SHIFT);
1694 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1695 unsigned long address,
1698 pages = __roundup_pow_of_two(pages);
1699 address >>= PAGE_SHIFT;
1701 free_iova_fast(&dma_dom->iovad, address, pages);
1704 /****************************************************************************
1706 * The next functions belong to the domain allocation. A domain is
1707 * allocated for every IOMMU as the default domain. If device isolation
1708 * is enabled, every device get its own domain. The most important thing
1709 * about domains is the page table mapping the DMA address space they
1712 ****************************************************************************/
1714 static u16 domain_id_alloc(void)
1718 spin_lock(&pd_bitmap_lock);
1719 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1721 if (id > 0 && id < MAX_DOMAIN_ID)
1722 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1725 spin_unlock(&pd_bitmap_lock);
1730 static void domain_id_free(int id)
1732 spin_lock(&pd_bitmap_lock);
1733 if (id > 0 && id < MAX_DOMAIN_ID)
1734 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1735 spin_unlock(&pd_bitmap_lock);
1738 static void free_gcr3_tbl_level1(u64 *tbl)
1743 for (i = 0; i < 512; ++i) {
1744 if (!(tbl[i] & GCR3_VALID))
1747 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1749 free_page((unsigned long)ptr);
1753 static void free_gcr3_tbl_level2(u64 *tbl)
1758 for (i = 0; i < 512; ++i) {
1759 if (!(tbl[i] & GCR3_VALID))
1762 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1764 free_gcr3_tbl_level1(ptr);
1768 static void free_gcr3_table(struct protection_domain *domain)
1770 if (domain->glx == 2)
1771 free_gcr3_tbl_level2(domain->gcr3_tbl);
1772 else if (domain->glx == 1)
1773 free_gcr3_tbl_level1(domain->gcr3_tbl);
1775 BUG_ON(domain->glx != 0);
1777 free_page((unsigned long)domain->gcr3_tbl);
1780 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1782 domain_flush_tlb(&dom->domain);
1783 domain_flush_complete(&dom->domain);
1786 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1788 struct dma_ops_domain *dom;
1790 dom = container_of(iovad, struct dma_ops_domain, iovad);
1792 dma_ops_domain_flush_tlb(dom);
1796 * Free a domain, only used if something went wrong in the
1797 * allocation path and we need to free an already allocated page table
1799 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1804 put_iova_domain(&dom->iovad);
1806 free_pagetable(&dom->domain);
1809 domain_id_free(dom->domain.id);
1815 * Allocates a new protection domain usable for the dma_ops functions.
1816 * It also initializes the page table and the address allocator data
1817 * structures required for the dma_ops interface
1819 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1821 struct dma_ops_domain *dma_dom;
1823 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1827 if (protection_domain_init(&dma_dom->domain))
1830 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1831 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1832 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1833 if (!dma_dom->domain.pt_root)
1836 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1838 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1841 /* Initialize reserved ranges */
1842 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1847 dma_ops_domain_free(dma_dom);
1853 * little helper function to check whether a given protection domain is a
1856 static bool dma_ops_domain(struct protection_domain *domain)
1858 return domain->flags & PD_DMA_OPS_MASK;
1861 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1867 if (domain->mode != PAGE_MODE_NONE)
1868 pte_root = iommu_virt_to_phys(domain->pt_root);
1870 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1871 << DEV_ENTRY_MODE_SHIFT;
1872 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1874 flags = amd_iommu_dev_table[devid].data[1];
1877 flags |= DTE_FLAG_IOTLB;
1880 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1882 if (iommu_feature(iommu, FEATURE_EPHSUP))
1883 pte_root |= 1ULL << DEV_ENTRY_PPR;
1886 if (domain->flags & PD_IOMMUV2_MASK) {
1887 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1888 u64 glx = domain->glx;
1891 pte_root |= DTE_FLAG_GV;
1892 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1894 /* First mask out possible old values for GCR3 table */
1895 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1898 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1901 /* Encode GCR3 table into DTE */
1902 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1905 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1908 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1912 flags &= ~DEV_DOMID_MASK;
1913 flags |= domain->id;
1915 amd_iommu_dev_table[devid].data[1] = flags;
1916 amd_iommu_dev_table[devid].data[0] = pte_root;
1919 static void clear_dte_entry(u16 devid)
1921 /* remove entry from the device table seen by the hardware */
1922 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1923 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1925 amd_iommu_apply_erratum_63(devid);
1928 static void do_attach(struct iommu_dev_data *dev_data,
1929 struct protection_domain *domain)
1931 struct amd_iommu *iommu;
1935 iommu = amd_iommu_rlookup_table[dev_data->devid];
1936 alias = dev_data->alias;
1937 ats = dev_data->ats.enabled;
1939 /* Update data structures */
1940 dev_data->domain = domain;
1941 list_add(&dev_data->list, &domain->dev_list);
1943 /* Do reference counting */
1944 domain->dev_iommu[iommu->index] += 1;
1945 domain->dev_cnt += 1;
1947 /* Update device table */
1948 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1949 if (alias != dev_data->devid)
1950 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1952 device_flush_dte(dev_data);
1955 static void do_detach(struct iommu_dev_data *dev_data)
1957 struct protection_domain *domain = dev_data->domain;
1958 struct amd_iommu *iommu;
1961 iommu = amd_iommu_rlookup_table[dev_data->devid];
1962 alias = dev_data->alias;
1964 /* Update data structures */
1965 dev_data->domain = NULL;
1966 list_del(&dev_data->list);
1967 clear_dte_entry(dev_data->devid);
1968 if (alias != dev_data->devid)
1969 clear_dte_entry(alias);
1971 /* Flush the DTE entry */
1972 device_flush_dte(dev_data);
1975 domain_flush_tlb_pde(domain);
1977 /* Wait for the flushes to finish */
1978 domain_flush_complete(domain);
1980 /* decrease reference counters - needs to happen after the flushes */
1981 domain->dev_iommu[iommu->index] -= 1;
1982 domain->dev_cnt -= 1;
1986 * If a device is not yet associated with a domain, this function makes the
1987 * device visible in the domain
1989 static int __attach_device(struct iommu_dev_data *dev_data,
1990 struct protection_domain *domain)
1995 spin_lock(&domain->lock);
1998 if (dev_data->domain != NULL)
2001 /* Attach alias group root */
2002 do_attach(dev_data, domain);
2009 spin_unlock(&domain->lock);
2015 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2017 pci_disable_ats(pdev);
2018 pci_disable_pri(pdev);
2019 pci_disable_pasid(pdev);
2022 /* FIXME: Change generic reset-function to do the same */
2023 static int pri_reset_while_enabled(struct pci_dev *pdev)
2028 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2032 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2033 control |= PCI_PRI_CTRL_RESET;
2034 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2039 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2044 /* FIXME: Hardcode number of outstanding requests for now */
2046 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2048 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2050 /* Only allow access to user-accessible pages */
2051 ret = pci_enable_pasid(pdev, 0);
2055 /* First reset the PRI state of the device */
2056 ret = pci_reset_pri(pdev);
2061 ret = pci_enable_pri(pdev, reqs);
2066 ret = pri_reset_while_enabled(pdev);
2071 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2078 pci_disable_pri(pdev);
2079 pci_disable_pasid(pdev);
2085 * If a device is not yet associated with a domain, this function makes the
2086 * device visible in the domain
2088 static int attach_device(struct device *dev,
2089 struct protection_domain *domain)
2091 struct pci_dev *pdev;
2092 struct iommu_dev_data *dev_data;
2093 unsigned long flags;
2096 dev_data = get_dev_data(dev);
2098 if (!dev_is_pci(dev))
2099 goto skip_ats_check;
2101 pdev = to_pci_dev(dev);
2102 if (domain->flags & PD_IOMMUV2_MASK) {
2103 if (!dev_data->passthrough)
2106 if (dev_data->iommu_v2) {
2107 if (pdev_iommuv2_enable(pdev) != 0)
2110 dev_data->ats.enabled = true;
2111 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2112 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2114 } else if (amd_iommu_iotlb_sup &&
2115 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2116 dev_data->ats.enabled = true;
2117 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2121 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2122 ret = __attach_device(dev_data, domain);
2123 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2126 * We might boot into a crash-kernel here. The crashed kernel
2127 * left the caches in the IOMMU dirty. So we have to flush
2128 * here to evict all dirty stuff.
2130 domain_flush_tlb_pde(domain);
2136 * Removes a device from a protection domain (unlocked)
2138 static void __detach_device(struct iommu_dev_data *dev_data)
2140 struct protection_domain *domain;
2142 domain = dev_data->domain;
2144 spin_lock(&domain->lock);
2146 do_detach(dev_data);
2148 spin_unlock(&domain->lock);
2152 * Removes a device from a protection domain (with devtable_lock held)
2154 static void detach_device(struct device *dev)
2156 struct protection_domain *domain;
2157 struct iommu_dev_data *dev_data;
2158 unsigned long flags;
2160 dev_data = get_dev_data(dev);
2161 domain = dev_data->domain;
2164 * First check if the device is still attached. It might already
2165 * be detached from its domain because the generic
2166 * iommu_detach_group code detached it and we try again here in
2167 * our alias handling.
2169 if (WARN_ON(!dev_data->domain))
2172 /* lock device table */
2173 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2174 __detach_device(dev_data);
2175 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2177 if (!dev_is_pci(dev))
2180 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2181 pdev_iommuv2_disable(to_pci_dev(dev));
2182 else if (dev_data->ats.enabled)
2183 pci_disable_ats(to_pci_dev(dev));
2185 dev_data->ats.enabled = false;
2188 static int amd_iommu_add_device(struct device *dev)
2190 struct iommu_dev_data *dev_data;
2191 struct iommu_domain *domain;
2192 struct amd_iommu *iommu;
2195 if (!check_device(dev) || get_dev_data(dev))
2198 devid = get_device_id(dev);
2202 iommu = amd_iommu_rlookup_table[devid];
2204 ret = iommu_init_device(dev);
2206 if (ret != -ENOTSUPP)
2207 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2209 iommu_ignore_device(dev);
2210 dev->dma_ops = NULL;
2213 init_iommu_group(dev);
2215 dev_data = get_dev_data(dev);
2219 if (iommu_pass_through || dev_data->iommu_v2)
2220 iommu_request_dm_for_dev(dev);
2222 /* Domains are initialized for this device - have a look what we ended up with */
2223 domain = iommu_get_domain_for_dev(dev);
2224 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2225 dev_data->passthrough = true;
2227 dev->dma_ops = &amd_iommu_dma_ops;
2230 iommu_completion_wait(iommu);
2235 static void amd_iommu_remove_device(struct device *dev)
2237 struct amd_iommu *iommu;
2240 if (!check_device(dev))
2243 devid = get_device_id(dev);
2247 iommu = amd_iommu_rlookup_table[devid];
2249 iommu_uninit_device(dev);
2250 iommu_completion_wait(iommu);
2253 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2255 if (dev_is_pci(dev))
2256 return pci_device_group(dev);
2258 return acpihid_device_group(dev);
2261 /*****************************************************************************
2263 * The next functions belong to the dma_ops mapping/unmapping code.
2265 *****************************************************************************/
2268 * In the dma_ops path we only have the struct device. This function
2269 * finds the corresponding IOMMU, the protection domain and the
2270 * requestor id for a given device.
2271 * If the device is not yet associated with a domain this is also done
2274 static struct protection_domain *get_domain(struct device *dev)
2276 struct protection_domain *domain;
2277 struct iommu_domain *io_domain;
2279 if (!check_device(dev))
2280 return ERR_PTR(-EINVAL);
2282 domain = get_dev_data(dev)->domain;
2283 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2284 get_dev_data(dev)->defer_attach = false;
2285 io_domain = iommu_get_domain_for_dev(dev);
2286 domain = to_pdomain(io_domain);
2287 attach_device(dev, domain);
2290 return ERR_PTR(-EBUSY);
2292 if (!dma_ops_domain(domain))
2293 return ERR_PTR(-EBUSY);
2298 static void update_device_table(struct protection_domain *domain)
2300 struct iommu_dev_data *dev_data;
2302 list_for_each_entry(dev_data, &domain->dev_list, list) {
2303 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2304 dev_data->iommu_v2);
2306 if (dev_data->devid == dev_data->alias)
2309 /* There is an alias, update device table entry for it */
2310 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2311 dev_data->iommu_v2);
2315 static void update_domain(struct protection_domain *domain)
2317 if (!domain->updated)
2320 update_device_table(domain);
2322 domain_flush_devices(domain);
2323 domain_flush_tlb_pde(domain);
2325 domain->updated = false;
2328 static int dir2prot(enum dma_data_direction direction)
2330 if (direction == DMA_TO_DEVICE)
2331 return IOMMU_PROT_IR;
2332 else if (direction == DMA_FROM_DEVICE)
2333 return IOMMU_PROT_IW;
2334 else if (direction == DMA_BIDIRECTIONAL)
2335 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2341 * This function contains common code for mapping of a physically
2342 * contiguous memory region into DMA address space. It is used by all
2343 * mapping functions provided with this IOMMU driver.
2344 * Must be called with the domain lock held.
2346 static dma_addr_t __map_single(struct device *dev,
2347 struct dma_ops_domain *dma_dom,
2350 enum dma_data_direction direction,
2353 dma_addr_t offset = paddr & ~PAGE_MASK;
2354 dma_addr_t address, start, ret;
2359 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2362 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2366 prot = dir2prot(direction);
2369 for (i = 0; i < pages; ++i) {
2370 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2371 PAGE_SIZE, prot, GFP_ATOMIC);
2380 if (unlikely(amd_iommu_np_cache)) {
2381 domain_flush_pages(&dma_dom->domain, address, size);
2382 domain_flush_complete(&dma_dom->domain);
2390 for (--i; i >= 0; --i) {
2392 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2395 domain_flush_tlb(&dma_dom->domain);
2396 domain_flush_complete(&dma_dom->domain);
2398 dma_ops_free_iova(dma_dom, address, pages);
2400 return DMA_MAPPING_ERROR;
2404 * Does the reverse of the __map_single function. Must be called with
2405 * the domain lock held too
2407 static void __unmap_single(struct dma_ops_domain *dma_dom,
2408 dma_addr_t dma_addr,
2412 dma_addr_t i, start;
2415 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2416 dma_addr &= PAGE_MASK;
2419 for (i = 0; i < pages; ++i) {
2420 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2424 if (amd_iommu_unmap_flush) {
2425 domain_flush_tlb(&dma_dom->domain);
2426 domain_flush_complete(&dma_dom->domain);
2427 dma_ops_free_iova(dma_dom, dma_addr, pages);
2429 pages = __roundup_pow_of_two(pages);
2430 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2435 * The exported map_single function for dma_ops.
2437 static dma_addr_t map_page(struct device *dev, struct page *page,
2438 unsigned long offset, size_t size,
2439 enum dma_data_direction dir,
2440 unsigned long attrs)
2442 phys_addr_t paddr = page_to_phys(page) + offset;
2443 struct protection_domain *domain;
2444 struct dma_ops_domain *dma_dom;
2447 domain = get_domain(dev);
2448 if (PTR_ERR(domain) == -EINVAL)
2449 return (dma_addr_t)paddr;
2450 else if (IS_ERR(domain))
2451 return DMA_MAPPING_ERROR;
2453 dma_mask = *dev->dma_mask;
2454 dma_dom = to_dma_ops_domain(domain);
2456 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2460 * The exported unmap_single function for dma_ops.
2462 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2463 enum dma_data_direction dir, unsigned long attrs)
2465 struct protection_domain *domain;
2466 struct dma_ops_domain *dma_dom;
2468 domain = get_domain(dev);
2472 dma_dom = to_dma_ops_domain(domain);
2474 __unmap_single(dma_dom, dma_addr, size, dir);
2477 static int sg_num_pages(struct device *dev,
2478 struct scatterlist *sglist,
2481 unsigned long mask, boundary_size;
2482 struct scatterlist *s;
2485 mask = dma_get_seg_boundary(dev);
2486 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2487 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2489 for_each_sg(sglist, s, nelems, i) {
2492 s->dma_address = npages << PAGE_SHIFT;
2493 p = npages % boundary_size;
2494 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2495 if (p + n > boundary_size)
2496 npages += boundary_size - p;
2504 * The exported map_sg function for dma_ops (handles scatter-gather
2507 static int map_sg(struct device *dev, struct scatterlist *sglist,
2508 int nelems, enum dma_data_direction direction,
2509 unsigned long attrs)
2511 int mapped_pages = 0, npages = 0, prot = 0, i;
2512 struct protection_domain *domain;
2513 struct dma_ops_domain *dma_dom;
2514 struct scatterlist *s;
2515 unsigned long address;
2519 domain = get_domain(dev);
2523 dma_dom = to_dma_ops_domain(domain);
2524 dma_mask = *dev->dma_mask;
2526 npages = sg_num_pages(dev, sglist, nelems);
2528 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2529 if (address == DMA_MAPPING_ERROR)
2532 prot = dir2prot(direction);
2534 /* Map all sg entries */
2535 for_each_sg(sglist, s, nelems, i) {
2536 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2538 for (j = 0; j < pages; ++j) {
2539 unsigned long bus_addr, phys_addr;
2541 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2542 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2543 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2551 /* Everything is mapped - write the right values into s->dma_address */
2552 for_each_sg(sglist, s, nelems, i) {
2554 * Add in the remaining piece of the scatter-gather offset that
2555 * was masked out when we were determining the physical address
2556 * via (sg_phys(s) & PAGE_MASK) earlier.
2558 s->dma_address += address + (s->offset & ~PAGE_MASK);
2559 s->dma_length = s->length;
2565 dev_err(dev, "IOMMU mapping error in map_sg (io-pages: %d reason: %d)\n",
2568 for_each_sg(sglist, s, nelems, i) {
2569 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2571 for (j = 0; j < pages; ++j) {
2572 unsigned long bus_addr;
2574 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2575 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2577 if (--mapped_pages == 0)
2583 free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages);
2590 * The exported map_sg function for dma_ops (handles scatter-gather
2593 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2594 int nelems, enum dma_data_direction dir,
2595 unsigned long attrs)
2597 struct protection_domain *domain;
2598 struct dma_ops_domain *dma_dom;
2599 unsigned long startaddr;
2602 domain = get_domain(dev);
2606 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2607 dma_dom = to_dma_ops_domain(domain);
2608 npages = sg_num_pages(dev, sglist, nelems);
2610 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2614 * The exported alloc_coherent function for dma_ops.
2616 static void *alloc_coherent(struct device *dev, size_t size,
2617 dma_addr_t *dma_addr, gfp_t flag,
2618 unsigned long attrs)
2620 u64 dma_mask = dev->coherent_dma_mask;
2621 struct protection_domain *domain;
2622 struct dma_ops_domain *dma_dom;
2625 domain = get_domain(dev);
2626 if (PTR_ERR(domain) == -EINVAL) {
2627 page = alloc_pages(flag, get_order(size));
2628 *dma_addr = page_to_phys(page);
2629 return page_address(page);
2630 } else if (IS_ERR(domain))
2633 dma_dom = to_dma_ops_domain(domain);
2634 size = PAGE_ALIGN(size);
2635 dma_mask = dev->coherent_dma_mask;
2636 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2639 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2641 if (!gfpflags_allow_blocking(flag))
2644 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2645 get_order(size), flag & __GFP_NOWARN);
2651 dma_mask = *dev->dma_mask;
2653 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2654 size, DMA_BIDIRECTIONAL, dma_mask);
2656 if (*dma_addr == DMA_MAPPING_ERROR)
2659 return page_address(page);
2663 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2664 __free_pages(page, get_order(size));
2670 * The exported free_coherent function for dma_ops.
2672 static void free_coherent(struct device *dev, size_t size,
2673 void *virt_addr, dma_addr_t dma_addr,
2674 unsigned long attrs)
2676 struct protection_domain *domain;
2677 struct dma_ops_domain *dma_dom;
2680 page = virt_to_page(virt_addr);
2681 size = PAGE_ALIGN(size);
2683 domain = get_domain(dev);
2687 dma_dom = to_dma_ops_domain(domain);
2689 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2692 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2693 __free_pages(page, get_order(size));
2697 * This function is called by the DMA layer to find out if we can handle a
2698 * particular device. It is part of the dma_ops.
2700 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2702 if (!dma_direct_supported(dev, mask))
2704 return check_device(dev);
2707 static const struct dma_map_ops amd_iommu_dma_ops = {
2708 .alloc = alloc_coherent,
2709 .free = free_coherent,
2710 .map_page = map_page,
2711 .unmap_page = unmap_page,
2713 .unmap_sg = unmap_sg,
2714 .dma_supported = amd_iommu_dma_supported,
2717 static int init_reserved_iova_ranges(void)
2719 struct pci_dev *pdev = NULL;
2722 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2724 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2725 &reserved_rbtree_key);
2727 /* MSI memory range */
2728 val = reserve_iova(&reserved_iova_ranges,
2729 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2731 pr_err("Reserving MSI range failed\n");
2735 /* HT memory range */
2736 val = reserve_iova(&reserved_iova_ranges,
2737 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2739 pr_err("Reserving HT range failed\n");
2744 * Memory used for PCI resources
2745 * FIXME: Check whether we can reserve the PCI-hole completly
2747 for_each_pci_dev(pdev) {
2750 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2751 struct resource *r = &pdev->resource[i];
2753 if (!(r->flags & IORESOURCE_MEM))
2756 val = reserve_iova(&reserved_iova_ranges,
2760 pci_err(pdev, "Reserve pci-resource range %pR failed\n", r);
2769 int __init amd_iommu_init_api(void)
2773 ret = iova_cache_get();
2777 ret = init_reserved_iova_ranges();
2781 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2784 #ifdef CONFIG_ARM_AMBA
2785 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2789 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2796 int __init amd_iommu_init_dma_ops(void)
2798 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2801 if (amd_iommu_unmap_flush)
2802 pr_info("IO/TLB flush on unmap enabled\n");
2804 pr_info("Lazy IO/TLB flushing enabled\n");
2810 /*****************************************************************************
2812 * The following functions belong to the exported interface of AMD IOMMU
2814 * This interface allows access to lower level functions of the IOMMU
2815 * like protection domain handling and assignement of devices to domains
2816 * which is not possible with the dma_ops interface.
2818 *****************************************************************************/
2820 static void cleanup_domain(struct protection_domain *domain)
2822 struct iommu_dev_data *entry;
2823 unsigned long flags;
2825 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2827 while (!list_empty(&domain->dev_list)) {
2828 entry = list_first_entry(&domain->dev_list,
2829 struct iommu_dev_data, list);
2830 BUG_ON(!entry->domain);
2831 __detach_device(entry);
2834 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2837 static void protection_domain_free(struct protection_domain *domain)
2843 domain_id_free(domain->id);
2848 static int protection_domain_init(struct protection_domain *domain)
2850 spin_lock_init(&domain->lock);
2851 mutex_init(&domain->api_lock);
2852 domain->id = domain_id_alloc();
2855 INIT_LIST_HEAD(&domain->dev_list);
2860 static struct protection_domain *protection_domain_alloc(void)
2862 struct protection_domain *domain;
2864 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2868 if (protection_domain_init(domain))
2879 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2881 struct protection_domain *pdomain;
2882 struct dma_ops_domain *dma_domain;
2885 case IOMMU_DOMAIN_UNMANAGED:
2886 pdomain = protection_domain_alloc();
2890 pdomain->mode = PAGE_MODE_3_LEVEL;
2891 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2892 if (!pdomain->pt_root) {
2893 protection_domain_free(pdomain);
2897 pdomain->domain.geometry.aperture_start = 0;
2898 pdomain->domain.geometry.aperture_end = ~0ULL;
2899 pdomain->domain.geometry.force_aperture = true;
2902 case IOMMU_DOMAIN_DMA:
2903 dma_domain = dma_ops_domain_alloc();
2905 pr_err("Failed to allocate\n");
2908 pdomain = &dma_domain->domain;
2910 case IOMMU_DOMAIN_IDENTITY:
2911 pdomain = protection_domain_alloc();
2915 pdomain->mode = PAGE_MODE_NONE;
2921 return &pdomain->domain;
2924 static void amd_iommu_domain_free(struct iommu_domain *dom)
2926 struct protection_domain *domain;
2927 struct dma_ops_domain *dma_dom;
2929 domain = to_pdomain(dom);
2931 if (domain->dev_cnt > 0)
2932 cleanup_domain(domain);
2934 BUG_ON(domain->dev_cnt != 0);
2939 switch (dom->type) {
2940 case IOMMU_DOMAIN_DMA:
2941 /* Now release the domain */
2942 dma_dom = to_dma_ops_domain(domain);
2943 dma_ops_domain_free(dma_dom);
2946 if (domain->mode != PAGE_MODE_NONE)
2947 free_pagetable(domain);
2949 if (domain->flags & PD_IOMMUV2_MASK)
2950 free_gcr3_table(domain);
2952 protection_domain_free(domain);
2957 static void amd_iommu_detach_device(struct iommu_domain *dom,
2960 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2961 struct amd_iommu *iommu;
2964 if (!check_device(dev))
2967 devid = get_device_id(dev);
2971 if (dev_data->domain != NULL)
2974 iommu = amd_iommu_rlookup_table[devid];
2978 #ifdef CONFIG_IRQ_REMAP
2979 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2980 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2981 dev_data->use_vapic = 0;
2984 iommu_completion_wait(iommu);
2987 static int amd_iommu_attach_device(struct iommu_domain *dom,
2990 struct protection_domain *domain = to_pdomain(dom);
2991 struct iommu_dev_data *dev_data;
2992 struct amd_iommu *iommu;
2995 if (!check_device(dev))
2998 dev_data = dev->archdata.iommu;
3000 iommu = amd_iommu_rlookup_table[dev_data->devid];
3004 if (dev_data->domain)
3007 ret = attach_device(dev, domain);
3009 #ifdef CONFIG_IRQ_REMAP
3010 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3011 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3012 dev_data->use_vapic = 1;
3014 dev_data->use_vapic = 0;
3018 iommu_completion_wait(iommu);
3023 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3024 phys_addr_t paddr, size_t page_size, int iommu_prot)
3026 struct protection_domain *domain = to_pdomain(dom);
3030 if (domain->mode == PAGE_MODE_NONE)
3033 if (iommu_prot & IOMMU_READ)
3034 prot |= IOMMU_PROT_IR;
3035 if (iommu_prot & IOMMU_WRITE)
3036 prot |= IOMMU_PROT_IW;
3038 mutex_lock(&domain->api_lock);
3039 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3040 mutex_unlock(&domain->api_lock);
3045 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3048 struct protection_domain *domain = to_pdomain(dom);
3051 if (domain->mode == PAGE_MODE_NONE)
3054 mutex_lock(&domain->api_lock);
3055 unmap_size = iommu_unmap_page(domain, iova, page_size);
3056 mutex_unlock(&domain->api_lock);
3061 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3064 struct protection_domain *domain = to_pdomain(dom);
3065 unsigned long offset_mask, pte_pgsize;
3068 if (domain->mode == PAGE_MODE_NONE)
3071 pte = fetch_pte(domain, iova, &pte_pgsize);
3073 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3076 offset_mask = pte_pgsize - 1;
3077 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3079 return (__pte & ~offset_mask) | (iova & offset_mask);
3082 static bool amd_iommu_capable(enum iommu_cap cap)
3085 case IOMMU_CAP_CACHE_COHERENCY:
3087 case IOMMU_CAP_INTR_REMAP:
3088 return (irq_remapping_enabled == 1);
3089 case IOMMU_CAP_NOEXEC:
3098 static void amd_iommu_get_resv_regions(struct device *dev,
3099 struct list_head *head)
3101 struct iommu_resv_region *region;
3102 struct unity_map_entry *entry;
3105 devid = get_device_id(dev);
3109 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3113 if (devid < entry->devid_start || devid > entry->devid_end)
3116 type = IOMMU_RESV_DIRECT;
3117 length = entry->address_end - entry->address_start;
3118 if (entry->prot & IOMMU_PROT_IR)
3120 if (entry->prot & IOMMU_PROT_IW)
3121 prot |= IOMMU_WRITE;
3122 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
3123 /* Exclusion range */
3124 type = IOMMU_RESV_RESERVED;
3126 region = iommu_alloc_resv_region(entry->address_start,
3127 length, prot, type);
3129 dev_err(dev, "Out of memory allocating dm-regions\n");
3132 list_add_tail(®ion->list, head);
3135 region = iommu_alloc_resv_region(MSI_RANGE_START,
3136 MSI_RANGE_END - MSI_RANGE_START + 1,
3140 list_add_tail(®ion->list, head);
3142 region = iommu_alloc_resv_region(HT_RANGE_START,
3143 HT_RANGE_END - HT_RANGE_START + 1,
3144 0, IOMMU_RESV_RESERVED);
3147 list_add_tail(®ion->list, head);
3150 static void amd_iommu_put_resv_regions(struct device *dev,
3151 struct list_head *head)
3153 struct iommu_resv_region *entry, *next;
3155 list_for_each_entry_safe(entry, next, head, list)
3159 static void amd_iommu_apply_resv_region(struct device *dev,
3160 struct iommu_domain *domain,
3161 struct iommu_resv_region *region)
3163 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3164 unsigned long start, end;
3166 start = IOVA_PFN(region->start);
3167 end = IOVA_PFN(region->start + region->length - 1);
3169 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3172 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3175 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3176 return dev_data->defer_attach;
3179 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3181 struct protection_domain *dom = to_pdomain(domain);
3183 domain_flush_tlb_pde(dom);
3184 domain_flush_complete(dom);
3187 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3188 unsigned long iova, size_t size)
3192 const struct iommu_ops amd_iommu_ops = {
3193 .capable = amd_iommu_capable,
3194 .domain_alloc = amd_iommu_domain_alloc,
3195 .domain_free = amd_iommu_domain_free,
3196 .attach_dev = amd_iommu_attach_device,
3197 .detach_dev = amd_iommu_detach_device,
3198 .map = amd_iommu_map,
3199 .unmap = amd_iommu_unmap,
3200 .iova_to_phys = amd_iommu_iova_to_phys,
3201 .add_device = amd_iommu_add_device,
3202 .remove_device = amd_iommu_remove_device,
3203 .device_group = amd_iommu_device_group,
3204 .get_resv_regions = amd_iommu_get_resv_regions,
3205 .put_resv_regions = amd_iommu_put_resv_regions,
3206 .apply_resv_region = amd_iommu_apply_resv_region,
3207 .is_attach_deferred = amd_iommu_is_attach_deferred,
3208 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3209 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3210 .iotlb_range_add = amd_iommu_iotlb_range_add,
3211 .iotlb_sync = amd_iommu_flush_iotlb_all,
3214 /*****************************************************************************
3216 * The next functions do a basic initialization of IOMMU for pass through
3219 * In passthrough mode the IOMMU is initialized and enabled but not used for
3220 * DMA-API translation.
3222 *****************************************************************************/
3224 /* IOMMUv2 specific functions */
3225 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3227 return atomic_notifier_chain_register(&ppr_notifier, nb);
3229 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3231 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3233 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3235 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3237 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3239 struct protection_domain *domain = to_pdomain(dom);
3240 unsigned long flags;
3242 spin_lock_irqsave(&domain->lock, flags);
3244 /* Update data structure */
3245 domain->mode = PAGE_MODE_NONE;
3246 domain->updated = true;
3248 /* Make changes visible to IOMMUs */
3249 update_domain(domain);
3251 /* Page-table is not visible to IOMMU anymore, so free it */
3252 free_pagetable(domain);
3254 spin_unlock_irqrestore(&domain->lock, flags);
3256 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3258 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3260 struct protection_domain *domain = to_pdomain(dom);
3261 unsigned long flags;
3264 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3267 /* Number of GCR3 table levels required */
3268 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3271 if (levels > amd_iommu_max_glx_val)
3274 spin_lock_irqsave(&domain->lock, flags);
3277 * Save us all sanity checks whether devices already in the
3278 * domain support IOMMUv2. Just force that the domain has no
3279 * devices attached when it is switched into IOMMUv2 mode.
3282 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3286 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3287 if (domain->gcr3_tbl == NULL)
3290 domain->glx = levels;
3291 domain->flags |= PD_IOMMUV2_MASK;
3292 domain->updated = true;
3294 update_domain(domain);
3299 spin_unlock_irqrestore(&domain->lock, flags);
3303 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3305 static int __flush_pasid(struct protection_domain *domain, int pasid,
3306 u64 address, bool size)
3308 struct iommu_dev_data *dev_data;
3309 struct iommu_cmd cmd;
3312 if (!(domain->flags & PD_IOMMUV2_MASK))
3315 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3318 * IOMMU TLB needs to be flushed before Device TLB to
3319 * prevent device TLB refill from IOMMU TLB
3321 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3322 if (domain->dev_iommu[i] == 0)
3325 ret = iommu_queue_command(amd_iommus[i], &cmd);
3330 /* Wait until IOMMU TLB flushes are complete */
3331 domain_flush_complete(domain);
3333 /* Now flush device TLBs */
3334 list_for_each_entry(dev_data, &domain->dev_list, list) {
3335 struct amd_iommu *iommu;
3339 There might be non-IOMMUv2 capable devices in an IOMMUv2
3342 if (!dev_data->ats.enabled)
3345 qdep = dev_data->ats.qdep;
3346 iommu = amd_iommu_rlookup_table[dev_data->devid];
3348 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3349 qdep, address, size);
3351 ret = iommu_queue_command(iommu, &cmd);
3356 /* Wait until all device TLBs are flushed */
3357 domain_flush_complete(domain);
3366 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3369 return __flush_pasid(domain, pasid, address, false);
3372 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3375 struct protection_domain *domain = to_pdomain(dom);
3376 unsigned long flags;
3379 spin_lock_irqsave(&domain->lock, flags);
3380 ret = __amd_iommu_flush_page(domain, pasid, address);
3381 spin_unlock_irqrestore(&domain->lock, flags);
3385 EXPORT_SYMBOL(amd_iommu_flush_page);
3387 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3389 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3393 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3395 struct protection_domain *domain = to_pdomain(dom);
3396 unsigned long flags;
3399 spin_lock_irqsave(&domain->lock, flags);
3400 ret = __amd_iommu_flush_tlb(domain, pasid);
3401 spin_unlock_irqrestore(&domain->lock, flags);
3405 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3407 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3414 index = (pasid >> (9 * level)) & 0x1ff;
3420 if (!(*pte & GCR3_VALID)) {
3424 root = (void *)get_zeroed_page(GFP_ATOMIC);
3428 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3431 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3439 static int __set_gcr3(struct protection_domain *domain, int pasid,
3444 if (domain->mode != PAGE_MODE_NONE)
3447 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3451 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3453 return __amd_iommu_flush_tlb(domain, pasid);
3456 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3460 if (domain->mode != PAGE_MODE_NONE)
3463 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3469 return __amd_iommu_flush_tlb(domain, pasid);
3472 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3475 struct protection_domain *domain = to_pdomain(dom);
3476 unsigned long flags;
3479 spin_lock_irqsave(&domain->lock, flags);
3480 ret = __set_gcr3(domain, pasid, cr3);
3481 spin_unlock_irqrestore(&domain->lock, flags);
3485 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3487 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3489 struct protection_domain *domain = to_pdomain(dom);
3490 unsigned long flags;
3493 spin_lock_irqsave(&domain->lock, flags);
3494 ret = __clear_gcr3(domain, pasid);
3495 spin_unlock_irqrestore(&domain->lock, flags);
3499 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3501 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3502 int status, int tag)
3504 struct iommu_dev_data *dev_data;
3505 struct amd_iommu *iommu;
3506 struct iommu_cmd cmd;
3508 dev_data = get_dev_data(&pdev->dev);
3509 iommu = amd_iommu_rlookup_table[dev_data->devid];
3511 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3512 tag, dev_data->pri_tlp);
3514 return iommu_queue_command(iommu, &cmd);
3516 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3518 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3520 struct protection_domain *pdomain;
3522 pdomain = get_domain(&pdev->dev);
3523 if (IS_ERR(pdomain))
3526 /* Only return IOMMUv2 domains */
3527 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3530 return &pdomain->domain;
3532 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3534 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3536 struct iommu_dev_data *dev_data;
3538 if (!amd_iommu_v2_supported())
3541 dev_data = get_dev_data(&pdev->dev);
3542 dev_data->errata |= (1 << erratum);
3544 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3546 int amd_iommu_device_info(struct pci_dev *pdev,
3547 struct amd_iommu_device_info *info)
3552 if (pdev == NULL || info == NULL)
3555 if (!amd_iommu_v2_supported())
3558 memset(info, 0, sizeof(*info));
3560 if (!pci_ats_disabled()) {
3561 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3563 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3566 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3568 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3570 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3574 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3575 max_pasids = min(max_pasids, (1 << 20));
3577 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3578 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3580 features = pci_pasid_features(pdev);
3581 if (features & PCI_PASID_CAP_EXEC)
3582 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3583 if (features & PCI_PASID_CAP_PRIV)
3584 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3589 EXPORT_SYMBOL(amd_iommu_device_info);
3591 #ifdef CONFIG_IRQ_REMAP
3593 /*****************************************************************************
3595 * Interrupt Remapping Implementation
3597 *****************************************************************************/
3599 static struct irq_chip amd_ir_chip;
3600 static DEFINE_SPINLOCK(iommu_table_lock);
3602 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3606 dte = amd_iommu_dev_table[devid].data[2];
3607 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3608 dte |= iommu_virt_to_phys(table->table);
3609 dte |= DTE_IRQ_REMAP_INTCTL;
3610 dte |= DTE_IRQ_TABLE_LEN;
3611 dte |= DTE_IRQ_REMAP_ENABLE;
3613 amd_iommu_dev_table[devid].data[2] = dte;
3616 static struct irq_remap_table *get_irq_table(u16 devid)
3618 struct irq_remap_table *table;
3620 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3621 "%s: no iommu for devid %x\n", __func__, devid))
3624 table = irq_lookup_table[devid];
3625 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3631 static struct irq_remap_table *__alloc_irq_table(void)
3633 struct irq_remap_table *table;
3635 table = kzalloc(sizeof(*table), GFP_KERNEL);
3639 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3640 if (!table->table) {
3644 raw_spin_lock_init(&table->lock);
3646 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3647 memset(table->table, 0,
3648 MAX_IRQS_PER_TABLE * sizeof(u32));
3650 memset(table->table, 0,
3651 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3655 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3656 struct irq_remap_table *table)
3658 irq_lookup_table[devid] = table;
3659 set_dte_irq_entry(devid, table);
3660 iommu_flush_dte(iommu, devid);
3663 static struct irq_remap_table *alloc_irq_table(u16 devid)
3665 struct irq_remap_table *table = NULL;
3666 struct irq_remap_table *new_table = NULL;
3667 struct amd_iommu *iommu;
3668 unsigned long flags;
3671 spin_lock_irqsave(&iommu_table_lock, flags);
3673 iommu = amd_iommu_rlookup_table[devid];
3677 table = irq_lookup_table[devid];
3681 alias = amd_iommu_alias_table[devid];
3682 table = irq_lookup_table[alias];
3684 set_remap_table_entry(iommu, devid, table);
3687 spin_unlock_irqrestore(&iommu_table_lock, flags);
3689 /* Nothing there yet, allocate new irq remapping table */
3690 new_table = __alloc_irq_table();
3694 spin_lock_irqsave(&iommu_table_lock, flags);
3696 table = irq_lookup_table[devid];
3700 table = irq_lookup_table[alias];
3702 set_remap_table_entry(iommu, devid, table);
3709 set_remap_table_entry(iommu, devid, table);
3711 set_remap_table_entry(iommu, alias, table);
3714 iommu_completion_wait(iommu);
3717 spin_unlock_irqrestore(&iommu_table_lock, flags);
3720 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3726 static int alloc_irq_index(u16 devid, int count, bool align)
3728 struct irq_remap_table *table;
3729 int index, c, alignment = 1;
3730 unsigned long flags;
3731 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3736 table = alloc_irq_table(devid);
3741 alignment = roundup_pow_of_two(count);
3743 raw_spin_lock_irqsave(&table->lock, flags);
3745 /* Scan table for free entries */
3746 for (index = ALIGN(table->min_index, alignment), c = 0;
3747 index < MAX_IRQS_PER_TABLE;) {
3748 if (!iommu->irte_ops->is_allocated(table, index)) {
3752 index = ALIGN(index + 1, alignment);
3758 iommu->irte_ops->set_allocated(table, index - c + 1);
3770 raw_spin_unlock_irqrestore(&table->lock, flags);
3775 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3776 struct amd_ir_data *data)
3778 struct irq_remap_table *table;
3779 struct amd_iommu *iommu;
3780 unsigned long flags;
3781 struct irte_ga *entry;
3783 iommu = amd_iommu_rlookup_table[devid];
3787 table = get_irq_table(devid);
3791 raw_spin_lock_irqsave(&table->lock, flags);
3793 entry = (struct irte_ga *)table->table;
3794 entry = &entry[index];
3795 entry->lo.fields_remap.valid = 0;
3796 entry->hi.val = irte->hi.val;
3797 entry->lo.val = irte->lo.val;
3798 entry->lo.fields_remap.valid = 1;
3802 raw_spin_unlock_irqrestore(&table->lock, flags);
3804 iommu_flush_irt(iommu, devid);
3805 iommu_completion_wait(iommu);
3810 static int modify_irte(u16 devid, int index, union irte *irte)
3812 struct irq_remap_table *table;
3813 struct amd_iommu *iommu;
3814 unsigned long flags;
3816 iommu = amd_iommu_rlookup_table[devid];
3820 table = get_irq_table(devid);
3824 raw_spin_lock_irqsave(&table->lock, flags);
3825 table->table[index] = irte->val;
3826 raw_spin_unlock_irqrestore(&table->lock, flags);
3828 iommu_flush_irt(iommu, devid);
3829 iommu_completion_wait(iommu);
3834 static void free_irte(u16 devid, int index)
3836 struct irq_remap_table *table;
3837 struct amd_iommu *iommu;
3838 unsigned long flags;
3840 iommu = amd_iommu_rlookup_table[devid];
3844 table = get_irq_table(devid);
3848 raw_spin_lock_irqsave(&table->lock, flags);
3849 iommu->irte_ops->clear_allocated(table, index);
3850 raw_spin_unlock_irqrestore(&table->lock, flags);
3852 iommu_flush_irt(iommu, devid);
3853 iommu_completion_wait(iommu);
3856 static void irte_prepare(void *entry,
3857 u32 delivery_mode, u32 dest_mode,
3858 u8 vector, u32 dest_apicid, int devid)
3860 union irte *irte = (union irte *) entry;
3863 irte->fields.vector = vector;
3864 irte->fields.int_type = delivery_mode;
3865 irte->fields.destination = dest_apicid;
3866 irte->fields.dm = dest_mode;
3867 irte->fields.valid = 1;
3870 static void irte_ga_prepare(void *entry,
3871 u32 delivery_mode, u32 dest_mode,
3872 u8 vector, u32 dest_apicid, int devid)
3874 struct irte_ga *irte = (struct irte_ga *) entry;
3878 irte->lo.fields_remap.int_type = delivery_mode;
3879 irte->lo.fields_remap.dm = dest_mode;
3880 irte->hi.fields.vector = vector;
3881 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3882 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3883 irte->lo.fields_remap.valid = 1;
3886 static void irte_activate(void *entry, u16 devid, u16 index)
3888 union irte *irte = (union irte *) entry;
3890 irte->fields.valid = 1;
3891 modify_irte(devid, index, irte);
3894 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3896 struct irte_ga *irte = (struct irte_ga *) entry;
3898 irte->lo.fields_remap.valid = 1;
3899 modify_irte_ga(devid, index, irte, NULL);
3902 static void irte_deactivate(void *entry, u16 devid, u16 index)
3904 union irte *irte = (union irte *) entry;
3906 irte->fields.valid = 0;
3907 modify_irte(devid, index, irte);
3910 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3912 struct irte_ga *irte = (struct irte_ga *) entry;
3914 irte->lo.fields_remap.valid = 0;
3915 modify_irte_ga(devid, index, irte, NULL);
3918 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3919 u8 vector, u32 dest_apicid)
3921 union irte *irte = (union irte *) entry;
3923 irte->fields.vector = vector;
3924 irte->fields.destination = dest_apicid;
3925 modify_irte(devid, index, irte);
3928 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3929 u8 vector, u32 dest_apicid)
3931 struct irte_ga *irte = (struct irte_ga *) entry;
3933 if (!irte->lo.fields_remap.guest_mode) {
3934 irte->hi.fields.vector = vector;
3935 irte->lo.fields_remap.destination =
3936 APICID_TO_IRTE_DEST_LO(dest_apicid);
3937 irte->hi.fields.destination =
3938 APICID_TO_IRTE_DEST_HI(dest_apicid);
3939 modify_irte_ga(devid, index, irte, NULL);
3943 #define IRTE_ALLOCATED (~1U)
3944 static void irte_set_allocated(struct irq_remap_table *table, int index)
3946 table->table[index] = IRTE_ALLOCATED;
3949 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3951 struct irte_ga *ptr = (struct irte_ga *)table->table;
3952 struct irte_ga *irte = &ptr[index];
3954 memset(&irte->lo.val, 0, sizeof(u64));
3955 memset(&irte->hi.val, 0, sizeof(u64));
3956 irte->hi.fields.vector = 0xff;
3959 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3961 union irte *ptr = (union irte *)table->table;
3962 union irte *irte = &ptr[index];
3964 return irte->val != 0;
3967 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3969 struct irte_ga *ptr = (struct irte_ga *)table->table;
3970 struct irte_ga *irte = &ptr[index];
3972 return irte->hi.fields.vector != 0;
3975 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3977 table->table[index] = 0;
3980 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3982 struct irte_ga *ptr = (struct irte_ga *)table->table;
3983 struct irte_ga *irte = &ptr[index];
3985 memset(&irte->lo.val, 0, sizeof(u64));
3986 memset(&irte->hi.val, 0, sizeof(u64));
3989 static int get_devid(struct irq_alloc_info *info)
3993 switch (info->type) {
3994 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3995 devid = get_ioapic_devid(info->ioapic_id);
3997 case X86_IRQ_ALLOC_TYPE_HPET:
3998 devid = get_hpet_devid(info->hpet_id);
4000 case X86_IRQ_ALLOC_TYPE_MSI:
4001 case X86_IRQ_ALLOC_TYPE_MSIX:
4002 devid = get_device_id(&info->msi_dev->dev);
4012 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4014 struct amd_iommu *iommu;
4020 devid = get_devid(info);
4022 iommu = amd_iommu_rlookup_table[devid];
4024 return iommu->ir_domain;
4030 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4032 struct amd_iommu *iommu;
4038 switch (info->type) {
4039 case X86_IRQ_ALLOC_TYPE_MSI:
4040 case X86_IRQ_ALLOC_TYPE_MSIX:
4041 devid = get_device_id(&info->msi_dev->dev);
4045 iommu = amd_iommu_rlookup_table[devid];
4047 return iommu->msi_domain;
4056 struct irq_remap_ops amd_iommu_irq_ops = {
4057 .prepare = amd_iommu_prepare,
4058 .enable = amd_iommu_enable,
4059 .disable = amd_iommu_disable,
4060 .reenable = amd_iommu_reenable,
4061 .enable_faulting = amd_iommu_enable_faulting,
4062 .get_ir_irq_domain = get_ir_irq_domain,
4063 .get_irq_domain = get_irq_domain,
4066 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4067 struct irq_cfg *irq_cfg,
4068 struct irq_alloc_info *info,
4069 int devid, int index, int sub_handle)
4071 struct irq_2_irte *irte_info = &data->irq_2_irte;
4072 struct msi_msg *msg = &data->msi_entry;
4073 struct IO_APIC_route_entry *entry;
4074 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4079 data->irq_2_irte.devid = devid;
4080 data->irq_2_irte.index = index + sub_handle;
4081 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4082 apic->irq_dest_mode, irq_cfg->vector,
4083 irq_cfg->dest_apicid, devid);
4085 switch (info->type) {
4086 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4087 /* Setup IOAPIC entry */
4088 entry = info->ioapic_entry;
4089 info->ioapic_entry = NULL;
4090 memset(entry, 0, sizeof(*entry));
4091 entry->vector = index;
4093 entry->trigger = info->ioapic_trigger;
4094 entry->polarity = info->ioapic_polarity;
4095 /* Mask level triggered irqs. */
4096 if (info->ioapic_trigger)
4100 case X86_IRQ_ALLOC_TYPE_HPET:
4101 case X86_IRQ_ALLOC_TYPE_MSI:
4102 case X86_IRQ_ALLOC_TYPE_MSIX:
4103 msg->address_hi = MSI_ADDR_BASE_HI;
4104 msg->address_lo = MSI_ADDR_BASE_LO;
4105 msg->data = irte_info->index;
4114 struct amd_irte_ops irte_32_ops = {
4115 .prepare = irte_prepare,
4116 .activate = irte_activate,
4117 .deactivate = irte_deactivate,
4118 .set_affinity = irte_set_affinity,
4119 .set_allocated = irte_set_allocated,
4120 .is_allocated = irte_is_allocated,
4121 .clear_allocated = irte_clear_allocated,
4124 struct amd_irte_ops irte_128_ops = {
4125 .prepare = irte_ga_prepare,
4126 .activate = irte_ga_activate,
4127 .deactivate = irte_ga_deactivate,
4128 .set_affinity = irte_ga_set_affinity,
4129 .set_allocated = irte_ga_set_allocated,
4130 .is_allocated = irte_ga_is_allocated,
4131 .clear_allocated = irte_ga_clear_allocated,
4134 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4135 unsigned int nr_irqs, void *arg)
4137 struct irq_alloc_info *info = arg;
4138 struct irq_data *irq_data;
4139 struct amd_ir_data *data = NULL;
4140 struct irq_cfg *cfg;
4146 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4147 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4151 * With IRQ remapping enabled, don't need contiguous CPU vectors
4152 * to support multiple MSI interrupts.
4154 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4155 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4157 devid = get_devid(info);
4161 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4165 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4166 struct irq_remap_table *table;
4167 struct amd_iommu *iommu;
4169 table = alloc_irq_table(devid);
4171 if (!table->min_index) {
4173 * Keep the first 32 indexes free for IOAPIC
4176 table->min_index = 32;
4177 iommu = amd_iommu_rlookup_table[devid];
4178 for (i = 0; i < 32; ++i)
4179 iommu->irte_ops->set_allocated(table, i);
4181 WARN_ON(table->min_index != 32);
4182 index = info->ioapic_pin;
4187 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4189 index = alloc_irq_index(devid, nr_irqs, align);
4192 pr_warn("Failed to allocate IRTE\n");
4194 goto out_free_parent;
4197 for (i = 0; i < nr_irqs; i++) {
4198 irq_data = irq_domain_get_irq_data(domain, virq + i);
4199 cfg = irqd_cfg(irq_data);
4200 if (!irq_data || !cfg) {
4206 data = kzalloc(sizeof(*data), GFP_KERNEL);
4210 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4211 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4213 data->entry = kzalloc(sizeof(struct irte_ga),
4220 irq_data->hwirq = (devid << 16) + i;
4221 irq_data->chip_data = data;
4222 irq_data->chip = &amd_ir_chip;
4223 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4224 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4230 for (i--; i >= 0; i--) {
4231 irq_data = irq_domain_get_irq_data(domain, virq + i);
4233 kfree(irq_data->chip_data);
4235 for (i = 0; i < nr_irqs; i++)
4236 free_irte(devid, index + i);
4238 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4242 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4243 unsigned int nr_irqs)
4245 struct irq_2_irte *irte_info;
4246 struct irq_data *irq_data;
4247 struct amd_ir_data *data;
4250 for (i = 0; i < nr_irqs; i++) {
4251 irq_data = irq_domain_get_irq_data(domain, virq + i);
4252 if (irq_data && irq_data->chip_data) {
4253 data = irq_data->chip_data;
4254 irte_info = &data->irq_2_irte;
4255 free_irte(irte_info->devid, irte_info->index);
4260 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4263 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4264 struct amd_ir_data *ir_data,
4265 struct irq_2_irte *irte_info,
4266 struct irq_cfg *cfg);
4268 static int irq_remapping_activate(struct irq_domain *domain,
4269 struct irq_data *irq_data, bool reserve)
4271 struct amd_ir_data *data = irq_data->chip_data;
4272 struct irq_2_irte *irte_info = &data->irq_2_irte;
4273 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4274 struct irq_cfg *cfg = irqd_cfg(irq_data);
4279 iommu->irte_ops->activate(data->entry, irte_info->devid,
4281 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4285 static void irq_remapping_deactivate(struct irq_domain *domain,
4286 struct irq_data *irq_data)
4288 struct amd_ir_data *data = irq_data->chip_data;
4289 struct irq_2_irte *irte_info = &data->irq_2_irte;
4290 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4293 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4297 static const struct irq_domain_ops amd_ir_domain_ops = {
4298 .alloc = irq_remapping_alloc,
4299 .free = irq_remapping_free,
4300 .activate = irq_remapping_activate,
4301 .deactivate = irq_remapping_deactivate,
4304 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4306 struct amd_iommu *iommu;
4307 struct amd_iommu_pi_data *pi_data = vcpu_info;
4308 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4309 struct amd_ir_data *ir_data = data->chip_data;
4310 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4311 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4312 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4315 * This device has never been set up for guest mode.
4316 * we should not modify the IRTE
4318 if (!dev_data || !dev_data->use_vapic)
4321 pi_data->ir_data = ir_data;
4324 * SVM tries to set up for VAPIC mode, but we are in
4325 * legacy mode. So, we force legacy mode instead.
4327 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4328 pr_debug("%s: Fall back to using intr legacy remap\n",
4330 pi_data->is_guest_mode = false;
4333 iommu = amd_iommu_rlookup_table[irte_info->devid];
4337 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4338 if (pi_data->is_guest_mode) {
4340 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4341 irte->hi.fields.vector = vcpu_pi_info->vector;
4342 irte->lo.fields_vapic.ga_log_intr = 1;
4343 irte->lo.fields_vapic.guest_mode = 1;
4344 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4346 ir_data->cached_ga_tag = pi_data->ga_tag;
4349 struct irq_cfg *cfg = irqd_cfg(data);
4353 irte->hi.fields.vector = cfg->vector;
4354 irte->lo.fields_remap.guest_mode = 0;
4355 irte->lo.fields_remap.destination =
4356 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4357 irte->hi.fields.destination =
4358 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4359 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4360 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4363 * This communicates the ga_tag back to the caller
4364 * so that it can do all the necessary clean up.
4366 ir_data->cached_ga_tag = 0;
4369 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4373 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4374 struct amd_ir_data *ir_data,
4375 struct irq_2_irte *irte_info,
4376 struct irq_cfg *cfg)
4380 * Atomically updates the IRTE with the new destination, vector
4381 * and flushes the interrupt entry cache.
4383 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4384 irte_info->index, cfg->vector,
4388 static int amd_ir_set_affinity(struct irq_data *data,
4389 const struct cpumask *mask, bool force)
4391 struct amd_ir_data *ir_data = data->chip_data;
4392 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4393 struct irq_cfg *cfg = irqd_cfg(data);
4394 struct irq_data *parent = data->parent_data;
4395 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4401 ret = parent->chip->irq_set_affinity(parent, mask, force);
4402 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4405 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4407 * After this point, all the interrupts will start arriving
4408 * at the new destination. So, time to cleanup the previous
4409 * vector allocation.
4411 send_cleanup_vector(cfg);
4413 return IRQ_SET_MASK_OK_DONE;
4416 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4418 struct amd_ir_data *ir_data = irq_data->chip_data;
4420 *msg = ir_data->msi_entry;
4423 static struct irq_chip amd_ir_chip = {
4425 .irq_ack = apic_ack_irq,
4426 .irq_set_affinity = amd_ir_set_affinity,
4427 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4428 .irq_compose_msi_msg = ir_compose_msi_msg,
4431 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4433 struct fwnode_handle *fn;
4435 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4438 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4439 irq_domain_free_fwnode(fn);
4440 if (!iommu->ir_domain)
4443 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4444 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4450 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4452 unsigned long flags;
4453 struct amd_iommu *iommu;
4454 struct irq_remap_table *table;
4455 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4456 int devid = ir_data->irq_2_irte.devid;
4457 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4458 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4460 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4461 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4464 iommu = amd_iommu_rlookup_table[devid];
4468 table = get_irq_table(devid);
4472 raw_spin_lock_irqsave(&table->lock, flags);
4474 if (ref->lo.fields_vapic.guest_mode) {
4476 ref->lo.fields_vapic.destination =
4477 APICID_TO_IRTE_DEST_LO(cpu);
4478 ref->hi.fields.destination =
4479 APICID_TO_IRTE_DEST_HI(cpu);
4481 ref->lo.fields_vapic.is_run = is_run;
4485 raw_spin_unlock_irqrestore(&table->lock, flags);
4487 iommu_flush_irt(iommu, devid);
4488 iommu_completion_wait(iommu);
4491 EXPORT_SYMBOL(amd_iommu_update_ga);