1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-direct.h>
23 #include <linux/iommu-helper.h>
24 #include <linux/iommu.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/dma-contiguous.h>
32 #include <linux/irqdomain.h>
33 #include <linux/percpu.h>
34 #include <linux/iova.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/io_apic.h>
38 #include <asm/hw_irq.h>
39 #include <asm/msidef.h>
40 #include <asm/proto.h>
41 #include <asm/iommu.h>
45 #include "amd_iommu_proto.h"
46 #include "amd_iommu_types.h"
47 #include "irq_remapping.h"
49 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
51 #define LOOP_TIMEOUT 100000
53 /* IO virtual address start page frame number */
54 #define IOVA_START_PFN (1)
55 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
57 /* Reserved IOVA ranges */
58 #define MSI_RANGE_START (0xfee00000)
59 #define MSI_RANGE_END (0xfeefffff)
60 #define HT_RANGE_START (0xfd00000000ULL)
61 #define HT_RANGE_END (0xffffffffffULL)
64 * This bitmap is used to advertise the page sizes our hardware support
65 * to the IOMMU core, which will then use this information to split
66 * physically contiguous memory regions it is mapping into page sizes
69 * 512GB Pages are not supported due to a hardware bug
71 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
73 static DEFINE_SPINLOCK(pd_bitmap_lock);
75 /* List of all available dev_data structures */
76 static LLIST_HEAD(dev_data_list);
78 LIST_HEAD(ioapic_map);
80 LIST_HEAD(acpihid_map);
83 * Domain for untranslated devices - only allocated
84 * if iommu=pt passed on kernel cmd line.
86 const struct iommu_ops amd_iommu_ops;
88 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
89 int amd_iommu_max_glx_val = -1;
91 static const struct dma_map_ops amd_iommu_dma_ops;
94 * general struct to manage commands send to an IOMMU
100 struct kmem_cache *amd_iommu_irq_cache;
102 static void update_domain(struct protection_domain *domain);
103 static int protection_domain_init(struct protection_domain *domain);
104 static void detach_device(struct device *dev);
105 static void iova_domain_flush_tlb(struct iova_domain *iovad);
108 * Data container for a dma_ops specific protection domain
110 struct dma_ops_domain {
111 /* generic protection domain information */
112 struct protection_domain domain;
115 struct iova_domain iovad;
118 static struct iova_domain reserved_iova_ranges;
119 static struct lock_class_key reserved_rbtree_key;
121 /****************************************************************************
125 ****************************************************************************/
127 static inline int match_hid_uid(struct device *dev,
128 struct acpihid_map_entry *entry)
130 struct acpi_device *adev = ACPI_COMPANION(dev);
131 const char *hid, *uid;
136 hid = acpi_device_hid(adev);
137 uid = acpi_device_uid(adev);
143 return strcmp(hid, entry->hid);
146 return strcmp(hid, entry->hid);
148 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
151 static inline u16 get_pci_device_id(struct device *dev)
153 struct pci_dev *pdev = to_pci_dev(dev);
155 return pci_dev_id(pdev);
158 static inline int get_acpihid_device_id(struct device *dev,
159 struct acpihid_map_entry **entry)
161 struct acpihid_map_entry *p;
163 list_for_each_entry(p, &acpihid_map, list) {
164 if (!match_hid_uid(dev, p)) {
173 static inline int get_device_id(struct device *dev)
178 devid = get_pci_device_id(dev);
180 devid = get_acpihid_device_id(dev, NULL);
185 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
187 return container_of(dom, struct protection_domain, domain);
190 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
192 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
193 return container_of(domain, struct dma_ops_domain, domain);
196 static struct iommu_dev_data *alloc_dev_data(u16 devid)
198 struct iommu_dev_data *dev_data;
200 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
204 spin_lock_init(&dev_data->lock);
205 dev_data->devid = devid;
206 ratelimit_default_init(&dev_data->rs);
208 llist_add(&dev_data->dev_data_list, &dev_data_list);
212 static struct iommu_dev_data *search_dev_data(u16 devid)
214 struct iommu_dev_data *dev_data;
215 struct llist_node *node;
217 if (llist_empty(&dev_data_list))
220 node = dev_data_list.first;
221 llist_for_each_entry(dev_data, node, dev_data_list) {
222 if (dev_data->devid == devid)
229 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
231 *(u16 *)data = alias;
235 static u16 get_alias(struct device *dev)
237 struct pci_dev *pdev = to_pci_dev(dev);
238 u16 devid, ivrs_alias, pci_alias;
240 /* The callers make sure that get_device_id() does not fail here */
241 devid = get_device_id(dev);
243 /* For ACPI HID devices, we simply return the devid as such */
244 if (!dev_is_pci(dev))
247 ivrs_alias = amd_iommu_alias_table[devid];
249 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
251 if (ivrs_alias == pci_alias)
257 * The IVRS is fairly reliable in telling us about aliases, but it
258 * can't know about every screwy device. If we don't have an IVRS
259 * reported alias, use the PCI reported alias. In that case we may
260 * still need to initialize the rlookup and dev_table entries if the
261 * alias is to a non-existent device.
263 if (ivrs_alias == devid) {
264 if (!amd_iommu_rlookup_table[pci_alias]) {
265 amd_iommu_rlookup_table[pci_alias] =
266 amd_iommu_rlookup_table[devid];
267 memcpy(amd_iommu_dev_table[pci_alias].data,
268 amd_iommu_dev_table[devid].data,
269 sizeof(amd_iommu_dev_table[pci_alias].data));
275 pci_info(pdev, "Using IVRS reported alias %02x:%02x.%d "
276 "for device [%04x:%04x], kernel reported alias "
277 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
278 PCI_FUNC(ivrs_alias), pdev->vendor, pdev->device,
279 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
280 PCI_FUNC(pci_alias));
283 * If we don't have a PCI DMA alias and the IVRS alias is on the same
284 * bus, then the IVRS table may know about a quirk that we don't.
286 if (pci_alias == devid &&
287 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
288 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
289 pci_info(pdev, "Added PCI DMA alias %02x.%d\n",
290 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias));
296 static struct iommu_dev_data *find_dev_data(u16 devid)
298 struct iommu_dev_data *dev_data;
299 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
301 dev_data = search_dev_data(devid);
303 if (dev_data == NULL) {
304 dev_data = alloc_dev_data(devid);
308 if (translation_pre_enabled(iommu))
309 dev_data->defer_attach = true;
315 struct iommu_dev_data *get_dev_data(struct device *dev)
317 return dev->archdata.iommu;
319 EXPORT_SYMBOL(get_dev_data);
322 * Find or create an IOMMU group for a acpihid device.
324 static struct iommu_group *acpihid_device_group(struct device *dev)
326 struct acpihid_map_entry *p, *entry = NULL;
329 devid = get_acpihid_device_id(dev, &entry);
331 return ERR_PTR(devid);
333 list_for_each_entry(p, &acpihid_map, list) {
334 if ((devid == p->devid) && p->group)
335 entry->group = p->group;
339 entry->group = generic_device_group(dev);
341 iommu_group_ref_get(entry->group);
346 static bool pci_iommuv2_capable(struct pci_dev *pdev)
348 static const int caps[] = {
351 PCI_EXT_CAP_ID_PASID,
355 if (pci_ats_disabled())
358 for (i = 0; i < 3; ++i) {
359 pos = pci_find_ext_capability(pdev, caps[i]);
367 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
369 struct iommu_dev_data *dev_data;
371 dev_data = get_dev_data(&pdev->dev);
373 return dev_data->errata & (1 << erratum) ? true : false;
377 * This function checks if the driver got a valid device from the caller to
378 * avoid dereferencing invalid pointers.
380 static bool check_device(struct device *dev)
384 if (!dev || !dev->dma_mask)
387 devid = get_device_id(dev);
391 /* Out of our scope? */
392 if (devid > amd_iommu_last_bdf)
395 if (amd_iommu_rlookup_table[devid] == NULL)
401 static void init_iommu_group(struct device *dev)
403 struct iommu_group *group;
405 group = iommu_group_get_for_dev(dev);
409 iommu_group_put(group);
412 static int iommu_init_device(struct device *dev)
414 struct iommu_dev_data *dev_data;
415 struct amd_iommu *iommu;
418 if (dev->archdata.iommu)
421 devid = get_device_id(dev);
425 iommu = amd_iommu_rlookup_table[devid];
427 dev_data = find_dev_data(devid);
431 dev_data->alias = get_alias(dev);
434 * By default we use passthrough mode for IOMMUv2 capable device.
435 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
436 * invalid address), we ignore the capability for the device so
437 * it'll be forced to go into translation mode.
439 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
440 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
441 struct amd_iommu *iommu;
443 iommu = amd_iommu_rlookup_table[dev_data->devid];
444 dev_data->iommu_v2 = iommu->is_iommu_v2;
447 dev->archdata.iommu = dev_data;
449 iommu_device_link(&iommu->iommu, dev);
454 static void iommu_ignore_device(struct device *dev)
459 devid = get_device_id(dev);
463 alias = get_alias(dev);
465 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
466 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
468 amd_iommu_rlookup_table[devid] = NULL;
469 amd_iommu_rlookup_table[alias] = NULL;
472 static void iommu_uninit_device(struct device *dev)
474 struct iommu_dev_data *dev_data;
475 struct amd_iommu *iommu;
478 devid = get_device_id(dev);
482 iommu = amd_iommu_rlookup_table[devid];
484 dev_data = search_dev_data(devid);
488 if (dev_data->domain)
491 iommu_device_unlink(&iommu->iommu, dev);
493 iommu_group_remove_device(dev);
499 * We keep dev_data around for unplugged devices and reuse it when the
500 * device is re-plugged - not doing so would introduce a ton of races.
505 * Helper function to get the first pte of a large mapping
507 static u64 *first_pte_l7(u64 *pte, unsigned long *page_size,
508 unsigned long *count)
510 unsigned long pte_mask, pg_size, cnt;
513 pg_size = PTE_PAGE_SIZE(*pte);
514 cnt = PAGE_SIZE_PTE_COUNT(pg_size);
515 pte_mask = ~((cnt << 3) - 1);
516 fpte = (u64 *)(((unsigned long)pte) & pte_mask);
519 *page_size = pg_size;
527 /****************************************************************************
529 * Interrupt handling functions
531 ****************************************************************************/
533 static void dump_dte_entry(u16 devid)
537 for (i = 0; i < 4; ++i)
538 pr_err("DTE[%d]: %016llx\n", i,
539 amd_iommu_dev_table[devid].data[i]);
542 static void dump_command(unsigned long phys_addr)
544 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
547 for (i = 0; i < 4; ++i)
548 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
551 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
552 u64 address, int flags)
554 struct iommu_dev_data *dev_data = NULL;
555 struct pci_dev *pdev;
557 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
560 dev_data = get_dev_data(&pdev->dev);
562 if (dev_data && __ratelimit(&dev_data->rs)) {
563 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
564 domain_id, address, flags);
565 } else if (printk_ratelimit()) {
566 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
567 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
568 domain_id, address, flags);
575 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
577 struct device *dev = iommu->iommu.dev;
578 int type, devid, pasid, flags, tag;
579 volatile u32 *event = __evt;
584 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
585 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
586 pasid = PPR_PASID(*(u64 *)&event[0]);
587 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
588 address = (u64)(((u64)event[3]) << 32) | event[2];
591 /* Did we hit the erratum? */
592 if (++count == LOOP_TIMEOUT) {
593 pr_err("No event written to event log\n");
600 if (type == EVENT_TYPE_IO_FAULT) {
601 amd_iommu_report_page_fault(devid, pasid, address, flags);
606 case EVENT_TYPE_ILL_DEV:
607 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
608 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
609 pasid, address, flags);
610 dump_dte_entry(devid);
612 case EVENT_TYPE_DEV_TAB_ERR:
613 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
614 "address=0x%llx flags=0x%04x]\n",
615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
618 case EVENT_TYPE_PAGE_TAB_ERR:
619 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
620 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
621 pasid, address, flags);
623 case EVENT_TYPE_ILL_CMD:
624 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
625 dump_command(address);
627 case EVENT_TYPE_CMD_HARD_ERR:
628 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
631 case EVENT_TYPE_IOTLB_INV_TO:
632 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
633 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
636 case EVENT_TYPE_INV_DEV_REQ:
637 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
638 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
639 pasid, address, flags);
641 case EVENT_TYPE_INV_PPR_REQ:
642 pasid = ((event[0] >> 16) & 0xFFFF)
643 | ((event[1] << 6) & 0xF0000);
644 tag = event[1] & 0x03FF;
645 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
646 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
647 pasid, address, flags, tag);
650 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
651 event[0], event[1], event[2], event[3]);
654 memset(__evt, 0, 4 * sizeof(u32));
657 static void iommu_poll_events(struct amd_iommu *iommu)
661 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
662 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
664 while (head != tail) {
665 iommu_print_event(iommu, iommu->evt_buf + head);
666 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
669 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
672 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
674 struct amd_iommu_fault fault;
676 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
677 pr_err_ratelimited("Unknown PPR request received\n");
681 fault.address = raw[1];
682 fault.pasid = PPR_PASID(raw[0]);
683 fault.device_id = PPR_DEVID(raw[0]);
684 fault.tag = PPR_TAG(raw[0]);
685 fault.flags = PPR_FLAGS(raw[0]);
687 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
690 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
694 if (iommu->ppr_log == NULL)
697 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
698 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
700 while (head != tail) {
705 raw = (u64 *)(iommu->ppr_log + head);
708 * Hardware bug: Interrupt may arrive before the entry is
709 * written to memory. If this happens we need to wait for the
712 for (i = 0; i < LOOP_TIMEOUT; ++i) {
713 if (PPR_REQ_TYPE(raw[0]) != 0)
718 /* Avoid memcpy function-call overhead */
723 * To detect the hardware bug we need to clear the entry
726 raw[0] = raw[1] = 0UL;
728 /* Update head pointer of hardware ring-buffer */
729 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
730 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
732 /* Handle PPR entry */
733 iommu_handle_ppr_entry(iommu, entry);
735 /* Refresh ring-buffer information */
736 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
737 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
741 #ifdef CONFIG_IRQ_REMAP
742 static int (*iommu_ga_log_notifier)(u32);
744 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
746 iommu_ga_log_notifier = notifier;
750 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
752 static void iommu_poll_ga_log(struct amd_iommu *iommu)
754 u32 head, tail, cnt = 0;
756 if (iommu->ga_log == NULL)
759 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
760 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
762 while (head != tail) {
766 raw = (u64 *)(iommu->ga_log + head);
769 /* Avoid memcpy function-call overhead */
772 /* Update head pointer of hardware ring-buffer */
773 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
774 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
776 /* Handle GA entry */
777 switch (GA_REQ_TYPE(log_entry)) {
779 if (!iommu_ga_log_notifier)
782 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
783 __func__, GA_DEVID(log_entry),
786 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
787 pr_err("GA log notifier failed.\n");
794 #endif /* CONFIG_IRQ_REMAP */
796 #define AMD_IOMMU_INT_MASK \
797 (MMIO_STATUS_EVT_INT_MASK | \
798 MMIO_STATUS_PPR_INT_MASK | \
799 MMIO_STATUS_GALOG_INT_MASK)
801 irqreturn_t amd_iommu_int_thread(int irq, void *data)
803 struct amd_iommu *iommu = (struct amd_iommu *) data;
804 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
806 while (status & AMD_IOMMU_INT_MASK) {
807 /* Enable EVT and PPR and GA interrupts again */
808 writel(AMD_IOMMU_INT_MASK,
809 iommu->mmio_base + MMIO_STATUS_OFFSET);
811 if (status & MMIO_STATUS_EVT_INT_MASK) {
812 pr_devel("Processing IOMMU Event Log\n");
813 iommu_poll_events(iommu);
816 if (status & MMIO_STATUS_PPR_INT_MASK) {
817 pr_devel("Processing IOMMU PPR Log\n");
818 iommu_poll_ppr_log(iommu);
821 #ifdef CONFIG_IRQ_REMAP
822 if (status & MMIO_STATUS_GALOG_INT_MASK) {
823 pr_devel("Processing IOMMU GA Log\n");
824 iommu_poll_ga_log(iommu);
829 * Hardware bug: ERBT1312
830 * When re-enabling interrupt (by writing 1
831 * to clear the bit), the hardware might also try to set
832 * the interrupt bit in the event status register.
833 * In this scenario, the bit will be set, and disable
834 * subsequent interrupts.
836 * Workaround: The IOMMU driver should read back the
837 * status register and check if the interrupt bits are cleared.
838 * If not, driver will need to go through the interrupt handler
839 * again and re-clear the bits
841 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
846 irqreturn_t amd_iommu_int_handler(int irq, void *data)
848 return IRQ_WAKE_THREAD;
851 /****************************************************************************
853 * IOMMU command queuing functions
855 ****************************************************************************/
857 static int wait_on_sem(volatile u64 *sem)
861 while (*sem == 0 && i < LOOP_TIMEOUT) {
866 if (i == LOOP_TIMEOUT) {
867 pr_alert("Completion-Wait loop timed out\n");
874 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
875 struct iommu_cmd *cmd)
879 target = iommu->cmd_buf + iommu->cmd_buf_tail;
881 iommu->cmd_buf_tail += sizeof(*cmd);
882 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
884 /* Copy command to buffer */
885 memcpy(target, cmd, sizeof(*cmd));
887 /* Tell the IOMMU about it */
888 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
891 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
893 u64 paddr = iommu_virt_to_phys((void *)address);
895 WARN_ON(address & 0x7ULL);
897 memset(cmd, 0, sizeof(*cmd));
898 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
899 cmd->data[1] = upper_32_bits(paddr);
901 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
904 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
906 memset(cmd, 0, sizeof(*cmd));
907 cmd->data[0] = devid;
908 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
911 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
912 size_t size, u16 domid, int pde)
917 pages = iommu_num_pages(address, size, PAGE_SIZE);
922 * If we have to flush more than one page, flush all
923 * TLB entries for this domain
925 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
929 address &= PAGE_MASK;
931 memset(cmd, 0, sizeof(*cmd));
932 cmd->data[1] |= domid;
933 cmd->data[2] = lower_32_bits(address);
934 cmd->data[3] = upper_32_bits(address);
935 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
936 if (s) /* size bit - we flush more than one 4kb page */
937 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
938 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
939 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
942 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
943 u64 address, size_t size)
948 pages = iommu_num_pages(address, size, PAGE_SIZE);
953 * If we have to flush more than one page, flush all
954 * TLB entries for this domain
956 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
960 address &= PAGE_MASK;
962 memset(cmd, 0, sizeof(*cmd));
963 cmd->data[0] = devid;
964 cmd->data[0] |= (qdep & 0xff) << 24;
965 cmd->data[1] = devid;
966 cmd->data[2] = lower_32_bits(address);
967 cmd->data[3] = upper_32_bits(address);
968 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
970 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
973 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
974 u64 address, bool size)
976 memset(cmd, 0, sizeof(*cmd));
978 address &= ~(0xfffULL);
980 cmd->data[0] = pasid;
981 cmd->data[1] = domid;
982 cmd->data[2] = lower_32_bits(address);
983 cmd->data[3] = upper_32_bits(address);
984 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
985 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
987 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
988 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
991 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
992 int qdep, u64 address, bool size)
994 memset(cmd, 0, sizeof(*cmd));
996 address &= ~(0xfffULL);
998 cmd->data[0] = devid;
999 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
1000 cmd->data[0] |= (qdep & 0xff) << 24;
1001 cmd->data[1] = devid;
1002 cmd->data[1] |= (pasid & 0xff) << 16;
1003 cmd->data[2] = lower_32_bits(address);
1004 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1005 cmd->data[3] = upper_32_bits(address);
1007 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1008 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
1011 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
1012 int status, int tag, bool gn)
1014 memset(cmd, 0, sizeof(*cmd));
1016 cmd->data[0] = devid;
1018 cmd->data[1] = pasid;
1019 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1021 cmd->data[3] = tag & 0x1ff;
1022 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1024 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1027 static void build_inv_all(struct iommu_cmd *cmd)
1029 memset(cmd, 0, sizeof(*cmd));
1030 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1033 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1035 memset(cmd, 0, sizeof(*cmd));
1036 cmd->data[0] = devid;
1037 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1041 * Writes the command to the IOMMUs command buffer and informs the
1042 * hardware about the new command.
1044 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1045 struct iommu_cmd *cmd,
1048 unsigned int count = 0;
1049 u32 left, next_tail;
1051 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1053 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1056 /* Skip udelay() the first time around */
1058 if (count == LOOP_TIMEOUT) {
1059 pr_err("Command buffer timeout\n");
1066 /* Update head and recheck remaining space */
1067 iommu->cmd_buf_head = readl(iommu->mmio_base +
1068 MMIO_CMD_HEAD_OFFSET);
1073 copy_cmd_to_buffer(iommu, cmd);
1075 /* Do we need to make sure all commands are processed? */
1076 iommu->need_sync = sync;
1081 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1082 struct iommu_cmd *cmd,
1085 unsigned long flags;
1088 raw_spin_lock_irqsave(&iommu->lock, flags);
1089 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1090 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1095 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1097 return iommu_queue_command_sync(iommu, cmd, true);
1101 * This function queues a completion wait command into the command
1102 * buffer of an IOMMU
1104 static int iommu_completion_wait(struct amd_iommu *iommu)
1106 struct iommu_cmd cmd;
1107 unsigned long flags;
1110 if (!iommu->need_sync)
1114 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1116 raw_spin_lock_irqsave(&iommu->lock, flags);
1120 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1124 ret = wait_on_sem(&iommu->cmd_sem);
1127 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1132 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1134 struct iommu_cmd cmd;
1136 build_inv_dte(&cmd, devid);
1138 return iommu_queue_command(iommu, &cmd);
1141 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1145 for (devid = 0; devid <= 0xffff; ++devid)
1146 iommu_flush_dte(iommu, devid);
1148 iommu_completion_wait(iommu);
1152 * This function uses heavy locking and may disable irqs for some time. But
1153 * this is no issue because it is only called during resume.
1155 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1159 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1160 struct iommu_cmd cmd;
1161 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1163 iommu_queue_command(iommu, &cmd);
1166 iommu_completion_wait(iommu);
1169 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1171 struct iommu_cmd cmd;
1173 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1175 iommu_queue_command(iommu, &cmd);
1177 iommu_completion_wait(iommu);
1180 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1182 struct iommu_cmd cmd;
1184 build_inv_all(&cmd);
1186 iommu_queue_command(iommu, &cmd);
1187 iommu_completion_wait(iommu);
1190 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1192 struct iommu_cmd cmd;
1194 build_inv_irt(&cmd, devid);
1196 iommu_queue_command(iommu, &cmd);
1199 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1203 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1204 iommu_flush_irt(iommu, devid);
1206 iommu_completion_wait(iommu);
1209 void iommu_flush_all_caches(struct amd_iommu *iommu)
1211 if (iommu_feature(iommu, FEATURE_IA)) {
1212 amd_iommu_flush_all(iommu);
1214 amd_iommu_flush_dte_all(iommu);
1215 amd_iommu_flush_irt_all(iommu);
1216 amd_iommu_flush_tlb_all(iommu);
1221 * Command send function for flushing on-device TLB
1223 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1224 u64 address, size_t size)
1226 struct amd_iommu *iommu;
1227 struct iommu_cmd cmd;
1230 qdep = dev_data->ats.qdep;
1231 iommu = amd_iommu_rlookup_table[dev_data->devid];
1233 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1235 return iommu_queue_command(iommu, &cmd);
1239 * Command send function for invalidating a device table entry
1241 static int device_flush_dte(struct iommu_dev_data *dev_data)
1243 struct amd_iommu *iommu;
1247 iommu = amd_iommu_rlookup_table[dev_data->devid];
1248 alias = dev_data->alias;
1250 ret = iommu_flush_dte(iommu, dev_data->devid);
1251 if (!ret && alias != dev_data->devid)
1252 ret = iommu_flush_dte(iommu, alias);
1256 if (dev_data->ats.enabled)
1257 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1263 * TLB invalidation function which is called from the mapping functions.
1264 * It invalidates a single PTE if the range to flush is within a single
1265 * page. Otherwise it flushes the whole TLB of the IOMMU.
1267 static void __domain_flush_pages(struct protection_domain *domain,
1268 u64 address, size_t size, int pde)
1270 struct iommu_dev_data *dev_data;
1271 struct iommu_cmd cmd;
1274 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1276 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1277 if (!domain->dev_iommu[i])
1281 * Devices of this domain are behind this IOMMU
1282 * We need a TLB flush
1284 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1287 list_for_each_entry(dev_data, &domain->dev_list, list) {
1289 if (!dev_data->ats.enabled)
1292 ret |= device_flush_iotlb(dev_data, address, size);
1298 static void domain_flush_pages(struct protection_domain *domain,
1299 u64 address, size_t size)
1301 __domain_flush_pages(domain, address, size, 0);
1304 /* Flush the whole IO/TLB for a given protection domain */
1305 static void domain_flush_tlb(struct protection_domain *domain)
1307 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1310 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1311 static void domain_flush_tlb_pde(struct protection_domain *domain)
1313 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1316 static void domain_flush_complete(struct protection_domain *domain)
1320 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1321 if (domain && !domain->dev_iommu[i])
1325 * Devices of this domain are behind this IOMMU
1326 * We need to wait for completion of all commands.
1328 iommu_completion_wait(amd_iommus[i]);
1332 /* Flush the not present cache if it exists */
1333 static void domain_flush_np_cache(struct protection_domain *domain,
1334 dma_addr_t iova, size_t size)
1336 if (unlikely(amd_iommu_np_cache)) {
1337 unsigned long flags;
1339 spin_lock_irqsave(&domain->lock, flags);
1340 domain_flush_pages(domain, iova, size);
1341 domain_flush_complete(domain);
1342 spin_unlock_irqrestore(&domain->lock, flags);
1348 * This function flushes the DTEs for all devices in domain
1350 static void domain_flush_devices(struct protection_domain *domain)
1352 struct iommu_dev_data *dev_data;
1354 list_for_each_entry(dev_data, &domain->dev_list, list)
1355 device_flush_dte(dev_data);
1358 /****************************************************************************
1360 * The functions below are used the create the page table mappings for
1361 * unity mapped regions.
1363 ****************************************************************************/
1365 static void free_page_list(struct page *freelist)
1367 while (freelist != NULL) {
1368 unsigned long p = (unsigned long)page_address(freelist);
1369 freelist = freelist->freelist;
1374 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1376 struct page *p = virt_to_page((void *)pt);
1378 p->freelist = freelist;
1383 #define DEFINE_FREE_PT_FN(LVL, FN) \
1384 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1392 for (i = 0; i < 512; ++i) { \
1393 /* PTE present? */ \
1394 if (!IOMMU_PTE_PRESENT(pt[i])) \
1398 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1399 PM_PTE_LEVEL(pt[i]) == 7) \
1402 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1403 freelist = FN(p, freelist); \
1406 return free_pt_page((unsigned long)pt, freelist); \
1409 DEFINE_FREE_PT_FN(l2, free_pt_page)
1410 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1411 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1412 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1413 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1415 static struct page *free_sub_pt(unsigned long root, int mode,
1416 struct page *freelist)
1419 case PAGE_MODE_NONE:
1420 case PAGE_MODE_7_LEVEL:
1422 case PAGE_MODE_1_LEVEL:
1423 freelist = free_pt_page(root, freelist);
1425 case PAGE_MODE_2_LEVEL:
1426 freelist = free_pt_l2(root, freelist);
1428 case PAGE_MODE_3_LEVEL:
1429 freelist = free_pt_l3(root, freelist);
1431 case PAGE_MODE_4_LEVEL:
1432 freelist = free_pt_l4(root, freelist);
1434 case PAGE_MODE_5_LEVEL:
1435 freelist = free_pt_l5(root, freelist);
1437 case PAGE_MODE_6_LEVEL:
1438 freelist = free_pt_l6(root, freelist);
1447 static void free_pagetable(struct protection_domain *domain)
1449 unsigned long root = (unsigned long)domain->pt_root;
1450 struct page *freelist = NULL;
1452 BUG_ON(domain->mode < PAGE_MODE_NONE ||
1453 domain->mode > PAGE_MODE_6_LEVEL);
1455 freelist = free_sub_pt(root, domain->mode, freelist);
1457 free_page_list(freelist);
1461 * This function is used to add another level to an IO page table. Adding
1462 * another level increases the size of the address space by 9 bits to a size up
1465 static bool increase_address_space(struct protection_domain *domain,
1468 unsigned long flags;
1472 spin_lock_irqsave(&domain->lock, flags);
1474 if (WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
1475 /* address space already 64 bit large */
1478 pte = (void *)get_zeroed_page(gfp);
1482 *pte = PM_LEVEL_PDE(domain->mode,
1483 iommu_virt_to_phys(domain->pt_root));
1484 domain->pt_root = pte;
1490 spin_unlock_irqrestore(&domain->lock, flags);
1495 static u64 *alloc_pte(struct protection_domain *domain,
1496 unsigned long address,
1497 unsigned long page_size,
1505 BUG_ON(!is_power_of_2(page_size));
1507 while (address > PM_LEVEL_SIZE(domain->mode))
1508 *updated = increase_address_space(domain, gfp) || *updated;
1510 level = domain->mode - 1;
1511 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1512 address = PAGE_SIZE_ALIGN(address, page_size);
1513 end_lvl = PAGE_SIZE_LEVEL(page_size);
1515 while (level > end_lvl) {
1520 pte_level = PM_PTE_LEVEL(__pte);
1523 * If we replace a series of large PTEs, we need
1524 * to tear down all of them.
1526 if (IOMMU_PTE_PRESENT(__pte) &&
1527 pte_level == PAGE_MODE_7_LEVEL) {
1528 unsigned long count, i;
1531 lpte = first_pte_l7(pte, NULL, &count);
1534 * Unmap the replicated PTEs that still match the
1535 * original large mapping
1537 for (i = 0; i < count; ++i)
1538 cmpxchg64(&lpte[i], __pte, 0ULL);
1544 if (!IOMMU_PTE_PRESENT(__pte) ||
1545 pte_level == PAGE_MODE_NONE) {
1546 page = (u64 *)get_zeroed_page(gfp);
1551 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1553 /* pte could have been changed somewhere. */
1554 if (cmpxchg64(pte, __pte, __npte) != __pte)
1555 free_page((unsigned long)page);
1556 else if (IOMMU_PTE_PRESENT(__pte))
1562 /* No level skipping support yet */
1563 if (pte_level != level)
1568 pte = IOMMU_PTE_PAGE(__pte);
1570 if (pte_page && level == end_lvl)
1573 pte = &pte[PM_LEVEL_INDEX(level, address)];
1580 * This function checks if there is a PTE for a given dma address. If
1581 * there is one, it returns the pointer to it.
1583 static u64 *fetch_pte(struct protection_domain *domain,
1584 unsigned long address,
1585 unsigned long *page_size)
1592 if (address > PM_LEVEL_SIZE(domain->mode))
1595 level = domain->mode - 1;
1596 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1597 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1602 if (!IOMMU_PTE_PRESENT(*pte))
1606 if (PM_PTE_LEVEL(*pte) == 7 ||
1607 PM_PTE_LEVEL(*pte) == 0)
1610 /* No level skipping support yet */
1611 if (PM_PTE_LEVEL(*pte) != level)
1616 /* Walk to the next level */
1617 pte = IOMMU_PTE_PAGE(*pte);
1618 pte = &pte[PM_LEVEL_INDEX(level, address)];
1619 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1623 * If we have a series of large PTEs, make
1624 * sure to return a pointer to the first one.
1626 if (PM_PTE_LEVEL(*pte) == PAGE_MODE_7_LEVEL)
1627 pte = first_pte_l7(pte, page_size, NULL);
1632 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1637 while (cmpxchg64(pte, pteval, 0) != pteval) {
1638 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1642 if (!IOMMU_PTE_PRESENT(pteval))
1645 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1646 mode = IOMMU_PTE_MODE(pteval);
1648 return free_sub_pt(pt, mode, freelist);
1652 * Generic mapping functions. It maps a physical address into a DMA
1653 * address space. It allocates the page table pages if necessary.
1654 * In the future it can be extended to a generic mapping function
1655 * supporting all features of AMD IOMMU page tables like level skipping
1656 * and full 64 bit address spaces.
1658 static int iommu_map_page(struct protection_domain *dom,
1659 unsigned long bus_addr,
1660 unsigned long phys_addr,
1661 unsigned long page_size,
1665 struct page *freelist = NULL;
1666 bool updated = false;
1670 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1671 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1674 if (!(prot & IOMMU_PROT_MASK))
1677 count = PAGE_SIZE_PTE_COUNT(page_size);
1678 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp, &updated);
1684 for (i = 0; i < count; ++i)
1685 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1687 if (freelist != NULL)
1691 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1692 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1694 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1696 if (prot & IOMMU_PROT_IR)
1697 __pte |= IOMMU_PTE_IR;
1698 if (prot & IOMMU_PROT_IW)
1699 __pte |= IOMMU_PTE_IW;
1701 for (i = 0; i < count; ++i)
1708 unsigned long flags;
1710 spin_lock_irqsave(&dom->lock, flags);
1712 spin_unlock_irqrestore(&dom->lock, flags);
1715 /* Everything flushed out, free pages now */
1716 free_page_list(freelist);
1721 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1722 unsigned long bus_addr,
1723 unsigned long page_size)
1725 unsigned long long unmapped;
1726 unsigned long unmap_size;
1729 BUG_ON(!is_power_of_2(page_size));
1733 while (unmapped < page_size) {
1735 pte = fetch_pte(dom, bus_addr, &unmap_size);
1740 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1741 for (i = 0; i < count; i++)
1745 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1746 unmapped += unmap_size;
1749 BUG_ON(unmapped && !is_power_of_2(unmapped));
1754 /****************************************************************************
1756 * The next functions belong to the address allocator for the dma_ops
1757 * interface functions.
1759 ****************************************************************************/
1762 static unsigned long dma_ops_alloc_iova(struct device *dev,
1763 struct dma_ops_domain *dma_dom,
1764 unsigned int pages, u64 dma_mask)
1766 unsigned long pfn = 0;
1768 pages = __roundup_pow_of_two(pages);
1770 if (dma_mask > DMA_BIT_MASK(32))
1771 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1772 IOVA_PFN(DMA_BIT_MASK(32)), false);
1775 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1776 IOVA_PFN(dma_mask), true);
1778 return (pfn << PAGE_SHIFT);
1781 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1782 unsigned long address,
1785 pages = __roundup_pow_of_two(pages);
1786 address >>= PAGE_SHIFT;
1788 free_iova_fast(&dma_dom->iovad, address, pages);
1791 /****************************************************************************
1793 * The next functions belong to the domain allocation. A domain is
1794 * allocated for every IOMMU as the default domain. If device isolation
1795 * is enabled, every device get its own domain. The most important thing
1796 * about domains is the page table mapping the DMA address space they
1799 ****************************************************************************/
1801 static u16 domain_id_alloc(void)
1805 spin_lock(&pd_bitmap_lock);
1806 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1808 if (id > 0 && id < MAX_DOMAIN_ID)
1809 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1812 spin_unlock(&pd_bitmap_lock);
1817 static void domain_id_free(int id)
1819 spin_lock(&pd_bitmap_lock);
1820 if (id > 0 && id < MAX_DOMAIN_ID)
1821 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1822 spin_unlock(&pd_bitmap_lock);
1825 static void free_gcr3_tbl_level1(u64 *tbl)
1830 for (i = 0; i < 512; ++i) {
1831 if (!(tbl[i] & GCR3_VALID))
1834 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1836 free_page((unsigned long)ptr);
1840 static void free_gcr3_tbl_level2(u64 *tbl)
1845 for (i = 0; i < 512; ++i) {
1846 if (!(tbl[i] & GCR3_VALID))
1849 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1851 free_gcr3_tbl_level1(ptr);
1855 static void free_gcr3_table(struct protection_domain *domain)
1857 if (domain->glx == 2)
1858 free_gcr3_tbl_level2(domain->gcr3_tbl);
1859 else if (domain->glx == 1)
1860 free_gcr3_tbl_level1(domain->gcr3_tbl);
1862 BUG_ON(domain->glx != 0);
1864 free_page((unsigned long)domain->gcr3_tbl);
1867 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1869 unsigned long flags;
1871 spin_lock_irqsave(&dom->domain.lock, flags);
1872 domain_flush_tlb(&dom->domain);
1873 domain_flush_complete(&dom->domain);
1874 spin_unlock_irqrestore(&dom->domain.lock, flags);
1877 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1879 struct dma_ops_domain *dom;
1881 dom = container_of(iovad, struct dma_ops_domain, iovad);
1883 dma_ops_domain_flush_tlb(dom);
1887 * Free a domain, only used if something went wrong in the
1888 * allocation path and we need to free an already allocated page table
1890 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1895 put_iova_domain(&dom->iovad);
1897 free_pagetable(&dom->domain);
1900 domain_id_free(dom->domain.id);
1906 * Allocates a new protection domain usable for the dma_ops functions.
1907 * It also initializes the page table and the address allocator data
1908 * structures required for the dma_ops interface
1910 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1912 struct dma_ops_domain *dma_dom;
1914 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1918 if (protection_domain_init(&dma_dom->domain))
1921 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1922 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1923 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1924 if (!dma_dom->domain.pt_root)
1927 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1929 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1932 /* Initialize reserved ranges */
1933 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1938 dma_ops_domain_free(dma_dom);
1944 * little helper function to check whether a given protection domain is a
1947 static bool dma_ops_domain(struct protection_domain *domain)
1949 return domain->flags & PD_DMA_OPS_MASK;
1952 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1959 if (domain->mode != PAGE_MODE_NONE)
1960 pte_root = iommu_virt_to_phys(domain->pt_root);
1962 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1963 << DEV_ENTRY_MODE_SHIFT;
1964 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1966 flags = amd_iommu_dev_table[devid].data[1];
1969 flags |= DTE_FLAG_IOTLB;
1972 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1974 if (iommu_feature(iommu, FEATURE_EPHSUP))
1975 pte_root |= 1ULL << DEV_ENTRY_PPR;
1978 if (domain->flags & PD_IOMMUV2_MASK) {
1979 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1980 u64 glx = domain->glx;
1983 pte_root |= DTE_FLAG_GV;
1984 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1986 /* First mask out possible old values for GCR3 table */
1987 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1990 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1993 /* Encode GCR3 table into DTE */
1994 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1997 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2000 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2004 flags &= ~DEV_DOMID_MASK;
2005 flags |= domain->id;
2007 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
2008 amd_iommu_dev_table[devid].data[1] = flags;
2009 amd_iommu_dev_table[devid].data[0] = pte_root;
2012 * A kdump kernel might be replacing a domain ID that was copied from
2013 * the previous kernel--if so, it needs to flush the translation cache
2014 * entries for the old domain ID that is being overwritten
2017 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2019 amd_iommu_flush_tlb_domid(iommu, old_domid);
2023 static void clear_dte_entry(u16 devid)
2025 /* remove entry from the device table seen by the hardware */
2026 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
2027 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
2029 amd_iommu_apply_erratum_63(devid);
2032 static void do_attach(struct iommu_dev_data *dev_data,
2033 struct protection_domain *domain)
2035 struct amd_iommu *iommu;
2039 iommu = amd_iommu_rlookup_table[dev_data->devid];
2040 alias = dev_data->alias;
2041 ats = dev_data->ats.enabled;
2043 /* Update data structures */
2044 dev_data->domain = domain;
2045 list_add(&dev_data->list, &domain->dev_list);
2047 /* Do reference counting */
2048 domain->dev_iommu[iommu->index] += 1;
2049 domain->dev_cnt += 1;
2051 /* Update device table */
2052 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
2053 if (alias != dev_data->devid)
2054 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
2056 device_flush_dte(dev_data);
2059 static void do_detach(struct iommu_dev_data *dev_data)
2061 struct protection_domain *domain = dev_data->domain;
2062 struct amd_iommu *iommu;
2065 iommu = amd_iommu_rlookup_table[dev_data->devid];
2066 alias = dev_data->alias;
2068 /* Update data structures */
2069 dev_data->domain = NULL;
2070 list_del(&dev_data->list);
2071 clear_dte_entry(dev_data->devid);
2072 if (alias != dev_data->devid)
2073 clear_dte_entry(alias);
2075 /* Flush the DTE entry */
2076 device_flush_dte(dev_data);
2079 domain_flush_tlb_pde(domain);
2081 /* Wait for the flushes to finish */
2082 domain_flush_complete(domain);
2084 /* decrease reference counters - needs to happen after the flushes */
2085 domain->dev_iommu[iommu->index] -= 1;
2086 domain->dev_cnt -= 1;
2089 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2091 pci_disable_ats(pdev);
2092 pci_disable_pri(pdev);
2093 pci_disable_pasid(pdev);
2096 /* FIXME: Change generic reset-function to do the same */
2097 static int pri_reset_while_enabled(struct pci_dev *pdev)
2102 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2106 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2107 control |= PCI_PRI_CTRL_RESET;
2108 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2113 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2118 /* FIXME: Hardcode number of outstanding requests for now */
2120 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2122 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2124 /* Only allow access to user-accessible pages */
2125 ret = pci_enable_pasid(pdev, 0);
2129 /* First reset the PRI state of the device */
2130 ret = pci_reset_pri(pdev);
2135 ret = pci_enable_pri(pdev, reqs);
2140 ret = pri_reset_while_enabled(pdev);
2145 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2152 pci_disable_pri(pdev);
2153 pci_disable_pasid(pdev);
2159 * If a device is not yet associated with a domain, this function makes the
2160 * device visible in the domain
2162 static int attach_device(struct device *dev,
2163 struct protection_domain *domain)
2165 struct pci_dev *pdev;
2166 struct iommu_dev_data *dev_data;
2167 unsigned long flags;
2170 spin_lock_irqsave(&domain->lock, flags);
2172 dev_data = get_dev_data(dev);
2174 spin_lock(&dev_data->lock);
2177 if (dev_data->domain != NULL)
2180 if (!dev_is_pci(dev))
2181 goto skip_ats_check;
2183 pdev = to_pci_dev(dev);
2184 if (domain->flags & PD_IOMMUV2_MASK) {
2186 if (!dev_data->passthrough)
2189 if (dev_data->iommu_v2) {
2190 if (pdev_iommuv2_enable(pdev) != 0)
2193 dev_data->ats.enabled = true;
2194 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2195 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2197 } else if (amd_iommu_iotlb_sup &&
2198 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2199 dev_data->ats.enabled = true;
2200 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2206 do_attach(dev_data, domain);
2209 * We might boot into a crash-kernel here. The crashed kernel
2210 * left the caches in the IOMMU dirty. So we have to flush
2211 * here to evict all dirty stuff.
2213 domain_flush_tlb_pde(domain);
2215 domain_flush_complete(domain);
2218 spin_unlock(&dev_data->lock);
2220 spin_unlock_irqrestore(&domain->lock, flags);
2226 * Removes a device from a protection domain (with devtable_lock held)
2228 static void detach_device(struct device *dev)
2230 struct protection_domain *domain;
2231 struct iommu_dev_data *dev_data;
2232 unsigned long flags;
2234 dev_data = get_dev_data(dev);
2235 domain = dev_data->domain;
2237 spin_lock_irqsave(&domain->lock, flags);
2239 spin_lock(&dev_data->lock);
2242 * First check if the device is still attached. It might already
2243 * be detached from its domain because the generic
2244 * iommu_detach_group code detached it and we try again here in
2245 * our alias handling.
2247 if (WARN_ON(!dev_data->domain))
2250 do_detach(dev_data);
2252 if (!dev_is_pci(dev))
2255 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2256 pdev_iommuv2_disable(to_pci_dev(dev));
2257 else if (dev_data->ats.enabled)
2258 pci_disable_ats(to_pci_dev(dev));
2260 dev_data->ats.enabled = false;
2263 spin_unlock(&dev_data->lock);
2265 spin_unlock_irqrestore(&domain->lock, flags);
2268 static int amd_iommu_add_device(struct device *dev)
2270 struct iommu_dev_data *dev_data;
2271 struct iommu_domain *domain;
2272 struct amd_iommu *iommu;
2275 if (!check_device(dev) || get_dev_data(dev))
2278 devid = get_device_id(dev);
2282 iommu = amd_iommu_rlookup_table[devid];
2284 ret = iommu_init_device(dev);
2286 if (ret != -ENOTSUPP)
2287 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2289 iommu_ignore_device(dev);
2290 dev->dma_ops = NULL;
2293 init_iommu_group(dev);
2295 dev_data = get_dev_data(dev);
2299 if (dev_data->iommu_v2)
2300 iommu_request_dm_for_dev(dev);
2302 /* Domains are initialized for this device - have a look what we ended up with */
2303 domain = iommu_get_domain_for_dev(dev);
2304 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2305 dev_data->passthrough = true;
2307 dev->dma_ops = &amd_iommu_dma_ops;
2310 iommu_completion_wait(iommu);
2315 static void amd_iommu_remove_device(struct device *dev)
2317 struct amd_iommu *iommu;
2320 if (!check_device(dev))
2323 devid = get_device_id(dev);
2327 iommu = amd_iommu_rlookup_table[devid];
2329 iommu_uninit_device(dev);
2330 iommu_completion_wait(iommu);
2333 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2335 if (dev_is_pci(dev))
2336 return pci_device_group(dev);
2338 return acpihid_device_group(dev);
2341 /*****************************************************************************
2343 * The next functions belong to the dma_ops mapping/unmapping code.
2345 *****************************************************************************/
2348 * In the dma_ops path we only have the struct device. This function
2349 * finds the corresponding IOMMU, the protection domain and the
2350 * requestor id for a given device.
2351 * If the device is not yet associated with a domain this is also done
2354 static struct protection_domain *get_domain(struct device *dev)
2356 struct protection_domain *domain;
2357 struct iommu_domain *io_domain;
2359 if (!check_device(dev))
2360 return ERR_PTR(-EINVAL);
2362 domain = get_dev_data(dev)->domain;
2363 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2364 get_dev_data(dev)->defer_attach = false;
2365 io_domain = iommu_get_domain_for_dev(dev);
2366 domain = to_pdomain(io_domain);
2367 attach_device(dev, domain);
2370 return ERR_PTR(-EBUSY);
2372 if (!dma_ops_domain(domain))
2373 return ERR_PTR(-EBUSY);
2378 static void update_device_table(struct protection_domain *domain)
2380 struct iommu_dev_data *dev_data;
2382 list_for_each_entry(dev_data, &domain->dev_list, list) {
2383 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2384 dev_data->iommu_v2);
2386 if (dev_data->devid == dev_data->alias)
2389 /* There is an alias, update device table entry for it */
2390 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2391 dev_data->iommu_v2);
2395 static void update_domain(struct protection_domain *domain)
2397 update_device_table(domain);
2399 domain_flush_devices(domain);
2400 domain_flush_tlb_pde(domain);
2403 static int dir2prot(enum dma_data_direction direction)
2405 if (direction == DMA_TO_DEVICE)
2406 return IOMMU_PROT_IR;
2407 else if (direction == DMA_FROM_DEVICE)
2408 return IOMMU_PROT_IW;
2409 else if (direction == DMA_BIDIRECTIONAL)
2410 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2416 * This function contains common code for mapping of a physically
2417 * contiguous memory region into DMA address space. It is used by all
2418 * mapping functions provided with this IOMMU driver.
2419 * Must be called with the domain lock held.
2421 static dma_addr_t __map_single(struct device *dev,
2422 struct dma_ops_domain *dma_dom,
2425 enum dma_data_direction direction,
2428 dma_addr_t offset = paddr & ~PAGE_MASK;
2429 dma_addr_t address, start, ret;
2430 unsigned long flags;
2435 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2438 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2442 prot = dir2prot(direction);
2445 for (i = 0; i < pages; ++i) {
2446 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2447 PAGE_SIZE, prot, GFP_ATOMIC);
2456 domain_flush_np_cache(&dma_dom->domain, address, size);
2463 for (--i; i >= 0; --i) {
2465 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2468 spin_lock_irqsave(&dma_dom->domain.lock, flags);
2469 domain_flush_tlb(&dma_dom->domain);
2470 domain_flush_complete(&dma_dom->domain);
2471 spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
2473 dma_ops_free_iova(dma_dom, address, pages);
2475 return DMA_MAPPING_ERROR;
2479 * Does the reverse of the __map_single function. Must be called with
2480 * the domain lock held too
2482 static void __unmap_single(struct dma_ops_domain *dma_dom,
2483 dma_addr_t dma_addr,
2487 dma_addr_t i, start;
2490 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2491 dma_addr &= PAGE_MASK;
2494 for (i = 0; i < pages; ++i) {
2495 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2499 if (amd_iommu_unmap_flush) {
2500 unsigned long flags;
2502 spin_lock_irqsave(&dma_dom->domain.lock, flags);
2503 domain_flush_tlb(&dma_dom->domain);
2504 domain_flush_complete(&dma_dom->domain);
2505 spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
2506 dma_ops_free_iova(dma_dom, dma_addr, pages);
2508 pages = __roundup_pow_of_two(pages);
2509 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2514 * The exported map_single function for dma_ops.
2516 static dma_addr_t map_page(struct device *dev, struct page *page,
2517 unsigned long offset, size_t size,
2518 enum dma_data_direction dir,
2519 unsigned long attrs)
2521 phys_addr_t paddr = page_to_phys(page) + offset;
2522 struct protection_domain *domain;
2523 struct dma_ops_domain *dma_dom;
2526 domain = get_domain(dev);
2527 if (PTR_ERR(domain) == -EINVAL)
2528 return (dma_addr_t)paddr;
2529 else if (IS_ERR(domain))
2530 return DMA_MAPPING_ERROR;
2532 dma_mask = *dev->dma_mask;
2533 dma_dom = to_dma_ops_domain(domain);
2535 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2539 * The exported unmap_single function for dma_ops.
2541 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2542 enum dma_data_direction dir, unsigned long attrs)
2544 struct protection_domain *domain;
2545 struct dma_ops_domain *dma_dom;
2547 domain = get_domain(dev);
2551 dma_dom = to_dma_ops_domain(domain);
2553 __unmap_single(dma_dom, dma_addr, size, dir);
2556 static int sg_num_pages(struct device *dev,
2557 struct scatterlist *sglist,
2560 unsigned long mask, boundary_size;
2561 struct scatterlist *s;
2564 mask = dma_get_seg_boundary(dev);
2565 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2566 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2568 for_each_sg(sglist, s, nelems, i) {
2571 s->dma_address = npages << PAGE_SHIFT;
2572 p = npages % boundary_size;
2573 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2574 if (p + n > boundary_size)
2575 npages += boundary_size - p;
2583 * The exported map_sg function for dma_ops (handles scatter-gather
2586 static int map_sg(struct device *dev, struct scatterlist *sglist,
2587 int nelems, enum dma_data_direction direction,
2588 unsigned long attrs)
2590 int mapped_pages = 0, npages = 0, prot = 0, i;
2591 struct protection_domain *domain;
2592 struct dma_ops_domain *dma_dom;
2593 struct scatterlist *s;
2594 unsigned long address;
2598 domain = get_domain(dev);
2602 dma_dom = to_dma_ops_domain(domain);
2603 dma_mask = *dev->dma_mask;
2605 npages = sg_num_pages(dev, sglist, nelems);
2607 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2611 prot = dir2prot(direction);
2613 /* Map all sg entries */
2614 for_each_sg(sglist, s, nelems, i) {
2615 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2617 for (j = 0; j < pages; ++j) {
2618 unsigned long bus_addr, phys_addr;
2620 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2621 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2622 ret = iommu_map_page(domain, bus_addr, phys_addr,
2624 GFP_ATOMIC | __GFP_NOWARN);
2632 /* Everything is mapped - write the right values into s->dma_address */
2633 for_each_sg(sglist, s, nelems, i) {
2635 * Add in the remaining piece of the scatter-gather offset that
2636 * was masked out when we were determining the physical address
2637 * via (sg_phys(s) & PAGE_MASK) earlier.
2639 s->dma_address += address + (s->offset & ~PAGE_MASK);
2640 s->dma_length = s->length;
2644 domain_flush_np_cache(domain, s->dma_address, s->dma_length);
2649 dev_err(dev, "IOMMU mapping error in map_sg (io-pages: %d reason: %d)\n",
2652 for_each_sg(sglist, s, nelems, i) {
2653 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2655 for (j = 0; j < pages; ++j) {
2656 unsigned long bus_addr;
2658 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2659 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2661 if (--mapped_pages == 0)
2667 free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages);
2674 * The exported map_sg function for dma_ops (handles scatter-gather
2677 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2678 int nelems, enum dma_data_direction dir,
2679 unsigned long attrs)
2681 struct protection_domain *domain;
2682 struct dma_ops_domain *dma_dom;
2683 unsigned long startaddr;
2686 domain = get_domain(dev);
2690 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2691 dma_dom = to_dma_ops_domain(domain);
2692 npages = sg_num_pages(dev, sglist, nelems);
2694 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2698 * The exported alloc_coherent function for dma_ops.
2700 static void *alloc_coherent(struct device *dev, size_t size,
2701 dma_addr_t *dma_addr, gfp_t flag,
2702 unsigned long attrs)
2704 u64 dma_mask = dev->coherent_dma_mask;
2705 struct protection_domain *domain;
2706 struct dma_ops_domain *dma_dom;
2709 domain = get_domain(dev);
2710 if (PTR_ERR(domain) == -EINVAL) {
2711 page = alloc_pages(flag, get_order(size));
2712 *dma_addr = page_to_phys(page);
2713 return page_address(page);
2714 } else if (IS_ERR(domain))
2717 dma_dom = to_dma_ops_domain(domain);
2718 size = PAGE_ALIGN(size);
2719 dma_mask = dev->coherent_dma_mask;
2720 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2723 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2725 if (!gfpflags_allow_blocking(flag))
2728 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2729 get_order(size), flag & __GFP_NOWARN);
2735 dma_mask = *dev->dma_mask;
2737 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2738 size, DMA_BIDIRECTIONAL, dma_mask);
2740 if (*dma_addr == DMA_MAPPING_ERROR)
2743 return page_address(page);
2747 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2748 __free_pages(page, get_order(size));
2754 * The exported free_coherent function for dma_ops.
2756 static void free_coherent(struct device *dev, size_t size,
2757 void *virt_addr, dma_addr_t dma_addr,
2758 unsigned long attrs)
2760 struct protection_domain *domain;
2761 struct dma_ops_domain *dma_dom;
2764 page = virt_to_page(virt_addr);
2765 size = PAGE_ALIGN(size);
2767 domain = get_domain(dev);
2771 dma_dom = to_dma_ops_domain(domain);
2773 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2776 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2777 __free_pages(page, get_order(size));
2781 * This function is called by the DMA layer to find out if we can handle a
2782 * particular device. It is part of the dma_ops.
2784 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2786 if (!dma_direct_supported(dev, mask))
2788 return check_device(dev);
2791 static const struct dma_map_ops amd_iommu_dma_ops = {
2792 .alloc = alloc_coherent,
2793 .free = free_coherent,
2794 .map_page = map_page,
2795 .unmap_page = unmap_page,
2797 .unmap_sg = unmap_sg,
2798 .dma_supported = amd_iommu_dma_supported,
2799 .mmap = dma_common_mmap,
2800 .get_sgtable = dma_common_get_sgtable,
2803 static int init_reserved_iova_ranges(void)
2805 struct pci_dev *pdev = NULL;
2808 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2810 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2811 &reserved_rbtree_key);
2813 /* MSI memory range */
2814 val = reserve_iova(&reserved_iova_ranges,
2815 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2817 pr_err("Reserving MSI range failed\n");
2821 /* HT memory range */
2822 val = reserve_iova(&reserved_iova_ranges,
2823 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2825 pr_err("Reserving HT range failed\n");
2830 * Memory used for PCI resources
2831 * FIXME: Check whether we can reserve the PCI-hole completly
2833 for_each_pci_dev(pdev) {
2836 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2837 struct resource *r = &pdev->resource[i];
2839 if (!(r->flags & IORESOURCE_MEM))
2842 val = reserve_iova(&reserved_iova_ranges,
2846 pci_err(pdev, "Reserve pci-resource range %pR failed\n", r);
2855 int __init amd_iommu_init_api(void)
2859 ret = iova_cache_get();
2863 ret = init_reserved_iova_ranges();
2867 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2870 #ifdef CONFIG_ARM_AMBA
2871 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2875 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2882 int __init amd_iommu_init_dma_ops(void)
2884 swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
2887 if (amd_iommu_unmap_flush)
2888 pr_info("IO/TLB flush on unmap enabled\n");
2890 pr_info("Lazy IO/TLB flushing enabled\n");
2896 /*****************************************************************************
2898 * The following functions belong to the exported interface of AMD IOMMU
2900 * This interface allows access to lower level functions of the IOMMU
2901 * like protection domain handling and assignement of devices to domains
2902 * which is not possible with the dma_ops interface.
2904 *****************************************************************************/
2906 static void cleanup_domain(struct protection_domain *domain)
2908 struct iommu_dev_data *entry;
2909 unsigned long flags;
2911 spin_lock_irqsave(&domain->lock, flags);
2913 while (!list_empty(&domain->dev_list)) {
2914 entry = list_first_entry(&domain->dev_list,
2915 struct iommu_dev_data, list);
2916 BUG_ON(!entry->domain);
2920 spin_unlock_irqrestore(&domain->lock, flags);
2923 static void protection_domain_free(struct protection_domain *domain)
2929 domain_id_free(domain->id);
2934 static int protection_domain_init(struct protection_domain *domain)
2936 spin_lock_init(&domain->lock);
2937 mutex_init(&domain->api_lock);
2938 domain->id = domain_id_alloc();
2941 INIT_LIST_HEAD(&domain->dev_list);
2946 static struct protection_domain *protection_domain_alloc(void)
2948 struct protection_domain *domain;
2950 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2954 if (protection_domain_init(domain))
2965 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2967 struct protection_domain *pdomain;
2968 struct dma_ops_domain *dma_domain;
2971 case IOMMU_DOMAIN_UNMANAGED:
2972 pdomain = protection_domain_alloc();
2976 pdomain->mode = PAGE_MODE_3_LEVEL;
2977 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2978 if (!pdomain->pt_root) {
2979 protection_domain_free(pdomain);
2983 pdomain->domain.geometry.aperture_start = 0;
2984 pdomain->domain.geometry.aperture_end = ~0ULL;
2985 pdomain->domain.geometry.force_aperture = true;
2988 case IOMMU_DOMAIN_DMA:
2989 dma_domain = dma_ops_domain_alloc();
2991 pr_err("Failed to allocate\n");
2994 pdomain = &dma_domain->domain;
2996 case IOMMU_DOMAIN_IDENTITY:
2997 pdomain = protection_domain_alloc();
3001 pdomain->mode = PAGE_MODE_NONE;
3007 return &pdomain->domain;
3010 static void amd_iommu_domain_free(struct iommu_domain *dom)
3012 struct protection_domain *domain;
3013 struct dma_ops_domain *dma_dom;
3015 domain = to_pdomain(dom);
3017 if (domain->dev_cnt > 0)
3018 cleanup_domain(domain);
3020 BUG_ON(domain->dev_cnt != 0);
3025 switch (dom->type) {
3026 case IOMMU_DOMAIN_DMA:
3027 /* Now release the domain */
3028 dma_dom = to_dma_ops_domain(domain);
3029 dma_ops_domain_free(dma_dom);
3032 if (domain->mode != PAGE_MODE_NONE)
3033 free_pagetable(domain);
3035 if (domain->flags & PD_IOMMUV2_MASK)
3036 free_gcr3_table(domain);
3038 protection_domain_free(domain);
3043 static void amd_iommu_detach_device(struct iommu_domain *dom,
3046 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3047 struct amd_iommu *iommu;
3050 if (!check_device(dev))
3053 devid = get_device_id(dev);
3057 if (dev_data->domain != NULL)
3060 iommu = amd_iommu_rlookup_table[devid];
3064 #ifdef CONFIG_IRQ_REMAP
3065 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3066 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3067 dev_data->use_vapic = 0;
3070 iommu_completion_wait(iommu);
3073 static int amd_iommu_attach_device(struct iommu_domain *dom,
3076 struct protection_domain *domain = to_pdomain(dom);
3077 struct iommu_dev_data *dev_data;
3078 struct amd_iommu *iommu;
3081 if (!check_device(dev))
3084 dev_data = dev->archdata.iommu;
3086 iommu = amd_iommu_rlookup_table[dev_data->devid];
3090 if (dev_data->domain)
3093 ret = attach_device(dev, domain);
3095 #ifdef CONFIG_IRQ_REMAP
3096 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3097 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3098 dev_data->use_vapic = 1;
3100 dev_data->use_vapic = 0;
3104 iommu_completion_wait(iommu);
3109 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3110 phys_addr_t paddr, size_t page_size, int iommu_prot)
3112 struct protection_domain *domain = to_pdomain(dom);
3116 if (domain->mode == PAGE_MODE_NONE)
3119 if (iommu_prot & IOMMU_READ)
3120 prot |= IOMMU_PROT_IR;
3121 if (iommu_prot & IOMMU_WRITE)
3122 prot |= IOMMU_PROT_IW;
3124 mutex_lock(&domain->api_lock);
3125 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3126 mutex_unlock(&domain->api_lock);
3128 domain_flush_np_cache(domain, iova, page_size);
3133 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3135 struct iommu_iotlb_gather *gather)
3137 struct protection_domain *domain = to_pdomain(dom);
3140 if (domain->mode == PAGE_MODE_NONE)
3143 mutex_lock(&domain->api_lock);
3144 unmap_size = iommu_unmap_page(domain, iova, page_size);
3145 mutex_unlock(&domain->api_lock);
3150 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3153 struct protection_domain *domain = to_pdomain(dom);
3154 unsigned long offset_mask, pte_pgsize;
3157 if (domain->mode == PAGE_MODE_NONE)
3160 pte = fetch_pte(domain, iova, &pte_pgsize);
3162 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3165 offset_mask = pte_pgsize - 1;
3166 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3168 return (__pte & ~offset_mask) | (iova & offset_mask);
3171 static bool amd_iommu_capable(enum iommu_cap cap)
3174 case IOMMU_CAP_CACHE_COHERENCY:
3176 case IOMMU_CAP_INTR_REMAP:
3177 return (irq_remapping_enabled == 1);
3178 case IOMMU_CAP_NOEXEC:
3187 static void amd_iommu_get_resv_regions(struct device *dev,
3188 struct list_head *head)
3190 struct iommu_resv_region *region;
3191 struct unity_map_entry *entry;
3194 devid = get_device_id(dev);
3198 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3202 if (devid < entry->devid_start || devid > entry->devid_end)
3205 type = IOMMU_RESV_DIRECT;
3206 length = entry->address_end - entry->address_start;
3207 if (entry->prot & IOMMU_PROT_IR)
3209 if (entry->prot & IOMMU_PROT_IW)
3210 prot |= IOMMU_WRITE;
3211 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
3212 /* Exclusion range */
3213 type = IOMMU_RESV_RESERVED;
3215 region = iommu_alloc_resv_region(entry->address_start,
3216 length, prot, type);
3218 dev_err(dev, "Out of memory allocating dm-regions\n");
3221 list_add_tail(®ion->list, head);
3224 region = iommu_alloc_resv_region(MSI_RANGE_START,
3225 MSI_RANGE_END - MSI_RANGE_START + 1,
3229 list_add_tail(®ion->list, head);
3231 region = iommu_alloc_resv_region(HT_RANGE_START,
3232 HT_RANGE_END - HT_RANGE_START + 1,
3233 0, IOMMU_RESV_RESERVED);
3236 list_add_tail(®ion->list, head);
3239 static void amd_iommu_put_resv_regions(struct device *dev,
3240 struct list_head *head)
3242 struct iommu_resv_region *entry, *next;
3244 list_for_each_entry_safe(entry, next, head, list)
3248 static void amd_iommu_apply_resv_region(struct device *dev,
3249 struct iommu_domain *domain,
3250 struct iommu_resv_region *region)
3252 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3253 unsigned long start, end;
3255 start = IOVA_PFN(region->start);
3256 end = IOVA_PFN(region->start + region->length - 1);
3258 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3261 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3264 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3265 return dev_data->defer_attach;
3268 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3270 struct protection_domain *dom = to_pdomain(domain);
3271 unsigned long flags;
3273 spin_lock_irqsave(&dom->lock, flags);
3274 domain_flush_tlb_pde(dom);
3275 domain_flush_complete(dom);
3276 spin_unlock_irqrestore(&dom->lock, flags);
3279 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
3280 struct iommu_iotlb_gather *gather)
3282 amd_iommu_flush_iotlb_all(domain);
3285 const struct iommu_ops amd_iommu_ops = {
3286 .capable = amd_iommu_capable,
3287 .domain_alloc = amd_iommu_domain_alloc,
3288 .domain_free = amd_iommu_domain_free,
3289 .attach_dev = amd_iommu_attach_device,
3290 .detach_dev = amd_iommu_detach_device,
3291 .map = amd_iommu_map,
3292 .unmap = amd_iommu_unmap,
3293 .iova_to_phys = amd_iommu_iova_to_phys,
3294 .add_device = amd_iommu_add_device,
3295 .remove_device = amd_iommu_remove_device,
3296 .device_group = amd_iommu_device_group,
3297 .get_resv_regions = amd_iommu_get_resv_regions,
3298 .put_resv_regions = amd_iommu_put_resv_regions,
3299 .apply_resv_region = amd_iommu_apply_resv_region,
3300 .is_attach_deferred = amd_iommu_is_attach_deferred,
3301 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3302 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3303 .iotlb_sync = amd_iommu_iotlb_sync,
3306 /*****************************************************************************
3308 * The next functions do a basic initialization of IOMMU for pass through
3311 * In passthrough mode the IOMMU is initialized and enabled but not used for
3312 * DMA-API translation.
3314 *****************************************************************************/
3316 /* IOMMUv2 specific functions */
3317 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3319 return atomic_notifier_chain_register(&ppr_notifier, nb);
3321 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3323 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3325 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3327 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3329 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3331 struct protection_domain *domain = to_pdomain(dom);
3332 unsigned long flags;
3334 spin_lock_irqsave(&domain->lock, flags);
3336 /* Update data structure */
3337 domain->mode = PAGE_MODE_NONE;
3339 /* Make changes visible to IOMMUs */
3340 update_domain(domain);
3342 /* Page-table is not visible to IOMMU anymore, so free it */
3343 free_pagetable(domain);
3345 spin_unlock_irqrestore(&domain->lock, flags);
3347 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3349 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3351 struct protection_domain *domain = to_pdomain(dom);
3352 unsigned long flags;
3355 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3358 /* Number of GCR3 table levels required */
3359 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3362 if (levels > amd_iommu_max_glx_val)
3365 spin_lock_irqsave(&domain->lock, flags);
3368 * Save us all sanity checks whether devices already in the
3369 * domain support IOMMUv2. Just force that the domain has no
3370 * devices attached when it is switched into IOMMUv2 mode.
3373 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3377 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3378 if (domain->gcr3_tbl == NULL)
3381 domain->glx = levels;
3382 domain->flags |= PD_IOMMUV2_MASK;
3384 update_domain(domain);
3389 spin_unlock_irqrestore(&domain->lock, flags);
3393 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3395 static int __flush_pasid(struct protection_domain *domain, int pasid,
3396 u64 address, bool size)
3398 struct iommu_dev_data *dev_data;
3399 struct iommu_cmd cmd;
3402 if (!(domain->flags & PD_IOMMUV2_MASK))
3405 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3408 * IOMMU TLB needs to be flushed before Device TLB to
3409 * prevent device TLB refill from IOMMU TLB
3411 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3412 if (domain->dev_iommu[i] == 0)
3415 ret = iommu_queue_command(amd_iommus[i], &cmd);
3420 /* Wait until IOMMU TLB flushes are complete */
3421 domain_flush_complete(domain);
3423 /* Now flush device TLBs */
3424 list_for_each_entry(dev_data, &domain->dev_list, list) {
3425 struct amd_iommu *iommu;
3429 There might be non-IOMMUv2 capable devices in an IOMMUv2
3432 if (!dev_data->ats.enabled)
3435 qdep = dev_data->ats.qdep;
3436 iommu = amd_iommu_rlookup_table[dev_data->devid];
3438 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3439 qdep, address, size);
3441 ret = iommu_queue_command(iommu, &cmd);
3446 /* Wait until all device TLBs are flushed */
3447 domain_flush_complete(domain);
3456 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3459 return __flush_pasid(domain, pasid, address, false);
3462 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3465 struct protection_domain *domain = to_pdomain(dom);
3466 unsigned long flags;
3469 spin_lock_irqsave(&domain->lock, flags);
3470 ret = __amd_iommu_flush_page(domain, pasid, address);
3471 spin_unlock_irqrestore(&domain->lock, flags);
3475 EXPORT_SYMBOL(amd_iommu_flush_page);
3477 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3479 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3483 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3485 struct protection_domain *domain = to_pdomain(dom);
3486 unsigned long flags;
3489 spin_lock_irqsave(&domain->lock, flags);
3490 ret = __amd_iommu_flush_tlb(domain, pasid);
3491 spin_unlock_irqrestore(&domain->lock, flags);
3495 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3497 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3504 index = (pasid >> (9 * level)) & 0x1ff;
3510 if (!(*pte & GCR3_VALID)) {
3514 root = (void *)get_zeroed_page(GFP_ATOMIC);
3518 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3521 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3529 static int __set_gcr3(struct protection_domain *domain, int pasid,
3534 if (domain->mode != PAGE_MODE_NONE)
3537 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3541 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3543 return __amd_iommu_flush_tlb(domain, pasid);
3546 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3550 if (domain->mode != PAGE_MODE_NONE)
3553 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3559 return __amd_iommu_flush_tlb(domain, pasid);
3562 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3565 struct protection_domain *domain = to_pdomain(dom);
3566 unsigned long flags;
3569 spin_lock_irqsave(&domain->lock, flags);
3570 ret = __set_gcr3(domain, pasid, cr3);
3571 spin_unlock_irqrestore(&domain->lock, flags);
3575 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3577 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3579 struct protection_domain *domain = to_pdomain(dom);
3580 unsigned long flags;
3583 spin_lock_irqsave(&domain->lock, flags);
3584 ret = __clear_gcr3(domain, pasid);
3585 spin_unlock_irqrestore(&domain->lock, flags);
3589 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3591 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3592 int status, int tag)
3594 struct iommu_dev_data *dev_data;
3595 struct amd_iommu *iommu;
3596 struct iommu_cmd cmd;
3598 dev_data = get_dev_data(&pdev->dev);
3599 iommu = amd_iommu_rlookup_table[dev_data->devid];
3601 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3602 tag, dev_data->pri_tlp);
3604 return iommu_queue_command(iommu, &cmd);
3606 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3608 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3610 struct protection_domain *pdomain;
3612 pdomain = get_domain(&pdev->dev);
3613 if (IS_ERR(pdomain))
3616 /* Only return IOMMUv2 domains */
3617 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3620 return &pdomain->domain;
3622 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3624 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3626 struct iommu_dev_data *dev_data;
3628 if (!amd_iommu_v2_supported())
3631 dev_data = get_dev_data(&pdev->dev);
3632 dev_data->errata |= (1 << erratum);
3634 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3636 int amd_iommu_device_info(struct pci_dev *pdev,
3637 struct amd_iommu_device_info *info)
3642 if (pdev == NULL || info == NULL)
3645 if (!amd_iommu_v2_supported())
3648 memset(info, 0, sizeof(*info));
3650 if (!pci_ats_disabled()) {
3651 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3653 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3656 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3658 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3660 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3664 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3665 max_pasids = min(max_pasids, (1 << 20));
3667 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3668 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3670 features = pci_pasid_features(pdev);
3671 if (features & PCI_PASID_CAP_EXEC)
3672 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3673 if (features & PCI_PASID_CAP_PRIV)
3674 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3679 EXPORT_SYMBOL(amd_iommu_device_info);
3681 #ifdef CONFIG_IRQ_REMAP
3683 /*****************************************************************************
3685 * Interrupt Remapping Implementation
3687 *****************************************************************************/
3689 static struct irq_chip amd_ir_chip;
3690 static DEFINE_SPINLOCK(iommu_table_lock);
3692 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3696 dte = amd_iommu_dev_table[devid].data[2];
3697 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3698 dte |= iommu_virt_to_phys(table->table);
3699 dte |= DTE_IRQ_REMAP_INTCTL;
3700 dte |= DTE_IRQ_TABLE_LEN;
3701 dte |= DTE_IRQ_REMAP_ENABLE;
3703 amd_iommu_dev_table[devid].data[2] = dte;
3706 static struct irq_remap_table *get_irq_table(u16 devid)
3708 struct irq_remap_table *table;
3710 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3711 "%s: no iommu for devid %x\n", __func__, devid))
3714 table = irq_lookup_table[devid];
3715 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3721 static struct irq_remap_table *__alloc_irq_table(void)
3723 struct irq_remap_table *table;
3725 table = kzalloc(sizeof(*table), GFP_KERNEL);
3729 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3730 if (!table->table) {
3734 raw_spin_lock_init(&table->lock);
3736 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3737 memset(table->table, 0,
3738 MAX_IRQS_PER_TABLE * sizeof(u32));
3740 memset(table->table, 0,
3741 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3745 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3746 struct irq_remap_table *table)
3748 irq_lookup_table[devid] = table;
3749 set_dte_irq_entry(devid, table);
3750 iommu_flush_dte(iommu, devid);
3753 static struct irq_remap_table *alloc_irq_table(u16 devid)
3755 struct irq_remap_table *table = NULL;
3756 struct irq_remap_table *new_table = NULL;
3757 struct amd_iommu *iommu;
3758 unsigned long flags;
3761 spin_lock_irqsave(&iommu_table_lock, flags);
3763 iommu = amd_iommu_rlookup_table[devid];
3767 table = irq_lookup_table[devid];
3771 alias = amd_iommu_alias_table[devid];
3772 table = irq_lookup_table[alias];
3774 set_remap_table_entry(iommu, devid, table);
3777 spin_unlock_irqrestore(&iommu_table_lock, flags);
3779 /* Nothing there yet, allocate new irq remapping table */
3780 new_table = __alloc_irq_table();
3784 spin_lock_irqsave(&iommu_table_lock, flags);
3786 table = irq_lookup_table[devid];
3790 table = irq_lookup_table[alias];
3792 set_remap_table_entry(iommu, devid, table);
3799 set_remap_table_entry(iommu, devid, table);
3801 set_remap_table_entry(iommu, alias, table);
3804 iommu_completion_wait(iommu);
3807 spin_unlock_irqrestore(&iommu_table_lock, flags);
3810 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3816 static int alloc_irq_index(u16 devid, int count, bool align)
3818 struct irq_remap_table *table;
3819 int index, c, alignment = 1;
3820 unsigned long flags;
3821 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3826 table = alloc_irq_table(devid);
3831 alignment = roundup_pow_of_two(count);
3833 raw_spin_lock_irqsave(&table->lock, flags);
3835 /* Scan table for free entries */
3836 for (index = ALIGN(table->min_index, alignment), c = 0;
3837 index < MAX_IRQS_PER_TABLE;) {
3838 if (!iommu->irte_ops->is_allocated(table, index)) {
3842 index = ALIGN(index + 1, alignment);
3848 iommu->irte_ops->set_allocated(table, index - c + 1);
3860 raw_spin_unlock_irqrestore(&table->lock, flags);
3865 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3866 struct amd_ir_data *data)
3868 struct irq_remap_table *table;
3869 struct amd_iommu *iommu;
3870 unsigned long flags;
3871 struct irte_ga *entry;
3873 iommu = amd_iommu_rlookup_table[devid];
3877 table = get_irq_table(devid);
3881 raw_spin_lock_irqsave(&table->lock, flags);
3883 entry = (struct irte_ga *)table->table;
3884 entry = &entry[index];
3885 entry->lo.fields_remap.valid = 0;
3886 entry->hi.val = irte->hi.val;
3887 entry->lo.val = irte->lo.val;
3888 entry->lo.fields_remap.valid = 1;
3892 raw_spin_unlock_irqrestore(&table->lock, flags);
3894 iommu_flush_irt(iommu, devid);
3895 iommu_completion_wait(iommu);
3900 static int modify_irte(u16 devid, int index, union irte *irte)
3902 struct irq_remap_table *table;
3903 struct amd_iommu *iommu;
3904 unsigned long flags;
3906 iommu = amd_iommu_rlookup_table[devid];
3910 table = get_irq_table(devid);
3914 raw_spin_lock_irqsave(&table->lock, flags);
3915 table->table[index] = irte->val;
3916 raw_spin_unlock_irqrestore(&table->lock, flags);
3918 iommu_flush_irt(iommu, devid);
3919 iommu_completion_wait(iommu);
3924 static void free_irte(u16 devid, int index)
3926 struct irq_remap_table *table;
3927 struct amd_iommu *iommu;
3928 unsigned long flags;
3930 iommu = amd_iommu_rlookup_table[devid];
3934 table = get_irq_table(devid);
3938 raw_spin_lock_irqsave(&table->lock, flags);
3939 iommu->irte_ops->clear_allocated(table, index);
3940 raw_spin_unlock_irqrestore(&table->lock, flags);
3942 iommu_flush_irt(iommu, devid);
3943 iommu_completion_wait(iommu);
3946 static void irte_prepare(void *entry,
3947 u32 delivery_mode, u32 dest_mode,
3948 u8 vector, u32 dest_apicid, int devid)
3950 union irte *irte = (union irte *) entry;
3953 irte->fields.vector = vector;
3954 irte->fields.int_type = delivery_mode;
3955 irte->fields.destination = dest_apicid;
3956 irte->fields.dm = dest_mode;
3957 irte->fields.valid = 1;
3960 static void irte_ga_prepare(void *entry,
3961 u32 delivery_mode, u32 dest_mode,
3962 u8 vector, u32 dest_apicid, int devid)
3964 struct irte_ga *irte = (struct irte_ga *) entry;
3968 irte->lo.fields_remap.int_type = delivery_mode;
3969 irte->lo.fields_remap.dm = dest_mode;
3970 irte->hi.fields.vector = vector;
3971 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3972 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3973 irte->lo.fields_remap.valid = 1;
3976 static void irte_activate(void *entry, u16 devid, u16 index)
3978 union irte *irte = (union irte *) entry;
3980 irte->fields.valid = 1;
3981 modify_irte(devid, index, irte);
3984 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3986 struct irte_ga *irte = (struct irte_ga *) entry;
3988 irte->lo.fields_remap.valid = 1;
3989 modify_irte_ga(devid, index, irte, NULL);
3992 static void irte_deactivate(void *entry, u16 devid, u16 index)
3994 union irte *irte = (union irte *) entry;
3996 irte->fields.valid = 0;
3997 modify_irte(devid, index, irte);
4000 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
4002 struct irte_ga *irte = (struct irte_ga *) entry;
4004 irte->lo.fields_remap.valid = 0;
4005 modify_irte_ga(devid, index, irte, NULL);
4008 static void irte_set_affinity(void *entry, u16 devid, u16 index,
4009 u8 vector, u32 dest_apicid)
4011 union irte *irte = (union irte *) entry;
4013 irte->fields.vector = vector;
4014 irte->fields.destination = dest_apicid;
4015 modify_irte(devid, index, irte);
4018 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
4019 u8 vector, u32 dest_apicid)
4021 struct irte_ga *irte = (struct irte_ga *) entry;
4023 if (!irte->lo.fields_remap.guest_mode) {
4024 irte->hi.fields.vector = vector;
4025 irte->lo.fields_remap.destination =
4026 APICID_TO_IRTE_DEST_LO(dest_apicid);
4027 irte->hi.fields.destination =
4028 APICID_TO_IRTE_DEST_HI(dest_apicid);
4029 modify_irte_ga(devid, index, irte, NULL);
4033 #define IRTE_ALLOCATED (~1U)
4034 static void irte_set_allocated(struct irq_remap_table *table, int index)
4036 table->table[index] = IRTE_ALLOCATED;
4039 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
4041 struct irte_ga *ptr = (struct irte_ga *)table->table;
4042 struct irte_ga *irte = &ptr[index];
4044 memset(&irte->lo.val, 0, sizeof(u64));
4045 memset(&irte->hi.val, 0, sizeof(u64));
4046 irte->hi.fields.vector = 0xff;
4049 static bool irte_is_allocated(struct irq_remap_table *table, int index)
4051 union irte *ptr = (union irte *)table->table;
4052 union irte *irte = &ptr[index];
4054 return irte->val != 0;
4057 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4059 struct irte_ga *ptr = (struct irte_ga *)table->table;
4060 struct irte_ga *irte = &ptr[index];
4062 return irte->hi.fields.vector != 0;
4065 static void irte_clear_allocated(struct irq_remap_table *table, int index)
4067 table->table[index] = 0;
4070 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4072 struct irte_ga *ptr = (struct irte_ga *)table->table;
4073 struct irte_ga *irte = &ptr[index];
4075 memset(&irte->lo.val, 0, sizeof(u64));
4076 memset(&irte->hi.val, 0, sizeof(u64));
4079 static int get_devid(struct irq_alloc_info *info)
4083 switch (info->type) {
4084 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4085 devid = get_ioapic_devid(info->ioapic_id);
4087 case X86_IRQ_ALLOC_TYPE_HPET:
4088 devid = get_hpet_devid(info->hpet_id);
4090 case X86_IRQ_ALLOC_TYPE_MSI:
4091 case X86_IRQ_ALLOC_TYPE_MSIX:
4092 devid = get_device_id(&info->msi_dev->dev);
4102 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4104 struct amd_iommu *iommu;
4110 devid = get_devid(info);
4112 iommu = amd_iommu_rlookup_table[devid];
4114 return iommu->ir_domain;
4120 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4122 struct amd_iommu *iommu;
4128 switch (info->type) {
4129 case X86_IRQ_ALLOC_TYPE_MSI:
4130 case X86_IRQ_ALLOC_TYPE_MSIX:
4131 devid = get_device_id(&info->msi_dev->dev);
4135 iommu = amd_iommu_rlookup_table[devid];
4137 return iommu->msi_domain;
4146 struct irq_remap_ops amd_iommu_irq_ops = {
4147 .prepare = amd_iommu_prepare,
4148 .enable = amd_iommu_enable,
4149 .disable = amd_iommu_disable,
4150 .reenable = amd_iommu_reenable,
4151 .enable_faulting = amd_iommu_enable_faulting,
4152 .get_ir_irq_domain = get_ir_irq_domain,
4153 .get_irq_domain = get_irq_domain,
4156 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4157 struct irq_cfg *irq_cfg,
4158 struct irq_alloc_info *info,
4159 int devid, int index, int sub_handle)
4161 struct irq_2_irte *irte_info = &data->irq_2_irte;
4162 struct msi_msg *msg = &data->msi_entry;
4163 struct IO_APIC_route_entry *entry;
4164 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4169 data->irq_2_irte.devid = devid;
4170 data->irq_2_irte.index = index + sub_handle;
4171 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4172 apic->irq_dest_mode, irq_cfg->vector,
4173 irq_cfg->dest_apicid, devid);
4175 switch (info->type) {
4176 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4177 /* Setup IOAPIC entry */
4178 entry = info->ioapic_entry;
4179 info->ioapic_entry = NULL;
4180 memset(entry, 0, sizeof(*entry));
4181 entry->vector = index;
4183 entry->trigger = info->ioapic_trigger;
4184 entry->polarity = info->ioapic_polarity;
4185 /* Mask level triggered irqs. */
4186 if (info->ioapic_trigger)
4190 case X86_IRQ_ALLOC_TYPE_HPET:
4191 case X86_IRQ_ALLOC_TYPE_MSI:
4192 case X86_IRQ_ALLOC_TYPE_MSIX:
4193 msg->address_hi = MSI_ADDR_BASE_HI;
4194 msg->address_lo = MSI_ADDR_BASE_LO;
4195 msg->data = irte_info->index;
4204 struct amd_irte_ops irte_32_ops = {
4205 .prepare = irte_prepare,
4206 .activate = irte_activate,
4207 .deactivate = irte_deactivate,
4208 .set_affinity = irte_set_affinity,
4209 .set_allocated = irte_set_allocated,
4210 .is_allocated = irte_is_allocated,
4211 .clear_allocated = irte_clear_allocated,
4214 struct amd_irte_ops irte_128_ops = {
4215 .prepare = irte_ga_prepare,
4216 .activate = irte_ga_activate,
4217 .deactivate = irte_ga_deactivate,
4218 .set_affinity = irte_ga_set_affinity,
4219 .set_allocated = irte_ga_set_allocated,
4220 .is_allocated = irte_ga_is_allocated,
4221 .clear_allocated = irte_ga_clear_allocated,
4224 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4225 unsigned int nr_irqs, void *arg)
4227 struct irq_alloc_info *info = arg;
4228 struct irq_data *irq_data;
4229 struct amd_ir_data *data = NULL;
4230 struct irq_cfg *cfg;
4236 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4237 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4241 * With IRQ remapping enabled, don't need contiguous CPU vectors
4242 * to support multiple MSI interrupts.
4244 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4245 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4247 devid = get_devid(info);
4251 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4255 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4256 struct irq_remap_table *table;
4257 struct amd_iommu *iommu;
4259 table = alloc_irq_table(devid);
4261 if (!table->min_index) {
4263 * Keep the first 32 indexes free for IOAPIC
4266 table->min_index = 32;
4267 iommu = amd_iommu_rlookup_table[devid];
4268 for (i = 0; i < 32; ++i)
4269 iommu->irte_ops->set_allocated(table, i);
4271 WARN_ON(table->min_index != 32);
4272 index = info->ioapic_pin;
4277 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4279 index = alloc_irq_index(devid, nr_irqs, align);
4282 pr_warn("Failed to allocate IRTE\n");
4284 goto out_free_parent;
4287 for (i = 0; i < nr_irqs; i++) {
4288 irq_data = irq_domain_get_irq_data(domain, virq + i);
4289 cfg = irqd_cfg(irq_data);
4290 if (!irq_data || !cfg) {
4296 data = kzalloc(sizeof(*data), GFP_KERNEL);
4300 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4301 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4303 data->entry = kzalloc(sizeof(struct irte_ga),
4310 irq_data->hwirq = (devid << 16) + i;
4311 irq_data->chip_data = data;
4312 irq_data->chip = &amd_ir_chip;
4313 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4314 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4320 for (i--; i >= 0; i--) {
4321 irq_data = irq_domain_get_irq_data(domain, virq + i);
4323 kfree(irq_data->chip_data);
4325 for (i = 0; i < nr_irqs; i++)
4326 free_irte(devid, index + i);
4328 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4332 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4333 unsigned int nr_irqs)
4335 struct irq_2_irte *irte_info;
4336 struct irq_data *irq_data;
4337 struct amd_ir_data *data;
4340 for (i = 0; i < nr_irqs; i++) {
4341 irq_data = irq_domain_get_irq_data(domain, virq + i);
4342 if (irq_data && irq_data->chip_data) {
4343 data = irq_data->chip_data;
4344 irte_info = &data->irq_2_irte;
4345 free_irte(irte_info->devid, irte_info->index);
4350 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4353 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4354 struct amd_ir_data *ir_data,
4355 struct irq_2_irte *irte_info,
4356 struct irq_cfg *cfg);
4358 static int irq_remapping_activate(struct irq_domain *domain,
4359 struct irq_data *irq_data, bool reserve)
4361 struct amd_ir_data *data = irq_data->chip_data;
4362 struct irq_2_irte *irte_info = &data->irq_2_irte;
4363 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4364 struct irq_cfg *cfg = irqd_cfg(irq_data);
4369 iommu->irte_ops->activate(data->entry, irte_info->devid,
4371 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4375 static void irq_remapping_deactivate(struct irq_domain *domain,
4376 struct irq_data *irq_data)
4378 struct amd_ir_data *data = irq_data->chip_data;
4379 struct irq_2_irte *irte_info = &data->irq_2_irte;
4380 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4383 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4387 static const struct irq_domain_ops amd_ir_domain_ops = {
4388 .alloc = irq_remapping_alloc,
4389 .free = irq_remapping_free,
4390 .activate = irq_remapping_activate,
4391 .deactivate = irq_remapping_deactivate,
4394 int amd_iommu_activate_guest_mode(void *data)
4396 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4397 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4399 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4400 !entry || entry->lo.fields_vapic.guest_mode)
4406 entry->lo.fields_vapic.guest_mode = 1;
4407 entry->lo.fields_vapic.ga_log_intr = 1;
4408 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
4409 entry->hi.fields.vector = ir_data->ga_vector;
4410 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
4412 return modify_irte_ga(ir_data->irq_2_irte.devid,
4413 ir_data->irq_2_irte.index, entry, NULL);
4415 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
4417 int amd_iommu_deactivate_guest_mode(void *data)
4419 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4420 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4421 struct irq_cfg *cfg = ir_data->cfg;
4423 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4424 !entry || !entry->lo.fields_vapic.guest_mode)
4430 entry->lo.fields_remap.dm = apic->irq_dest_mode;
4431 entry->lo.fields_remap.int_type = apic->irq_delivery_mode;
4432 entry->hi.fields.vector = cfg->vector;
4433 entry->lo.fields_remap.destination =
4434 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4435 entry->hi.fields.destination =
4436 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4438 return modify_irte_ga(ir_data->irq_2_irte.devid,
4439 ir_data->irq_2_irte.index, entry, NULL);
4441 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
4443 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4446 struct amd_iommu *iommu;
4447 struct amd_iommu_pi_data *pi_data = vcpu_info;
4448 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4449 struct amd_ir_data *ir_data = data->chip_data;
4450 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4451 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4454 * This device has never been set up for guest mode.
4455 * we should not modify the IRTE
4457 if (!dev_data || !dev_data->use_vapic)
4460 ir_data->cfg = irqd_cfg(data);
4461 pi_data->ir_data = ir_data;
4464 * SVM tries to set up for VAPIC mode, but we are in
4465 * legacy mode. So, we force legacy mode instead.
4467 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4468 pr_debug("%s: Fall back to using intr legacy remap\n",
4470 pi_data->is_guest_mode = false;
4473 iommu = amd_iommu_rlookup_table[irte_info->devid];
4477 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4478 if (pi_data->is_guest_mode) {
4479 ir_data->ga_root_ptr = (pi_data->base >> 12);
4480 ir_data->ga_vector = vcpu_pi_info->vector;
4481 ir_data->ga_tag = pi_data->ga_tag;
4482 ret = amd_iommu_activate_guest_mode(ir_data);
4484 ir_data->cached_ga_tag = pi_data->ga_tag;
4486 ret = amd_iommu_deactivate_guest_mode(ir_data);
4489 * This communicates the ga_tag back to the caller
4490 * so that it can do all the necessary clean up.
4493 ir_data->cached_ga_tag = 0;
4500 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4501 struct amd_ir_data *ir_data,
4502 struct irq_2_irte *irte_info,
4503 struct irq_cfg *cfg)
4507 * Atomically updates the IRTE with the new destination, vector
4508 * and flushes the interrupt entry cache.
4510 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4511 irte_info->index, cfg->vector,
4515 static int amd_ir_set_affinity(struct irq_data *data,
4516 const struct cpumask *mask, bool force)
4518 struct amd_ir_data *ir_data = data->chip_data;
4519 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4520 struct irq_cfg *cfg = irqd_cfg(data);
4521 struct irq_data *parent = data->parent_data;
4522 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4528 ret = parent->chip->irq_set_affinity(parent, mask, force);
4529 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4532 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4534 * After this point, all the interrupts will start arriving
4535 * at the new destination. So, time to cleanup the previous
4536 * vector allocation.
4538 send_cleanup_vector(cfg);
4540 return IRQ_SET_MASK_OK_DONE;
4543 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4545 struct amd_ir_data *ir_data = irq_data->chip_data;
4547 *msg = ir_data->msi_entry;
4550 static struct irq_chip amd_ir_chip = {
4552 .irq_ack = apic_ack_irq,
4553 .irq_set_affinity = amd_ir_set_affinity,
4554 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4555 .irq_compose_msi_msg = ir_compose_msi_msg,
4558 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4560 struct fwnode_handle *fn;
4562 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4565 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4566 irq_domain_free_fwnode(fn);
4567 if (!iommu->ir_domain)
4570 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4571 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4577 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4579 unsigned long flags;
4580 struct amd_iommu *iommu;
4581 struct irq_remap_table *table;
4582 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4583 int devid = ir_data->irq_2_irte.devid;
4584 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4585 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4587 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4588 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4591 iommu = amd_iommu_rlookup_table[devid];
4595 table = get_irq_table(devid);
4599 raw_spin_lock_irqsave(&table->lock, flags);
4601 if (ref->lo.fields_vapic.guest_mode) {
4603 ref->lo.fields_vapic.destination =
4604 APICID_TO_IRTE_DEST_LO(cpu);
4605 ref->hi.fields.destination =
4606 APICID_TO_IRTE_DEST_HI(cpu);
4608 ref->lo.fields_vapic.is_run = is_run;
4612 raw_spin_unlock_irqrestore(&table->lock, flags);
4614 iommu_flush_irt(iommu, devid);
4615 iommu_completion_wait(iommu);
4618 EXPORT_SYMBOL(amd_iommu_update_ga);