1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm SDM630/SDM636/SDM660 Network-on-Chip (NoC) QoS driver
4 * Copyright (C) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
7 #include <dt-bindings/interconnect/qcom,sdm660.h>
9 #include <linux/device.h>
10 #include <linux/interconnect-provider.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
23 SDM660_MASTER_IPA = 1,
24 SDM660_MASTER_CNOC_A2NOC,
32 SDM660_MASTER_CRYPTO_C0,
33 SDM660_MASTER_GNOC_BIMC,
35 SDM660_MASTER_MNOC_BIMC,
36 SDM660_MASTER_SNOC_BIMC,
38 SDM660_MASTER_SNOC_CNOC,
39 SDM660_MASTER_QDSS_DAP,
40 SDM660_MASTER_APPS_PROC,
41 SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
42 SDM660_MASTER_CNOC_MNOC_CFG,
49 SDM660_MASTER_QDSS_ETR,
50 SDM660_MASTER_QDSS_BAM,
51 SDM660_MASTER_SNOC_CFG,
52 SDM660_MASTER_BIMC_SNOC,
53 SDM660_MASTER_A2NOC_SNOC,
54 SDM660_MASTER_GNOC_SNOC,
56 SDM660_SLAVE_A2NOC_SNOC,
59 SDM660_SLAVE_BIMC_SNOC,
60 SDM660_SLAVE_CNOC_A2NOC,
62 SDM660_SLAVE_PMIC_ARB,
63 SDM660_SLAVE_TLMM_NORTH,
65 SDM660_SLAVE_PIMEM_CFG,
66 SDM660_SLAVE_IMEM_CFG,
67 SDM660_SLAVE_MESSAGE_RAM,
69 SDM660_SLAVE_BIMC_CFG,
72 SDM660_SLAVE_QDSS_CFG,
73 SDM660_SLAVE_CNOC_MNOC_CFG,
74 SDM660_SLAVE_SNOC_CFG,
78 SDM660_SLAVE_TLMM_SOUTH,
80 SDM660_SLAVE_A2NOC_CFG,
81 SDM660_SLAVE_A2NOC_SMMU_CFG,
82 SDM660_SLAVE_GPUSS_CFG,
87 SDM660_SLAVE_TLMM_CENTER,
90 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
93 SDM660_SLAVE_SRVC_CNOC,
94 SDM660_SLAVE_GNOC_BIMC,
95 SDM660_SLAVE_GNOC_SNOC,
96 SDM660_SLAVE_CAMERA_CFG,
97 SDM660_SLAVE_CAMERA_THROTTLE_CFG,
98 SDM660_SLAVE_MISC_CFG,
99 SDM660_SLAVE_VENUS_THROTTLE_CFG,
100 SDM660_SLAVE_VENUS_CFG,
101 SDM660_SLAVE_MMSS_CLK_XPU_CFG,
102 SDM660_SLAVE_MMSS_CLK_CFG,
103 SDM660_SLAVE_MNOC_MPU_CFG,
104 SDM660_SLAVE_DISPLAY_CFG,
105 SDM660_SLAVE_CSI_PHY_CFG,
106 SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
107 SDM660_SLAVE_SMMU_CFG,
108 SDM660_SLAVE_MNOC_BIMC,
109 SDM660_SLAVE_SRVC_MNOC,
115 SDM660_SLAVE_SNOC_BIMC,
116 SDM660_SLAVE_SNOC_CNOC,
119 SDM660_SLAVE_QDSS_STM,
120 SDM660_SLAVE_SRVC_SNOC,
130 static const char * const bus_mm_clocks[] = {
136 static const char * const bus_a2noc_clocks[] = {
146 static const u16 mas_ipa_links[] = {
147 SDM660_SLAVE_A2NOC_SNOC
150 static struct qcom_icc_node mas_ipa = {
152 .id = SDM660_MASTER_IPA,
156 .qos.ap_owned = true,
157 .qos.qos_mode = NOC_QOS_MODE_FIXED,
161 .num_links = ARRAY_SIZE(mas_ipa_links),
162 .links = mas_ipa_links,
165 static const u16 mas_cnoc_a2noc_links[] = {
166 SDM660_SLAVE_A2NOC_SNOC
169 static struct qcom_icc_node mas_cnoc_a2noc = {
170 .name = "mas_cnoc_a2noc",
171 .id = SDM660_MASTER_CNOC_A2NOC,
175 .qos.ap_owned = true,
176 .qos.qos_mode = NOC_QOS_MODE_INVALID,
177 .num_links = ARRAY_SIZE(mas_cnoc_a2noc_links),
178 .links = mas_cnoc_a2noc_links,
181 static const u16 mas_sdcc_1_links[] = {
182 SDM660_SLAVE_A2NOC_SNOC
185 static struct qcom_icc_node mas_sdcc_1 = {
186 .name = "mas_sdcc_1",
187 .id = SDM660_MASTER_SDCC_1,
191 .num_links = ARRAY_SIZE(mas_sdcc_1_links),
192 .links = mas_sdcc_1_links,
195 static const u16 mas_sdcc_2_links[] = {
196 SDM660_SLAVE_A2NOC_SNOC
199 static struct qcom_icc_node mas_sdcc_2 = {
200 .name = "mas_sdcc_2",
201 .id = SDM660_MASTER_SDCC_2,
205 .num_links = ARRAY_SIZE(mas_sdcc_2_links),
206 .links = mas_sdcc_2_links,
209 static const u16 mas_blsp_1_links[] = {
210 SDM660_SLAVE_A2NOC_SNOC
213 static struct qcom_icc_node mas_blsp_1 = {
214 .name = "mas_blsp_1",
215 .id = SDM660_MASTER_BLSP_1,
219 .num_links = ARRAY_SIZE(mas_blsp_1_links),
220 .links = mas_blsp_1_links,
223 static const u16 mas_blsp_2_links[] = {
224 SDM660_SLAVE_A2NOC_SNOC
227 static struct qcom_icc_node mas_blsp_2 = {
228 .name = "mas_blsp_2",
229 .id = SDM660_MASTER_BLSP_2,
233 .num_links = ARRAY_SIZE(mas_blsp_2_links),
234 .links = mas_blsp_2_links,
237 static const u16 mas_ufs_links[] = {
238 SDM660_SLAVE_A2NOC_SNOC
241 static struct qcom_icc_node mas_ufs = {
243 .id = SDM660_MASTER_UFS,
247 .qos.ap_owned = true,
248 .qos.qos_mode = NOC_QOS_MODE_FIXED,
252 .num_links = ARRAY_SIZE(mas_ufs_links),
253 .links = mas_ufs_links,
256 static const u16 mas_usb_hs_links[] = {
257 SDM660_SLAVE_A2NOC_SNOC
260 static struct qcom_icc_node mas_usb_hs = {
261 .name = "mas_usb_hs",
262 .id = SDM660_MASTER_USB_HS,
266 .qos.ap_owned = true,
267 .qos.qos_mode = NOC_QOS_MODE_FIXED,
271 .num_links = ARRAY_SIZE(mas_usb_hs_links),
272 .links = mas_usb_hs_links,
275 static const u16 mas_usb3_links[] = {
276 SDM660_SLAVE_A2NOC_SNOC
279 static struct qcom_icc_node mas_usb3 = {
281 .id = SDM660_MASTER_USB3,
285 .qos.ap_owned = true,
286 .qos.qos_mode = NOC_QOS_MODE_FIXED,
290 .num_links = ARRAY_SIZE(mas_usb3_links),
291 .links = mas_usb3_links,
294 static const u16 mas_crypto_links[] = {
295 SDM660_SLAVE_A2NOC_SNOC
298 static struct qcom_icc_node mas_crypto = {
299 .name = "mas_crypto",
300 .id = SDM660_MASTER_CRYPTO_C0,
304 .qos.ap_owned = true,
305 .qos.qos_mode = NOC_QOS_MODE_FIXED,
309 .num_links = ARRAY_SIZE(mas_crypto_links),
310 .links = mas_crypto_links,
313 static const u16 mas_gnoc_bimc_links[] = {
317 static struct qcom_icc_node mas_gnoc_bimc = {
318 .name = "mas_gnoc_bimc",
319 .id = SDM660_MASTER_GNOC_BIMC,
323 .qos.ap_owned = true,
324 .qos.qos_mode = NOC_QOS_MODE_FIXED,
328 .num_links = ARRAY_SIZE(mas_gnoc_bimc_links),
329 .links = mas_gnoc_bimc_links,
332 static const u16 mas_oxili_links[] = {
333 SDM660_SLAVE_HMSS_L3,
335 SDM660_SLAVE_BIMC_SNOC
338 static struct qcom_icc_node mas_oxili = {
340 .id = SDM660_MASTER_OXILI,
344 .qos.ap_owned = true,
345 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
349 .num_links = ARRAY_SIZE(mas_oxili_links),
350 .links = mas_oxili_links,
353 static const u16 mas_mnoc_bimc_links[] = {
354 SDM660_SLAVE_HMSS_L3,
356 SDM660_SLAVE_BIMC_SNOC
359 static struct qcom_icc_node mas_mnoc_bimc = {
360 .name = "mas_mnoc_bimc",
361 .id = SDM660_MASTER_MNOC_BIMC,
365 .qos.ap_owned = true,
366 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
370 .num_links = ARRAY_SIZE(mas_mnoc_bimc_links),
371 .links = mas_mnoc_bimc_links,
374 static const u16 mas_snoc_bimc_links[] = {
375 SDM660_SLAVE_HMSS_L3,
379 static struct qcom_icc_node mas_snoc_bimc = {
380 .name = "mas_snoc_bimc",
381 .id = SDM660_MASTER_SNOC_BIMC,
385 .num_links = ARRAY_SIZE(mas_snoc_bimc_links),
386 .links = mas_snoc_bimc_links,
389 static const u16 mas_pimem_links[] = {
390 SDM660_SLAVE_HMSS_L3,
394 static struct qcom_icc_node mas_pimem = {
396 .id = SDM660_MASTER_PIMEM,
400 .qos.ap_owned = true,
401 .qos.qos_mode = NOC_QOS_MODE_FIXED,
405 .num_links = ARRAY_SIZE(mas_pimem_links),
406 .links = mas_pimem_links,
409 static const u16 mas_snoc_cnoc_links[] = {
410 SDM660_SLAVE_CLK_CTL,
411 SDM660_SLAVE_QDSS_CFG,
413 SDM660_SLAVE_SRVC_CNOC,
414 SDM660_SLAVE_UFS_CFG,
416 SDM660_SLAVE_A2NOC_SMMU_CFG,
417 SDM660_SLAVE_SNOC_CFG,
418 SDM660_SLAVE_TLMM_SOUTH,
420 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
424 SDM660_SLAVE_PMIC_ARB,
426 SDM660_SLAVE_MSS_CFG,
427 SDM660_SLAVE_GPUSS_CFG,
428 SDM660_SLAVE_IMEM_CFG,
430 SDM660_SLAVE_A2NOC_CFG,
431 SDM660_SLAVE_TLMM_NORTH,
434 SDM660_SLAVE_TLMM_CENTER,
435 SDM660_SLAVE_AHB2PHY,
438 SDM660_SLAVE_PIMEM_CFG,
440 SDM660_SLAVE_MESSAGE_RAM,
441 SDM660_SLAVE_BIMC_CFG,
442 SDM660_SLAVE_CNOC_MNOC_CFG
445 static struct qcom_icc_node mas_snoc_cnoc = {
446 .name = "mas_snoc_cnoc",
447 .id = SDM660_MASTER_SNOC_CNOC,
451 .qos.ap_owned = true,
452 .qos.qos_mode = NOC_QOS_MODE_INVALID,
453 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
454 .links = mas_snoc_cnoc_links,
457 static const u16 mas_qdss_dap_links[] = {
458 SDM660_SLAVE_CLK_CTL,
459 SDM660_SLAVE_QDSS_CFG,
461 SDM660_SLAVE_SRVC_CNOC,
462 SDM660_SLAVE_UFS_CFG,
464 SDM660_SLAVE_A2NOC_SMMU_CFG,
465 SDM660_SLAVE_SNOC_CFG,
466 SDM660_SLAVE_TLMM_SOUTH,
468 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
472 SDM660_SLAVE_PMIC_ARB,
474 SDM660_SLAVE_MSS_CFG,
475 SDM660_SLAVE_GPUSS_CFG,
476 SDM660_SLAVE_IMEM_CFG,
478 SDM660_SLAVE_A2NOC_CFG,
479 SDM660_SLAVE_TLMM_NORTH,
482 SDM660_SLAVE_TLMM_CENTER,
483 SDM660_SLAVE_AHB2PHY,
486 SDM660_SLAVE_PIMEM_CFG,
488 SDM660_SLAVE_MESSAGE_RAM,
489 SDM660_SLAVE_CNOC_A2NOC,
490 SDM660_SLAVE_BIMC_CFG,
491 SDM660_SLAVE_CNOC_MNOC_CFG
494 static struct qcom_icc_node mas_qdss_dap = {
495 .name = "mas_qdss_dap",
496 .id = SDM660_MASTER_QDSS_DAP,
500 .qos.ap_owned = true,
501 .qos.qos_mode = NOC_QOS_MODE_INVALID,
502 .num_links = ARRAY_SIZE(mas_qdss_dap_links),
503 .links = mas_qdss_dap_links,
506 static const u16 mas_apss_proc_links[] = {
507 SDM660_SLAVE_GNOC_SNOC,
508 SDM660_SLAVE_GNOC_BIMC
511 static struct qcom_icc_node mas_apss_proc = {
512 .name = "mas_apss_proc",
513 .id = SDM660_MASTER_APPS_PROC,
517 .qos.ap_owned = true,
518 .qos.qos_mode = NOC_QOS_MODE_INVALID,
519 .num_links = ARRAY_SIZE(mas_apss_proc_links),
520 .links = mas_apss_proc_links,
523 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = {
524 SDM660_SLAVE_VENUS_THROTTLE_CFG,
525 SDM660_SLAVE_VENUS_CFG,
526 SDM660_SLAVE_CAMERA_THROTTLE_CFG,
527 SDM660_SLAVE_SMMU_CFG,
528 SDM660_SLAVE_CAMERA_CFG,
529 SDM660_SLAVE_CSI_PHY_CFG,
530 SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
531 SDM660_SLAVE_DISPLAY_CFG,
532 SDM660_SLAVE_MMSS_CLK_CFG,
533 SDM660_SLAVE_MNOC_MPU_CFG,
534 SDM660_SLAVE_MISC_CFG,
535 SDM660_SLAVE_MMSS_CLK_XPU_CFG
538 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
539 .name = "mas_cnoc_mnoc_mmss_cfg",
540 .id = SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
544 .qos.ap_owned = true,
545 .qos.qos_mode = NOC_QOS_MODE_INVALID,
546 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links),
547 .links = mas_cnoc_mnoc_mmss_cfg_links,
550 static const u16 mas_cnoc_mnoc_cfg_links[] = {
551 SDM660_SLAVE_SRVC_MNOC
554 static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
555 .name = "mas_cnoc_mnoc_cfg",
556 .id = SDM660_MASTER_CNOC_MNOC_CFG,
560 .qos.ap_owned = true,
561 .qos.qos_mode = NOC_QOS_MODE_INVALID,
562 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links),
563 .links = mas_cnoc_mnoc_cfg_links,
566 static const u16 mas_cpp_links[] = {
567 SDM660_SLAVE_MNOC_BIMC
570 static struct qcom_icc_node mas_cpp = {
572 .id = SDM660_MASTER_CPP,
576 .qos.ap_owned = true,
577 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
581 .num_links = ARRAY_SIZE(mas_cpp_links),
582 .links = mas_cpp_links,
585 static const u16 mas_jpeg_links[] = {
586 SDM660_SLAVE_MNOC_BIMC
589 static struct qcom_icc_node mas_jpeg = {
591 .id = SDM660_MASTER_JPEG,
595 .qos.ap_owned = true,
596 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
600 .num_links = ARRAY_SIZE(mas_jpeg_links),
601 .links = mas_jpeg_links,
604 static const u16 mas_mdp_p0_links[] = {
605 SDM660_SLAVE_MNOC_BIMC
608 static struct qcom_icc_node mas_mdp_p0 = {
609 .name = "mas_mdp_p0",
610 .id = SDM660_MASTER_MDP_P0,
614 .qos.ap_owned = true,
615 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
619 .num_links = ARRAY_SIZE(mas_mdp_p0_links),
620 .links = mas_mdp_p0_links,
623 static const u16 mas_mdp_p1_links[] = {
624 SDM660_SLAVE_MNOC_BIMC
627 static struct qcom_icc_node mas_mdp_p1 = {
628 .name = "mas_mdp_p1",
629 .id = SDM660_MASTER_MDP_P1,
633 .qos.ap_owned = true,
634 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
638 .num_links = ARRAY_SIZE(mas_mdp_p1_links),
639 .links = mas_mdp_p1_links,
642 static const u16 mas_venus_links[] = {
643 SDM660_SLAVE_MNOC_BIMC
646 static struct qcom_icc_node mas_venus = {
648 .id = SDM660_MASTER_VENUS,
652 .qos.ap_owned = true,
653 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
657 .num_links = ARRAY_SIZE(mas_venus_links),
658 .links = mas_venus_links,
661 static const u16 mas_vfe_links[] = {
662 SDM660_SLAVE_MNOC_BIMC
665 static struct qcom_icc_node mas_vfe = {
667 .id = SDM660_MASTER_VFE,
671 .qos.ap_owned = true,
672 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
676 .num_links = ARRAY_SIZE(mas_vfe_links),
677 .links = mas_vfe_links,
680 static const u16 mas_qdss_etr_links[] = {
683 SDM660_SLAVE_SNOC_CNOC,
684 SDM660_SLAVE_SNOC_BIMC
687 static struct qcom_icc_node mas_qdss_etr = {
688 .name = "mas_qdss_etr",
689 .id = SDM660_MASTER_QDSS_ETR,
693 .qos.ap_owned = true,
694 .qos.qos_mode = NOC_QOS_MODE_FIXED,
698 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
699 .links = mas_qdss_etr_links,
702 static const u16 mas_qdss_bam_links[] = {
705 SDM660_SLAVE_SNOC_CNOC,
706 SDM660_SLAVE_SNOC_BIMC
709 static struct qcom_icc_node mas_qdss_bam = {
710 .name = "mas_qdss_bam",
711 .id = SDM660_MASTER_QDSS_BAM,
715 .qos.ap_owned = true,
716 .qos.qos_mode = NOC_QOS_MODE_FIXED,
720 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
721 .links = mas_qdss_bam_links,
724 static const u16 mas_snoc_cfg_links[] = {
725 SDM660_SLAVE_SRVC_SNOC
728 static struct qcom_icc_node mas_snoc_cfg = {
729 .name = "mas_snoc_cfg",
730 .id = SDM660_MASTER_SNOC_CFG,
734 .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
735 .links = mas_snoc_cfg_links,
738 static const u16 mas_bimc_snoc_links[] = {
741 SDM660_SLAVE_QDSS_STM,
745 SDM660_SLAVE_SNOC_CNOC,
750 static struct qcom_icc_node mas_bimc_snoc = {
751 .name = "mas_bimc_snoc",
752 .id = SDM660_MASTER_BIMC_SNOC,
756 .num_links = ARRAY_SIZE(mas_bimc_snoc_links),
757 .links = mas_bimc_snoc_links,
760 static const u16 mas_gnoc_snoc_links[] = {
763 SDM660_SLAVE_QDSS_STM,
767 SDM660_SLAVE_SNOC_CNOC,
772 static struct qcom_icc_node mas_gnoc_snoc = {
773 .name = "mas_gnoc_snoc",
774 .id = SDM660_MASTER_GNOC_SNOC,
778 .num_links = ARRAY_SIZE(mas_gnoc_snoc_links),
779 .links = mas_gnoc_snoc_links,
782 static const u16 mas_a2noc_snoc_links[] = {
785 SDM660_SLAVE_QDSS_STM,
788 SDM660_SLAVE_SNOC_BIMC,
790 SDM660_SLAVE_SNOC_CNOC,
795 static struct qcom_icc_node mas_a2noc_snoc = {
796 .name = "mas_a2noc_snoc",
797 .id = SDM660_MASTER_A2NOC_SNOC,
801 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links),
802 .links = mas_a2noc_snoc_links,
805 static const u16 slv_a2noc_snoc_links[] = {
806 SDM660_MASTER_A2NOC_SNOC
809 static struct qcom_icc_node slv_a2noc_snoc = {
810 .name = "slv_a2noc_snoc",
811 .id = SDM660_SLAVE_A2NOC_SNOC,
815 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links),
816 .links = slv_a2noc_snoc_links,
819 static struct qcom_icc_node slv_ebi = {
821 .id = SDM660_SLAVE_EBI,
827 static struct qcom_icc_node slv_hmss_l3 = {
828 .name = "slv_hmss_l3",
829 .id = SDM660_SLAVE_HMSS_L3,
835 static const u16 slv_bimc_snoc_links[] = {
836 SDM660_MASTER_BIMC_SNOC
839 static struct qcom_icc_node slv_bimc_snoc = {
840 .name = "slv_bimc_snoc",
841 .id = SDM660_SLAVE_BIMC_SNOC,
845 .num_links = ARRAY_SIZE(slv_bimc_snoc_links),
846 .links = slv_bimc_snoc_links,
849 static const u16 slv_cnoc_a2noc_links[] = {
850 SDM660_MASTER_CNOC_A2NOC
853 static struct qcom_icc_node slv_cnoc_a2noc = {
854 .name = "slv_cnoc_a2noc",
855 .id = SDM660_SLAVE_CNOC_A2NOC,
859 .qos.ap_owned = true,
860 .qos.qos_mode = NOC_QOS_MODE_INVALID,
861 .num_links = ARRAY_SIZE(slv_cnoc_a2noc_links),
862 .links = slv_cnoc_a2noc_links,
865 static struct qcom_icc_node slv_mpm = {
867 .id = SDM660_SLAVE_MPM,
871 .qos.ap_owned = true,
872 .qos.qos_mode = NOC_QOS_MODE_INVALID,
875 static struct qcom_icc_node slv_pmic_arb = {
876 .name = "slv_pmic_arb",
877 .id = SDM660_SLAVE_PMIC_ARB,
881 .qos.ap_owned = true,
882 .qos.qos_mode = NOC_QOS_MODE_INVALID,
885 static struct qcom_icc_node slv_tlmm_north = {
886 .name = "slv_tlmm_north",
887 .id = SDM660_SLAVE_TLMM_NORTH,
891 .qos.ap_owned = true,
892 .qos.qos_mode = NOC_QOS_MODE_INVALID,
895 static struct qcom_icc_node slv_tcsr = {
897 .id = SDM660_SLAVE_TCSR,
901 .qos.ap_owned = true,
902 .qos.qos_mode = NOC_QOS_MODE_INVALID,
905 static struct qcom_icc_node slv_pimem_cfg = {
906 .name = "slv_pimem_cfg",
907 .id = SDM660_SLAVE_PIMEM_CFG,
911 .qos.ap_owned = true,
912 .qos.qos_mode = NOC_QOS_MODE_INVALID,
915 static struct qcom_icc_node slv_imem_cfg = {
916 .name = "slv_imem_cfg",
917 .id = SDM660_SLAVE_IMEM_CFG,
921 .qos.ap_owned = true,
922 .qos.qos_mode = NOC_QOS_MODE_INVALID,
925 static struct qcom_icc_node slv_message_ram = {
926 .name = "slv_message_ram",
927 .id = SDM660_SLAVE_MESSAGE_RAM,
931 .qos.ap_owned = true,
932 .qos.qos_mode = NOC_QOS_MODE_INVALID,
935 static struct qcom_icc_node slv_glm = {
937 .id = SDM660_SLAVE_GLM,
941 .qos.ap_owned = true,
942 .qos.qos_mode = NOC_QOS_MODE_INVALID,
945 static struct qcom_icc_node slv_bimc_cfg = {
946 .name = "slv_bimc_cfg",
947 .id = SDM660_SLAVE_BIMC_CFG,
951 .qos.ap_owned = true,
952 .qos.qos_mode = NOC_QOS_MODE_INVALID,
955 static struct qcom_icc_node slv_prng = {
957 .id = SDM660_SLAVE_PRNG,
961 .qos.ap_owned = true,
962 .qos.qos_mode = NOC_QOS_MODE_INVALID,
965 static struct qcom_icc_node slv_spdm = {
967 .id = SDM660_SLAVE_SPDM,
971 .qos.ap_owned = true,
972 .qos.qos_mode = NOC_QOS_MODE_INVALID,
975 static struct qcom_icc_node slv_qdss_cfg = {
976 .name = "slv_qdss_cfg",
977 .id = SDM660_SLAVE_QDSS_CFG,
981 .qos.ap_owned = true,
982 .qos.qos_mode = NOC_QOS_MODE_INVALID,
985 static const u16 slv_cnoc_mnoc_cfg_links[] = {
986 SDM660_MASTER_CNOC_MNOC_CFG
989 static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
990 .name = "slv_cnoc_mnoc_cfg",
991 .id = SDM660_SLAVE_CNOC_MNOC_CFG,
995 .qos.ap_owned = true,
996 .qos.qos_mode = NOC_QOS_MODE_INVALID,
997 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
998 .links = slv_cnoc_mnoc_cfg_links,
1001 static struct qcom_icc_node slv_snoc_cfg = {
1002 .name = "slv_snoc_cfg",
1003 .id = SDM660_SLAVE_SNOC_CFG,
1007 .qos.ap_owned = true,
1008 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1011 static struct qcom_icc_node slv_qm_cfg = {
1012 .name = "slv_qm_cfg",
1013 .id = SDM660_SLAVE_QM_CFG,
1017 .qos.ap_owned = true,
1018 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1021 static struct qcom_icc_node slv_clk_ctl = {
1022 .name = "slv_clk_ctl",
1023 .id = SDM660_SLAVE_CLK_CTL,
1027 .qos.ap_owned = true,
1028 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1031 static struct qcom_icc_node slv_mss_cfg = {
1032 .name = "slv_mss_cfg",
1033 .id = SDM660_SLAVE_MSS_CFG,
1037 .qos.ap_owned = true,
1038 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1041 static struct qcom_icc_node slv_tlmm_south = {
1042 .name = "slv_tlmm_south",
1043 .id = SDM660_SLAVE_TLMM_SOUTH,
1047 .qos.ap_owned = true,
1048 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1051 static struct qcom_icc_node slv_ufs_cfg = {
1052 .name = "slv_ufs_cfg",
1053 .id = SDM660_SLAVE_UFS_CFG,
1057 .qos.ap_owned = true,
1058 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1061 static struct qcom_icc_node slv_a2noc_cfg = {
1062 .name = "slv_a2noc_cfg",
1063 .id = SDM660_SLAVE_A2NOC_CFG,
1067 .qos.ap_owned = true,
1068 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1071 static struct qcom_icc_node slv_a2noc_smmu_cfg = {
1072 .name = "slv_a2noc_smmu_cfg",
1073 .id = SDM660_SLAVE_A2NOC_SMMU_CFG,
1077 .qos.ap_owned = true,
1078 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1081 static struct qcom_icc_node slv_gpuss_cfg = {
1082 .name = "slv_gpuss_cfg",
1083 .id = SDM660_SLAVE_GPUSS_CFG,
1087 .qos.ap_owned = true,
1088 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1091 static struct qcom_icc_node slv_ahb2phy = {
1092 .name = "slv_ahb2phy",
1093 .id = SDM660_SLAVE_AHB2PHY,
1097 .qos.ap_owned = true,
1098 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1101 static struct qcom_icc_node slv_blsp_1 = {
1102 .name = "slv_blsp_1",
1103 .id = SDM660_SLAVE_BLSP_1,
1107 .qos.ap_owned = true,
1108 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1111 static struct qcom_icc_node slv_sdcc_1 = {
1112 .name = "slv_sdcc_1",
1113 .id = SDM660_SLAVE_SDCC_1,
1117 .qos.ap_owned = true,
1118 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1121 static struct qcom_icc_node slv_sdcc_2 = {
1122 .name = "slv_sdcc_2",
1123 .id = SDM660_SLAVE_SDCC_2,
1127 .qos.ap_owned = true,
1128 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1131 static struct qcom_icc_node slv_tlmm_center = {
1132 .name = "slv_tlmm_center",
1133 .id = SDM660_SLAVE_TLMM_CENTER,
1137 .qos.ap_owned = true,
1138 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1141 static struct qcom_icc_node slv_blsp_2 = {
1142 .name = "slv_blsp_2",
1143 .id = SDM660_SLAVE_BLSP_2,
1147 .qos.ap_owned = true,
1148 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1151 static struct qcom_icc_node slv_pdm = {
1153 .id = SDM660_SLAVE_PDM,
1157 .qos.ap_owned = true,
1158 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1161 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = {
1162 SDM660_MASTER_CNOC_MNOC_MMSS_CFG
1165 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
1166 .name = "slv_cnoc_mnoc_mmss_cfg",
1167 .id = SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
1171 .qos.ap_owned = true,
1172 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1173 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links),
1174 .links = slv_cnoc_mnoc_mmss_cfg_links,
1177 static struct qcom_icc_node slv_usb_hs = {
1178 .name = "slv_usb_hs",
1179 .id = SDM660_SLAVE_USB_HS,
1183 .qos.ap_owned = true,
1184 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1187 static struct qcom_icc_node slv_usb3_0 = {
1188 .name = "slv_usb3_0",
1189 .id = SDM660_SLAVE_USB3_0,
1193 .qos.ap_owned = true,
1194 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1197 static struct qcom_icc_node slv_srvc_cnoc = {
1198 .name = "slv_srvc_cnoc",
1199 .id = SDM660_SLAVE_SRVC_CNOC,
1203 .qos.ap_owned = true,
1204 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1207 static const u16 slv_gnoc_bimc_links[] = {
1208 SDM660_MASTER_GNOC_BIMC
1211 static struct qcom_icc_node slv_gnoc_bimc = {
1212 .name = "slv_gnoc_bimc",
1213 .id = SDM660_SLAVE_GNOC_BIMC,
1217 .qos.ap_owned = true,
1218 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1219 .num_links = ARRAY_SIZE(slv_gnoc_bimc_links),
1220 .links = slv_gnoc_bimc_links,
1223 static const u16 slv_gnoc_snoc_links[] = {
1224 SDM660_MASTER_GNOC_SNOC
1227 static struct qcom_icc_node slv_gnoc_snoc = {
1228 .name = "slv_gnoc_snoc",
1229 .id = SDM660_SLAVE_GNOC_SNOC,
1233 .qos.ap_owned = true,
1234 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1235 .num_links = ARRAY_SIZE(slv_gnoc_snoc_links),
1236 .links = slv_gnoc_snoc_links,
1239 static struct qcom_icc_node slv_camera_cfg = {
1240 .name = "slv_camera_cfg",
1241 .id = SDM660_SLAVE_CAMERA_CFG,
1245 .qos.ap_owned = true,
1246 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1249 static struct qcom_icc_node slv_camera_throttle_cfg = {
1250 .name = "slv_camera_throttle_cfg",
1251 .id = SDM660_SLAVE_CAMERA_THROTTLE_CFG,
1255 .qos.ap_owned = true,
1256 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1259 static struct qcom_icc_node slv_misc_cfg = {
1260 .name = "slv_misc_cfg",
1261 .id = SDM660_SLAVE_MISC_CFG,
1265 .qos.ap_owned = true,
1266 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1269 static struct qcom_icc_node slv_venus_throttle_cfg = {
1270 .name = "slv_venus_throttle_cfg",
1271 .id = SDM660_SLAVE_VENUS_THROTTLE_CFG,
1275 .qos.ap_owned = true,
1276 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1279 static struct qcom_icc_node slv_venus_cfg = {
1280 .name = "slv_venus_cfg",
1281 .id = SDM660_SLAVE_VENUS_CFG,
1285 .qos.ap_owned = true,
1286 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1289 static struct qcom_icc_node slv_mmss_clk_xpu_cfg = {
1290 .name = "slv_mmss_clk_xpu_cfg",
1291 .id = SDM660_SLAVE_MMSS_CLK_XPU_CFG,
1295 .qos.ap_owned = true,
1296 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1299 static struct qcom_icc_node slv_mmss_clk_cfg = {
1300 .name = "slv_mmss_clk_cfg",
1301 .id = SDM660_SLAVE_MMSS_CLK_CFG,
1305 .qos.ap_owned = true,
1306 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1309 static struct qcom_icc_node slv_mnoc_mpu_cfg = {
1310 .name = "slv_mnoc_mpu_cfg",
1311 .id = SDM660_SLAVE_MNOC_MPU_CFG,
1315 .qos.ap_owned = true,
1316 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1319 static struct qcom_icc_node slv_display_cfg = {
1320 .name = "slv_display_cfg",
1321 .id = SDM660_SLAVE_DISPLAY_CFG,
1325 .qos.ap_owned = true,
1326 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1329 static struct qcom_icc_node slv_csi_phy_cfg = {
1330 .name = "slv_csi_phy_cfg",
1331 .id = SDM660_SLAVE_CSI_PHY_CFG,
1335 .qos.ap_owned = true,
1336 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1339 static struct qcom_icc_node slv_display_throttle_cfg = {
1340 .name = "slv_display_throttle_cfg",
1341 .id = SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
1345 .qos.ap_owned = true,
1346 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1349 static struct qcom_icc_node slv_smmu_cfg = {
1350 .name = "slv_smmu_cfg",
1351 .id = SDM660_SLAVE_SMMU_CFG,
1355 .qos.ap_owned = true,
1356 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1359 static const u16 slv_mnoc_bimc_links[] = {
1360 SDM660_MASTER_MNOC_BIMC
1363 static struct qcom_icc_node slv_mnoc_bimc = {
1364 .name = "slv_mnoc_bimc",
1365 .id = SDM660_SLAVE_MNOC_BIMC,
1369 .qos.ap_owned = true,
1370 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1371 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links),
1372 .links = slv_mnoc_bimc_links,
1375 static struct qcom_icc_node slv_srvc_mnoc = {
1376 .name = "slv_srvc_mnoc",
1377 .id = SDM660_SLAVE_SRVC_MNOC,
1381 .qos.ap_owned = true,
1382 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1385 static struct qcom_icc_node slv_hmss = {
1387 .id = SDM660_SLAVE_HMSS,
1391 .qos.ap_owned = true,
1392 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1395 static struct qcom_icc_node slv_lpass = {
1396 .name = "slv_lpass",
1397 .id = SDM660_SLAVE_LPASS,
1401 .qos.ap_owned = true,
1402 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1405 static struct qcom_icc_node slv_wlan = {
1407 .id = SDM660_SLAVE_WLAN,
1413 static struct qcom_icc_node slv_cdsp = {
1415 .id = SDM660_SLAVE_CDSP,
1419 .qos.ap_owned = true,
1420 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1423 static struct qcom_icc_node slv_ipa = {
1425 .id = SDM660_SLAVE_IPA,
1429 .qos.ap_owned = true,
1430 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1433 static const u16 slv_snoc_bimc_links[] = {
1434 SDM660_MASTER_SNOC_BIMC
1437 static struct qcom_icc_node slv_snoc_bimc = {
1438 .name = "slv_snoc_bimc",
1439 .id = SDM660_SLAVE_SNOC_BIMC,
1443 .num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1444 .links = slv_snoc_bimc_links,
1447 static const u16 slv_snoc_cnoc_links[] = {
1448 SDM660_MASTER_SNOC_CNOC
1451 static struct qcom_icc_node slv_snoc_cnoc = {
1452 .name = "slv_snoc_cnoc",
1453 .id = SDM660_SLAVE_SNOC_CNOC,
1457 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1458 .links = slv_snoc_cnoc_links,
1461 static struct qcom_icc_node slv_imem = {
1463 .id = SDM660_SLAVE_IMEM,
1469 static struct qcom_icc_node slv_pimem = {
1470 .name = "slv_pimem",
1471 .id = SDM660_SLAVE_PIMEM,
1477 static struct qcom_icc_node slv_qdss_stm = {
1478 .name = "slv_qdss_stm",
1479 .id = SDM660_SLAVE_QDSS_STM,
1485 static struct qcom_icc_node slv_srvc_snoc = {
1486 .name = "slv_srvc_snoc",
1487 .id = SDM660_SLAVE_SRVC_SNOC,
1493 static struct qcom_icc_node * const sdm660_a2noc_nodes[] = {
1494 [MASTER_IPA] = &mas_ipa,
1495 [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc,
1496 [MASTER_SDCC_1] = &mas_sdcc_1,
1497 [MASTER_SDCC_2] = &mas_sdcc_2,
1498 [MASTER_BLSP_1] = &mas_blsp_1,
1499 [MASTER_BLSP_2] = &mas_blsp_2,
1500 [MASTER_UFS] = &mas_ufs,
1501 [MASTER_USB_HS] = &mas_usb_hs,
1502 [MASTER_USB3] = &mas_usb3,
1503 [MASTER_CRYPTO_C0] = &mas_crypto,
1504 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
1507 static const struct regmap_config sdm660_a2noc_regmap_config = {
1511 .max_register = 0x20000,
1515 static const struct qcom_icc_desc sdm660_a2noc = {
1516 .type = QCOM_ICC_NOC,
1517 .nodes = sdm660_a2noc_nodes,
1518 .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
1519 .clocks = bus_a2noc_clocks,
1520 .num_clocks = ARRAY_SIZE(bus_a2noc_clocks),
1521 .regmap_cfg = &sdm660_a2noc_regmap_config,
1524 static struct qcom_icc_node * const sdm660_bimc_nodes[] = {
1525 [MASTER_GNOC_BIMC] = &mas_gnoc_bimc,
1526 [MASTER_OXILI] = &mas_oxili,
1527 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
1528 [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1529 [MASTER_PIMEM] = &mas_pimem,
1530 [SLAVE_EBI] = &slv_ebi,
1531 [SLAVE_HMSS_L3] = &slv_hmss_l3,
1532 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
1535 static const struct regmap_config sdm660_bimc_regmap_config = {
1539 .max_register = 0x80000,
1543 static const struct qcom_icc_desc sdm660_bimc = {
1544 .type = QCOM_ICC_BIMC,
1545 .nodes = sdm660_bimc_nodes,
1546 .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
1547 .regmap_cfg = &sdm660_bimc_regmap_config,
1550 static struct qcom_icc_node * const sdm660_cnoc_nodes[] = {
1551 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1552 [MASTER_QDSS_DAP] = &mas_qdss_dap,
1553 [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc,
1554 [SLAVE_MPM] = &slv_mpm,
1555 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1556 [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
1557 [SLAVE_TCSR] = &slv_tcsr,
1558 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1559 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1560 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1561 [SLAVE_GLM] = &slv_glm,
1562 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1563 [SLAVE_PRNG] = &slv_prng,
1564 [SLAVE_SPDM] = &slv_spdm,
1565 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1566 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
1567 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1568 [SLAVE_QM_CFG] = &slv_qm_cfg,
1569 [SLAVE_CLK_CTL] = &slv_clk_ctl,
1570 [SLAVE_MSS_CFG] = &slv_mss_cfg,
1571 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
1572 [SLAVE_UFS_CFG] = &slv_ufs_cfg,
1573 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
1574 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
1575 [SLAVE_GPUSS_CFG] = &slv_gpuss_cfg,
1576 [SLAVE_AHB2PHY] = &slv_ahb2phy,
1577 [SLAVE_BLSP_1] = &slv_blsp_1,
1578 [SLAVE_SDCC_1] = &slv_sdcc_1,
1579 [SLAVE_SDCC_2] = &slv_sdcc_2,
1580 [SLAVE_TLMM_CENTER] = &slv_tlmm_center,
1581 [SLAVE_BLSP_2] = &slv_blsp_2,
1582 [SLAVE_PDM] = &slv_pdm,
1583 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
1584 [SLAVE_USB_HS] = &slv_usb_hs,
1585 [SLAVE_USB3_0] = &slv_usb3_0,
1586 [SLAVE_SRVC_CNOC] = &slv_srvc_cnoc,
1589 static const struct regmap_config sdm660_cnoc_regmap_config = {
1593 .max_register = 0x10000,
1597 static const struct qcom_icc_desc sdm660_cnoc = {
1598 .type = QCOM_ICC_NOC,
1599 .nodes = sdm660_cnoc_nodes,
1600 .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
1601 .regmap_cfg = &sdm660_cnoc_regmap_config,
1604 static struct qcom_icc_node * const sdm660_gnoc_nodes[] = {
1605 [MASTER_APSS_PROC] = &mas_apss_proc,
1606 [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc,
1607 [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc,
1610 static const struct regmap_config sdm660_gnoc_regmap_config = {
1614 .max_register = 0xe000,
1618 static const struct qcom_icc_desc sdm660_gnoc = {
1619 .type = QCOM_ICC_NOC,
1620 .nodes = sdm660_gnoc_nodes,
1621 .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
1622 .regmap_cfg = &sdm660_gnoc_regmap_config,
1625 static struct qcom_icc_node * const sdm660_mnoc_nodes[] = {
1626 [MASTER_CPP] = &mas_cpp,
1627 [MASTER_JPEG] = &mas_jpeg,
1628 [MASTER_MDP_P0] = &mas_mdp_p0,
1629 [MASTER_MDP_P1] = &mas_mdp_p1,
1630 [MASTER_VENUS] = &mas_venus,
1631 [MASTER_VFE] = &mas_vfe,
1632 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
1633 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
1634 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1635 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
1636 [SLAVE_MISC_CFG] = &slv_misc_cfg,
1637 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1638 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1639 [SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
1640 [SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
1641 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
1642 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1643 [SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg,
1644 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1645 [SLAVE_SMMU_CFG] = &slv_smmu_cfg,
1646 [SLAVE_SRVC_MNOC] = &slv_srvc_mnoc,
1647 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
1650 static const struct regmap_config sdm660_mnoc_regmap_config = {
1654 .max_register = 0x10000,
1658 static const struct qcom_icc_desc sdm660_mnoc = {
1659 .type = QCOM_ICC_NOC,
1660 .nodes = sdm660_mnoc_nodes,
1661 .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
1662 .clocks = bus_mm_clocks,
1663 .num_clocks = ARRAY_SIZE(bus_mm_clocks),
1664 .regmap_cfg = &sdm660_mnoc_regmap_config,
1667 static struct qcom_icc_node * const sdm660_snoc_nodes[] = {
1668 [MASTER_QDSS_ETR] = &mas_qdss_etr,
1669 [MASTER_QDSS_BAM] = &mas_qdss_bam,
1670 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
1671 [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1672 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
1673 [MASTER_GNOC_SNOC] = &mas_gnoc_snoc,
1674 [SLAVE_HMSS] = &slv_hmss,
1675 [SLAVE_LPASS] = &slv_lpass,
1676 [SLAVE_WLAN] = &slv_wlan,
1677 [SLAVE_CDSP] = &slv_cdsp,
1678 [SLAVE_IPA] = &slv_ipa,
1679 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
1680 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
1681 [SLAVE_IMEM] = &slv_imem,
1682 [SLAVE_PIMEM] = &slv_pimem,
1683 [SLAVE_QDSS_STM] = &slv_qdss_stm,
1684 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
1687 static const struct regmap_config sdm660_snoc_regmap_config = {
1691 .max_register = 0x20000,
1695 static const struct qcom_icc_desc sdm660_snoc = {
1696 .type = QCOM_ICC_NOC,
1697 .nodes = sdm660_snoc_nodes,
1698 .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
1699 .regmap_cfg = &sdm660_snoc_regmap_config,
1702 static const struct of_device_id sdm660_noc_of_match[] = {
1703 { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc },
1704 { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc },
1705 { .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc },
1706 { .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc },
1707 { .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc },
1708 { .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc },
1711 MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);
1713 static struct platform_driver sdm660_noc_driver = {
1714 .probe = qnoc_probe,
1715 .remove = qnoc_remove,
1717 .name = "qnoc-sdm660",
1718 .of_match_table = sdm660_noc_of_match,
1721 module_platform_driver(sdm660_noc_driver);
1722 MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver");
1723 MODULE_LICENSE("GPL v2");