2 * Copyright (c) 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2013 Cisco Systems. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/dma-mapping.h>
37 #include <linux/sched.h>
38 #include <linux/hugetlb.h>
39 #include <linux/iommu.h>
40 #include <linux/workqueue.h>
41 #include <linux/list.h>
42 #include <linux/pci.h>
44 #include "usnic_log.h"
45 #include "usnic_uiom.h"
46 #include "usnic_uiom_interval_tree.h"
48 static struct workqueue_struct *usnic_uiom_wq;
50 #define USNIC_UIOM_PAGE_CHUNK \
51 ((PAGE_SIZE - offsetof(struct usnic_uiom_chunk, page_list)) /\
52 ((void *) &((struct usnic_uiom_chunk *) 0)->page_list[1] - \
53 (void *) &((struct usnic_uiom_chunk *) 0)->page_list[0]))
55 static void usnic_uiom_reg_account(struct work_struct *work)
57 struct usnic_uiom_reg *umem = container_of(work,
58 struct usnic_uiom_reg, work);
60 down_write(&umem->mm->mmap_sem);
61 umem->mm->locked_vm -= umem->diff;
62 up_write(&umem->mm->mmap_sem);
67 static int usnic_uiom_dma_fault(struct iommu_domain *domain,
69 unsigned long iova, int flags,
72 usnic_err("Device %s iommu fault domain 0x%pK va 0x%lx flags 0x%x\n",
78 static void usnic_uiom_put_pages(struct list_head *chunk_list, int dirty)
80 struct usnic_uiom_chunk *chunk, *tmp;
82 struct scatterlist *sg;
86 list_for_each_entry_safe(chunk, tmp, chunk_list, list) {
87 for_each_sg(chunk->page_list, sg, chunk->nents, i) {
91 set_page_dirty_lock(page);
93 usnic_dbg("pa: %pa\n", &pa);
99 static int usnic_uiom_get_pages(unsigned long addr, size_t size, int writable,
100 int dmasync, struct list_head *chunk_list)
102 struct page **page_list;
103 struct scatterlist *sg;
104 struct usnic_uiom_chunk *chunk;
105 unsigned long locked;
106 unsigned long lock_limit;
107 unsigned long cur_base;
108 unsigned long npages;
118 INIT_LIST_HEAD(chunk_list);
120 page_list = (struct page **) __get_free_page(GFP_KERNEL);
124 npages = PAGE_ALIGN(size + (addr & ~PAGE_MASK)) >> PAGE_SHIFT;
126 down_write(¤t->mm->mmap_sem);
128 locked = npages + current->mm->locked_vm;
129 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
131 if ((locked > lock_limit) && !capable(CAP_IPC_LOCK)) {
136 flags = IOMMU_READ | IOMMU_CACHE;
137 flags |= (writable) ? IOMMU_WRITE : 0;
138 cur_base = addr & PAGE_MASK;
142 ret = get_user_pages(cur_base,
143 min_t(unsigned long, npages,
144 PAGE_SIZE / sizeof(struct page *)),
145 1, !writable, page_list, NULL);
154 chunk = kmalloc(sizeof(*chunk) +
155 sizeof(struct scatterlist) *
156 min_t(int, ret, USNIC_UIOM_PAGE_CHUNK),
163 chunk->nents = min_t(int, ret, USNIC_UIOM_PAGE_CHUNK);
164 sg_init_table(chunk->page_list, chunk->nents);
165 for_each_sg(chunk->page_list, sg, chunk->nents, i) {
166 sg_set_page(sg, page_list[i + off],
169 usnic_dbg("va: 0x%lx pa: %pa\n",
170 cur_base + i*PAGE_SIZE, &pa);
172 cur_base += chunk->nents * PAGE_SIZE;
175 list_add_tail(&chunk->list, chunk_list);
183 usnic_uiom_put_pages(chunk_list, 0);
185 current->mm->locked_vm = locked;
187 up_write(¤t->mm->mmap_sem);
188 free_page((unsigned long) page_list);
192 static void usnic_uiom_unmap_sorted_intervals(struct list_head *intervals,
193 struct usnic_uiom_pd *pd)
195 struct usnic_uiom_interval_node *interval, *tmp;
196 long unsigned va, size;
198 list_for_each_entry_safe(interval, tmp, intervals, link) {
199 va = interval->start << PAGE_SHIFT;
200 size = ((interval->last - interval->start) + 1) << PAGE_SHIFT;
202 /* Workaround for RH 970401 */
203 usnic_dbg("va 0x%lx size 0x%lx", va, PAGE_SIZE);
204 iommu_unmap(pd->domain, va, PAGE_SIZE);
211 static void __usnic_uiom_reg_release(struct usnic_uiom_pd *pd,
212 struct usnic_uiom_reg *uiomr,
216 unsigned long vpn_start, vpn_last;
217 struct usnic_uiom_interval_node *interval, *tmp;
219 LIST_HEAD(rm_intervals);
221 npages = PAGE_ALIGN(uiomr->length + uiomr->offset) >> PAGE_SHIFT;
222 vpn_start = (uiomr->va & PAGE_MASK) >> PAGE_SHIFT;
223 vpn_last = vpn_start + npages - 1;
225 spin_lock(&pd->lock);
226 usnic_uiom_remove_interval(&pd->rb_root, vpn_start,
227 vpn_last, &rm_intervals);
228 usnic_uiom_unmap_sorted_intervals(&rm_intervals, pd);
230 list_for_each_entry_safe(interval, tmp, &rm_intervals, link) {
231 if (interval->flags & IOMMU_WRITE)
233 list_del(&interval->link);
237 usnic_uiom_put_pages(&uiomr->chunk_list, dirty & writable);
238 spin_unlock(&pd->lock);
241 static int usnic_uiom_map_sorted_intervals(struct list_head *intervals,
242 struct usnic_uiom_reg *uiomr)
246 struct usnic_uiom_chunk *chunk;
247 struct usnic_uiom_interval_node *interval_node;
249 dma_addr_t pa_start = 0;
250 dma_addr_t pa_end = 0;
251 long int va_start = -EINVAL;
252 struct usnic_uiom_pd *pd = uiomr->pd;
253 long int va = uiomr->va & PAGE_MASK;
254 int flags = IOMMU_READ | IOMMU_CACHE;
256 flags |= (uiomr->writable) ? IOMMU_WRITE : 0;
257 chunk = list_first_entry(&uiomr->chunk_list, struct usnic_uiom_chunk,
259 list_for_each_entry(interval_node, intervals, link) {
261 for (i = 0; i < chunk->nents; i++, va += PAGE_SIZE) {
262 pa = sg_phys(&chunk->page_list[i]);
263 if ((va >> PAGE_SHIFT) < interval_node->start)
266 if ((va >> PAGE_SHIFT) == interval_node->start) {
267 /* First page of the interval */
273 WARN_ON(va_start == -EINVAL);
275 if ((pa_end + PAGE_SIZE != pa) &&
277 /* PAs are not contiguous */
278 size = pa_end - pa_start + PAGE_SIZE;
279 usnic_dbg("va 0x%lx pa %pa size 0x%zx flags 0x%x",
280 va_start, &pa_start, size, flags);
281 err = iommu_map(pd->domain, va_start, pa_start,
284 usnic_err("Failed to map va 0x%lx pa %pa size 0x%zx with err %d\n",
285 va_start, &pa_start, size, err);
293 if ((va >> PAGE_SHIFT) == interval_node->last) {
294 /* Last page of the interval */
295 size = pa - pa_start + PAGE_SIZE;
296 usnic_dbg("va 0x%lx pa %pa size 0x%zx flags 0x%x\n",
297 va_start, &pa_start, size, flags);
298 err = iommu_map(pd->domain, va_start, pa_start,
301 usnic_err("Failed to map va 0x%lx pa %pa size 0x%zx with err %d\n",
302 va_start, &pa_start, size, err);
312 if (i == chunk->nents) {
314 * Hit last entry of the chunk,
315 * hence advance to next chunk
317 chunk = list_first_entry(&chunk->list,
318 struct usnic_uiom_chunk,
327 usnic_uiom_unmap_sorted_intervals(intervals, pd);
331 struct usnic_uiom_reg *usnic_uiom_reg_get(struct usnic_uiom_pd *pd,
332 unsigned long addr, size_t size,
333 int writable, int dmasync)
335 struct usnic_uiom_reg *uiomr;
336 unsigned long va_base, vpn_start, vpn_last;
337 unsigned long npages;
339 LIST_HEAD(sorted_diff_intervals);
342 * Intel IOMMU map throws an error if a translation entry is
343 * changed from read to write. This module may not unmap
344 * and then remap the entry after fixing the permission
345 * b/c this open up a small windows where hw DMA may page fault
346 * Hence, make all entries to be writable.
350 va_base = addr & PAGE_MASK;
351 offset = addr & ~PAGE_MASK;
352 npages = PAGE_ALIGN(size + offset) >> PAGE_SHIFT;
353 vpn_start = (addr & PAGE_MASK) >> PAGE_SHIFT;
354 vpn_last = vpn_start + npages - 1;
356 uiomr = kmalloc(sizeof(*uiomr), GFP_KERNEL);
358 return ERR_PTR(-ENOMEM);
361 uiomr->offset = offset;
362 uiomr->length = size;
363 uiomr->writable = writable;
366 err = usnic_uiom_get_pages(addr, size, writable, dmasync,
369 usnic_err("Failed get_pages vpn [0x%lx,0x%lx] err %d\n",
370 vpn_start, vpn_last, err);
374 spin_lock(&pd->lock);
375 err = usnic_uiom_get_intervals_diff(vpn_start, vpn_last,
376 (writable) ? IOMMU_WRITE : 0,
379 &sorted_diff_intervals);
381 usnic_err("Failed disjoint interval vpn [0x%lx,0x%lx] err %d\n",
382 vpn_start, vpn_last, err);
386 err = usnic_uiom_map_sorted_intervals(&sorted_diff_intervals, uiomr);
388 usnic_err("Failed map interval vpn [0x%lx,0x%lx] err %d\n",
389 vpn_start, vpn_last, err);
390 goto out_put_intervals;
394 err = usnic_uiom_insert_interval(&pd->rb_root, vpn_start, vpn_last,
395 (writable) ? IOMMU_WRITE : 0);
397 usnic_err("Failed insert interval vpn [0x%lx,0x%lx] err %d\n",
398 vpn_start, vpn_last, err);
399 goto out_unmap_intervals;
402 usnic_uiom_put_interval_set(&sorted_diff_intervals);
403 spin_unlock(&pd->lock);
408 usnic_uiom_unmap_sorted_intervals(&sorted_diff_intervals, pd);
410 usnic_uiom_put_interval_set(&sorted_diff_intervals);
412 usnic_uiom_put_pages(&uiomr->chunk_list, 0);
413 spin_unlock(&pd->lock);
419 void usnic_uiom_reg_release(struct usnic_uiom_reg *uiomr, int closing)
421 struct mm_struct *mm;
424 __usnic_uiom_reg_release(uiomr->pd, uiomr, 1);
426 mm = get_task_mm(current);
432 diff = PAGE_ALIGN(uiomr->length + uiomr->offset) >> PAGE_SHIFT;
435 * We may be called with the mm's mmap_sem already held. This
436 * can happen when a userspace munmap() is the call that drops
437 * the last reference to our file and calls our release
438 * method. If there are memory regions to destroy, we'll end
439 * up here and not be able to take the mmap_sem. In that case
440 * we defer the vm_locked accounting to the system workqueue.
443 if (!down_write_trylock(&mm->mmap_sem)) {
444 INIT_WORK(&uiomr->work, usnic_uiom_reg_account);
448 queue_work(usnic_uiom_wq, &uiomr->work);
452 down_write(&mm->mmap_sem);
454 current->mm->locked_vm -= diff;
455 up_write(&mm->mmap_sem);
460 struct usnic_uiom_pd *usnic_uiom_alloc_pd(void)
462 struct usnic_uiom_pd *pd;
465 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
467 return ERR_PTR(-ENOMEM);
469 pd->domain = domain = iommu_domain_alloc(&pci_bus_type);
471 usnic_err("Failed to allocate IOMMU domain");
473 return ERR_PTR(-ENOMEM);
476 iommu_set_fault_handler(pd->domain, usnic_uiom_dma_fault, NULL);
478 spin_lock_init(&pd->lock);
479 INIT_LIST_HEAD(&pd->devs);
484 void usnic_uiom_dealloc_pd(struct usnic_uiom_pd *pd)
486 iommu_domain_free(pd->domain);
490 int usnic_uiom_attach_dev_to_pd(struct usnic_uiom_pd *pd, struct device *dev)
492 struct usnic_uiom_dev *uiom_dev;
495 uiom_dev = kzalloc(sizeof(*uiom_dev), GFP_ATOMIC);
500 err = iommu_attach_device(pd->domain, dev);
504 if (!iommu_capable(dev->bus, IOMMU_CAP_CACHE_COHERENCY)) {
505 usnic_err("IOMMU of %s does not support cache coherency\n",
508 goto out_detach_device;
511 spin_lock(&pd->lock);
512 list_add_tail(&uiom_dev->link, &pd->devs);
514 spin_unlock(&pd->lock);
519 iommu_detach_device(pd->domain, dev);
525 void usnic_uiom_detach_dev_from_pd(struct usnic_uiom_pd *pd, struct device *dev)
527 struct usnic_uiom_dev *uiom_dev;
530 spin_lock(&pd->lock);
531 list_for_each_entry(uiom_dev, &pd->devs, link) {
532 if (uiom_dev->dev == dev) {
539 usnic_err("Unable to free dev %s - not found\n",
541 spin_unlock(&pd->lock);
545 list_del(&uiom_dev->link);
547 spin_unlock(&pd->lock);
549 return iommu_detach_device(pd->domain, dev);
552 struct device **usnic_uiom_get_dev_list(struct usnic_uiom_pd *pd)
554 struct usnic_uiom_dev *uiom_dev;
555 struct device **devs;
558 spin_lock(&pd->lock);
559 devs = kcalloc(pd->dev_cnt + 1, sizeof(*devs), GFP_ATOMIC);
561 devs = ERR_PTR(-ENOMEM);
565 list_for_each_entry(uiom_dev, &pd->devs, link) {
566 devs[i++] = uiom_dev->dev;
569 spin_unlock(&pd->lock);
573 void usnic_uiom_free_dev_list(struct device **devs)
578 int usnic_uiom_init(char *drv_name)
580 if (!iommu_present(&pci_bus_type)) {
581 usnic_err("IOMMU required but not present or enabled. USNIC QPs will not function w/o enabling IOMMU\n");
585 usnic_uiom_wq = create_workqueue(drv_name);
586 if (!usnic_uiom_wq) {
587 usnic_err("Unable to alloc wq for drv %s\n", drv_name);
594 void usnic_uiom_fini(void)
596 flush_workqueue(usnic_uiom_wq);
597 destroy_workqueue(usnic_uiom_wq);