drivers/infiniband/hw/qedr/main.c

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/module.h>
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_addr.h>
  35 #include <rdma/ib_user_verbs.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/iommu.h>
  38 #include <net/addrconf.h>
  39 #include <linux/qed/qede_roce.h>
  40 #include <linux/qed/qed_chain.h>
  41 #include <linux/qed/qed_if.h>
  42 #include "qedr.h"
  43 #include "verbs.h"
  44 #include <rdma/qedr-abi.h>
  45
  46 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
  47 MODULE_AUTHOR("QLogic Corporation");
  48 MODULE_LICENSE("Dual BSD/GPL");
  49 MODULE_VERSION(QEDR_MODULE_VERSION);
  50
  51 void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
  52                             enum ib_event_type type)
  53 {
  54         struct ib_event ibev;
  55
  56         ibev.device = &dev->ibdev;
  57         ibev.element.port_num = port_num;
  58         ibev.event = type;
  59
  60         ib_dispatch_event(&ibev);
  61 }
  62
  63 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
  64                                             u8 port_num)
  65 {
  66         return IB_LINK_LAYER_ETHERNET;
  67 }
  68
  69 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str,
  70                                 size_t str_len)
  71 {
  72         struct qedr_dev *qedr = get_qedr_dev(ibdev);
  73         u32 fw_ver = (u32)qedr->attr.fw_ver;
  74
  75         snprintf(str, str_len, "%d. %d. %d. %d",
  76                  (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
  77                  (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
  78 }
  79
  80 static int qedr_register_device(struct qedr_dev *dev)
  81 {
  82         strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
  83
  84         memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
  85         dev->ibdev.owner = THIS_MODULE;
  86         dev->ibdev.uverbs_abi_ver = QEDR_ABI_VERSION;
  87
  88         dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
  89                                      QEDR_UVERBS(QUERY_DEVICE) |
  90                                      QEDR_UVERBS(QUERY_PORT);
  91
  92         dev->ibdev.phys_port_cnt = 1;
  93         dev->ibdev.num_comp_vectors = dev->num_cnq;
  94         dev->ibdev.node_type = RDMA_NODE_IB_CA;
  95
  96         dev->ibdev.query_device = qedr_query_device;
  97         dev->ibdev.query_port = qedr_query_port;
  98         dev->ibdev.modify_port = qedr_modify_port;
  99
 100         dev->ibdev.query_gid = qedr_query_gid;
 101         dev->ibdev.add_gid = qedr_add_gid;
 102         dev->ibdev.del_gid = qedr_del_gid;
 103
 104         dev->ibdev.alloc_ucontext = qedr_alloc_ucontext;
 105         dev->ibdev.dealloc_ucontext = qedr_dealloc_ucontext;
 106         dev->ibdev.mmap = qedr_mmap;
 107
 108         dev->ibdev.dma_device = &dev->pdev->dev;
 109
 110         dev->ibdev.get_link_layer = qedr_link_layer;
 111         dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str;
 112
 113         return 0;
 114 }
 115
 116 /* This function allocates fast-path status block memory */
 117 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
 118                              struct qed_sb_info *sb_info, u16 sb_id)
 119 {
 120         struct status_block *sb_virt;
 121         dma_addr_t sb_phys;
 122         int rc;
 123
 124         sb_virt = dma_alloc_coherent(&dev->pdev->dev,
 125                                      sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
 126         if (!sb_virt)
 127                 return -ENOMEM;
 128
 129         rc = dev->ops->common->sb_init(dev->cdev, sb_info,
 130                                        sb_virt, sb_phys, sb_id,
 131                                        QED_SB_TYPE_CNQ);
 132         if (rc) {
 133                 pr_err("Status block initialization failed\n");
 134                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
 135                                   sb_virt, sb_phys);
 136                 return rc;
 137         }
 138
 139         return 0;
 140 }
 141
 142 static void qedr_free_mem_sb(struct qedr_dev *dev,
 143                              struct qed_sb_info *sb_info, int sb_id)
 144 {
 145         if (sb_info->sb_virt) {
 146                 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
 147                 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
 148                                   (void *)sb_info->sb_virt, sb_info->sb_phys);
 149         }
 150 }
 151
 152 static void qedr_free_resources(struct qedr_dev *dev)
 153 {
 154         int i;
 155
 156         for (i = 0; i < dev->num_cnq; i++) {
 157                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 158                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 159         }
 160
 161         kfree(dev->cnq_array);
 162         kfree(dev->sb_array);
 163         kfree(dev->sgid_tbl);
 164 }
 165
 166 static int qedr_alloc_resources(struct qedr_dev *dev)
 167 {
 168         struct qedr_cnq *cnq;
 169         __le16 *cons_pi;
 170         u16 n_entries;
 171         int i, rc;
 172
 173         dev->sgid_tbl = kzalloc(sizeof(union ib_gid) *
 174                                 QEDR_MAX_SGID, GFP_KERNEL);
 175         if (!dev->sgid_tbl)
 176                 return -ENOMEM;
 177
 178         spin_lock_init(&dev->sgid_lock);
 179
 180         /* Allocate Status blocks for CNQ */
 181         dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
 182                                 GFP_KERNEL);
 183         if (!dev->sb_array) {
 184                 rc = -ENOMEM;
 185                 goto err1;
 186         }
 187
 188         dev->cnq_array = kcalloc(dev->num_cnq,
 189                                  sizeof(*dev->cnq_array), GFP_KERNEL);
 190         if (!dev->cnq_array) {
 191                 rc = -ENOMEM;
 192                 goto err2;
 193         }
 194
 195         dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
 196
 197         /* Allocate CNQ PBLs */
 198         n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
 199         for (i = 0; i < dev->num_cnq; i++) {
 200                 cnq = &dev->cnq_array[i];
 201
 202                 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
 203                                        dev->sb_start + i);
 204                 if (rc)
 205                         goto err3;
 206
 207                 rc = dev->ops->common->chain_alloc(dev->cdev,
 208                                                    QED_CHAIN_USE_TO_CONSUME,
 209                                                    QED_CHAIN_MODE_PBL,
 210                                                    QED_CHAIN_CNT_TYPE_U16,
 211                                                    n_entries,
 212                                                    sizeof(struct regpair *),
 213                                                    &cnq->pbl);
 214                 if (rc)
 215                         goto err4;
 216
 217                 cnq->dev = dev;
 218                 cnq->sb = &dev->sb_array[i];
 219                 cons_pi = dev->sb_array[i].sb_virt->pi_array;
 220                 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
 221                 cnq->index = i;
 222                 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
 223
 224                 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
 225                          i, qed_chain_get_cons_idx(&cnq->pbl));
 226         }
 227
 228         return 0;
 229 err4:
 230         qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 231 err3:
 232         for (--i; i >= 0; i--) {
 233                 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
 234                 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
 235         }
 236         kfree(dev->cnq_array);
 237 err2:
 238         kfree(dev->sb_array);
 239 err1:
 240         kfree(dev->sgid_tbl);
 241         return rc;
 242 }
 243
 244 /* QEDR sysfs interface */
 245 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
 246                         char *buf)
 247 {
 248         struct qedr_dev *dev = dev_get_drvdata(device);
 249
 250         return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->pdev->vendor);
 251 }
 252
 253 static ssize_t show_hca_type(struct device *device,
 254                              struct device_attribute *attr, char *buf)
 255 {
 256         return scnprintf(buf, PAGE_SIZE, "%s\n", "HCA_TYPE_TO_SET");
 257 }
 258
 259 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
 260 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL);
 261
 262 static struct device_attribute *qedr_attributes[] = {
 263         &dev_attr_hw_rev,
 264         &dev_attr_hca_type
 265 };
 266
 267 static void qedr_remove_sysfiles(struct qedr_dev *dev)
 268 {
 269         int i;
 270
 271         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 272                 device_remove_file(&dev->ibdev.dev, qedr_attributes[i]);
 273 }
 274
 275 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
 276 {
 277         struct pci_dev *bridge;
 278         u32 val;
 279
 280         dev->atomic_cap = IB_ATOMIC_NONE;
 281
 282         bridge = pdev->bus->self;
 283         if (!bridge)
 284                 return;
 285
 286         /* Check whether we are connected directly or via a switch */
 287         while (bridge && bridge->bus->parent) {
 288                 DP_DEBUG(dev, QEDR_MSG_INIT,
 289                          "Device is not connected directly to root. bridge->bus->number=%d primary=%d\n",
 290                          bridge->bus->number, bridge->bus->primary);
 291                 /* Need to check Atomic Op Routing Supported all the way to
 292                  * root complex.
 293                  */
 294                 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
 295                 if (!(val & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) {
 296                         pcie_capability_clear_word(pdev,
 297                                                    PCI_EXP_DEVCTL2,
 298                                                    PCI_EXP_DEVCTL2_ATOMIC_REQ);
 299                         return;
 300                 }
 301                 bridge = bridge->bus->parent->self;
 302         }
 303         bridge = pdev->bus->self;
 304
 305         /* according to bridge capability */
 306         pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &val);
 307         if (val & PCI_EXP_DEVCAP2_ATOMIC_COMP64) {
 308                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
 309                                          PCI_EXP_DEVCTL2_ATOMIC_REQ);
 310                 dev->atomic_cap = IB_ATOMIC_GLOB;
 311         } else {
 312                 pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2,
 313                                            PCI_EXP_DEVCTL2_ATOMIC_REQ);
 314         }
 315 }
 316
 317 static const struct qed_rdma_ops *qed_ops;
 318
 319 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 320
 321 static irqreturn_t qedr_irq_handler(int irq, void *handle)
 322 {
 323         u16 hw_comp_cons, sw_comp_cons;
 324         struct qedr_cnq *cnq = handle;
 325
 326         qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
 327
 328         qed_sb_update_sb_idx(cnq->sb);
 329
 330         hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
 331         sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 332
 333         /* Align protocol-index and chain reads */
 334         rmb();
 335
 336         while (sw_comp_cons != hw_comp_cons) {
 337                 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
 338                 cnq->n_comp++;
 339         }
 340
 341         qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
 342                                       sw_comp_cons);
 343
 344         qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
 345
 346         return IRQ_HANDLED;
 347 }
 348
 349 static void qedr_sync_free_irqs(struct qedr_dev *dev)
 350 {
 351         u32 vector;
 352         int i;
 353
 354         for (i = 0; i < dev->int_info.used_cnt; i++) {
 355                 if (dev->int_info.msix_cnt) {
 356                         vector = dev->int_info.msix[i * dev->num_hwfns].vector;
 357                         synchronize_irq(vector);
 358                         free_irq(vector, &dev->cnq_array[i]);
 359                 }
 360         }
 361
 362         dev->int_info.used_cnt = 0;
 363 }
 364
 365 static int qedr_req_msix_irqs(struct qedr_dev *dev)
 366 {
 367         int i, rc = 0;
 368
 369         if (dev->num_cnq > dev->int_info.msix_cnt) {
 370                 DP_ERR(dev,
 371                        "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
 372                        dev->num_cnq, dev->int_info.msix_cnt);
 373                 return -EINVAL;
 374         }
 375
 376         for (i = 0; i < dev->num_cnq; i++) {
 377                 rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
 378                                  qedr_irq_handler, 0, dev->cnq_array[i].name,
 379                                  &dev->cnq_array[i]);
 380                 if (rc) {
 381                         DP_ERR(dev, "Request cnq %d irq failed\n", i);
 382                         qedr_sync_free_irqs(dev);
 383                 } else {
 384                         DP_DEBUG(dev, QEDR_MSG_INIT,
 385                                  "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
 386                                  dev->cnq_array[i].name, i,
 387                                  &dev->cnq_array[i]);
 388                         dev->int_info.used_cnt++;
 389                 }
 390         }
 391
 392         return rc;
 393 }
 394
 395 static int qedr_setup_irqs(struct qedr_dev *dev)
 396 {
 397         int rc;
 398
 399         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
 400
 401         /* Learn Interrupt configuration */
 402         rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
 403         if (rc < 0)
 404                 return rc;
 405
 406         rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
 407         if (rc) {
 408                 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
 409                 return rc;
 410         }
 411
 412         if (dev->int_info.msix_cnt) {
 413                 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
 414                          dev->int_info.msix_cnt);
 415                 rc = qedr_req_msix_irqs(dev);
 416                 if (rc)
 417                         return rc;
 418         }
 419
 420         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
 421
 422         return 0;
 423 }
 424
 425 static int qedr_set_device_attr(struct qedr_dev *dev)
 426 {
 427         struct qed_rdma_device *qed_attr;
 428         struct qedr_device_attr *attr;
 429         u32 page_size;
 430
 431         /* Part 1 - query core capabilities */
 432         qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
 433
 434         /* Part 2 - check capabilities */
 435         page_size = ~dev->attr.page_size_caps + 1;
 436         if (page_size > PAGE_SIZE) {
 437                 DP_ERR(dev,
 438                        "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
 439                        PAGE_SIZE, page_size);
 440                 return -ENODEV;
 441         }
 442
 443         /* Part 3 - copy and update capabilities */
 444         attr = &dev->attr;
 445         attr->vendor_id = qed_attr->vendor_id;
 446         attr->vendor_part_id = qed_attr->vendor_part_id;
 447         attr->hw_ver = qed_attr->hw_ver;
 448         attr->fw_ver = qed_attr->fw_ver;
 449         attr->node_guid = qed_attr->node_guid;
 450         attr->sys_image_guid = qed_attr->sys_image_guid;
 451         attr->max_cnq = qed_attr->max_cnq;
 452         attr->max_sge = qed_attr->max_sge;
 453         attr->max_inline = qed_attr->max_inline;
 454         attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
 455         attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
 456         attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
 457         attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
 458         attr->max_dev_resp_rd_atomic_resc =
 459             qed_attr->max_dev_resp_rd_atomic_resc;
 460         attr->max_cq = qed_attr->max_cq;
 461         attr->max_qp = qed_attr->max_qp;
 462         attr->max_mr = qed_attr->max_mr;
 463         attr->max_mr_size = qed_attr->max_mr_size;
 464         attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
 465         attr->max_mw = qed_attr->max_mw;
 466         attr->max_fmr = qed_attr->max_fmr;
 467         attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
 468         attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
 469         attr->max_pd = qed_attr->max_pd;
 470         attr->max_ah = qed_attr->max_ah;
 471         attr->max_pkey = qed_attr->max_pkey;
 472         attr->max_srq = qed_attr->max_srq;
 473         attr->max_srq_wr = qed_attr->max_srq_wr;
 474         attr->dev_caps = qed_attr->dev_caps;
 475         attr->page_size_caps = qed_attr->page_size_caps;
 476         attr->dev_ack_delay = qed_attr->dev_ack_delay;
 477         attr->reserved_lkey = qed_attr->reserved_lkey;
 478         attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
 479         attr->max_stats_queues = qed_attr->max_stats_queues;
 480
 481         return 0;
 482 }
 483
 484 static int qedr_init_hw(struct qedr_dev *dev)
 485 {
 486         struct qed_rdma_add_user_out_params out_params;
 487         struct qed_rdma_start_in_params *in_params;
 488         struct qed_rdma_cnq_params *cur_pbl;
 489         struct qed_rdma_events events;
 490         dma_addr_t p_phys_table;
 491         u32 page_cnt;
 492         int rc = 0;
 493         int i;
 494
 495         in_params =  kzalloc(sizeof(*in_params), GFP_KERNEL);
 496         if (!in_params) {
 497                 rc = -ENOMEM;
 498                 goto out;
 499         }
 500
 501         in_params->desired_cnq = dev->num_cnq;
 502         for (i = 0; i < dev->num_cnq; i++) {
 503                 cur_pbl = &in_params->cnq_pbl_list[i];
 504
 505                 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
 506                 cur_pbl->num_pbl_pages = page_cnt;
 507
 508                 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
 509                 cur_pbl->pbl_ptr = (u64)p_phys_table;
 510         }
 511
 512         events.context = dev;
 513
 514         in_params->events = &events;
 515         in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
 516         in_params->max_mtu = dev->ndev->mtu;
 517         ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
 518
 519         rc = dev->ops->rdma_init(dev->cdev, in_params);
 520         if (rc)
 521                 goto out;
 522
 523         rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
 524         if (rc)
 525                 goto out;
 526
 527         dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr;
 528         dev->db_phys_addr = out_params.dpi_phys_addr;
 529         dev->db_size = out_params.dpi_size;
 530         dev->dpi = out_params.dpi;
 531
 532         rc = qedr_set_device_attr(dev);
 533 out:
 534         kfree(in_params);
 535         if (rc)
 536                 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
 537
 538         return rc;
 539 }
 540
 541 void qedr_stop_hw(struct qedr_dev *dev)
 542 {
 543         dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
 544         dev->ops->rdma_stop(dev->rdma_ctx);
 545 }
 546
 547 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
 548                                  struct net_device *ndev)
 549 {
 550         struct qed_dev_rdma_info dev_info;
 551         struct qedr_dev *dev;
 552         int rc = 0, i;
 553
 554         dev = (struct qedr_dev *)ib_alloc_device(sizeof(*dev));
 555         if (!dev) {
 556                 pr_err("Unable to allocate ib device\n");
 557                 return NULL;
 558         }
 559
 560         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
 561
 562         dev->pdev = pdev;
 563         dev->ndev = ndev;
 564         dev->cdev = cdev;
 565
 566         qed_ops = qed_get_rdma_ops();
 567         if (!qed_ops) {
 568                 DP_ERR(dev, "Failed to get qed roce operations\n");
 569                 goto init_err;
 570         }
 571
 572         dev->ops = qed_ops;
 573         rc = qed_ops->fill_dev_info(cdev, &dev_info);
 574         if (rc)
 575                 goto init_err;
 576
 577         dev->num_hwfns = dev_info.common.num_hwfns;
 578         dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
 579
 580         dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
 581         if (!dev->num_cnq) {
 582                 DP_ERR(dev, "not enough CNQ resources.\n");
 583                 goto init_err;
 584         }
 585
 586         qedr_pci_set_atomic(dev, pdev);
 587
 588         rc = qedr_alloc_resources(dev);
 589         if (rc)
 590                 goto init_err;
 591
 592         rc = qedr_init_hw(dev);
 593         if (rc)
 594                 goto alloc_err;
 595
 596         rc = qedr_setup_irqs(dev);
 597         if (rc)
 598                 goto irq_err;
 599
 600         rc = qedr_register_device(dev);
 601         if (rc) {
 602                 DP_ERR(dev, "Unable to allocate register device\n");
 603                 goto reg_err;
 604         }
 605
 606         for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
 607                 if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
 608                         goto reg_err;
 609
 610         DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
 611         return dev;
 612
 613 reg_err:
 614         qedr_sync_free_irqs(dev);
 615 irq_err:
 616         qedr_stop_hw(dev);
 617 alloc_err:
 618         qedr_free_resources(dev);
 619 init_err:
 620         ib_dealloc_device(&dev->ibdev);
 621         DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
 622
 623         return NULL;
 624 }
 625
 626 static void qedr_remove(struct qedr_dev *dev)
 627 {
 628         /* First unregister with stack to stop all the active traffic
 629          * of the registered clients.
 630          */
 631         qedr_remove_sysfiles(dev);
 632
 633         qedr_stop_hw(dev);
 634         qedr_sync_free_irqs(dev);
 635         qedr_free_resources(dev);
 636         ib_dealloc_device(&dev->ibdev);
 637 }
 638
 639 static int qedr_close(struct qedr_dev *dev)
 640 {
 641         qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
 642
 643         return 0;
 644 }
 645
 646 static void qedr_shutdown(struct qedr_dev *dev)
 647 {
 648         qedr_close(dev);
 649         qedr_remove(dev);
 650 }
 651
 652 /* event handling via NIC driver ensures that all the NIC specific
 653  * initialization done before RoCE driver notifies
 654  * event to stack.
 655  */
 656 static void qedr_notify(struct qedr_dev *dev, enum qede_roce_event event)
 657 {
 658         switch (event) {
 659         case QEDE_UP:
 660                 qedr_ib_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
 661                 break;
 662         case QEDE_DOWN:
 663                 qedr_close(dev);
 664                 break;
 665         case QEDE_CLOSE:
 666                 qedr_shutdown(dev);
 667                 break;
 668         case QEDE_CHANGE_ADDR:
 669                 qedr_ib_dispatch_event(dev, 1, IB_EVENT_GID_CHANGE);
 670                 break;
 671         default:
 672                 pr_err("Event not supported\n");
 673         }
 674 }
 675
 676 static struct qedr_driver qedr_drv = {
 677         .name = "qedr_driver",
 678         .add = qedr_add,
 679         .remove = qedr_remove,
 680         .notify = qedr_notify,
 681 };
 682
 683 static int __init qedr_init_module(void)
 684 {
 685         return qede_roce_register_driver(&qedr_drv);
 686 }
 687
 688 static void __exit qedr_exit_module(void)
 689 {
 690         qede_roce_unregister_driver(&qedr_drv);
 691 }
 692
 693 module_init(qedr_init_module);
 694 module_exit(qedr_exit_module);