drivers/infiniband/hw/ocrdma/ocrdma_sli.h

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) adapters.                   *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #ifndef __OCRDMA_SLI_H__
  29 #define __OCRDMA_SLI_H__
  30
  31 #define Bit(_b) (1 << (_b))
  32
  33 #define OCRDMA_GEN1_FAMILY      0xB
  34 #define OCRDMA_GEN2_FAMILY      0x0F
  35
  36 #define OCRDMA_SUBSYS_ROCE 10
  37 enum {
  38         OCRDMA_CMD_QUERY_CONFIG = 1,
  39         OCRDMA_CMD_ALLOC_PD,
  40         OCRDMA_CMD_DEALLOC_PD,
  41
  42         OCRDMA_CMD_CREATE_AH_TBL,
  43         OCRDMA_CMD_DELETE_AH_TBL,
  44
  45         OCRDMA_CMD_CREATE_QP,
  46         OCRDMA_CMD_QUERY_QP,
  47         OCRDMA_CMD_MODIFY_QP,
  48         OCRDMA_CMD_DELETE_QP,
  49
  50         OCRDMA_CMD_RSVD1,
  51         OCRDMA_CMD_ALLOC_LKEY,
  52         OCRDMA_CMD_DEALLOC_LKEY,
  53         OCRDMA_CMD_REGISTER_NSMR,
  54         OCRDMA_CMD_REREGISTER_NSMR,
  55         OCRDMA_CMD_REGISTER_NSMR_CONT,
  56         OCRDMA_CMD_QUERY_NSMR,
  57         OCRDMA_CMD_ALLOC_MW,
  58         OCRDMA_CMD_QUERY_MW,
  59
  60         OCRDMA_CMD_CREATE_SRQ,
  61         OCRDMA_CMD_QUERY_SRQ,
  62         OCRDMA_CMD_MODIFY_SRQ,
  63         OCRDMA_CMD_DELETE_SRQ,
  64
  65         OCRDMA_CMD_ATTACH_MCAST,
  66         OCRDMA_CMD_DETACH_MCAST,
  67
  68         OCRDMA_CMD_MAX
  69 };
  70
  71 #define OCRDMA_SUBSYS_COMMON 1
  72 enum {
  73         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5,
  74         OCRDMA_CMD_CREATE_CQ            = 12,
  75         OCRDMA_CMD_CREATE_EQ            = 13,
  76         OCRDMA_CMD_CREATE_MQ            = 21,
  77         OCRDMA_CMD_GET_FW_VER           = 35,
  78         OCRDMA_CMD_DELETE_MQ            = 53,
  79         OCRDMA_CMD_DELETE_CQ            = 54,
  80         OCRDMA_CMD_DELETE_EQ            = 55,
  81         OCRDMA_CMD_GET_FW_CONFIG        = 58,
  82         OCRDMA_CMD_CREATE_MQ_EXT        = 90
  83 };
  84
  85 enum {
  86         QTYPE_EQ        = 1,
  87         QTYPE_CQ        = 2,
  88         QTYPE_MCCQ      = 3
  89 };
  90
  91 #define OCRDMA_MAX_SGID (8)
  92
  93 #define OCRDMA_MAX_QP    2048
  94 #define OCRDMA_MAX_CQ    2048
  95 #define OCRDMA_MAX_STAG  8192
  96
  97 enum {
  98         OCRDMA_DB_RQ_OFFSET             = 0xE0,
  99         OCRDMA_DB_GEN2_RQ_OFFSET        = 0x100,
 100         OCRDMA_DB_SQ_OFFSET             = 0x60,
 101         OCRDMA_DB_GEN2_SQ_OFFSET        = 0x1C0,
 102         OCRDMA_DB_SRQ_OFFSET            = OCRDMA_DB_RQ_OFFSET,
 103         OCRDMA_DB_GEN2_SRQ_OFFSET       = OCRDMA_DB_GEN2_RQ_OFFSET,
 104         OCRDMA_DB_CQ_OFFSET             = 0x120,
 105         OCRDMA_DB_EQ_OFFSET             = OCRDMA_DB_CQ_OFFSET,
 106         OCRDMA_DB_MQ_OFFSET             = 0x140
 107 };
 108
 109 #define OCRDMA_DB_CQ_RING_ID_MASK       0x3FF   /* bits 0 - 9 */
 110 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK  0x0C00   /* bits 10-11 of qid at 12-11 */
 111 /* qid #2 msbits at 12-11 */
 112 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT  0x1
 113 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT       (16)        /* bits 16 - 28 */
 114 /* Rearm bit */
 115 #define OCRDMA_DB_CQ_REARM_SHIFT        (29)    /* bit 29 */
 116 /* solicited bit */
 117 #define OCRDMA_DB_CQ_SOLICIT_SHIFT   (31)       /* bit 31 */
 118
 119 #define OCRDMA_EQ_ID_MASK               0x1FF   /* bits 0 - 8 */
 120 #define OCRDMA_EQ_ID_EXT_MASK           0x3e00  /* bits 9-13 */
 121 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT     (2)     /* qid bits 9-13 at 11-15 */
 122
 123 /* Clear the interrupt for this eq */
 124 #define OCRDMA_EQ_CLR_SHIFT                     (9)     /* bit 9 */
 125 /* Must be 1 */
 126 #define OCRDMA_EQ_TYPE_SHIFT            (10)    /* bit 10 */
 127 /* Number of event entries processed */
 128 #define OCRDMA_NUM_EQE_SHIFT            (16)    /* bits 16 - 28 */
 129 /* Rearm bit */
 130 #define OCRDMA_REARM_SHIFT              (29)    /* bit 29 */
 131
 132 #define OCRDMA_MQ_ID_MASK               0x7FF   /* bits 0 - 10 */
 133 /* Number of entries posted */
 134 #define OCRDMA_MQ_NUM_MQE_SHIFT (16)    /* bits 16 - 29 */
 135
 136 #define OCRDMA_MIN_HPAGE_SIZE (4096)
 137
 138 #define OCRDMA_MIN_Q_PAGE_SIZE (4096)
 139 #define OCRDMA_MAX_Q_PAGES     (8)
 140
 141 /*
 142 # 0: 4K Bytes
 143 # 1: 8K Bytes
 144 # 2: 16K Bytes
 145 # 3: 32K Bytes
 146 # 4: 64K Bytes
 147 # 5: 128K Bytes
 148 # 6: 256K Bytes
 149 # 7: 512K Bytes
 150 */
 151 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (8)
 152 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
 153
 154 #define MAX_OCRDMA_QP_PAGES      (8)
 155 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
 156
 157 #define OCRDMA_CREATE_CQ_MAX_PAGES (4)
 158 #define OCRDMA_DPP_CQE_SIZE (4)
 159
 160 #define OCRDMA_GEN2_MAX_CQE 1024
 161 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
 162 #define OCRDMA_GEN2_WQE_SIZE 256
 163 #define OCRDMA_MAX_CQE  4095
 164 #define OCRDMA_CQ_PAGE_SIZE 16384
 165 #define OCRDMA_WQE_SIZE 128
 166 #define OCRDMA_WQE_STRIDE 8
 167 #define OCRDMA_WQE_ALIGN_BYTES 16
 168
 169 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
 170
 171 enum {
 172         OCRDMA_MCH_OPCODE_SHIFT = 0,
 173         OCRDMA_MCH_OPCODE_MASK  = 0xFF,
 174         OCRDMA_MCH_SUBSYS_SHIFT = 8,
 175         OCRDMA_MCH_SUBSYS_MASK  = 0xFF00
 176 };
 177
 178 /* mailbox cmd header */
 179 struct ocrdma_mbx_hdr {
 180         u32 subsys_op;
 181         u32 timeout;            /* in seconds */
 182         u32 cmd_len;
 183         u32 rsvd_version;
 184 };
 185
 186 enum {
 187         OCRDMA_MBX_RSP_OPCODE_SHIFT     = 0,
 188         OCRDMA_MBX_RSP_OPCODE_MASK      = 0xFF,
 189         OCRDMA_MBX_RSP_SUBSYS_SHIFT     = 8,
 190         OCRDMA_MBX_RSP_SUBSYS_MASK      = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,
 191
 192         OCRDMA_MBX_RSP_STATUS_SHIFT     = 0,
 193         OCRDMA_MBX_RSP_STATUS_MASK      = 0xFF,
 194         OCRDMA_MBX_RSP_ASTATUS_SHIFT    = 8,
 195         OCRDMA_MBX_RSP_ASTATUS_MASK     = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
 196 };
 197
 198 /* mailbox cmd response */
 199 struct ocrdma_mbx_rsp {
 200         u32 subsys_op;
 201         u32 status;
 202         u32 rsp_len;
 203         u32 add_rsp_len;
 204 };
 205
 206 enum {
 207         OCRDMA_MQE_EMBEDDED     = 1,
 208         OCRDMA_MQE_NONEMBEDDED  = 0
 209 };
 210
 211 struct ocrdma_mqe_sge {
 212         u32 pa_lo;
 213         u32 pa_hi;
 214         u32 len;
 215 };
 216
 217 enum {
 218         OCRDMA_MQE_HDR_EMB_SHIFT        = 0,
 219         OCRDMA_MQE_HDR_EMB_MASK         = Bit(0),
 220         OCRDMA_MQE_HDR_SGE_CNT_SHIFT    = 3,
 221         OCRDMA_MQE_HDR_SGE_CNT_MASK     = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
 222         OCRDMA_MQE_HDR_SPECIAL_SHIFT    = 24,
 223         OCRDMA_MQE_HDR_SPECIAL_MASK     = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
 224 };
 225
 226 struct ocrdma_mqe_hdr {
 227         u32 spcl_sge_cnt_emb;
 228         u32 pyld_len;
 229         u32 tag_lo;
 230         u32 tag_hi;
 231         u32 rsvd3;
 232 };
 233
 234 struct ocrdma_mqe_emb_cmd {
 235         struct ocrdma_mbx_hdr mch;
 236         u8 pyld[220];
 237 };
 238
 239 struct ocrdma_mqe {
 240         struct ocrdma_mqe_hdr hdr;
 241         union {
 242                 struct ocrdma_mqe_emb_cmd emb_req;
 243                 struct {
 244                         struct ocrdma_mqe_sge sge[19];
 245                 } nonemb_req;
 246                 u8 cmd[236];
 247                 struct ocrdma_mbx_rsp rsp;
 248         } u;
 249 };
 250
 251 #define OCRDMA_EQ_LEN       4096
 252 #define OCRDMA_MQ_CQ_LEN    256
 253 #define OCRDMA_MQ_LEN       128
 254
 255 #define PAGE_SHIFT_4K           12
 256 #define PAGE_SIZE_4K            (1 << PAGE_SHIFT_4K)
 257
 258 /* Returns number of pages spanned by the data starting at the given addr */
 259 #define PAGES_4K_SPANNED(_address, size) \
 260         ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +     \
 261                         (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
 262
 263 struct ocrdma_delete_q_req {
 264         struct ocrdma_mbx_hdr req;
 265         u32 id;
 266 };
 267
 268 struct ocrdma_pa {
 269         u32 lo;
 270         u32 hi;
 271 };
 272
 273 #define MAX_OCRDMA_EQ_PAGES (8)
 274 struct ocrdma_create_eq_req {
 275         struct ocrdma_mbx_hdr req;
 276         u32 num_pages;
 277         u32 valid;
 278         u32 cnt;
 279         u32 delay;
 280         u32 rsvd;
 281         struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];
 282 };
 283
 284 enum {
 285         OCRDMA_CREATE_EQ_VALID  = Bit(29),
 286         OCRDMA_CREATE_EQ_CNT_SHIFT      = 26,
 287         OCRDMA_CREATE_CQ_DELAY_SHIFT    = 13,
 288 };
 289
 290 struct ocrdma_create_eq_rsp {
 291         struct ocrdma_mbx_rsp rsp;
 292         u32 vector_eqid;
 293 };
 294
 295 #define OCRDMA_EQ_MINOR_OTHER (0x1)
 296
 297 enum {
 298         OCRDMA_MCQE_STATUS_SHIFT        = 0,
 299         OCRDMA_MCQE_STATUS_MASK         = 0xFFFF,
 300         OCRDMA_MCQE_ESTATUS_SHIFT       = 16,
 301         OCRDMA_MCQE_ESTATUS_MASK        = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
 302         OCRDMA_MCQE_CONS_SHIFT          = 27,
 303         OCRDMA_MCQE_CONS_MASK           = Bit(27),
 304         OCRDMA_MCQE_CMPL_SHIFT          = 28,
 305         OCRDMA_MCQE_CMPL_MASK           = Bit(28),
 306         OCRDMA_MCQE_AE_SHIFT            = 30,
 307         OCRDMA_MCQE_AE_MASK             = Bit(30),
 308         OCRDMA_MCQE_VALID_SHIFT         = 31,
 309         OCRDMA_MCQE_VALID_MASK          = Bit(31)
 310 };
 311
 312 struct ocrdma_mcqe {
 313         u32 status;
 314         u32 tag_lo;
 315         u32 tag_hi;
 316         u32 valid_ae_cmpl_cons;
 317 };
 318
 319 enum {
 320         OCRDMA_AE_MCQE_QPVALID          = Bit(31),
 321         OCRDMA_AE_MCQE_QPID_MASK        = 0xFFFF,
 322
 323         OCRDMA_AE_MCQE_CQVALID          = Bit(31),
 324         OCRDMA_AE_MCQE_CQID_MASK        = 0xFFFF,
 325         OCRDMA_AE_MCQE_VALID            = Bit(31),
 326         OCRDMA_AE_MCQE_AE               = Bit(30),
 327         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
 328         OCRDMA_AE_MCQE_EVENT_TYPE_MASK  =
 329                                         0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
 330         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,
 331         OCRDMA_AE_MCQE_EVENT_CODE_MASK  =
 332                                         0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
 333 };
 334 struct ocrdma_ae_mcqe {
 335         u32 qpvalid_qpid;
 336         u32 cqvalid_cqid;
 337         u32 evt_tag;
 338         u32 valid_ae_event;
 339 };
 340
 341 enum {
 342         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0,
 343         OCRDMA_AE_PVID_MCQE_ENABLED_MASK  = 0xFF,
 344         OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16,
 345         OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT
 346 };
 347
 348 struct ocrdma_ae_pvid_mcqe {
 349         u32 tag_enabled;
 350         u32 event_tag;
 351         u32 rsvd1;
 352         u32 rsvd2;
 353 };
 354
 355 enum {
 356         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT         = 16,
 357         OCRDMA_AE_MPA_MCQE_REQ_ID_MASK          = 0xFFFF <<
 358                                         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
 359
 360         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT     = 8,
 361         OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK      = 0xFF <<
 362                                         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
 363         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT     = 16,
 364         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK      = 0xFF <<
 365                                         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
 366         OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT       = 30,
 367         OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK        = Bit(30),
 368         OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT    = 31,
 369         OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK     = Bit(31)
 370 };
 371
 372 struct ocrdma_ae_mpa_mcqe {
 373         u32 req_id;
 374         u32 w1;
 375         u32 w2;
 376         u32 valid_ae_event;
 377 };
 378
 379 enum {
 380         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT    = 0,
 381         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK     = 0xFFFF,
 382         OCRDMA_AE_QP_MCQE_QP_ID_SHIFT           = 16,
 383         OCRDMA_AE_QP_MCQE_QP_ID_MASK            = 0xFFFF <<
 384                                                 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
 385
 386         OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT      = 8,
 387         OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK       = 0xFF <<
 388                                 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
 389         OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT      = 16,
 390         OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK       = 0xFF <<
 391                                 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
 392         OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT        = 30,
 393         OCRDMA_AE_QP_MCQE_EVENT_AE_MASK         = Bit(30),
 394         OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT     = 31,
 395         OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK      = Bit(31)
 396 };
 397
 398 struct ocrdma_ae_qp_mcqe {
 399         u32 qp_id_state;
 400         u32 w1;
 401         u32 w2;
 402         u32 valid_ae_event;
 403 };
 404
 405 #define OCRDMA_ASYNC_RDMA_EVE_CODE 0x14
 406 #define OCRDMA_ASYNC_GRP5_EVE_CODE 0x5
 407 #define OCRDMA_ASYNC_EVENT_PVID_STATE 0x3
 408
 409 enum OCRDMA_ASYNC_EVENT_TYPE {
 410         OCRDMA_CQ_ERROR                 = 0x00,
 411         OCRDMA_CQ_OVERRUN_ERROR         = 0x01,
 412         OCRDMA_CQ_QPCAT_ERROR           = 0x02,
 413         OCRDMA_QP_ACCESS_ERROR          = 0x03,
 414         OCRDMA_QP_COMM_EST_EVENT        = 0x04,
 415         OCRDMA_SQ_DRAINED_EVENT         = 0x05,
 416         OCRDMA_DEVICE_FATAL_EVENT       = 0x08,
 417         OCRDMA_SRQCAT_ERROR             = 0x0E,
 418         OCRDMA_SRQ_LIMIT_EVENT          = 0x0F,
 419         OCRDMA_QP_LAST_WQE_EVENT        = 0x10
 420 };
 421
 422 /* mailbox command request and responses */
 423 enum {
 424         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT          = 2,
 425         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK           = Bit(2),
 426         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT        = 3,
 427         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK         = Bit(3),
 428         OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT               = 8,
 429         OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK                = 0xFFFFFF <<
 430                                 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
 431
 432         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT               = 16,
 433         OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK                = 0xFFFF <<
 434                                         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
 435         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT         = 8,
 436         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK          = 0xFF <<
 437                                 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
 438
 439         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT         = 0,
 440         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK          = 0xFFFF,
 441         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT        = 16,
 442         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK         = 0xFFFF <<
 443                                 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT,
 444
 445         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT       = 0,
 446         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK        = 0xFFFF,
 447         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT       = 16,
 448         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK        = 0xFFFF <<
 449                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
 450
 451         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET        = 24,
 452         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK          = 0xFF <<
 453                                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
 454         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET        = 16,
 455         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK          = 0xFF <<
 456                                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
 457         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET        = 0,
 458         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK          = 0xFFFF <<
 459                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
 460
 461         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET             = 16,
 462         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK               = 0xFFFF <<
 463                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
 464         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET        = 0,
 465         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK          = 0xFFFF <<
 466                                 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
 467
 468         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET         = 16,
 469         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK           = 0xFFFF <<
 470                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
 471         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET     = 0,
 472         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK       = 0xFFFF <<
 473                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
 474
 475         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET         = 0,
 476         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK           = 0xFFFF <<
 477                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
 478
 479         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET     = 16,
 480         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK       = 0xFFFF <<
 481                                 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
 482         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET     = 0,
 483         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK       = 0xFFFF <<
 484                                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,
 485
 486         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET              = 16,
 487         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK                = 0xFFFF <<
 488                                 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
 489         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET     = 0,
 490         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK       = 0xFFFF <<
 491                                 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
 492
 493         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET         = 16,
 494         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK           = 0xFFFF <<
 495                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
 496         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET         = 0,
 497         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK           = 0xFFFF <<
 498                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
 499 };
 500
 501 struct ocrdma_mbx_query_config {
 502         struct ocrdma_mqe_hdr hdr;
 503         struct ocrdma_mbx_rsp rsp;
 504         u32 qp_srq_cq_ird_ord;
 505         u32 max_pd_ca_ack_delay;
 506         u32 max_write_send_sge;
 507         u32 max_ird_ord_per_qp;
 508         u32 max_shared_ird_ord;
 509         u32 max_mr;
 510         u32 max_mr_size_lo;
 511         u32 max_mr_size_hi;
 512         u32 max_num_mr_pbl;
 513         u32 max_mw;
 514         u32 max_fmr;
 515         u32 max_pages_per_frmr;
 516         u32 max_mcast_group;
 517         u32 max_mcast_qp_attach;
 518         u32 max_total_mcast_qp_attach;
 519         u32 wqe_rqe_stride_max_dpp_cqs;
 520         u32 max_srq_rpir_qps;
 521         u32 max_dpp_pds_credits;
 522         u32 max_dpp_credits_pds_per_pd;
 523         u32 max_wqes_rqes_per_q;
 524         u32 max_cq_cqes_per_cq;
 525         u32 max_srq_rqe_sge;
 526 };
 527
 528 struct ocrdma_fw_ver_rsp {
 529         struct ocrdma_mqe_hdr hdr;
 530         struct ocrdma_mbx_rsp rsp;
 531
 532         u8 running_ver[32];
 533 };
 534
 535 struct ocrdma_fw_conf_rsp {
 536         struct ocrdma_mqe_hdr hdr;
 537         struct ocrdma_mbx_rsp rsp;
 538
 539         u32 config_num;
 540         u32 asic_revision;
 541         u32 phy_port;
 542         u32 fn_mode;
 543         struct {
 544                 u32 mode;
 545                 u32 nic_wqid_base;
 546                 u32 nic_wq_tot;
 547                 u32 prot_wqid_base;
 548                 u32 prot_wq_tot;
 549                 u32 prot_rqid_base;
 550                 u32 prot_rqid_tot;
 551                 u32 rsvd[6];
 552         } ulp[2];
 553         u32 fn_capabilities;
 554         u32 rsvd1;
 555         u32 rsvd2;
 556         u32 base_eqid;
 557         u32 max_eq;
 558
 559 };
 560
 561 enum {
 562         OCRDMA_FN_MODE_RDMA     = 0x4
 563 };
 564
 565 struct ocrdma_get_link_speed_rsp {
 566         struct ocrdma_mqe_hdr hdr;
 567         struct ocrdma_mbx_rsp rsp;
 568
 569         u8 pt_port_num;
 570         u8 link_duplex;
 571         u8 phys_port_speed;
 572         u8 phys_port_fault;
 573         u16 rsvd1;
 574         u16 qos_lnk_speed;
 575         u8 logical_lnk_status;
 576         u8 rsvd2[3];
 577 };
 578
 579 enum {
 580         OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0,
 581         OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1,
 582         OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2,
 583         OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3,
 584         OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4,
 585         OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5,
 586         OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6,
 587         OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7,
 588         OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8
 589 };
 590
 591 enum {
 592         OCRDMA_CREATE_CQ_VER2                   = 2,
 593         OCRDMA_CREATE_CQ_VER3                   = 3,
 594
 595         OCRDMA_CREATE_CQ_PAGE_CNT_MASK          = 0xFFFF,
 596         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT        = 16,
 597         OCRDMA_CREATE_CQ_PAGE_SIZE_MASK         = 0xFF,
 598
 599         OCRDMA_CREATE_CQ_COALESCWM_SHIFT        = 12,
 600         OCRDMA_CREATE_CQ_COALESCWM_MASK         = Bit(13) | Bit(12),
 601         OCRDMA_CREATE_CQ_FLAGS_NODELAY          = Bit(14),
 602         OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID       = Bit(15),
 603
 604         OCRDMA_CREATE_CQ_EQ_ID_MASK             = 0xFFFF,
 605         OCRDMA_CREATE_CQ_CQE_COUNT_MASK         = 0xFFFF
 606 };
 607
 608 enum {
 609         OCRDMA_CREATE_CQ_VER0                   = 0,
 610         OCRDMA_CREATE_CQ_DPP                    = 1,
 611         OCRDMA_CREATE_CQ_TYPE_SHIFT             = 24,
 612         OCRDMA_CREATE_CQ_EQID_SHIFT             = 22,
 613
 614         OCRDMA_CREATE_CQ_CNT_SHIFT              = 27,
 615         OCRDMA_CREATE_CQ_FLAGS_VALID            = Bit(29),
 616         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE        = Bit(31),
 617         OCRDMA_CREATE_CQ_DEF_FLAGS              = OCRDMA_CREATE_CQ_FLAGS_VALID |
 618                                         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
 619                                         OCRDMA_CREATE_CQ_FLAGS_NODELAY
 620 };
 621
 622 struct ocrdma_create_cq_cmd {
 623         struct ocrdma_mbx_hdr req;
 624         u32 pgsz_pgcnt;
 625         u32 ev_cnt_flags;
 626         u32 eqn;
 627         u16 cqe_count;
 628         u16 pd_id;
 629         u32 rsvd6;
 630         struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];
 631 };
 632
 633 struct ocrdma_create_cq {
 634         struct ocrdma_mqe_hdr hdr;
 635         struct ocrdma_create_cq_cmd cmd;
 636 };
 637
 638 enum {
 639         OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF
 640 };
 641
 642 struct ocrdma_create_cq_cmd_rsp {
 643         struct ocrdma_mbx_rsp rsp;
 644         u32 cq_id;
 645 };
 646
 647 struct ocrdma_create_cq_rsp {
 648         struct ocrdma_mqe_hdr hdr;
 649         struct ocrdma_create_cq_cmd_rsp rsp;
 650 };
 651
 652 enum {
 653         OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT         = 22,
 654         OCRDMA_CREATE_MQ_CQ_ID_SHIFT            = 16,
 655         OCRDMA_CREATE_MQ_RING_SIZE_SHIFT        = 16,
 656         OCRDMA_CREATE_MQ_VALID                  = Bit(31),
 657         OCRDMA_CREATE_MQ_ASYNC_CQ_VALID         = Bit(0)
 658 };
 659
 660 struct ocrdma_create_mq_req {
 661         struct ocrdma_mbx_hdr req;
 662         u32 cqid_pages;
 663         u32 async_event_bitmap;
 664         u32 async_cqid_ringsize;
 665         u32 valid;
 666         u32 async_cqid_valid;
 667         u32 rsvd;
 668         struct ocrdma_pa pa[8];
 669 };
 670
 671 struct ocrdma_create_mq_rsp {
 672         struct ocrdma_mbx_rsp rsp;
 673         u32 id;
 674 };
 675
 676 enum {
 677         OCRDMA_DESTROY_CQ_QID_SHIFT                     = 0,
 678         OCRDMA_DESTROY_CQ_QID_MASK                      = 0xFFFF,
 679         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT        = 16,
 680         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK         = 0xFFFF <<
 681                                 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
 682 };
 683
 684 struct ocrdma_destroy_cq {
 685         struct ocrdma_mqe_hdr hdr;
 686         struct ocrdma_mbx_hdr req;
 687
 688         u32 bypass_flush_qid;
 689 };
 690
 691 struct ocrdma_destroy_cq_rsp {
 692         struct ocrdma_mqe_hdr hdr;
 693         struct ocrdma_mbx_rsp rsp;
 694 };
 695
 696 enum {
 697         OCRDMA_QPT_GSI  = 1,
 698         OCRDMA_QPT_RC   = 2,
 699         OCRDMA_QPT_UD   = 4,
 700 };
 701
 702 enum {
 703         OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT        = 0,
 704         OCRDMA_CREATE_QP_REQ_PD_ID_MASK         = 0xFFFF,
 705         OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
 706         OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
 707         OCRDMA_CREATE_QP_REQ_QPT_SHIFT          = 29,
 708         OCRDMA_CREATE_QP_REQ_QPT_MASK           = Bit(31) | Bit(30) | Bit(29),
 709
 710         OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT      = 0,
 711         OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK       = 0xFFFF,
 712         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT      = 16,
 713         OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK       = 0xFFFF <<
 714                                         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
 715
 716         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT        = 0,
 717         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK         = 0xFFFF,
 718         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT         = 16,
 719         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK          = 0xFFFF <<
 720                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
 721
 722         OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT               = 0,
 723         OCRDMA_CREATE_QP_REQ_FMR_EN_MASK                = Bit(0),
 724         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT          = 1,
 725         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK           = Bit(1),
 726         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT          = 2,
 727         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK           = Bit(2),
 728         OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT             = 3,
 729         OCRDMA_CREATE_QP_REQ_INB_WREN_MASK              = Bit(3),
 730         OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT             = 4,
 731         OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK              = Bit(4),
 732         OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT              = 5,
 733         OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK               = Bit(5),
 734         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT          = 6,
 735         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK           = Bit(6),
 736         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT           = 7,
 737         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK            = Bit(7),
 738         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT        = 8,
 739         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK         = Bit(8),
 740         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT         = 16,
 741         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK          = 0xFFFF <<
 742                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
 743
 744         OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT              = 0,
 745         OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK               = 0xFFFF,
 746         OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT              = 16,
 747         OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK               = 0xFFFF <<
 748                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
 749
 750         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT         = 0,
 751         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK          = 0xFFFF,
 752         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT         = 16,
 753         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK          = 0xFFFF <<
 754                                 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
 755
 756         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT             = 0,
 757         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK              = 0xFFFF,
 758         OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT             = 16,
 759         OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK              = 0xFFFF <<
 760                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
 761
 762         OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT              = 0,
 763         OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK               = 0xFFFF,
 764         OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT              = 16,
 765         OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK               = 0xFFFF <<
 766                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
 767
 768         OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT            = 0,
 769         OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK             = 0xFFFF,
 770         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT           = 16,
 771         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK            = 0xFFFF <<
 772                                 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
 773 };
 774
 775 enum {
 776         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT   = 16,
 777         OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT     = 1
 778 };
 779
 780 #define MAX_OCRDMA_IRD_PAGES 4
 781
 782 enum ocrdma_qp_flags {
 783         OCRDMA_QP_MW_BIND       = 1,
 784         OCRDMA_QP_LKEY0         = (1 << 1),
 785         OCRDMA_QP_FAST_REG      = (1 << 2),
 786         OCRDMA_QP_INB_RD        = (1 << 6),
 787         OCRDMA_QP_INB_WR        = (1 << 7),
 788 };
 789
 790 enum ocrdma_qp_state {
 791         OCRDMA_QPS_RST          = 0,
 792         OCRDMA_QPS_INIT         = 1,
 793         OCRDMA_QPS_RTR          = 2,
 794         OCRDMA_QPS_RTS          = 3,
 795         OCRDMA_QPS_SQE          = 4,
 796         OCRDMA_QPS_SQ_DRAINING  = 5,
 797         OCRDMA_QPS_ERR          = 6,
 798         OCRDMA_QPS_SQD          = 7
 799 };
 800
 801 struct ocrdma_create_qp_req {
 802         struct ocrdma_mqe_hdr hdr;
 803         struct ocrdma_mbx_hdr req;
 804
 805         u32 type_pgsz_pdn;
 806         u32 max_wqe_rqe;
 807         u32 max_sge_send_write;
 808         u32 max_sge_recv_flags;
 809         u32 max_ord_ird;
 810         u32 num_wq_rq_pages;
 811         u32 wqe_rqe_size;
 812         u32 wq_rq_cqid;
 813         struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];
 814         struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];
 815         u32 dpp_credits_cqid;
 816         u32 rpir_lkey;
 817         struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];
 818 };
 819
 820 enum {
 821         OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT                = 0,
 822         OCRDMA_CREATE_QP_RSP_QP_ID_MASK                 = 0xFFFF,
 823
 824         OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT              = 0,
 825         OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK               = 0xFFFF,
 826         OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT              = 16,
 827         OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK               = 0xFFFF <<
 828                                 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
 829
 830         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT        = 0,
 831         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK         = 0xFFFF,
 832         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT         = 16,
 833         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK          = 0xFFFF <<
 834                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
 835
 836         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT         = 16,
 837         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK          = 0xFFFF <<
 838                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
 839
 840         OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT              = 0,
 841         OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK               = 0xFFFF,
 842         OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT              = 16,
 843         OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK               = 0xFFFF <<
 844                                 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
 845
 846         OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT                = 0,
 847         OCRDMA_CREATE_QP_RSP_RQ_ID_MASK                 = 0xFFFF,
 848         OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT                = 16,
 849         OCRDMA_CREATE_QP_RSP_SQ_ID_MASK                 = 0xFFFF <<
 850                                 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
 851
 852         OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK           = Bit(0),
 853         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT      = 1,
 854         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK       = 0x7FFF <<
 855                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
 856         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT          = 16,
 857         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK           = 0xFFFF <<
 858                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
 859 };
 860
 861 struct ocrdma_create_qp_rsp {
 862         struct ocrdma_mqe_hdr hdr;
 863         struct ocrdma_mbx_rsp rsp;
 864
 865         u32 qp_id;
 866         u32 max_wqe_rqe;
 867         u32 max_sge_send_write;
 868         u32 max_sge_recv;
 869         u32 max_ord_ird;
 870         u32 sq_rq_id;
 871         u32 dpp_response;
 872 };
 873
 874 struct ocrdma_destroy_qp {
 875         struct ocrdma_mqe_hdr hdr;
 876         struct ocrdma_mbx_hdr req;
 877         u32 qp_id;
 878 };
 879
 880 struct ocrdma_destroy_qp_rsp {
 881         struct ocrdma_mqe_hdr hdr;
 882         struct ocrdma_mbx_rsp rsp;
 883 };
 884
 885 enum {
 886         OCRDMA_MODIFY_QP_ID_SHIFT       = 0,
 887         OCRDMA_MODIFY_QP_ID_MASK        = 0xFFFF,
 888
 889         OCRDMA_QP_PARA_QPS_VALID        = Bit(0),
 890         OCRDMA_QP_PARA_SQD_ASYNC_VALID  = Bit(1),
 891         OCRDMA_QP_PARA_PKEY_VALID       = Bit(2),
 892         OCRDMA_QP_PARA_QKEY_VALID       = Bit(3),
 893         OCRDMA_QP_PARA_PMTU_VALID       = Bit(4),
 894         OCRDMA_QP_PARA_ACK_TO_VALID     = Bit(5),
 895         OCRDMA_QP_PARA_RETRY_CNT_VALID  = Bit(6),
 896         OCRDMA_QP_PARA_RRC_VALID        = Bit(7),
 897         OCRDMA_QP_PARA_RQPSN_VALID      = Bit(8),
 898         OCRDMA_QP_PARA_MAX_IRD_VALID    = Bit(9),
 899         OCRDMA_QP_PARA_MAX_ORD_VALID    = Bit(10),
 900         OCRDMA_QP_PARA_RNT_VALID        = Bit(11),
 901         OCRDMA_QP_PARA_SQPSN_VALID      = Bit(12),
 902         OCRDMA_QP_PARA_DST_QPN_VALID    = Bit(13),
 903         OCRDMA_QP_PARA_MAX_WQE_VALID    = Bit(14),
 904         OCRDMA_QP_PARA_MAX_RQE_VALID    = Bit(15),
 905         OCRDMA_QP_PARA_SGE_SEND_VALID   = Bit(16),
 906         OCRDMA_QP_PARA_SGE_RECV_VALID   = Bit(17),
 907         OCRDMA_QP_PARA_SGE_WR_VALID     = Bit(18),
 908         OCRDMA_QP_PARA_INB_RDEN_VALID   = Bit(19),
 909         OCRDMA_QP_PARA_INB_WREN_VALID   = Bit(20),
 910         OCRDMA_QP_PARA_FLOW_LBL_VALID   = Bit(21),
 911         OCRDMA_QP_PARA_BIND_EN_VALID    = Bit(22),
 912         OCRDMA_QP_PARA_ZLKEY_EN_VALID   = Bit(23),
 913         OCRDMA_QP_PARA_FMR_EN_VALID     = Bit(24),
 914         OCRDMA_QP_PARA_INBAT_EN_VALID   = Bit(25),
 915         OCRDMA_QP_PARA_VLAN_EN_VALID    = Bit(26),
 916
 917         OCRDMA_MODIFY_QP_FLAGS_RD       = Bit(0),
 918         OCRDMA_MODIFY_QP_FLAGS_WR       = Bit(1),
 919         OCRDMA_MODIFY_QP_FLAGS_SEND     = Bit(2),
 920         OCRDMA_MODIFY_QP_FLAGS_ATOMIC   = Bit(3)
 921 };
 922
 923 enum {
 924         OCRDMA_QP_PARAMS_SRQ_ID_SHIFT           = 0,
 925         OCRDMA_QP_PARAMS_SRQ_ID_MASK            = 0xFFFF,
 926
 927         OCRDMA_QP_PARAMS_MAX_RQE_SHIFT          = 0,
 928         OCRDMA_QP_PARAMS_MAX_RQE_MASK           = 0xFFFF,
 929         OCRDMA_QP_PARAMS_MAX_WQE_SHIFT          = 16,
 930         OCRDMA_QP_PARAMS_MAX_WQE_MASK           = 0xFFFF <<
 931             OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
 932
 933         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT    = 0,
 934         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK     = 0xFFFF,
 935         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT     = 16,
 936         OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK      = 0xFFFF <<
 937                                         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
 938
 939         OCRDMA_QP_PARAMS_FLAGS_FMR_EN           = Bit(0),
 940         OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN        = Bit(1),
 941         OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN       = Bit(2),
 942         OCRDMA_QP_PARAMS_FLAGS_INBWR_EN         = Bit(3),
 943         OCRDMA_QP_PARAMS_FLAGS_INBRD_EN         = Bit(4),
 944         OCRDMA_QP_PARAMS_STATE_SHIFT            = 5,
 945         OCRDMA_QP_PARAMS_STATE_MASK             = Bit(5) | Bit(6) | Bit(7),
 946         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC        = Bit(8),
 947         OCRDMA_QP_PARAMS_FLAGS_INB_ATEN         = Bit(9),
 948         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT     = 16,
 949         OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK      = 0xFFFF <<
 950                                         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
 951
 952         OCRDMA_QP_PARAMS_MAX_IRD_SHIFT          = 0,
 953         OCRDMA_QP_PARAMS_MAX_IRD_MASK           = 0xFFFF,
 954         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT          = 16,
 955         OCRDMA_QP_PARAMS_MAX_ORD_MASK           = 0xFFFF <<
 956                                         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
 957
 958         OCRDMA_QP_PARAMS_RQ_CQID_SHIFT          = 0,
 959         OCRDMA_QP_PARAMS_RQ_CQID_MASK           = 0xFFFF,
 960         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT          = 16,
 961         OCRDMA_QP_PARAMS_WQ_CQID_MASK           = 0xFFFF <<
 962                                         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
 963
 964         OCRDMA_QP_PARAMS_RQ_PSN_SHIFT           = 0,
 965         OCRDMA_QP_PARAMS_RQ_PSN_MASK            = 0xFFFFFF,
 966         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT          = 24,
 967         OCRDMA_QP_PARAMS_HOP_LMT_MASK           = 0xFF <<
 968                                         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
 969
 970         OCRDMA_QP_PARAMS_SQ_PSN_SHIFT           = 0,
 971         OCRDMA_QP_PARAMS_SQ_PSN_MASK            = 0xFFFFFF,
 972         OCRDMA_QP_PARAMS_TCLASS_SHIFT           = 24,
 973         OCRDMA_QP_PARAMS_TCLASS_MASK            = 0xFF <<
 974                                         OCRDMA_QP_PARAMS_TCLASS_SHIFT,
 975
 976         OCRDMA_QP_PARAMS_DEST_QPN_SHIFT         = 0,
 977         OCRDMA_QP_PARAMS_DEST_QPN_MASK          = 0xFFFFFF,
 978         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT    = 24,
 979         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK     = 0x7 <<
 980                                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
 981         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT      = 27,
 982         OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK       = 0x1F <<
 983                                         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
 984
 985         OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT       = 0,
 986         OCRDMA_QP_PARAMS_PKEY_INDEX_MASK        = 0xFFFF,
 987         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT         = 18,
 988         OCRDMA_QP_PARAMS_PATH_MTU_MASK          = 0x3FFF <<
 989                                         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
 990
 991         OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT       = 0,
 992         OCRDMA_QP_PARAMS_FLOW_LABEL_MASK        = 0xFFFFF,
 993         OCRDMA_QP_PARAMS_SL_SHIFT               = 20,
 994         OCRDMA_QP_PARAMS_SL_MASK                = 0xF <<
 995                                         OCRDMA_QP_PARAMS_SL_SHIFT,
 996         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT        = 24,
 997         OCRDMA_QP_PARAMS_RETRY_CNT_MASK         = 0x7 <<
 998                                         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
 999         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT    = 27,
1000         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK     = 0x1F <<
1001                                         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
1002
1003         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT    = 0,
1004         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK     = 0xFFFF,
1005         OCRDMA_QP_PARAMS_VLAN_SHIFT             = 16,
1006         OCRDMA_QP_PARAMS_VLAN_MASK              = 0xFFFF <<
1007                                         OCRDMA_QP_PARAMS_VLAN_SHIFT
1008 };
1009
1010 struct ocrdma_qp_params {
1011         u32 id;
1012         u32 max_wqe_rqe;
1013         u32 max_sge_send_write;
1014         u32 max_sge_recv_flags;
1015         u32 max_ord_ird;
1016         u32 wq_rq_cqid;
1017         u32 hop_lmt_rq_psn;
1018         u32 tclass_sq_psn;
1019         u32 ack_to_rnr_rtc_dest_qpn;
1020         u32 path_mtu_pkey_indx;
1021         u32 rnt_rc_sl_fl;
1022         u8 sgid[16];
1023         u8 dgid[16];
1024         u32 dmac_b0_to_b3;
1025         u32 vlan_dmac_b4_to_b5;
1026         u32 qkey;
1027 };
1028
1029
1030 struct ocrdma_modify_qp {
1031         struct ocrdma_mqe_hdr hdr;
1032         struct ocrdma_mbx_hdr req;
1033
1034         struct ocrdma_qp_params params;
1035         u32 flags;
1036         u32 rdma_flags;
1037         u32 num_outstanding_atomic_rd;
1038 };
1039
1040 enum {
1041         OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT      = 0,
1042         OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK       = 0xFFFF,
1043         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT      = 16,
1044         OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK       = 0xFFFF <<
1045                                         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1046
1047         OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT      = 0,
1048         OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK       = 0xFFFF,
1049         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT      = 16,
1050         OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK       = 0xFFFF <<
1051                                         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1052 };
1053 struct ocrdma_modify_qp_rsp {
1054         struct ocrdma_mqe_hdr hdr;
1055         struct ocrdma_mbx_rsp rsp;
1056
1057         u32 max_wqe_rqe;
1058         u32 max_ord_ird;
1059 };
1060
1061 struct ocrdma_query_qp {
1062         struct ocrdma_mqe_hdr hdr;
1063         struct ocrdma_mbx_hdr req;
1064
1065 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0
1066 #define OCRDMA_QUERY_UP_QP_ID_MASK   0xFFFFFF
1067         u32 qp_id;
1068 };
1069
1070 struct ocrdma_query_qp_rsp {
1071         struct ocrdma_mqe_hdr hdr;
1072         struct ocrdma_mbx_rsp rsp;
1073         struct ocrdma_qp_params params;
1074 };
1075
1076 enum {
1077         OCRDMA_CREATE_SRQ_PD_ID_SHIFT           = 0,
1078         OCRDMA_CREATE_SRQ_PD_ID_MASK            = 0xFFFF,
1079         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT           = 16,
1080         OCRDMA_CREATE_SRQ_PG_SZ_MASK            = 0x3 <<
1081                                         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1082
1083         OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT         = 0,
1084         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT    = 16,
1085         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK     = 0xFFFF <<
1086                                         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1087
1088         OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT        = 0,
1089         OCRDMA_CREATE_SRQ_RQE_SIZE_MASK         = 0xFFFF,
1090         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT    = 16,
1091         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK     = 0xFFFF <<
1092                                         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1093 };
1094
1095 struct ocrdma_create_srq {
1096         struct ocrdma_mqe_hdr hdr;
1097         struct ocrdma_mbx_hdr req;
1098
1099         u32 pgsz_pdid;
1100         u32 max_sge_rqe;
1101         u32 pages_rqe_sz;
1102         struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];
1103 };
1104
1105 enum {
1106         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT                      = 0,
1107         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK                       = 0xFFFFFF,
1108
1109         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT           = 0,
1110         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK            = 0xFFFF,
1111         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT      = 16,
1112         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK       = 0xFFFF <<
1113                         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1114 };
1115
1116 struct ocrdma_create_srq_rsp {
1117         struct ocrdma_mqe_hdr hdr;
1118         struct ocrdma_mbx_rsp rsp;
1119
1120         u32 id;
1121         u32 max_sge_rqe_allocated;
1122 };
1123
1124 enum {
1125         OCRDMA_MODIFY_SRQ_ID_SHIFT      = 0,
1126         OCRDMA_MODIFY_SRQ_ID_MASK       = 0xFFFFFF,
1127
1128         OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,
1129         OCRDMA_MODIFY_SRQ_MAX_RQE_MASK  = 0xFFFF,
1130         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT   = 16,
1131         OCRDMA_MODIFY_SRQ__LIMIT_MASK   = 0xFFFF <<
1132                                         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1133 };
1134
1135 struct ocrdma_modify_srq {
1136         struct ocrdma_mqe_hdr hdr;
1137         struct ocrdma_mbx_rsp rep;
1138
1139         u32 id;
1140         u32 limit_max_rqe;
1141 };
1142
1143 enum {
1144         OCRDMA_QUERY_SRQ_ID_SHIFT       = 0,
1145         OCRDMA_QUERY_SRQ_ID_MASK        = 0xFFFFFF
1146 };
1147
1148 struct ocrdma_query_srq {
1149         struct ocrdma_mqe_hdr hdr;
1150         struct ocrdma_mbx_rsp req;
1151
1152         u32 id;
1153 };
1154
1155 enum {
1156         OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT        = 0,
1157         OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK         = 0xFFFF,
1158         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT      = 16,
1159         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK       = 0xFFFF <<
1160                                         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1161
1162         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,
1163         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK  = 0xFFFF,
1164         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT    = 16,
1165         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK     = 0xFFFF <<
1166                                         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1167 };
1168
1169 struct ocrdma_query_srq_rsp {
1170         struct ocrdma_mqe_hdr hdr;
1171         struct ocrdma_mbx_rsp req;
1172
1173         u32 max_rqe_pdid;
1174         u32 srq_lmt_max_sge;
1175 };
1176
1177 enum {
1178         OCRDMA_DESTROY_SRQ_ID_SHIFT     = 0,
1179         OCRDMA_DESTROY_SRQ_ID_MASK      = 0xFFFFFF
1180 };
1181
1182 struct ocrdma_destroy_srq {
1183         struct ocrdma_mqe_hdr hdr;
1184         struct ocrdma_mbx_rsp req;
1185
1186         u32 id;
1187 };
1188
1189 enum {
1190         OCRDMA_ALLOC_PD_ENABLE_DPP      = BIT(16),
1191         OCRDMA_PD_MAX_DPP_ENABLED_QP    = 8,
1192         OCRDMA_DPP_PAGE_SIZE            = 4096
1193 };
1194
1195 struct ocrdma_alloc_pd {
1196         struct ocrdma_mqe_hdr hdr;
1197         struct ocrdma_mbx_hdr req;
1198         u32 enable_dpp_rsvd;
1199 };
1200
1201 enum {
1202         OCRDMA_ALLOC_PD_RSP_DPP                 = Bit(16),
1203         OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT      = 20,
1204         OCRDMA_ALLOC_PD_RSP_PDID_MASK           = 0xFFFF,
1205 };
1206
1207 struct ocrdma_alloc_pd_rsp {
1208         struct ocrdma_mqe_hdr hdr;
1209         struct ocrdma_mbx_rsp rsp;
1210         u32 dpp_page_pdid;
1211 };
1212
1213 struct ocrdma_dealloc_pd {
1214         struct ocrdma_mqe_hdr hdr;
1215         struct ocrdma_mbx_hdr req;
1216         u32 id;
1217 };
1218
1219 struct ocrdma_dealloc_pd_rsp {
1220         struct ocrdma_mqe_hdr hdr;
1221         struct ocrdma_mbx_rsp rsp;
1222 };
1223
1224 enum {
1225         OCRDMA_ADDR_CHECK_ENABLE        = 1,
1226         OCRDMA_ADDR_CHECK_DISABLE       = 0
1227 };
1228
1229 enum {
1230         OCRDMA_ALLOC_LKEY_PD_ID_SHIFT           = 0,
1231         OCRDMA_ALLOC_LKEY_PD_ID_MASK            = 0xFFFF,
1232
1233         OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT      = 0,
1234         OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK       = Bit(0),
1235         OCRDMA_ALLOC_LKEY_FMR_SHIFT             = 1,
1236         OCRDMA_ALLOC_LKEY_FMR_MASK              = Bit(1),
1237         OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT      = 2,
1238         OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK       = Bit(2),
1239         OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT       = 3,
1240         OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK        = Bit(3),
1241         OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT       = 4,
1242         OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK        = Bit(4),
1243         OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT        = 5,
1244         OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK         = Bit(5),
1245         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK    = Bit(6),
1246         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT   = 6,
1247         OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT        = 16,
1248         OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK         = 0xFFFF <<
1249                                                 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1250 };
1251
1252 struct ocrdma_alloc_lkey {
1253         struct ocrdma_mqe_hdr hdr;
1254         struct ocrdma_mbx_hdr req;
1255
1256         u32 pdid;
1257         u32 pbl_sz_flags;
1258 };
1259
1260 struct ocrdma_alloc_lkey_rsp {
1261         struct ocrdma_mqe_hdr hdr;
1262         struct ocrdma_mbx_rsp rsp;
1263
1264         u32 lrkey;
1265         u32 num_pbl_rsvd;
1266 };
1267
1268 struct ocrdma_dealloc_lkey {
1269         struct ocrdma_mqe_hdr hdr;
1270         struct ocrdma_mbx_hdr req;
1271
1272         u32 lkey;
1273         u32 rsvd_frmr;
1274 };
1275
1276 struct ocrdma_dealloc_lkey_rsp {
1277         struct ocrdma_mqe_hdr hdr;
1278         struct ocrdma_mbx_rsp rsp;
1279 };
1280
1281 #define MAX_OCRDMA_NSMR_PBL    (u32)22
1282 #define MAX_OCRDMA_PBL_SIZE     65536
1283 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1284
1285 enum {
1286         OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT       = 0,
1287         OCRDMA_REG_NSMR_LRKEY_INDEX_MASK        = 0xFFFFFF,
1288         OCRDMA_REG_NSMR_LRKEY_SHIFT             = 24,
1289         OCRDMA_REG_NSMR_LRKEY_MASK              = 0xFF <<
1290                                         OCRDMA_REG_NSMR_LRKEY_SHIFT,
1291
1292         OCRDMA_REG_NSMR_PD_ID_SHIFT             = 0,
1293         OCRDMA_REG_NSMR_PD_ID_MASK              = 0xFFFF,
1294         OCRDMA_REG_NSMR_NUM_PBL_SHIFT           = 16,
1295         OCRDMA_REG_NSMR_NUM_PBL_MASK            = 0xFFFF <<
1296                                         OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1297
1298         OCRDMA_REG_NSMR_PBE_SIZE_SHIFT          = 0,
1299         OCRDMA_REG_NSMR_PBE_SIZE_MASK           = 0xFFFF,
1300         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT        = 16,
1301         OCRDMA_REG_NSMR_HPAGE_SIZE_MASK         = 0xFF <<
1302                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1303         OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT       = 24,
1304         OCRDMA_REG_NSMR_BIND_MEMWIN_MASK        = Bit(24),
1305         OCRDMA_REG_NSMR_ZB_SHIFT                = 25,
1306         OCRDMA_REG_NSMR_ZB_SHIFT_MASK           = Bit(25),
1307         OCRDMA_REG_NSMR_REMOTE_INV_SHIFT        = 26,
1308         OCRDMA_REG_NSMR_REMOTE_INV_MASK         = Bit(26),
1309         OCRDMA_REG_NSMR_REMOTE_WR_SHIFT         = 27,
1310         OCRDMA_REG_NSMR_REMOTE_WR_MASK          = Bit(27),
1311         OCRDMA_REG_NSMR_REMOTE_RD_SHIFT         = 28,
1312         OCRDMA_REG_NSMR_REMOTE_RD_MASK          = Bit(28),
1313         OCRDMA_REG_NSMR_LOCAL_WR_SHIFT          = 29,
1314         OCRDMA_REG_NSMR_LOCAL_WR_MASK           = Bit(29),
1315         OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT     = 30,
1316         OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK      = Bit(30),
1317         OCRDMA_REG_NSMR_LAST_SHIFT              = 31,
1318         OCRDMA_REG_NSMR_LAST_MASK               = Bit(31)
1319 };
1320
1321 struct ocrdma_reg_nsmr {
1322         struct ocrdma_mqe_hdr hdr;
1323         struct ocrdma_mbx_hdr cmd;
1324
1325         u32 fr_mr;
1326         u32 num_pbl_pdid;
1327         u32 flags_hpage_pbe_sz;
1328         u32 totlen_low;
1329         u32 totlen_high;
1330         u32 fbo_low;
1331         u32 fbo_high;
1332         u32 va_loaddr;
1333         u32 va_hiaddr;
1334         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1335 };
1336
1337 enum {
1338         OCRDMA_REG_NSMR_CONT_PBL_SHIFT          = 0,
1339         OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK     = 0xFFFF,
1340         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT      = 16,
1341         OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK       = 0xFFFF <<
1342                                         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1343
1344         OCRDMA_REG_NSMR_CONT_LAST_SHIFT         = 31,
1345         OCRDMA_REG_NSMR_CONT_LAST_MASK          = Bit(31)
1346 };
1347
1348 struct ocrdma_reg_nsmr_cont {
1349         struct ocrdma_mqe_hdr hdr;
1350         struct ocrdma_mbx_hdr cmd;
1351
1352         u32 lrkey;
1353         u32 num_pbl_offset;
1354         u32 last;
1355
1356         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1357 };
1358
1359 struct ocrdma_pbe {
1360         u32 pa_hi;
1361         u32 pa_lo;
1362 };
1363
1364 enum {
1365         OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT       = 16,
1366         OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK        = 0xFFFF0000
1367 };
1368 struct ocrdma_reg_nsmr_rsp {
1369         struct ocrdma_mqe_hdr hdr;
1370         struct ocrdma_mbx_rsp rsp;
1371
1372         u32 lrkey;
1373         u32 num_pbl;
1374 };
1375
1376 enum {
1377         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT      = 0,
1378         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK       = 0xFFFFFF,
1379         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT            = 24,
1380         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK             = 0xFF <<
1381                                         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1382
1383         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT          = 16,
1384         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK           = 0xFFFF <<
1385                                         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1386 };
1387
1388 struct ocrdma_reg_nsmr_cont_rsp {
1389         struct ocrdma_mqe_hdr hdr;
1390         struct ocrdma_mbx_rsp rsp;
1391
1392         u32 lrkey_key_index;
1393         u32 num_pbl;
1394 };
1395
1396 enum {
1397         OCRDMA_ALLOC_MW_PD_ID_SHIFT     = 0,
1398         OCRDMA_ALLOC_MW_PD_ID_MASK      = 0xFFFF
1399 };
1400
1401 struct ocrdma_alloc_mw {
1402         struct ocrdma_mqe_hdr hdr;
1403         struct ocrdma_mbx_hdr req;
1404
1405         u32 pdid;
1406 };
1407
1408 enum {
1409         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT   = 0,
1410         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK    = 0xFFFFFF
1411 };
1412
1413 struct ocrdma_alloc_mw_rsp {
1414         struct ocrdma_mqe_hdr hdr;
1415         struct ocrdma_mbx_rsp rsp;
1416
1417         u32 lrkey_index;
1418 };
1419
1420 struct ocrdma_attach_mcast {
1421         struct ocrdma_mqe_hdr hdr;
1422         struct ocrdma_mbx_hdr req;
1423         u32 qp_id;
1424         u8 mgid[16];
1425         u32 mac_b0_to_b3;
1426         u32 vlan_mac_b4_to_b5;
1427 };
1428
1429 struct ocrdma_attach_mcast_rsp {
1430         struct ocrdma_mqe_hdr hdr;
1431         struct ocrdma_mbx_rsp rsp;
1432 };
1433
1434 struct ocrdma_detach_mcast {
1435         struct ocrdma_mqe_hdr hdr;
1436         struct ocrdma_mbx_hdr req;
1437         u32 qp_id;
1438         u8 mgid[16];
1439         u32 mac_b0_to_b3;
1440         u32 vlan_mac_b4_to_b5;
1441 };
1442
1443 struct ocrdma_detach_mcast_rsp {
1444         struct ocrdma_mqe_hdr hdr;
1445         struct ocrdma_mbx_rsp rsp;
1446 };
1447
1448 enum {
1449         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT        = 19,
1450         OCRDMA_CREATE_AH_NUM_PAGES_MASK         = 0xF <<
1451                                         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1452
1453         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT        = 16,
1454         OCRDMA_CREATE_AH_PAGE_SIZE_MASK         = 0x7 <<
1455                                         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1456
1457         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT       = 23,
1458         OCRDMA_CREATE_AH_ENTRY_SIZE_MASK        = 0x1FF <<
1459                                         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1460 };
1461
1462 #define OCRDMA_AH_TBL_PAGES 8
1463
1464 struct ocrdma_create_ah_tbl {
1465         struct ocrdma_mqe_hdr hdr;
1466         struct ocrdma_mbx_hdr req;
1467
1468         u32 ah_conf;
1469         struct ocrdma_pa tbl_addr[8];
1470 };
1471
1472 struct ocrdma_create_ah_tbl_rsp {
1473         struct ocrdma_mqe_hdr hdr;
1474         struct ocrdma_mbx_rsp rsp;
1475         u32 ahid;
1476 };
1477
1478 struct ocrdma_delete_ah_tbl {
1479         struct ocrdma_mqe_hdr hdr;
1480         struct ocrdma_mbx_hdr req;
1481         u32 ahid;
1482 };
1483
1484 struct ocrdma_delete_ah_tbl_rsp {
1485         struct ocrdma_mqe_hdr hdr;
1486         struct ocrdma_mbx_rsp rsp;
1487 };
1488
1489 enum {
1490         OCRDMA_EQE_VALID_SHIFT          = 0,
1491         OCRDMA_EQE_VALID_MASK           = Bit(0),
1492         OCRDMA_EQE_FOR_CQE_MASK         = 0xFFFE,
1493         OCRDMA_EQE_RESOURCE_ID_SHIFT    = 16,
1494         OCRDMA_EQE_RESOURCE_ID_MASK     = 0xFFFF <<
1495                                 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1496 };
1497
1498 struct ocrdma_eqe {
1499         u32 id_valid;
1500 };
1501
1502 enum OCRDMA_CQE_STATUS {
1503         OCRDMA_CQE_SUCCESS = 0,
1504         OCRDMA_CQE_LOC_LEN_ERR,
1505         OCRDMA_CQE_LOC_QP_OP_ERR,
1506         OCRDMA_CQE_LOC_EEC_OP_ERR,
1507         OCRDMA_CQE_LOC_PROT_ERR,
1508         OCRDMA_CQE_WR_FLUSH_ERR,
1509         OCRDMA_CQE_MW_BIND_ERR,
1510         OCRDMA_CQE_BAD_RESP_ERR,
1511         OCRDMA_CQE_LOC_ACCESS_ERR,
1512         OCRDMA_CQE_REM_INV_REQ_ERR,
1513         OCRDMA_CQE_REM_ACCESS_ERR,
1514         OCRDMA_CQE_REM_OP_ERR,
1515         OCRDMA_CQE_RETRY_EXC_ERR,
1516         OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1517         OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1518         OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1519         OCRDMA_CQE_REM_ABORT_ERR,
1520         OCRDMA_CQE_INV_EECN_ERR,
1521         OCRDMA_CQE_INV_EEC_STATE_ERR,
1522         OCRDMA_CQE_FATAL_ERR,
1523         OCRDMA_CQE_RESP_TIMEOUT_ERR,
1524         OCRDMA_CQE_GENERAL_ERR
1525 };
1526
1527 enum {
1528         /* w0 */
1529         OCRDMA_CQE_WQEIDX_SHIFT         = 0,
1530         OCRDMA_CQE_WQEIDX_MASK          = 0xFFFF,
1531
1532         /* w1 */
1533         OCRDMA_CQE_UD_XFER_LEN_SHIFT    = 16,
1534         OCRDMA_CQE_PKEY_SHIFT           = 0,
1535         OCRDMA_CQE_PKEY_MASK            = 0xFFFF,
1536
1537         /* w2 */
1538         OCRDMA_CQE_QPN_SHIFT            = 0,
1539         OCRDMA_CQE_QPN_MASK             = 0x0000FFFF,
1540
1541         OCRDMA_CQE_BUFTAG_SHIFT         = 16,
1542         OCRDMA_CQE_BUFTAG_MASK          = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,
1543
1544         /* w3 */
1545         OCRDMA_CQE_UD_STATUS_SHIFT      = 24,
1546         OCRDMA_CQE_UD_STATUS_MASK       = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
1547         OCRDMA_CQE_STATUS_SHIFT         = 16,
1548         OCRDMA_CQE_STATUS_MASK          = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
1549         OCRDMA_CQE_VALID                = Bit(31),
1550         OCRDMA_CQE_INVALIDATE           = Bit(30),
1551         OCRDMA_CQE_QTYPE                = Bit(29),
1552         OCRDMA_CQE_IMM                  = Bit(28),
1553         OCRDMA_CQE_WRITE_IMM            = Bit(27),
1554         OCRDMA_CQE_QTYPE_SQ             = 0,
1555         OCRDMA_CQE_QTYPE_RQ             = 1,
1556         OCRDMA_CQE_SRCQP_MASK           = 0xFFFFFF
1557 };
1558
1559 struct ocrdma_cqe {
1560         union {
1561                 /* w0 to w2 */
1562                 struct {
1563                         u32 wqeidx;
1564                         u32 bytes_xfered;
1565                         u32 qpn;
1566                 } wq;
1567                 struct {
1568                         u32 lkey_immdt;
1569                         u32 rxlen;
1570                         u32 buftag_qpn;
1571                 } rq;
1572                 struct {
1573                         u32 lkey_immdt;
1574                         u32 rxlen_pkey;
1575                         u32 buftag_qpn;
1576                 } ud;
1577                 struct {
1578                         u32 word_0;
1579                         u32 word_1;
1580                         u32 qpn;
1581                 } cmn;
1582         };
1583         u32 flags_status_srcqpn;        /* w3 */
1584 };
1585
1586 struct ocrdma_sge {
1587         u32 addr_hi;
1588         u32 addr_lo;
1589         u32 lrkey;
1590         u32 len;
1591 };
1592
1593 enum {
1594         OCRDMA_FLAG_SIG         = 0x1,
1595         OCRDMA_FLAG_INV         = 0x2,
1596         OCRDMA_FLAG_FENCE_L     = 0x4,
1597         OCRDMA_FLAG_FENCE_R     = 0x8,
1598         OCRDMA_FLAG_SOLICIT     = 0x10,
1599         OCRDMA_FLAG_IMM         = 0x20,
1600
1601         /* Stag flags */
1602         OCRDMA_LKEY_FLAG_LOCAL_WR       = 0x1,
1603         OCRDMA_LKEY_FLAG_REMOTE_RD      = 0x2,
1604         OCRDMA_LKEY_FLAG_REMOTE_WR      = 0x4,
1605         OCRDMA_LKEY_FLAG_VATO           = 0x8,
1606 };
1607
1608 enum OCRDMA_WQE_OPCODE {
1609         OCRDMA_WRITE            = 0x06,
1610         OCRDMA_READ             = 0x0C,
1611         OCRDMA_RESV0            = 0x02,
1612         OCRDMA_SEND             = 0x00,
1613         OCRDMA_CMP_SWP          = 0x14,
1614         OCRDMA_BIND_MW          = 0x10,
1615         OCRDMA_FR_MR            = 0x11,
1616         OCRDMA_RESV1            = 0x0A,
1617         OCRDMA_LKEY_INV         = 0x15,
1618         OCRDMA_FETCH_ADD        = 0x13,
1619         OCRDMA_POST_RQ          = 0x12
1620 };
1621
1622 enum {
1623         OCRDMA_TYPE_INLINE      = 0x0,
1624         OCRDMA_TYPE_LKEY        = 0x1,
1625 };
1626
1627 enum {
1628         OCRDMA_WQE_OPCODE_SHIFT         = 0,
1629         OCRDMA_WQE_OPCODE_MASK          = 0x0000001F,
1630         OCRDMA_WQE_FLAGS_SHIFT          = 5,
1631         OCRDMA_WQE_TYPE_SHIFT           = 16,
1632         OCRDMA_WQE_TYPE_MASK            = 0x00030000,
1633         OCRDMA_WQE_SIZE_SHIFT           = 18,
1634         OCRDMA_WQE_SIZE_MASK            = 0xFF,
1635         OCRDMA_WQE_NXT_WQE_SIZE_SHIFT   = 25,
1636
1637         OCRDMA_WQE_LKEY_FLAGS_SHIFT     = 0,
1638         OCRDMA_WQE_LKEY_FLAGS_MASK      = 0xF
1639 };
1640
1641 /* header WQE for all the SQ and RQ operations */
1642 struct ocrdma_hdr_wqe {
1643         u32 cw;
1644         union {
1645                 u32 rsvd_tag;
1646                 u32 rsvd_lkey_flags;
1647         };
1648         union {
1649                 u32 immdt;
1650                 u32 lkey;
1651         };
1652         u32 total_len;
1653 };
1654
1655 struct ocrdma_ewqe_ud_hdr {
1656         u32 rsvd_dest_qpn;
1657         u32 qkey;
1658         u32 rsvd_ahid;
1659         u32 rsvd;
1660 };
1661
1662 /* extended wqe followed by hdr_wqe for Fast Memory register */
1663 struct ocrdma_ewqe_fr {
1664         u32 va_hi;
1665         u32 va_lo;
1666         u32 fbo_hi;
1667         u32 fbo_lo;
1668         u32 size_sge;
1669         u32 num_sges;
1670         u32 rsvd;
1671         u32 rsvd2;
1672 };
1673
1674 struct ocrdma_eth_basic {
1675         u8 dmac[6];
1676         u8 smac[6];
1677         __be16 eth_type;
1678 } __packed;
1679
1680 struct ocrdma_eth_vlan {
1681         u8 dmac[6];
1682         u8 smac[6];
1683         __be16 eth_type;
1684         __be16 vlan_tag;
1685 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1686         __be16 roce_eth_type;
1687 } __packed;
1688
1689 struct ocrdma_grh {
1690         __be32  tclass_flow;
1691         __be32  pdid_hoplimit;
1692         u8      sgid[16];
1693         u8      dgid[16];
1694         u16     rsvd;
1695 } __packed;
1696
1697 #define OCRDMA_AV_VALID         Bit(7)
1698 #define OCRDMA_AV_VLAN_VALID    Bit(1)
1699
1700 struct ocrdma_av {
1701         struct ocrdma_eth_vlan eth_hdr;
1702         struct ocrdma_grh grh;
1703         u32 valid;
1704 } __packed;
1705
1706 #endif                          /* __OCRDMA_SLI_H__ */