1 /*******************************************************************
2 * This file is part of the Emulex RoCE Device Driver for *
3 * RoCE (RDMA over Converged Ethernet) adapters. *
4 * Copyright (C) 2008-2012 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
20 * Contact Information:
21 * linux-drivers@emulex.com
25 * Costa Mesa, CA 92626
26 *******************************************************************/
28 #ifndef __OCRDMA_SLI_H__
29 #define __OCRDMA_SLI_H__
31 #define Bit(_b) (1 << (_b))
34 OCRDMA_ASIC_GEN_SKH_R = 0x04,
35 OCRDMA_ASIC_GEN_LANCER = 0x0B
39 OCRDMA_ASIC_REV_A0 = 0x00,
40 OCRDMA_ASIC_REV_B0 = 0x10,
41 OCRDMA_ASIC_REV_C0 = 0x20
44 #define OCRDMA_SUBSYS_ROCE 10
46 OCRDMA_CMD_QUERY_CONFIG = 1,
48 OCRDMA_CMD_DEALLOC_PD,
50 OCRDMA_CMD_CREATE_AH_TBL,
51 OCRDMA_CMD_DELETE_AH_TBL,
59 OCRDMA_CMD_ALLOC_LKEY,
60 OCRDMA_CMD_DEALLOC_LKEY,
61 OCRDMA_CMD_REGISTER_NSMR,
62 OCRDMA_CMD_REREGISTER_NSMR,
63 OCRDMA_CMD_REGISTER_NSMR_CONT,
64 OCRDMA_CMD_QUERY_NSMR,
68 OCRDMA_CMD_CREATE_SRQ,
70 OCRDMA_CMD_MODIFY_SRQ,
71 OCRDMA_CMD_DELETE_SRQ,
73 OCRDMA_CMD_ATTACH_MCAST,
74 OCRDMA_CMD_DETACH_MCAST,
75 OCRDMA_CMD_GET_RDMA_STATS,
80 #define OCRDMA_SUBSYS_COMMON 1
82 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5,
83 OCRDMA_CMD_CREATE_CQ = 12,
84 OCRDMA_CMD_CREATE_EQ = 13,
85 OCRDMA_CMD_CREATE_MQ = 21,
86 OCRDMA_CMD_GET_CTRL_ATTRIBUTES = 32,
87 OCRDMA_CMD_GET_FW_VER = 35,
88 OCRDMA_CMD_DELETE_MQ = 53,
89 OCRDMA_CMD_DELETE_CQ = 54,
90 OCRDMA_CMD_DELETE_EQ = 55,
91 OCRDMA_CMD_GET_FW_CONFIG = 58,
92 OCRDMA_CMD_CREATE_MQ_EXT = 90,
93 OCRDMA_CMD_PHY_DETAILS = 102
102 #define OCRDMA_MAX_SGID (8)
104 #define OCRDMA_MAX_QP 2048
105 #define OCRDMA_MAX_CQ 2048
106 #define OCRDMA_MAX_STAG 8192
109 OCRDMA_DB_RQ_OFFSET = 0xE0,
110 OCRDMA_DB_GEN2_RQ_OFFSET = 0x100,
111 OCRDMA_DB_SQ_OFFSET = 0x60,
112 OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0,
113 OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET,
114 OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ_OFFSET,
115 OCRDMA_DB_CQ_OFFSET = 0x120,
116 OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET,
117 OCRDMA_DB_MQ_OFFSET = 0x140,
119 OCRDMA_DB_SQ_SHIFT = 16,
120 OCRDMA_DB_RQ_SHIFT = 24
123 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
124 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */
125 /* qid #2 msbits at 12-11 */
126 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1
127 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
129 #define OCRDMA_DB_CQ_REARM_SHIFT (29) /* bit 29 */
131 #define OCRDMA_DB_CQ_SOLICIT_SHIFT (31) /* bit 31 */
133 #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */
134 #define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */
135 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 at 11-15 */
137 /* Clear the interrupt for this eq */
138 #define OCRDMA_EQ_CLR_SHIFT (9) /* bit 9 */
140 #define OCRDMA_EQ_TYPE_SHIFT (10) /* bit 10 */
141 /* Number of event entries processed */
142 #define OCRDMA_NUM_EQE_SHIFT (16) /* bits 16 - 28 */
144 #define OCRDMA_REARM_SHIFT (29) /* bit 29 */
146 #define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */
147 /* Number of entries posted */
148 #define OCRDMA_MQ_NUM_MQE_SHIFT (16) /* bits 16 - 29 */
150 #define OCRDMA_MIN_HPAGE_SIZE (4096)
152 #define OCRDMA_MIN_Q_PAGE_SIZE (4096)
153 #define OCRDMA_MAX_Q_PAGES (8)
155 #define OCRDMA_SLI_ASIC_ID_OFFSET 0x9C
156 #define OCRDMA_SLI_ASIC_REV_MASK 0x000000FF
157 #define OCRDMA_SLI_ASIC_GEN_NUM_MASK 0x0000FF00
158 #define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT 0x08
169 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (8)
170 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
172 #define MAX_OCRDMA_QP_PAGES (8)
173 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
175 #define OCRDMA_CREATE_CQ_MAX_PAGES (4)
176 #define OCRDMA_DPP_CQE_SIZE (4)
178 #define OCRDMA_GEN2_MAX_CQE 1024
179 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
180 #define OCRDMA_GEN2_WQE_SIZE 256
181 #define OCRDMA_MAX_CQE 4095
182 #define OCRDMA_CQ_PAGE_SIZE 16384
183 #define OCRDMA_WQE_SIZE 128
184 #define OCRDMA_WQE_STRIDE 8
185 #define OCRDMA_WQE_ALIGN_BYTES 16
187 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
190 OCRDMA_MCH_OPCODE_SHIFT = 0,
191 OCRDMA_MCH_OPCODE_MASK = 0xFF,
192 OCRDMA_MCH_SUBSYS_SHIFT = 8,
193 OCRDMA_MCH_SUBSYS_MASK = 0xFF00
196 /* mailbox cmd header */
197 struct ocrdma_mbx_hdr {
199 u32 timeout; /* in seconds */
205 OCRDMA_MBX_RSP_OPCODE_SHIFT = 0,
206 OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF,
207 OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8,
208 OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,
210 OCRDMA_MBX_RSP_STATUS_SHIFT = 0,
211 OCRDMA_MBX_RSP_STATUS_MASK = 0xFF,
212 OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8,
213 OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
216 /* mailbox cmd response */
217 struct ocrdma_mbx_rsp {
225 OCRDMA_MQE_EMBEDDED = 1,
226 OCRDMA_MQE_NONEMBEDDED = 0
229 struct ocrdma_mqe_sge {
236 OCRDMA_MQE_HDR_EMB_SHIFT = 0,
237 OCRDMA_MQE_HDR_EMB_MASK = Bit(0),
238 OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3,
239 OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
240 OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24,
241 OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
244 struct ocrdma_mqe_hdr {
245 u32 spcl_sge_cnt_emb;
252 struct ocrdma_mqe_emb_cmd {
253 struct ocrdma_mbx_hdr mch;
258 struct ocrdma_mqe_hdr hdr;
260 struct ocrdma_mqe_emb_cmd emb_req;
262 struct ocrdma_mqe_sge sge[19];
265 struct ocrdma_mbx_rsp rsp;
269 #define OCRDMA_EQ_LEN 4096
270 #define OCRDMA_MQ_CQ_LEN 256
271 #define OCRDMA_MQ_LEN 128
273 #define PAGE_SHIFT_4K 12
274 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
276 /* Returns number of pages spanned by the data starting at the given addr */
277 #define PAGES_4K_SPANNED(_address, size) \
278 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
279 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
281 struct ocrdma_delete_q_req {
282 struct ocrdma_mbx_hdr req;
291 #define MAX_OCRDMA_EQ_PAGES (8)
292 struct ocrdma_create_eq_req {
293 struct ocrdma_mbx_hdr req;
299 struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];
303 OCRDMA_CREATE_EQ_VALID = Bit(29),
304 OCRDMA_CREATE_EQ_CNT_SHIFT = 26,
305 OCRDMA_CREATE_CQ_DELAY_SHIFT = 13,
308 struct ocrdma_create_eq_rsp {
309 struct ocrdma_mbx_rsp rsp;
313 #define OCRDMA_EQ_MINOR_OTHER (0x1)
316 OCRDMA_MCQE_STATUS_SHIFT = 0,
317 OCRDMA_MCQE_STATUS_MASK = 0xFFFF,
318 OCRDMA_MCQE_ESTATUS_SHIFT = 16,
319 OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
320 OCRDMA_MCQE_CONS_SHIFT = 27,
321 OCRDMA_MCQE_CONS_MASK = Bit(27),
322 OCRDMA_MCQE_CMPL_SHIFT = 28,
323 OCRDMA_MCQE_CMPL_MASK = Bit(28),
324 OCRDMA_MCQE_AE_SHIFT = 30,
325 OCRDMA_MCQE_AE_MASK = Bit(30),
326 OCRDMA_MCQE_VALID_SHIFT = 31,
327 OCRDMA_MCQE_VALID_MASK = Bit(31)
334 u32 valid_ae_cmpl_cons;
338 OCRDMA_AE_MCQE_QPVALID = Bit(31),
339 OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF,
341 OCRDMA_AE_MCQE_CQVALID = Bit(31),
342 OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF,
343 OCRDMA_AE_MCQE_VALID = Bit(31),
344 OCRDMA_AE_MCQE_AE = Bit(30),
345 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
346 OCRDMA_AE_MCQE_EVENT_TYPE_MASK =
347 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
348 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,
349 OCRDMA_AE_MCQE_EVENT_CODE_MASK =
350 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
352 struct ocrdma_ae_mcqe {
360 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0,
361 OCRDMA_AE_PVID_MCQE_ENABLED_MASK = 0xFF,
362 OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16,
363 OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT
366 struct ocrdma_ae_pvid_mcqe {
374 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16,
375 OCRDMA_AE_MPA_MCQE_REQ_ID_MASK = 0xFFFF <<
376 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
378 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8,
379 OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK = 0xFF <<
380 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
381 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16,
382 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF <<
383 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
384 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30,
385 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = Bit(30),
386 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31,
387 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = Bit(31)
390 struct ocrdma_ae_mpa_mcqe {
398 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0,
399 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF,
400 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16,
401 OCRDMA_AE_QP_MCQE_QP_ID_MASK = 0xFFFF <<
402 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
404 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8,
405 OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK = 0xFF <<
406 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
407 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16,
408 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF <<
409 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
410 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30,
411 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = Bit(30),
412 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31,
413 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = Bit(31)
416 struct ocrdma_ae_qp_mcqe {
423 #define OCRDMA_ASYNC_RDMA_EVE_CODE 0x14
424 #define OCRDMA_ASYNC_GRP5_EVE_CODE 0x5
426 enum ocrdma_async_grp5_events {
427 OCRDMA_ASYNC_EVENT_QOS_VALUE = 0x01,
428 OCRDMA_ASYNC_EVENT_COS_VALUE = 0x02,
429 OCRDMA_ASYNC_EVENT_PVID_STATE = 0x03
432 enum OCRDMA_ASYNC_EVENT_TYPE {
433 OCRDMA_CQ_ERROR = 0x00,
434 OCRDMA_CQ_OVERRUN_ERROR = 0x01,
435 OCRDMA_CQ_QPCAT_ERROR = 0x02,
436 OCRDMA_QP_ACCESS_ERROR = 0x03,
437 OCRDMA_QP_COMM_EST_EVENT = 0x04,
438 OCRDMA_SQ_DRAINED_EVENT = 0x05,
439 OCRDMA_DEVICE_FATAL_EVENT = 0x08,
440 OCRDMA_SRQCAT_ERROR = 0x0E,
441 OCRDMA_SRQ_LIMIT_EVENT = 0x0F,
442 OCRDMA_QP_LAST_WQE_EVENT = 0x10
445 /* mailbox command request and responses */
447 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2,
448 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = Bit(2),
449 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3,
450 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = Bit(3),
451 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8,
452 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF <<
453 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
455 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16,
456 OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK = 0xFFFF <<
457 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
458 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8,
459 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK = 0xFF <<
460 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
462 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0,
463 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF,
464 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT = 16,
465 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK = 0xFFFF <<
466 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT,
468 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0,
469 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF,
470 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16,
471 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK = 0xFFFF <<
472 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
474 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24,
475 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK = 0xFF <<
476 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
477 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16,
478 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK = 0xFF <<
479 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
480 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0,
481 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK = 0xFFFF <<
482 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
484 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16,
485 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK = 0xFFFF <<
486 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
487 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0,
488 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK = 0xFFFF <<
489 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
491 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16,
492 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK = 0xFFFF <<
493 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
494 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0,
495 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK = 0xFFFF <<
496 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
498 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0,
499 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK = 0xFFFF <<
500 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
502 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16,
503 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK = 0xFFFF <<
504 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
505 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0,
506 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK = 0xFFFF <<
507 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,
509 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16,
510 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK = 0xFFFF <<
511 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
512 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0,
513 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK = 0xFFFF <<
514 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
516 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16,
517 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK = 0xFFFF <<
518 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
519 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0,
520 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK = 0xFFFF <<
521 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
524 struct ocrdma_mbx_query_config {
525 struct ocrdma_mqe_hdr hdr;
526 struct ocrdma_mbx_rsp rsp;
527 u32 qp_srq_cq_ird_ord;
528 u32 max_pd_ca_ack_delay;
529 u32 max_write_send_sge;
530 u32 max_ird_ord_per_qp;
531 u32 max_shared_ird_ord;
538 u32 max_pages_per_frmr;
540 u32 max_mcast_qp_attach;
541 u32 max_total_mcast_qp_attach;
542 u32 wqe_rqe_stride_max_dpp_cqs;
543 u32 max_srq_rpir_qps;
544 u32 max_dpp_pds_credits;
545 u32 max_dpp_credits_pds_per_pd;
546 u32 max_wqes_rqes_per_q;
547 u32 max_cq_cqes_per_cq;
551 struct ocrdma_fw_ver_rsp {
552 struct ocrdma_mqe_hdr hdr;
553 struct ocrdma_mbx_rsp rsp;
558 struct ocrdma_fw_conf_rsp {
559 struct ocrdma_mqe_hdr hdr;
560 struct ocrdma_mbx_rsp rsp;
585 OCRDMA_FN_MODE_RDMA = 0x4
588 struct ocrdma_get_phy_info_rsp {
589 struct ocrdma_mqe_hdr hdr;
590 struct ocrdma_mbx_rsp rsp;
597 u16 auto_speeds_supported;
598 u16 fixed_speeds_supported;
603 OCRDMA_PHY_SPEED_ZERO = 0x0,
604 OCRDMA_PHY_SPEED_10MBPS = 0x1,
605 OCRDMA_PHY_SPEED_100MBPS = 0x2,
606 OCRDMA_PHY_SPEED_1GBPS = 0x4,
607 OCRDMA_PHY_SPEED_10GBPS = 0x8,
608 OCRDMA_PHY_SPEED_40GBPS = 0x20
612 struct ocrdma_get_link_speed_rsp {
613 struct ocrdma_mqe_hdr hdr;
614 struct ocrdma_mbx_rsp rsp;
622 u8 logical_lnk_status;
627 OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0,
628 OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1,
629 OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2,
630 OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3,
631 OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4,
632 OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5,
633 OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6,
634 OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7,
635 OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8
639 OCRDMA_CREATE_CQ_VER2 = 2,
640 OCRDMA_CREATE_CQ_VER3 = 3,
642 OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF,
643 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16,
644 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF,
646 OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12,
647 OCRDMA_CREATE_CQ_COALESCWM_MASK = Bit(13) | Bit(12),
648 OCRDMA_CREATE_CQ_FLAGS_NODELAY = Bit(14),
649 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = Bit(15),
651 OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF,
652 OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF
656 OCRDMA_CREATE_CQ_VER0 = 0,
657 OCRDMA_CREATE_CQ_DPP = 1,
658 OCRDMA_CREATE_CQ_TYPE_SHIFT = 24,
659 OCRDMA_CREATE_CQ_EQID_SHIFT = 22,
661 OCRDMA_CREATE_CQ_CNT_SHIFT = 27,
662 OCRDMA_CREATE_CQ_FLAGS_VALID = Bit(29),
663 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = Bit(31),
664 OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID |
665 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
666 OCRDMA_CREATE_CQ_FLAGS_NODELAY
669 struct ocrdma_create_cq_cmd {
670 struct ocrdma_mbx_hdr req;
677 struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];
680 struct ocrdma_create_cq {
681 struct ocrdma_mqe_hdr hdr;
682 struct ocrdma_create_cq_cmd cmd;
686 OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF
689 struct ocrdma_create_cq_cmd_rsp {
690 struct ocrdma_mbx_rsp rsp;
694 struct ocrdma_create_cq_rsp {
695 struct ocrdma_mqe_hdr hdr;
696 struct ocrdma_create_cq_cmd_rsp rsp;
700 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22,
701 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16,
702 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16,
703 OCRDMA_CREATE_MQ_VALID = Bit(31),
704 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = Bit(0)
707 struct ocrdma_create_mq_req {
708 struct ocrdma_mbx_hdr req;
710 u32 async_event_bitmap;
711 u32 async_cqid_ringsize;
713 u32 async_cqid_valid;
715 struct ocrdma_pa pa[8];
718 struct ocrdma_create_mq_rsp {
719 struct ocrdma_mbx_rsp rsp;
724 OCRDMA_DESTROY_CQ_QID_SHIFT = 0,
725 OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF,
726 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16,
727 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK = 0xFFFF <<
728 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
731 struct ocrdma_destroy_cq {
732 struct ocrdma_mqe_hdr hdr;
733 struct ocrdma_mbx_hdr req;
735 u32 bypass_flush_qid;
738 struct ocrdma_destroy_cq_rsp {
739 struct ocrdma_mqe_hdr hdr;
740 struct ocrdma_mbx_rsp rsp;
750 OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0,
751 OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF,
752 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
753 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
754 OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29,
755 OCRDMA_CREATE_QP_REQ_QPT_MASK = Bit(31) | Bit(30) | Bit(29),
757 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0,
758 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF,
759 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16,
760 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK = 0xFFFF <<
761 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
763 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0,
764 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF,
765 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16,
766 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK = 0xFFFF <<
767 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
769 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0,
770 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = Bit(0),
771 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1,
772 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = Bit(1),
773 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2,
774 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = Bit(2),
775 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3,
776 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = Bit(3),
777 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4,
778 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = Bit(4),
779 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5,
780 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = Bit(5),
781 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6,
782 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = Bit(6),
783 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7,
784 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = Bit(7),
785 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8,
786 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = Bit(8),
787 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16,
788 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF <<
789 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
791 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0,
792 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF,
793 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16,
794 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK = 0xFFFF <<
795 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
797 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0,
798 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF,
799 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16,
800 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK = 0xFFFF <<
801 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
803 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0,
804 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF,
805 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16,
806 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK = 0xFFFF <<
807 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
809 OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0,
810 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF,
811 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16,
812 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK = 0xFFFF <<
813 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
815 OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0,
816 OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF,
817 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16,
818 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK = 0xFFFF <<
819 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
823 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16,
824 OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1
827 #define MAX_OCRDMA_IRD_PAGES 4
829 enum ocrdma_qp_flags {
830 OCRDMA_QP_MW_BIND = 1,
831 OCRDMA_QP_LKEY0 = (1 << 1),
832 OCRDMA_QP_FAST_REG = (1 << 2),
833 OCRDMA_QP_INB_RD = (1 << 6),
834 OCRDMA_QP_INB_WR = (1 << 7),
837 enum ocrdma_qp_state {
843 OCRDMA_QPS_SQ_DRAINING = 5,
848 struct ocrdma_create_qp_req {
849 struct ocrdma_mqe_hdr hdr;
850 struct ocrdma_mbx_hdr req;
854 u32 max_sge_send_write;
855 u32 max_sge_recv_flags;
860 struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];
861 struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];
862 u32 dpp_credits_cqid;
864 struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];
868 OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0,
869 OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF,
871 OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0,
872 OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF,
873 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16,
874 OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK = 0xFFFF <<
875 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
877 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0,
878 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF,
879 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16,
880 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK = 0xFFFF <<
881 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
883 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16,
884 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK = 0xFFFF <<
885 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
887 OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0,
888 OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF,
889 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16,
890 OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK = 0xFFFF <<
891 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
893 OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0,
894 OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF,
895 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16,
896 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF <<
897 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
899 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = Bit(0),
900 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1,
901 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF <<
902 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
903 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16,
904 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK = 0xFFFF <<
905 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
908 struct ocrdma_create_qp_rsp {
909 struct ocrdma_mqe_hdr hdr;
910 struct ocrdma_mbx_rsp rsp;
914 u32 max_sge_send_write;
921 struct ocrdma_destroy_qp {
922 struct ocrdma_mqe_hdr hdr;
923 struct ocrdma_mbx_hdr req;
927 struct ocrdma_destroy_qp_rsp {
928 struct ocrdma_mqe_hdr hdr;
929 struct ocrdma_mbx_rsp rsp;
933 OCRDMA_MODIFY_QP_ID_SHIFT = 0,
934 OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF,
936 OCRDMA_QP_PARA_QPS_VALID = Bit(0),
937 OCRDMA_QP_PARA_SQD_ASYNC_VALID = Bit(1),
938 OCRDMA_QP_PARA_PKEY_VALID = Bit(2),
939 OCRDMA_QP_PARA_QKEY_VALID = Bit(3),
940 OCRDMA_QP_PARA_PMTU_VALID = Bit(4),
941 OCRDMA_QP_PARA_ACK_TO_VALID = Bit(5),
942 OCRDMA_QP_PARA_RETRY_CNT_VALID = Bit(6),
943 OCRDMA_QP_PARA_RRC_VALID = Bit(7),
944 OCRDMA_QP_PARA_RQPSN_VALID = Bit(8),
945 OCRDMA_QP_PARA_MAX_IRD_VALID = Bit(9),
946 OCRDMA_QP_PARA_MAX_ORD_VALID = Bit(10),
947 OCRDMA_QP_PARA_RNT_VALID = Bit(11),
948 OCRDMA_QP_PARA_SQPSN_VALID = Bit(12),
949 OCRDMA_QP_PARA_DST_QPN_VALID = Bit(13),
950 OCRDMA_QP_PARA_MAX_WQE_VALID = Bit(14),
951 OCRDMA_QP_PARA_MAX_RQE_VALID = Bit(15),
952 OCRDMA_QP_PARA_SGE_SEND_VALID = Bit(16),
953 OCRDMA_QP_PARA_SGE_RECV_VALID = Bit(17),
954 OCRDMA_QP_PARA_SGE_WR_VALID = Bit(18),
955 OCRDMA_QP_PARA_INB_RDEN_VALID = Bit(19),
956 OCRDMA_QP_PARA_INB_WREN_VALID = Bit(20),
957 OCRDMA_QP_PARA_FLOW_LBL_VALID = Bit(21),
958 OCRDMA_QP_PARA_BIND_EN_VALID = Bit(22),
959 OCRDMA_QP_PARA_ZLKEY_EN_VALID = Bit(23),
960 OCRDMA_QP_PARA_FMR_EN_VALID = Bit(24),
961 OCRDMA_QP_PARA_INBAT_EN_VALID = Bit(25),
962 OCRDMA_QP_PARA_VLAN_EN_VALID = Bit(26),
964 OCRDMA_MODIFY_QP_FLAGS_RD = Bit(0),
965 OCRDMA_MODIFY_QP_FLAGS_WR = Bit(1),
966 OCRDMA_MODIFY_QP_FLAGS_SEND = Bit(2),
967 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = Bit(3)
971 OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0,
972 OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF,
974 OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0,
975 OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF,
976 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16,
977 OCRDMA_QP_PARAMS_MAX_WQE_MASK = 0xFFFF <<
978 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
980 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0,
981 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF,
982 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16,
983 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF <<
984 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
986 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = Bit(0),
987 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = Bit(1),
988 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = Bit(2),
989 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = Bit(3),
990 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = Bit(4),
991 OCRDMA_QP_PARAMS_STATE_SHIFT = 5,
992 OCRDMA_QP_PARAMS_STATE_MASK = Bit(5) | Bit(6) | Bit(7),
993 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = Bit(8),
994 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = Bit(9),
995 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16,
996 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF <<
997 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
999 OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0,
1000 OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF,
1001 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16,
1002 OCRDMA_QP_PARAMS_MAX_ORD_MASK = 0xFFFF <<
1003 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
1005 OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0,
1006 OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF,
1007 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16,
1008 OCRDMA_QP_PARAMS_WQ_CQID_MASK = 0xFFFF <<
1009 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
1011 OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0,
1012 OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF,
1013 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24,
1014 OCRDMA_QP_PARAMS_HOP_LMT_MASK = 0xFF <<
1015 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
1017 OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0,
1018 OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF,
1019 OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24,
1020 OCRDMA_QP_PARAMS_TCLASS_MASK = 0xFF <<
1021 OCRDMA_QP_PARAMS_TCLASS_SHIFT,
1023 OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0,
1024 OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF,
1025 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24,
1026 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK = 0x7 <<
1027 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
1028 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27,
1029 OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK = 0x1F <<
1030 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
1032 OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0,
1033 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF,
1034 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18,
1035 OCRDMA_QP_PARAMS_PATH_MTU_MASK = 0x3FFF <<
1036 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
1038 OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0,
1039 OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF,
1040 OCRDMA_QP_PARAMS_SL_SHIFT = 20,
1041 OCRDMA_QP_PARAMS_SL_MASK = 0xF <<
1042 OCRDMA_QP_PARAMS_SL_SHIFT,
1043 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24,
1044 OCRDMA_QP_PARAMS_RETRY_CNT_MASK = 0x7 <<
1045 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
1046 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27,
1047 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK = 0x1F <<
1048 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
1050 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0,
1051 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF,
1052 OCRDMA_QP_PARAMS_VLAN_SHIFT = 16,
1053 OCRDMA_QP_PARAMS_VLAN_MASK = 0xFFFF <<
1054 OCRDMA_QP_PARAMS_VLAN_SHIFT
1057 struct ocrdma_qp_params {
1060 u32 max_sge_send_write;
1061 u32 max_sge_recv_flags;
1066 u32 ack_to_rnr_rtc_dest_qpn;
1067 u32 path_mtu_pkey_indx;
1072 u32 vlan_dmac_b4_to_b5;
1077 struct ocrdma_modify_qp {
1078 struct ocrdma_mqe_hdr hdr;
1079 struct ocrdma_mbx_hdr req;
1081 struct ocrdma_qp_params params;
1084 u32 num_outstanding_atomic_rd;
1088 OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0,
1089 OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF,
1090 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16,
1091 OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK = 0xFFFF <<
1092 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1094 OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0,
1095 OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF,
1096 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16,
1097 OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK = 0xFFFF <<
1098 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1101 struct ocrdma_modify_qp_rsp {
1102 struct ocrdma_mqe_hdr hdr;
1103 struct ocrdma_mbx_rsp rsp;
1109 struct ocrdma_query_qp {
1110 struct ocrdma_mqe_hdr hdr;
1111 struct ocrdma_mbx_hdr req;
1113 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0
1114 #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF
1118 struct ocrdma_query_qp_rsp {
1119 struct ocrdma_mqe_hdr hdr;
1120 struct ocrdma_mbx_rsp rsp;
1121 struct ocrdma_qp_params params;
1125 OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0,
1126 OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF,
1127 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16,
1128 OCRDMA_CREATE_SRQ_PG_SZ_MASK = 0x3 <<
1129 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1131 OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0,
1132 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16,
1133 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK = 0xFFFF <<
1134 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1136 OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0,
1137 OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF,
1138 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16,
1139 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK = 0xFFFF <<
1140 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1143 struct ocrdma_create_srq {
1144 struct ocrdma_mqe_hdr hdr;
1145 struct ocrdma_mbx_hdr req;
1150 struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];
1154 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0,
1155 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF,
1157 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0,
1158 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF,
1159 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16,
1160 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK = 0xFFFF <<
1161 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1164 struct ocrdma_create_srq_rsp {
1165 struct ocrdma_mqe_hdr hdr;
1166 struct ocrdma_mbx_rsp rsp;
1169 u32 max_sge_rqe_allocated;
1173 OCRDMA_MODIFY_SRQ_ID_SHIFT = 0,
1174 OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF,
1176 OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,
1177 OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF,
1178 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16,
1179 OCRDMA_MODIFY_SRQ__LIMIT_MASK = 0xFFFF <<
1180 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1183 struct ocrdma_modify_srq {
1184 struct ocrdma_mqe_hdr hdr;
1185 struct ocrdma_mbx_rsp rep;
1192 OCRDMA_QUERY_SRQ_ID_SHIFT = 0,
1193 OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF
1196 struct ocrdma_query_srq {
1197 struct ocrdma_mqe_hdr hdr;
1198 struct ocrdma_mbx_rsp req;
1204 OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0,
1205 OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF,
1206 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16,
1207 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK = 0xFFFF <<
1208 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1210 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,
1211 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF,
1212 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16,
1213 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK = 0xFFFF <<
1214 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1217 struct ocrdma_query_srq_rsp {
1218 struct ocrdma_mqe_hdr hdr;
1219 struct ocrdma_mbx_rsp req;
1222 u32 srq_lmt_max_sge;
1226 OCRDMA_DESTROY_SRQ_ID_SHIFT = 0,
1227 OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF
1230 struct ocrdma_destroy_srq {
1231 struct ocrdma_mqe_hdr hdr;
1232 struct ocrdma_mbx_rsp req;
1238 OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16),
1239 OCRDMA_DPP_PAGE_SIZE = 4096
1242 struct ocrdma_alloc_pd {
1243 struct ocrdma_mqe_hdr hdr;
1244 struct ocrdma_mbx_hdr req;
1245 u32 enable_dpp_rsvd;
1249 OCRDMA_ALLOC_PD_RSP_DPP = Bit(16),
1250 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20,
1251 OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF,
1254 struct ocrdma_alloc_pd_rsp {
1255 struct ocrdma_mqe_hdr hdr;
1256 struct ocrdma_mbx_rsp rsp;
1260 struct ocrdma_dealloc_pd {
1261 struct ocrdma_mqe_hdr hdr;
1262 struct ocrdma_mbx_hdr req;
1266 struct ocrdma_dealloc_pd_rsp {
1267 struct ocrdma_mqe_hdr hdr;
1268 struct ocrdma_mbx_rsp rsp;
1272 OCRDMA_ADDR_CHECK_ENABLE = 1,
1273 OCRDMA_ADDR_CHECK_DISABLE = 0
1277 OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0,
1278 OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF,
1280 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0,
1281 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = Bit(0),
1282 OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1,
1283 OCRDMA_ALLOC_LKEY_FMR_MASK = Bit(1),
1284 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2,
1285 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = Bit(2),
1286 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3,
1287 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = Bit(3),
1288 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4,
1289 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = Bit(4),
1290 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5,
1291 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = Bit(5),
1292 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = Bit(6),
1293 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6,
1294 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16,
1295 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF <<
1296 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1299 struct ocrdma_alloc_lkey {
1300 struct ocrdma_mqe_hdr hdr;
1301 struct ocrdma_mbx_hdr req;
1307 struct ocrdma_alloc_lkey_rsp {
1308 struct ocrdma_mqe_hdr hdr;
1309 struct ocrdma_mbx_rsp rsp;
1315 struct ocrdma_dealloc_lkey {
1316 struct ocrdma_mqe_hdr hdr;
1317 struct ocrdma_mbx_hdr req;
1323 struct ocrdma_dealloc_lkey_rsp {
1324 struct ocrdma_mqe_hdr hdr;
1325 struct ocrdma_mbx_rsp rsp;
1328 #define MAX_OCRDMA_NSMR_PBL (u32)22
1329 #define MAX_OCRDMA_PBL_SIZE 65536
1330 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1333 OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0,
1334 OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF,
1335 OCRDMA_REG_NSMR_LRKEY_SHIFT = 24,
1336 OCRDMA_REG_NSMR_LRKEY_MASK = 0xFF <<
1337 OCRDMA_REG_NSMR_LRKEY_SHIFT,
1339 OCRDMA_REG_NSMR_PD_ID_SHIFT = 0,
1340 OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF,
1341 OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16,
1342 OCRDMA_REG_NSMR_NUM_PBL_MASK = 0xFFFF <<
1343 OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1345 OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0,
1346 OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF,
1347 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16,
1348 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF <<
1349 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1350 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24,
1351 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = Bit(24),
1352 OCRDMA_REG_NSMR_ZB_SHIFT = 25,
1353 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = Bit(25),
1354 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26,
1355 OCRDMA_REG_NSMR_REMOTE_INV_MASK = Bit(26),
1356 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27,
1357 OCRDMA_REG_NSMR_REMOTE_WR_MASK = Bit(27),
1358 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28,
1359 OCRDMA_REG_NSMR_REMOTE_RD_MASK = Bit(28),
1360 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29,
1361 OCRDMA_REG_NSMR_LOCAL_WR_MASK = Bit(29),
1362 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30,
1363 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = Bit(30),
1364 OCRDMA_REG_NSMR_LAST_SHIFT = 31,
1365 OCRDMA_REG_NSMR_LAST_MASK = Bit(31)
1368 struct ocrdma_reg_nsmr {
1369 struct ocrdma_mqe_hdr hdr;
1370 struct ocrdma_mbx_hdr cmd;
1374 u32 flags_hpage_pbe_sz;
1381 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1385 OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0,
1386 OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF,
1387 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16,
1388 OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK = 0xFFFF <<
1389 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1391 OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31,
1392 OCRDMA_REG_NSMR_CONT_LAST_MASK = Bit(31)
1395 struct ocrdma_reg_nsmr_cont {
1396 struct ocrdma_mqe_hdr hdr;
1397 struct ocrdma_mbx_hdr cmd;
1403 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1412 OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16,
1413 OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF0000
1415 struct ocrdma_reg_nsmr_rsp {
1416 struct ocrdma_mqe_hdr hdr;
1417 struct ocrdma_mbx_rsp rsp;
1424 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0,
1425 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF,
1426 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24,
1427 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK = 0xFF <<
1428 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1430 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16,
1431 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK = 0xFFFF <<
1432 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1435 struct ocrdma_reg_nsmr_cont_rsp {
1436 struct ocrdma_mqe_hdr hdr;
1437 struct ocrdma_mbx_rsp rsp;
1439 u32 lrkey_key_index;
1444 OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0,
1445 OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF
1448 struct ocrdma_alloc_mw {
1449 struct ocrdma_mqe_hdr hdr;
1450 struct ocrdma_mbx_hdr req;
1456 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0,
1457 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF
1460 struct ocrdma_alloc_mw_rsp {
1461 struct ocrdma_mqe_hdr hdr;
1462 struct ocrdma_mbx_rsp rsp;
1467 struct ocrdma_attach_mcast {
1468 struct ocrdma_mqe_hdr hdr;
1469 struct ocrdma_mbx_hdr req;
1473 u32 vlan_mac_b4_to_b5;
1476 struct ocrdma_attach_mcast_rsp {
1477 struct ocrdma_mqe_hdr hdr;
1478 struct ocrdma_mbx_rsp rsp;
1481 struct ocrdma_detach_mcast {
1482 struct ocrdma_mqe_hdr hdr;
1483 struct ocrdma_mbx_hdr req;
1487 u32 vlan_mac_b4_to_b5;
1490 struct ocrdma_detach_mcast_rsp {
1491 struct ocrdma_mqe_hdr hdr;
1492 struct ocrdma_mbx_rsp rsp;
1496 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19,
1497 OCRDMA_CREATE_AH_NUM_PAGES_MASK = 0xF <<
1498 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1500 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16,
1501 OCRDMA_CREATE_AH_PAGE_SIZE_MASK = 0x7 <<
1502 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1504 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23,
1505 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK = 0x1FF <<
1506 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1509 #define OCRDMA_AH_TBL_PAGES 8
1511 struct ocrdma_create_ah_tbl {
1512 struct ocrdma_mqe_hdr hdr;
1513 struct ocrdma_mbx_hdr req;
1516 struct ocrdma_pa tbl_addr[8];
1519 struct ocrdma_create_ah_tbl_rsp {
1520 struct ocrdma_mqe_hdr hdr;
1521 struct ocrdma_mbx_rsp rsp;
1525 struct ocrdma_delete_ah_tbl {
1526 struct ocrdma_mqe_hdr hdr;
1527 struct ocrdma_mbx_hdr req;
1531 struct ocrdma_delete_ah_tbl_rsp {
1532 struct ocrdma_mqe_hdr hdr;
1533 struct ocrdma_mbx_rsp rsp;
1537 OCRDMA_EQE_VALID_SHIFT = 0,
1538 OCRDMA_EQE_VALID_MASK = Bit(0),
1539 OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE,
1540 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16,
1541 OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF <<
1542 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1549 enum OCRDMA_CQE_STATUS {
1550 OCRDMA_CQE_SUCCESS = 0,
1551 OCRDMA_CQE_LOC_LEN_ERR,
1552 OCRDMA_CQE_LOC_QP_OP_ERR,
1553 OCRDMA_CQE_LOC_EEC_OP_ERR,
1554 OCRDMA_CQE_LOC_PROT_ERR,
1555 OCRDMA_CQE_WR_FLUSH_ERR,
1556 OCRDMA_CQE_MW_BIND_ERR,
1557 OCRDMA_CQE_BAD_RESP_ERR,
1558 OCRDMA_CQE_LOC_ACCESS_ERR,
1559 OCRDMA_CQE_REM_INV_REQ_ERR,
1560 OCRDMA_CQE_REM_ACCESS_ERR,
1561 OCRDMA_CQE_REM_OP_ERR,
1562 OCRDMA_CQE_RETRY_EXC_ERR,
1563 OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1564 OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1565 OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1566 OCRDMA_CQE_REM_ABORT_ERR,
1567 OCRDMA_CQE_INV_EECN_ERR,
1568 OCRDMA_CQE_INV_EEC_STATE_ERR,
1569 OCRDMA_CQE_FATAL_ERR,
1570 OCRDMA_CQE_RESP_TIMEOUT_ERR,
1571 OCRDMA_CQE_GENERAL_ERR
1576 OCRDMA_CQE_WQEIDX_SHIFT = 0,
1577 OCRDMA_CQE_WQEIDX_MASK = 0xFFFF,
1580 OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16,
1581 OCRDMA_CQE_PKEY_SHIFT = 0,
1582 OCRDMA_CQE_PKEY_MASK = 0xFFFF,
1585 OCRDMA_CQE_QPN_SHIFT = 0,
1586 OCRDMA_CQE_QPN_MASK = 0x0000FFFF,
1588 OCRDMA_CQE_BUFTAG_SHIFT = 16,
1589 OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,
1592 OCRDMA_CQE_UD_STATUS_SHIFT = 24,
1593 OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
1594 OCRDMA_CQE_STATUS_SHIFT = 16,
1595 OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
1596 OCRDMA_CQE_VALID = Bit(31),
1597 OCRDMA_CQE_INVALIDATE = Bit(30),
1598 OCRDMA_CQE_QTYPE = Bit(29),
1599 OCRDMA_CQE_IMM = Bit(28),
1600 OCRDMA_CQE_WRITE_IMM = Bit(27),
1601 OCRDMA_CQE_QTYPE_SQ = 0,
1602 OCRDMA_CQE_QTYPE_RQ = 1,
1603 OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF
1630 u32 flags_status_srcqpn; /* w3 */
1641 OCRDMA_FLAG_SIG = 0x1,
1642 OCRDMA_FLAG_INV = 0x2,
1643 OCRDMA_FLAG_FENCE_L = 0x4,
1644 OCRDMA_FLAG_FENCE_R = 0x8,
1645 OCRDMA_FLAG_SOLICIT = 0x10,
1646 OCRDMA_FLAG_IMM = 0x20,
1649 OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1,
1650 OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2,
1651 OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4,
1652 OCRDMA_LKEY_FLAG_VATO = 0x8,
1655 enum OCRDMA_WQE_OPCODE {
1656 OCRDMA_WRITE = 0x06,
1658 OCRDMA_RESV0 = 0x02,
1660 OCRDMA_CMP_SWP = 0x14,
1661 OCRDMA_BIND_MW = 0x10,
1662 OCRDMA_FR_MR = 0x11,
1663 OCRDMA_RESV1 = 0x0A,
1664 OCRDMA_LKEY_INV = 0x15,
1665 OCRDMA_FETCH_ADD = 0x13,
1666 OCRDMA_POST_RQ = 0x12
1670 OCRDMA_TYPE_INLINE = 0x0,
1671 OCRDMA_TYPE_LKEY = 0x1,
1675 OCRDMA_WQE_OPCODE_SHIFT = 0,
1676 OCRDMA_WQE_OPCODE_MASK = 0x0000001F,
1677 OCRDMA_WQE_FLAGS_SHIFT = 5,
1678 OCRDMA_WQE_TYPE_SHIFT = 16,
1679 OCRDMA_WQE_TYPE_MASK = 0x00030000,
1680 OCRDMA_WQE_SIZE_SHIFT = 18,
1681 OCRDMA_WQE_SIZE_MASK = 0xFF,
1682 OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25,
1684 OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0,
1685 OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF
1688 /* header WQE for all the SQ and RQ operations */
1689 struct ocrdma_hdr_wqe {
1693 u32 rsvd_lkey_flags;
1702 struct ocrdma_ewqe_ud_hdr {
1709 /* extended wqe followed by hdr_wqe for Fast Memory register */
1710 struct ocrdma_ewqe_fr {
1721 struct ocrdma_eth_basic {
1727 struct ocrdma_eth_vlan {
1732 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1733 __be16 roce_eth_type;
1738 __be32 pdid_hoplimit;
1744 #define OCRDMA_AV_VALID Bit(7)
1745 #define OCRDMA_AV_VLAN_VALID Bit(1)
1748 struct ocrdma_eth_vlan eth_hdr;
1749 struct ocrdma_grh grh;
1753 struct ocrdma_rsrc_stats {
1767 u32 r64K_to_2M_nsmr;
1768 u32 r2M_to_44M_nsmr;
1769 u32 r44M_to_1G_nsmr;
1771 u32 nsmr_count_4G_to_32G;
1772 u32 r32G_to_64G_nsmr;
1773 u32 r64G_to_128G_nsmr;
1774 u32 r128G_to_higher_nsmr;
1784 struct ocrdma_db_err_stats {
1785 u32 sq_doorbell_errors;
1786 u32 cq_doorbell_errors;
1787 u32 rq_srq_doorbell_errors;
1788 u32 cq_overflow_errors;
1792 struct ocrdma_wqe_stats {
1793 u32 large_send_rc_wqes_lo;
1794 u32 large_send_rc_wqes_hi;
1795 u32 large_write_rc_wqes_lo;
1796 u32 large_write_rc_wqes_hi;
1802 u32 mw_bind_wqes_lo;
1803 u32 mw_bind_wqes_hi;
1804 u32 invalidate_wqes_lo;
1805 u32 invalidate_wqes_hi;
1811 struct ocrdma_tx_stats {
1818 u32 read_rsp_pkts_lo;
1819 u32 read_rsp_pkts_hi;
1826 u32 read_req_bytes_lo;
1827 u32 read_req_bytes_hi;
1828 u32 read_rsp_bytes_lo;
1829 u32 read_rsp_bytes_hi;
1835 struct ocrdma_tx_qp_err_stats {
1836 u32 local_length_errors;
1837 u32 local_protection_errors;
1838 u32 local_qp_operation_errors;
1839 u32 retry_count_exceeded_errors;
1840 u32 rnr_retry_count_exceeded_errors;
1844 struct ocrdma_rx_stats {
1845 u32 roce_frame_bytes_lo;
1846 u32 roce_frame_bytes_hi;
1847 u32 roce_frame_icrc_drops;
1848 u32 roce_frame_payload_len_drops;
1851 u32 psn_error_request_packets;
1852 u32 psn_error_resp_packets;
1853 u32 rnr_nak_timeouts;
1854 u32 rnr_nak_receives;
1855 u32 roce_frame_rxmt_drops;
1856 u32 nak_count_psn_sequence_errors;
1857 u32 rc_drop_count_lookup_errors;
1865 struct ocrdma_rx_qp_err_stats {
1866 u32 nak_invalid_requst_errors;
1867 u32 nak_remote_operation_errors;
1868 u32 nak_count_remote_access_errors;
1869 u32 local_length_errors;
1870 u32 local_protection_errors;
1871 u32 local_qp_operation_errors;
1875 struct ocrdma_tx_dbg_stats {
1879 struct ocrdma_rx_dbg_stats {
1883 struct ocrdma_rdma_stats_req {
1884 struct ocrdma_mbx_hdr hdr;
1889 struct ocrdma_rdma_stats_resp {
1890 struct ocrdma_mbx_hdr hdr;
1891 struct ocrdma_rsrc_stats act_rsrc_stats;
1892 struct ocrdma_rsrc_stats th_rsrc_stats;
1893 struct ocrdma_db_err_stats db_err_stats;
1894 struct ocrdma_wqe_stats wqe_stats;
1895 struct ocrdma_tx_stats tx_stats;
1896 struct ocrdma_tx_qp_err_stats tx_qp_err_stats;
1897 struct ocrdma_rx_stats rx_stats;
1898 struct ocrdma_rx_qp_err_stats rx_qp_err_stats;
1899 struct ocrdma_tx_dbg_stats tx_dbg_stats;
1900 struct ocrdma_rx_dbg_stats rx_dbg_stats;
1904 struct mgmt_hba_attribs {
1905 u8 flashrom_version_string[32];
1906 u8 manufacturer_name[32];
1907 u32 supported_modes;
1909 u8 ncsi_ver_string[12];
1910 u32 default_extended_timeout;
1911 u8 controller_model_number[32];
1912 u8 controller_description[64];
1913 u8 controller_serial_number[32];
1914 u8 ip_version_string[32];
1915 u8 firmware_version_string[32];
1916 u8 bios_version_string[32];
1917 u8 redboot_version_string[32];
1918 u8 driver_version_string[32];
1919 u8 fw_on_flash_version_string[32];
1920 u32 functionalities_supported;
1923 u8 generational_guid[16];
1925 u16 default_link_down_timeout;
1926 u8 iscsi_ver_min_max;
1927 u8 multifunction_device;
1930 u8 max_domains_supported;
1932 u32 firmware_post_status;
1937 struct mgmt_controller_attrib {
1938 struct mgmt_hba_attribs hba_attribs;
1941 u16 pci_sub_vendor_id;
1942 u16 pci_sub_system_id;
1944 u8 pci_device_number;
1945 u8 pci_function_number;
1947 u64 unique_identifier;
1951 struct ocrdma_get_ctrl_attribs_rsp {
1952 struct ocrdma_mbx_hdr hdr;
1953 struct mgmt_controller_attrib ctrl_attribs;
1956 #define OCRDMA_SUBSYS_DCBX 0x10
1958 enum OCRDMA_DCBX_OPCODE {
1959 OCRDMA_CMD_GET_DCBX_CONFIG = 0x01
1962 enum OCRDMA_DCBX_PARAM_TYPE {
1963 OCRDMA_PARAMETER_TYPE_ADMIN = 0x00,
1964 OCRDMA_PARAMETER_TYPE_OPER = 0x01,
1965 OCRDMA_PARAMETER_TYPE_PEER = 0x02
1968 enum OCRDMA_DCBX_APP_PROTO {
1969 OCRDMA_APP_PROTO_ROCE = 0x8915
1972 enum OCRDMA_DCBX_PROTO {
1973 OCRDMA_PROTO_SELECT_L2 = 0x00,
1974 OCRDMA_PROTO_SELECT_L4 = 0x01
1977 enum OCRDMA_DCBX_APP_PARAM {
1978 OCRDMA_APP_PARAM_APP_PROTO_MASK = 0xFFFF,
1979 OCRDMA_APP_PARAM_PROTO_SEL_MASK = 0xFF,
1980 OCRDMA_APP_PARAM_PROTO_SEL_SHIFT = 0x10,
1981 OCRDMA_APP_PARAM_VALID_MASK = 0xFF,
1982 OCRDMA_APP_PARAM_VALID_SHIFT = 0x18
1985 enum OCRDMA_DCBX_STATE_FLAGS {
1986 OCRDMA_STATE_FLAG_ENABLED = 0x01,
1987 OCRDMA_STATE_FLAG_ADDVERTISED = 0x02,
1988 OCRDMA_STATE_FLAG_WILLING = 0x04,
1989 OCRDMA_STATE_FLAG_SYNC = 0x08,
1990 OCRDMA_STATE_FLAG_UNSUPPORTED = 0x40000000,
1991 OCRDMA_STATE_FLAG_NEG_FAILD = 0x80000000
1994 enum OCRDMA_TCV_AEV_OPV_ST {
1995 OCRDMA_DCBX_TC_SUPPORT_MASK = 0xFF,
1996 OCRDMA_DCBX_TC_SUPPORT_SHIFT = 0x18,
1997 OCRDMA_DCBX_APP_ENTRY_SHIFT = 0x10,
1998 OCRDMA_DCBX_OP_PARAM_SHIFT = 0x08,
1999 OCRDMA_DCBX_STATE_MASK = 0xFF
2002 struct ocrdma_app_parameter {
2003 u32 valid_proto_app;
2008 struct ocrdma_dcbx_cfg {
2018 struct ocrdma_app_parameter app_param[15];
2021 struct ocrdma_get_dcbx_cfg_req {
2022 struct ocrdma_mbx_hdr hdr;
2026 struct ocrdma_get_dcbx_cfg_rsp {
2027 struct ocrdma_mbx_rsp hdr;
2028 struct ocrdma_dcbx_cfg cfg;
2031 #endif /* __OCRDMA_SLI_H__ */