drivers/infiniband/hw/ocrdma/ocrdma_hw.c

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) CNA Adapters.              *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #include <linux/sched.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/log2.h>
  31 #include <linux/dma-mapping.h>
  32
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_user_verbs.h>
  35
  36 #include "ocrdma.h"
  37 #include "ocrdma_hw.h"
  38 #include "ocrdma_verbs.h"
  39 #include "ocrdma_ah.h"
  40
  41 enum mbx_status {
  42         OCRDMA_MBX_STATUS_FAILED                = 1,
  43         OCRDMA_MBX_STATUS_ILLEGAL_FIELD         = 3,
  44         OCRDMA_MBX_STATUS_OOR                   = 100,
  45         OCRDMA_MBX_STATUS_INVALID_PD            = 101,
  46         OCRDMA_MBX_STATUS_PD_INUSE              = 102,
  47         OCRDMA_MBX_STATUS_INVALID_CQ            = 103,
  48         OCRDMA_MBX_STATUS_INVALID_QP            = 104,
  49         OCRDMA_MBX_STATUS_INVALID_LKEY          = 105,
  50         OCRDMA_MBX_STATUS_ORD_EXCEEDS           = 106,
  51         OCRDMA_MBX_STATUS_IRD_EXCEEDS           = 107,
  52         OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS     = 108,
  53         OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS     = 109,
  54         OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS      = 110,
  55         OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS     = 111,
  56         OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS      = 112,
  57         OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE  = 113,
  58         OCRDMA_MBX_STATUS_MW_BOUND              = 114,
  59         OCRDMA_MBX_STATUS_INVALID_VA            = 115,
  60         OCRDMA_MBX_STATUS_INVALID_LENGTH        = 116,
  61         OCRDMA_MBX_STATUS_INVALID_FBO           = 117,
  62         OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS    = 118,
  63         OCRDMA_MBX_STATUS_INVALID_PBE_SIZE      = 119,
  64         OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY     = 120,
  65         OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT     = 121,
  66         OCRDMA_MBX_STATUS_INVALID_SRQ_ID        = 129,
  67         OCRDMA_MBX_STATUS_SRQ_ERROR             = 133,
  68         OCRDMA_MBX_STATUS_RQE_EXCEEDS           = 134,
  69         OCRDMA_MBX_STATUS_MTU_EXCEEDS           = 135,
  70         OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS        = 136,
  71         OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS     = 137,
  72         OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS     = 138,
  73         OCRDMA_MBX_STATUS_QP_BOUND              = 130,
  74         OCRDMA_MBX_STATUS_INVALID_CHANGE        = 139,
  75         OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP      = 140,
  76         OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
  77         OCRDMA_MBX_STATUS_MW_STILL_BOUND        = 142,
  78         OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID    = 143,
  79         OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS    = 144
  80 };
  81
  82 enum additional_status {
  83         OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
  84 };
  85
  86 enum cqe_status {
  87         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES  = 1,
  88         OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER         = 2,
  89         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES    = 3,
  90         OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING            = 4,
  91         OCRDMA_MBX_CQE_STATUS_DMA_FAILED                = 5
  92 };
  93
  94 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
  95 {
  96         return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
  97 }
  98
  99 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
 100 {
 101         eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
 102 }
 103
 104 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
 105 {
 106         struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
 107             (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
 108
 109         if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
 110                 return NULL;
 111         return cqe;
 112 }
 113
 114 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
 115 {
 116         dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
 117 }
 118
 119 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
 120 {
 121         return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
 122 }
 123
 124 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
 125 {
 126         dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
 127 }
 128
 129 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
 130 {
 131         return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
 132 }
 133
 134 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
 135 {
 136         switch (qps) {
 137         case OCRDMA_QPS_RST:
 138                 return IB_QPS_RESET;
 139         case OCRDMA_QPS_INIT:
 140                 return IB_QPS_INIT;
 141         case OCRDMA_QPS_RTR:
 142                 return IB_QPS_RTR;
 143         case OCRDMA_QPS_RTS:
 144                 return IB_QPS_RTS;
 145         case OCRDMA_QPS_SQD:
 146         case OCRDMA_QPS_SQ_DRAINING:
 147                 return IB_QPS_SQD;
 148         case OCRDMA_QPS_SQE:
 149                 return IB_QPS_SQE;
 150         case OCRDMA_QPS_ERR:
 151                 return IB_QPS_ERR;
 152         }
 153         return IB_QPS_ERR;
 154 }
 155
 156 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
 157 {
 158         switch (qps) {
 159         case IB_QPS_RESET:
 160                 return OCRDMA_QPS_RST;
 161         case IB_QPS_INIT:
 162                 return OCRDMA_QPS_INIT;
 163         case IB_QPS_RTR:
 164                 return OCRDMA_QPS_RTR;
 165         case IB_QPS_RTS:
 166                 return OCRDMA_QPS_RTS;
 167         case IB_QPS_SQD:
 168                 return OCRDMA_QPS_SQD;
 169         case IB_QPS_SQE:
 170                 return OCRDMA_QPS_SQE;
 171         case IB_QPS_ERR:
 172                 return OCRDMA_QPS_ERR;
 173         }
 174         return OCRDMA_QPS_ERR;
 175 }
 176
 177 static int ocrdma_get_mbx_errno(u32 status)
 178 {
 179         int err_num;
 180         u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
 181                                         OCRDMA_MBX_RSP_STATUS_SHIFT;
 182         u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
 183                                         OCRDMA_MBX_RSP_ASTATUS_SHIFT;
 184
 185         switch (mbox_status) {
 186         case OCRDMA_MBX_STATUS_OOR:
 187         case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
 188                 err_num = -EAGAIN;
 189                 break;
 190
 191         case OCRDMA_MBX_STATUS_INVALID_PD:
 192         case OCRDMA_MBX_STATUS_INVALID_CQ:
 193         case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
 194         case OCRDMA_MBX_STATUS_INVALID_QP:
 195         case OCRDMA_MBX_STATUS_INVALID_CHANGE:
 196         case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
 197         case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
 198         case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
 199         case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
 200         case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
 201         case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
 202         case OCRDMA_MBX_STATUS_INVALID_LKEY:
 203         case OCRDMA_MBX_STATUS_INVALID_VA:
 204         case OCRDMA_MBX_STATUS_INVALID_LENGTH:
 205         case OCRDMA_MBX_STATUS_INVALID_FBO:
 206         case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
 207         case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
 208         case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
 209         case OCRDMA_MBX_STATUS_SRQ_ERROR:
 210         case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
 211                 err_num = -EINVAL;
 212                 break;
 213
 214         case OCRDMA_MBX_STATUS_PD_INUSE:
 215         case OCRDMA_MBX_STATUS_QP_BOUND:
 216         case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
 217         case OCRDMA_MBX_STATUS_MW_BOUND:
 218                 err_num = -EBUSY;
 219                 break;
 220
 221         case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
 222         case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
 223         case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
 224         case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
 225         case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
 226         case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
 227         case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
 228         case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
 229         case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
 230                 err_num = -ENOBUFS;
 231                 break;
 232
 233         case OCRDMA_MBX_STATUS_FAILED:
 234                 switch (add_status) {
 235                 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
 236                         err_num = -EAGAIN;
 237                         break;
 238                 }
 239         default:
 240                 err_num = -EFAULT;
 241         }
 242         return err_num;
 243 }
 244
 245 char *port_speed_string(struct ocrdma_dev *dev)
 246 {
 247         char *str = "";
 248         u16 speeds_supported;
 249
 250         speeds_supported = dev->phy.fixed_speeds_supported |
 251                                 dev->phy.auto_speeds_supported;
 252         if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
 253                 str = "40Gbps ";
 254         else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
 255                 str = "10Gbps ";
 256         else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
 257                 str = "1Gbps ";
 258
 259         return str;
 260 }
 261
 262 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
 263 {
 264         int err_num = -EINVAL;
 265
 266         switch (cqe_status) {
 267         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
 268                 err_num = -EPERM;
 269                 break;
 270         case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
 271                 err_num = -EINVAL;
 272                 break;
 273         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
 274         case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
 275                 err_num = -EINVAL;
 276                 break;
 277         case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
 278         default:
 279                 err_num = -EINVAL;
 280                 break;
 281         }
 282         return err_num;
 283 }
 284
 285 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
 286                        bool solicited, u16 cqe_popped)
 287 {
 288         u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
 289
 290         val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
 291              OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
 292
 293         if (armed)
 294                 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
 295         if (solicited)
 296                 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
 297         val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
 298         iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
 299 }
 300
 301 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
 302 {
 303         u32 val = 0;
 304
 305         val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
 306         val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
 307         iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
 308 }
 309
 310 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
 311                               bool arm, bool clear_int, u16 num_eqe)
 312 {
 313         u32 val = 0;
 314
 315         val |= eq_id & OCRDMA_EQ_ID_MASK;
 316         val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
 317         if (arm)
 318                 val |= (1 << OCRDMA_REARM_SHIFT);
 319         if (clear_int)
 320                 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
 321         val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
 322         val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
 323         iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
 324 }
 325
 326 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
 327                             u8 opcode, u8 subsys, u32 cmd_len)
 328 {
 329         cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
 330         cmd_hdr->timeout = 20; /* seconds */
 331         cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
 332 }
 333
 334 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
 335 {
 336         struct ocrdma_mqe *mqe;
 337
 338         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
 339         if (!mqe)
 340                 return NULL;
 341         mqe->hdr.spcl_sge_cnt_emb |=
 342                 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
 343                                         OCRDMA_MQE_HDR_EMB_MASK;
 344         mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
 345
 346         ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
 347                         mqe->hdr.pyld_len);
 348         return mqe;
 349 }
 350
 351 static void *ocrdma_alloc_mqe(void)
 352 {
 353         return kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
 354 }
 355
 356 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
 357 {
 358         dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
 359 }
 360
 361 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
 362                           struct ocrdma_queue_info *q, u16 len, u16 entry_size)
 363 {
 364         memset(q, 0, sizeof(*q));
 365         q->len = len;
 366         q->entry_size = entry_size;
 367         q->size = len * entry_size;
 368         q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
 369                                    &q->dma, GFP_KERNEL);
 370         if (!q->va)
 371                 return -ENOMEM;
 372         memset(q->va, 0, q->size);
 373         return 0;
 374 }
 375
 376 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
 377                                         dma_addr_t host_pa, int hw_page_size)
 378 {
 379         int i;
 380
 381         for (i = 0; i < cnt; i++) {
 382                 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
 383                 q_pa[i].hi = (u32) upper_32_bits(host_pa);
 384                 host_pa += hw_page_size;
 385         }
 386 }
 387
 388 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
 389                                struct ocrdma_queue_info *q, int queue_type)
 390 {
 391         u8 opcode = 0;
 392         int status;
 393         struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
 394
 395         switch (queue_type) {
 396         case QTYPE_MCCQ:
 397                 opcode = OCRDMA_CMD_DELETE_MQ;
 398                 break;
 399         case QTYPE_CQ:
 400                 opcode = OCRDMA_CMD_DELETE_CQ;
 401                 break;
 402         case QTYPE_EQ:
 403                 opcode = OCRDMA_CMD_DELETE_EQ;
 404                 break;
 405         default:
 406                 BUG();
 407         }
 408         memset(cmd, 0, sizeof(*cmd));
 409         ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 410         cmd->id = q->id;
 411
 412         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 413                                  cmd, sizeof(*cmd), NULL, NULL);
 414         if (!status)
 415                 q->created = false;
 416         return status;
 417 }
 418
 419 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 420 {
 421         int status;
 422         struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
 423         struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
 424
 425         memset(cmd, 0, sizeof(*cmd));
 426         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
 427                         sizeof(*cmd));
 428
 429         cmd->req.rsvd_version = 2;
 430         cmd->num_pages = 4;
 431         cmd->valid = OCRDMA_CREATE_EQ_VALID;
 432         cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
 433
 434         ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
 435                              PAGE_SIZE_4K);
 436         status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
 437                                  NULL);
 438         if (!status) {
 439                 eq->q.id = rsp->vector_eqid & 0xffff;
 440                 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
 441                 eq->q.created = true;
 442         }
 443         return status;
 444 }
 445
 446 static int ocrdma_create_eq(struct ocrdma_dev *dev,
 447                             struct ocrdma_eq *eq, u16 q_len)
 448 {
 449         int status;
 450
 451         status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
 452                                 sizeof(struct ocrdma_eqe));
 453         if (status)
 454                 return status;
 455
 456         status = ocrdma_mbx_create_eq(dev, eq);
 457         if (status)
 458                 goto mbx_err;
 459         eq->dev = dev;
 460         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 461
 462         return 0;
 463 mbx_err:
 464         ocrdma_free_q(dev, &eq->q);
 465         return status;
 466 }
 467
 468 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 469 {
 470         int irq;
 471
 472         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
 473                 irq = dev->nic_info.pdev->irq;
 474         else
 475                 irq = dev->nic_info.msix.vector_list[eq->vector];
 476         return irq;
 477 }
 478
 479 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 480 {
 481         if (eq->q.created) {
 482                 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
 483                 ocrdma_free_q(dev, &eq->q);
 484         }
 485 }
 486
 487 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 488 {
 489         int irq;
 490
 491         /* disarm EQ so that interrupts are not generated
 492          * during freeing and EQ delete is in progress.
 493          */
 494         ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
 495
 496         irq = ocrdma_get_irq(dev, eq);
 497         free_irq(irq, eq);
 498         _ocrdma_destroy_eq(dev, eq);
 499 }
 500
 501 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
 502 {
 503         int i;
 504
 505         for (i = 0; i < dev->eq_cnt; i++)
 506                 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
 507 }
 508
 509 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
 510                                    struct ocrdma_queue_info *cq,
 511                                    struct ocrdma_queue_info *eq)
 512 {
 513         struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
 514         struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
 515         int status;
 516
 517         memset(cmd, 0, sizeof(*cmd));
 518         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
 519                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 520
 521         cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
 522         cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
 523                 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
 524         cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
 525
 526         cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
 527         cmd->eqn = eq->id;
 528         cmd->cqe_count = cq->size / sizeof(struct ocrdma_mcqe);
 529
 530         ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
 531                              cq->dma, PAGE_SIZE_4K);
 532         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 533                                  cmd, sizeof(*cmd), NULL, NULL);
 534         if (!status) {
 535                 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
 536                 cq->created = true;
 537         }
 538         return status;
 539 }
 540
 541 static u32 ocrdma_encoded_q_len(int q_len)
 542 {
 543         u32 len_encoded = fls(q_len);   /* log2(len) + 1 */
 544
 545         if (len_encoded == 16)
 546                 len_encoded = 0;
 547         return len_encoded;
 548 }
 549
 550 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
 551                                 struct ocrdma_queue_info *mq,
 552                                 struct ocrdma_queue_info *cq)
 553 {
 554         int num_pages, status;
 555         struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
 556         struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
 557         struct ocrdma_pa *pa;
 558
 559         memset(cmd, 0, sizeof(*cmd));
 560         num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
 561
 562         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
 563                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 564         cmd->req.rsvd_version = 1;
 565         cmd->cqid_pages = num_pages;
 566         cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
 567         cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
 568
 569         cmd->async_event_bitmap = Bit(OCRDMA_ASYNC_GRP5_EVE_CODE);
 570         cmd->async_event_bitmap |= Bit(OCRDMA_ASYNC_RDMA_EVE_CODE);
 571
 572         cmd->async_cqid_ringsize = cq->id;
 573         cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
 574                                 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
 575         cmd->valid = OCRDMA_CREATE_MQ_VALID;
 576         pa = &cmd->pa[0];
 577
 578         ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
 579         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 580                                  cmd, sizeof(*cmd), NULL, NULL);
 581         if (!status) {
 582                 mq->id = rsp->id;
 583                 mq->created = true;
 584         }
 585         return status;
 586 }
 587
 588 static int ocrdma_create_mq(struct ocrdma_dev *dev)
 589 {
 590         int status;
 591
 592         /* Alloc completion queue for Mailbox queue */
 593         status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
 594                                 sizeof(struct ocrdma_mcqe));
 595         if (status)
 596                 goto alloc_err;
 597
 598         dev->eq_tbl[0].cq_cnt++;
 599         status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
 600         if (status)
 601                 goto mbx_cq_free;
 602
 603         memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
 604         init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
 605         mutex_init(&dev->mqe_ctx.lock);
 606
 607         /* Alloc Mailbox queue */
 608         status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
 609                                 sizeof(struct ocrdma_mqe));
 610         if (status)
 611                 goto mbx_cq_destroy;
 612         status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
 613         if (status)
 614                 goto mbx_q_free;
 615         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
 616         return 0;
 617
 618 mbx_q_free:
 619         ocrdma_free_q(dev, &dev->mq.sq);
 620 mbx_cq_destroy:
 621         ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
 622 mbx_cq_free:
 623         ocrdma_free_q(dev, &dev->mq.cq);
 624 alloc_err:
 625         return status;
 626 }
 627
 628 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
 629 {
 630         struct ocrdma_queue_info *mbxq, *cq;
 631
 632         /* mqe_ctx lock synchronizes with any other pending cmds. */
 633         mutex_lock(&dev->mqe_ctx.lock);
 634         mbxq = &dev->mq.sq;
 635         if (mbxq->created) {
 636                 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
 637                 ocrdma_free_q(dev, mbxq);
 638         }
 639         mutex_unlock(&dev->mqe_ctx.lock);
 640
 641         cq = &dev->mq.cq;
 642         if (cq->created) {
 643                 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
 644                 ocrdma_free_q(dev, cq);
 645         }
 646 }
 647
 648 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
 649                                        struct ocrdma_qp *qp)
 650 {
 651         enum ib_qp_state new_ib_qps = IB_QPS_ERR;
 652         enum ib_qp_state old_ib_qps;
 653
 654         if (qp == NULL)
 655                 BUG();
 656         ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
 657 }
 658
 659 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
 660                                     struct ocrdma_ae_mcqe *cqe)
 661 {
 662         struct ocrdma_qp *qp = NULL;
 663         struct ocrdma_cq *cq = NULL;
 664         struct ib_event ib_evt = { 0 };
 665         int cq_event = 0;
 666         int qp_event = 1;
 667         int srq_event = 0;
 668         int dev_event = 0;
 669         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 670             OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 671
 672         if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
 673                 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
 674         if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
 675                 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
 676
 677         ib_evt.device = &dev->ibdev;
 678
 679         switch (type) {
 680         case OCRDMA_CQ_ERROR:
 681                 ib_evt.element.cq = &cq->ibcq;
 682                 ib_evt.event = IB_EVENT_CQ_ERR;
 683                 cq_event = 1;
 684                 qp_event = 0;
 685                 break;
 686         case OCRDMA_CQ_OVERRUN_ERROR:
 687                 ib_evt.element.cq = &cq->ibcq;
 688                 ib_evt.event = IB_EVENT_CQ_ERR;
 689                 cq_event = 1;
 690                 qp_event = 0;
 691                 break;
 692         case OCRDMA_CQ_QPCAT_ERROR:
 693                 ib_evt.element.qp = &qp->ibqp;
 694                 ib_evt.event = IB_EVENT_QP_FATAL;
 695                 ocrdma_process_qpcat_error(dev, qp);
 696                 break;
 697         case OCRDMA_QP_ACCESS_ERROR:
 698                 ib_evt.element.qp = &qp->ibqp;
 699                 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
 700                 break;
 701         case OCRDMA_QP_COMM_EST_EVENT:
 702                 ib_evt.element.qp = &qp->ibqp;
 703                 ib_evt.event = IB_EVENT_COMM_EST;
 704                 break;
 705         case OCRDMA_SQ_DRAINED_EVENT:
 706                 ib_evt.element.qp = &qp->ibqp;
 707                 ib_evt.event = IB_EVENT_SQ_DRAINED;
 708                 break;
 709         case OCRDMA_DEVICE_FATAL_EVENT:
 710                 ib_evt.element.port_num = 1;
 711                 ib_evt.event = IB_EVENT_DEVICE_FATAL;
 712                 qp_event = 0;
 713                 dev_event = 1;
 714                 break;
 715         case OCRDMA_SRQCAT_ERROR:
 716                 ib_evt.element.srq = &qp->srq->ibsrq;
 717                 ib_evt.event = IB_EVENT_SRQ_ERR;
 718                 srq_event = 1;
 719                 qp_event = 0;
 720                 break;
 721         case OCRDMA_SRQ_LIMIT_EVENT:
 722                 ib_evt.element.srq = &qp->srq->ibsrq;
 723                 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
 724                 srq_event = 1;
 725                 qp_event = 0;
 726                 break;
 727         case OCRDMA_QP_LAST_WQE_EVENT:
 728                 ib_evt.element.qp = &qp->ibqp;
 729                 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
 730                 break;
 731         default:
 732                 cq_event = 0;
 733                 qp_event = 0;
 734                 srq_event = 0;
 735                 dev_event = 0;
 736                 pr_err("%s() unknown type=0x%x\n", __func__, type);
 737                 break;
 738         }
 739
 740         if (qp_event) {
 741                 if (qp->ibqp.event_handler)
 742                         qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
 743         } else if (cq_event) {
 744                 if (cq->ibcq.event_handler)
 745                         cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
 746         } else if (srq_event) {
 747                 if (qp->srq->ibsrq.event_handler)
 748                         qp->srq->ibsrq.event_handler(&ib_evt,
 749                                                      qp->srq->ibsrq.
 750                                                      srq_context);
 751         } else if (dev_event) {
 752                 pr_err("%s: Fatal event received\n", dev->ibdev.name);
 753                 ib_dispatch_event(&ib_evt);
 754         }
 755
 756 }
 757
 758 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
 759                                         struct ocrdma_ae_mcqe *cqe)
 760 {
 761         struct ocrdma_ae_pvid_mcqe *evt;
 762         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 763                         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 764
 765         switch (type) {
 766         case OCRDMA_ASYNC_EVENT_PVID_STATE:
 767                 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
 768                 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
 769                         OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
 770                         dev->pvid = ((evt->tag_enabled &
 771                                         OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
 772                                         OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
 773                 break;
 774
 775         case OCRDMA_ASYNC_EVENT_COS_VALUE:
 776                 atomic_set(&dev->update_sl, 1);
 777                 break;
 778         default:
 779                 /* Not interested evts. */
 780                 break;
 781         }
 782 }
 783
 784 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
 785 {
 786         /* async CQE processing */
 787         struct ocrdma_ae_mcqe *cqe = ae_cqe;
 788         u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
 789                         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
 790
 791         if (evt_code == OCRDMA_ASYNC_RDMA_EVE_CODE)
 792                 ocrdma_dispatch_ibevent(dev, cqe);
 793         else if (evt_code == OCRDMA_ASYNC_GRP5_EVE_CODE)
 794                 ocrdma_process_grp5_aync(dev, cqe);
 795         else
 796                 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
 797                        dev->id, evt_code);
 798 }
 799
 800 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
 801 {
 802         if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
 803                 dev->mqe_ctx.cqe_status = (cqe->status &
 804                      OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
 805                 dev->mqe_ctx.ext_status =
 806                     (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
 807                     >> OCRDMA_MCQE_ESTATUS_SHIFT;
 808                 dev->mqe_ctx.cmd_done = true;
 809                 wake_up(&dev->mqe_ctx.cmd_wait);
 810         } else
 811                 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
 812                        __func__, cqe->tag_lo, dev->mqe_ctx.tag);
 813 }
 814
 815 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 816 {
 817         u16 cqe_popped = 0;
 818         struct ocrdma_mcqe *cqe;
 819
 820         while (1) {
 821                 cqe = ocrdma_get_mcqe(dev);
 822                 if (cqe == NULL)
 823                         break;
 824                 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
 825                 cqe_popped += 1;
 826                 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
 827                         ocrdma_process_acqe(dev, cqe);
 828                 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
 829                         ocrdma_process_mcqe(dev, cqe);
 830                 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
 831                 ocrdma_mcq_inc_tail(dev);
 832         }
 833         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
 834         return 0;
 835 }
 836
 837 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
 838                                        struct ocrdma_cq *cq)
 839 {
 840         unsigned long flags;
 841         struct ocrdma_qp *qp;
 842         bool buddy_cq_found = false;
 843         /* Go through list of QPs in error state which are using this CQ
 844          * and invoke its callback handler to trigger CQE processing for
 845          * error/flushed CQE. It is rare to find more than few entries in
 846          * this list as most consumers stops after getting error CQE.
 847          * List is traversed only once when a matching buddy cq found for a QP.
 848          */
 849         spin_lock_irqsave(&dev->flush_q_lock, flags);
 850         list_for_each_entry(qp, &cq->sq_head, sq_entry) {
 851                 if (qp->srq)
 852                         continue;
 853                 /* if wq and rq share the same cq, than comp_handler
 854                  * is already invoked.
 855                  */
 856                 if (qp->sq_cq == qp->rq_cq)
 857                         continue;
 858                 /* if completion came on sq, rq's cq is buddy cq.
 859                  * if completion came on rq, sq's cq is buddy cq.
 860                  */
 861                 if (qp->sq_cq == cq)
 862                         cq = qp->rq_cq;
 863                 else
 864                         cq = qp->sq_cq;
 865                 buddy_cq_found = true;
 866                 break;
 867         }
 868         spin_unlock_irqrestore(&dev->flush_q_lock, flags);
 869         if (buddy_cq_found == false)
 870                 return;
 871         if (cq->ibcq.comp_handler) {
 872                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 873                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 874                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 875         }
 876 }
 877
 878 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
 879 {
 880         unsigned long flags;
 881         struct ocrdma_cq *cq;
 882
 883         if (cq_idx >= OCRDMA_MAX_CQ)
 884                 BUG();
 885
 886         cq = dev->cq_tbl[cq_idx];
 887         if (cq == NULL)
 888                 return;
 889
 890         if (cq->ibcq.comp_handler) {
 891                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 892                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 893                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 894         }
 895         ocrdma_qp_buddy_cq_handler(dev, cq);
 896 }
 897
 898 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 899 {
 900         /* process the MQ-CQE. */
 901         if (cq_id == dev->mq.cq.id)
 902                 ocrdma_mq_cq_handler(dev, cq_id);
 903         else
 904                 ocrdma_qp_cq_handler(dev, cq_id);
 905 }
 906
 907 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
 908 {
 909         struct ocrdma_eq *eq = handle;
 910         struct ocrdma_dev *dev = eq->dev;
 911         struct ocrdma_eqe eqe;
 912         struct ocrdma_eqe *ptr;
 913         u16 cq_id;
 914         int budget = eq->cq_cnt;
 915
 916         do {
 917                 ptr = ocrdma_get_eqe(eq);
 918                 eqe = *ptr;
 919                 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
 920                 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
 921                         break;
 922
 923                 ptr->id_valid = 0;
 924                 /* ring eq doorbell as soon as its consumed. */
 925                 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
 926                 /* check whether its CQE or not. */
 927                 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
 928                         cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
 929                         ocrdma_cq_handler(dev, cq_id);
 930                 }
 931                 ocrdma_eq_inc_tail(eq);
 932
 933                 /* There can be a stale EQE after the last bound CQ is
 934                  * destroyed. EQE valid and budget == 0 implies this.
 935                  */
 936                 if (budget)
 937                         budget--;
 938
 939         } while (budget);
 940
 941         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 942         return IRQ_HANDLED;
 943 }
 944
 945 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
 946 {
 947         struct ocrdma_mqe *mqe;
 948
 949         dev->mqe_ctx.tag = dev->mq.sq.head;
 950         dev->mqe_ctx.cmd_done = false;
 951         mqe = ocrdma_get_mqe(dev);
 952         cmd->hdr.tag_lo = dev->mq.sq.head;
 953         ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
 954         /* make sure descriptor is written before ringing doorbell */
 955         wmb();
 956         ocrdma_mq_inc_head(dev);
 957         ocrdma_ring_mq_db(dev);
 958 }
 959
 960 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
 961 {
 962         long status;
 963         /* 30 sec timeout */
 964         status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
 965                                     (dev->mqe_ctx.cmd_done != false),
 966                                     msecs_to_jiffies(30000));
 967         if (status)
 968                 return 0;
 969         else
 970                 return -1;
 971 }
 972
 973 /* issue a mailbox command on the MQ */
 974 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
 975 {
 976         int status = 0;
 977         u16 cqe_status, ext_status;
 978         struct ocrdma_mqe *rsp_mqe;
 979         struct ocrdma_mbx_rsp *rsp = NULL;
 980
 981         mutex_lock(&dev->mqe_ctx.lock);
 982         ocrdma_post_mqe(dev, mqe);
 983         status = ocrdma_wait_mqe_cmpl(dev);
 984         if (status)
 985                 goto mbx_err;
 986         cqe_status = dev->mqe_ctx.cqe_status;
 987         ext_status = dev->mqe_ctx.ext_status;
 988         rsp_mqe = ocrdma_get_mqe_rsp(dev);
 989         ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
 990         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
 991                                 OCRDMA_MQE_HDR_EMB_SHIFT)
 992                 rsp = &mqe->u.rsp;
 993
 994         if (cqe_status || ext_status) {
 995                 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,",
 996                        __func__, cqe_status, ext_status);
 997                 if (rsp) {
 998                         /* This is for embedded cmds. */
 999                         pr_err("opcode=0x%x, subsystem=0x%x\n",
1000                                (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1001                                 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1002                                 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1003                                 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1004                 }
1005                 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1006                 goto mbx_err;
1007         }
1008         /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1009         if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
1010                 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1011 mbx_err:
1012         mutex_unlock(&dev->mqe_ctx.lock);
1013         return status;
1014 }
1015
1016 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1017                                  void *payload_va)
1018 {
1019         int status = 0;
1020         struct ocrdma_mbx_rsp *rsp = payload_va;
1021
1022         if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1023                                 OCRDMA_MQE_HDR_EMB_SHIFT)
1024                 BUG();
1025
1026         status = ocrdma_mbx_cmd(dev, mqe);
1027         if (!status)
1028                 /* For non embedded, only CQE failures are handled in
1029                  * ocrdma_mbx_cmd. We need to check for RSP errors.
1030                  */
1031                 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1032                         status = ocrdma_get_mbx_errno(rsp->status);
1033
1034         if (status)
1035                 pr_err("opcode=0x%x, subsystem=0x%x\n",
1036                        (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1037                         OCRDMA_MBX_RSP_OPCODE_SHIFT,
1038                         (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1039                         OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1040         return status;
1041 }
1042
1043 static void ocrdma_get_attr(struct ocrdma_dev *dev,
1044                               struct ocrdma_dev_attr *attr,
1045                               struct ocrdma_mbx_query_config *rsp)
1046 {
1047         attr->max_pd =
1048             (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1049             OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1050         attr->max_qp =
1051             (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1052             OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1053         attr->max_srq =
1054                 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1055                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1056         attr->max_send_sge = ((rsp->max_write_send_sge &
1057                                OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1058                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1059         attr->max_recv_sge = (rsp->max_write_send_sge &
1060                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1061             OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
1062         attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1063                               OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1064             OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
1065         attr->max_rdma_sge = (rsp->max_write_send_sge &
1066                               OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK) >>
1067             OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT;
1068         attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1069                                 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1070             OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1071         attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1072                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1073             OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1074         attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1075                                     OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1076             OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1077         attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1078                                OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1079             OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1080         attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1081                                     OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1082             OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1083         attr->max_mw = rsp->max_mw;
1084         attr->max_mr = rsp->max_mr;
1085         attr->max_mr_size = ~0ull;
1086         attr->max_fmr = 0;
1087         attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1088         attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1089         attr->max_cqe = rsp->max_cq_cqes_per_cq &
1090                         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1091         attr->max_cq = (rsp->max_cq_cqes_per_cq &
1092                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1093                         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1094         attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1095                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1096                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1097                 OCRDMA_WQE_STRIDE;
1098         attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1099                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1100                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1101                 OCRDMA_WQE_STRIDE;
1102         attr->max_inline_data =
1103             attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1104                               sizeof(struct ocrdma_sge));
1105         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1106                 attr->ird = 1;
1107                 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1108                 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1109         }
1110         dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1111                  OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1112         dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1113                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1114 }
1115
1116 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1117                                    struct ocrdma_fw_conf_rsp *conf)
1118 {
1119         u32 fn_mode;
1120
1121         fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1122         if (fn_mode != OCRDMA_FN_MODE_RDMA)
1123                 return -EINVAL;
1124         dev->base_eqid = conf->base_eqid;
1125         dev->max_eq = conf->max_eq;
1126         return 0;
1127 }
1128
1129 /* can be issued only during init time. */
1130 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1131 {
1132         int status = -ENOMEM;
1133         struct ocrdma_mqe *cmd;
1134         struct ocrdma_fw_ver_rsp *rsp;
1135
1136         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1137         if (!cmd)
1138                 return -ENOMEM;
1139         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1140                         OCRDMA_CMD_GET_FW_VER,
1141                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1142
1143         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1144         if (status)
1145                 goto mbx_err;
1146         rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1147         memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1148         memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1149                sizeof(rsp->running_ver));
1150         ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1151 mbx_err:
1152         kfree(cmd);
1153         return status;
1154 }
1155
1156 /* can be issued only during init time. */
1157 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1158 {
1159         int status = -ENOMEM;
1160         struct ocrdma_mqe *cmd;
1161         struct ocrdma_fw_conf_rsp *rsp;
1162
1163         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1164         if (!cmd)
1165                 return -ENOMEM;
1166         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1167                         OCRDMA_CMD_GET_FW_CONFIG,
1168                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1169         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1170         if (status)
1171                 goto mbx_err;
1172         rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1173         status = ocrdma_check_fw_config(dev, rsp);
1174 mbx_err:
1175         kfree(cmd);
1176         return status;
1177 }
1178
1179 int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1180 {
1181         struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1182         struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1183         struct ocrdma_rdma_stats_resp *old_stats = NULL;
1184         int status;
1185
1186         old_stats = kzalloc(sizeof(*old_stats), GFP_KERNEL);
1187         if (old_stats == NULL)
1188                 return -ENOMEM;
1189
1190         memset(mqe, 0, sizeof(*mqe));
1191         mqe->hdr.pyld_len = dev->stats_mem.size;
1192         mqe->hdr.spcl_sge_cnt_emb |=
1193                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1194                                 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1195         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1196         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1197         mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1198
1199         /* Cache the old stats */
1200         memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1201         memset(req, 0, dev->stats_mem.size);
1202
1203         ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1204                         OCRDMA_CMD_GET_RDMA_STATS,
1205                         OCRDMA_SUBSYS_ROCE,
1206                         dev->stats_mem.size);
1207         if (reset)
1208                 req->reset_stats = reset;
1209
1210         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1211         if (status)
1212                 /* Copy from cache, if mbox fails */
1213                 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1214         else
1215                 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1216
1217         kfree(old_stats);
1218         return status;
1219 }
1220
1221 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1222 {
1223         int status = -ENOMEM;
1224         struct ocrdma_dma_mem dma;
1225         struct ocrdma_mqe *mqe;
1226         struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1227         struct mgmt_hba_attribs *hba_attribs;
1228
1229         mqe = ocrdma_alloc_mqe();
1230         if (!mqe)
1231                 return status;
1232         memset(mqe, 0, sizeof(*mqe));
1233
1234         dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1235         dma.va   = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1236                                         dma.size, &dma.pa, GFP_KERNEL);
1237         if (!dma.va)
1238                 goto free_mqe;
1239
1240         mqe->hdr.pyld_len = dma.size;
1241         mqe->hdr.spcl_sge_cnt_emb |=
1242                         (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1243                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
1244         mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1245         mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1246         mqe->u.nonemb_req.sge[0].len = dma.size;
1247
1248         memset(dma.va, 0, dma.size);
1249         ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1250                         OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1251                         OCRDMA_SUBSYS_COMMON,
1252                         dma.size);
1253
1254         status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1255         if (!status) {
1256                 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1257                 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1258
1259                 dev->hba_port_num = hba_attribs->phy_port;
1260                 strncpy(dev->model_number,
1261                         hba_attribs->controller_model_number, 31);
1262         }
1263         dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1264 free_mqe:
1265         kfree(mqe);
1266         return status;
1267 }
1268
1269 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1270 {
1271         int status = -ENOMEM;
1272         struct ocrdma_mbx_query_config *rsp;
1273         struct ocrdma_mqe *cmd;
1274
1275         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1276         if (!cmd)
1277                 return status;
1278         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1279         if (status)
1280                 goto mbx_err;
1281         rsp = (struct ocrdma_mbx_query_config *)cmd;
1282         ocrdma_get_attr(dev, &dev->attr, rsp);
1283 mbx_err:
1284         kfree(cmd);
1285         return status;
1286 }
1287
1288 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed)
1289 {
1290         int status = -ENOMEM;
1291         struct ocrdma_get_link_speed_rsp *rsp;
1292         struct ocrdma_mqe *cmd;
1293
1294         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1295                                   sizeof(*cmd));
1296         if (!cmd)
1297                 return status;
1298         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1299                         OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1300                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1301
1302         ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1303
1304         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1305         if (status)
1306                 goto mbx_err;
1307
1308         rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1309         *lnk_speed = rsp->phys_port_speed;
1310
1311 mbx_err:
1312         kfree(cmd);
1313         return status;
1314 }
1315
1316 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1317 {
1318         int status = -ENOMEM;
1319         struct ocrdma_mqe *cmd;
1320         struct ocrdma_get_phy_info_rsp *rsp;
1321
1322         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1323         if (!cmd)
1324                 return status;
1325
1326         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1327                         OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1328                         sizeof(*cmd));
1329
1330         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1331         if (status)
1332                 goto mbx_err;
1333
1334         rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1335         dev->phy.phy_type = le16_to_cpu(rsp->phy_type);
1336         dev->phy.auto_speeds_supported  =
1337                         le16_to_cpu(rsp->auto_speeds_supported);
1338         dev->phy.fixed_speeds_supported =
1339                         le16_to_cpu(rsp->fixed_speeds_supported);
1340 mbx_err:
1341         kfree(cmd);
1342         return status;
1343 }
1344
1345 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1346 {
1347         int status = -ENOMEM;
1348         struct ocrdma_alloc_pd *cmd;
1349         struct ocrdma_alloc_pd_rsp *rsp;
1350
1351         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1352         if (!cmd)
1353                 return status;
1354         if (pd->dpp_enabled)
1355                 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1356         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1357         if (status)
1358                 goto mbx_err;
1359         rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1360         pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1361         if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1362                 pd->dpp_enabled = true;
1363                 pd->dpp_page = rsp->dpp_page_pdid >>
1364                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1365         } else {
1366                 pd->dpp_enabled = false;
1367                 pd->num_dpp_qp = 0;
1368         }
1369 mbx_err:
1370         kfree(cmd);
1371         return status;
1372 }
1373
1374 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1375 {
1376         int status = -ENOMEM;
1377         struct ocrdma_dealloc_pd *cmd;
1378
1379         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1380         if (!cmd)
1381                 return status;
1382         cmd->id = pd->id;
1383         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1384         kfree(cmd);
1385         return status;
1386 }
1387
1388 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1389                                int *num_pages, int *page_size)
1390 {
1391         int i;
1392         int mem_size;
1393
1394         *num_entries = roundup_pow_of_two(*num_entries);
1395         mem_size = *num_entries * entry_size;
1396         /* find the possible lowest possible multiplier */
1397         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1398                 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1399                         break;
1400         }
1401         if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1402                 return -EINVAL;
1403         mem_size = roundup(mem_size,
1404                        ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1405         *num_pages =
1406             mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1407         *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1408         *num_entries = mem_size / entry_size;
1409         return 0;
1410 }
1411
1412 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1413 {
1414         int i;
1415         int status = 0;
1416         int max_ah;
1417         struct ocrdma_create_ah_tbl *cmd;
1418         struct ocrdma_create_ah_tbl_rsp *rsp;
1419         struct pci_dev *pdev = dev->nic_info.pdev;
1420         dma_addr_t pa;
1421         struct ocrdma_pbe *pbes;
1422
1423         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1424         if (!cmd)
1425                 return status;
1426
1427         max_ah = OCRDMA_MAX_AH;
1428         dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1429
1430         /* number of PBEs in PBL */
1431         cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1432                                 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1433                                 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1434
1435         /* page size */
1436         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1437                 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1438                         break;
1439         }
1440         cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1441                                 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1442
1443         /* ah_entry size */
1444         cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1445                                 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1446                                 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1447
1448         dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1449                                                 &dev->av_tbl.pbl.pa,
1450                                                 GFP_KERNEL);
1451         if (dev->av_tbl.pbl.va == NULL)
1452                 goto mem_err;
1453
1454         dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1455                                             &pa, GFP_KERNEL);
1456         if (dev->av_tbl.va == NULL)
1457                 goto mem_err_ah;
1458         dev->av_tbl.pa = pa;
1459         dev->av_tbl.num_ah = max_ah;
1460         memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1461
1462         pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1463         for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1464                 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1465                 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1466                 pa += PAGE_SIZE;
1467         }
1468         cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1469         cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1470         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1471         if (status)
1472                 goto mbx_err;
1473         rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1474         dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1475         kfree(cmd);
1476         return 0;
1477
1478 mbx_err:
1479         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1480                           dev->av_tbl.pa);
1481         dev->av_tbl.va = NULL;
1482 mem_err_ah:
1483         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1484                           dev->av_tbl.pbl.pa);
1485         dev->av_tbl.pbl.va = NULL;
1486         dev->av_tbl.size = 0;
1487 mem_err:
1488         kfree(cmd);
1489         return status;
1490 }
1491
1492 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1493 {
1494         struct ocrdma_delete_ah_tbl *cmd;
1495         struct pci_dev *pdev = dev->nic_info.pdev;
1496
1497         if (dev->av_tbl.va == NULL)
1498                 return;
1499
1500         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1501         if (!cmd)
1502                 return;
1503         cmd->ahid = dev->av_tbl.ahid;
1504
1505         ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1506         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1507                           dev->av_tbl.pa);
1508         dev->av_tbl.va = NULL;
1509         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1510                           dev->av_tbl.pbl.pa);
1511         kfree(cmd);
1512 }
1513
1514 /* Multiple CQs uses the EQ. This routine returns least used
1515  * EQ to associate with CQ. This will distributes the interrupt
1516  * processing and CPU load to associated EQ, vector and so to that CPU.
1517  */
1518 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1519 {
1520         int i, selected_eq = 0, cq_cnt = 0;
1521         u16 eq_id;
1522
1523         mutex_lock(&dev->dev_lock);
1524         cq_cnt = dev->eq_tbl[0].cq_cnt;
1525         eq_id = dev->eq_tbl[0].q.id;
1526         /* find the EQ which is has the least number of
1527          * CQs associated with it.
1528          */
1529         for (i = 0; i < dev->eq_cnt; i++) {
1530                 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1531                         cq_cnt = dev->eq_tbl[i].cq_cnt;
1532                         eq_id = dev->eq_tbl[i].q.id;
1533                         selected_eq = i;
1534                 }
1535         }
1536         dev->eq_tbl[selected_eq].cq_cnt += 1;
1537         mutex_unlock(&dev->dev_lock);
1538         return eq_id;
1539 }
1540
1541 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1542 {
1543         int i;
1544
1545         mutex_lock(&dev->dev_lock);
1546         i = ocrdma_get_eq_table_index(dev, eq_id);
1547         if (i == -EINVAL)
1548                 BUG();
1549         dev->eq_tbl[i].cq_cnt -= 1;
1550         mutex_unlock(&dev->dev_lock);
1551 }
1552
1553 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1554                          int entries, int dpp_cq, u16 pd_id)
1555 {
1556         int status = -ENOMEM; int max_hw_cqe;
1557         struct pci_dev *pdev = dev->nic_info.pdev;
1558         struct ocrdma_create_cq *cmd;
1559         struct ocrdma_create_cq_rsp *rsp;
1560         u32 hw_pages, cqe_size, page_size, cqe_count;
1561
1562         if (entries > dev->attr.max_cqe) {
1563                 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1564                        __func__, dev->id, dev->attr.max_cqe, entries);
1565                 return -EINVAL;
1566         }
1567         if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1568                 return -EINVAL;
1569
1570         if (dpp_cq) {
1571                 cq->max_hw_cqe = 1;
1572                 max_hw_cqe = 1;
1573                 cqe_size = OCRDMA_DPP_CQE_SIZE;
1574                 hw_pages = 1;
1575         } else {
1576                 cq->max_hw_cqe = dev->attr.max_cqe;
1577                 max_hw_cqe = dev->attr.max_cqe;
1578                 cqe_size = sizeof(struct ocrdma_cqe);
1579                 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1580         }
1581
1582         cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1583
1584         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1585         if (!cmd)
1586                 return -ENOMEM;
1587         ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1588                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1589         cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1590         if (!cq->va) {
1591                 status = -ENOMEM;
1592                 goto mem_err;
1593         }
1594         memset(cq->va, 0, cq->len);
1595         page_size = cq->len / hw_pages;
1596         cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1597                                         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1598         cmd->cmd.pgsz_pgcnt |= hw_pages;
1599         cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1600
1601         cq->eqn = ocrdma_bind_eq(dev);
1602         cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1603         cqe_count = cq->len / cqe_size;
1604         cq->cqe_cnt = cqe_count;
1605         if (cqe_count > 1024) {
1606                 /* Set cnt to 3 to indicate more than 1024 cq entries */
1607                 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1608         } else {
1609                 u8 count = 0;
1610                 switch (cqe_count) {
1611                 case 256:
1612                         count = 0;
1613                         break;
1614                 case 512:
1615                         count = 1;
1616                         break;
1617                 case 1024:
1618                         count = 2;
1619                         break;
1620                 default:
1621                         goto mbx_err;
1622                 }
1623                 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1624         }
1625         /* shared eq between all the consumer cqs. */
1626         cmd->cmd.eqn = cq->eqn;
1627         if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1628                 if (dpp_cq)
1629                         cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1630                                 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1631                 cq->phase_change = false;
1632                 cmd->cmd.cqe_count = (cq->len / cqe_size);
1633         } else {
1634                 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1635                 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1636                 cq->phase_change = true;
1637         }
1638
1639         cmd->cmd.pd_id = pd_id; /* valid only for v3 */
1640         ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1641         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1642         if (status)
1643                 goto mbx_err;
1644
1645         rsp = (struct ocrdma_create_cq_rsp *)cmd;
1646         cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1647         kfree(cmd);
1648         return 0;
1649 mbx_err:
1650         ocrdma_unbind_eq(dev, cq->eqn);
1651         dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1652 mem_err:
1653         kfree(cmd);
1654         return status;
1655 }
1656
1657 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1658 {
1659         int status = -ENOMEM;
1660         struct ocrdma_destroy_cq *cmd;
1661
1662         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1663         if (!cmd)
1664                 return status;
1665         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1666                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1667
1668         cmd->bypass_flush_qid |=
1669             (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1670             OCRDMA_DESTROY_CQ_QID_MASK;
1671
1672         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1673         ocrdma_unbind_eq(dev, cq->eqn);
1674         dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1675         kfree(cmd);
1676         return status;
1677 }
1678
1679 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1680                           u32 pdid, int addr_check)
1681 {
1682         int status = -ENOMEM;
1683         struct ocrdma_alloc_lkey *cmd;
1684         struct ocrdma_alloc_lkey_rsp *rsp;
1685
1686         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1687         if (!cmd)
1688                 return status;
1689         cmd->pdid = pdid;
1690         cmd->pbl_sz_flags |= addr_check;
1691         cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1692         cmd->pbl_sz_flags |=
1693             (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1694         cmd->pbl_sz_flags |=
1695             (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1696         cmd->pbl_sz_flags |=
1697             (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1698         cmd->pbl_sz_flags |=
1699             (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1700         cmd->pbl_sz_flags |=
1701             (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1702
1703         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1704         if (status)
1705                 goto mbx_err;
1706         rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1707         hwmr->lkey = rsp->lrkey;
1708 mbx_err:
1709         kfree(cmd);
1710         return status;
1711 }
1712
1713 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1714 {
1715         int status = -ENOMEM;
1716         struct ocrdma_dealloc_lkey *cmd;
1717
1718         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1719         if (!cmd)
1720                 return -ENOMEM;
1721         cmd->lkey = lkey;
1722         cmd->rsvd_frmr = fr_mr ? 1 : 0;
1723         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1724         if (status)
1725                 goto mbx_err;
1726 mbx_err:
1727         kfree(cmd);
1728         return status;
1729 }
1730
1731 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1732                              u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1733 {
1734         int status = -ENOMEM;
1735         int i;
1736         struct ocrdma_reg_nsmr *cmd;
1737         struct ocrdma_reg_nsmr_rsp *rsp;
1738
1739         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1740         if (!cmd)
1741                 return -ENOMEM;
1742         cmd->num_pbl_pdid =
1743             pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1744         cmd->fr_mr = hwmr->fr_mr;
1745
1746         cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1747                                     OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1748         cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1749                                     OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1750         cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1751                                     OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1752         cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1753                                     OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1754         cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1755                                     OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1756         cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1757
1758         cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1759         cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1760                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1761         cmd->totlen_low = hwmr->len;
1762         cmd->totlen_high = upper_32_bits(hwmr->len);
1763         cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1764         cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1765         cmd->va_loaddr = (u32) hwmr->va;
1766         cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1767
1768         for (i = 0; i < pbl_cnt; i++) {
1769                 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1770                 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1771         }
1772         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1773         if (status)
1774                 goto mbx_err;
1775         rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1776         hwmr->lkey = rsp->lrkey;
1777 mbx_err:
1778         kfree(cmd);
1779         return status;
1780 }
1781
1782 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1783                                   struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1784                                   u32 pbl_offset, u32 last)
1785 {
1786         int status = -ENOMEM;
1787         int i;
1788         struct ocrdma_reg_nsmr_cont *cmd;
1789
1790         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1791         if (!cmd)
1792                 return -ENOMEM;
1793         cmd->lrkey = hwmr->lkey;
1794         cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1795             (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1796         cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1797
1798         for (i = 0; i < pbl_cnt; i++) {
1799                 cmd->pbl[i].lo =
1800                     (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1801                 cmd->pbl[i].hi =
1802                     upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1803         }
1804         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1805         if (status)
1806                 goto mbx_err;
1807 mbx_err:
1808         kfree(cmd);
1809         return status;
1810 }
1811
1812 int ocrdma_reg_mr(struct ocrdma_dev *dev,
1813                   struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1814 {
1815         int status;
1816         u32 last = 0;
1817         u32 cur_pbl_cnt, pbl_offset;
1818         u32 pending_pbl_cnt = hwmr->num_pbls;
1819
1820         pbl_offset = 0;
1821         cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1822         if (cur_pbl_cnt == pending_pbl_cnt)
1823                 last = 1;
1824
1825         status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1826                                    cur_pbl_cnt, hwmr->pbe_size, last);
1827         if (status) {
1828                 pr_err("%s() status=%d\n", __func__, status);
1829                 return status;
1830         }
1831         /* if there is no more pbls to register then exit. */
1832         if (last)
1833                 return 0;
1834
1835         while (!last) {
1836                 pbl_offset += cur_pbl_cnt;
1837                 pending_pbl_cnt -= cur_pbl_cnt;
1838                 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1839                 /* if we reach the end of the pbls, then need to set the last
1840                  * bit, indicating no more pbls to register for this memory key.
1841                  */
1842                 if (cur_pbl_cnt == pending_pbl_cnt)
1843                         last = 1;
1844
1845                 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1846                                                 pbl_offset, last);
1847                 if (status)
1848                         break;
1849         }
1850         if (status)
1851                 pr_err("%s() err. status=%d\n", __func__, status);
1852
1853         return status;
1854 }
1855
1856 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1857 {
1858         struct ocrdma_qp *tmp;
1859         bool found = false;
1860         list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1861                 if (qp == tmp) {
1862                         found = true;
1863                         break;
1864                 }
1865         }
1866         return found;
1867 }
1868
1869 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1870 {
1871         struct ocrdma_qp *tmp;
1872         bool found = false;
1873         list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1874                 if (qp == tmp) {
1875                         found = true;
1876                         break;
1877                 }
1878         }
1879         return found;
1880 }
1881
1882 void ocrdma_flush_qp(struct ocrdma_qp *qp)
1883 {
1884         bool found;
1885         unsigned long flags;
1886
1887         spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1888         found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1889         if (!found)
1890                 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1891         if (!qp->srq) {
1892                 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1893                 if (!found)
1894                         list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1895         }
1896         spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1897 }
1898
1899 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
1900 {
1901         qp->sq.head = 0;
1902         qp->sq.tail = 0;
1903         qp->rq.head = 0;
1904         qp->rq.tail = 0;
1905 }
1906
1907 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1908                            enum ib_qp_state *old_ib_state)
1909 {
1910         unsigned long flags;
1911         int status = 0;
1912         enum ocrdma_qp_state new_state;
1913         new_state = get_ocrdma_qp_state(new_ib_state);
1914
1915         /* sync with wqe and rqe posting */
1916         spin_lock_irqsave(&qp->q_lock, flags);
1917
1918         if (old_ib_state)
1919                 *old_ib_state = get_ibqp_state(qp->state);
1920         if (new_state == qp->state) {
1921                 spin_unlock_irqrestore(&qp->q_lock, flags);
1922                 return 1;
1923         }
1924
1925
1926         if (new_state == OCRDMA_QPS_INIT) {
1927                 ocrdma_init_hwq_ptr(qp);
1928                 ocrdma_del_flush_qp(qp);
1929         } else if (new_state == OCRDMA_QPS_ERR) {
1930                 ocrdma_flush_qp(qp);
1931         }
1932
1933         qp->state = new_state;
1934
1935         spin_unlock_irqrestore(&qp->q_lock, flags);
1936         return status;
1937 }
1938
1939 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1940 {
1941         u32 flags = 0;
1942         if (qp->cap_flags & OCRDMA_QP_INB_RD)
1943                 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1944         if (qp->cap_flags & OCRDMA_QP_INB_WR)
1945                 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1946         if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1947                 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1948         if (qp->cap_flags & OCRDMA_QP_LKEY0)
1949                 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1950         if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1951                 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1952         return flags;
1953 }
1954
1955 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1956                                         struct ib_qp_init_attr *attrs,
1957                                         struct ocrdma_qp *qp)
1958 {
1959         int status;
1960         u32 len, hw_pages, hw_page_size;
1961         dma_addr_t pa;
1962         struct ocrdma_dev *dev = qp->dev;
1963         struct pci_dev *pdev = dev->nic_info.pdev;
1964         u32 max_wqe_allocated;
1965         u32 max_sges = attrs->cap.max_send_sge;
1966
1967         /* QP1 may exceed 127 */
1968         max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
1969                                 dev->attr.max_wqe);
1970
1971         status = ocrdma_build_q_conf(&max_wqe_allocated,
1972                 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1973         if (status) {
1974                 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
1975                        max_wqe_allocated);
1976                 return -EINVAL;
1977         }
1978         qp->sq.max_cnt = max_wqe_allocated;
1979         len = (hw_pages * hw_page_size);
1980
1981         qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1982         if (!qp->sq.va)
1983                 return -EINVAL;
1984         memset(qp->sq.va, 0, len);
1985         qp->sq.len = len;
1986         qp->sq.pa = pa;
1987         qp->sq.entry_size = dev->attr.wqe_size;
1988         ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1989
1990         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1991                                 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1992         cmd->num_wq_rq_pages |= (hw_pages <<
1993                                  OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
1994             OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
1995         cmd->max_sge_send_write |= (max_sges <<
1996                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
1997             OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
1998         cmd->max_sge_send_write |= (max_sges <<
1999                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2000                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2001         cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2002                              OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2003                                 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2004         cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2005                               OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2006                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2007         return 0;
2008 }
2009
2010 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2011                                         struct ib_qp_init_attr *attrs,
2012                                         struct ocrdma_qp *qp)
2013 {
2014         int status;
2015         u32 len, hw_pages, hw_page_size;
2016         dma_addr_t pa = 0;
2017         struct ocrdma_dev *dev = qp->dev;
2018         struct pci_dev *pdev = dev->nic_info.pdev;
2019         u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2020
2021         status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2022                                      &hw_pages, &hw_page_size);
2023         if (status) {
2024                 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2025                        attrs->cap.max_recv_wr + 1);
2026                 return status;
2027         }
2028         qp->rq.max_cnt = max_rqe_allocated;
2029         len = (hw_pages * hw_page_size);
2030
2031         qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2032         if (!qp->rq.va)
2033                 return -ENOMEM;
2034         memset(qp->rq.va, 0, len);
2035         qp->rq.pa = pa;
2036         qp->rq.len = len;
2037         qp->rq.entry_size = dev->attr.rqe_size;
2038
2039         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2040         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2041                 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2042         cmd->num_wq_rq_pages |=
2043             (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2044             OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2045         cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2046                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2047                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2048         cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2049                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2050                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2051         cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2052                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2053                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2054         return 0;
2055 }
2056
2057 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2058                                          struct ocrdma_pd *pd,
2059                                          struct ocrdma_qp *qp,
2060                                          u8 enable_dpp_cq, u16 dpp_cq_id)
2061 {
2062         pd->num_dpp_qp--;
2063         qp->dpp_enabled = true;
2064         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2065         if (!enable_dpp_cq)
2066                 return;
2067         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2068         cmd->dpp_credits_cqid = dpp_cq_id;
2069         cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2070                                         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2071 }
2072
2073 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2074                                         struct ocrdma_qp *qp)
2075 {
2076         struct ocrdma_dev *dev = qp->dev;
2077         struct pci_dev *pdev = dev->nic_info.pdev;
2078         dma_addr_t pa = 0;
2079         int ird_page_size = dev->attr.ird_page_size;
2080         int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
2081         struct ocrdma_hdr_wqe *rqe;
2082         int i  = 0;
2083
2084         if (dev->attr.ird == 0)
2085                 return 0;
2086
2087         qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
2088                                         &pa, GFP_KERNEL);
2089         if (!qp->ird_q_va)
2090                 return -ENOMEM;
2091         memset(qp->ird_q_va, 0, ird_q_len);
2092         ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2093                              pa, ird_page_size);
2094         for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2095                 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2096                         (i * dev->attr.rqe_size));
2097                 rqe->cw = 0;
2098                 rqe->cw |= 2;
2099                 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2100                 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2101                 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2102         }
2103         return 0;
2104 }
2105
2106 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2107                                      struct ocrdma_qp *qp,
2108                                      struct ib_qp_init_attr *attrs,
2109                                      u16 *dpp_offset, u16 *dpp_credit_lmt)
2110 {
2111         u32 max_wqe_allocated, max_rqe_allocated;
2112         qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2113         qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2114         qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2115         qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2116         qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2117         qp->dpp_enabled = false;
2118         if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2119                 qp->dpp_enabled = true;
2120                 *dpp_credit_lmt = (rsp->dpp_response &
2121                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2122                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2123                 *dpp_offset = (rsp->dpp_response &
2124                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2125                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2126         }
2127         max_wqe_allocated =
2128                 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2129         max_wqe_allocated = 1 << max_wqe_allocated;
2130         max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2131
2132         qp->sq.max_cnt = max_wqe_allocated;
2133         qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2134
2135         if (!attrs->srq) {
2136                 qp->rq.max_cnt = max_rqe_allocated;
2137                 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
2138         }
2139 }
2140
2141 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2142                          u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2143                          u16 *dpp_credit_lmt)
2144 {
2145         int status = -ENOMEM;
2146         u32 flags = 0;
2147         struct ocrdma_dev *dev = qp->dev;
2148         struct ocrdma_pd *pd = qp->pd;
2149         struct pci_dev *pdev = dev->nic_info.pdev;
2150         struct ocrdma_cq *cq;
2151         struct ocrdma_create_qp_req *cmd;
2152         struct ocrdma_create_qp_rsp *rsp;
2153         int qptype;
2154
2155         switch (attrs->qp_type) {
2156         case IB_QPT_GSI:
2157                 qptype = OCRDMA_QPT_GSI;
2158                 break;
2159         case IB_QPT_RC:
2160                 qptype = OCRDMA_QPT_RC;
2161                 break;
2162         case IB_QPT_UD:
2163                 qptype = OCRDMA_QPT_UD;
2164                 break;
2165         default:
2166                 return -EINVAL;
2167         }
2168
2169         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2170         if (!cmd)
2171                 return status;
2172         cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2173                                                 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2174         status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2175         if (status)
2176                 goto sq_err;
2177
2178         if (attrs->srq) {
2179                 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2180                 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2181                 cmd->rq_addr[0].lo = srq->id;
2182                 qp->srq = srq;
2183         } else {
2184                 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2185                 if (status)
2186                         goto rq_err;
2187         }
2188
2189         status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2190         if (status)
2191                 goto mbx_err;
2192
2193         cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2194                                 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2195
2196         flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2197
2198         cmd->max_sge_recv_flags |= flags;
2199         cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2200                              OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2201                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2202         cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2203                              OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2204                                 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2205         cq = get_ocrdma_cq(attrs->send_cq);
2206         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2207                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2208         qp->sq_cq = cq;
2209         cq = get_ocrdma_cq(attrs->recv_cq);
2210         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2211                                 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2212         qp->rq_cq = cq;
2213
2214         if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2215             (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2216                 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2217                                              dpp_cq_id);
2218         }
2219
2220         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2221         if (status)
2222                 goto mbx_err;
2223         rsp = (struct ocrdma_create_qp_rsp *)cmd;
2224         ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2225         qp->state = OCRDMA_QPS_RST;
2226         kfree(cmd);
2227         return 0;
2228 mbx_err:
2229         if (qp->rq.va)
2230                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2231 rq_err:
2232         pr_err("%s(%d) rq_err\n", __func__, dev->id);
2233         dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2234 sq_err:
2235         pr_err("%s(%d) sq_err\n", __func__, dev->id);
2236         kfree(cmd);
2237         return status;
2238 }
2239
2240 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2241                         struct ocrdma_qp_params *param)
2242 {
2243         int status = -ENOMEM;
2244         struct ocrdma_query_qp *cmd;
2245         struct ocrdma_query_qp_rsp *rsp;
2246
2247         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2248         if (!cmd)
2249                 return status;
2250         cmd->qp_id = qp->id;
2251         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2252         if (status)
2253                 goto mbx_err;
2254         rsp = (struct ocrdma_query_qp_rsp *)cmd;
2255         memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2256 mbx_err:
2257         kfree(cmd);
2258         return status;
2259 }
2260
2261 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2262                                 struct ocrdma_modify_qp *cmd,
2263                                 struct ib_qp_attr *attrs)
2264 {
2265         int status;
2266         struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2267         union ib_gid sgid, zgid;
2268         u32 vlan_id;
2269         u8 mac_addr[6];
2270
2271         if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2272                 return -EINVAL;
2273         if (atomic_cmpxchg(&qp->dev->update_sl, 1, 0))
2274                 ocrdma_init_service_level(qp->dev);
2275         cmd->params.tclass_sq_psn |=
2276             (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2277         cmd->params.rnt_rc_sl_fl |=
2278             (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2279         cmd->params.rnt_rc_sl_fl |= (ah_attr->sl << OCRDMA_QP_PARAMS_SL_SHIFT);
2280         cmd->params.hop_lmt_rq_psn |=
2281             (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2282         cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2283         memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2284                sizeof(cmd->params.dgid));
2285         status = ocrdma_query_gid(&qp->dev->ibdev, 1,
2286                         ah_attr->grh.sgid_index, &sgid);
2287         if (status)
2288                 return status;
2289
2290         memset(&zgid, 0, sizeof(zgid));
2291         if (!memcmp(&sgid, &zgid, sizeof(zgid)))
2292                 return -EINVAL;
2293
2294         qp->sgid_idx = ah_attr->grh.sgid_index;
2295         memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2296         ocrdma_resolve_dmac(qp->dev, ah_attr, &mac_addr[0]);
2297         cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2298                                 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2299         /* convert them to LE format. */
2300         ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2301         ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2302         cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2303         vlan_id = ah_attr->vlan_id;
2304         if (vlan_id && (vlan_id < 0x1000)) {
2305                 cmd->params.vlan_dmac_b4_to_b5 |=
2306                     vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2307                 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2308                 /* override the sl with default priority if 0 */
2309                 cmd->params.rnt_rc_sl_fl |=
2310                         (ah_attr->sl ? ah_attr->sl :
2311                                 qp->dev->sl) << OCRDMA_QP_PARAMS_SL_SHIFT;
2312         }
2313         return 0;
2314 }
2315
2316 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2317                                 struct ocrdma_modify_qp *cmd,
2318                                 struct ib_qp_attr *attrs, int attr_mask)
2319 {
2320         int status = 0;
2321
2322         if (attr_mask & IB_QP_PKEY_INDEX) {
2323                 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2324                                             OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2325                 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2326         }
2327         if (attr_mask & IB_QP_QKEY) {
2328                 qp->qkey = attrs->qkey;
2329                 cmd->params.qkey = attrs->qkey;
2330                 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2331         }
2332         if (attr_mask & IB_QP_AV) {
2333                 status = ocrdma_set_av_params(qp, cmd, attrs);
2334                 if (status)
2335                         return status;
2336         } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2337                 /* set the default mac address for UD, GSI QPs */
2338                 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2339                         (qp->dev->nic_info.mac_addr[1] << 8) |
2340                         (qp->dev->nic_info.mac_addr[2] << 16) |
2341                         (qp->dev->nic_info.mac_addr[3] << 24);
2342                 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2343                                         (qp->dev->nic_info.mac_addr[5] << 8);
2344         }
2345         if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2346             attrs->en_sqd_async_notify) {
2347                 cmd->params.max_sge_recv_flags |=
2348                         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2349                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2350         }
2351         if (attr_mask & IB_QP_DEST_QPN) {
2352                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2353                                 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2354                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2355         }
2356         if (attr_mask & IB_QP_PATH_MTU) {
2357                 if (attrs->path_mtu < IB_MTU_256 ||
2358                     attrs->path_mtu > IB_MTU_4096) {
2359                         status = -EINVAL;
2360                         goto pmtu_err;
2361                 }
2362                 cmd->params.path_mtu_pkey_indx |=
2363                     (ib_mtu_enum_to_int(attrs->path_mtu) <<
2364                      OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2365                     OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2366                 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2367         }
2368         if (attr_mask & IB_QP_TIMEOUT) {
2369                 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2370                     OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2371                 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2372         }
2373         if (attr_mask & IB_QP_RETRY_CNT) {
2374                 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2375                                       OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2376                     OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2377                 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2378         }
2379         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2380                 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2381                                       OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2382                     OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2383                 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2384         }
2385         if (attr_mask & IB_QP_RNR_RETRY) {
2386                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2387                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2388                         & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2389                 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2390         }
2391         if (attr_mask & IB_QP_SQ_PSN) {
2392                 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2393                 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2394         }
2395         if (attr_mask & IB_QP_RQ_PSN) {
2396                 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2397                 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2398         }
2399         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2400                 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2401                         status = -EINVAL;
2402                         goto pmtu_err;
2403                 }
2404                 qp->max_ord = attrs->max_rd_atomic;
2405                 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2406         }
2407         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2408                 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2409                         status = -EINVAL;
2410                         goto pmtu_err;
2411                 }
2412                 qp->max_ird = attrs->max_dest_rd_atomic;
2413                 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2414         }
2415         cmd->params.max_ord_ird = (qp->max_ord <<
2416                                 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2417                                 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2418 pmtu_err:
2419         return status;
2420 }
2421
2422 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2423                          struct ib_qp_attr *attrs, int attr_mask)
2424 {
2425         int status = -ENOMEM;
2426         struct ocrdma_modify_qp *cmd;
2427
2428         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2429         if (!cmd)
2430                 return status;
2431
2432         cmd->params.id = qp->id;
2433         cmd->flags = 0;
2434         if (attr_mask & IB_QP_STATE) {
2435                 cmd->params.max_sge_recv_flags |=
2436                     (get_ocrdma_qp_state(attrs->qp_state) <<
2437                      OCRDMA_QP_PARAMS_STATE_SHIFT) &
2438                     OCRDMA_QP_PARAMS_STATE_MASK;
2439                 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2440         } else {
2441                 cmd->params.max_sge_recv_flags |=
2442                     (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2443                     OCRDMA_QP_PARAMS_STATE_MASK;
2444         }
2445
2446         status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2447         if (status)
2448                 goto mbx_err;
2449         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2450         if (status)
2451                 goto mbx_err;
2452
2453 mbx_err:
2454         kfree(cmd);
2455         return status;
2456 }
2457
2458 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2459 {
2460         int status = -ENOMEM;
2461         struct ocrdma_destroy_qp *cmd;
2462         struct pci_dev *pdev = dev->nic_info.pdev;
2463
2464         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2465         if (!cmd)
2466                 return status;
2467         cmd->qp_id = qp->id;
2468         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2469         if (status)
2470                 goto mbx_err;
2471
2472 mbx_err:
2473         kfree(cmd);
2474         if (qp->sq.va)
2475                 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2476         if (!qp->srq && qp->rq.va)
2477                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2478         if (qp->dpp_enabled)
2479                 qp->pd->num_dpp_qp++;
2480         return status;
2481 }
2482
2483 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2484                           struct ib_srq_init_attr *srq_attr,
2485                           struct ocrdma_pd *pd)
2486 {
2487         int status = -ENOMEM;
2488         int hw_pages, hw_page_size;
2489         int len;
2490         struct ocrdma_create_srq_rsp *rsp;
2491         struct ocrdma_create_srq *cmd;
2492         dma_addr_t pa;
2493         struct pci_dev *pdev = dev->nic_info.pdev;
2494         u32 max_rqe_allocated;
2495
2496         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2497         if (!cmd)
2498                 return status;
2499
2500         cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2501         max_rqe_allocated = srq_attr->attr.max_wr + 1;
2502         status = ocrdma_build_q_conf(&max_rqe_allocated,
2503                                 dev->attr.rqe_size,
2504                                 &hw_pages, &hw_page_size);
2505         if (status) {
2506                 pr_err("%s() req. max_wr=0x%x\n", __func__,
2507                        srq_attr->attr.max_wr);
2508                 status = -EINVAL;
2509                 goto ret;
2510         }
2511         len = hw_pages * hw_page_size;
2512         srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2513         if (!srq->rq.va) {
2514                 status = -ENOMEM;
2515                 goto ret;
2516         }
2517         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2518
2519         srq->rq.entry_size = dev->attr.rqe_size;
2520         srq->rq.pa = pa;
2521         srq->rq.len = len;
2522         srq->rq.max_cnt = max_rqe_allocated;
2523
2524         cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2525         cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2526                                 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2527
2528         cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2529                 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2530         cmd->pages_rqe_sz |= (dev->attr.rqe_size
2531                 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2532                 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2533         cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2534
2535         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2536         if (status)
2537                 goto mbx_err;
2538         rsp = (struct ocrdma_create_srq_rsp *)cmd;
2539         srq->id = rsp->id;
2540         srq->rq.dbid = rsp->id;
2541         max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2542                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2543                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2544         max_rqe_allocated = (1 << max_rqe_allocated);
2545         srq->rq.max_cnt = max_rqe_allocated;
2546         srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2547         srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2548                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2549                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2550         goto ret;
2551 mbx_err:
2552         dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2553 ret:
2554         kfree(cmd);
2555         return status;
2556 }
2557
2558 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2559 {
2560         int status = -ENOMEM;
2561         struct ocrdma_modify_srq *cmd;
2562         struct ocrdma_pd *pd = srq->pd;
2563         struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2564
2565         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2566         if (!cmd)
2567                 return status;
2568         cmd->id = srq->id;
2569         cmd->limit_max_rqe |= srq_attr->srq_limit <<
2570             OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2571         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2572         kfree(cmd);
2573         return status;
2574 }
2575
2576 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2577 {
2578         int status = -ENOMEM;
2579         struct ocrdma_query_srq *cmd;
2580         struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2581
2582         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2583         if (!cmd)
2584                 return status;
2585         cmd->id = srq->rq.dbid;
2586         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2587         if (status == 0) {
2588                 struct ocrdma_query_srq_rsp *rsp =
2589                     (struct ocrdma_query_srq_rsp *)cmd;
2590                 srq_attr->max_sge =
2591                     rsp->srq_lmt_max_sge &
2592                     OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2593                 srq_attr->max_wr =
2594                     rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2595                 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2596                     OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2597         }
2598         kfree(cmd);
2599         return status;
2600 }
2601
2602 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2603 {
2604         int status = -ENOMEM;
2605         struct ocrdma_destroy_srq *cmd;
2606         struct pci_dev *pdev = dev->nic_info.pdev;
2607         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2608         if (!cmd)
2609                 return status;
2610         cmd->id = srq->id;
2611         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2612         if (srq->rq.va)
2613                 dma_free_coherent(&pdev->dev, srq->rq.len,
2614                                   srq->rq.va, srq->rq.pa);
2615         kfree(cmd);
2616         return status;
2617 }
2618
2619 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2620                                       struct ocrdma_dcbx_cfg *dcbxcfg)
2621 {
2622         int status = 0;
2623         dma_addr_t pa;
2624         struct ocrdma_mqe cmd;
2625
2626         struct ocrdma_get_dcbx_cfg_req *req = NULL;
2627         struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2628         struct pci_dev *pdev = dev->nic_info.pdev;
2629         struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2630
2631         memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2632         cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2633                                         sizeof(struct ocrdma_get_dcbx_cfg_req));
2634         req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2635         if (!req) {
2636                 status = -ENOMEM;
2637                 goto mem_err;
2638         }
2639
2640         cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2641                                         OCRDMA_MQE_HDR_SGE_CNT_MASK;
2642         mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2643         mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2644         mqe_sge->len = cmd.hdr.pyld_len;
2645
2646         memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2647         ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2648                         OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2649         req->param_type = ptype;
2650
2651         status = ocrdma_mbx_cmd(dev, &cmd);
2652         if (status)
2653                 goto mbx_err;
2654
2655         rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2656         ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2657         memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2658
2659 mbx_err:
2660         dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2661 mem_err:
2662         return status;
2663 }
2664
2665 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX  0x08
2666 #define OCRDMA_DEFAULT_SERVICE_LEVEL    0x05
2667
2668 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2669                                     struct ocrdma_dcbx_cfg *dcbxcfg,
2670                                     u8 *srvc_lvl)
2671 {
2672         int status = -EINVAL, indx, slindx;
2673         int ventry_cnt;
2674         struct ocrdma_app_parameter *app_param;
2675         u8 valid, proto_sel;
2676         u8 app_prio, pfc_prio;
2677         u16 proto;
2678
2679         if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2680                 pr_info("%s ocrdma%d DCBX is disabled\n",
2681                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2682                 goto out;
2683         }
2684
2685         if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2686                 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2687                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2688                         (ptype > 0 ? "operational" : "admin"),
2689                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2690                         "enabled" : "disabled",
2691                         (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2692                         "" : ", not sync'ed");
2693                 goto out;
2694         } else {
2695                 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2696                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2697         }
2698
2699         ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2700                                 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2701                                 & OCRDMA_DCBX_STATE_MASK;
2702
2703         for (indx = 0; indx < ventry_cnt; indx++) {
2704                 app_param = &dcbxcfg->app_param[indx];
2705                 valid = (app_param->valid_proto_app >>
2706                                 OCRDMA_APP_PARAM_VALID_SHIFT)
2707                                 & OCRDMA_APP_PARAM_VALID_MASK;
2708                 proto_sel = (app_param->valid_proto_app
2709                                 >>  OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2710                                 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2711                 proto = app_param->valid_proto_app &
2712                                 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2713
2714                 if (
2715                         valid && proto == OCRDMA_APP_PROTO_ROCE &&
2716                         proto_sel == OCRDMA_PROTO_SELECT_L2) {
2717                         for (slindx = 0; slindx <
2718                                 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2719                                 app_prio = ocrdma_get_app_prio(
2720                                                 (u8 *)app_param->app_prio,
2721                                                 slindx);
2722                                 pfc_prio = ocrdma_get_pfc_prio(
2723                                                 (u8 *)dcbxcfg->pfc_prio,
2724                                                 slindx);
2725
2726                                 if (app_prio && pfc_prio) {
2727                                         *srvc_lvl = slindx;
2728                                         status = 0;
2729                                         goto out;
2730                                 }
2731                         }
2732                         if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
2733                                 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2734                                         dev_name(&dev->nic_info.pdev->dev),
2735                                         dev->id, proto);
2736                         }
2737                 }
2738         }
2739
2740 out:
2741         return status;
2742 }
2743
2744 void ocrdma_init_service_level(struct ocrdma_dev *dev)
2745 {
2746         int status = 0, indx;
2747         struct ocrdma_dcbx_cfg dcbxcfg;
2748         u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
2749         int ptype = OCRDMA_PARAMETER_TYPE_OPER;
2750
2751         for (indx = 0; indx < 2; indx++) {
2752                 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
2753                 if (status) {
2754                         pr_err("%s(): status=%d\n", __func__, status);
2755                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2756                         continue;
2757                 }
2758
2759                 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
2760                                                   &dcbxcfg, &srvc_lvl);
2761                 if (status) {
2762                         ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
2763                         continue;
2764                 }
2765
2766                 break;
2767         }
2768
2769         if (status)
2770                 pr_info("%s ocrdma%d service level default\n",
2771                         dev_name(&dev->nic_info.pdev->dev), dev->id);
2772         else
2773                 pr_info("%s ocrdma%d service level %d\n",
2774                         dev_name(&dev->nic_info.pdev->dev), dev->id,
2775                         srvc_lvl);
2776
2777         dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
2778         dev->sl = srvc_lvl;
2779 }
2780
2781 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2782 {
2783         int i;
2784         int status = -EINVAL;
2785         struct ocrdma_av *av;
2786         unsigned long flags;
2787
2788         av = dev->av_tbl.va;
2789         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2790         for (i = 0; i < dev->av_tbl.num_ah; i++) {
2791                 if (av->valid == 0) {
2792                         av->valid = OCRDMA_AV_VALID;
2793                         ah->av = av;
2794                         ah->id = i;
2795                         status = 0;
2796                         break;
2797                 }
2798                 av++;
2799         }
2800         if (i == dev->av_tbl.num_ah)
2801                 status = -EAGAIN;
2802         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2803         return status;
2804 }
2805
2806 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2807 {
2808         unsigned long flags;
2809         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2810         ah->av->valid = 0;
2811         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2812         return 0;
2813 }
2814
2815 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
2816 {
2817         int num_eq, i, status = 0;
2818         int irq;
2819         unsigned long flags = 0;
2820
2821         num_eq = dev->nic_info.msix.num_vectors -
2822                         dev->nic_info.msix.start_vector;
2823         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2824                 num_eq = 1;
2825                 flags = IRQF_SHARED;
2826         } else {
2827                 num_eq = min_t(u32, num_eq, num_online_cpus());
2828         }
2829
2830         if (!num_eq)
2831                 return -EINVAL;
2832
2833         dev->eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2834         if (!dev->eq_tbl)
2835                 return -ENOMEM;
2836
2837         for (i = 0; i < num_eq; i++) {
2838                 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
2839                                         OCRDMA_EQ_LEN);
2840                 if (status) {
2841                         status = -EINVAL;
2842                         break;
2843                 }
2844                 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
2845                         dev->id, i);
2846                 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
2847                 status = request_irq(irq, ocrdma_irq_handler, flags,
2848                                      dev->eq_tbl[i].irq_name,
2849                                      &dev->eq_tbl[i]);
2850                 if (status)
2851                         goto done;
2852                 dev->eq_cnt += 1;
2853         }
2854         /* one eq is sufficient for data path to work */
2855         return 0;
2856 done:
2857         ocrdma_destroy_eqs(dev);
2858         return status;
2859 }
2860
2861 int ocrdma_init_hw(struct ocrdma_dev *dev)
2862 {
2863         int status;
2864
2865         /* create the eqs  */
2866         status = ocrdma_create_eqs(dev);
2867         if (status)
2868                 goto qpeq_err;
2869         status = ocrdma_create_mq(dev);
2870         if (status)
2871                 goto mq_err;
2872         status = ocrdma_mbx_query_fw_config(dev);
2873         if (status)
2874                 goto conf_err;
2875         status = ocrdma_mbx_query_dev(dev);
2876         if (status)
2877                 goto conf_err;
2878         status = ocrdma_mbx_query_fw_ver(dev);
2879         if (status)
2880                 goto conf_err;
2881         status = ocrdma_mbx_create_ah_tbl(dev);
2882         if (status)
2883                 goto conf_err;
2884         status = ocrdma_mbx_get_phy_info(dev);
2885         if (status)
2886                 goto info_attrb_err;
2887         status = ocrdma_mbx_get_ctrl_attribs(dev);
2888         if (status)
2889                 goto info_attrb_err;
2890
2891         return 0;
2892
2893 info_attrb_err:
2894         ocrdma_mbx_delete_ah_tbl(dev);
2895 conf_err:
2896         ocrdma_destroy_mq(dev);
2897 mq_err:
2898         ocrdma_destroy_eqs(dev);
2899 qpeq_err:
2900         pr_err("%s() status=%d\n", __func__, status);
2901         return status;
2902 }
2903
2904 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2905 {
2906         ocrdma_mbx_delete_ah_tbl(dev);
2907
2908         /* cleanup the eqs */
2909         ocrdma_destroy_eqs(dev);
2910
2911         /* cleanup the control path */
2912         ocrdma_destroy_mq(dev);
2913 }