2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
41 /* not supported currently */
42 static int wq_signature;
45 MLX5_IB_ACK_REQ_FREQ = 8,
49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
51 MLX5_IB_LINK_TYPE_IB = 0,
52 MLX5_IB_LINK_TYPE_ETH = 1
56 MLX5_IB_SQ_STRIDE = 6,
57 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
60 static const u32 mlx5_ib_opcode[] = {
61 [IB_WR_SEND] = MLX5_OPCODE_SEND,
62 [IB_WR_LSO] = MLX5_OPCODE_LSO,
63 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
64 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
65 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
66 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
67 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
68 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
69 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
70 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
71 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
72 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
73 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
74 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
77 struct mlx5_wqe_eth_pad {
81 enum raw_qp_set_mask_map {
82 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
83 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
86 struct mlx5_modify_raw_qp_param {
89 u32 set_mask; /* raw_qp_set_mask_map */
91 struct mlx5_rate_limit rl;
96 static void get_cqs(enum ib_qp_type qp_type,
97 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
98 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
100 static int is_qp0(enum ib_qp_type qp_type)
102 return qp_type == IB_QPT_SMI;
105 static int is_sqp(enum ib_qp_type qp_type)
107 return is_qp0(qp_type) || is_qp1(qp_type);
110 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
112 return mlx5_buf_offset(&qp->buf, offset);
115 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
117 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
120 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
122 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
126 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
128 * @qp: QP to copy from.
129 * @send: copy from the send queue when non-zero, use the receive queue
131 * @wqe_index: index to start copying from. For send work queues, the
132 * wqe_index is in units of MLX5_SEND_WQE_BB.
133 * For receive work queue, it is the number of work queue
134 * element in the queue.
135 * @buffer: destination buffer.
136 * @length: maximum number of bytes to copy.
138 * Copies at least a single WQE, but may copy more data.
140 * Return: the number of bytes copied, or an error code.
142 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
143 void *buffer, u32 length,
144 struct mlx5_ib_qp_base *base)
146 struct ib_device *ibdev = qp->ibqp.device;
147 struct mlx5_ib_dev *dev = to_mdev(ibdev);
148 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
151 struct ib_umem *umem = base->ubuffer.umem;
152 u32 first_copy_length;
156 if (wq->wqe_cnt == 0) {
157 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
162 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
163 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
165 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
168 if (offset > umem->length ||
169 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
172 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
173 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
178 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
179 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
181 wqe_length = ds * MLX5_WQE_DS_UNITS;
183 wqe_length = 1 << wq->wqe_shift;
186 if (wqe_length <= first_copy_length)
187 return first_copy_length;
189 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
190 wqe_length - first_copy_length);
197 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
199 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
200 struct ib_event event;
202 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
203 /* This event is only valid for trans_qps */
204 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
207 if (ibqp->event_handler) {
208 event.device = ibqp->device;
209 event.element.qp = ibqp;
211 case MLX5_EVENT_TYPE_PATH_MIG:
212 event.event = IB_EVENT_PATH_MIG;
214 case MLX5_EVENT_TYPE_COMM_EST:
215 event.event = IB_EVENT_COMM_EST;
217 case MLX5_EVENT_TYPE_SQ_DRAINED:
218 event.event = IB_EVENT_SQ_DRAINED;
220 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
221 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
223 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
224 event.event = IB_EVENT_QP_FATAL;
226 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
227 event.event = IB_EVENT_PATH_MIG_ERR;
229 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
230 event.event = IB_EVENT_QP_REQ_ERR;
232 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
233 event.event = IB_EVENT_QP_ACCESS_ERR;
236 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
240 ibqp->event_handler(&event, ibqp->qp_context);
244 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
245 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
250 /* Sanity check RQ size before proceeding */
251 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
257 qp->rq.wqe_shift = 0;
258 cap->max_recv_wr = 0;
259 cap->max_recv_sge = 0;
262 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
263 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
265 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
266 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
268 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
269 qp->rq.max_post = qp->rq.wqe_cnt;
271 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
272 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
273 wqe_size = roundup_pow_of_two(wqe_size);
274 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
275 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
276 qp->rq.wqe_cnt = wq_size / wqe_size;
277 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
278 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
280 MLX5_CAP_GEN(dev->mdev,
284 qp->rq.wqe_shift = ilog2(wqe_size);
285 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
286 qp->rq.max_post = qp->rq.wqe_cnt;
293 static int sq_overhead(struct ib_qp_init_attr *attr)
297 switch (attr->qp_type) {
299 size += sizeof(struct mlx5_wqe_xrc_seg);
302 size += sizeof(struct mlx5_wqe_ctrl_seg) +
303 max(sizeof(struct mlx5_wqe_atomic_seg) +
304 sizeof(struct mlx5_wqe_raddr_seg),
305 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
306 sizeof(struct mlx5_mkey_seg) +
307 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
308 MLX5_IB_UMR_OCTOWORD);
315 size += sizeof(struct mlx5_wqe_ctrl_seg) +
316 max(sizeof(struct mlx5_wqe_raddr_seg),
317 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
318 sizeof(struct mlx5_mkey_seg));
322 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
323 size += sizeof(struct mlx5_wqe_eth_pad) +
324 sizeof(struct mlx5_wqe_eth_seg);
327 case MLX5_IB_QPT_HW_GSI:
328 size += sizeof(struct mlx5_wqe_ctrl_seg) +
329 sizeof(struct mlx5_wqe_datagram_seg);
332 case MLX5_IB_QPT_REG_UMR:
333 size += sizeof(struct mlx5_wqe_ctrl_seg) +
334 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
335 sizeof(struct mlx5_mkey_seg);
345 static int calc_send_wqe(struct ib_qp_init_attr *attr)
350 size = sq_overhead(attr);
354 if (attr->cap.max_inline_data) {
355 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
356 attr->cap.max_inline_data;
359 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
360 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
361 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
362 return MLX5_SIG_WQE_SIZE;
364 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
367 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
371 if (attr->qp_type == IB_QPT_RC)
372 max_sge = (min_t(int, wqe_size, 512) -
373 sizeof(struct mlx5_wqe_ctrl_seg) -
374 sizeof(struct mlx5_wqe_raddr_seg)) /
375 sizeof(struct mlx5_wqe_data_seg);
376 else if (attr->qp_type == IB_QPT_XRC_INI)
377 max_sge = (min_t(int, wqe_size, 512) -
378 sizeof(struct mlx5_wqe_ctrl_seg) -
379 sizeof(struct mlx5_wqe_xrc_seg) -
380 sizeof(struct mlx5_wqe_raddr_seg)) /
381 sizeof(struct mlx5_wqe_data_seg);
383 max_sge = (wqe_size - sq_overhead(attr)) /
384 sizeof(struct mlx5_wqe_data_seg);
386 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
387 sizeof(struct mlx5_wqe_data_seg));
390 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
391 struct mlx5_ib_qp *qp)
396 if (!attr->cap.max_send_wr)
399 wqe_size = calc_send_wqe(attr);
400 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
404 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
405 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
406 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
410 qp->max_inline_data = wqe_size - sq_overhead(attr) -
411 sizeof(struct mlx5_wqe_inline_seg);
412 attr->cap.max_inline_data = qp->max_inline_data;
414 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
415 qp->signature_en = true;
417 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
418 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
419 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
420 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
421 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
423 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
426 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
427 qp->sq.max_gs = get_send_sge(attr, wqe_size);
428 if (qp->sq.max_gs < attr->cap.max_send_sge)
431 attr->cap.max_send_sge = qp->sq.max_gs;
432 qp->sq.max_post = wq_size / wqe_size;
433 attr->cap.max_send_wr = qp->sq.max_post;
438 static int set_user_buf_size(struct mlx5_ib_dev *dev,
439 struct mlx5_ib_qp *qp,
440 struct mlx5_ib_create_qp *ucmd,
441 struct mlx5_ib_qp_base *base,
442 struct ib_qp_init_attr *attr)
444 int desc_sz = 1 << qp->sq.wqe_shift;
446 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
447 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
448 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
452 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
453 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
454 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
458 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
460 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
461 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
463 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
467 if (attr->qp_type == IB_QPT_RAW_PACKET ||
468 qp->flags & MLX5_IB_QP_UNDERLAY) {
469 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
470 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
472 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
473 (qp->sq.wqe_cnt << 6);
479 static int qp_has_rq(struct ib_qp_init_attr *attr)
481 if (attr->qp_type == IB_QPT_XRC_INI ||
482 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
483 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
484 !attr->cap.max_recv_wr)
491 /* this is the first blue flame register in the array of bfregs assigned
492 * to a processes. Since we do not use it for blue flame but rather
493 * regular 64 bit doorbells, we do not need a lock for maintaiing
496 NUM_NON_BLUE_FLAME_BFREGS = 1,
499 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
501 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
504 static int num_med_bfreg(struct mlx5_ib_dev *dev,
505 struct mlx5_bfreg_info *bfregi)
509 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
510 NUM_NON_BLUE_FLAME_BFREGS;
512 return n >= 0 ? n : 0;
515 static int first_med_bfreg(struct mlx5_ib_dev *dev,
516 struct mlx5_bfreg_info *bfregi)
518 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
521 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
522 struct mlx5_bfreg_info *bfregi)
526 med = num_med_bfreg(dev, bfregi);
530 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
531 struct mlx5_bfreg_info *bfregi)
535 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
536 if (!bfregi->count[i]) {
545 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
546 struct mlx5_bfreg_info *bfregi)
548 int minidx = first_med_bfreg(dev, bfregi);
554 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
555 if (bfregi->count[i] < bfregi->count[minidx])
557 if (!bfregi->count[minidx])
561 bfregi->count[minidx]++;
565 static int alloc_bfreg(struct mlx5_ib_dev *dev,
566 struct mlx5_bfreg_info *bfregi,
567 enum mlx5_ib_latency_class lat)
569 int bfregn = -EINVAL;
571 mutex_lock(&bfregi->lock);
573 case MLX5_IB_LATENCY_CLASS_LOW:
574 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
576 bfregi->count[bfregn]++;
579 case MLX5_IB_LATENCY_CLASS_MEDIUM:
583 bfregn = alloc_med_class_bfreg(dev, bfregi);
586 case MLX5_IB_LATENCY_CLASS_HIGH:
590 bfregn = alloc_high_class_bfreg(dev, bfregi);
593 mutex_unlock(&bfregi->lock);
598 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
600 mutex_lock(&bfregi->lock);
601 bfregi->count[bfregn]--;
602 mutex_unlock(&bfregi->lock);
605 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
608 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
609 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
610 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
611 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
612 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
613 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
614 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
619 static int to_mlx5_st(enum ib_qp_type type)
622 case IB_QPT_RC: return MLX5_QP_ST_RC;
623 case IB_QPT_UC: return MLX5_QP_ST_UC;
624 case IB_QPT_UD: return MLX5_QP_ST_UD;
625 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
627 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
628 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
629 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
630 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
631 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
632 case IB_QPT_RAW_PACKET:
633 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
635 default: return -EINVAL;
639 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
640 struct mlx5_ib_cq *recv_cq);
641 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
642 struct mlx5_ib_cq *recv_cq);
644 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
645 struct mlx5_bfreg_info *bfregi, int bfregn,
648 int bfregs_per_sys_page;
649 int index_of_sys_page;
652 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
653 MLX5_NON_FP_BFREGS_PER_UAR;
654 index_of_sys_page = bfregn / bfregs_per_sys_page;
657 index_of_sys_page += bfregi->num_static_sys_pages;
658 if (bfregn > bfregi->num_dyn_bfregs ||
659 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
660 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
665 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
666 return bfregi->sys_pages[index_of_sys_page] + offset;
669 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
671 unsigned long addr, size_t size,
672 struct ib_umem **umem,
673 int *npages, int *page_shift, int *ncont,
678 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
680 mlx5_ib_dbg(dev, "umem_get failed\n");
681 return PTR_ERR(*umem);
684 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
686 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
688 mlx5_ib_warn(dev, "bad offset\n");
692 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
693 addr, size, *npages, *page_shift, *ncont, *offset);
698 ib_umem_release(*umem);
704 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
705 struct mlx5_ib_rwq *rwq)
707 struct mlx5_ib_ucontext *context;
709 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
710 atomic_dec(&dev->delay_drop.rqs_cnt);
712 context = to_mucontext(pd->uobject->context);
713 mlx5_ib_db_unmap_user(context, &rwq->db);
715 ib_umem_release(rwq->umem);
718 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
719 struct mlx5_ib_rwq *rwq,
720 struct mlx5_ib_create_wq *ucmd)
722 struct mlx5_ib_ucontext *context;
732 context = to_mucontext(pd->uobject->context);
733 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
734 rwq->buf_size, 0, 0);
735 if (IS_ERR(rwq->umem)) {
736 mlx5_ib_dbg(dev, "umem_get failed\n");
737 err = PTR_ERR(rwq->umem);
741 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
743 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
744 &rwq->rq_page_offset);
746 mlx5_ib_warn(dev, "bad offset\n");
750 rwq->rq_num_pas = ncont;
751 rwq->page_shift = page_shift;
752 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
753 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
755 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
756 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
757 npages, page_shift, ncont, offset);
759 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
761 mlx5_ib_dbg(dev, "map failed\n");
765 rwq->create_type = MLX5_WQ_USER;
769 ib_umem_release(rwq->umem);
773 static int adjust_bfregn(struct mlx5_ib_dev *dev,
774 struct mlx5_bfreg_info *bfregi, int bfregn)
776 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
777 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
780 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
781 struct mlx5_ib_qp *qp, struct ib_udata *udata,
782 struct ib_qp_init_attr *attr,
784 struct mlx5_ib_create_qp_resp *resp, int *inlen,
785 struct mlx5_ib_qp_base *base)
787 struct mlx5_ib_ucontext *context;
788 struct mlx5_ib_create_qp ucmd;
789 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
800 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
802 mlx5_ib_dbg(dev, "copy failed\n");
806 context = to_mucontext(pd->uobject->context);
807 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
808 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
809 ucmd.bfreg_index, true);
813 bfregn = MLX5_IB_INVALID_BFREG;
814 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
816 * TBD: should come from the verbs when we have the API
818 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
819 bfregn = MLX5_CROSS_CHANNEL_BFREG;
822 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
824 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
825 mlx5_ib_dbg(dev, "reverting to medium latency\n");
826 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
828 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
829 mlx5_ib_dbg(dev, "reverting to high latency\n");
830 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
832 mlx5_ib_warn(dev, "bfreg allocation failed\n");
839 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
840 if (bfregn != MLX5_IB_INVALID_BFREG)
841 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
845 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
846 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
848 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
852 if (ucmd.buf_addr && ubuffer->buf_size) {
853 ubuffer->buf_addr = ucmd.buf_addr;
854 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
856 &ubuffer->umem, &npages, &page_shift,
861 ubuffer->umem = NULL;
864 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
865 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
866 *in = kvzalloc(*inlen, GFP_KERNEL);
872 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
874 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
876 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
878 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
879 MLX5_SET(qpc, qpc, page_offset, offset);
881 MLX5_SET(qpc, qpc, uar_page, uar_index);
882 if (bfregn != MLX5_IB_INVALID_BFREG)
883 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
885 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
888 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
890 mlx5_ib_dbg(dev, "map failed\n");
894 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
896 mlx5_ib_dbg(dev, "copy failed\n");
899 qp->create_type = MLX5_QP_USER;
904 mlx5_ib_db_unmap_user(context, &qp->db);
911 ib_umem_release(ubuffer->umem);
914 if (bfregn != MLX5_IB_INVALID_BFREG)
915 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
919 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
920 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
922 struct mlx5_ib_ucontext *context;
924 context = to_mucontext(pd->uobject->context);
925 mlx5_ib_db_unmap_user(context, &qp->db);
926 if (base->ubuffer.umem)
927 ib_umem_release(base->ubuffer.umem);
930 * Free only the BFREGs which are handled by the kernel.
931 * BFREGs of UARs allocated dynamically are handled by user.
933 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
934 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
937 static int create_kernel_qp(struct mlx5_ib_dev *dev,
938 struct ib_qp_init_attr *init_attr,
939 struct mlx5_ib_qp *qp,
940 u32 **in, int *inlen,
941 struct mlx5_ib_qp_base *base)
947 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
948 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
949 IB_QP_CREATE_IPOIB_UD_LSO |
950 IB_QP_CREATE_NETIF_QP |
951 mlx5_ib_create_qp_sqpn_qp1()))
954 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
955 qp->bf.bfreg = &dev->fp_bfreg;
957 qp->bf.bfreg = &dev->bfreg;
959 /* We need to divide by two since each register is comprised of
960 * two buffers of identical size, namely odd and even
962 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
963 uar_index = qp->bf.bfreg->index;
965 err = calc_sq_size(dev, init_attr, qp);
967 mlx5_ib_dbg(dev, "err %d\n", err);
972 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
973 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
975 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
977 mlx5_ib_dbg(dev, "err %d\n", err);
981 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
982 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
983 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
984 *in = kvzalloc(*inlen, GFP_KERNEL);
990 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
991 MLX5_SET(qpc, qpc, uar_page, uar_index);
992 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
994 /* Set "fast registration enabled" for all kernel QPs */
995 MLX5_SET(qpc, qpc, fre, 1);
996 MLX5_SET(qpc, qpc, rlky, 1);
998 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
999 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1000 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1003 mlx5_fill_page_array(&qp->buf,
1004 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
1006 err = mlx5_db_alloc(dev->mdev, &qp->db);
1008 mlx5_ib_dbg(dev, "err %d\n", err);
1012 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1013 sizeof(*qp->sq.wrid), GFP_KERNEL);
1014 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1015 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1016 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1017 sizeof(*qp->rq.wrid), GFP_KERNEL);
1018 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1019 sizeof(*qp->sq.w_list), GFP_KERNEL);
1020 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1021 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1023 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1024 !qp->sq.w_list || !qp->sq.wqe_head) {
1028 qp->create_type = MLX5_QP_KERNEL;
1033 kvfree(qp->sq.wqe_head);
1034 kvfree(qp->sq.w_list);
1035 kvfree(qp->sq.wrid);
1036 kvfree(qp->sq.wr_data);
1037 kvfree(qp->rq.wrid);
1038 mlx5_db_free(dev->mdev, &qp->db);
1044 mlx5_buf_free(dev->mdev, &qp->buf);
1048 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1050 kvfree(qp->sq.wqe_head);
1051 kvfree(qp->sq.w_list);
1052 kvfree(qp->sq.wrid);
1053 kvfree(qp->sq.wr_data);
1054 kvfree(qp->rq.wrid);
1055 mlx5_db_free(dev->mdev, &qp->db);
1056 mlx5_buf_free(dev->mdev, &qp->buf);
1059 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1061 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1062 (attr->qp_type == MLX5_IB_QPT_DCI) ||
1063 (attr->qp_type == IB_QPT_XRC_INI))
1065 else if (!qp->has_rq)
1066 return MLX5_ZERO_LEN_RQ;
1068 return MLX5_NON_ZERO_RQ;
1071 static int is_connected(enum ib_qp_type qp_type)
1073 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1079 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1080 struct mlx5_ib_qp *qp,
1081 struct mlx5_ib_sq *sq, u32 tdn)
1083 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1084 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1086 MLX5_SET(tisc, tisc, transport_domain, tdn);
1087 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1088 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1090 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1093 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1094 struct mlx5_ib_sq *sq)
1096 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1099 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1100 struct mlx5_ib_sq *sq)
1103 mlx5_del_flow_rules(sq->flow_rule);
1106 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1107 struct mlx5_ib_sq *sq, void *qpin,
1110 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1114 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1123 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1124 &sq->ubuffer.umem, &npages, &page_shift,
1129 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1130 in = kvzalloc(inlen, GFP_KERNEL);
1136 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1137 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1138 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1139 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1140 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1141 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1142 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1143 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1144 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1145 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1146 MLX5_CAP_ETH(dev->mdev, swp))
1147 MLX5_SET(sqc, sqc, allow_swp, 1);
1149 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1150 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1151 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1152 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1153 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1154 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1155 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1156 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1157 MLX5_SET(wq, wq, page_offset, offset);
1159 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1160 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1162 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1169 err = create_flow_rule_vport_sq(dev, sq);
1176 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1179 ib_umem_release(sq->ubuffer.umem);
1180 sq->ubuffer.umem = NULL;
1185 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1186 struct mlx5_ib_sq *sq)
1188 destroy_flow_rule_vport_sq(dev, sq);
1189 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1190 ib_umem_release(sq->ubuffer.umem);
1193 static size_t get_rq_pas_size(void *qpc)
1195 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1196 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1197 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1198 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1199 u32 po_quanta = 1 << (log_page_size - 6);
1200 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1201 u32 page_size = 1 << log_page_size;
1202 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1203 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1205 return rq_num_pas * sizeof(u64);
1208 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1209 struct mlx5_ib_rq *rq, void *qpin,
1212 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1218 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1219 size_t rq_pas_size = get_rq_pas_size(qpc);
1223 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1226 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1227 in = kvzalloc(inlen, GFP_KERNEL);
1231 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1232 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1233 MLX5_SET(rqc, rqc, vsd, 1);
1234 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1235 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1236 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1237 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1238 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1240 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1241 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1243 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1244 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1245 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1246 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1247 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1248 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1249 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1250 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1251 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1252 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1254 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1255 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1256 memcpy(pas, qp_pas, rq_pas_size);
1258 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1265 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1266 struct mlx5_ib_rq *rq)
1268 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1271 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1273 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1274 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1275 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1278 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1279 struct mlx5_ib_rq *rq, u32 tdn,
1280 bool tunnel_offload_en)
1287 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1288 in = kvzalloc(inlen, GFP_KERNEL);
1292 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1293 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1294 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1295 MLX5_SET(tirc, tirc, transport_domain, tdn);
1296 if (tunnel_offload_en)
1297 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1300 MLX5_SET(tirc, tirc, self_lb_block,
1301 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1303 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1310 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1311 struct mlx5_ib_rq *rq)
1313 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1316 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1317 u32 *in, size_t inlen,
1320 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1321 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1322 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1323 struct ib_uobject *uobj = pd->uobject;
1324 struct ib_ucontext *ucontext = uobj->context;
1325 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1327 u32 tdn = mucontext->tdn;
1329 if (qp->sq.wqe_cnt) {
1330 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1334 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1336 goto err_destroy_tis;
1338 sq->base.container_mibqp = qp;
1339 sq->base.mqp.event = mlx5_ib_qp_event;
1342 if (qp->rq.wqe_cnt) {
1343 rq->base.container_mibqp = qp;
1345 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1346 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1347 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1348 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1349 err = create_raw_packet_qp_rq(dev, rq, in, inlen);
1351 goto err_destroy_sq;
1354 err = create_raw_packet_qp_tir(dev, rq, tdn,
1355 qp->tunnel_offload_en);
1357 goto err_destroy_rq;
1360 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1366 destroy_raw_packet_qp_rq(dev, rq);
1368 if (!qp->sq.wqe_cnt)
1370 destroy_raw_packet_qp_sq(dev, sq);
1372 destroy_raw_packet_qp_tis(dev, sq);
1377 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1378 struct mlx5_ib_qp *qp)
1380 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1381 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1382 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1384 if (qp->rq.wqe_cnt) {
1385 destroy_raw_packet_qp_tir(dev, rq);
1386 destroy_raw_packet_qp_rq(dev, rq);
1389 if (qp->sq.wqe_cnt) {
1390 destroy_raw_packet_qp_sq(dev, sq);
1391 destroy_raw_packet_qp_tis(dev, sq);
1395 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1396 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1398 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1399 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1403 sq->doorbell = &qp->db;
1404 rq->doorbell = &qp->db;
1407 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1409 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1412 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1414 struct ib_qp_init_attr *init_attr,
1415 struct ib_udata *udata)
1417 struct ib_uobject *uobj = pd->uobject;
1418 struct ib_ucontext *ucontext = uobj->context;
1419 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1420 struct mlx5_ib_create_qp_resp resp = {};
1426 u32 selected_fields = 0;
1428 size_t min_resp_len;
1429 u32 tdn = mucontext->tdn;
1430 struct mlx5_ib_create_qp_rss ucmd = {};
1431 size_t required_cmd_sz;
1433 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1436 if (init_attr->create_flags || init_attr->send_cq)
1439 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1440 if (udata->outlen < min_resp_len)
1443 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1444 if (udata->inlen < required_cmd_sz) {
1445 mlx5_ib_dbg(dev, "invalid inlen\n");
1449 if (udata->inlen > sizeof(ucmd) &&
1450 !ib_is_udata_cleared(udata, sizeof(ucmd),
1451 udata->inlen - sizeof(ucmd))) {
1452 mlx5_ib_dbg(dev, "inlen is not supported\n");
1456 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1457 mlx5_ib_dbg(dev, "copy failed\n");
1461 if (ucmd.comp_mask) {
1462 mlx5_ib_dbg(dev, "invalid comp mask\n");
1466 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1467 mlx5_ib_dbg(dev, "invalid flags\n");
1471 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1472 !tunnel_offload_supported(dev->mdev)) {
1473 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1477 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1478 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1479 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1483 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1485 mlx5_ib_dbg(dev, "copy failed\n");
1489 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1490 in = kvzalloc(inlen, GFP_KERNEL);
1494 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1495 MLX5_SET(tirc, tirc, disp_type,
1496 MLX5_TIRC_DISP_TYPE_INDIRECT);
1497 MLX5_SET(tirc, tirc, indirect_table,
1498 init_attr->rwq_ind_tbl->ind_tbl_num);
1499 MLX5_SET(tirc, tirc, transport_domain, tdn);
1501 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1503 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1504 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1506 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1507 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1509 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1511 switch (ucmd.rx_hash_function) {
1512 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1514 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1515 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1517 if (len != ucmd.rx_key_len) {
1522 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1523 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1524 memcpy(rss_key, ucmd.rx_hash_key, len);
1532 if (!ucmd.rx_hash_fields_mask) {
1533 /* special case when this TIR serves as steering entry without hashing */
1534 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1540 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1541 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1542 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1543 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1548 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1549 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1550 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1551 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1552 MLX5_L3_PROT_TYPE_IPV4);
1553 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1554 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1555 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1556 MLX5_L3_PROT_TYPE_IPV6);
1558 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1559 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1560 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1561 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1562 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1564 /* Check that only one l4 protocol is set */
1565 if (outer_l4 & (outer_l4 - 1)) {
1570 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1571 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1572 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1573 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1574 MLX5_L4_PROT_TYPE_TCP);
1575 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1576 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1577 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1578 MLX5_L4_PROT_TYPE_UDP);
1580 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1581 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1582 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1584 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1585 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1586 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1588 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1589 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1590 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1592 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1593 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1594 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1596 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1597 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1599 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1603 MLX5_SET(tirc, tirc, self_lb_block,
1604 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1606 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1612 /* qpn is reserved for that QP */
1613 qp->trans_qp.base.mqp.qpn = 0;
1614 qp->flags |= MLX5_IB_QP_RSS;
1622 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1623 struct ib_qp_init_attr *init_attr,
1624 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1626 struct mlx5_ib_resources *devr = &dev->devr;
1627 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1628 struct mlx5_core_dev *mdev = dev->mdev;
1629 struct mlx5_ib_create_qp_resp resp;
1630 struct mlx5_ib_cq *send_cq;
1631 struct mlx5_ib_cq *recv_cq;
1632 unsigned long flags;
1633 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1634 struct mlx5_ib_create_qp ucmd;
1635 struct mlx5_ib_qp_base *base;
1641 mutex_init(&qp->mutex);
1642 spin_lock_init(&qp->sq.lock);
1643 spin_lock_init(&qp->rq.lock);
1645 mlx5_st = to_mlx5_st(init_attr->qp_type);
1649 if (init_attr->rwq_ind_tbl) {
1653 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1657 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1658 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1659 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1662 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1666 if (init_attr->create_flags &
1667 (IB_QP_CREATE_CROSS_CHANNEL |
1668 IB_QP_CREATE_MANAGED_SEND |
1669 IB_QP_CREATE_MANAGED_RECV)) {
1670 if (!MLX5_CAP_GEN(mdev, cd)) {
1671 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1674 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1675 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1676 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1677 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1678 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1679 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1682 if (init_attr->qp_type == IB_QPT_UD &&
1683 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1684 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1685 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1689 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1690 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1691 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1694 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1695 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1696 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1699 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1702 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1703 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1705 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1706 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1707 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1708 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1710 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1713 if (pd && pd->uobject) {
1714 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1715 mlx5_ib_dbg(dev, "copy failed\n");
1719 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1720 &ucmd, udata->inlen, &uidx);
1724 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1725 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1726 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1727 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1728 !tunnel_offload_supported(mdev)) {
1729 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1732 qp->tunnel_offload_en = true;
1735 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1736 if (init_attr->qp_type != IB_QPT_UD ||
1737 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1738 MLX5_CAP_PORT_TYPE_IB) ||
1739 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1740 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1744 qp->flags |= MLX5_IB_QP_UNDERLAY;
1745 qp->underlay_qpn = init_attr->source_qpn;
1748 qp->wq_sig = !!wq_signature;
1751 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1752 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1753 &qp->raw_packet_qp.rq.base :
1756 qp->has_rq = qp_has_rq(init_attr);
1757 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1758 qp, (pd && pd->uobject) ? &ucmd : NULL);
1760 mlx5_ib_dbg(dev, "err %d\n", err);
1767 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1768 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1769 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1770 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1771 mlx5_ib_dbg(dev, "invalid rq params\n");
1774 if (ucmd.sq_wqe_count > max_wqes) {
1775 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1776 ucmd.sq_wqe_count, max_wqes);
1779 if (init_attr->create_flags &
1780 mlx5_ib_create_qp_sqpn_qp1()) {
1781 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1784 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1785 &resp, &inlen, base);
1787 mlx5_ib_dbg(dev, "err %d\n", err);
1789 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1792 mlx5_ib_dbg(dev, "err %d\n", err);
1798 in = kvzalloc(inlen, GFP_KERNEL);
1802 qp->create_type = MLX5_QP_EMPTY;
1805 if (is_sqp(init_attr->qp_type))
1806 qp->port = init_attr->port_num;
1808 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1810 MLX5_SET(qpc, qpc, st, mlx5_st);
1811 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1813 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1814 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1816 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1820 MLX5_SET(qpc, qpc, wq_signature, 1);
1822 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1823 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1825 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1826 MLX5_SET(qpc, qpc, cd_master, 1);
1827 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1828 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1829 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1830 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1832 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1836 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1837 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1840 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1842 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1844 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1846 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1848 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1852 if (qp->rq.wqe_cnt) {
1853 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1854 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1857 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1859 if (qp->sq.wqe_cnt) {
1860 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1862 MLX5_SET(qpc, qpc, no_sq, 1);
1863 if (init_attr->srq &&
1864 init_attr->srq->srq_type == IB_SRQT_TM)
1865 MLX5_SET(qpc, qpc, offload_type,
1866 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1869 /* Set default resources */
1870 switch (init_attr->qp_type) {
1871 case IB_QPT_XRC_TGT:
1872 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1873 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1874 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1875 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1877 case IB_QPT_XRC_INI:
1878 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1879 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1880 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1883 if (init_attr->srq) {
1884 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1885 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1887 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1888 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1892 if (init_attr->send_cq)
1893 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1895 if (init_attr->recv_cq)
1896 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1898 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1900 /* 0xffffff means we ask to work with cqe version 0 */
1901 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1902 MLX5_SET(qpc, qpc, user_index, uidx);
1904 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1905 if (init_attr->qp_type == IB_QPT_UD &&
1906 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1907 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1908 qp->flags |= MLX5_IB_QP_LSO;
1911 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1912 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1913 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1916 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1917 MLX5_SET(qpc, qpc, end_padding_mode,
1918 MLX5_WQ_END_PAD_MODE_ALIGN);
1920 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1929 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1930 qp->flags & MLX5_IB_QP_UNDERLAY) {
1931 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1932 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1933 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
1935 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1939 mlx5_ib_dbg(dev, "create qp failed\n");
1945 base->container_mibqp = qp;
1946 base->mqp.event = mlx5_ib_qp_event;
1948 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1949 &send_cq, &recv_cq);
1950 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1951 mlx5_ib_lock_cqs(send_cq, recv_cq);
1952 /* Maintain device to QPs access, needed for further handling via reset
1955 list_add_tail(&qp->qps_list, &dev->qp_list);
1956 /* Maintain CQ to QPs access, needed for further handling via reset flow
1959 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1961 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1962 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1963 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1968 if (qp->create_type == MLX5_QP_USER)
1969 destroy_qp_user(dev, pd, qp, base);
1970 else if (qp->create_type == MLX5_QP_KERNEL)
1971 destroy_qp_kernel(dev, qp);
1978 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1979 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1983 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1984 spin_lock(&send_cq->lock);
1985 spin_lock_nested(&recv_cq->lock,
1986 SINGLE_DEPTH_NESTING);
1987 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1988 spin_lock(&send_cq->lock);
1989 __acquire(&recv_cq->lock);
1991 spin_lock(&recv_cq->lock);
1992 spin_lock_nested(&send_cq->lock,
1993 SINGLE_DEPTH_NESTING);
1996 spin_lock(&send_cq->lock);
1997 __acquire(&recv_cq->lock);
1999 } else if (recv_cq) {
2000 spin_lock(&recv_cq->lock);
2001 __acquire(&send_cq->lock);
2003 __acquire(&send_cq->lock);
2004 __acquire(&recv_cq->lock);
2008 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2009 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2013 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2014 spin_unlock(&recv_cq->lock);
2015 spin_unlock(&send_cq->lock);
2016 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2017 __release(&recv_cq->lock);
2018 spin_unlock(&send_cq->lock);
2020 spin_unlock(&send_cq->lock);
2021 spin_unlock(&recv_cq->lock);
2024 __release(&recv_cq->lock);
2025 spin_unlock(&send_cq->lock);
2027 } else if (recv_cq) {
2028 __release(&send_cq->lock);
2029 spin_unlock(&recv_cq->lock);
2031 __release(&recv_cq->lock);
2032 __release(&send_cq->lock);
2036 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2038 return to_mpd(qp->ibqp.pd);
2041 static void get_cqs(enum ib_qp_type qp_type,
2042 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2043 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2046 case IB_QPT_XRC_TGT:
2050 case MLX5_IB_QPT_REG_UMR:
2051 case IB_QPT_XRC_INI:
2052 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2057 case MLX5_IB_QPT_HW_GSI:
2061 case IB_QPT_RAW_IPV6:
2062 case IB_QPT_RAW_ETHERTYPE:
2063 case IB_QPT_RAW_PACKET:
2064 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2065 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2076 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2077 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2078 u8 lag_tx_affinity);
2080 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2082 struct mlx5_ib_cq *send_cq, *recv_cq;
2083 struct mlx5_ib_qp_base *base;
2084 unsigned long flags;
2087 if (qp->ibqp.rwq_ind_tbl) {
2088 destroy_rss_raw_qp_tir(dev, qp);
2092 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2093 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2094 &qp->raw_packet_qp.rq.base :
2097 if (qp->state != IB_QPS_RESET) {
2098 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2099 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2100 err = mlx5_core_qp_modify(dev->mdev,
2101 MLX5_CMD_OP_2RST_QP, 0,
2104 struct mlx5_modify_raw_qp_param raw_qp_param = {
2105 .operation = MLX5_CMD_OP_2RST_QP
2108 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2111 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2115 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2116 &send_cq, &recv_cq);
2118 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2119 mlx5_ib_lock_cqs(send_cq, recv_cq);
2120 /* del from lists under both locks above to protect reset flow paths */
2121 list_del(&qp->qps_list);
2123 list_del(&qp->cq_send_list);
2126 list_del(&qp->cq_recv_list);
2128 if (qp->create_type == MLX5_QP_KERNEL) {
2129 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2130 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2131 if (send_cq != recv_cq)
2132 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2135 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2136 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2138 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2139 qp->flags & MLX5_IB_QP_UNDERLAY) {
2140 destroy_raw_packet_qp(dev, qp);
2142 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2144 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2148 if (qp->create_type == MLX5_QP_KERNEL)
2149 destroy_qp_kernel(dev, qp);
2150 else if (qp->create_type == MLX5_QP_USER)
2151 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2154 static const char *ib_qp_type_str(enum ib_qp_type type)
2158 return "IB_QPT_SMI";
2160 return "IB_QPT_GSI";
2167 case IB_QPT_RAW_IPV6:
2168 return "IB_QPT_RAW_IPV6";
2169 case IB_QPT_RAW_ETHERTYPE:
2170 return "IB_QPT_RAW_ETHERTYPE";
2171 case IB_QPT_XRC_INI:
2172 return "IB_QPT_XRC_INI";
2173 case IB_QPT_XRC_TGT:
2174 return "IB_QPT_XRC_TGT";
2175 case IB_QPT_RAW_PACKET:
2176 return "IB_QPT_RAW_PACKET";
2177 case MLX5_IB_QPT_REG_UMR:
2178 return "MLX5_IB_QPT_REG_UMR";
2180 return "IB_QPT_DRIVER";
2183 return "Invalid QP type";
2187 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2188 struct ib_qp_init_attr *attr,
2189 struct mlx5_ib_create_qp *ucmd)
2191 struct mlx5_ib_qp *qp;
2193 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2196 if (!attr->srq || !attr->recv_cq)
2197 return ERR_PTR(-EINVAL);
2199 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2200 ucmd, sizeof(*ucmd), &uidx);
2202 return ERR_PTR(err);
2204 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2206 return ERR_PTR(-ENOMEM);
2208 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2214 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2215 qp->qp_sub_type = MLX5_IB_QPT_DCT;
2216 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2217 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2218 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2219 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2220 MLX5_SET(dctc, dctc, user_index, uidx);
2222 qp->state = IB_QPS_RESET;
2227 return ERR_PTR(err);
2230 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2231 struct ib_qp_init_attr *init_attr,
2232 struct mlx5_ib_create_qp *ucmd,
2233 struct ib_udata *udata)
2235 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2241 if (udata->inlen < sizeof(*ucmd)) {
2242 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2245 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2249 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2250 init_attr->qp_type = MLX5_IB_QPT_DCI;
2252 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2253 init_attr->qp_type = MLX5_IB_QPT_DCT;
2255 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2260 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2261 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2268 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2269 struct ib_qp_init_attr *verbs_init_attr,
2270 struct ib_udata *udata)
2272 struct mlx5_ib_dev *dev;
2273 struct mlx5_ib_qp *qp;
2276 struct ib_qp_init_attr mlx_init_attr;
2277 struct ib_qp_init_attr *init_attr = verbs_init_attr;
2280 dev = to_mdev(pd->device);
2282 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2284 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2285 return ERR_PTR(-EINVAL);
2286 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2287 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2288 return ERR_PTR(-EINVAL);
2292 /* being cautious here */
2293 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2294 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2295 pr_warn("%s: no PD for transport %s\n", __func__,
2296 ib_qp_type_str(init_attr->qp_type));
2297 return ERR_PTR(-EINVAL);
2299 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2302 if (init_attr->qp_type == IB_QPT_DRIVER) {
2303 struct mlx5_ib_create_qp ucmd;
2305 init_attr = &mlx_init_attr;
2306 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2307 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2309 return ERR_PTR(err);
2311 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2312 if (init_attr->cap.max_recv_wr ||
2313 init_attr->cap.max_recv_sge) {
2314 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2315 return ERR_PTR(-EINVAL);
2318 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2322 switch (init_attr->qp_type) {
2323 case IB_QPT_XRC_TGT:
2324 case IB_QPT_XRC_INI:
2325 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2326 mlx5_ib_dbg(dev, "XRC not supported\n");
2327 return ERR_PTR(-ENOSYS);
2329 init_attr->recv_cq = NULL;
2330 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2331 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2332 init_attr->send_cq = NULL;
2336 case IB_QPT_RAW_PACKET:
2341 case MLX5_IB_QPT_HW_GSI:
2342 case MLX5_IB_QPT_REG_UMR:
2343 case MLX5_IB_QPT_DCI:
2344 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2346 return ERR_PTR(-ENOMEM);
2348 err = create_qp_common(dev, pd, init_attr, udata, qp);
2350 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2352 return ERR_PTR(err);
2355 if (is_qp0(init_attr->qp_type))
2356 qp->ibqp.qp_num = 0;
2357 else if (is_qp1(init_attr->qp_type))
2358 qp->ibqp.qp_num = 1;
2360 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2362 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2363 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2364 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2365 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2367 qp->trans_qp.xrcdn = xrcdn;
2372 return mlx5_ib_gsi_create_qp(pd, init_attr);
2374 case IB_QPT_RAW_IPV6:
2375 case IB_QPT_RAW_ETHERTYPE:
2378 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2379 init_attr->qp_type);
2380 /* Don't support raw QPs */
2381 return ERR_PTR(-EINVAL);
2384 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2385 qp->qp_sub_type = init_attr->qp_type;
2390 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2392 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2394 if (mqp->state == IB_QPS_RTR) {
2397 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2399 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2409 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2411 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2412 struct mlx5_ib_qp *mqp = to_mqp(qp);
2414 if (unlikely(qp->qp_type == IB_QPT_GSI))
2415 return mlx5_ib_gsi_destroy_qp(qp);
2417 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2418 return mlx5_ib_destroy_dct(mqp);
2420 destroy_qp_common(dev, mqp);
2427 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2430 u32 hw_access_flags = 0;
2434 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2435 dest_rd_atomic = attr->max_dest_rd_atomic;
2437 dest_rd_atomic = qp->trans_qp.resp_depth;
2439 if (attr_mask & IB_QP_ACCESS_FLAGS)
2440 access_flags = attr->qp_access_flags;
2442 access_flags = qp->trans_qp.atomic_rd_en;
2444 if (!dest_rd_atomic)
2445 access_flags &= IB_ACCESS_REMOTE_WRITE;
2447 if (access_flags & IB_ACCESS_REMOTE_READ)
2448 hw_access_flags |= MLX5_QP_BIT_RRE;
2449 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2450 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2451 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2452 hw_access_flags |= MLX5_QP_BIT_RWE;
2454 return cpu_to_be32(hw_access_flags);
2458 MLX5_PATH_FLAG_FL = 1 << 0,
2459 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2460 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2463 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2465 if (rate == IB_RATE_PORT_CURRENT)
2468 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2471 while (rate != IB_RATE_PORT_CURRENT &&
2472 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2473 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2476 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2479 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2480 struct mlx5_ib_sq *sq, u8 sl)
2487 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2488 in = kvzalloc(inlen, GFP_KERNEL);
2492 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2494 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2495 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2497 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2504 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2505 struct mlx5_ib_sq *sq, u8 tx_affinity)
2512 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2513 in = kvzalloc(inlen, GFP_KERNEL);
2517 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2519 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2520 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2522 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2529 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2530 const struct rdma_ah_attr *ah,
2531 struct mlx5_qp_path *path, u8 port, int attr_mask,
2532 u32 path_flags, const struct ib_qp_attr *attr,
2535 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2537 enum ib_gid_type gid_type;
2538 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2539 u8 sl = rdma_ah_get_sl(ah);
2541 if (attr_mask & IB_QP_PKEY_INDEX)
2542 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2545 if (ah_flags & IB_AH_GRH) {
2546 if (grh->sgid_index >=
2547 dev->mdev->port_caps[port - 1].gid_table_len) {
2548 pr_err("sgid_index (%u) too large. max is %d\n",
2550 dev->mdev->port_caps[port - 1].gid_table_len);
2555 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2556 if (!(ah_flags & IB_AH_GRH))
2559 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2560 if (qp->ibqp.qp_type == IB_QPT_RC ||
2561 qp->ibqp.qp_type == IB_QPT_UC ||
2562 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2563 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2565 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2566 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2567 gid_type = ah->grh.sgid_attr->gid_type;
2568 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2569 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2571 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2573 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2574 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2575 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2576 if (ah_flags & IB_AH_GRH)
2577 path->grh_mlid |= 1 << 7;
2578 path->dci_cfi_prio_sl = sl & 0xf;
2581 if (ah_flags & IB_AH_GRH) {
2582 path->mgid_index = grh->sgid_index;
2583 path->hop_limit = grh->hop_limit;
2584 path->tclass_flowlabel =
2585 cpu_to_be32((grh->traffic_class << 20) |
2587 memcpy(path->rgid, grh->dgid.raw, 16);
2590 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2593 path->static_rate = err;
2596 if (attr_mask & IB_QP_TIMEOUT)
2597 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2599 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2600 return modify_raw_packet_eth_prio(dev->mdev,
2601 &qp->raw_packet_qp.sq,
2607 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2608 [MLX5_QP_STATE_INIT] = {
2609 [MLX5_QP_STATE_INIT] = {
2610 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2611 MLX5_QP_OPTPAR_RAE |
2612 MLX5_QP_OPTPAR_RWE |
2613 MLX5_QP_OPTPAR_PKEY_INDEX |
2614 MLX5_QP_OPTPAR_PRI_PORT,
2615 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2616 MLX5_QP_OPTPAR_PKEY_INDEX |
2617 MLX5_QP_OPTPAR_PRI_PORT,
2618 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2619 MLX5_QP_OPTPAR_Q_KEY |
2620 MLX5_QP_OPTPAR_PRI_PORT,
2622 [MLX5_QP_STATE_RTR] = {
2623 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2624 MLX5_QP_OPTPAR_RRE |
2625 MLX5_QP_OPTPAR_RAE |
2626 MLX5_QP_OPTPAR_RWE |
2627 MLX5_QP_OPTPAR_PKEY_INDEX,
2628 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2629 MLX5_QP_OPTPAR_RWE |
2630 MLX5_QP_OPTPAR_PKEY_INDEX,
2631 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2632 MLX5_QP_OPTPAR_Q_KEY,
2633 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2634 MLX5_QP_OPTPAR_Q_KEY,
2635 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2636 MLX5_QP_OPTPAR_RRE |
2637 MLX5_QP_OPTPAR_RAE |
2638 MLX5_QP_OPTPAR_RWE |
2639 MLX5_QP_OPTPAR_PKEY_INDEX,
2642 [MLX5_QP_STATE_RTR] = {
2643 [MLX5_QP_STATE_RTS] = {
2644 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2645 MLX5_QP_OPTPAR_RRE |
2646 MLX5_QP_OPTPAR_RAE |
2647 MLX5_QP_OPTPAR_RWE |
2648 MLX5_QP_OPTPAR_PM_STATE |
2649 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2650 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2651 MLX5_QP_OPTPAR_RWE |
2652 MLX5_QP_OPTPAR_PM_STATE,
2653 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2656 [MLX5_QP_STATE_RTS] = {
2657 [MLX5_QP_STATE_RTS] = {
2658 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2659 MLX5_QP_OPTPAR_RAE |
2660 MLX5_QP_OPTPAR_RWE |
2661 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2662 MLX5_QP_OPTPAR_PM_STATE |
2663 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2664 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2665 MLX5_QP_OPTPAR_PM_STATE |
2666 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2667 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2668 MLX5_QP_OPTPAR_SRQN |
2669 MLX5_QP_OPTPAR_CQN_RCV,
2672 [MLX5_QP_STATE_SQER] = {
2673 [MLX5_QP_STATE_RTS] = {
2674 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2675 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2676 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2677 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2678 MLX5_QP_OPTPAR_RWE |
2679 MLX5_QP_OPTPAR_RAE |
2685 static int ib_nr_to_mlx5_nr(int ib_mask)
2690 case IB_QP_CUR_STATE:
2692 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2694 case IB_QP_ACCESS_FLAGS:
2695 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2697 case IB_QP_PKEY_INDEX:
2698 return MLX5_QP_OPTPAR_PKEY_INDEX;
2700 return MLX5_QP_OPTPAR_PRI_PORT;
2702 return MLX5_QP_OPTPAR_Q_KEY;
2704 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2705 MLX5_QP_OPTPAR_PRI_PORT;
2706 case IB_QP_PATH_MTU:
2709 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2710 case IB_QP_RETRY_CNT:
2711 return MLX5_QP_OPTPAR_RETRY_COUNT;
2712 case IB_QP_RNR_RETRY:
2713 return MLX5_QP_OPTPAR_RNR_RETRY;
2716 case IB_QP_MAX_QP_RD_ATOMIC:
2717 return MLX5_QP_OPTPAR_SRA_MAX;
2718 case IB_QP_ALT_PATH:
2719 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2720 case IB_QP_MIN_RNR_TIMER:
2721 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2724 case IB_QP_MAX_DEST_RD_ATOMIC:
2725 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2726 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2727 case IB_QP_PATH_MIG_STATE:
2728 return MLX5_QP_OPTPAR_PM_STATE;
2731 case IB_QP_DEST_QPN:
2737 static int ib_mask_to_mlx5_opt(int ib_mask)
2742 for (i = 0; i < 8 * sizeof(int); i++) {
2743 if ((1 << i) & ib_mask)
2744 result |= ib_nr_to_mlx5_nr(1 << i);
2750 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2751 struct mlx5_ib_rq *rq, int new_state,
2752 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2759 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2760 in = kvzalloc(inlen, GFP_KERNEL);
2764 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2766 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2767 MLX5_SET(rqc, rqc, state, new_state);
2769 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2770 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2771 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2772 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2773 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2775 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2779 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2783 rq->state = new_state;
2790 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2791 struct mlx5_ib_sq *sq,
2793 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2795 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2796 struct mlx5_rate_limit old_rl = ibqp->rl;
2797 struct mlx5_rate_limit new_rl = old_rl;
2798 bool new_rate_added = false;
2805 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2806 in = kvzalloc(inlen, GFP_KERNEL);
2810 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2812 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2813 MLX5_SET(sqc, sqc, state, new_state);
2815 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2816 if (new_state != MLX5_SQC_STATE_RDY)
2817 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2820 new_rl = raw_qp_param->rl;
2823 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2825 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
2827 pr_err("Failed configuring rate limit(err %d): \
2828 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2829 err, new_rl.rate, new_rl.max_burst_sz,
2830 new_rl.typical_pkt_sz);
2834 new_rate_added = true;
2837 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2838 /* index 0 means no limit */
2839 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2842 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2844 /* Remove new rate from table if failed */
2846 mlx5_rl_remove_rate(dev, &new_rl);
2850 /* Only remove the old rate after new rate was set */
2852 !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
2853 (new_state != MLX5_SQC_STATE_RDY))
2854 mlx5_rl_remove_rate(dev, &old_rl);
2857 sq->state = new_state;
2864 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2865 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2868 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2869 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2870 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2871 int modify_rq = !!qp->rq.wqe_cnt;
2872 int modify_sq = !!qp->sq.wqe_cnt;
2877 switch (raw_qp_param->operation) {
2878 case MLX5_CMD_OP_RST2INIT_QP:
2879 rq_state = MLX5_RQC_STATE_RDY;
2880 sq_state = MLX5_SQC_STATE_RDY;
2882 case MLX5_CMD_OP_2ERR_QP:
2883 rq_state = MLX5_RQC_STATE_ERR;
2884 sq_state = MLX5_SQC_STATE_ERR;
2886 case MLX5_CMD_OP_2RST_QP:
2887 rq_state = MLX5_RQC_STATE_RST;
2888 sq_state = MLX5_SQC_STATE_RST;
2890 case MLX5_CMD_OP_RTR2RTS_QP:
2891 case MLX5_CMD_OP_RTS2RTS_QP:
2892 if (raw_qp_param->set_mask ==
2893 MLX5_RAW_QP_RATE_LIMIT) {
2895 sq_state = sq->state;
2897 return raw_qp_param->set_mask ? -EINVAL : 0;
2900 case MLX5_CMD_OP_INIT2INIT_QP:
2901 case MLX5_CMD_OP_INIT2RTR_QP:
2902 if (raw_qp_param->set_mask)
2912 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2919 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2925 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2931 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2932 const struct ib_qp_attr *attr, int attr_mask,
2933 enum ib_qp_state cur_state, enum ib_qp_state new_state,
2934 const struct mlx5_ib_modify_qp *ucmd)
2936 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2937 [MLX5_QP_STATE_RST] = {
2938 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2939 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2940 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2942 [MLX5_QP_STATE_INIT] = {
2943 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2944 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2945 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2946 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2948 [MLX5_QP_STATE_RTR] = {
2949 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2950 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2951 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2953 [MLX5_QP_STATE_RTS] = {
2954 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2955 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2956 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2958 [MLX5_QP_STATE_SQD] = {
2959 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2960 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2962 [MLX5_QP_STATE_SQER] = {
2963 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2964 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2965 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2967 [MLX5_QP_STATE_ERR] = {
2968 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2969 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2973 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2974 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2975 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2976 struct mlx5_ib_cq *send_cq, *recv_cq;
2977 struct mlx5_qp_context *context;
2978 struct mlx5_ib_pd *pd;
2979 struct mlx5_ib_port *mibport = NULL;
2980 enum mlx5_qp_state mlx5_cur, mlx5_new;
2981 enum mlx5_qp_optpar optpar;
2987 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
2988 qp->qp_sub_type : ibqp->qp_type);
2992 context = kzalloc(sizeof(*context), GFP_KERNEL);
2996 context->flags = cpu_to_be32(mlx5_st << 16);
2998 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2999 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3001 switch (attr->path_mig_state) {
3002 case IB_MIG_MIGRATED:
3003 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3006 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3009 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3014 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3015 if ((ibqp->qp_type == IB_QPT_RC) ||
3016 (ibqp->qp_type == IB_QPT_UD &&
3017 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3018 (ibqp->qp_type == IB_QPT_UC) ||
3019 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3020 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3021 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3022 if (mlx5_lag_is_active(dev->mdev)) {
3023 u8 p = mlx5_core_native_port_num(dev->mdev);
3024 tx_affinity = (unsigned int)atomic_add_return(1,
3025 &dev->roce[p].next_port) %
3027 context->flags |= cpu_to_be32(tx_affinity << 24);
3032 if (is_sqp(ibqp->qp_type)) {
3033 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3034 } else if ((ibqp->qp_type == IB_QPT_UD &&
3035 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3036 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3037 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3038 } else if (attr_mask & IB_QP_PATH_MTU) {
3039 if (attr->path_mtu < IB_MTU_256 ||
3040 attr->path_mtu > IB_MTU_4096) {
3041 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3045 context->mtu_msgmax = (attr->path_mtu << 5) |
3046 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3049 if (attr_mask & IB_QP_DEST_QPN)
3050 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3052 if (attr_mask & IB_QP_PKEY_INDEX)
3053 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3055 /* todo implement counter_index functionality */
3057 if (is_sqp(ibqp->qp_type))
3058 context->pri_path.port = qp->port;
3060 if (attr_mask & IB_QP_PORT)
3061 context->pri_path.port = attr->port_num;
3063 if (attr_mask & IB_QP_AV) {
3064 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3065 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3066 attr_mask, 0, attr, false);
3071 if (attr_mask & IB_QP_TIMEOUT)
3072 context->pri_path.ackto_lt |= attr->timeout << 3;
3074 if (attr_mask & IB_QP_ALT_PATH) {
3075 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3078 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3085 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3086 &send_cq, &recv_cq);
3088 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3089 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3090 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3091 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3093 if (attr_mask & IB_QP_RNR_RETRY)
3094 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3096 if (attr_mask & IB_QP_RETRY_CNT)
3097 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3099 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3100 if (attr->max_rd_atomic)
3102 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3105 if (attr_mask & IB_QP_SQ_PSN)
3106 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3108 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3109 if (attr->max_dest_rd_atomic)
3111 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3114 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3115 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3117 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3118 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3120 if (attr_mask & IB_QP_RQ_PSN)
3121 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3123 if (attr_mask & IB_QP_QKEY)
3124 context->qkey = cpu_to_be32(attr->qkey);
3126 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3127 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3129 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3130 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3133 /* Underlay port should be used - index 0 function per port */
3134 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3137 mibport = &dev->port[port_num];
3138 context->qp_counter_set_usr_page |=
3139 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3142 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3143 context->sq_crq_size |= cpu_to_be16(1 << 4);
3145 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3146 context->deth_sqpn = cpu_to_be32(1);
3148 mlx5_cur = to_mlx5_state(cur_state);
3149 mlx5_new = to_mlx5_state(new_state);
3151 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3152 !optab[mlx5_cur][mlx5_new]) {
3157 op = optab[mlx5_cur][mlx5_new];
3158 optpar = ib_mask_to_mlx5_opt(attr_mask);
3159 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3161 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3162 qp->flags & MLX5_IB_QP_UNDERLAY) {
3163 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3165 raw_qp_param.operation = op;
3166 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3167 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3168 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3171 if (attr_mask & IB_QP_RATE_LIMIT) {
3172 raw_qp_param.rl.rate = attr->rate_limit;
3174 if (ucmd->burst_info.max_burst_sz) {
3175 if (attr->rate_limit &&
3176 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3177 raw_qp_param.rl.max_burst_sz =
3178 ucmd->burst_info.max_burst_sz;
3185 if (ucmd->burst_info.typical_pkt_sz) {
3186 if (attr->rate_limit &&
3187 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3188 raw_qp_param.rl.typical_pkt_sz =
3189 ucmd->burst_info.typical_pkt_sz;
3196 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3199 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3201 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3208 qp->state = new_state;
3210 if (attr_mask & IB_QP_ACCESS_FLAGS)
3211 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3212 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3213 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3214 if (attr_mask & IB_QP_PORT)
3215 qp->port = attr->port_num;
3216 if (attr_mask & IB_QP_ALT_PATH)
3217 qp->trans_qp.alt_port = attr->alt_port_num;
3220 * If we moved a kernel QP to RESET, clean up all old CQ
3221 * entries and reinitialize the QP.
3223 if (new_state == IB_QPS_RESET &&
3224 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3225 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3226 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3227 if (send_cq != recv_cq)
3228 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3234 qp->sq.cur_post = 0;
3235 qp->sq.last_poll = 0;
3236 qp->db.db[MLX5_RCV_DBR] = 0;
3237 qp->db.db[MLX5_SND_DBR] = 0;
3245 static inline bool is_valid_mask(int mask, int req, int opt)
3247 if ((mask & req) != req)
3250 if (mask & ~(req | opt))
3256 /* check valid transition for driver QP types
3257 * for now the only QP type that this function supports is DCI
3259 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3260 enum ib_qp_attr_mask attr_mask)
3262 int req = IB_QP_STATE;
3265 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3266 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3267 return is_valid_mask(attr_mask, req, opt);
3268 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3269 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3270 return is_valid_mask(attr_mask, req, opt);
3271 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3272 req |= IB_QP_PATH_MTU;
3273 opt = IB_QP_PKEY_INDEX;
3274 return is_valid_mask(attr_mask, req, opt);
3275 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3276 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3277 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3278 opt = IB_QP_MIN_RNR_TIMER;
3279 return is_valid_mask(attr_mask, req, opt);
3280 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3281 opt = IB_QP_MIN_RNR_TIMER;
3282 return is_valid_mask(attr_mask, req, opt);
3283 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3284 return is_valid_mask(attr_mask, req, opt);
3289 /* mlx5_ib_modify_dct: modify a DCT QP
3290 * valid transitions are:
3291 * RESET to INIT: must set access_flags, pkey_index and port
3292 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3293 * mtu, gid_index and hop_limit
3294 * Other transitions and attributes are illegal
3296 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3297 int attr_mask, struct ib_udata *udata)
3299 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3300 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3301 enum ib_qp_state cur_state, new_state;
3303 int required = IB_QP_STATE;
3306 if (!(attr_mask & IB_QP_STATE))
3309 cur_state = qp->state;
3310 new_state = attr->qp_state;
3312 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3313 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3314 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3315 if (!is_valid_mask(attr_mask, required, 0))
3318 if (attr->port_num == 0 ||
3319 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3320 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3321 attr->port_num, dev->num_ports);
3324 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3325 MLX5_SET(dctc, dctc, rre, 1);
3326 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3327 MLX5_SET(dctc, dctc, rwe, 1);
3328 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3329 if (!mlx5_ib_dc_atomic_is_supported(dev))
3331 MLX5_SET(dctc, dctc, rae, 1);
3332 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3334 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3335 MLX5_SET(dctc, dctc, port, attr->port_num);
3336 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3338 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3339 struct mlx5_ib_modify_qp_resp resp = {};
3340 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3343 if (udata->outlen < min_resp_len)
3345 resp.response_length = min_resp_len;
3347 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3348 if (!is_valid_mask(attr_mask, required, 0))
3350 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3351 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3352 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3353 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3354 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3355 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3357 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3358 MLX5_ST_SZ_BYTES(create_dct_in));
3361 resp.dctn = qp->dct.mdct.mqp.qpn;
3362 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3364 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3368 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3372 qp->state = IB_QPS_ERR;
3374 qp->state = new_state;
3378 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3379 int attr_mask, struct ib_udata *udata)
3381 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3382 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3383 struct mlx5_ib_modify_qp ucmd = {};
3384 enum ib_qp_type qp_type;
3385 enum ib_qp_state cur_state, new_state;
3386 size_t required_cmd_sz;
3389 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
3391 if (ibqp->rwq_ind_tbl)
3394 if (udata && udata->inlen) {
3395 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3396 sizeof(ucmd.reserved);
3397 if (udata->inlen < required_cmd_sz)
3400 if (udata->inlen > sizeof(ucmd) &&
3401 !ib_is_udata_cleared(udata, sizeof(ucmd),
3402 udata->inlen - sizeof(ucmd)))
3405 if (ib_copy_from_udata(&ucmd, udata,
3406 min(udata->inlen, sizeof(ucmd))))
3409 if (ucmd.comp_mask ||
3410 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3411 memchr_inv(&ucmd.burst_info.reserved, 0,
3412 sizeof(ucmd.burst_info.reserved)))
3416 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3417 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3419 if (ibqp->qp_type == IB_QPT_DRIVER)
3420 qp_type = qp->qp_sub_type;
3422 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3423 IB_QPT_GSI : ibqp->qp_type;
3425 if (qp_type == MLX5_IB_QPT_DCT)
3426 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3428 mutex_lock(&qp->mutex);
3430 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3431 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3433 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3434 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3435 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3438 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3439 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3440 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3444 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3445 qp_type != MLX5_IB_QPT_DCI &&
3446 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
3447 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3448 cur_state, new_state, ibqp->qp_type, attr_mask);
3450 } else if (qp_type == MLX5_IB_QPT_DCI &&
3451 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3452 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3453 cur_state, new_state, qp_type, attr_mask);
3457 if ((attr_mask & IB_QP_PORT) &&
3458 (attr->port_num == 0 ||
3459 attr->port_num > dev->num_ports)) {
3460 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3461 attr->port_num, dev->num_ports);
3465 if (attr_mask & IB_QP_PKEY_INDEX) {
3466 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3467 if (attr->pkey_index >=
3468 dev->mdev->port_caps[port - 1].pkey_table_len) {
3469 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3475 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3476 attr->max_rd_atomic >
3477 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3478 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3479 attr->max_rd_atomic);
3483 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3484 attr->max_dest_rd_atomic >
3485 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3486 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3487 attr->max_dest_rd_atomic);
3491 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3496 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3500 mutex_unlock(&qp->mutex);
3504 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3506 struct mlx5_ib_cq *cq;
3509 cur = wq->head - wq->tail;
3510 if (likely(cur + nreq < wq->max_post))
3514 spin_lock(&cq->lock);
3515 cur = wq->head - wq->tail;
3516 spin_unlock(&cq->lock);
3518 return cur + nreq >= wq->max_post;
3521 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3522 u64 remote_addr, u32 rkey)
3524 rseg->raddr = cpu_to_be64(remote_addr);
3525 rseg->rkey = cpu_to_be32(rkey);
3529 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3530 struct ib_send_wr *wr, void *qend,
3531 struct mlx5_ib_qp *qp, int *size)
3535 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3537 if (wr->send_flags & IB_SEND_IP_CSUM)
3538 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3539 MLX5_ETH_WQE_L4_CSUM;
3541 seg += sizeof(struct mlx5_wqe_eth_seg);
3542 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3544 if (wr->opcode == IB_WR_LSO) {
3545 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3546 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3547 u64 left, leftlen, copysz;
3548 void *pdata = ud_wr->header;
3551 eseg->mss = cpu_to_be16(ud_wr->mss);
3552 eseg->inline_hdr.sz = cpu_to_be16(left);
3555 * check if there is space till the end of queue, if yes,
3556 * copy all in one shot, otherwise copy till the end of queue,
3557 * rollback and than the copy the left
3559 leftlen = qend - (void *)eseg->inline_hdr.start;
3560 copysz = min_t(u64, leftlen, left);
3562 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3564 if (likely(copysz > size_of_inl_hdr_start)) {
3565 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3566 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3569 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3570 seg = mlx5_get_send_wqe(qp, 0);
3573 memcpy(seg, pdata, left);
3574 seg += ALIGN(left, 16);
3575 *size += ALIGN(left, 16) / 16;
3582 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3583 struct ib_send_wr *wr)
3585 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3586 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3587 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3590 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3592 dseg->byte_count = cpu_to_be32(sg->length);
3593 dseg->lkey = cpu_to_be32(sg->lkey);
3594 dseg->addr = cpu_to_be64(sg->addr);
3597 static u64 get_xlt_octo(u64 bytes)
3599 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3600 MLX5_IB_UMR_OCTOWORD;
3603 static __be64 frwr_mkey_mask(void)
3607 result = MLX5_MKEY_MASK_LEN |
3608 MLX5_MKEY_MASK_PAGE_SIZE |
3609 MLX5_MKEY_MASK_START_ADDR |
3610 MLX5_MKEY_MASK_EN_RINVAL |
3611 MLX5_MKEY_MASK_KEY |
3617 MLX5_MKEY_MASK_SMALL_FENCE |
3618 MLX5_MKEY_MASK_FREE;
3620 return cpu_to_be64(result);
3623 static __be64 sig_mkey_mask(void)
3627 result = MLX5_MKEY_MASK_LEN |
3628 MLX5_MKEY_MASK_PAGE_SIZE |
3629 MLX5_MKEY_MASK_START_ADDR |
3630 MLX5_MKEY_MASK_EN_SIGERR |
3631 MLX5_MKEY_MASK_EN_RINVAL |
3632 MLX5_MKEY_MASK_KEY |
3637 MLX5_MKEY_MASK_SMALL_FENCE |
3638 MLX5_MKEY_MASK_FREE |
3639 MLX5_MKEY_MASK_BSF_EN;
3641 return cpu_to_be64(result);
3644 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3645 struct mlx5_ib_mr *mr, bool umr_inline)
3647 int size = mr->ndescs * mr->desc_size;
3649 memset(umr, 0, sizeof(*umr));
3651 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3653 umr->flags |= MLX5_UMR_INLINE;
3654 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3655 umr->mkey_mask = frwr_mkey_mask();
3658 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3660 memset(umr, 0, sizeof(*umr));
3661 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3662 umr->flags = MLX5_UMR_INLINE;
3665 static __be64 get_umr_enable_mr_mask(void)
3669 result = MLX5_MKEY_MASK_KEY |
3670 MLX5_MKEY_MASK_FREE;
3672 return cpu_to_be64(result);
3675 static __be64 get_umr_disable_mr_mask(void)
3679 result = MLX5_MKEY_MASK_FREE;
3681 return cpu_to_be64(result);
3684 static __be64 get_umr_update_translation_mask(void)
3688 result = MLX5_MKEY_MASK_LEN |
3689 MLX5_MKEY_MASK_PAGE_SIZE |
3690 MLX5_MKEY_MASK_START_ADDR;
3692 return cpu_to_be64(result);
3695 static __be64 get_umr_update_access_mask(int atomic)
3699 result = MLX5_MKEY_MASK_LR |
3705 result |= MLX5_MKEY_MASK_A;
3707 return cpu_to_be64(result);
3710 static __be64 get_umr_update_pd_mask(void)
3714 result = MLX5_MKEY_MASK_PD;
3716 return cpu_to_be64(result);
3719 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
3721 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
3722 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
3723 (mask & MLX5_MKEY_MASK_A &&
3724 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
3729 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
3730 struct mlx5_wqe_umr_ctrl_seg *umr,
3731 struct ib_send_wr *wr, int atomic)
3733 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3735 memset(umr, 0, sizeof(*umr));
3737 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3738 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3740 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3742 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3743 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3744 u64 offset = get_xlt_octo(umrwr->offset);
3746 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3747 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3748 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3750 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3751 umr->mkey_mask |= get_umr_update_translation_mask();
3752 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3753 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3754 umr->mkey_mask |= get_umr_update_pd_mask();
3756 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3757 umr->mkey_mask |= get_umr_enable_mr_mask();
3758 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3759 umr->mkey_mask |= get_umr_disable_mr_mask();
3762 umr->flags |= MLX5_UMR_INLINE;
3764 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
3767 static u8 get_umr_flags(int acc)
3769 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3770 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3771 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3772 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3773 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3776 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3777 struct mlx5_ib_mr *mr,
3778 u32 key, int access)
3780 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3782 memset(seg, 0, sizeof(*seg));
3784 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3785 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3786 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3787 /* KLMs take twice the size of MTTs */
3790 seg->flags = get_umr_flags(access) | mr->access_mode;
3791 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3792 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3793 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3794 seg->len = cpu_to_be64(mr->ibmr.length);
3795 seg->xlt_oct_size = cpu_to_be32(ndescs);
3798 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3800 memset(seg, 0, sizeof(*seg));
3801 seg->status = MLX5_MKEY_STATUS_FREE;
3804 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3806 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3808 memset(seg, 0, sizeof(*seg));
3809 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3810 seg->status = MLX5_MKEY_STATUS_FREE;
3812 seg->flags = convert_access(umrwr->access_flags);
3814 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3815 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3817 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3819 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3820 seg->len = cpu_to_be64(umrwr->length);
3821 seg->log2_page_size = umrwr->page_shift;
3822 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3823 mlx5_mkey_variant(umrwr->mkey));
3826 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3827 struct mlx5_ib_mr *mr,
3828 struct mlx5_ib_pd *pd)
3830 int bcount = mr->desc_size * mr->ndescs;
3832 dseg->addr = cpu_to_be64(mr->desc_map);
3833 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3834 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3837 static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp,
3838 struct mlx5_ib_mr *mr, int mr_list_size)
3840 void *qend = qp->sq.qend;
3841 void *addr = mr->descs;
3844 if (unlikely(seg + mr_list_size > qend)) {
3846 memcpy(seg, addr, copy);
3848 mr_list_size -= copy;
3849 seg = mlx5_get_send_wqe(qp, 0);
3851 memcpy(seg, addr, mr_list_size);
3852 seg += mr_list_size;
3855 static __be32 send_ieth(struct ib_send_wr *wr)
3857 switch (wr->opcode) {
3858 case IB_WR_SEND_WITH_IMM:
3859 case IB_WR_RDMA_WRITE_WITH_IMM:
3860 return wr->ex.imm_data;
3862 case IB_WR_SEND_WITH_INV:
3863 return cpu_to_be32(wr->ex.invalidate_rkey);
3870 static u8 calc_sig(void *wqe, int size)
3876 for (i = 0; i < size; i++)
3882 static u8 wq_sig(void *wqe)
3884 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3887 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3890 struct mlx5_wqe_inline_seg *seg;
3891 void *qend = qp->sq.qend;
3899 wqe += sizeof(*seg);
3900 for (i = 0; i < wr->num_sge; i++) {
3901 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3902 len = wr->sg_list[i].length;
3905 if (unlikely(inl > qp->max_inline_data))
3908 if (unlikely(wqe + len > qend)) {
3910 memcpy(wqe, addr, copy);
3913 wqe = mlx5_get_send_wqe(qp, 0);
3915 memcpy(wqe, addr, len);
3919 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3921 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3926 static u16 prot_field_size(enum ib_signature_type type)
3929 case IB_SIG_TYPE_T10_DIF:
3930 return MLX5_DIF_SIZE;
3936 static u8 bs_selector(int block_size)
3938 switch (block_size) {
3939 case 512: return 0x1;
3940 case 520: return 0x2;
3941 case 4096: return 0x3;
3942 case 4160: return 0x4;
3943 case 1073741824: return 0x5;
3948 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3949 struct mlx5_bsf_inl *inl)
3951 /* Valid inline section and allow BSF refresh */
3952 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3953 MLX5_BSF_REFRESH_DIF);
3954 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3955 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3956 /* repeating block */
3957 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3958 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3959 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3961 if (domain->sig.dif.ref_remap)
3962 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3964 if (domain->sig.dif.app_escape) {
3965 if (domain->sig.dif.ref_escape)
3966 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3968 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3971 inl->dif_app_bitmask_check =
3972 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3975 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3976 struct ib_sig_attrs *sig_attrs,
3977 struct mlx5_bsf *bsf, u32 data_size)
3979 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3980 struct mlx5_bsf_basic *basic = &bsf->basic;
3981 struct ib_sig_domain *mem = &sig_attrs->mem;
3982 struct ib_sig_domain *wire = &sig_attrs->wire;
3984 memset(bsf, 0, sizeof(*bsf));
3986 /* Basic + Extended + Inline */
3987 basic->bsf_size_sbs = 1 << 7;
3988 /* Input domain check byte mask */
3989 basic->check_byte_mask = sig_attrs->check_mask;
3990 basic->raw_data_size = cpu_to_be32(data_size);
3993 switch (sig_attrs->mem.sig_type) {
3994 case IB_SIG_TYPE_NONE:
3996 case IB_SIG_TYPE_T10_DIF:
3997 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3998 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3999 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4006 switch (sig_attrs->wire.sig_type) {
4007 case IB_SIG_TYPE_NONE:
4009 case IB_SIG_TYPE_T10_DIF:
4010 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4011 mem->sig_type == wire->sig_type) {
4012 /* Same block structure */
4013 basic->bsf_size_sbs |= 1 << 4;
4014 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4015 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4016 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4017 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4018 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4019 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4021 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4023 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4024 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4033 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
4034 struct mlx5_ib_qp *qp, void **seg, int *size)
4036 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4037 struct ib_mr *sig_mr = wr->sig_mr;
4038 struct mlx5_bsf *bsf;
4039 u32 data_len = wr->wr.sg_list->length;
4040 u32 data_key = wr->wr.sg_list->lkey;
4041 u64 data_va = wr->wr.sg_list->addr;
4046 (data_key == wr->prot->lkey &&
4047 data_va == wr->prot->addr &&
4048 data_len == wr->prot->length)) {
4050 * Source domain doesn't contain signature information
4051 * or data and protection are interleaved in memory.
4052 * So need construct:
4053 * ------------------
4055 * ------------------
4057 * ------------------
4059 struct mlx5_klm *data_klm = *seg;
4061 data_klm->bcount = cpu_to_be32(data_len);
4062 data_klm->key = cpu_to_be32(data_key);
4063 data_klm->va = cpu_to_be64(data_va);
4064 wqe_size = ALIGN(sizeof(*data_klm), 64);
4067 * Source domain contains signature information
4068 * So need construct a strided block format:
4069 * ---------------------------
4070 * | stride_block_ctrl |
4071 * ---------------------------
4073 * ---------------------------
4075 * ---------------------------
4077 * ---------------------------
4079 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4080 struct mlx5_stride_block_entry *data_sentry;
4081 struct mlx5_stride_block_entry *prot_sentry;
4082 u32 prot_key = wr->prot->lkey;
4083 u64 prot_va = wr->prot->addr;
4084 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4088 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4089 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4091 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4093 pr_err("Bad block size given: %u\n", block_size);
4096 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4098 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4099 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4100 sblock_ctrl->num_entries = cpu_to_be16(2);
4102 data_sentry->bcount = cpu_to_be16(block_size);
4103 data_sentry->key = cpu_to_be32(data_key);
4104 data_sentry->va = cpu_to_be64(data_va);
4105 data_sentry->stride = cpu_to_be16(block_size);
4107 prot_sentry->bcount = cpu_to_be16(prot_size);
4108 prot_sentry->key = cpu_to_be32(prot_key);
4109 prot_sentry->va = cpu_to_be64(prot_va);
4110 prot_sentry->stride = cpu_to_be16(prot_size);
4112 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4113 sizeof(*prot_sentry), 64);
4117 *size += wqe_size / 16;
4118 if (unlikely((*seg == qp->sq.qend)))
4119 *seg = mlx5_get_send_wqe(qp, 0);
4122 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4126 *seg += sizeof(*bsf);
4127 *size += sizeof(*bsf) / 16;
4128 if (unlikely((*seg == qp->sq.qend)))
4129 *seg = mlx5_get_send_wqe(qp, 0);
4134 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4135 struct ib_sig_handover_wr *wr, u32 size,
4136 u32 length, u32 pdn)
4138 struct ib_mr *sig_mr = wr->sig_mr;
4139 u32 sig_key = sig_mr->rkey;
4140 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4142 memset(seg, 0, sizeof(*seg));
4144 seg->flags = get_umr_flags(wr->access_flags) |
4145 MLX5_MKC_ACCESS_MODE_KLMS;
4146 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4147 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4148 MLX5_MKEY_BSF_EN | pdn);
4149 seg->len = cpu_to_be64(length);
4150 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4151 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4154 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4157 memset(umr, 0, sizeof(*umr));
4159 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4160 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4161 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4162 umr->mkey_mask = sig_mkey_mask();
4166 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
4167 void **seg, int *size)
4169 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4170 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4171 u32 pdn = get_pd(qp)->pdn;
4173 int region_len, ret;
4175 if (unlikely(wr->wr.num_sge != 1) ||
4176 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4177 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4178 unlikely(!sig_mr->sig->sig_status_checked))
4181 /* length of the protected region, data + protection */
4182 region_len = wr->wr.sg_list->length;
4184 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4185 wr->prot->addr != wr->wr.sg_list->addr ||
4186 wr->prot->length != wr->wr.sg_list->length))
4187 region_len += wr->prot->length;
4190 * KLM octoword size - if protection was provided
4191 * then we use strided block format (3 octowords),
4192 * else we use single KLM (1 octoword)
4194 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4196 set_sig_umr_segment(*seg, xlt_size);
4197 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4198 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4199 if (unlikely((*seg == qp->sq.qend)))
4200 *seg = mlx5_get_send_wqe(qp, 0);
4202 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4203 *seg += sizeof(struct mlx5_mkey_seg);
4204 *size += sizeof(struct mlx5_mkey_seg) / 16;
4205 if (unlikely((*seg == qp->sq.qend)))
4206 *seg = mlx5_get_send_wqe(qp, 0);
4208 ret = set_sig_data_segment(wr, qp, seg, size);
4212 sig_mr->sig->sig_status_checked = false;
4216 static int set_psv_wr(struct ib_sig_domain *domain,
4217 u32 psv_idx, void **seg, int *size)
4219 struct mlx5_seg_set_psv *psv_seg = *seg;
4221 memset(psv_seg, 0, sizeof(*psv_seg));
4222 psv_seg->psv_num = cpu_to_be32(psv_idx);
4223 switch (domain->sig_type) {
4224 case IB_SIG_TYPE_NONE:
4226 case IB_SIG_TYPE_T10_DIF:
4227 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4228 domain->sig.dif.app_tag);
4229 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4232 pr_err("Bad signature type (%d) is given.\n",
4237 *seg += sizeof(*psv_seg);
4238 *size += sizeof(*psv_seg) / 16;
4243 static int set_reg_wr(struct mlx5_ib_qp *qp,
4244 struct ib_reg_wr *wr,
4245 void **seg, int *size)
4247 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4248 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4249 int mr_list_size = mr->ndescs * mr->desc_size;
4250 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4252 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4253 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4254 "Invalid IB_SEND_INLINE send flag\n");
4258 set_reg_umr_seg(*seg, mr, umr_inline);
4259 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4260 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4261 if (unlikely((*seg == qp->sq.qend)))
4262 *seg = mlx5_get_send_wqe(qp, 0);
4264 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4265 *seg += sizeof(struct mlx5_mkey_seg);
4266 *size += sizeof(struct mlx5_mkey_seg) / 16;
4267 if (unlikely((*seg == qp->sq.qend)))
4268 *seg = mlx5_get_send_wqe(qp, 0);
4271 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size);
4272 *size += get_xlt_octo(mr_list_size);
4274 set_reg_data_seg(*seg, mr, pd);
4275 *seg += sizeof(struct mlx5_wqe_data_seg);
4276 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4281 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
4283 set_linv_umr_seg(*seg);
4284 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4285 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4286 if (unlikely((*seg == qp->sq.qend)))
4287 *seg = mlx5_get_send_wqe(qp, 0);
4288 set_linv_mkey_seg(*seg);
4289 *seg += sizeof(struct mlx5_mkey_seg);
4290 *size += sizeof(struct mlx5_mkey_seg) / 16;
4291 if (unlikely((*seg == qp->sq.qend)))
4292 *seg = mlx5_get_send_wqe(qp, 0);
4295 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4301 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4302 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4303 if ((i & 0xf) == 0) {
4304 void *buf = mlx5_get_send_wqe(qp, tidx);
4305 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4309 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4310 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4311 be32_to_cpu(p[j + 3]));
4315 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4316 struct mlx5_wqe_ctrl_seg **ctrl,
4317 struct ib_send_wr *wr, unsigned *idx,
4318 int *size, int nreq)
4320 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4323 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4324 *seg = mlx5_get_send_wqe(qp, *idx);
4326 *(uint32_t *)(*seg + 8) = 0;
4327 (*ctrl)->imm = send_ieth(wr);
4328 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4329 (wr->send_flags & IB_SEND_SIGNALED ?
4330 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4331 (wr->send_flags & IB_SEND_SOLICITED ?
4332 MLX5_WQE_CTRL_SOLICITED : 0);
4334 *seg += sizeof(**ctrl);
4335 *size = sizeof(**ctrl) / 16;
4340 static void finish_wqe(struct mlx5_ib_qp *qp,
4341 struct mlx5_wqe_ctrl_seg *ctrl,
4342 u8 size, unsigned idx, u64 wr_id,
4343 int nreq, u8 fence, u32 mlx5_opcode)
4347 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4348 mlx5_opcode | ((u32)opmod << 24));
4349 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4350 ctrl->fm_ce_se |= fence;
4351 if (unlikely(qp->wq_sig))
4352 ctrl->signature = wq_sig(ctrl);
4354 qp->sq.wrid[idx] = wr_id;
4355 qp->sq.w_list[idx].opcode = mlx5_opcode;
4356 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4357 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4358 qp->sq.w_list[idx].next = qp->sq.cur_post;
4362 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4363 struct ib_send_wr **bad_wr)
4365 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4366 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4367 struct mlx5_core_dev *mdev = dev->mdev;
4368 struct mlx5_ib_qp *qp;
4369 struct mlx5_ib_mr *mr;
4370 struct mlx5_wqe_data_seg *dpseg;
4371 struct mlx5_wqe_xrc_seg *xrc;
4373 int uninitialized_var(size);
4375 unsigned long flags;
4385 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4386 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4392 spin_lock_irqsave(&qp->sq.lock, flags);
4394 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4401 for (nreq = 0; wr; nreq++, wr = wr->next) {
4402 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4403 mlx5_ib_warn(dev, "\n");
4409 num_sge = wr->num_sge;
4410 if (unlikely(num_sge > qp->sq.max_gs)) {
4411 mlx5_ib_warn(dev, "\n");
4417 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4419 mlx5_ib_warn(dev, "\n");
4425 if (wr->opcode == IB_WR_LOCAL_INV ||
4426 wr->opcode == IB_WR_REG_MR) {
4427 fence = dev->umr_fence;
4428 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4429 } else if (wr->send_flags & IB_SEND_FENCE) {
4431 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4433 fence = MLX5_FENCE_MODE_FENCE;
4435 fence = qp->next_fence;
4438 switch (ibqp->qp_type) {
4439 case IB_QPT_XRC_INI:
4441 seg += sizeof(*xrc);
4442 size += sizeof(*xrc) / 16;
4445 switch (wr->opcode) {
4446 case IB_WR_RDMA_READ:
4447 case IB_WR_RDMA_WRITE:
4448 case IB_WR_RDMA_WRITE_WITH_IMM:
4449 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4451 seg += sizeof(struct mlx5_wqe_raddr_seg);
4452 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4455 case IB_WR_ATOMIC_CMP_AND_SWP:
4456 case IB_WR_ATOMIC_FETCH_AND_ADD:
4457 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4458 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4463 case IB_WR_LOCAL_INV:
4464 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4465 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4466 set_linv_wr(qp, &seg, &size);
4471 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4472 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4473 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4481 case IB_WR_REG_SIG_MR:
4482 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4483 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4485 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4486 err = set_sig_umr_wr(wr, qp, &seg, &size);
4488 mlx5_ib_warn(dev, "\n");
4493 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4494 fence, MLX5_OPCODE_UMR);
4496 * SET_PSV WQEs are not signaled and solicited
4499 wr->send_flags &= ~IB_SEND_SIGNALED;
4500 wr->send_flags |= IB_SEND_SOLICITED;
4501 err = begin_wqe(qp, &seg, &ctrl, wr,
4504 mlx5_ib_warn(dev, "\n");
4510 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4511 mr->sig->psv_memory.psv_idx, &seg,
4514 mlx5_ib_warn(dev, "\n");
4519 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4520 fence, MLX5_OPCODE_SET_PSV);
4521 err = begin_wqe(qp, &seg, &ctrl, wr,
4524 mlx5_ib_warn(dev, "\n");
4530 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4531 mr->sig->psv_wire.psv_idx, &seg,
4534 mlx5_ib_warn(dev, "\n");
4539 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4540 fence, MLX5_OPCODE_SET_PSV);
4541 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4551 switch (wr->opcode) {
4552 case IB_WR_RDMA_WRITE:
4553 case IB_WR_RDMA_WRITE_WITH_IMM:
4554 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4556 seg += sizeof(struct mlx5_wqe_raddr_seg);
4557 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4566 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4567 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4573 case MLX5_IB_QPT_HW_GSI:
4574 set_datagram_seg(seg, wr);
4575 seg += sizeof(struct mlx5_wqe_datagram_seg);
4576 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4577 if (unlikely((seg == qend)))
4578 seg = mlx5_get_send_wqe(qp, 0);
4581 set_datagram_seg(seg, wr);
4582 seg += sizeof(struct mlx5_wqe_datagram_seg);
4583 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4585 if (unlikely((seg == qend)))
4586 seg = mlx5_get_send_wqe(qp, 0);
4588 /* handle qp that supports ud offload */
4589 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4590 struct mlx5_wqe_eth_pad *pad;
4593 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4594 seg += sizeof(struct mlx5_wqe_eth_pad);
4595 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4597 seg = set_eth_seg(seg, wr, qend, qp, &size);
4599 if (unlikely((seg == qend)))
4600 seg = mlx5_get_send_wqe(qp, 0);
4603 case MLX5_IB_QPT_REG_UMR:
4604 if (wr->opcode != MLX5_IB_WR_UMR) {
4606 mlx5_ib_warn(dev, "bad opcode\n");
4609 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4610 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4611 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4614 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4615 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4616 if (unlikely((seg == qend)))
4617 seg = mlx5_get_send_wqe(qp, 0);
4618 set_reg_mkey_segment(seg, wr);
4619 seg += sizeof(struct mlx5_mkey_seg);
4620 size += sizeof(struct mlx5_mkey_seg) / 16;
4621 if (unlikely((seg == qend)))
4622 seg = mlx5_get_send_wqe(qp, 0);
4629 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4630 int uninitialized_var(sz);
4632 err = set_data_inl_seg(qp, wr, seg, &sz);
4633 if (unlikely(err)) {
4634 mlx5_ib_warn(dev, "\n");
4641 for (i = 0; i < num_sge; i++) {
4642 if (unlikely(dpseg == qend)) {
4643 seg = mlx5_get_send_wqe(qp, 0);
4646 if (likely(wr->sg_list[i].length)) {
4647 set_data_ptr_seg(dpseg, wr->sg_list + i);
4648 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4654 qp->next_fence = next_fence;
4655 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4656 mlx5_ib_opcode[wr->opcode]);
4659 dump_wqe(qp, idx, size);
4664 qp->sq.head += nreq;
4666 /* Make sure that descriptors are written before
4667 * updating doorbell record and ringing the doorbell
4671 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4673 /* Make sure doorbell record is visible to the HCA before
4674 * we hit doorbell */
4677 /* currently we support only regular doorbells */
4678 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4679 /* Make sure doorbells don't leak out of SQ spinlock
4680 * and reach the HCA out of order.
4683 bf->offset ^= bf->buf_size;
4686 spin_unlock_irqrestore(&qp->sq.lock, flags);
4691 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4693 sig->signature = calc_sig(sig, size);
4696 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4697 struct ib_recv_wr **bad_wr)
4699 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4700 struct mlx5_wqe_data_seg *scat;
4701 struct mlx5_rwqe_sig *sig;
4702 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4703 struct mlx5_core_dev *mdev = dev->mdev;
4704 unsigned long flags;
4710 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4711 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4713 spin_lock_irqsave(&qp->rq.lock, flags);
4715 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4722 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4724 for (nreq = 0; wr; nreq++, wr = wr->next) {
4725 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4731 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4737 scat = get_recv_wqe(qp, ind);
4741 for (i = 0; i < wr->num_sge; i++)
4742 set_data_ptr_seg(scat + i, wr->sg_list + i);
4744 if (i < qp->rq.max_gs) {
4745 scat[i].byte_count = 0;
4746 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4751 sig = (struct mlx5_rwqe_sig *)scat;
4752 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4755 qp->rq.wrid[ind] = wr->wr_id;
4757 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4762 qp->rq.head += nreq;
4764 /* Make sure that descriptors are written before
4769 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4772 spin_unlock_irqrestore(&qp->rq.lock, flags);
4777 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4779 switch (mlx5_state) {
4780 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4781 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4782 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4783 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4784 case MLX5_QP_STATE_SQ_DRAINING:
4785 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4786 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4787 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4792 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4794 switch (mlx5_mig_state) {
4795 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4796 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4797 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4802 static int to_ib_qp_access_flags(int mlx5_flags)
4806 if (mlx5_flags & MLX5_QP_BIT_RRE)
4807 ib_flags |= IB_ACCESS_REMOTE_READ;
4808 if (mlx5_flags & MLX5_QP_BIT_RWE)
4809 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4810 if (mlx5_flags & MLX5_QP_BIT_RAE)
4811 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4816 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4817 struct rdma_ah_attr *ah_attr,
4818 struct mlx5_qp_path *path)
4821 memset(ah_attr, 0, sizeof(*ah_attr));
4823 if (!path->port || path->port > ibdev->num_ports)
4826 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4828 rdma_ah_set_port_num(ah_attr, path->port);
4829 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4831 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4832 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4833 rdma_ah_set_static_rate(ah_attr,
4834 path->static_rate ? path->static_rate - 5 : 0);
4835 if (path->grh_mlid & (1 << 7)) {
4836 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4838 rdma_ah_set_grh(ah_attr, NULL,
4842 (tc_fl >> 20) & 0xff);
4843 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4847 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4848 struct mlx5_ib_sq *sq,
4853 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4856 sq->state = *sq_state;
4862 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4863 struct mlx5_ib_rq *rq,
4871 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4872 out = kvzalloc(inlen, GFP_KERNEL);
4876 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4880 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4881 *rq_state = MLX5_GET(rqc, rqc, state);
4882 rq->state = *rq_state;
4889 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4890 struct mlx5_ib_qp *qp, u8 *qp_state)
4892 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4893 [MLX5_RQC_STATE_RST] = {
4894 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4895 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4896 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4897 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4899 [MLX5_RQC_STATE_RDY] = {
4900 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4901 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4902 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4903 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4905 [MLX5_RQC_STATE_ERR] = {
4906 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4907 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4908 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4909 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4911 [MLX5_RQ_STATE_NA] = {
4912 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4913 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4914 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4915 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4919 *qp_state = sqrq_trans[rq_state][sq_state];
4921 if (*qp_state == MLX5_QP_STATE_BAD) {
4922 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4923 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4924 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4928 if (*qp_state == MLX5_QP_STATE)
4929 *qp_state = qp->state;
4934 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4935 struct mlx5_ib_qp *qp,
4936 u8 *raw_packet_qp_state)
4938 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4939 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4940 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4942 u8 sq_state = MLX5_SQ_STATE_NA;
4943 u8 rq_state = MLX5_RQ_STATE_NA;
4945 if (qp->sq.wqe_cnt) {
4946 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4951 if (qp->rq.wqe_cnt) {
4952 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4957 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4958 raw_packet_qp_state);
4961 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4962 struct ib_qp_attr *qp_attr)
4964 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4965 struct mlx5_qp_context *context;
4970 outb = kzalloc(outlen, GFP_KERNEL);
4974 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4979 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4980 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4982 mlx5_state = be32_to_cpu(context->flags) >> 28;
4984 qp->state = to_ib_qp_state(mlx5_state);
4985 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4986 qp_attr->path_mig_state =
4987 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4988 qp_attr->qkey = be32_to_cpu(context->qkey);
4989 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4990 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4991 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4992 qp_attr->qp_access_flags =
4993 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4995 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4996 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4997 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4998 qp_attr->alt_pkey_index =
4999 be16_to_cpu(context->alt_path.pkey_index);
5000 qp_attr->alt_port_num =
5001 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5004 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5005 qp_attr->port_num = context->pri_path.port;
5007 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5008 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5010 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5012 qp_attr->max_dest_rd_atomic =
5013 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5014 qp_attr->min_rnr_timer =
5015 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5016 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5017 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5018 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5019 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
5026 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5027 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5028 struct ib_qp_init_attr *qp_init_attr)
5030 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5032 u32 access_flags = 0;
5033 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5036 int supported_mask = IB_QP_STATE |
5037 IB_QP_ACCESS_FLAGS |
5039 IB_QP_MIN_RNR_TIMER |
5044 if (qp_attr_mask & ~supported_mask)
5046 if (mqp->state != IB_QPS_RTR)
5049 out = kzalloc(outlen, GFP_KERNEL);
5053 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5057 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5059 if (qp_attr_mask & IB_QP_STATE)
5060 qp_attr->qp_state = IB_QPS_RTR;
5062 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5063 if (MLX5_GET(dctc, dctc, rre))
5064 access_flags |= IB_ACCESS_REMOTE_READ;
5065 if (MLX5_GET(dctc, dctc, rwe))
5066 access_flags |= IB_ACCESS_REMOTE_WRITE;
5067 if (MLX5_GET(dctc, dctc, rae))
5068 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5069 qp_attr->qp_access_flags = access_flags;
5072 if (qp_attr_mask & IB_QP_PORT)
5073 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5074 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5075 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5076 if (qp_attr_mask & IB_QP_AV) {
5077 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5078 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5079 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5080 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5082 if (qp_attr_mask & IB_QP_PATH_MTU)
5083 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5084 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5085 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5091 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5092 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5094 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5095 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5097 u8 raw_packet_qp_state;
5099 if (ibqp->rwq_ind_tbl)
5102 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5103 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5106 /* Not all of output fields are applicable, make sure to zero them */
5107 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5108 memset(qp_attr, 0, sizeof(*qp_attr));
5110 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5111 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5112 qp_attr_mask, qp_init_attr);
5114 mutex_lock(&qp->mutex);
5116 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5117 qp->flags & MLX5_IB_QP_UNDERLAY) {
5118 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5121 qp->state = raw_packet_qp_state;
5122 qp_attr->port_num = 1;
5124 err = query_qp_attr(dev, qp, qp_attr);
5129 qp_attr->qp_state = qp->state;
5130 qp_attr->cur_qp_state = qp_attr->qp_state;
5131 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5132 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5134 if (!ibqp->uobject) {
5135 qp_attr->cap.max_send_wr = qp->sq.max_post;
5136 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5137 qp_init_attr->qp_context = ibqp->qp_context;
5139 qp_attr->cap.max_send_wr = 0;
5140 qp_attr->cap.max_send_sge = 0;
5143 qp_init_attr->qp_type = ibqp->qp_type;
5144 qp_init_attr->recv_cq = ibqp->recv_cq;
5145 qp_init_attr->send_cq = ibqp->send_cq;
5146 qp_init_attr->srq = ibqp->srq;
5147 qp_attr->cap.max_inline_data = qp->max_inline_data;
5149 qp_init_attr->cap = qp_attr->cap;
5151 qp_init_attr->create_flags = 0;
5152 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5153 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5155 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5156 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5157 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5158 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5159 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5160 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5161 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5162 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5164 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5165 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5168 mutex_unlock(&qp->mutex);
5172 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5173 struct ib_ucontext *context,
5174 struct ib_udata *udata)
5176 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5177 struct mlx5_ib_xrcd *xrcd;
5180 if (!MLX5_CAP_GEN(dev->mdev, xrc))
5181 return ERR_PTR(-ENOSYS);
5183 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5185 return ERR_PTR(-ENOMEM);
5187 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
5190 return ERR_PTR(-ENOMEM);
5193 return &xrcd->ibxrcd;
5196 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5198 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5199 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5202 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
5204 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5210 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5212 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5213 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5214 struct ib_event event;
5216 if (rwq->ibwq.event_handler) {
5217 event.device = rwq->ibwq.device;
5218 event.element.wq = &rwq->ibwq;
5220 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5221 event.event = IB_EVENT_WQ_FATAL;
5224 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5228 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5232 static int set_delay_drop(struct mlx5_ib_dev *dev)
5236 mutex_lock(&dev->delay_drop.lock);
5237 if (dev->delay_drop.activate)
5240 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5244 dev->delay_drop.activate = true;
5246 mutex_unlock(&dev->delay_drop.lock);
5249 atomic_inc(&dev->delay_drop.rqs_cnt);
5253 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5254 struct ib_wq_init_attr *init_attr)
5256 struct mlx5_ib_dev *dev;
5257 int has_net_offloads;
5265 dev = to_mdev(pd->device);
5267 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5268 in = kvzalloc(inlen, GFP_KERNEL);
5272 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5273 MLX5_SET(rqc, rqc, mem_rq_type,
5274 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5275 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5276 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5277 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5278 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5279 wq = MLX5_ADDR_OF(rqc, rqc, wq);
5280 MLX5_SET(wq, wq, wq_type,
5281 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5282 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5283 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5284 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5285 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5289 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5292 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5293 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5294 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5295 MLX5_SET(wq, wq, log_wqe_stride_size,
5296 rwq->single_stride_log_num_of_bytes -
5297 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5298 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5299 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5301 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5302 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5303 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5304 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5305 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5306 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5307 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5308 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5309 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5310 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5315 MLX5_SET(rqc, rqc, vsd, 1);
5317 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5318 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5319 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5323 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5325 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5326 if (!(dev->ib_dev.attrs.raw_packet_caps &
5327 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5328 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5332 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5334 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5335 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5336 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5337 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5338 err = set_delay_drop(dev);
5340 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5342 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5344 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5352 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5353 struct ib_wq_init_attr *wq_init_attr,
5354 struct mlx5_ib_create_wq *ucmd,
5355 struct mlx5_ib_rwq *rwq)
5357 /* Sanity check RQ size before proceeding */
5358 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5361 if (!ucmd->rq_wqe_count)
5364 rwq->wqe_count = ucmd->rq_wqe_count;
5365 rwq->wqe_shift = ucmd->rq_wqe_shift;
5366 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
5367 rwq->log_rq_stride = rwq->wqe_shift;
5368 rwq->log_rq_size = ilog2(rwq->wqe_count);
5372 static int prepare_user_rq(struct ib_pd *pd,
5373 struct ib_wq_init_attr *init_attr,
5374 struct ib_udata *udata,
5375 struct mlx5_ib_rwq *rwq)
5377 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5378 struct mlx5_ib_create_wq ucmd = {};
5380 size_t required_cmd_sz;
5382 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5383 + sizeof(ucmd.single_stride_log_num_of_bytes);
5384 if (udata->inlen < required_cmd_sz) {
5385 mlx5_ib_dbg(dev, "invalid inlen\n");
5389 if (udata->inlen > sizeof(ucmd) &&
5390 !ib_is_udata_cleared(udata, sizeof(ucmd),
5391 udata->inlen - sizeof(ucmd))) {
5392 mlx5_ib_dbg(dev, "inlen is not supported\n");
5396 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5397 mlx5_ib_dbg(dev, "copy failed\n");
5401 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5402 mlx5_ib_dbg(dev, "invalid comp mask\n");
5404 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5405 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5406 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5409 if ((ucmd.single_stride_log_num_of_bytes <
5410 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5411 (ucmd.single_stride_log_num_of_bytes >
5412 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5413 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5414 ucmd.single_stride_log_num_of_bytes,
5415 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5416 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5419 if ((ucmd.single_wqe_log_num_of_strides >
5420 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5421 (ucmd.single_wqe_log_num_of_strides <
5422 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5423 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5424 ucmd.single_wqe_log_num_of_strides,
5425 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5426 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5429 rwq->single_stride_log_num_of_bytes =
5430 ucmd.single_stride_log_num_of_bytes;
5431 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5432 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5433 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5436 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5438 mlx5_ib_dbg(dev, "err %d\n", err);
5442 err = create_user_rq(dev, pd, rwq, &ucmd);
5444 mlx5_ib_dbg(dev, "err %d\n", err);
5449 rwq->user_index = ucmd.user_index;
5453 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5454 struct ib_wq_init_attr *init_attr,
5455 struct ib_udata *udata)
5457 struct mlx5_ib_dev *dev;
5458 struct mlx5_ib_rwq *rwq;
5459 struct mlx5_ib_create_wq_resp resp = {};
5460 size_t min_resp_len;
5464 return ERR_PTR(-ENOSYS);
5466 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5467 if (udata->outlen && udata->outlen < min_resp_len)
5468 return ERR_PTR(-EINVAL);
5470 dev = to_mdev(pd->device);
5471 switch (init_attr->wq_type) {
5473 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5475 return ERR_PTR(-ENOMEM);
5476 err = prepare_user_rq(pd, init_attr, udata, rwq);
5479 err = create_rq(rwq, pd, init_attr);
5484 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5485 init_attr->wq_type);
5486 return ERR_PTR(-EINVAL);
5489 rwq->ibwq.wq_num = rwq->core_qp.qpn;
5490 rwq->ibwq.state = IB_WQS_RESET;
5491 if (udata->outlen) {
5492 resp.response_length = offsetof(typeof(resp), response_length) +
5493 sizeof(resp.response_length);
5494 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5499 rwq->core_qp.event = mlx5_ib_wq_event;
5500 rwq->ibwq.event_handler = init_attr->event_handler;
5504 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5506 destroy_user_rq(dev, pd, rwq);
5509 return ERR_PTR(err);
5512 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5514 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5515 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5517 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5518 destroy_user_rq(dev, wq->pd, rwq);
5524 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5525 struct ib_rwq_ind_table_init_attr *init_attr,
5526 struct ib_udata *udata)
5528 struct mlx5_ib_dev *dev = to_mdev(device);
5529 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5530 int sz = 1 << init_attr->log_ind_tbl_size;
5531 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5532 size_t min_resp_len;
5539 if (udata->inlen > 0 &&
5540 !ib_is_udata_cleared(udata, 0,
5542 return ERR_PTR(-EOPNOTSUPP);
5544 if (init_attr->log_ind_tbl_size >
5545 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5546 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5547 init_attr->log_ind_tbl_size,
5548 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5549 return ERR_PTR(-EINVAL);
5552 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5553 if (udata->outlen && udata->outlen < min_resp_len)
5554 return ERR_PTR(-EINVAL);
5556 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5558 return ERR_PTR(-ENOMEM);
5560 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5561 in = kvzalloc(inlen, GFP_KERNEL);
5567 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5569 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5570 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5572 for (i = 0; i < sz; i++)
5573 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5575 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5581 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5582 if (udata->outlen) {
5583 resp.response_length = offsetof(typeof(resp), response_length) +
5584 sizeof(resp.response_length);
5585 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5590 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5593 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5596 return ERR_PTR(err);
5599 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5601 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5602 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5604 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5610 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5611 u32 wq_attr_mask, struct ib_udata *udata)
5613 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5614 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5615 struct mlx5_ib_modify_wq ucmd = {};
5616 size_t required_cmd_sz;
5624 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5625 if (udata->inlen < required_cmd_sz)
5628 if (udata->inlen > sizeof(ucmd) &&
5629 !ib_is_udata_cleared(udata, sizeof(ucmd),
5630 udata->inlen - sizeof(ucmd)))
5633 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5636 if (ucmd.comp_mask || ucmd.reserved)
5639 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5640 in = kvzalloc(inlen, GFP_KERNEL);
5644 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5646 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5647 wq_attr->curr_wq_state : wq->state;
5648 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5649 wq_attr->wq_state : curr_wq_state;
5650 if (curr_wq_state == IB_WQS_ERR)
5651 curr_wq_state = MLX5_RQC_STATE_ERR;
5652 if (wq_state == IB_WQS_ERR)
5653 wq_state = MLX5_RQC_STATE_ERR;
5654 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5655 MLX5_SET(rqc, rqc, state, wq_state);
5657 if (wq_attr_mask & IB_WQ_FLAGS) {
5658 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5659 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5660 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5661 mlx5_ib_dbg(dev, "VLAN offloads are not "
5666 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5667 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5668 MLX5_SET(rqc, rqc, vsd,
5669 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5672 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5673 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5679 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5680 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5681 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5682 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5683 MLX5_SET(rqc, rqc, counter_set_id,
5684 dev->port->cnts.set_id);
5686 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5690 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5692 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;