2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
41 /* not supported currently */
42 static int wq_signature;
45 MLX5_IB_ACK_REQ_FREQ = 8,
49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
51 MLX5_IB_LINK_TYPE_IB = 0,
52 MLX5_IB_LINK_TYPE_ETH = 1
56 MLX5_IB_SQ_STRIDE = 6,
57 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
60 static const u32 mlx5_ib_opcode[] = {
61 [IB_WR_SEND] = MLX5_OPCODE_SEND,
62 [IB_WR_LSO] = MLX5_OPCODE_LSO,
63 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
64 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
65 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
66 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
67 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
68 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
69 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
70 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
71 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
72 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
73 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
74 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
77 struct mlx5_wqe_eth_pad {
81 enum raw_qp_set_mask_map {
82 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
83 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
86 struct mlx5_modify_raw_qp_param {
89 u32 set_mask; /* raw_qp_set_mask_map */
91 struct mlx5_rate_limit rl;
96 static void get_cqs(enum ib_qp_type qp_type,
97 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
98 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
100 static int is_qp0(enum ib_qp_type qp_type)
102 return qp_type == IB_QPT_SMI;
105 static int is_sqp(enum ib_qp_type qp_type)
107 return is_qp0(qp_type) || is_qp1(qp_type);
110 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
112 return mlx5_buf_offset(&qp->buf, offset);
115 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
117 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
120 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
122 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
126 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
128 * @qp: QP to copy from.
129 * @send: copy from the send queue when non-zero, use the receive queue
131 * @wqe_index: index to start copying from. For send work queues, the
132 * wqe_index is in units of MLX5_SEND_WQE_BB.
133 * For receive work queue, it is the number of work queue
134 * element in the queue.
135 * @buffer: destination buffer.
136 * @length: maximum number of bytes to copy.
138 * Copies at least a single WQE, but may copy more data.
140 * Return: the number of bytes copied, or an error code.
142 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
143 void *buffer, u32 length,
144 struct mlx5_ib_qp_base *base)
146 struct ib_device *ibdev = qp->ibqp.device;
147 struct mlx5_ib_dev *dev = to_mdev(ibdev);
148 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
151 struct ib_umem *umem = base->ubuffer.umem;
152 u32 first_copy_length;
156 if (wq->wqe_cnt == 0) {
157 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
162 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
163 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
165 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
168 if (offset > umem->length ||
169 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
172 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
173 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
178 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
179 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
181 wqe_length = ds * MLX5_WQE_DS_UNITS;
183 wqe_length = 1 << wq->wqe_shift;
186 if (wqe_length <= first_copy_length)
187 return first_copy_length;
189 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
190 wqe_length - first_copy_length);
197 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
199 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
200 struct ib_event event;
202 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
203 /* This event is only valid for trans_qps */
204 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
207 if (ibqp->event_handler) {
208 event.device = ibqp->device;
209 event.element.qp = ibqp;
211 case MLX5_EVENT_TYPE_PATH_MIG:
212 event.event = IB_EVENT_PATH_MIG;
214 case MLX5_EVENT_TYPE_COMM_EST:
215 event.event = IB_EVENT_COMM_EST;
217 case MLX5_EVENT_TYPE_SQ_DRAINED:
218 event.event = IB_EVENT_SQ_DRAINED;
220 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
221 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
223 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
224 event.event = IB_EVENT_QP_FATAL;
226 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
227 event.event = IB_EVENT_PATH_MIG_ERR;
229 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
230 event.event = IB_EVENT_QP_REQ_ERR;
232 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
233 event.event = IB_EVENT_QP_ACCESS_ERR;
236 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
240 ibqp->event_handler(&event, ibqp->qp_context);
244 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
245 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
250 /* Sanity check RQ size before proceeding */
251 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
257 qp->rq.wqe_shift = 0;
258 cap->max_recv_wr = 0;
259 cap->max_recv_sge = 0;
262 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
263 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
265 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
266 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
268 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
269 qp->rq.max_post = qp->rq.wqe_cnt;
271 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
272 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
273 wqe_size = roundup_pow_of_two(wqe_size);
274 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
275 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
276 qp->rq.wqe_cnt = wq_size / wqe_size;
277 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
278 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
280 MLX5_CAP_GEN(dev->mdev,
284 qp->rq.wqe_shift = ilog2(wqe_size);
285 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
286 qp->rq.max_post = qp->rq.wqe_cnt;
293 static int sq_overhead(struct ib_qp_init_attr *attr)
297 switch (attr->qp_type) {
299 size += sizeof(struct mlx5_wqe_xrc_seg);
302 size += sizeof(struct mlx5_wqe_ctrl_seg) +
303 max(sizeof(struct mlx5_wqe_atomic_seg) +
304 sizeof(struct mlx5_wqe_raddr_seg),
305 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
306 sizeof(struct mlx5_mkey_seg) +
307 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
308 MLX5_IB_UMR_OCTOWORD);
315 size += sizeof(struct mlx5_wqe_ctrl_seg) +
316 max(sizeof(struct mlx5_wqe_raddr_seg),
317 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
318 sizeof(struct mlx5_mkey_seg));
322 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
323 size += sizeof(struct mlx5_wqe_eth_pad) +
324 sizeof(struct mlx5_wqe_eth_seg);
327 case MLX5_IB_QPT_HW_GSI:
328 size += sizeof(struct mlx5_wqe_ctrl_seg) +
329 sizeof(struct mlx5_wqe_datagram_seg);
332 case MLX5_IB_QPT_REG_UMR:
333 size += sizeof(struct mlx5_wqe_ctrl_seg) +
334 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
335 sizeof(struct mlx5_mkey_seg);
345 static int calc_send_wqe(struct ib_qp_init_attr *attr)
350 size = sq_overhead(attr);
354 if (attr->cap.max_inline_data) {
355 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
356 attr->cap.max_inline_data;
359 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
360 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
361 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
362 return MLX5_SIG_WQE_SIZE;
364 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
367 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
371 if (attr->qp_type == IB_QPT_RC)
372 max_sge = (min_t(int, wqe_size, 512) -
373 sizeof(struct mlx5_wqe_ctrl_seg) -
374 sizeof(struct mlx5_wqe_raddr_seg)) /
375 sizeof(struct mlx5_wqe_data_seg);
376 else if (attr->qp_type == IB_QPT_XRC_INI)
377 max_sge = (min_t(int, wqe_size, 512) -
378 sizeof(struct mlx5_wqe_ctrl_seg) -
379 sizeof(struct mlx5_wqe_xrc_seg) -
380 sizeof(struct mlx5_wqe_raddr_seg)) /
381 sizeof(struct mlx5_wqe_data_seg);
383 max_sge = (wqe_size - sq_overhead(attr)) /
384 sizeof(struct mlx5_wqe_data_seg);
386 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
387 sizeof(struct mlx5_wqe_data_seg));
390 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
391 struct mlx5_ib_qp *qp)
396 if (!attr->cap.max_send_wr)
399 wqe_size = calc_send_wqe(attr);
400 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
404 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
405 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
406 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
410 qp->max_inline_data = wqe_size - sq_overhead(attr) -
411 sizeof(struct mlx5_wqe_inline_seg);
412 attr->cap.max_inline_data = qp->max_inline_data;
414 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
415 qp->signature_en = true;
417 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
418 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
419 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
420 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
421 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
423 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
426 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
427 qp->sq.max_gs = get_send_sge(attr, wqe_size);
428 if (qp->sq.max_gs < attr->cap.max_send_sge)
431 attr->cap.max_send_sge = qp->sq.max_gs;
432 qp->sq.max_post = wq_size / wqe_size;
433 attr->cap.max_send_wr = qp->sq.max_post;
438 static int set_user_buf_size(struct mlx5_ib_dev *dev,
439 struct mlx5_ib_qp *qp,
440 struct mlx5_ib_create_qp *ucmd,
441 struct mlx5_ib_qp_base *base,
442 struct ib_qp_init_attr *attr)
444 int desc_sz = 1 << qp->sq.wqe_shift;
446 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
447 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
448 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
452 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
453 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
454 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
458 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
460 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
461 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
463 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
467 if (attr->qp_type == IB_QPT_RAW_PACKET ||
468 qp->flags & MLX5_IB_QP_UNDERLAY) {
469 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
470 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
472 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
473 (qp->sq.wqe_cnt << 6);
479 static int qp_has_rq(struct ib_qp_init_attr *attr)
481 if (attr->qp_type == IB_QPT_XRC_INI ||
482 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
483 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
484 !attr->cap.max_recv_wr)
491 /* this is the first blue flame register in the array of bfregs assigned
492 * to a processes. Since we do not use it for blue flame but rather
493 * regular 64 bit doorbells, we do not need a lock for maintaiing
496 NUM_NON_BLUE_FLAME_BFREGS = 1,
499 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
501 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
504 static int num_med_bfreg(struct mlx5_ib_dev *dev,
505 struct mlx5_bfreg_info *bfregi)
509 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
510 NUM_NON_BLUE_FLAME_BFREGS;
512 return n >= 0 ? n : 0;
515 static int first_med_bfreg(struct mlx5_ib_dev *dev,
516 struct mlx5_bfreg_info *bfregi)
518 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
521 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
522 struct mlx5_bfreg_info *bfregi)
526 med = num_med_bfreg(dev, bfregi);
530 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
531 struct mlx5_bfreg_info *bfregi)
535 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
536 if (!bfregi->count[i]) {
545 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
546 struct mlx5_bfreg_info *bfregi)
548 int minidx = first_med_bfreg(dev, bfregi);
554 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
555 if (bfregi->count[i] < bfregi->count[minidx])
557 if (!bfregi->count[minidx])
561 bfregi->count[minidx]++;
565 static int alloc_bfreg(struct mlx5_ib_dev *dev,
566 struct mlx5_bfreg_info *bfregi,
567 enum mlx5_ib_latency_class lat)
569 int bfregn = -EINVAL;
571 mutex_lock(&bfregi->lock);
573 case MLX5_IB_LATENCY_CLASS_LOW:
574 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
576 bfregi->count[bfregn]++;
579 case MLX5_IB_LATENCY_CLASS_MEDIUM:
583 bfregn = alloc_med_class_bfreg(dev, bfregi);
586 case MLX5_IB_LATENCY_CLASS_HIGH:
590 bfregn = alloc_high_class_bfreg(dev, bfregi);
593 mutex_unlock(&bfregi->lock);
598 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
600 mutex_lock(&bfregi->lock);
601 bfregi->count[bfregn]--;
602 mutex_unlock(&bfregi->lock);
605 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
608 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
609 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
610 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
611 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
612 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
613 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
614 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
619 static int to_mlx5_st(enum ib_qp_type type)
622 case IB_QPT_RC: return MLX5_QP_ST_RC;
623 case IB_QPT_UC: return MLX5_QP_ST_UC;
624 case IB_QPT_UD: return MLX5_QP_ST_UD;
625 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
627 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
628 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
629 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
630 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
631 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
632 case IB_QPT_RAW_PACKET:
633 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
635 default: return -EINVAL;
639 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
640 struct mlx5_ib_cq *recv_cq);
641 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
642 struct mlx5_ib_cq *recv_cq);
644 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
645 struct mlx5_bfreg_info *bfregi, int bfregn,
648 int bfregs_per_sys_page;
649 int index_of_sys_page;
652 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
653 MLX5_NON_FP_BFREGS_PER_UAR;
654 index_of_sys_page = bfregn / bfregs_per_sys_page;
657 index_of_sys_page += bfregi->num_static_sys_pages;
658 if (bfregn > bfregi->num_dyn_bfregs ||
659 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
660 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
665 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
666 return bfregi->sys_pages[index_of_sys_page] + offset;
669 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
671 unsigned long addr, size_t size,
672 struct ib_umem **umem,
673 int *npages, int *page_shift, int *ncont,
678 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
680 mlx5_ib_dbg(dev, "umem_get failed\n");
681 return PTR_ERR(*umem);
684 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
686 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
688 mlx5_ib_warn(dev, "bad offset\n");
692 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
693 addr, size, *npages, *page_shift, *ncont, *offset);
698 ib_umem_release(*umem);
704 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
705 struct mlx5_ib_rwq *rwq)
707 struct mlx5_ib_ucontext *context;
709 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
710 atomic_dec(&dev->delay_drop.rqs_cnt);
712 context = to_mucontext(pd->uobject->context);
713 mlx5_ib_db_unmap_user(context, &rwq->db);
715 ib_umem_release(rwq->umem);
718 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
719 struct mlx5_ib_rwq *rwq,
720 struct mlx5_ib_create_wq *ucmd)
722 struct mlx5_ib_ucontext *context;
732 context = to_mucontext(pd->uobject->context);
733 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
734 rwq->buf_size, 0, 0);
735 if (IS_ERR(rwq->umem)) {
736 mlx5_ib_dbg(dev, "umem_get failed\n");
737 err = PTR_ERR(rwq->umem);
741 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
743 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
744 &rwq->rq_page_offset);
746 mlx5_ib_warn(dev, "bad offset\n");
750 rwq->rq_num_pas = ncont;
751 rwq->page_shift = page_shift;
752 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
753 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
755 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
756 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
757 npages, page_shift, ncont, offset);
759 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
761 mlx5_ib_dbg(dev, "map failed\n");
765 rwq->create_type = MLX5_WQ_USER;
769 ib_umem_release(rwq->umem);
773 static int adjust_bfregn(struct mlx5_ib_dev *dev,
774 struct mlx5_bfreg_info *bfregi, int bfregn)
776 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
777 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
780 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
781 struct mlx5_ib_qp *qp, struct ib_udata *udata,
782 struct ib_qp_init_attr *attr,
784 struct mlx5_ib_create_qp_resp *resp, int *inlen,
785 struct mlx5_ib_qp_base *base)
787 struct mlx5_ib_ucontext *context;
788 struct mlx5_ib_create_qp ucmd;
789 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
800 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
802 mlx5_ib_dbg(dev, "copy failed\n");
806 context = to_mucontext(pd->uobject->context);
807 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
808 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
809 ucmd.bfreg_index, true);
813 bfregn = MLX5_IB_INVALID_BFREG;
814 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
816 * TBD: should come from the verbs when we have the API
818 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
819 bfregn = MLX5_CROSS_CHANNEL_BFREG;
822 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
824 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
825 mlx5_ib_dbg(dev, "reverting to medium latency\n");
826 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
828 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
829 mlx5_ib_dbg(dev, "reverting to high latency\n");
830 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
832 mlx5_ib_warn(dev, "bfreg allocation failed\n");
839 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
840 if (bfregn != MLX5_IB_INVALID_BFREG)
841 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
845 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
846 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
848 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
852 if (ucmd.buf_addr && ubuffer->buf_size) {
853 ubuffer->buf_addr = ucmd.buf_addr;
854 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
856 &ubuffer->umem, &npages, &page_shift,
861 ubuffer->umem = NULL;
864 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
865 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
866 *in = kvzalloc(*inlen, GFP_KERNEL);
872 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
874 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
876 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
878 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
879 MLX5_SET(qpc, qpc, page_offset, offset);
881 MLX5_SET(qpc, qpc, uar_page, uar_index);
882 if (bfregn != MLX5_IB_INVALID_BFREG)
883 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
885 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
888 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
890 mlx5_ib_dbg(dev, "map failed\n");
894 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
896 mlx5_ib_dbg(dev, "copy failed\n");
899 qp->create_type = MLX5_QP_USER;
904 mlx5_ib_db_unmap_user(context, &qp->db);
911 ib_umem_release(ubuffer->umem);
914 if (bfregn != MLX5_IB_INVALID_BFREG)
915 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
919 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
920 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
922 struct mlx5_ib_ucontext *context;
924 context = to_mucontext(pd->uobject->context);
925 mlx5_ib_db_unmap_user(context, &qp->db);
926 if (base->ubuffer.umem)
927 ib_umem_release(base->ubuffer.umem);
930 * Free only the BFREGs which are handled by the kernel.
931 * BFREGs of UARs allocated dynamically are handled by user.
933 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
934 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
937 static int create_kernel_qp(struct mlx5_ib_dev *dev,
938 struct ib_qp_init_attr *init_attr,
939 struct mlx5_ib_qp *qp,
940 u32 **in, int *inlen,
941 struct mlx5_ib_qp_base *base)
947 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
948 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
949 IB_QP_CREATE_IPOIB_UD_LSO |
950 IB_QP_CREATE_NETIF_QP |
951 mlx5_ib_create_qp_sqpn_qp1()))
954 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
955 qp->bf.bfreg = &dev->fp_bfreg;
957 qp->bf.bfreg = &dev->bfreg;
959 /* We need to divide by two since each register is comprised of
960 * two buffers of identical size, namely odd and even
962 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
963 uar_index = qp->bf.bfreg->index;
965 err = calc_sq_size(dev, init_attr, qp);
967 mlx5_ib_dbg(dev, "err %d\n", err);
972 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
973 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
975 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
977 mlx5_ib_dbg(dev, "err %d\n", err);
981 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
982 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
983 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
984 *in = kvzalloc(*inlen, GFP_KERNEL);
990 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
991 MLX5_SET(qpc, qpc, uar_page, uar_index);
992 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
994 /* Set "fast registration enabled" for all kernel QPs */
995 MLX5_SET(qpc, qpc, fre, 1);
996 MLX5_SET(qpc, qpc, rlky, 1);
998 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
999 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1000 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1003 mlx5_fill_page_array(&qp->buf,
1004 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
1006 err = mlx5_db_alloc(dev->mdev, &qp->db);
1008 mlx5_ib_dbg(dev, "err %d\n", err);
1012 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1013 sizeof(*qp->sq.wrid), GFP_KERNEL);
1014 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1015 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1016 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1017 sizeof(*qp->rq.wrid), GFP_KERNEL);
1018 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1019 sizeof(*qp->sq.w_list), GFP_KERNEL);
1020 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1021 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1023 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1024 !qp->sq.w_list || !qp->sq.wqe_head) {
1028 qp->create_type = MLX5_QP_KERNEL;
1033 kvfree(qp->sq.wqe_head);
1034 kvfree(qp->sq.w_list);
1035 kvfree(qp->sq.wrid);
1036 kvfree(qp->sq.wr_data);
1037 kvfree(qp->rq.wrid);
1038 mlx5_db_free(dev->mdev, &qp->db);
1044 mlx5_buf_free(dev->mdev, &qp->buf);
1048 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1050 kvfree(qp->sq.wqe_head);
1051 kvfree(qp->sq.w_list);
1052 kvfree(qp->sq.wrid);
1053 kvfree(qp->sq.wr_data);
1054 kvfree(qp->rq.wrid);
1055 mlx5_db_free(dev->mdev, &qp->db);
1056 mlx5_buf_free(dev->mdev, &qp->buf);
1059 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1061 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1062 (attr->qp_type == MLX5_IB_QPT_DCI) ||
1063 (attr->qp_type == IB_QPT_XRC_INI))
1065 else if (!qp->has_rq)
1066 return MLX5_ZERO_LEN_RQ;
1068 return MLX5_NON_ZERO_RQ;
1071 static int is_connected(enum ib_qp_type qp_type)
1073 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1079 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1080 struct mlx5_ib_qp *qp,
1081 struct mlx5_ib_sq *sq, u32 tdn)
1083 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1084 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1086 MLX5_SET(tisc, tisc, transport_domain, tdn);
1087 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1088 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1090 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1093 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1094 struct mlx5_ib_sq *sq)
1096 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1099 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1100 struct mlx5_ib_sq *sq)
1103 mlx5_del_flow_rules(sq->flow_rule);
1106 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1107 struct mlx5_ib_sq *sq, void *qpin,
1110 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1114 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1123 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1124 &sq->ubuffer.umem, &npages, &page_shift,
1129 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1130 in = kvzalloc(inlen, GFP_KERNEL);
1136 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1137 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1138 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1139 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1140 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1141 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1142 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1143 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1144 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1145 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1146 MLX5_CAP_ETH(dev->mdev, swp))
1147 MLX5_SET(sqc, sqc, allow_swp, 1);
1149 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1150 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1151 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1152 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1153 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1154 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1155 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1156 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1157 MLX5_SET(wq, wq, page_offset, offset);
1159 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1160 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1162 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1169 err = create_flow_rule_vport_sq(dev, sq);
1176 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1179 ib_umem_release(sq->ubuffer.umem);
1180 sq->ubuffer.umem = NULL;
1185 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1186 struct mlx5_ib_sq *sq)
1188 destroy_flow_rule_vport_sq(dev, sq);
1189 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1190 ib_umem_release(sq->ubuffer.umem);
1193 static size_t get_rq_pas_size(void *qpc)
1195 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1196 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1197 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1198 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1199 u32 po_quanta = 1 << (log_page_size - 6);
1200 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1201 u32 page_size = 1 << log_page_size;
1202 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1203 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1205 return rq_num_pas * sizeof(u64);
1208 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1209 struct mlx5_ib_rq *rq, void *qpin,
1212 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1218 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1219 size_t rq_pas_size = get_rq_pas_size(qpc);
1223 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1226 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1227 in = kvzalloc(inlen, GFP_KERNEL);
1231 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1232 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1233 MLX5_SET(rqc, rqc, vsd, 1);
1234 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1235 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1236 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1237 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1238 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1240 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1241 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1243 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1244 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1245 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1246 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1247 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1248 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1249 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1250 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1251 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1252 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1254 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1255 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1256 memcpy(pas, qp_pas, rq_pas_size);
1258 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1265 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1266 struct mlx5_ib_rq *rq)
1268 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1271 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1273 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1274 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1275 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1278 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1279 struct mlx5_ib_rq *rq, u32 tdn,
1280 bool tunnel_offload_en)
1287 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1288 in = kvzalloc(inlen, GFP_KERNEL);
1292 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1293 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1294 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1295 MLX5_SET(tirc, tirc, transport_domain, tdn);
1296 if (tunnel_offload_en)
1297 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1300 MLX5_SET(tirc, tirc, self_lb_block,
1301 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1303 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1310 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1311 struct mlx5_ib_rq *rq)
1313 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1316 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1317 u32 *in, size_t inlen,
1320 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1321 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1322 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1323 struct ib_uobject *uobj = pd->uobject;
1324 struct ib_ucontext *ucontext = uobj->context;
1325 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1327 u32 tdn = mucontext->tdn;
1329 if (qp->sq.wqe_cnt) {
1330 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1334 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1336 goto err_destroy_tis;
1338 sq->base.container_mibqp = qp;
1339 sq->base.mqp.event = mlx5_ib_qp_event;
1342 if (qp->rq.wqe_cnt) {
1343 rq->base.container_mibqp = qp;
1345 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1346 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1347 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1348 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1349 err = create_raw_packet_qp_rq(dev, rq, in, inlen);
1351 goto err_destroy_sq;
1354 err = create_raw_packet_qp_tir(dev, rq, tdn,
1355 qp->tunnel_offload_en);
1357 goto err_destroy_rq;
1360 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1366 destroy_raw_packet_qp_rq(dev, rq);
1368 if (!qp->sq.wqe_cnt)
1370 destroy_raw_packet_qp_sq(dev, sq);
1372 destroy_raw_packet_qp_tis(dev, sq);
1377 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1378 struct mlx5_ib_qp *qp)
1380 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1381 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1382 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1384 if (qp->rq.wqe_cnt) {
1385 destroy_raw_packet_qp_tir(dev, rq);
1386 destroy_raw_packet_qp_rq(dev, rq);
1389 if (qp->sq.wqe_cnt) {
1390 destroy_raw_packet_qp_sq(dev, sq);
1391 destroy_raw_packet_qp_tis(dev, sq);
1395 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1396 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1398 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1399 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1403 sq->doorbell = &qp->db;
1404 rq->doorbell = &qp->db;
1407 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1409 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1412 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1414 struct ib_qp_init_attr *init_attr,
1415 struct ib_udata *udata)
1417 struct ib_uobject *uobj = pd->uobject;
1418 struct ib_ucontext *ucontext = uobj->context;
1419 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1420 struct mlx5_ib_create_qp_resp resp = {};
1426 u32 selected_fields = 0;
1428 size_t min_resp_len;
1429 u32 tdn = mucontext->tdn;
1430 struct mlx5_ib_create_qp_rss ucmd = {};
1431 size_t required_cmd_sz;
1433 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1436 if (init_attr->create_flags || init_attr->send_cq)
1439 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1440 if (udata->outlen < min_resp_len)
1443 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1444 if (udata->inlen < required_cmd_sz) {
1445 mlx5_ib_dbg(dev, "invalid inlen\n");
1449 if (udata->inlen > sizeof(ucmd) &&
1450 !ib_is_udata_cleared(udata, sizeof(ucmd),
1451 udata->inlen - sizeof(ucmd))) {
1452 mlx5_ib_dbg(dev, "inlen is not supported\n");
1456 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1457 mlx5_ib_dbg(dev, "copy failed\n");
1461 if (ucmd.comp_mask) {
1462 mlx5_ib_dbg(dev, "invalid comp mask\n");
1466 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1467 mlx5_ib_dbg(dev, "invalid flags\n");
1471 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1472 !tunnel_offload_supported(dev->mdev)) {
1473 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1477 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1478 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1479 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1483 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1485 mlx5_ib_dbg(dev, "copy failed\n");
1489 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1490 in = kvzalloc(inlen, GFP_KERNEL);
1494 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1495 MLX5_SET(tirc, tirc, disp_type,
1496 MLX5_TIRC_DISP_TYPE_INDIRECT);
1497 MLX5_SET(tirc, tirc, indirect_table,
1498 init_attr->rwq_ind_tbl->ind_tbl_num);
1499 MLX5_SET(tirc, tirc, transport_domain, tdn);
1501 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1503 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1504 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1506 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1507 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1509 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1511 switch (ucmd.rx_hash_function) {
1512 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1514 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1515 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1517 if (len != ucmd.rx_key_len) {
1522 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1523 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1524 memcpy(rss_key, ucmd.rx_hash_key, len);
1532 if (!ucmd.rx_hash_fields_mask) {
1533 /* special case when this TIR serves as steering entry without hashing */
1534 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1540 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1541 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1542 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1543 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1548 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1549 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1550 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1551 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1552 MLX5_L3_PROT_TYPE_IPV4);
1553 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1554 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1555 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1556 MLX5_L3_PROT_TYPE_IPV6);
1558 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1559 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1560 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1561 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1562 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1564 /* Check that only one l4 protocol is set */
1565 if (outer_l4 & (outer_l4 - 1)) {
1570 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1571 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1572 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1573 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1574 MLX5_L4_PROT_TYPE_TCP);
1575 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1576 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1577 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1578 MLX5_L4_PROT_TYPE_UDP);
1580 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1581 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1582 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1584 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1585 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1586 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1588 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1589 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1590 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1592 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1593 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1594 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1596 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1597 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1599 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1603 MLX5_SET(tirc, tirc, self_lb_block,
1604 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1606 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1612 /* qpn is reserved for that QP */
1613 qp->trans_qp.base.mqp.qpn = 0;
1614 qp->flags |= MLX5_IB_QP_RSS;
1622 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1623 struct ib_qp_init_attr *init_attr,
1624 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1626 struct mlx5_ib_resources *devr = &dev->devr;
1627 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1628 struct mlx5_core_dev *mdev = dev->mdev;
1629 struct mlx5_ib_create_qp_resp resp;
1630 struct mlx5_ib_cq *send_cq;
1631 struct mlx5_ib_cq *recv_cq;
1632 unsigned long flags;
1633 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1634 struct mlx5_ib_create_qp ucmd;
1635 struct mlx5_ib_qp_base *base;
1641 mutex_init(&qp->mutex);
1642 spin_lock_init(&qp->sq.lock);
1643 spin_lock_init(&qp->rq.lock);
1645 mlx5_st = to_mlx5_st(init_attr->qp_type);
1649 if (init_attr->rwq_ind_tbl) {
1653 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1657 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1658 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1659 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1662 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1666 if (init_attr->create_flags &
1667 (IB_QP_CREATE_CROSS_CHANNEL |
1668 IB_QP_CREATE_MANAGED_SEND |
1669 IB_QP_CREATE_MANAGED_RECV)) {
1670 if (!MLX5_CAP_GEN(mdev, cd)) {
1671 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1674 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1675 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1676 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1677 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1678 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1679 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1682 if (init_attr->qp_type == IB_QPT_UD &&
1683 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1684 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1685 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1689 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1690 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1691 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1694 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1695 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1696 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1699 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1702 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1703 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1705 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1706 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1707 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1708 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1710 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1713 if (pd && pd->uobject) {
1714 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1715 mlx5_ib_dbg(dev, "copy failed\n");
1719 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1720 &ucmd, udata->inlen, &uidx);
1724 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1725 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1726 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1727 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1728 !tunnel_offload_supported(mdev)) {
1729 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1732 qp->tunnel_offload_en = true;
1735 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1736 if (init_attr->qp_type != IB_QPT_UD ||
1737 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1738 MLX5_CAP_PORT_TYPE_IB) ||
1739 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1740 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1744 qp->flags |= MLX5_IB_QP_UNDERLAY;
1745 qp->underlay_qpn = init_attr->source_qpn;
1748 qp->wq_sig = !!wq_signature;
1751 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1752 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1753 &qp->raw_packet_qp.rq.base :
1756 qp->has_rq = qp_has_rq(init_attr);
1757 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1758 qp, (pd && pd->uobject) ? &ucmd : NULL);
1760 mlx5_ib_dbg(dev, "err %d\n", err);
1767 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1768 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1769 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1770 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1771 mlx5_ib_dbg(dev, "invalid rq params\n");
1774 if (ucmd.sq_wqe_count > max_wqes) {
1775 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1776 ucmd.sq_wqe_count, max_wqes);
1779 if (init_attr->create_flags &
1780 mlx5_ib_create_qp_sqpn_qp1()) {
1781 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1784 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1785 &resp, &inlen, base);
1787 mlx5_ib_dbg(dev, "err %d\n", err);
1789 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1792 mlx5_ib_dbg(dev, "err %d\n", err);
1798 in = kvzalloc(inlen, GFP_KERNEL);
1802 qp->create_type = MLX5_QP_EMPTY;
1805 if (is_sqp(init_attr->qp_type))
1806 qp->port = init_attr->port_num;
1808 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1810 MLX5_SET(qpc, qpc, st, mlx5_st);
1811 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1813 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1814 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1816 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1820 MLX5_SET(qpc, qpc, wq_signature, 1);
1822 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1823 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1825 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1826 MLX5_SET(qpc, qpc, cd_master, 1);
1827 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1828 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1829 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1830 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1832 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1836 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1837 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1840 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1842 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1844 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1846 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1848 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1852 if (qp->rq.wqe_cnt) {
1853 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1854 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1857 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1859 if (qp->sq.wqe_cnt) {
1860 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1862 MLX5_SET(qpc, qpc, no_sq, 1);
1863 if (init_attr->srq &&
1864 init_attr->srq->srq_type == IB_SRQT_TM)
1865 MLX5_SET(qpc, qpc, offload_type,
1866 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1869 /* Set default resources */
1870 switch (init_attr->qp_type) {
1871 case IB_QPT_XRC_TGT:
1872 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1873 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1874 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1875 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1877 case IB_QPT_XRC_INI:
1878 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1879 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1880 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1883 if (init_attr->srq) {
1884 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1885 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1887 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1888 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1892 if (init_attr->send_cq)
1893 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1895 if (init_attr->recv_cq)
1896 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1898 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1900 /* 0xffffff means we ask to work with cqe version 0 */
1901 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1902 MLX5_SET(qpc, qpc, user_index, uidx);
1904 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1905 if (init_attr->qp_type == IB_QPT_UD &&
1906 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1907 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1908 qp->flags |= MLX5_IB_QP_LSO;
1911 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1912 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1913 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1916 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1917 MLX5_SET(qpc, qpc, end_padding_mode,
1918 MLX5_WQ_END_PAD_MODE_ALIGN);
1920 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1929 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1930 qp->flags & MLX5_IB_QP_UNDERLAY) {
1931 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1932 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1933 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
1935 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1939 mlx5_ib_dbg(dev, "create qp failed\n");
1945 base->container_mibqp = qp;
1946 base->mqp.event = mlx5_ib_qp_event;
1948 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1949 &send_cq, &recv_cq);
1950 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1951 mlx5_ib_lock_cqs(send_cq, recv_cq);
1952 /* Maintain device to QPs access, needed for further handling via reset
1955 list_add_tail(&qp->qps_list, &dev->qp_list);
1956 /* Maintain CQ to QPs access, needed for further handling via reset flow
1959 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1961 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1962 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1963 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1968 if (qp->create_type == MLX5_QP_USER)
1969 destroy_qp_user(dev, pd, qp, base);
1970 else if (qp->create_type == MLX5_QP_KERNEL)
1971 destroy_qp_kernel(dev, qp);
1978 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1979 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1983 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1984 spin_lock(&send_cq->lock);
1985 spin_lock_nested(&recv_cq->lock,
1986 SINGLE_DEPTH_NESTING);
1987 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1988 spin_lock(&send_cq->lock);
1989 __acquire(&recv_cq->lock);
1991 spin_lock(&recv_cq->lock);
1992 spin_lock_nested(&send_cq->lock,
1993 SINGLE_DEPTH_NESTING);
1996 spin_lock(&send_cq->lock);
1997 __acquire(&recv_cq->lock);
1999 } else if (recv_cq) {
2000 spin_lock(&recv_cq->lock);
2001 __acquire(&send_cq->lock);
2003 __acquire(&send_cq->lock);
2004 __acquire(&recv_cq->lock);
2008 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2009 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2013 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2014 spin_unlock(&recv_cq->lock);
2015 spin_unlock(&send_cq->lock);
2016 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2017 __release(&recv_cq->lock);
2018 spin_unlock(&send_cq->lock);
2020 spin_unlock(&send_cq->lock);
2021 spin_unlock(&recv_cq->lock);
2024 __release(&recv_cq->lock);
2025 spin_unlock(&send_cq->lock);
2027 } else if (recv_cq) {
2028 __release(&send_cq->lock);
2029 spin_unlock(&recv_cq->lock);
2031 __release(&recv_cq->lock);
2032 __release(&send_cq->lock);
2036 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2038 return to_mpd(qp->ibqp.pd);
2041 static void get_cqs(enum ib_qp_type qp_type,
2042 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2043 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2046 case IB_QPT_XRC_TGT:
2050 case MLX5_IB_QPT_REG_UMR:
2051 case IB_QPT_XRC_INI:
2052 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2057 case MLX5_IB_QPT_HW_GSI:
2061 case IB_QPT_RAW_IPV6:
2062 case IB_QPT_RAW_ETHERTYPE:
2063 case IB_QPT_RAW_PACKET:
2064 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2065 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2076 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2077 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2078 u8 lag_tx_affinity);
2080 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2082 struct mlx5_ib_cq *send_cq, *recv_cq;
2083 struct mlx5_ib_qp_base *base;
2084 unsigned long flags;
2087 if (qp->ibqp.rwq_ind_tbl) {
2088 destroy_rss_raw_qp_tir(dev, qp);
2092 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2093 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2094 &qp->raw_packet_qp.rq.base :
2097 if (qp->state != IB_QPS_RESET) {
2098 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2099 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2100 err = mlx5_core_qp_modify(dev->mdev,
2101 MLX5_CMD_OP_2RST_QP, 0,
2104 struct mlx5_modify_raw_qp_param raw_qp_param = {
2105 .operation = MLX5_CMD_OP_2RST_QP
2108 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2111 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2115 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2116 &send_cq, &recv_cq);
2118 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2119 mlx5_ib_lock_cqs(send_cq, recv_cq);
2120 /* del from lists under both locks above to protect reset flow paths */
2121 list_del(&qp->qps_list);
2123 list_del(&qp->cq_send_list);
2126 list_del(&qp->cq_recv_list);
2128 if (qp->create_type == MLX5_QP_KERNEL) {
2129 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2130 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2131 if (send_cq != recv_cq)
2132 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2135 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2136 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2138 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2139 qp->flags & MLX5_IB_QP_UNDERLAY) {
2140 destroy_raw_packet_qp(dev, qp);
2142 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2144 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2148 if (qp->create_type == MLX5_QP_KERNEL)
2149 destroy_qp_kernel(dev, qp);
2150 else if (qp->create_type == MLX5_QP_USER)
2151 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2154 static const char *ib_qp_type_str(enum ib_qp_type type)
2158 return "IB_QPT_SMI";
2160 return "IB_QPT_GSI";
2167 case IB_QPT_RAW_IPV6:
2168 return "IB_QPT_RAW_IPV6";
2169 case IB_QPT_RAW_ETHERTYPE:
2170 return "IB_QPT_RAW_ETHERTYPE";
2171 case IB_QPT_XRC_INI:
2172 return "IB_QPT_XRC_INI";
2173 case IB_QPT_XRC_TGT:
2174 return "IB_QPT_XRC_TGT";
2175 case IB_QPT_RAW_PACKET:
2176 return "IB_QPT_RAW_PACKET";
2177 case MLX5_IB_QPT_REG_UMR:
2178 return "MLX5_IB_QPT_REG_UMR";
2180 return "IB_QPT_DRIVER";
2183 return "Invalid QP type";
2187 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2188 struct ib_qp_init_attr *attr,
2189 struct mlx5_ib_create_qp *ucmd)
2191 struct mlx5_ib_qp *qp;
2193 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2196 if (!attr->srq || !attr->recv_cq)
2197 return ERR_PTR(-EINVAL);
2199 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2200 ucmd, sizeof(*ucmd), &uidx);
2202 return ERR_PTR(err);
2204 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2206 return ERR_PTR(-ENOMEM);
2208 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2214 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2215 qp->qp_sub_type = MLX5_IB_QPT_DCT;
2216 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2217 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2218 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2219 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2220 MLX5_SET(dctc, dctc, user_index, uidx);
2222 qp->state = IB_QPS_RESET;
2227 return ERR_PTR(err);
2230 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2231 struct ib_qp_init_attr *init_attr,
2232 struct mlx5_ib_create_qp *ucmd,
2233 struct ib_udata *udata)
2235 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2241 if (udata->inlen < sizeof(*ucmd)) {
2242 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2245 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2249 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2250 init_attr->qp_type = MLX5_IB_QPT_DCI;
2252 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2253 init_attr->qp_type = MLX5_IB_QPT_DCT;
2255 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2260 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2261 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2268 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2269 struct ib_qp_init_attr *verbs_init_attr,
2270 struct ib_udata *udata)
2272 struct mlx5_ib_dev *dev;
2273 struct mlx5_ib_qp *qp;
2276 struct ib_qp_init_attr mlx_init_attr;
2277 struct ib_qp_init_attr *init_attr = verbs_init_attr;
2280 dev = to_mdev(pd->device);
2282 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2284 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2285 return ERR_PTR(-EINVAL);
2286 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2287 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2288 return ERR_PTR(-EINVAL);
2292 /* being cautious here */
2293 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2294 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2295 pr_warn("%s: no PD for transport %s\n", __func__,
2296 ib_qp_type_str(init_attr->qp_type));
2297 return ERR_PTR(-EINVAL);
2299 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2302 if (init_attr->qp_type == IB_QPT_DRIVER) {
2303 struct mlx5_ib_create_qp ucmd;
2305 init_attr = &mlx_init_attr;
2306 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2307 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2309 return ERR_PTR(err);
2311 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2312 if (init_attr->cap.max_recv_wr ||
2313 init_attr->cap.max_recv_sge) {
2314 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2315 return ERR_PTR(-EINVAL);
2318 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2322 switch (init_attr->qp_type) {
2323 case IB_QPT_XRC_TGT:
2324 case IB_QPT_XRC_INI:
2325 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2326 mlx5_ib_dbg(dev, "XRC not supported\n");
2327 return ERR_PTR(-ENOSYS);
2329 init_attr->recv_cq = NULL;
2330 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2331 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2332 init_attr->send_cq = NULL;
2336 case IB_QPT_RAW_PACKET:
2341 case MLX5_IB_QPT_HW_GSI:
2342 case MLX5_IB_QPT_REG_UMR:
2343 case MLX5_IB_QPT_DCI:
2344 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2346 return ERR_PTR(-ENOMEM);
2348 err = create_qp_common(dev, pd, init_attr, udata, qp);
2350 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2352 return ERR_PTR(err);
2355 if (is_qp0(init_attr->qp_type))
2356 qp->ibqp.qp_num = 0;
2357 else if (is_qp1(init_attr->qp_type))
2358 qp->ibqp.qp_num = 1;
2360 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2362 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2363 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2364 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2365 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2367 qp->trans_qp.xrcdn = xrcdn;
2372 return mlx5_ib_gsi_create_qp(pd, init_attr);
2374 case IB_QPT_RAW_IPV6:
2375 case IB_QPT_RAW_ETHERTYPE:
2378 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2379 init_attr->qp_type);
2380 /* Don't support raw QPs */
2381 return ERR_PTR(-EINVAL);
2384 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2385 qp->qp_sub_type = init_attr->qp_type;
2390 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2392 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2394 if (mqp->state == IB_QPS_RTR) {
2397 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2399 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2409 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2411 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2412 struct mlx5_ib_qp *mqp = to_mqp(qp);
2414 if (unlikely(qp->qp_type == IB_QPT_GSI))
2415 return mlx5_ib_gsi_destroy_qp(qp);
2417 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2418 return mlx5_ib_destroy_dct(mqp);
2420 destroy_qp_common(dev, mqp);
2427 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2430 u32 hw_access_flags = 0;
2434 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2435 dest_rd_atomic = attr->max_dest_rd_atomic;
2437 dest_rd_atomic = qp->trans_qp.resp_depth;
2439 if (attr_mask & IB_QP_ACCESS_FLAGS)
2440 access_flags = attr->qp_access_flags;
2442 access_flags = qp->trans_qp.atomic_rd_en;
2444 if (!dest_rd_atomic)
2445 access_flags &= IB_ACCESS_REMOTE_WRITE;
2447 if (access_flags & IB_ACCESS_REMOTE_READ)
2448 hw_access_flags |= MLX5_QP_BIT_RRE;
2449 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2450 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2451 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2452 hw_access_flags |= MLX5_QP_BIT_RWE;
2454 return cpu_to_be32(hw_access_flags);
2458 MLX5_PATH_FLAG_FL = 1 << 0,
2459 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2460 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2463 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2465 if (rate == IB_RATE_PORT_CURRENT)
2468 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2471 while (rate != IB_RATE_PORT_CURRENT &&
2472 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2473 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2476 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2479 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2480 struct mlx5_ib_sq *sq, u8 sl)
2487 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2488 in = kvzalloc(inlen, GFP_KERNEL);
2492 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2494 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2495 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2497 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2504 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2505 struct mlx5_ib_sq *sq, u8 tx_affinity)
2512 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2513 in = kvzalloc(inlen, GFP_KERNEL);
2517 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2519 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2520 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2522 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2529 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2530 const struct rdma_ah_attr *ah,
2531 struct mlx5_qp_path *path, u8 port, int attr_mask,
2532 u32 path_flags, const struct ib_qp_attr *attr,
2535 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2537 enum ib_gid_type gid_type;
2538 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2539 u8 sl = rdma_ah_get_sl(ah);
2541 if (attr_mask & IB_QP_PKEY_INDEX)
2542 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2545 if (ah_flags & IB_AH_GRH) {
2546 if (grh->sgid_index >=
2547 dev->mdev->port_caps[port - 1].gid_table_len) {
2548 pr_err("sgid_index (%u) too large. max is %d\n",
2550 dev->mdev->port_caps[port - 1].gid_table_len);
2555 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2556 if (!(ah_flags & IB_AH_GRH))
2558 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
2562 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2563 if (qp->ibqp.qp_type == IB_QPT_RC ||
2564 qp->ibqp.qp_type == IB_QPT_UC ||
2565 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2566 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2567 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2569 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2570 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2571 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2573 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2575 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2576 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2577 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2578 if (ah_flags & IB_AH_GRH)
2579 path->grh_mlid |= 1 << 7;
2580 path->dci_cfi_prio_sl = sl & 0xf;
2583 if (ah_flags & IB_AH_GRH) {
2584 path->mgid_index = grh->sgid_index;
2585 path->hop_limit = grh->hop_limit;
2586 path->tclass_flowlabel =
2587 cpu_to_be32((grh->traffic_class << 20) |
2589 memcpy(path->rgid, grh->dgid.raw, 16);
2592 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2595 path->static_rate = err;
2598 if (attr_mask & IB_QP_TIMEOUT)
2599 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2601 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2602 return modify_raw_packet_eth_prio(dev->mdev,
2603 &qp->raw_packet_qp.sq,
2609 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2610 [MLX5_QP_STATE_INIT] = {
2611 [MLX5_QP_STATE_INIT] = {
2612 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2613 MLX5_QP_OPTPAR_RAE |
2614 MLX5_QP_OPTPAR_RWE |
2615 MLX5_QP_OPTPAR_PKEY_INDEX |
2616 MLX5_QP_OPTPAR_PRI_PORT,
2617 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2618 MLX5_QP_OPTPAR_PKEY_INDEX |
2619 MLX5_QP_OPTPAR_PRI_PORT,
2620 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2621 MLX5_QP_OPTPAR_Q_KEY |
2622 MLX5_QP_OPTPAR_PRI_PORT,
2624 [MLX5_QP_STATE_RTR] = {
2625 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2626 MLX5_QP_OPTPAR_RRE |
2627 MLX5_QP_OPTPAR_RAE |
2628 MLX5_QP_OPTPAR_RWE |
2629 MLX5_QP_OPTPAR_PKEY_INDEX,
2630 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2631 MLX5_QP_OPTPAR_RWE |
2632 MLX5_QP_OPTPAR_PKEY_INDEX,
2633 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2634 MLX5_QP_OPTPAR_Q_KEY,
2635 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2636 MLX5_QP_OPTPAR_Q_KEY,
2637 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2638 MLX5_QP_OPTPAR_RRE |
2639 MLX5_QP_OPTPAR_RAE |
2640 MLX5_QP_OPTPAR_RWE |
2641 MLX5_QP_OPTPAR_PKEY_INDEX,
2644 [MLX5_QP_STATE_RTR] = {
2645 [MLX5_QP_STATE_RTS] = {
2646 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2647 MLX5_QP_OPTPAR_RRE |
2648 MLX5_QP_OPTPAR_RAE |
2649 MLX5_QP_OPTPAR_RWE |
2650 MLX5_QP_OPTPAR_PM_STATE |
2651 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2652 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2653 MLX5_QP_OPTPAR_RWE |
2654 MLX5_QP_OPTPAR_PM_STATE,
2655 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2658 [MLX5_QP_STATE_RTS] = {
2659 [MLX5_QP_STATE_RTS] = {
2660 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2661 MLX5_QP_OPTPAR_RAE |
2662 MLX5_QP_OPTPAR_RWE |
2663 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2664 MLX5_QP_OPTPAR_PM_STATE |
2665 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2666 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2667 MLX5_QP_OPTPAR_PM_STATE |
2668 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2669 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2670 MLX5_QP_OPTPAR_SRQN |
2671 MLX5_QP_OPTPAR_CQN_RCV,
2674 [MLX5_QP_STATE_SQER] = {
2675 [MLX5_QP_STATE_RTS] = {
2676 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2677 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2678 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2679 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2680 MLX5_QP_OPTPAR_RWE |
2681 MLX5_QP_OPTPAR_RAE |
2687 static int ib_nr_to_mlx5_nr(int ib_mask)
2692 case IB_QP_CUR_STATE:
2694 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2696 case IB_QP_ACCESS_FLAGS:
2697 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2699 case IB_QP_PKEY_INDEX:
2700 return MLX5_QP_OPTPAR_PKEY_INDEX;
2702 return MLX5_QP_OPTPAR_PRI_PORT;
2704 return MLX5_QP_OPTPAR_Q_KEY;
2706 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2707 MLX5_QP_OPTPAR_PRI_PORT;
2708 case IB_QP_PATH_MTU:
2711 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2712 case IB_QP_RETRY_CNT:
2713 return MLX5_QP_OPTPAR_RETRY_COUNT;
2714 case IB_QP_RNR_RETRY:
2715 return MLX5_QP_OPTPAR_RNR_RETRY;
2718 case IB_QP_MAX_QP_RD_ATOMIC:
2719 return MLX5_QP_OPTPAR_SRA_MAX;
2720 case IB_QP_ALT_PATH:
2721 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2722 case IB_QP_MIN_RNR_TIMER:
2723 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2726 case IB_QP_MAX_DEST_RD_ATOMIC:
2727 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2728 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2729 case IB_QP_PATH_MIG_STATE:
2730 return MLX5_QP_OPTPAR_PM_STATE;
2733 case IB_QP_DEST_QPN:
2739 static int ib_mask_to_mlx5_opt(int ib_mask)
2744 for (i = 0; i < 8 * sizeof(int); i++) {
2745 if ((1 << i) & ib_mask)
2746 result |= ib_nr_to_mlx5_nr(1 << i);
2752 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2753 struct mlx5_ib_rq *rq, int new_state,
2754 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2761 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2762 in = kvzalloc(inlen, GFP_KERNEL);
2766 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2768 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2769 MLX5_SET(rqc, rqc, state, new_state);
2771 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2772 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2773 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2774 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2775 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2777 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2781 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2785 rq->state = new_state;
2792 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2793 struct mlx5_ib_sq *sq,
2795 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2797 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2798 struct mlx5_rate_limit old_rl = ibqp->rl;
2799 struct mlx5_rate_limit new_rl = old_rl;
2800 bool new_rate_added = false;
2807 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2808 in = kvzalloc(inlen, GFP_KERNEL);
2812 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2814 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2815 MLX5_SET(sqc, sqc, state, new_state);
2817 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2818 if (new_state != MLX5_SQC_STATE_RDY)
2819 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2822 new_rl = raw_qp_param->rl;
2825 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2827 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
2829 pr_err("Failed configuring rate limit(err %d): \
2830 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2831 err, new_rl.rate, new_rl.max_burst_sz,
2832 new_rl.typical_pkt_sz);
2836 new_rate_added = true;
2839 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2840 /* index 0 means no limit */
2841 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2844 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2846 /* Remove new rate from table if failed */
2848 mlx5_rl_remove_rate(dev, &new_rl);
2852 /* Only remove the old rate after new rate was set */
2854 !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
2855 (new_state != MLX5_SQC_STATE_RDY))
2856 mlx5_rl_remove_rate(dev, &old_rl);
2859 sq->state = new_state;
2866 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2867 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2870 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2871 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2872 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2873 int modify_rq = !!qp->rq.wqe_cnt;
2874 int modify_sq = !!qp->sq.wqe_cnt;
2879 switch (raw_qp_param->operation) {
2880 case MLX5_CMD_OP_RST2INIT_QP:
2881 rq_state = MLX5_RQC_STATE_RDY;
2882 sq_state = MLX5_SQC_STATE_RDY;
2884 case MLX5_CMD_OP_2ERR_QP:
2885 rq_state = MLX5_RQC_STATE_ERR;
2886 sq_state = MLX5_SQC_STATE_ERR;
2888 case MLX5_CMD_OP_2RST_QP:
2889 rq_state = MLX5_RQC_STATE_RST;
2890 sq_state = MLX5_SQC_STATE_RST;
2892 case MLX5_CMD_OP_RTR2RTS_QP:
2893 case MLX5_CMD_OP_RTS2RTS_QP:
2894 if (raw_qp_param->set_mask ==
2895 MLX5_RAW_QP_RATE_LIMIT) {
2897 sq_state = sq->state;
2899 return raw_qp_param->set_mask ? -EINVAL : 0;
2902 case MLX5_CMD_OP_INIT2INIT_QP:
2903 case MLX5_CMD_OP_INIT2RTR_QP:
2904 if (raw_qp_param->set_mask)
2914 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2921 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2927 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2933 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2934 const struct ib_qp_attr *attr, int attr_mask,
2935 enum ib_qp_state cur_state, enum ib_qp_state new_state,
2936 const struct mlx5_ib_modify_qp *ucmd)
2938 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2939 [MLX5_QP_STATE_RST] = {
2940 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2941 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2942 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2944 [MLX5_QP_STATE_INIT] = {
2945 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2946 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2947 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2948 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2950 [MLX5_QP_STATE_RTR] = {
2951 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2952 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2953 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2955 [MLX5_QP_STATE_RTS] = {
2956 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2957 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2958 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2960 [MLX5_QP_STATE_SQD] = {
2961 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2962 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2964 [MLX5_QP_STATE_SQER] = {
2965 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2966 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2967 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2969 [MLX5_QP_STATE_ERR] = {
2970 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2971 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2975 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2976 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2977 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2978 struct mlx5_ib_cq *send_cq, *recv_cq;
2979 struct mlx5_qp_context *context;
2980 struct mlx5_ib_pd *pd;
2981 struct mlx5_ib_port *mibport = NULL;
2982 enum mlx5_qp_state mlx5_cur, mlx5_new;
2983 enum mlx5_qp_optpar optpar;
2989 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
2990 qp->qp_sub_type : ibqp->qp_type);
2994 context = kzalloc(sizeof(*context), GFP_KERNEL);
2998 context->flags = cpu_to_be32(mlx5_st << 16);
3000 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3001 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3003 switch (attr->path_mig_state) {
3004 case IB_MIG_MIGRATED:
3005 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3008 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3011 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3016 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3017 if ((ibqp->qp_type == IB_QPT_RC) ||
3018 (ibqp->qp_type == IB_QPT_UD &&
3019 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3020 (ibqp->qp_type == IB_QPT_UC) ||
3021 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3022 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3023 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3024 if (mlx5_lag_is_active(dev->mdev)) {
3025 u8 p = mlx5_core_native_port_num(dev->mdev);
3026 tx_affinity = (unsigned int)atomic_add_return(1,
3027 &dev->roce[p].next_port) %
3029 context->flags |= cpu_to_be32(tx_affinity << 24);
3034 if (is_sqp(ibqp->qp_type)) {
3035 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3036 } else if ((ibqp->qp_type == IB_QPT_UD &&
3037 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3038 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3039 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3040 } else if (attr_mask & IB_QP_PATH_MTU) {
3041 if (attr->path_mtu < IB_MTU_256 ||
3042 attr->path_mtu > IB_MTU_4096) {
3043 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3047 context->mtu_msgmax = (attr->path_mtu << 5) |
3048 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3051 if (attr_mask & IB_QP_DEST_QPN)
3052 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3054 if (attr_mask & IB_QP_PKEY_INDEX)
3055 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3057 /* todo implement counter_index functionality */
3059 if (is_sqp(ibqp->qp_type))
3060 context->pri_path.port = qp->port;
3062 if (attr_mask & IB_QP_PORT)
3063 context->pri_path.port = attr->port_num;
3065 if (attr_mask & IB_QP_AV) {
3066 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3067 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3068 attr_mask, 0, attr, false);
3073 if (attr_mask & IB_QP_TIMEOUT)
3074 context->pri_path.ackto_lt |= attr->timeout << 3;
3076 if (attr_mask & IB_QP_ALT_PATH) {
3077 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3080 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3087 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3088 &send_cq, &recv_cq);
3090 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3091 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3092 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3093 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3095 if (attr_mask & IB_QP_RNR_RETRY)
3096 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3098 if (attr_mask & IB_QP_RETRY_CNT)
3099 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3101 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3102 if (attr->max_rd_atomic)
3104 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3107 if (attr_mask & IB_QP_SQ_PSN)
3108 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3110 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3111 if (attr->max_dest_rd_atomic)
3113 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3116 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3117 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3119 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3120 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3122 if (attr_mask & IB_QP_RQ_PSN)
3123 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3125 if (attr_mask & IB_QP_QKEY)
3126 context->qkey = cpu_to_be32(attr->qkey);
3128 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3129 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3131 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3132 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3135 /* Underlay port should be used - index 0 function per port */
3136 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3139 mibport = &dev->port[port_num];
3140 context->qp_counter_set_usr_page |=
3141 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3144 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3145 context->sq_crq_size |= cpu_to_be16(1 << 4);
3147 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3148 context->deth_sqpn = cpu_to_be32(1);
3150 mlx5_cur = to_mlx5_state(cur_state);
3151 mlx5_new = to_mlx5_state(new_state);
3153 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3154 !optab[mlx5_cur][mlx5_new]) {
3159 op = optab[mlx5_cur][mlx5_new];
3160 optpar = ib_mask_to_mlx5_opt(attr_mask);
3161 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3163 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3164 qp->flags & MLX5_IB_QP_UNDERLAY) {
3165 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3167 raw_qp_param.operation = op;
3168 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3169 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3170 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3173 if (attr_mask & IB_QP_RATE_LIMIT) {
3174 raw_qp_param.rl.rate = attr->rate_limit;
3176 if (ucmd->burst_info.max_burst_sz) {
3177 if (attr->rate_limit &&
3178 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3179 raw_qp_param.rl.max_burst_sz =
3180 ucmd->burst_info.max_burst_sz;
3187 if (ucmd->burst_info.typical_pkt_sz) {
3188 if (attr->rate_limit &&
3189 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3190 raw_qp_param.rl.typical_pkt_sz =
3191 ucmd->burst_info.typical_pkt_sz;
3198 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3201 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3203 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3210 qp->state = new_state;
3212 if (attr_mask & IB_QP_ACCESS_FLAGS)
3213 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3214 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3215 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3216 if (attr_mask & IB_QP_PORT)
3217 qp->port = attr->port_num;
3218 if (attr_mask & IB_QP_ALT_PATH)
3219 qp->trans_qp.alt_port = attr->alt_port_num;
3222 * If we moved a kernel QP to RESET, clean up all old CQ
3223 * entries and reinitialize the QP.
3225 if (new_state == IB_QPS_RESET &&
3226 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3227 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3228 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3229 if (send_cq != recv_cq)
3230 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3236 qp->sq.cur_post = 0;
3237 qp->sq.last_poll = 0;
3238 qp->db.db[MLX5_RCV_DBR] = 0;
3239 qp->db.db[MLX5_SND_DBR] = 0;
3247 static inline bool is_valid_mask(int mask, int req, int opt)
3249 if ((mask & req) != req)
3252 if (mask & ~(req | opt))
3258 /* check valid transition for driver QP types
3259 * for now the only QP type that this function supports is DCI
3261 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3262 enum ib_qp_attr_mask attr_mask)
3264 int req = IB_QP_STATE;
3267 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3268 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3269 return is_valid_mask(attr_mask, req, opt);
3270 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3271 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3272 return is_valid_mask(attr_mask, req, opt);
3273 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3274 req |= IB_QP_PATH_MTU;
3275 opt = IB_QP_PKEY_INDEX;
3276 return is_valid_mask(attr_mask, req, opt);
3277 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3278 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3279 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3280 opt = IB_QP_MIN_RNR_TIMER;
3281 return is_valid_mask(attr_mask, req, opt);
3282 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3283 opt = IB_QP_MIN_RNR_TIMER;
3284 return is_valid_mask(attr_mask, req, opt);
3285 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3286 return is_valid_mask(attr_mask, req, opt);
3291 /* mlx5_ib_modify_dct: modify a DCT QP
3292 * valid transitions are:
3293 * RESET to INIT: must set access_flags, pkey_index and port
3294 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3295 * mtu, gid_index and hop_limit
3296 * Other transitions and attributes are illegal
3298 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3299 int attr_mask, struct ib_udata *udata)
3301 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3302 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3303 enum ib_qp_state cur_state, new_state;
3305 int required = IB_QP_STATE;
3308 if (!(attr_mask & IB_QP_STATE))
3311 cur_state = qp->state;
3312 new_state = attr->qp_state;
3314 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3315 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3316 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3317 if (!is_valid_mask(attr_mask, required, 0))
3320 if (attr->port_num == 0 ||
3321 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3322 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3323 attr->port_num, dev->num_ports);
3326 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3327 MLX5_SET(dctc, dctc, rre, 1);
3328 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3329 MLX5_SET(dctc, dctc, rwe, 1);
3330 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3331 if (!mlx5_ib_dc_atomic_is_supported(dev))
3333 MLX5_SET(dctc, dctc, rae, 1);
3334 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3336 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3337 MLX5_SET(dctc, dctc, port, attr->port_num);
3338 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3340 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3341 struct mlx5_ib_modify_qp_resp resp = {};
3342 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3345 if (udata->outlen < min_resp_len)
3347 resp.response_length = min_resp_len;
3349 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3350 if (!is_valid_mask(attr_mask, required, 0))
3352 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3353 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3354 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3355 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3356 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3357 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3359 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3360 MLX5_ST_SZ_BYTES(create_dct_in));
3363 resp.dctn = qp->dct.mdct.mqp.qpn;
3364 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3366 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3370 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3374 qp->state = IB_QPS_ERR;
3376 qp->state = new_state;
3380 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3381 int attr_mask, struct ib_udata *udata)
3383 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3384 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3385 struct mlx5_ib_modify_qp ucmd = {};
3386 enum ib_qp_type qp_type;
3387 enum ib_qp_state cur_state, new_state;
3388 size_t required_cmd_sz;
3391 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
3393 if (ibqp->rwq_ind_tbl)
3396 if (udata && udata->inlen) {
3397 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3398 sizeof(ucmd.reserved);
3399 if (udata->inlen < required_cmd_sz)
3402 if (udata->inlen > sizeof(ucmd) &&
3403 !ib_is_udata_cleared(udata, sizeof(ucmd),
3404 udata->inlen - sizeof(ucmd)))
3407 if (ib_copy_from_udata(&ucmd, udata,
3408 min(udata->inlen, sizeof(ucmd))))
3411 if (ucmd.comp_mask ||
3412 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3413 memchr_inv(&ucmd.burst_info.reserved, 0,
3414 sizeof(ucmd.burst_info.reserved)))
3418 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3419 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3421 if (ibqp->qp_type == IB_QPT_DRIVER)
3422 qp_type = qp->qp_sub_type;
3424 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3425 IB_QPT_GSI : ibqp->qp_type;
3427 if (qp_type == MLX5_IB_QPT_DCT)
3428 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3430 mutex_lock(&qp->mutex);
3432 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3433 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3435 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3436 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3437 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3440 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3441 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3442 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3446 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3447 qp_type != MLX5_IB_QPT_DCI &&
3448 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
3449 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3450 cur_state, new_state, ibqp->qp_type, attr_mask);
3452 } else if (qp_type == MLX5_IB_QPT_DCI &&
3453 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3454 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3455 cur_state, new_state, qp_type, attr_mask);
3459 if ((attr_mask & IB_QP_PORT) &&
3460 (attr->port_num == 0 ||
3461 attr->port_num > dev->num_ports)) {
3462 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3463 attr->port_num, dev->num_ports);
3467 if (attr_mask & IB_QP_PKEY_INDEX) {
3468 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3469 if (attr->pkey_index >=
3470 dev->mdev->port_caps[port - 1].pkey_table_len) {
3471 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3477 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3478 attr->max_rd_atomic >
3479 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3480 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3481 attr->max_rd_atomic);
3485 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3486 attr->max_dest_rd_atomic >
3487 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3488 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3489 attr->max_dest_rd_atomic);
3493 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3498 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3502 mutex_unlock(&qp->mutex);
3506 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3508 struct mlx5_ib_cq *cq;
3511 cur = wq->head - wq->tail;
3512 if (likely(cur + nreq < wq->max_post))
3516 spin_lock(&cq->lock);
3517 cur = wq->head - wq->tail;
3518 spin_unlock(&cq->lock);
3520 return cur + nreq >= wq->max_post;
3523 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3524 u64 remote_addr, u32 rkey)
3526 rseg->raddr = cpu_to_be64(remote_addr);
3527 rseg->rkey = cpu_to_be32(rkey);
3531 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3532 struct ib_send_wr *wr, void *qend,
3533 struct mlx5_ib_qp *qp, int *size)
3537 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3539 if (wr->send_flags & IB_SEND_IP_CSUM)
3540 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3541 MLX5_ETH_WQE_L4_CSUM;
3543 seg += sizeof(struct mlx5_wqe_eth_seg);
3544 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3546 if (wr->opcode == IB_WR_LSO) {
3547 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3548 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3549 u64 left, leftlen, copysz;
3550 void *pdata = ud_wr->header;
3553 eseg->mss = cpu_to_be16(ud_wr->mss);
3554 eseg->inline_hdr.sz = cpu_to_be16(left);
3557 * check if there is space till the end of queue, if yes,
3558 * copy all in one shot, otherwise copy till the end of queue,
3559 * rollback and than the copy the left
3561 leftlen = qend - (void *)eseg->inline_hdr.start;
3562 copysz = min_t(u64, leftlen, left);
3564 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3566 if (likely(copysz > size_of_inl_hdr_start)) {
3567 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3568 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3571 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3572 seg = mlx5_get_send_wqe(qp, 0);
3575 memcpy(seg, pdata, left);
3576 seg += ALIGN(left, 16);
3577 *size += ALIGN(left, 16) / 16;
3584 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3585 struct ib_send_wr *wr)
3587 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3588 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3589 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3592 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3594 dseg->byte_count = cpu_to_be32(sg->length);
3595 dseg->lkey = cpu_to_be32(sg->lkey);
3596 dseg->addr = cpu_to_be64(sg->addr);
3599 static u64 get_xlt_octo(u64 bytes)
3601 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3602 MLX5_IB_UMR_OCTOWORD;
3605 static __be64 frwr_mkey_mask(void)
3609 result = MLX5_MKEY_MASK_LEN |
3610 MLX5_MKEY_MASK_PAGE_SIZE |
3611 MLX5_MKEY_MASK_START_ADDR |
3612 MLX5_MKEY_MASK_EN_RINVAL |
3613 MLX5_MKEY_MASK_KEY |
3619 MLX5_MKEY_MASK_SMALL_FENCE |
3620 MLX5_MKEY_MASK_FREE;
3622 return cpu_to_be64(result);
3625 static __be64 sig_mkey_mask(void)
3629 result = MLX5_MKEY_MASK_LEN |
3630 MLX5_MKEY_MASK_PAGE_SIZE |
3631 MLX5_MKEY_MASK_START_ADDR |
3632 MLX5_MKEY_MASK_EN_SIGERR |
3633 MLX5_MKEY_MASK_EN_RINVAL |
3634 MLX5_MKEY_MASK_KEY |
3639 MLX5_MKEY_MASK_SMALL_FENCE |
3640 MLX5_MKEY_MASK_FREE |
3641 MLX5_MKEY_MASK_BSF_EN;
3643 return cpu_to_be64(result);
3646 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3647 struct mlx5_ib_mr *mr, bool umr_inline)
3649 int size = mr->ndescs * mr->desc_size;
3651 memset(umr, 0, sizeof(*umr));
3653 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3655 umr->flags |= MLX5_UMR_INLINE;
3656 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3657 umr->mkey_mask = frwr_mkey_mask();
3660 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3662 memset(umr, 0, sizeof(*umr));
3663 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3664 umr->flags = MLX5_UMR_INLINE;
3667 static __be64 get_umr_enable_mr_mask(void)
3671 result = MLX5_MKEY_MASK_KEY |
3672 MLX5_MKEY_MASK_FREE;
3674 return cpu_to_be64(result);
3677 static __be64 get_umr_disable_mr_mask(void)
3681 result = MLX5_MKEY_MASK_FREE;
3683 return cpu_to_be64(result);
3686 static __be64 get_umr_update_translation_mask(void)
3690 result = MLX5_MKEY_MASK_LEN |
3691 MLX5_MKEY_MASK_PAGE_SIZE |
3692 MLX5_MKEY_MASK_START_ADDR;
3694 return cpu_to_be64(result);
3697 static __be64 get_umr_update_access_mask(int atomic)
3701 result = MLX5_MKEY_MASK_LR |
3707 result |= MLX5_MKEY_MASK_A;
3709 return cpu_to_be64(result);
3712 static __be64 get_umr_update_pd_mask(void)
3716 result = MLX5_MKEY_MASK_PD;
3718 return cpu_to_be64(result);
3721 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
3723 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
3724 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
3725 (mask & MLX5_MKEY_MASK_A &&
3726 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
3731 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
3732 struct mlx5_wqe_umr_ctrl_seg *umr,
3733 struct ib_send_wr *wr, int atomic)
3735 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3737 memset(umr, 0, sizeof(*umr));
3739 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3740 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3742 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3744 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3745 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3746 u64 offset = get_xlt_octo(umrwr->offset);
3748 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3749 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3750 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3752 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3753 umr->mkey_mask |= get_umr_update_translation_mask();
3754 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3755 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3756 umr->mkey_mask |= get_umr_update_pd_mask();
3758 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3759 umr->mkey_mask |= get_umr_enable_mr_mask();
3760 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3761 umr->mkey_mask |= get_umr_disable_mr_mask();
3764 umr->flags |= MLX5_UMR_INLINE;
3766 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
3769 static u8 get_umr_flags(int acc)
3771 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3772 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3773 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3774 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3775 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3778 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3779 struct mlx5_ib_mr *mr,
3780 u32 key, int access)
3782 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3784 memset(seg, 0, sizeof(*seg));
3786 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3787 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3788 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3789 /* KLMs take twice the size of MTTs */
3792 seg->flags = get_umr_flags(access) | mr->access_mode;
3793 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3794 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3795 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3796 seg->len = cpu_to_be64(mr->ibmr.length);
3797 seg->xlt_oct_size = cpu_to_be32(ndescs);
3800 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3802 memset(seg, 0, sizeof(*seg));
3803 seg->status = MLX5_MKEY_STATUS_FREE;
3806 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3808 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3810 memset(seg, 0, sizeof(*seg));
3811 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3812 seg->status = MLX5_MKEY_STATUS_FREE;
3814 seg->flags = convert_access(umrwr->access_flags);
3816 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3817 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3819 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3821 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3822 seg->len = cpu_to_be64(umrwr->length);
3823 seg->log2_page_size = umrwr->page_shift;
3824 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3825 mlx5_mkey_variant(umrwr->mkey));
3828 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3829 struct mlx5_ib_mr *mr,
3830 struct mlx5_ib_pd *pd)
3832 int bcount = mr->desc_size * mr->ndescs;
3834 dseg->addr = cpu_to_be64(mr->desc_map);
3835 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3836 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3839 static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp,
3840 struct mlx5_ib_mr *mr, int mr_list_size)
3842 void *qend = qp->sq.qend;
3843 void *addr = mr->descs;
3846 if (unlikely(seg + mr_list_size > qend)) {
3848 memcpy(seg, addr, copy);
3850 mr_list_size -= copy;
3851 seg = mlx5_get_send_wqe(qp, 0);
3853 memcpy(seg, addr, mr_list_size);
3854 seg += mr_list_size;
3857 static __be32 send_ieth(struct ib_send_wr *wr)
3859 switch (wr->opcode) {
3860 case IB_WR_SEND_WITH_IMM:
3861 case IB_WR_RDMA_WRITE_WITH_IMM:
3862 return wr->ex.imm_data;
3864 case IB_WR_SEND_WITH_INV:
3865 return cpu_to_be32(wr->ex.invalidate_rkey);
3872 static u8 calc_sig(void *wqe, int size)
3878 for (i = 0; i < size; i++)
3884 static u8 wq_sig(void *wqe)
3886 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3889 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3892 struct mlx5_wqe_inline_seg *seg;
3893 void *qend = qp->sq.qend;
3901 wqe += sizeof(*seg);
3902 for (i = 0; i < wr->num_sge; i++) {
3903 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3904 len = wr->sg_list[i].length;
3907 if (unlikely(inl > qp->max_inline_data))
3910 if (unlikely(wqe + len > qend)) {
3912 memcpy(wqe, addr, copy);
3915 wqe = mlx5_get_send_wqe(qp, 0);
3917 memcpy(wqe, addr, len);
3921 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3923 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3928 static u16 prot_field_size(enum ib_signature_type type)
3931 case IB_SIG_TYPE_T10_DIF:
3932 return MLX5_DIF_SIZE;
3938 static u8 bs_selector(int block_size)
3940 switch (block_size) {
3941 case 512: return 0x1;
3942 case 520: return 0x2;
3943 case 4096: return 0x3;
3944 case 4160: return 0x4;
3945 case 1073741824: return 0x5;
3950 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3951 struct mlx5_bsf_inl *inl)
3953 /* Valid inline section and allow BSF refresh */
3954 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3955 MLX5_BSF_REFRESH_DIF);
3956 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3957 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3958 /* repeating block */
3959 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3960 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3961 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3963 if (domain->sig.dif.ref_remap)
3964 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3966 if (domain->sig.dif.app_escape) {
3967 if (domain->sig.dif.ref_escape)
3968 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3970 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3973 inl->dif_app_bitmask_check =
3974 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3977 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3978 struct ib_sig_attrs *sig_attrs,
3979 struct mlx5_bsf *bsf, u32 data_size)
3981 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3982 struct mlx5_bsf_basic *basic = &bsf->basic;
3983 struct ib_sig_domain *mem = &sig_attrs->mem;
3984 struct ib_sig_domain *wire = &sig_attrs->wire;
3986 memset(bsf, 0, sizeof(*bsf));
3988 /* Basic + Extended + Inline */
3989 basic->bsf_size_sbs = 1 << 7;
3990 /* Input domain check byte mask */
3991 basic->check_byte_mask = sig_attrs->check_mask;
3992 basic->raw_data_size = cpu_to_be32(data_size);
3995 switch (sig_attrs->mem.sig_type) {
3996 case IB_SIG_TYPE_NONE:
3998 case IB_SIG_TYPE_T10_DIF:
3999 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4000 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4001 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4008 switch (sig_attrs->wire.sig_type) {
4009 case IB_SIG_TYPE_NONE:
4011 case IB_SIG_TYPE_T10_DIF:
4012 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4013 mem->sig_type == wire->sig_type) {
4014 /* Same block structure */
4015 basic->bsf_size_sbs |= 1 << 4;
4016 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4017 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4018 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4019 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4020 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4021 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4023 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4025 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4026 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4035 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
4036 struct mlx5_ib_qp *qp, void **seg, int *size)
4038 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4039 struct ib_mr *sig_mr = wr->sig_mr;
4040 struct mlx5_bsf *bsf;
4041 u32 data_len = wr->wr.sg_list->length;
4042 u32 data_key = wr->wr.sg_list->lkey;
4043 u64 data_va = wr->wr.sg_list->addr;
4048 (data_key == wr->prot->lkey &&
4049 data_va == wr->prot->addr &&
4050 data_len == wr->prot->length)) {
4052 * Source domain doesn't contain signature information
4053 * or data and protection are interleaved in memory.
4054 * So need construct:
4055 * ------------------
4057 * ------------------
4059 * ------------------
4061 struct mlx5_klm *data_klm = *seg;
4063 data_klm->bcount = cpu_to_be32(data_len);
4064 data_klm->key = cpu_to_be32(data_key);
4065 data_klm->va = cpu_to_be64(data_va);
4066 wqe_size = ALIGN(sizeof(*data_klm), 64);
4069 * Source domain contains signature information
4070 * So need construct a strided block format:
4071 * ---------------------------
4072 * | stride_block_ctrl |
4073 * ---------------------------
4075 * ---------------------------
4077 * ---------------------------
4079 * ---------------------------
4081 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4082 struct mlx5_stride_block_entry *data_sentry;
4083 struct mlx5_stride_block_entry *prot_sentry;
4084 u32 prot_key = wr->prot->lkey;
4085 u64 prot_va = wr->prot->addr;
4086 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4090 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4091 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4093 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4095 pr_err("Bad block size given: %u\n", block_size);
4098 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4100 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4101 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4102 sblock_ctrl->num_entries = cpu_to_be16(2);
4104 data_sentry->bcount = cpu_to_be16(block_size);
4105 data_sentry->key = cpu_to_be32(data_key);
4106 data_sentry->va = cpu_to_be64(data_va);
4107 data_sentry->stride = cpu_to_be16(block_size);
4109 prot_sentry->bcount = cpu_to_be16(prot_size);
4110 prot_sentry->key = cpu_to_be32(prot_key);
4111 prot_sentry->va = cpu_to_be64(prot_va);
4112 prot_sentry->stride = cpu_to_be16(prot_size);
4114 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4115 sizeof(*prot_sentry), 64);
4119 *size += wqe_size / 16;
4120 if (unlikely((*seg == qp->sq.qend)))
4121 *seg = mlx5_get_send_wqe(qp, 0);
4124 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4128 *seg += sizeof(*bsf);
4129 *size += sizeof(*bsf) / 16;
4130 if (unlikely((*seg == qp->sq.qend)))
4131 *seg = mlx5_get_send_wqe(qp, 0);
4136 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4137 struct ib_sig_handover_wr *wr, u32 size,
4138 u32 length, u32 pdn)
4140 struct ib_mr *sig_mr = wr->sig_mr;
4141 u32 sig_key = sig_mr->rkey;
4142 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4144 memset(seg, 0, sizeof(*seg));
4146 seg->flags = get_umr_flags(wr->access_flags) |
4147 MLX5_MKC_ACCESS_MODE_KLMS;
4148 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4149 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4150 MLX5_MKEY_BSF_EN | pdn);
4151 seg->len = cpu_to_be64(length);
4152 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4153 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4156 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4159 memset(umr, 0, sizeof(*umr));
4161 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4162 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4163 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4164 umr->mkey_mask = sig_mkey_mask();
4168 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
4169 void **seg, int *size)
4171 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4172 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4173 u32 pdn = get_pd(qp)->pdn;
4175 int region_len, ret;
4177 if (unlikely(wr->wr.num_sge != 1) ||
4178 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4179 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4180 unlikely(!sig_mr->sig->sig_status_checked))
4183 /* length of the protected region, data + protection */
4184 region_len = wr->wr.sg_list->length;
4186 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4187 wr->prot->addr != wr->wr.sg_list->addr ||
4188 wr->prot->length != wr->wr.sg_list->length))
4189 region_len += wr->prot->length;
4192 * KLM octoword size - if protection was provided
4193 * then we use strided block format (3 octowords),
4194 * else we use single KLM (1 octoword)
4196 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4198 set_sig_umr_segment(*seg, xlt_size);
4199 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4200 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4201 if (unlikely((*seg == qp->sq.qend)))
4202 *seg = mlx5_get_send_wqe(qp, 0);
4204 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4205 *seg += sizeof(struct mlx5_mkey_seg);
4206 *size += sizeof(struct mlx5_mkey_seg) / 16;
4207 if (unlikely((*seg == qp->sq.qend)))
4208 *seg = mlx5_get_send_wqe(qp, 0);
4210 ret = set_sig_data_segment(wr, qp, seg, size);
4214 sig_mr->sig->sig_status_checked = false;
4218 static int set_psv_wr(struct ib_sig_domain *domain,
4219 u32 psv_idx, void **seg, int *size)
4221 struct mlx5_seg_set_psv *psv_seg = *seg;
4223 memset(psv_seg, 0, sizeof(*psv_seg));
4224 psv_seg->psv_num = cpu_to_be32(psv_idx);
4225 switch (domain->sig_type) {
4226 case IB_SIG_TYPE_NONE:
4228 case IB_SIG_TYPE_T10_DIF:
4229 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4230 domain->sig.dif.app_tag);
4231 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4234 pr_err("Bad signature type (%d) is given.\n",
4239 *seg += sizeof(*psv_seg);
4240 *size += sizeof(*psv_seg) / 16;
4245 static int set_reg_wr(struct mlx5_ib_qp *qp,
4246 struct ib_reg_wr *wr,
4247 void **seg, int *size)
4249 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4250 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4251 int mr_list_size = mr->ndescs * mr->desc_size;
4252 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4254 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4255 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4256 "Invalid IB_SEND_INLINE send flag\n");
4260 set_reg_umr_seg(*seg, mr, umr_inline);
4261 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4262 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4263 if (unlikely((*seg == qp->sq.qend)))
4264 *seg = mlx5_get_send_wqe(qp, 0);
4266 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4267 *seg += sizeof(struct mlx5_mkey_seg);
4268 *size += sizeof(struct mlx5_mkey_seg) / 16;
4269 if (unlikely((*seg == qp->sq.qend)))
4270 *seg = mlx5_get_send_wqe(qp, 0);
4273 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size);
4274 *size += get_xlt_octo(mr_list_size);
4276 set_reg_data_seg(*seg, mr, pd);
4277 *seg += sizeof(struct mlx5_wqe_data_seg);
4278 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4283 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
4285 set_linv_umr_seg(*seg);
4286 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4287 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4288 if (unlikely((*seg == qp->sq.qend)))
4289 *seg = mlx5_get_send_wqe(qp, 0);
4290 set_linv_mkey_seg(*seg);
4291 *seg += sizeof(struct mlx5_mkey_seg);
4292 *size += sizeof(struct mlx5_mkey_seg) / 16;
4293 if (unlikely((*seg == qp->sq.qend)))
4294 *seg = mlx5_get_send_wqe(qp, 0);
4297 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4303 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4304 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4305 if ((i & 0xf) == 0) {
4306 void *buf = mlx5_get_send_wqe(qp, tidx);
4307 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4311 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4312 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4313 be32_to_cpu(p[j + 3]));
4317 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4318 struct mlx5_wqe_ctrl_seg **ctrl,
4319 struct ib_send_wr *wr, unsigned *idx,
4320 int *size, int nreq)
4322 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4325 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4326 *seg = mlx5_get_send_wqe(qp, *idx);
4328 *(uint32_t *)(*seg + 8) = 0;
4329 (*ctrl)->imm = send_ieth(wr);
4330 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4331 (wr->send_flags & IB_SEND_SIGNALED ?
4332 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4333 (wr->send_flags & IB_SEND_SOLICITED ?
4334 MLX5_WQE_CTRL_SOLICITED : 0);
4336 *seg += sizeof(**ctrl);
4337 *size = sizeof(**ctrl) / 16;
4342 static void finish_wqe(struct mlx5_ib_qp *qp,
4343 struct mlx5_wqe_ctrl_seg *ctrl,
4344 u8 size, unsigned idx, u64 wr_id,
4345 int nreq, u8 fence, u32 mlx5_opcode)
4349 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4350 mlx5_opcode | ((u32)opmod << 24));
4351 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4352 ctrl->fm_ce_se |= fence;
4353 if (unlikely(qp->wq_sig))
4354 ctrl->signature = wq_sig(ctrl);
4356 qp->sq.wrid[idx] = wr_id;
4357 qp->sq.w_list[idx].opcode = mlx5_opcode;
4358 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4359 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4360 qp->sq.w_list[idx].next = qp->sq.cur_post;
4364 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4365 struct ib_send_wr **bad_wr)
4367 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4368 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4369 struct mlx5_core_dev *mdev = dev->mdev;
4370 struct mlx5_ib_qp *qp;
4371 struct mlx5_ib_mr *mr;
4372 struct mlx5_wqe_data_seg *dpseg;
4373 struct mlx5_wqe_xrc_seg *xrc;
4375 int uninitialized_var(size);
4377 unsigned long flags;
4387 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4388 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4394 spin_lock_irqsave(&qp->sq.lock, flags);
4396 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4403 for (nreq = 0; wr; nreq++, wr = wr->next) {
4404 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4405 mlx5_ib_warn(dev, "\n");
4411 num_sge = wr->num_sge;
4412 if (unlikely(num_sge > qp->sq.max_gs)) {
4413 mlx5_ib_warn(dev, "\n");
4419 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4421 mlx5_ib_warn(dev, "\n");
4427 if (wr->opcode == IB_WR_LOCAL_INV ||
4428 wr->opcode == IB_WR_REG_MR) {
4429 fence = dev->umr_fence;
4430 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4431 } else if (wr->send_flags & IB_SEND_FENCE) {
4433 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4435 fence = MLX5_FENCE_MODE_FENCE;
4437 fence = qp->next_fence;
4440 switch (ibqp->qp_type) {
4441 case IB_QPT_XRC_INI:
4443 seg += sizeof(*xrc);
4444 size += sizeof(*xrc) / 16;
4447 switch (wr->opcode) {
4448 case IB_WR_RDMA_READ:
4449 case IB_WR_RDMA_WRITE:
4450 case IB_WR_RDMA_WRITE_WITH_IMM:
4451 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4453 seg += sizeof(struct mlx5_wqe_raddr_seg);
4454 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4457 case IB_WR_ATOMIC_CMP_AND_SWP:
4458 case IB_WR_ATOMIC_FETCH_AND_ADD:
4459 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4460 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4465 case IB_WR_LOCAL_INV:
4466 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4467 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4468 set_linv_wr(qp, &seg, &size);
4473 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4474 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4475 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4483 case IB_WR_REG_SIG_MR:
4484 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4485 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4487 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4488 err = set_sig_umr_wr(wr, qp, &seg, &size);
4490 mlx5_ib_warn(dev, "\n");
4495 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4496 fence, MLX5_OPCODE_UMR);
4498 * SET_PSV WQEs are not signaled and solicited
4501 wr->send_flags &= ~IB_SEND_SIGNALED;
4502 wr->send_flags |= IB_SEND_SOLICITED;
4503 err = begin_wqe(qp, &seg, &ctrl, wr,
4506 mlx5_ib_warn(dev, "\n");
4512 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4513 mr->sig->psv_memory.psv_idx, &seg,
4516 mlx5_ib_warn(dev, "\n");
4521 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4522 fence, MLX5_OPCODE_SET_PSV);
4523 err = begin_wqe(qp, &seg, &ctrl, wr,
4526 mlx5_ib_warn(dev, "\n");
4532 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4533 mr->sig->psv_wire.psv_idx, &seg,
4536 mlx5_ib_warn(dev, "\n");
4541 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4542 fence, MLX5_OPCODE_SET_PSV);
4543 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4553 switch (wr->opcode) {
4554 case IB_WR_RDMA_WRITE:
4555 case IB_WR_RDMA_WRITE_WITH_IMM:
4556 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4558 seg += sizeof(struct mlx5_wqe_raddr_seg);
4559 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4568 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4569 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4575 case MLX5_IB_QPT_HW_GSI:
4576 set_datagram_seg(seg, wr);
4577 seg += sizeof(struct mlx5_wqe_datagram_seg);
4578 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4579 if (unlikely((seg == qend)))
4580 seg = mlx5_get_send_wqe(qp, 0);
4583 set_datagram_seg(seg, wr);
4584 seg += sizeof(struct mlx5_wqe_datagram_seg);
4585 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4587 if (unlikely((seg == qend)))
4588 seg = mlx5_get_send_wqe(qp, 0);
4590 /* handle qp that supports ud offload */
4591 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4592 struct mlx5_wqe_eth_pad *pad;
4595 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4596 seg += sizeof(struct mlx5_wqe_eth_pad);
4597 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4599 seg = set_eth_seg(seg, wr, qend, qp, &size);
4601 if (unlikely((seg == qend)))
4602 seg = mlx5_get_send_wqe(qp, 0);
4605 case MLX5_IB_QPT_REG_UMR:
4606 if (wr->opcode != MLX5_IB_WR_UMR) {
4608 mlx5_ib_warn(dev, "bad opcode\n");
4611 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4612 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4613 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4616 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4617 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4618 if (unlikely((seg == qend)))
4619 seg = mlx5_get_send_wqe(qp, 0);
4620 set_reg_mkey_segment(seg, wr);
4621 seg += sizeof(struct mlx5_mkey_seg);
4622 size += sizeof(struct mlx5_mkey_seg) / 16;
4623 if (unlikely((seg == qend)))
4624 seg = mlx5_get_send_wqe(qp, 0);
4631 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4632 int uninitialized_var(sz);
4634 err = set_data_inl_seg(qp, wr, seg, &sz);
4635 if (unlikely(err)) {
4636 mlx5_ib_warn(dev, "\n");
4643 for (i = 0; i < num_sge; i++) {
4644 if (unlikely(dpseg == qend)) {
4645 seg = mlx5_get_send_wqe(qp, 0);
4648 if (likely(wr->sg_list[i].length)) {
4649 set_data_ptr_seg(dpseg, wr->sg_list + i);
4650 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4656 qp->next_fence = next_fence;
4657 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4658 mlx5_ib_opcode[wr->opcode]);
4661 dump_wqe(qp, idx, size);
4666 qp->sq.head += nreq;
4668 /* Make sure that descriptors are written before
4669 * updating doorbell record and ringing the doorbell
4673 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4675 /* Make sure doorbell record is visible to the HCA before
4676 * we hit doorbell */
4679 /* currently we support only regular doorbells */
4680 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4681 /* Make sure doorbells don't leak out of SQ spinlock
4682 * and reach the HCA out of order.
4685 bf->offset ^= bf->buf_size;
4688 spin_unlock_irqrestore(&qp->sq.lock, flags);
4693 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4695 sig->signature = calc_sig(sig, size);
4698 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4699 struct ib_recv_wr **bad_wr)
4701 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4702 struct mlx5_wqe_data_seg *scat;
4703 struct mlx5_rwqe_sig *sig;
4704 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4705 struct mlx5_core_dev *mdev = dev->mdev;
4706 unsigned long flags;
4712 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4713 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4715 spin_lock_irqsave(&qp->rq.lock, flags);
4717 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4724 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4726 for (nreq = 0; wr; nreq++, wr = wr->next) {
4727 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4733 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4739 scat = get_recv_wqe(qp, ind);
4743 for (i = 0; i < wr->num_sge; i++)
4744 set_data_ptr_seg(scat + i, wr->sg_list + i);
4746 if (i < qp->rq.max_gs) {
4747 scat[i].byte_count = 0;
4748 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4753 sig = (struct mlx5_rwqe_sig *)scat;
4754 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4757 qp->rq.wrid[ind] = wr->wr_id;
4759 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4764 qp->rq.head += nreq;
4766 /* Make sure that descriptors are written before
4771 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4774 spin_unlock_irqrestore(&qp->rq.lock, flags);
4779 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4781 switch (mlx5_state) {
4782 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4783 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4784 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4785 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4786 case MLX5_QP_STATE_SQ_DRAINING:
4787 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4788 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4789 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4794 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4796 switch (mlx5_mig_state) {
4797 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4798 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4799 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4804 static int to_ib_qp_access_flags(int mlx5_flags)
4808 if (mlx5_flags & MLX5_QP_BIT_RRE)
4809 ib_flags |= IB_ACCESS_REMOTE_READ;
4810 if (mlx5_flags & MLX5_QP_BIT_RWE)
4811 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4812 if (mlx5_flags & MLX5_QP_BIT_RAE)
4813 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4818 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4819 struct rdma_ah_attr *ah_attr,
4820 struct mlx5_qp_path *path)
4823 memset(ah_attr, 0, sizeof(*ah_attr));
4825 if (!path->port || path->port > ibdev->num_ports)
4828 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4830 rdma_ah_set_port_num(ah_attr, path->port);
4831 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4833 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4834 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4835 rdma_ah_set_static_rate(ah_attr,
4836 path->static_rate ? path->static_rate - 5 : 0);
4837 if (path->grh_mlid & (1 << 7)) {
4838 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4840 rdma_ah_set_grh(ah_attr, NULL,
4844 (tc_fl >> 20) & 0xff);
4845 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4849 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4850 struct mlx5_ib_sq *sq,
4855 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4858 sq->state = *sq_state;
4864 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4865 struct mlx5_ib_rq *rq,
4873 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4874 out = kvzalloc(inlen, GFP_KERNEL);
4878 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4882 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4883 *rq_state = MLX5_GET(rqc, rqc, state);
4884 rq->state = *rq_state;
4891 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4892 struct mlx5_ib_qp *qp, u8 *qp_state)
4894 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4895 [MLX5_RQC_STATE_RST] = {
4896 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4897 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4898 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4899 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4901 [MLX5_RQC_STATE_RDY] = {
4902 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4903 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4904 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4905 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4907 [MLX5_RQC_STATE_ERR] = {
4908 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4909 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4910 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4911 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4913 [MLX5_RQ_STATE_NA] = {
4914 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4915 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4916 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4917 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4921 *qp_state = sqrq_trans[rq_state][sq_state];
4923 if (*qp_state == MLX5_QP_STATE_BAD) {
4924 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4925 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4926 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4930 if (*qp_state == MLX5_QP_STATE)
4931 *qp_state = qp->state;
4936 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4937 struct mlx5_ib_qp *qp,
4938 u8 *raw_packet_qp_state)
4940 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4941 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4942 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4944 u8 sq_state = MLX5_SQ_STATE_NA;
4945 u8 rq_state = MLX5_RQ_STATE_NA;
4947 if (qp->sq.wqe_cnt) {
4948 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4953 if (qp->rq.wqe_cnt) {
4954 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4959 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4960 raw_packet_qp_state);
4963 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4964 struct ib_qp_attr *qp_attr)
4966 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4967 struct mlx5_qp_context *context;
4972 outb = kzalloc(outlen, GFP_KERNEL);
4976 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4981 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4982 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4984 mlx5_state = be32_to_cpu(context->flags) >> 28;
4986 qp->state = to_ib_qp_state(mlx5_state);
4987 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4988 qp_attr->path_mig_state =
4989 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4990 qp_attr->qkey = be32_to_cpu(context->qkey);
4991 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4992 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4993 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4994 qp_attr->qp_access_flags =
4995 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4997 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4998 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4999 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5000 qp_attr->alt_pkey_index =
5001 be16_to_cpu(context->alt_path.pkey_index);
5002 qp_attr->alt_port_num =
5003 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5006 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5007 qp_attr->port_num = context->pri_path.port;
5009 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5010 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5012 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5014 qp_attr->max_dest_rd_atomic =
5015 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5016 qp_attr->min_rnr_timer =
5017 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5018 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5019 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5020 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5021 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
5028 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5029 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5030 struct ib_qp_init_attr *qp_init_attr)
5032 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5034 u32 access_flags = 0;
5035 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5038 int supported_mask = IB_QP_STATE |
5039 IB_QP_ACCESS_FLAGS |
5041 IB_QP_MIN_RNR_TIMER |
5046 if (qp_attr_mask & ~supported_mask)
5048 if (mqp->state != IB_QPS_RTR)
5051 out = kzalloc(outlen, GFP_KERNEL);
5055 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5059 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5061 if (qp_attr_mask & IB_QP_STATE)
5062 qp_attr->qp_state = IB_QPS_RTR;
5064 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5065 if (MLX5_GET(dctc, dctc, rre))
5066 access_flags |= IB_ACCESS_REMOTE_READ;
5067 if (MLX5_GET(dctc, dctc, rwe))
5068 access_flags |= IB_ACCESS_REMOTE_WRITE;
5069 if (MLX5_GET(dctc, dctc, rae))
5070 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5071 qp_attr->qp_access_flags = access_flags;
5074 if (qp_attr_mask & IB_QP_PORT)
5075 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5076 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5077 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5078 if (qp_attr_mask & IB_QP_AV) {
5079 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5080 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5081 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5082 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5084 if (qp_attr_mask & IB_QP_PATH_MTU)
5085 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5086 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5087 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5093 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5094 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5096 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5097 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5099 u8 raw_packet_qp_state;
5101 if (ibqp->rwq_ind_tbl)
5104 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5105 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5108 /* Not all of output fields are applicable, make sure to zero them */
5109 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5110 memset(qp_attr, 0, sizeof(*qp_attr));
5112 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5113 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5114 qp_attr_mask, qp_init_attr);
5116 mutex_lock(&qp->mutex);
5118 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5119 qp->flags & MLX5_IB_QP_UNDERLAY) {
5120 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5123 qp->state = raw_packet_qp_state;
5124 qp_attr->port_num = 1;
5126 err = query_qp_attr(dev, qp, qp_attr);
5131 qp_attr->qp_state = qp->state;
5132 qp_attr->cur_qp_state = qp_attr->qp_state;
5133 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5134 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5136 if (!ibqp->uobject) {
5137 qp_attr->cap.max_send_wr = qp->sq.max_post;
5138 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5139 qp_init_attr->qp_context = ibqp->qp_context;
5141 qp_attr->cap.max_send_wr = 0;
5142 qp_attr->cap.max_send_sge = 0;
5145 qp_init_attr->qp_type = ibqp->qp_type;
5146 qp_init_attr->recv_cq = ibqp->recv_cq;
5147 qp_init_attr->send_cq = ibqp->send_cq;
5148 qp_init_attr->srq = ibqp->srq;
5149 qp_attr->cap.max_inline_data = qp->max_inline_data;
5151 qp_init_attr->cap = qp_attr->cap;
5153 qp_init_attr->create_flags = 0;
5154 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5155 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5157 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5158 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5159 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5160 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5161 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5162 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5163 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5164 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5166 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5167 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5170 mutex_unlock(&qp->mutex);
5174 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5175 struct ib_ucontext *context,
5176 struct ib_udata *udata)
5178 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5179 struct mlx5_ib_xrcd *xrcd;
5182 if (!MLX5_CAP_GEN(dev->mdev, xrc))
5183 return ERR_PTR(-ENOSYS);
5185 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5187 return ERR_PTR(-ENOMEM);
5189 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
5192 return ERR_PTR(-ENOMEM);
5195 return &xrcd->ibxrcd;
5198 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5200 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5201 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5204 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
5206 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5212 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5214 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5215 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5216 struct ib_event event;
5218 if (rwq->ibwq.event_handler) {
5219 event.device = rwq->ibwq.device;
5220 event.element.wq = &rwq->ibwq;
5222 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5223 event.event = IB_EVENT_WQ_FATAL;
5226 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5230 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5234 static int set_delay_drop(struct mlx5_ib_dev *dev)
5238 mutex_lock(&dev->delay_drop.lock);
5239 if (dev->delay_drop.activate)
5242 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5246 dev->delay_drop.activate = true;
5248 mutex_unlock(&dev->delay_drop.lock);
5251 atomic_inc(&dev->delay_drop.rqs_cnt);
5255 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5256 struct ib_wq_init_attr *init_attr)
5258 struct mlx5_ib_dev *dev;
5259 int has_net_offloads;
5267 dev = to_mdev(pd->device);
5269 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5270 in = kvzalloc(inlen, GFP_KERNEL);
5274 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5275 MLX5_SET(rqc, rqc, mem_rq_type,
5276 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5277 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5278 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5279 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5280 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5281 wq = MLX5_ADDR_OF(rqc, rqc, wq);
5282 MLX5_SET(wq, wq, wq_type,
5283 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5284 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5285 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5286 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5287 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5291 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5294 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5295 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5296 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5297 MLX5_SET(wq, wq, log_wqe_stride_size,
5298 rwq->single_stride_log_num_of_bytes -
5299 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5300 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5301 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5303 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5304 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5305 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5306 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5307 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5308 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5309 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5310 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5311 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5312 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5317 MLX5_SET(rqc, rqc, vsd, 1);
5319 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5320 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5321 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5325 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5327 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5328 if (!(dev->ib_dev.attrs.raw_packet_caps &
5329 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5330 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5334 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5336 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5337 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5338 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5339 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5340 err = set_delay_drop(dev);
5342 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5344 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5346 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5354 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5355 struct ib_wq_init_attr *wq_init_attr,
5356 struct mlx5_ib_create_wq *ucmd,
5357 struct mlx5_ib_rwq *rwq)
5359 /* Sanity check RQ size before proceeding */
5360 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5363 if (!ucmd->rq_wqe_count)
5366 rwq->wqe_count = ucmd->rq_wqe_count;
5367 rwq->wqe_shift = ucmd->rq_wqe_shift;
5368 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
5369 rwq->log_rq_stride = rwq->wqe_shift;
5370 rwq->log_rq_size = ilog2(rwq->wqe_count);
5374 static int prepare_user_rq(struct ib_pd *pd,
5375 struct ib_wq_init_attr *init_attr,
5376 struct ib_udata *udata,
5377 struct mlx5_ib_rwq *rwq)
5379 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5380 struct mlx5_ib_create_wq ucmd = {};
5382 size_t required_cmd_sz;
5384 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5385 + sizeof(ucmd.single_stride_log_num_of_bytes);
5386 if (udata->inlen < required_cmd_sz) {
5387 mlx5_ib_dbg(dev, "invalid inlen\n");
5391 if (udata->inlen > sizeof(ucmd) &&
5392 !ib_is_udata_cleared(udata, sizeof(ucmd),
5393 udata->inlen - sizeof(ucmd))) {
5394 mlx5_ib_dbg(dev, "inlen is not supported\n");
5398 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5399 mlx5_ib_dbg(dev, "copy failed\n");
5403 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5404 mlx5_ib_dbg(dev, "invalid comp mask\n");
5406 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5407 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5408 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5411 if ((ucmd.single_stride_log_num_of_bytes <
5412 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5413 (ucmd.single_stride_log_num_of_bytes >
5414 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5415 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5416 ucmd.single_stride_log_num_of_bytes,
5417 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5418 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5421 if ((ucmd.single_wqe_log_num_of_strides >
5422 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5423 (ucmd.single_wqe_log_num_of_strides <
5424 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5425 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5426 ucmd.single_wqe_log_num_of_strides,
5427 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5428 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5431 rwq->single_stride_log_num_of_bytes =
5432 ucmd.single_stride_log_num_of_bytes;
5433 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5434 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5435 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5438 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5440 mlx5_ib_dbg(dev, "err %d\n", err);
5444 err = create_user_rq(dev, pd, rwq, &ucmd);
5446 mlx5_ib_dbg(dev, "err %d\n", err);
5451 rwq->user_index = ucmd.user_index;
5455 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5456 struct ib_wq_init_attr *init_attr,
5457 struct ib_udata *udata)
5459 struct mlx5_ib_dev *dev;
5460 struct mlx5_ib_rwq *rwq;
5461 struct mlx5_ib_create_wq_resp resp = {};
5462 size_t min_resp_len;
5466 return ERR_PTR(-ENOSYS);
5468 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5469 if (udata->outlen && udata->outlen < min_resp_len)
5470 return ERR_PTR(-EINVAL);
5472 dev = to_mdev(pd->device);
5473 switch (init_attr->wq_type) {
5475 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5477 return ERR_PTR(-ENOMEM);
5478 err = prepare_user_rq(pd, init_attr, udata, rwq);
5481 err = create_rq(rwq, pd, init_attr);
5486 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5487 init_attr->wq_type);
5488 return ERR_PTR(-EINVAL);
5491 rwq->ibwq.wq_num = rwq->core_qp.qpn;
5492 rwq->ibwq.state = IB_WQS_RESET;
5493 if (udata->outlen) {
5494 resp.response_length = offsetof(typeof(resp), response_length) +
5495 sizeof(resp.response_length);
5496 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5501 rwq->core_qp.event = mlx5_ib_wq_event;
5502 rwq->ibwq.event_handler = init_attr->event_handler;
5506 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5508 destroy_user_rq(dev, pd, rwq);
5511 return ERR_PTR(err);
5514 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5516 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5517 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5519 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5520 destroy_user_rq(dev, wq->pd, rwq);
5526 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5527 struct ib_rwq_ind_table_init_attr *init_attr,
5528 struct ib_udata *udata)
5530 struct mlx5_ib_dev *dev = to_mdev(device);
5531 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5532 int sz = 1 << init_attr->log_ind_tbl_size;
5533 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5534 size_t min_resp_len;
5541 if (udata->inlen > 0 &&
5542 !ib_is_udata_cleared(udata, 0,
5544 return ERR_PTR(-EOPNOTSUPP);
5546 if (init_attr->log_ind_tbl_size >
5547 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5548 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5549 init_attr->log_ind_tbl_size,
5550 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5551 return ERR_PTR(-EINVAL);
5554 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5555 if (udata->outlen && udata->outlen < min_resp_len)
5556 return ERR_PTR(-EINVAL);
5558 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5560 return ERR_PTR(-ENOMEM);
5562 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5563 in = kvzalloc(inlen, GFP_KERNEL);
5569 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5571 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5572 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5574 for (i = 0; i < sz; i++)
5575 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5577 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5583 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5584 if (udata->outlen) {
5585 resp.response_length = offsetof(typeof(resp), response_length) +
5586 sizeof(resp.response_length);
5587 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5592 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5595 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5598 return ERR_PTR(err);
5601 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5603 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5604 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5606 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5612 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5613 u32 wq_attr_mask, struct ib_udata *udata)
5615 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5616 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5617 struct mlx5_ib_modify_wq ucmd = {};
5618 size_t required_cmd_sz;
5626 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5627 if (udata->inlen < required_cmd_sz)
5630 if (udata->inlen > sizeof(ucmd) &&
5631 !ib_is_udata_cleared(udata, sizeof(ucmd),
5632 udata->inlen - sizeof(ucmd)))
5635 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5638 if (ucmd.comp_mask || ucmd.reserved)
5641 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5642 in = kvzalloc(inlen, GFP_KERNEL);
5646 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5648 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5649 wq_attr->curr_wq_state : wq->state;
5650 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5651 wq_attr->wq_state : curr_wq_state;
5652 if (curr_wq_state == IB_WQS_ERR)
5653 curr_wq_state = MLX5_RQC_STATE_ERR;
5654 if (wq_state == IB_WQS_ERR)
5655 wq_state = MLX5_RQC_STATE_ERR;
5656 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5657 MLX5_SET(rqc, rqc, state, wq_state);
5659 if (wq_attr_mask & IB_WQ_FLAGS) {
5660 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5661 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5662 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5663 mlx5_ib_dbg(dev, "VLAN offloads are not "
5668 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5669 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5670 MLX5_SET(rqc, rqc, vsd,
5671 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5674 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5675 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5681 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5682 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5683 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5684 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5685 MLX5_SET(rqc, rqc, counter_set_id,
5686 dev->port->cnts.set_id);
5688 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5692 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5694 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;