2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
41 /* not supported currently */
42 static int wq_signature;
45 MLX5_IB_ACK_REQ_FREQ = 8,
49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
51 MLX5_IB_LINK_TYPE_IB = 0,
52 MLX5_IB_LINK_TYPE_ETH = 1
56 MLX5_IB_SQ_STRIDE = 6,
57 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
60 static const u32 mlx5_ib_opcode[] = {
61 [IB_WR_SEND] = MLX5_OPCODE_SEND,
62 [IB_WR_LSO] = MLX5_OPCODE_LSO,
63 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
64 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
65 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
66 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
67 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
68 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
69 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
70 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
71 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
72 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
73 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
74 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
77 struct mlx5_wqe_eth_pad {
81 enum raw_qp_set_mask_map {
82 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
83 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
86 struct mlx5_modify_raw_qp_param {
89 u32 set_mask; /* raw_qp_set_mask_map */
91 struct mlx5_rate_limit rl;
96 static void get_cqs(enum ib_qp_type qp_type,
97 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
98 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
100 static int is_qp0(enum ib_qp_type qp_type)
102 return qp_type == IB_QPT_SMI;
105 static int is_sqp(enum ib_qp_type qp_type)
107 return is_qp0(qp_type) || is_qp1(qp_type);
110 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
112 return mlx5_buf_offset(&qp->buf, offset);
115 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
117 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
120 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
122 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
126 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
128 * @qp: QP to copy from.
129 * @send: copy from the send queue when non-zero, use the receive queue
131 * @wqe_index: index to start copying from. For send work queues, the
132 * wqe_index is in units of MLX5_SEND_WQE_BB.
133 * For receive work queue, it is the number of work queue
134 * element in the queue.
135 * @buffer: destination buffer.
136 * @length: maximum number of bytes to copy.
138 * Copies at least a single WQE, but may copy more data.
140 * Return: the number of bytes copied, or an error code.
142 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
143 void *buffer, u32 length,
144 struct mlx5_ib_qp_base *base)
146 struct ib_device *ibdev = qp->ibqp.device;
147 struct mlx5_ib_dev *dev = to_mdev(ibdev);
148 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
151 struct ib_umem *umem = base->ubuffer.umem;
152 u32 first_copy_length;
156 if (wq->wqe_cnt == 0) {
157 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
162 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
163 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
165 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
168 if (offset > umem->length ||
169 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
172 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
173 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
178 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
179 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
181 wqe_length = ds * MLX5_WQE_DS_UNITS;
183 wqe_length = 1 << wq->wqe_shift;
186 if (wqe_length <= first_copy_length)
187 return first_copy_length;
189 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
190 wqe_length - first_copy_length);
197 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
199 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
200 struct ib_event event;
202 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
203 /* This event is only valid for trans_qps */
204 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
207 if (ibqp->event_handler) {
208 event.device = ibqp->device;
209 event.element.qp = ibqp;
211 case MLX5_EVENT_TYPE_PATH_MIG:
212 event.event = IB_EVENT_PATH_MIG;
214 case MLX5_EVENT_TYPE_COMM_EST:
215 event.event = IB_EVENT_COMM_EST;
217 case MLX5_EVENT_TYPE_SQ_DRAINED:
218 event.event = IB_EVENT_SQ_DRAINED;
220 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
221 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
223 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
224 event.event = IB_EVENT_QP_FATAL;
226 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
227 event.event = IB_EVENT_PATH_MIG_ERR;
229 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
230 event.event = IB_EVENT_QP_REQ_ERR;
232 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
233 event.event = IB_EVENT_QP_ACCESS_ERR;
236 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
240 ibqp->event_handler(&event, ibqp->qp_context);
244 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
245 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
250 /* Sanity check RQ size before proceeding */
251 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
257 qp->rq.wqe_shift = 0;
258 cap->max_recv_wr = 0;
259 cap->max_recv_sge = 0;
262 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
263 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
265 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
266 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
268 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
269 qp->rq.max_post = qp->rq.wqe_cnt;
271 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
272 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
273 wqe_size = roundup_pow_of_two(wqe_size);
274 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
275 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
276 qp->rq.wqe_cnt = wq_size / wqe_size;
277 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
278 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
280 MLX5_CAP_GEN(dev->mdev,
284 qp->rq.wqe_shift = ilog2(wqe_size);
285 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
286 qp->rq.max_post = qp->rq.wqe_cnt;
293 static int sq_overhead(struct ib_qp_init_attr *attr)
297 switch (attr->qp_type) {
299 size += sizeof(struct mlx5_wqe_xrc_seg);
302 size += sizeof(struct mlx5_wqe_ctrl_seg) +
303 max(sizeof(struct mlx5_wqe_atomic_seg) +
304 sizeof(struct mlx5_wqe_raddr_seg),
305 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
306 sizeof(struct mlx5_mkey_seg) +
307 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
308 MLX5_IB_UMR_OCTOWORD);
315 size += sizeof(struct mlx5_wqe_ctrl_seg) +
316 max(sizeof(struct mlx5_wqe_raddr_seg),
317 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
318 sizeof(struct mlx5_mkey_seg));
322 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
323 size += sizeof(struct mlx5_wqe_eth_pad) +
324 sizeof(struct mlx5_wqe_eth_seg);
327 case MLX5_IB_QPT_HW_GSI:
328 size += sizeof(struct mlx5_wqe_ctrl_seg) +
329 sizeof(struct mlx5_wqe_datagram_seg);
332 case MLX5_IB_QPT_REG_UMR:
333 size += sizeof(struct mlx5_wqe_ctrl_seg) +
334 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
335 sizeof(struct mlx5_mkey_seg);
345 static int calc_send_wqe(struct ib_qp_init_attr *attr)
350 size = sq_overhead(attr);
354 if (attr->cap.max_inline_data) {
355 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
356 attr->cap.max_inline_data;
359 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
360 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
361 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
362 return MLX5_SIG_WQE_SIZE;
364 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
367 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
371 if (attr->qp_type == IB_QPT_RC)
372 max_sge = (min_t(int, wqe_size, 512) -
373 sizeof(struct mlx5_wqe_ctrl_seg) -
374 sizeof(struct mlx5_wqe_raddr_seg)) /
375 sizeof(struct mlx5_wqe_data_seg);
376 else if (attr->qp_type == IB_QPT_XRC_INI)
377 max_sge = (min_t(int, wqe_size, 512) -
378 sizeof(struct mlx5_wqe_ctrl_seg) -
379 sizeof(struct mlx5_wqe_xrc_seg) -
380 sizeof(struct mlx5_wqe_raddr_seg)) /
381 sizeof(struct mlx5_wqe_data_seg);
383 max_sge = (wqe_size - sq_overhead(attr)) /
384 sizeof(struct mlx5_wqe_data_seg);
386 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
387 sizeof(struct mlx5_wqe_data_seg));
390 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
391 struct mlx5_ib_qp *qp)
396 if (!attr->cap.max_send_wr)
399 wqe_size = calc_send_wqe(attr);
400 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
404 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
405 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
406 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
410 qp->max_inline_data = wqe_size - sq_overhead(attr) -
411 sizeof(struct mlx5_wqe_inline_seg);
412 attr->cap.max_inline_data = qp->max_inline_data;
414 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
415 qp->signature_en = true;
417 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
418 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
419 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
420 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
421 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
423 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
426 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
427 qp->sq.max_gs = get_send_sge(attr, wqe_size);
428 if (qp->sq.max_gs < attr->cap.max_send_sge)
431 attr->cap.max_send_sge = qp->sq.max_gs;
432 qp->sq.max_post = wq_size / wqe_size;
433 attr->cap.max_send_wr = qp->sq.max_post;
438 static int set_user_buf_size(struct mlx5_ib_dev *dev,
439 struct mlx5_ib_qp *qp,
440 struct mlx5_ib_create_qp *ucmd,
441 struct mlx5_ib_qp_base *base,
442 struct ib_qp_init_attr *attr)
444 int desc_sz = 1 << qp->sq.wqe_shift;
446 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
447 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
448 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
452 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
453 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
454 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
458 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
460 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
461 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
463 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
467 if (attr->qp_type == IB_QPT_RAW_PACKET ||
468 qp->flags & MLX5_IB_QP_UNDERLAY) {
469 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
470 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
472 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
473 (qp->sq.wqe_cnt << 6);
479 static int qp_has_rq(struct ib_qp_init_attr *attr)
481 if (attr->qp_type == IB_QPT_XRC_INI ||
482 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
483 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
484 !attr->cap.max_recv_wr)
491 /* this is the first blue flame register in the array of bfregs assigned
492 * to a processes. Since we do not use it for blue flame but rather
493 * regular 64 bit doorbells, we do not need a lock for maintaiing
496 NUM_NON_BLUE_FLAME_BFREGS = 1,
499 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
501 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
504 static int num_med_bfreg(struct mlx5_ib_dev *dev,
505 struct mlx5_bfreg_info *bfregi)
509 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
510 NUM_NON_BLUE_FLAME_BFREGS;
512 return n >= 0 ? n : 0;
515 static int first_med_bfreg(struct mlx5_ib_dev *dev,
516 struct mlx5_bfreg_info *bfregi)
518 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
521 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
522 struct mlx5_bfreg_info *bfregi)
526 med = num_med_bfreg(dev, bfregi);
530 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
531 struct mlx5_bfreg_info *bfregi)
535 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
536 if (!bfregi->count[i]) {
545 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
546 struct mlx5_bfreg_info *bfregi)
548 int minidx = first_med_bfreg(dev, bfregi);
554 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
555 if (bfregi->count[i] < bfregi->count[minidx])
557 if (!bfregi->count[minidx])
561 bfregi->count[minidx]++;
565 static int alloc_bfreg(struct mlx5_ib_dev *dev,
566 struct mlx5_bfreg_info *bfregi)
568 int bfregn = -ENOMEM;
570 mutex_lock(&bfregi->lock);
571 if (bfregi->ver >= 2) {
572 bfregn = alloc_high_class_bfreg(dev, bfregi);
574 bfregn = alloc_med_class_bfreg(dev, bfregi);
578 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
580 bfregi->count[bfregn]++;
582 mutex_unlock(&bfregi->lock);
587 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
589 mutex_lock(&bfregi->lock);
590 bfregi->count[bfregn]--;
591 mutex_unlock(&bfregi->lock);
594 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
597 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
598 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
599 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
600 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
601 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
602 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
603 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
608 static int to_mlx5_st(enum ib_qp_type type)
611 case IB_QPT_RC: return MLX5_QP_ST_RC;
612 case IB_QPT_UC: return MLX5_QP_ST_UC;
613 case IB_QPT_UD: return MLX5_QP_ST_UD;
614 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
616 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
617 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
618 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
619 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
620 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
621 case IB_QPT_RAW_PACKET:
622 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
624 default: return -EINVAL;
628 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
629 struct mlx5_ib_cq *recv_cq);
630 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
631 struct mlx5_ib_cq *recv_cq);
633 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
634 struct mlx5_bfreg_info *bfregi, u32 bfregn,
637 unsigned int bfregs_per_sys_page;
638 u32 index_of_sys_page;
641 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
642 MLX5_NON_FP_BFREGS_PER_UAR;
643 index_of_sys_page = bfregn / bfregs_per_sys_page;
646 index_of_sys_page += bfregi->num_static_sys_pages;
648 if (index_of_sys_page >= bfregi->num_sys_pages)
651 if (bfregn > bfregi->num_dyn_bfregs ||
652 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
653 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
658 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
659 return bfregi->sys_pages[index_of_sys_page] + offset;
662 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
664 unsigned long addr, size_t size,
665 struct ib_umem **umem,
666 int *npages, int *page_shift, int *ncont,
671 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
673 mlx5_ib_dbg(dev, "umem_get failed\n");
674 return PTR_ERR(*umem);
677 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
679 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
681 mlx5_ib_warn(dev, "bad offset\n");
685 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
686 addr, size, *npages, *page_shift, *ncont, *offset);
691 ib_umem_release(*umem);
697 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
698 struct mlx5_ib_rwq *rwq)
700 struct mlx5_ib_ucontext *context;
702 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
703 atomic_dec(&dev->delay_drop.rqs_cnt);
705 context = to_mucontext(pd->uobject->context);
706 mlx5_ib_db_unmap_user(context, &rwq->db);
708 ib_umem_release(rwq->umem);
711 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
712 struct mlx5_ib_rwq *rwq,
713 struct mlx5_ib_create_wq *ucmd)
715 struct mlx5_ib_ucontext *context;
725 context = to_mucontext(pd->uobject->context);
726 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
727 rwq->buf_size, 0, 0);
728 if (IS_ERR(rwq->umem)) {
729 mlx5_ib_dbg(dev, "umem_get failed\n");
730 err = PTR_ERR(rwq->umem);
734 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
736 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
737 &rwq->rq_page_offset);
739 mlx5_ib_warn(dev, "bad offset\n");
743 rwq->rq_num_pas = ncont;
744 rwq->page_shift = page_shift;
745 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
746 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
748 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
749 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
750 npages, page_shift, ncont, offset);
752 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
754 mlx5_ib_dbg(dev, "map failed\n");
758 rwq->create_type = MLX5_WQ_USER;
762 ib_umem_release(rwq->umem);
766 static int adjust_bfregn(struct mlx5_ib_dev *dev,
767 struct mlx5_bfreg_info *bfregi, int bfregn)
769 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
770 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
773 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
774 struct mlx5_ib_qp *qp, struct ib_udata *udata,
775 struct ib_qp_init_attr *attr,
777 struct mlx5_ib_create_qp_resp *resp, int *inlen,
778 struct mlx5_ib_qp_base *base)
780 struct mlx5_ib_ucontext *context;
781 struct mlx5_ib_create_qp ucmd;
782 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
793 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
795 mlx5_ib_dbg(dev, "copy failed\n");
799 context = to_mucontext(pd->uobject->context);
800 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
801 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
802 ucmd.bfreg_index, true);
806 bfregn = MLX5_IB_INVALID_BFREG;
807 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
809 * TBD: should come from the verbs when we have the API
811 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
812 bfregn = MLX5_CROSS_CHANNEL_BFREG;
815 bfregn = alloc_bfreg(dev, &context->bfregi);
820 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
821 if (bfregn != MLX5_IB_INVALID_BFREG)
822 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
826 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
827 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
829 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
833 if (ucmd.buf_addr && ubuffer->buf_size) {
834 ubuffer->buf_addr = ucmd.buf_addr;
835 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
837 &ubuffer->umem, &npages, &page_shift,
842 ubuffer->umem = NULL;
845 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
846 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
847 *in = kvzalloc(*inlen, GFP_KERNEL);
853 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
855 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
857 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
859 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
860 MLX5_SET(qpc, qpc, page_offset, offset);
862 MLX5_SET(qpc, qpc, uar_page, uar_index);
863 if (bfregn != MLX5_IB_INVALID_BFREG)
864 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
866 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
869 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
871 mlx5_ib_dbg(dev, "map failed\n");
875 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
877 mlx5_ib_dbg(dev, "copy failed\n");
880 qp->create_type = MLX5_QP_USER;
885 mlx5_ib_db_unmap_user(context, &qp->db);
892 ib_umem_release(ubuffer->umem);
895 if (bfregn != MLX5_IB_INVALID_BFREG)
896 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
900 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
901 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
903 struct mlx5_ib_ucontext *context;
905 context = to_mucontext(pd->uobject->context);
906 mlx5_ib_db_unmap_user(context, &qp->db);
907 if (base->ubuffer.umem)
908 ib_umem_release(base->ubuffer.umem);
911 * Free only the BFREGs which are handled by the kernel.
912 * BFREGs of UARs allocated dynamically are handled by user.
914 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
915 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
918 static int create_kernel_qp(struct mlx5_ib_dev *dev,
919 struct ib_qp_init_attr *init_attr,
920 struct mlx5_ib_qp *qp,
921 u32 **in, int *inlen,
922 struct mlx5_ib_qp_base *base)
928 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
929 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
930 IB_QP_CREATE_IPOIB_UD_LSO |
931 IB_QP_CREATE_NETIF_QP |
932 mlx5_ib_create_qp_sqpn_qp1()))
935 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
936 qp->bf.bfreg = &dev->fp_bfreg;
938 qp->bf.bfreg = &dev->bfreg;
940 /* We need to divide by two since each register is comprised of
941 * two buffers of identical size, namely odd and even
943 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
944 uar_index = qp->bf.bfreg->index;
946 err = calc_sq_size(dev, init_attr, qp);
948 mlx5_ib_dbg(dev, "err %d\n", err);
953 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
954 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
956 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
958 mlx5_ib_dbg(dev, "err %d\n", err);
962 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
963 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
964 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
965 *in = kvzalloc(*inlen, GFP_KERNEL);
971 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
972 MLX5_SET(qpc, qpc, uar_page, uar_index);
973 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
975 /* Set "fast registration enabled" for all kernel QPs */
976 MLX5_SET(qpc, qpc, fre, 1);
977 MLX5_SET(qpc, qpc, rlky, 1);
979 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
980 MLX5_SET(qpc, qpc, deth_sqpn, 1);
981 qp->flags |= MLX5_IB_QP_SQPN_QP1;
984 mlx5_fill_page_array(&qp->buf,
985 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
987 err = mlx5_db_alloc(dev->mdev, &qp->db);
989 mlx5_ib_dbg(dev, "err %d\n", err);
993 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
994 sizeof(*qp->sq.wrid), GFP_KERNEL);
995 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
996 sizeof(*qp->sq.wr_data), GFP_KERNEL);
997 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
998 sizeof(*qp->rq.wrid), GFP_KERNEL);
999 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1000 sizeof(*qp->sq.w_list), GFP_KERNEL);
1001 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1002 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1004 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1005 !qp->sq.w_list || !qp->sq.wqe_head) {
1009 qp->create_type = MLX5_QP_KERNEL;
1014 kvfree(qp->sq.wqe_head);
1015 kvfree(qp->sq.w_list);
1016 kvfree(qp->sq.wrid);
1017 kvfree(qp->sq.wr_data);
1018 kvfree(qp->rq.wrid);
1019 mlx5_db_free(dev->mdev, &qp->db);
1025 mlx5_buf_free(dev->mdev, &qp->buf);
1029 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1031 kvfree(qp->sq.wqe_head);
1032 kvfree(qp->sq.w_list);
1033 kvfree(qp->sq.wrid);
1034 kvfree(qp->sq.wr_data);
1035 kvfree(qp->rq.wrid);
1036 mlx5_db_free(dev->mdev, &qp->db);
1037 mlx5_buf_free(dev->mdev, &qp->buf);
1040 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1042 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1043 (attr->qp_type == MLX5_IB_QPT_DCI) ||
1044 (attr->qp_type == IB_QPT_XRC_INI))
1046 else if (!qp->has_rq)
1047 return MLX5_ZERO_LEN_RQ;
1049 return MLX5_NON_ZERO_RQ;
1052 static int is_connected(enum ib_qp_type qp_type)
1054 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1060 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1061 struct mlx5_ib_qp *qp,
1062 struct mlx5_ib_sq *sq, u32 tdn)
1064 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1065 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1067 MLX5_SET(tisc, tisc, transport_domain, tdn);
1068 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1069 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1071 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1074 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1075 struct mlx5_ib_sq *sq)
1077 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1080 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1081 struct mlx5_ib_sq *sq)
1084 mlx5_del_flow_rules(sq->flow_rule);
1087 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1088 struct mlx5_ib_sq *sq, void *qpin,
1091 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1095 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1104 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1105 &sq->ubuffer.umem, &npages, &page_shift,
1110 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1111 in = kvzalloc(inlen, GFP_KERNEL);
1117 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1118 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1119 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1120 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1121 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1122 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1123 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1124 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1125 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1126 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1127 MLX5_CAP_ETH(dev->mdev, swp))
1128 MLX5_SET(sqc, sqc, allow_swp, 1);
1130 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1131 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1132 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1133 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1134 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1135 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1136 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1137 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1138 MLX5_SET(wq, wq, page_offset, offset);
1140 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1141 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1143 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1150 err = create_flow_rule_vport_sq(dev, sq);
1157 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1160 ib_umem_release(sq->ubuffer.umem);
1161 sq->ubuffer.umem = NULL;
1166 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1167 struct mlx5_ib_sq *sq)
1169 destroy_flow_rule_vport_sq(dev, sq);
1170 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1171 ib_umem_release(sq->ubuffer.umem);
1174 static size_t get_rq_pas_size(void *qpc)
1176 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1177 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1178 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1179 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1180 u32 po_quanta = 1 << (log_page_size - 6);
1181 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1182 u32 page_size = 1 << log_page_size;
1183 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1184 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1186 return rq_num_pas * sizeof(u64);
1189 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1190 struct mlx5_ib_rq *rq, void *qpin,
1193 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1199 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1200 size_t rq_pas_size = get_rq_pas_size(qpc);
1204 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1207 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1208 in = kvzalloc(inlen, GFP_KERNEL);
1212 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1213 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1214 MLX5_SET(rqc, rqc, vsd, 1);
1215 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1216 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1217 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1218 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1219 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1221 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1222 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1224 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1225 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1226 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1227 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1228 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1229 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1230 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1231 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1232 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1233 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1235 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1236 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1237 memcpy(pas, qp_pas, rq_pas_size);
1239 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1246 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1247 struct mlx5_ib_rq *rq)
1249 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1252 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1254 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1255 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1256 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1259 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1260 struct mlx5_ib_rq *rq, u32 tdn,
1261 bool tunnel_offload_en)
1268 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1269 in = kvzalloc(inlen, GFP_KERNEL);
1273 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1274 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1275 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1276 MLX5_SET(tirc, tirc, transport_domain, tdn);
1277 if (tunnel_offload_en)
1278 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1281 MLX5_SET(tirc, tirc, self_lb_block,
1282 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1284 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1291 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1292 struct mlx5_ib_rq *rq)
1294 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1297 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1298 u32 *in, size_t inlen,
1301 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1302 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1303 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1304 struct ib_uobject *uobj = pd->uobject;
1305 struct ib_ucontext *ucontext = uobj->context;
1306 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1308 u32 tdn = mucontext->tdn;
1310 if (qp->sq.wqe_cnt) {
1311 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1315 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1317 goto err_destroy_tis;
1319 sq->base.container_mibqp = qp;
1320 sq->base.mqp.event = mlx5_ib_qp_event;
1323 if (qp->rq.wqe_cnt) {
1324 rq->base.container_mibqp = qp;
1326 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1327 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1328 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1329 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1330 err = create_raw_packet_qp_rq(dev, rq, in, inlen);
1332 goto err_destroy_sq;
1335 err = create_raw_packet_qp_tir(dev, rq, tdn,
1336 qp->tunnel_offload_en);
1338 goto err_destroy_rq;
1341 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1347 destroy_raw_packet_qp_rq(dev, rq);
1349 if (!qp->sq.wqe_cnt)
1351 destroy_raw_packet_qp_sq(dev, sq);
1353 destroy_raw_packet_qp_tis(dev, sq);
1358 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1359 struct mlx5_ib_qp *qp)
1361 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1362 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1363 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1365 if (qp->rq.wqe_cnt) {
1366 destroy_raw_packet_qp_tir(dev, rq);
1367 destroy_raw_packet_qp_rq(dev, rq);
1370 if (qp->sq.wqe_cnt) {
1371 destroy_raw_packet_qp_sq(dev, sq);
1372 destroy_raw_packet_qp_tis(dev, sq);
1376 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1377 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1379 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1380 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1384 sq->doorbell = &qp->db;
1385 rq->doorbell = &qp->db;
1388 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1390 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1393 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1395 struct ib_qp_init_attr *init_attr,
1396 struct ib_udata *udata)
1398 struct ib_uobject *uobj = pd->uobject;
1399 struct ib_ucontext *ucontext = uobj->context;
1400 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1401 struct mlx5_ib_create_qp_resp resp = {};
1407 u32 selected_fields = 0;
1409 size_t min_resp_len;
1410 u32 tdn = mucontext->tdn;
1411 struct mlx5_ib_create_qp_rss ucmd = {};
1412 size_t required_cmd_sz;
1414 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1417 if (init_attr->create_flags || init_attr->send_cq)
1420 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1421 if (udata->outlen < min_resp_len)
1424 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1425 if (udata->inlen < required_cmd_sz) {
1426 mlx5_ib_dbg(dev, "invalid inlen\n");
1430 if (udata->inlen > sizeof(ucmd) &&
1431 !ib_is_udata_cleared(udata, sizeof(ucmd),
1432 udata->inlen - sizeof(ucmd))) {
1433 mlx5_ib_dbg(dev, "inlen is not supported\n");
1437 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1438 mlx5_ib_dbg(dev, "copy failed\n");
1442 if (ucmd.comp_mask) {
1443 mlx5_ib_dbg(dev, "invalid comp mask\n");
1447 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1448 mlx5_ib_dbg(dev, "invalid flags\n");
1452 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1453 !tunnel_offload_supported(dev->mdev)) {
1454 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1458 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1459 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1460 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1464 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1466 mlx5_ib_dbg(dev, "copy failed\n");
1470 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1471 in = kvzalloc(inlen, GFP_KERNEL);
1475 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1476 MLX5_SET(tirc, tirc, disp_type,
1477 MLX5_TIRC_DISP_TYPE_INDIRECT);
1478 MLX5_SET(tirc, tirc, indirect_table,
1479 init_attr->rwq_ind_tbl->ind_tbl_num);
1480 MLX5_SET(tirc, tirc, transport_domain, tdn);
1482 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1484 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1485 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1487 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1488 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1490 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1492 switch (ucmd.rx_hash_function) {
1493 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1495 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1496 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1498 if (len != ucmd.rx_key_len) {
1503 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1504 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1505 memcpy(rss_key, ucmd.rx_hash_key, len);
1513 if (!ucmd.rx_hash_fields_mask) {
1514 /* special case when this TIR serves as steering entry without hashing */
1515 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1521 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1522 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1523 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1524 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1529 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1530 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1531 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1532 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1533 MLX5_L3_PROT_TYPE_IPV4);
1534 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1535 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1536 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1537 MLX5_L3_PROT_TYPE_IPV6);
1539 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1540 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1541 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1542 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1543 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1545 /* Check that only one l4 protocol is set */
1546 if (outer_l4 & (outer_l4 - 1)) {
1551 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1552 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1553 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1554 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1555 MLX5_L4_PROT_TYPE_TCP);
1556 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1557 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1558 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1559 MLX5_L4_PROT_TYPE_UDP);
1561 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1562 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1563 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1565 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1566 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1567 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1569 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1570 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1571 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1573 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1574 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1575 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1577 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1578 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1580 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1584 MLX5_SET(tirc, tirc, self_lb_block,
1585 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1587 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1593 /* qpn is reserved for that QP */
1594 qp->trans_qp.base.mqp.qpn = 0;
1595 qp->flags |= MLX5_IB_QP_RSS;
1603 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1604 struct ib_qp_init_attr *init_attr,
1605 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1607 struct mlx5_ib_resources *devr = &dev->devr;
1608 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1609 struct mlx5_core_dev *mdev = dev->mdev;
1610 struct mlx5_ib_create_qp_resp resp;
1611 struct mlx5_ib_cq *send_cq;
1612 struct mlx5_ib_cq *recv_cq;
1613 unsigned long flags;
1614 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1615 struct mlx5_ib_create_qp ucmd;
1616 struct mlx5_ib_qp_base *base;
1622 mutex_init(&qp->mutex);
1623 spin_lock_init(&qp->sq.lock);
1624 spin_lock_init(&qp->rq.lock);
1626 mlx5_st = to_mlx5_st(init_attr->qp_type);
1630 if (init_attr->rwq_ind_tbl) {
1634 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1638 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1639 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1640 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1643 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1647 if (init_attr->create_flags &
1648 (IB_QP_CREATE_CROSS_CHANNEL |
1649 IB_QP_CREATE_MANAGED_SEND |
1650 IB_QP_CREATE_MANAGED_RECV)) {
1651 if (!MLX5_CAP_GEN(mdev, cd)) {
1652 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1655 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1656 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1657 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1658 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1659 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1660 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1663 if (init_attr->qp_type == IB_QPT_UD &&
1664 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1665 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1666 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1670 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1671 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1672 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1675 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1676 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1677 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1680 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1683 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1684 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1686 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1687 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1688 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1689 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1691 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1694 if (pd && pd->uobject) {
1695 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1696 mlx5_ib_dbg(dev, "copy failed\n");
1700 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1701 &ucmd, udata->inlen, &uidx);
1705 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1706 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1707 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1708 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1709 !tunnel_offload_supported(mdev)) {
1710 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1713 qp->tunnel_offload_en = true;
1716 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1717 if (init_attr->qp_type != IB_QPT_UD ||
1718 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1719 MLX5_CAP_PORT_TYPE_IB) ||
1720 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1721 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1725 qp->flags |= MLX5_IB_QP_UNDERLAY;
1726 qp->underlay_qpn = init_attr->source_qpn;
1729 qp->wq_sig = !!wq_signature;
1732 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1733 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1734 &qp->raw_packet_qp.rq.base :
1737 qp->has_rq = qp_has_rq(init_attr);
1738 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1739 qp, (pd && pd->uobject) ? &ucmd : NULL);
1741 mlx5_ib_dbg(dev, "err %d\n", err);
1748 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1749 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1750 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1751 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1752 mlx5_ib_dbg(dev, "invalid rq params\n");
1755 if (ucmd.sq_wqe_count > max_wqes) {
1756 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1757 ucmd.sq_wqe_count, max_wqes);
1760 if (init_attr->create_flags &
1761 mlx5_ib_create_qp_sqpn_qp1()) {
1762 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1765 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1766 &resp, &inlen, base);
1768 mlx5_ib_dbg(dev, "err %d\n", err);
1770 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1773 mlx5_ib_dbg(dev, "err %d\n", err);
1779 in = kvzalloc(inlen, GFP_KERNEL);
1783 qp->create_type = MLX5_QP_EMPTY;
1786 if (is_sqp(init_attr->qp_type))
1787 qp->port = init_attr->port_num;
1789 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1791 MLX5_SET(qpc, qpc, st, mlx5_st);
1792 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1794 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1795 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1797 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1801 MLX5_SET(qpc, qpc, wq_signature, 1);
1803 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1804 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1806 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1807 MLX5_SET(qpc, qpc, cd_master, 1);
1808 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1809 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1810 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1811 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1813 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1817 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1818 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1821 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1823 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1825 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1827 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1829 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1833 if (qp->rq.wqe_cnt) {
1834 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1835 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1838 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1840 if (qp->sq.wqe_cnt) {
1841 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1843 MLX5_SET(qpc, qpc, no_sq, 1);
1844 if (init_attr->srq &&
1845 init_attr->srq->srq_type == IB_SRQT_TM)
1846 MLX5_SET(qpc, qpc, offload_type,
1847 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1850 /* Set default resources */
1851 switch (init_attr->qp_type) {
1852 case IB_QPT_XRC_TGT:
1853 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1854 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1855 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1856 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1858 case IB_QPT_XRC_INI:
1859 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1860 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1861 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1864 if (init_attr->srq) {
1865 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1866 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1868 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1869 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1873 if (init_attr->send_cq)
1874 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1876 if (init_attr->recv_cq)
1877 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1879 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1881 /* 0xffffff means we ask to work with cqe version 0 */
1882 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1883 MLX5_SET(qpc, qpc, user_index, uidx);
1885 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1886 if (init_attr->qp_type == IB_QPT_UD &&
1887 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1888 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1889 qp->flags |= MLX5_IB_QP_LSO;
1892 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1893 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1894 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1897 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1898 MLX5_SET(qpc, qpc, end_padding_mode,
1899 MLX5_WQ_END_PAD_MODE_ALIGN);
1901 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1910 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1911 qp->flags & MLX5_IB_QP_UNDERLAY) {
1912 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1913 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1914 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
1916 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1920 mlx5_ib_dbg(dev, "create qp failed\n");
1926 base->container_mibqp = qp;
1927 base->mqp.event = mlx5_ib_qp_event;
1929 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1930 &send_cq, &recv_cq);
1931 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1932 mlx5_ib_lock_cqs(send_cq, recv_cq);
1933 /* Maintain device to QPs access, needed for further handling via reset
1936 list_add_tail(&qp->qps_list, &dev->qp_list);
1937 /* Maintain CQ to QPs access, needed for further handling via reset flow
1940 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1942 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1943 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1944 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1949 if (qp->create_type == MLX5_QP_USER)
1950 destroy_qp_user(dev, pd, qp, base);
1951 else if (qp->create_type == MLX5_QP_KERNEL)
1952 destroy_qp_kernel(dev, qp);
1959 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1960 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1964 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1965 spin_lock(&send_cq->lock);
1966 spin_lock_nested(&recv_cq->lock,
1967 SINGLE_DEPTH_NESTING);
1968 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1969 spin_lock(&send_cq->lock);
1970 __acquire(&recv_cq->lock);
1972 spin_lock(&recv_cq->lock);
1973 spin_lock_nested(&send_cq->lock,
1974 SINGLE_DEPTH_NESTING);
1977 spin_lock(&send_cq->lock);
1978 __acquire(&recv_cq->lock);
1980 } else if (recv_cq) {
1981 spin_lock(&recv_cq->lock);
1982 __acquire(&send_cq->lock);
1984 __acquire(&send_cq->lock);
1985 __acquire(&recv_cq->lock);
1989 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1990 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1994 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1995 spin_unlock(&recv_cq->lock);
1996 spin_unlock(&send_cq->lock);
1997 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1998 __release(&recv_cq->lock);
1999 spin_unlock(&send_cq->lock);
2001 spin_unlock(&send_cq->lock);
2002 spin_unlock(&recv_cq->lock);
2005 __release(&recv_cq->lock);
2006 spin_unlock(&send_cq->lock);
2008 } else if (recv_cq) {
2009 __release(&send_cq->lock);
2010 spin_unlock(&recv_cq->lock);
2012 __release(&recv_cq->lock);
2013 __release(&send_cq->lock);
2017 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2019 return to_mpd(qp->ibqp.pd);
2022 static void get_cqs(enum ib_qp_type qp_type,
2023 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2024 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2027 case IB_QPT_XRC_TGT:
2031 case MLX5_IB_QPT_REG_UMR:
2032 case IB_QPT_XRC_INI:
2033 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2038 case MLX5_IB_QPT_HW_GSI:
2042 case IB_QPT_RAW_IPV6:
2043 case IB_QPT_RAW_ETHERTYPE:
2044 case IB_QPT_RAW_PACKET:
2045 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2046 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2057 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2058 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2059 u8 lag_tx_affinity);
2061 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2063 struct mlx5_ib_cq *send_cq, *recv_cq;
2064 struct mlx5_ib_qp_base *base;
2065 unsigned long flags;
2068 if (qp->ibqp.rwq_ind_tbl) {
2069 destroy_rss_raw_qp_tir(dev, qp);
2073 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2074 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2075 &qp->raw_packet_qp.rq.base :
2078 if (qp->state != IB_QPS_RESET) {
2079 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2080 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2081 err = mlx5_core_qp_modify(dev->mdev,
2082 MLX5_CMD_OP_2RST_QP, 0,
2085 struct mlx5_modify_raw_qp_param raw_qp_param = {
2086 .operation = MLX5_CMD_OP_2RST_QP
2089 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2092 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2096 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2097 &send_cq, &recv_cq);
2099 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2100 mlx5_ib_lock_cqs(send_cq, recv_cq);
2101 /* del from lists under both locks above to protect reset flow paths */
2102 list_del(&qp->qps_list);
2104 list_del(&qp->cq_send_list);
2107 list_del(&qp->cq_recv_list);
2109 if (qp->create_type == MLX5_QP_KERNEL) {
2110 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2111 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2112 if (send_cq != recv_cq)
2113 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2116 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2117 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2119 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2120 qp->flags & MLX5_IB_QP_UNDERLAY) {
2121 destroy_raw_packet_qp(dev, qp);
2123 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2125 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2129 if (qp->create_type == MLX5_QP_KERNEL)
2130 destroy_qp_kernel(dev, qp);
2131 else if (qp->create_type == MLX5_QP_USER)
2132 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2135 static const char *ib_qp_type_str(enum ib_qp_type type)
2139 return "IB_QPT_SMI";
2141 return "IB_QPT_GSI";
2148 case IB_QPT_RAW_IPV6:
2149 return "IB_QPT_RAW_IPV6";
2150 case IB_QPT_RAW_ETHERTYPE:
2151 return "IB_QPT_RAW_ETHERTYPE";
2152 case IB_QPT_XRC_INI:
2153 return "IB_QPT_XRC_INI";
2154 case IB_QPT_XRC_TGT:
2155 return "IB_QPT_XRC_TGT";
2156 case IB_QPT_RAW_PACKET:
2157 return "IB_QPT_RAW_PACKET";
2158 case MLX5_IB_QPT_REG_UMR:
2159 return "MLX5_IB_QPT_REG_UMR";
2161 return "IB_QPT_DRIVER";
2164 return "Invalid QP type";
2168 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2169 struct ib_qp_init_attr *attr,
2170 struct mlx5_ib_create_qp *ucmd)
2172 struct mlx5_ib_qp *qp;
2174 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2177 if (!attr->srq || !attr->recv_cq)
2178 return ERR_PTR(-EINVAL);
2180 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2181 ucmd, sizeof(*ucmd), &uidx);
2183 return ERR_PTR(err);
2185 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2187 return ERR_PTR(-ENOMEM);
2189 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2195 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2196 qp->qp_sub_type = MLX5_IB_QPT_DCT;
2197 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2198 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2199 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2200 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2201 MLX5_SET(dctc, dctc, user_index, uidx);
2203 qp->state = IB_QPS_RESET;
2208 return ERR_PTR(err);
2211 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2212 struct ib_qp_init_attr *init_attr,
2213 struct mlx5_ib_create_qp *ucmd,
2214 struct ib_udata *udata)
2216 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2222 if (udata->inlen < sizeof(*ucmd)) {
2223 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2226 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2230 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2231 init_attr->qp_type = MLX5_IB_QPT_DCI;
2233 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2234 init_attr->qp_type = MLX5_IB_QPT_DCT;
2236 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2241 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2242 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2249 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2250 struct ib_qp_init_attr *verbs_init_attr,
2251 struct ib_udata *udata)
2253 struct mlx5_ib_dev *dev;
2254 struct mlx5_ib_qp *qp;
2257 struct ib_qp_init_attr mlx_init_attr;
2258 struct ib_qp_init_attr *init_attr = verbs_init_attr;
2261 dev = to_mdev(pd->device);
2263 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2265 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2266 return ERR_PTR(-EINVAL);
2267 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2268 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2269 return ERR_PTR(-EINVAL);
2273 /* being cautious here */
2274 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2275 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2276 pr_warn("%s: no PD for transport %s\n", __func__,
2277 ib_qp_type_str(init_attr->qp_type));
2278 return ERR_PTR(-EINVAL);
2280 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2283 if (init_attr->qp_type == IB_QPT_DRIVER) {
2284 struct mlx5_ib_create_qp ucmd;
2286 init_attr = &mlx_init_attr;
2287 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2288 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2290 return ERR_PTR(err);
2292 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2293 if (init_attr->cap.max_recv_wr ||
2294 init_attr->cap.max_recv_sge) {
2295 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2296 return ERR_PTR(-EINVAL);
2299 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2303 switch (init_attr->qp_type) {
2304 case IB_QPT_XRC_TGT:
2305 case IB_QPT_XRC_INI:
2306 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2307 mlx5_ib_dbg(dev, "XRC not supported\n");
2308 return ERR_PTR(-ENOSYS);
2310 init_attr->recv_cq = NULL;
2311 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2312 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2313 init_attr->send_cq = NULL;
2317 case IB_QPT_RAW_PACKET:
2322 case MLX5_IB_QPT_HW_GSI:
2323 case MLX5_IB_QPT_REG_UMR:
2324 case MLX5_IB_QPT_DCI:
2325 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2327 return ERR_PTR(-ENOMEM);
2329 err = create_qp_common(dev, pd, init_attr, udata, qp);
2331 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2333 return ERR_PTR(err);
2336 if (is_qp0(init_attr->qp_type))
2337 qp->ibqp.qp_num = 0;
2338 else if (is_qp1(init_attr->qp_type))
2339 qp->ibqp.qp_num = 1;
2341 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2343 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2344 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2345 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2346 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2348 qp->trans_qp.xrcdn = xrcdn;
2353 return mlx5_ib_gsi_create_qp(pd, init_attr);
2355 case IB_QPT_RAW_IPV6:
2356 case IB_QPT_RAW_ETHERTYPE:
2359 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2360 init_attr->qp_type);
2361 /* Don't support raw QPs */
2362 return ERR_PTR(-EINVAL);
2365 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2366 qp->qp_sub_type = init_attr->qp_type;
2371 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2373 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2375 if (mqp->state == IB_QPS_RTR) {
2378 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2380 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2390 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2392 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2393 struct mlx5_ib_qp *mqp = to_mqp(qp);
2395 if (unlikely(qp->qp_type == IB_QPT_GSI))
2396 return mlx5_ib_gsi_destroy_qp(qp);
2398 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2399 return mlx5_ib_destroy_dct(mqp);
2401 destroy_qp_common(dev, mqp);
2408 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2411 u32 hw_access_flags = 0;
2415 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2416 dest_rd_atomic = attr->max_dest_rd_atomic;
2418 dest_rd_atomic = qp->trans_qp.resp_depth;
2420 if (attr_mask & IB_QP_ACCESS_FLAGS)
2421 access_flags = attr->qp_access_flags;
2423 access_flags = qp->trans_qp.atomic_rd_en;
2425 if (!dest_rd_atomic)
2426 access_flags &= IB_ACCESS_REMOTE_WRITE;
2428 if (access_flags & IB_ACCESS_REMOTE_READ)
2429 hw_access_flags |= MLX5_QP_BIT_RRE;
2430 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2431 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2432 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2433 hw_access_flags |= MLX5_QP_BIT_RWE;
2435 return cpu_to_be32(hw_access_flags);
2439 MLX5_PATH_FLAG_FL = 1 << 0,
2440 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2441 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2444 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2446 if (rate == IB_RATE_PORT_CURRENT)
2449 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2452 while (rate != IB_RATE_PORT_CURRENT &&
2453 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2454 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2457 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2460 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2461 struct mlx5_ib_sq *sq, u8 sl)
2468 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2469 in = kvzalloc(inlen, GFP_KERNEL);
2473 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2475 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2476 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2478 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2485 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2486 struct mlx5_ib_sq *sq, u8 tx_affinity)
2493 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2494 in = kvzalloc(inlen, GFP_KERNEL);
2498 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2500 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2501 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2503 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2510 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2511 const struct rdma_ah_attr *ah,
2512 struct mlx5_qp_path *path, u8 port, int attr_mask,
2513 u32 path_flags, const struct ib_qp_attr *attr,
2516 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2518 enum ib_gid_type gid_type;
2519 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2520 u8 sl = rdma_ah_get_sl(ah);
2522 if (attr_mask & IB_QP_PKEY_INDEX)
2523 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2526 if (ah_flags & IB_AH_GRH) {
2527 if (grh->sgid_index >=
2528 dev->mdev->port_caps[port - 1].gid_table_len) {
2529 pr_err("sgid_index (%u) too large. max is %d\n",
2531 dev->mdev->port_caps[port - 1].gid_table_len);
2536 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2537 if (!(ah_flags & IB_AH_GRH))
2540 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2541 if (qp->ibqp.qp_type == IB_QPT_RC ||
2542 qp->ibqp.qp_type == IB_QPT_UC ||
2543 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2544 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2546 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2547 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2548 gid_type = ah->grh.sgid_attr->gid_type;
2549 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2550 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2552 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2554 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2555 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2556 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2557 if (ah_flags & IB_AH_GRH)
2558 path->grh_mlid |= 1 << 7;
2559 path->dci_cfi_prio_sl = sl & 0xf;
2562 if (ah_flags & IB_AH_GRH) {
2563 path->mgid_index = grh->sgid_index;
2564 path->hop_limit = grh->hop_limit;
2565 path->tclass_flowlabel =
2566 cpu_to_be32((grh->traffic_class << 20) |
2568 memcpy(path->rgid, grh->dgid.raw, 16);
2571 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2574 path->static_rate = err;
2577 if (attr_mask & IB_QP_TIMEOUT)
2578 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2580 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2581 return modify_raw_packet_eth_prio(dev->mdev,
2582 &qp->raw_packet_qp.sq,
2588 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2589 [MLX5_QP_STATE_INIT] = {
2590 [MLX5_QP_STATE_INIT] = {
2591 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2592 MLX5_QP_OPTPAR_RAE |
2593 MLX5_QP_OPTPAR_RWE |
2594 MLX5_QP_OPTPAR_PKEY_INDEX |
2595 MLX5_QP_OPTPAR_PRI_PORT,
2596 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2597 MLX5_QP_OPTPAR_PKEY_INDEX |
2598 MLX5_QP_OPTPAR_PRI_PORT,
2599 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2600 MLX5_QP_OPTPAR_Q_KEY |
2601 MLX5_QP_OPTPAR_PRI_PORT,
2603 [MLX5_QP_STATE_RTR] = {
2604 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2605 MLX5_QP_OPTPAR_RRE |
2606 MLX5_QP_OPTPAR_RAE |
2607 MLX5_QP_OPTPAR_RWE |
2608 MLX5_QP_OPTPAR_PKEY_INDEX,
2609 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2610 MLX5_QP_OPTPAR_RWE |
2611 MLX5_QP_OPTPAR_PKEY_INDEX,
2612 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2613 MLX5_QP_OPTPAR_Q_KEY,
2614 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2615 MLX5_QP_OPTPAR_Q_KEY,
2616 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2617 MLX5_QP_OPTPAR_RRE |
2618 MLX5_QP_OPTPAR_RAE |
2619 MLX5_QP_OPTPAR_RWE |
2620 MLX5_QP_OPTPAR_PKEY_INDEX,
2623 [MLX5_QP_STATE_RTR] = {
2624 [MLX5_QP_STATE_RTS] = {
2625 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2626 MLX5_QP_OPTPAR_RRE |
2627 MLX5_QP_OPTPAR_RAE |
2628 MLX5_QP_OPTPAR_RWE |
2629 MLX5_QP_OPTPAR_PM_STATE |
2630 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2631 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2632 MLX5_QP_OPTPAR_RWE |
2633 MLX5_QP_OPTPAR_PM_STATE,
2634 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2637 [MLX5_QP_STATE_RTS] = {
2638 [MLX5_QP_STATE_RTS] = {
2639 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2640 MLX5_QP_OPTPAR_RAE |
2641 MLX5_QP_OPTPAR_RWE |
2642 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2643 MLX5_QP_OPTPAR_PM_STATE |
2644 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2645 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2646 MLX5_QP_OPTPAR_PM_STATE |
2647 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2648 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2649 MLX5_QP_OPTPAR_SRQN |
2650 MLX5_QP_OPTPAR_CQN_RCV,
2653 [MLX5_QP_STATE_SQER] = {
2654 [MLX5_QP_STATE_RTS] = {
2655 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2656 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2657 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2658 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2659 MLX5_QP_OPTPAR_RWE |
2660 MLX5_QP_OPTPAR_RAE |
2666 static int ib_nr_to_mlx5_nr(int ib_mask)
2671 case IB_QP_CUR_STATE:
2673 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2675 case IB_QP_ACCESS_FLAGS:
2676 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2678 case IB_QP_PKEY_INDEX:
2679 return MLX5_QP_OPTPAR_PKEY_INDEX;
2681 return MLX5_QP_OPTPAR_PRI_PORT;
2683 return MLX5_QP_OPTPAR_Q_KEY;
2685 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2686 MLX5_QP_OPTPAR_PRI_PORT;
2687 case IB_QP_PATH_MTU:
2690 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2691 case IB_QP_RETRY_CNT:
2692 return MLX5_QP_OPTPAR_RETRY_COUNT;
2693 case IB_QP_RNR_RETRY:
2694 return MLX5_QP_OPTPAR_RNR_RETRY;
2697 case IB_QP_MAX_QP_RD_ATOMIC:
2698 return MLX5_QP_OPTPAR_SRA_MAX;
2699 case IB_QP_ALT_PATH:
2700 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2701 case IB_QP_MIN_RNR_TIMER:
2702 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2705 case IB_QP_MAX_DEST_RD_ATOMIC:
2706 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2707 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2708 case IB_QP_PATH_MIG_STATE:
2709 return MLX5_QP_OPTPAR_PM_STATE;
2712 case IB_QP_DEST_QPN:
2718 static int ib_mask_to_mlx5_opt(int ib_mask)
2723 for (i = 0; i < 8 * sizeof(int); i++) {
2724 if ((1 << i) & ib_mask)
2725 result |= ib_nr_to_mlx5_nr(1 << i);
2731 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2732 struct mlx5_ib_rq *rq, int new_state,
2733 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2740 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2741 in = kvzalloc(inlen, GFP_KERNEL);
2745 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2747 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2748 MLX5_SET(rqc, rqc, state, new_state);
2750 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2751 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2752 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2753 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2754 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2756 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2760 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2764 rq->state = new_state;
2771 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2772 struct mlx5_ib_sq *sq,
2774 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2776 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2777 struct mlx5_rate_limit old_rl = ibqp->rl;
2778 struct mlx5_rate_limit new_rl = old_rl;
2779 bool new_rate_added = false;
2786 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2787 in = kvzalloc(inlen, GFP_KERNEL);
2791 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2793 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2794 MLX5_SET(sqc, sqc, state, new_state);
2796 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2797 if (new_state != MLX5_SQC_STATE_RDY)
2798 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2801 new_rl = raw_qp_param->rl;
2804 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2806 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
2808 pr_err("Failed configuring rate limit(err %d): \
2809 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2810 err, new_rl.rate, new_rl.max_burst_sz,
2811 new_rl.typical_pkt_sz);
2815 new_rate_added = true;
2818 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2819 /* index 0 means no limit */
2820 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2823 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2825 /* Remove new rate from table if failed */
2827 mlx5_rl_remove_rate(dev, &new_rl);
2831 /* Only remove the old rate after new rate was set */
2833 !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
2834 (new_state != MLX5_SQC_STATE_RDY))
2835 mlx5_rl_remove_rate(dev, &old_rl);
2838 sq->state = new_state;
2845 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2846 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2849 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2850 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2851 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2852 int modify_rq = !!qp->rq.wqe_cnt;
2853 int modify_sq = !!qp->sq.wqe_cnt;
2858 switch (raw_qp_param->operation) {
2859 case MLX5_CMD_OP_RST2INIT_QP:
2860 rq_state = MLX5_RQC_STATE_RDY;
2861 sq_state = MLX5_SQC_STATE_RDY;
2863 case MLX5_CMD_OP_2ERR_QP:
2864 rq_state = MLX5_RQC_STATE_ERR;
2865 sq_state = MLX5_SQC_STATE_ERR;
2867 case MLX5_CMD_OP_2RST_QP:
2868 rq_state = MLX5_RQC_STATE_RST;
2869 sq_state = MLX5_SQC_STATE_RST;
2871 case MLX5_CMD_OP_RTR2RTS_QP:
2872 case MLX5_CMD_OP_RTS2RTS_QP:
2873 if (raw_qp_param->set_mask ==
2874 MLX5_RAW_QP_RATE_LIMIT) {
2876 sq_state = sq->state;
2878 return raw_qp_param->set_mask ? -EINVAL : 0;
2881 case MLX5_CMD_OP_INIT2INIT_QP:
2882 case MLX5_CMD_OP_INIT2RTR_QP:
2883 if (raw_qp_param->set_mask)
2893 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2900 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2906 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2912 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2913 const struct ib_qp_attr *attr, int attr_mask,
2914 enum ib_qp_state cur_state, enum ib_qp_state new_state,
2915 const struct mlx5_ib_modify_qp *ucmd)
2917 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2918 [MLX5_QP_STATE_RST] = {
2919 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2920 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2921 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2923 [MLX5_QP_STATE_INIT] = {
2924 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2925 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2926 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2927 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2929 [MLX5_QP_STATE_RTR] = {
2930 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2931 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2932 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2934 [MLX5_QP_STATE_RTS] = {
2935 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2936 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2937 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2939 [MLX5_QP_STATE_SQD] = {
2940 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2941 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2943 [MLX5_QP_STATE_SQER] = {
2944 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2945 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2946 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2948 [MLX5_QP_STATE_ERR] = {
2949 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2950 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2954 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2955 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2956 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2957 struct mlx5_ib_cq *send_cq, *recv_cq;
2958 struct mlx5_qp_context *context;
2959 struct mlx5_ib_pd *pd;
2960 struct mlx5_ib_port *mibport = NULL;
2961 enum mlx5_qp_state mlx5_cur, mlx5_new;
2962 enum mlx5_qp_optpar optpar;
2968 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
2969 qp->qp_sub_type : ibqp->qp_type);
2973 context = kzalloc(sizeof(*context), GFP_KERNEL);
2977 context->flags = cpu_to_be32(mlx5_st << 16);
2979 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2980 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2982 switch (attr->path_mig_state) {
2983 case IB_MIG_MIGRATED:
2984 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2987 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2990 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2995 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2996 if ((ibqp->qp_type == IB_QPT_RC) ||
2997 (ibqp->qp_type == IB_QPT_UD &&
2998 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2999 (ibqp->qp_type == IB_QPT_UC) ||
3000 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3001 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3002 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3003 if (mlx5_lag_is_active(dev->mdev)) {
3004 u8 p = mlx5_core_native_port_num(dev->mdev);
3005 tx_affinity = (unsigned int)atomic_add_return(1,
3006 &dev->roce[p].next_port) %
3008 context->flags |= cpu_to_be32(tx_affinity << 24);
3013 if (is_sqp(ibqp->qp_type)) {
3014 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3015 } else if ((ibqp->qp_type == IB_QPT_UD &&
3016 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3017 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3018 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3019 } else if (attr_mask & IB_QP_PATH_MTU) {
3020 if (attr->path_mtu < IB_MTU_256 ||
3021 attr->path_mtu > IB_MTU_4096) {
3022 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3026 context->mtu_msgmax = (attr->path_mtu << 5) |
3027 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3030 if (attr_mask & IB_QP_DEST_QPN)
3031 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3033 if (attr_mask & IB_QP_PKEY_INDEX)
3034 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3036 /* todo implement counter_index functionality */
3038 if (is_sqp(ibqp->qp_type))
3039 context->pri_path.port = qp->port;
3041 if (attr_mask & IB_QP_PORT)
3042 context->pri_path.port = attr->port_num;
3044 if (attr_mask & IB_QP_AV) {
3045 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3046 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3047 attr_mask, 0, attr, false);
3052 if (attr_mask & IB_QP_TIMEOUT)
3053 context->pri_path.ackto_lt |= attr->timeout << 3;
3055 if (attr_mask & IB_QP_ALT_PATH) {
3056 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3059 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3066 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3067 &send_cq, &recv_cq);
3069 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3070 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3071 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3072 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3074 if (attr_mask & IB_QP_RNR_RETRY)
3075 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3077 if (attr_mask & IB_QP_RETRY_CNT)
3078 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3080 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3081 if (attr->max_rd_atomic)
3083 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3086 if (attr_mask & IB_QP_SQ_PSN)
3087 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3089 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3090 if (attr->max_dest_rd_atomic)
3092 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3095 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3096 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3098 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3099 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3101 if (attr_mask & IB_QP_RQ_PSN)
3102 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3104 if (attr_mask & IB_QP_QKEY)
3105 context->qkey = cpu_to_be32(attr->qkey);
3107 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3108 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3110 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3111 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3114 /* Underlay port should be used - index 0 function per port */
3115 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3118 mibport = &dev->port[port_num];
3119 context->qp_counter_set_usr_page |=
3120 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3123 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3124 context->sq_crq_size |= cpu_to_be16(1 << 4);
3126 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3127 context->deth_sqpn = cpu_to_be32(1);
3129 mlx5_cur = to_mlx5_state(cur_state);
3130 mlx5_new = to_mlx5_state(new_state);
3132 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3133 !optab[mlx5_cur][mlx5_new]) {
3138 op = optab[mlx5_cur][mlx5_new];
3139 optpar = ib_mask_to_mlx5_opt(attr_mask);
3140 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3142 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3143 qp->flags & MLX5_IB_QP_UNDERLAY) {
3144 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3146 raw_qp_param.operation = op;
3147 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3148 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3149 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3152 if (attr_mask & IB_QP_RATE_LIMIT) {
3153 raw_qp_param.rl.rate = attr->rate_limit;
3155 if (ucmd->burst_info.max_burst_sz) {
3156 if (attr->rate_limit &&
3157 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3158 raw_qp_param.rl.max_burst_sz =
3159 ucmd->burst_info.max_burst_sz;
3166 if (ucmd->burst_info.typical_pkt_sz) {
3167 if (attr->rate_limit &&
3168 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3169 raw_qp_param.rl.typical_pkt_sz =
3170 ucmd->burst_info.typical_pkt_sz;
3177 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3180 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3182 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3189 qp->state = new_state;
3191 if (attr_mask & IB_QP_ACCESS_FLAGS)
3192 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3193 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3194 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3195 if (attr_mask & IB_QP_PORT)
3196 qp->port = attr->port_num;
3197 if (attr_mask & IB_QP_ALT_PATH)
3198 qp->trans_qp.alt_port = attr->alt_port_num;
3201 * If we moved a kernel QP to RESET, clean up all old CQ
3202 * entries and reinitialize the QP.
3204 if (new_state == IB_QPS_RESET &&
3205 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3206 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3207 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3208 if (send_cq != recv_cq)
3209 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3215 qp->sq.cur_post = 0;
3216 qp->sq.last_poll = 0;
3217 qp->db.db[MLX5_RCV_DBR] = 0;
3218 qp->db.db[MLX5_SND_DBR] = 0;
3226 static inline bool is_valid_mask(int mask, int req, int opt)
3228 if ((mask & req) != req)
3231 if (mask & ~(req | opt))
3237 /* check valid transition for driver QP types
3238 * for now the only QP type that this function supports is DCI
3240 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3241 enum ib_qp_attr_mask attr_mask)
3243 int req = IB_QP_STATE;
3246 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3247 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3248 return is_valid_mask(attr_mask, req, opt);
3249 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3250 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3251 return is_valid_mask(attr_mask, req, opt);
3252 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3253 req |= IB_QP_PATH_MTU;
3254 opt = IB_QP_PKEY_INDEX;
3255 return is_valid_mask(attr_mask, req, opt);
3256 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3257 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3258 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3259 opt = IB_QP_MIN_RNR_TIMER;
3260 return is_valid_mask(attr_mask, req, opt);
3261 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3262 opt = IB_QP_MIN_RNR_TIMER;
3263 return is_valid_mask(attr_mask, req, opt);
3264 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3265 return is_valid_mask(attr_mask, req, opt);
3270 /* mlx5_ib_modify_dct: modify a DCT QP
3271 * valid transitions are:
3272 * RESET to INIT: must set access_flags, pkey_index and port
3273 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3274 * mtu, gid_index and hop_limit
3275 * Other transitions and attributes are illegal
3277 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3278 int attr_mask, struct ib_udata *udata)
3280 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3281 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3282 enum ib_qp_state cur_state, new_state;
3284 int required = IB_QP_STATE;
3287 if (!(attr_mask & IB_QP_STATE))
3290 cur_state = qp->state;
3291 new_state = attr->qp_state;
3293 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3294 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3295 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3296 if (!is_valid_mask(attr_mask, required, 0))
3299 if (attr->port_num == 0 ||
3300 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3301 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3302 attr->port_num, dev->num_ports);
3305 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3306 MLX5_SET(dctc, dctc, rre, 1);
3307 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3308 MLX5_SET(dctc, dctc, rwe, 1);
3309 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3310 if (!mlx5_ib_dc_atomic_is_supported(dev))
3312 MLX5_SET(dctc, dctc, rae, 1);
3313 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3315 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3316 MLX5_SET(dctc, dctc, port, attr->port_num);
3317 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3319 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3320 struct mlx5_ib_modify_qp_resp resp = {};
3321 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3324 if (udata->outlen < min_resp_len)
3326 resp.response_length = min_resp_len;
3328 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3329 if (!is_valid_mask(attr_mask, required, 0))
3331 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3332 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3333 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3334 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3335 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3336 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3338 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3339 MLX5_ST_SZ_BYTES(create_dct_in));
3342 resp.dctn = qp->dct.mdct.mqp.qpn;
3343 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3345 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3349 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3353 qp->state = IB_QPS_ERR;
3355 qp->state = new_state;
3359 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3360 int attr_mask, struct ib_udata *udata)
3362 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3363 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3364 struct mlx5_ib_modify_qp ucmd = {};
3365 enum ib_qp_type qp_type;
3366 enum ib_qp_state cur_state, new_state;
3367 size_t required_cmd_sz;
3370 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
3372 if (ibqp->rwq_ind_tbl)
3375 if (udata && udata->inlen) {
3376 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3377 sizeof(ucmd.reserved);
3378 if (udata->inlen < required_cmd_sz)
3381 if (udata->inlen > sizeof(ucmd) &&
3382 !ib_is_udata_cleared(udata, sizeof(ucmd),
3383 udata->inlen - sizeof(ucmd)))
3386 if (ib_copy_from_udata(&ucmd, udata,
3387 min(udata->inlen, sizeof(ucmd))))
3390 if (ucmd.comp_mask ||
3391 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3392 memchr_inv(&ucmd.burst_info.reserved, 0,
3393 sizeof(ucmd.burst_info.reserved)))
3397 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3398 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3400 if (ibqp->qp_type == IB_QPT_DRIVER)
3401 qp_type = qp->qp_sub_type;
3403 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3404 IB_QPT_GSI : ibqp->qp_type;
3406 if (qp_type == MLX5_IB_QPT_DCT)
3407 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3409 mutex_lock(&qp->mutex);
3411 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3412 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3414 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3415 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3416 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3419 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3420 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3421 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3425 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3426 qp_type != MLX5_IB_QPT_DCI &&
3427 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
3428 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3429 cur_state, new_state, ibqp->qp_type, attr_mask);
3431 } else if (qp_type == MLX5_IB_QPT_DCI &&
3432 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3433 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3434 cur_state, new_state, qp_type, attr_mask);
3438 if ((attr_mask & IB_QP_PORT) &&
3439 (attr->port_num == 0 ||
3440 attr->port_num > dev->num_ports)) {
3441 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3442 attr->port_num, dev->num_ports);
3446 if (attr_mask & IB_QP_PKEY_INDEX) {
3447 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3448 if (attr->pkey_index >=
3449 dev->mdev->port_caps[port - 1].pkey_table_len) {
3450 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3456 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3457 attr->max_rd_atomic >
3458 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3459 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3460 attr->max_rd_atomic);
3464 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3465 attr->max_dest_rd_atomic >
3466 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3467 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3468 attr->max_dest_rd_atomic);
3472 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3477 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3481 mutex_unlock(&qp->mutex);
3485 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3487 struct mlx5_ib_cq *cq;
3490 cur = wq->head - wq->tail;
3491 if (likely(cur + nreq < wq->max_post))
3495 spin_lock(&cq->lock);
3496 cur = wq->head - wq->tail;
3497 spin_unlock(&cq->lock);
3499 return cur + nreq >= wq->max_post;
3502 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3503 u64 remote_addr, u32 rkey)
3505 rseg->raddr = cpu_to_be64(remote_addr);
3506 rseg->rkey = cpu_to_be32(rkey);
3510 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3511 struct ib_send_wr *wr, void *qend,
3512 struct mlx5_ib_qp *qp, int *size)
3516 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3518 if (wr->send_flags & IB_SEND_IP_CSUM)
3519 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3520 MLX5_ETH_WQE_L4_CSUM;
3522 seg += sizeof(struct mlx5_wqe_eth_seg);
3523 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3525 if (wr->opcode == IB_WR_LSO) {
3526 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3527 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3528 u64 left, leftlen, copysz;
3529 void *pdata = ud_wr->header;
3532 eseg->mss = cpu_to_be16(ud_wr->mss);
3533 eseg->inline_hdr.sz = cpu_to_be16(left);
3536 * check if there is space till the end of queue, if yes,
3537 * copy all in one shot, otherwise copy till the end of queue,
3538 * rollback and than the copy the left
3540 leftlen = qend - (void *)eseg->inline_hdr.start;
3541 copysz = min_t(u64, leftlen, left);
3543 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3545 if (likely(copysz > size_of_inl_hdr_start)) {
3546 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3547 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3550 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3551 seg = mlx5_get_send_wqe(qp, 0);
3554 memcpy(seg, pdata, left);
3555 seg += ALIGN(left, 16);
3556 *size += ALIGN(left, 16) / 16;
3563 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3564 struct ib_send_wr *wr)
3566 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3567 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3568 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3571 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3573 dseg->byte_count = cpu_to_be32(sg->length);
3574 dseg->lkey = cpu_to_be32(sg->lkey);
3575 dseg->addr = cpu_to_be64(sg->addr);
3578 static u64 get_xlt_octo(u64 bytes)
3580 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3581 MLX5_IB_UMR_OCTOWORD;
3584 static __be64 frwr_mkey_mask(void)
3588 result = MLX5_MKEY_MASK_LEN |
3589 MLX5_MKEY_MASK_PAGE_SIZE |
3590 MLX5_MKEY_MASK_START_ADDR |
3591 MLX5_MKEY_MASK_EN_RINVAL |
3592 MLX5_MKEY_MASK_KEY |
3598 MLX5_MKEY_MASK_SMALL_FENCE |
3599 MLX5_MKEY_MASK_FREE;
3601 return cpu_to_be64(result);
3604 static __be64 sig_mkey_mask(void)
3608 result = MLX5_MKEY_MASK_LEN |
3609 MLX5_MKEY_MASK_PAGE_SIZE |
3610 MLX5_MKEY_MASK_START_ADDR |
3611 MLX5_MKEY_MASK_EN_SIGERR |
3612 MLX5_MKEY_MASK_EN_RINVAL |
3613 MLX5_MKEY_MASK_KEY |
3618 MLX5_MKEY_MASK_SMALL_FENCE |
3619 MLX5_MKEY_MASK_FREE |
3620 MLX5_MKEY_MASK_BSF_EN;
3622 return cpu_to_be64(result);
3625 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3626 struct mlx5_ib_mr *mr, bool umr_inline)
3628 int size = mr->ndescs * mr->desc_size;
3630 memset(umr, 0, sizeof(*umr));
3632 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3634 umr->flags |= MLX5_UMR_INLINE;
3635 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3636 umr->mkey_mask = frwr_mkey_mask();
3639 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3641 memset(umr, 0, sizeof(*umr));
3642 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3643 umr->flags = MLX5_UMR_INLINE;
3646 static __be64 get_umr_enable_mr_mask(void)
3650 result = MLX5_MKEY_MASK_KEY |
3651 MLX5_MKEY_MASK_FREE;
3653 return cpu_to_be64(result);
3656 static __be64 get_umr_disable_mr_mask(void)
3660 result = MLX5_MKEY_MASK_FREE;
3662 return cpu_to_be64(result);
3665 static __be64 get_umr_update_translation_mask(void)
3669 result = MLX5_MKEY_MASK_LEN |
3670 MLX5_MKEY_MASK_PAGE_SIZE |
3671 MLX5_MKEY_MASK_START_ADDR;
3673 return cpu_to_be64(result);
3676 static __be64 get_umr_update_access_mask(int atomic)
3680 result = MLX5_MKEY_MASK_LR |
3686 result |= MLX5_MKEY_MASK_A;
3688 return cpu_to_be64(result);
3691 static __be64 get_umr_update_pd_mask(void)
3695 result = MLX5_MKEY_MASK_PD;
3697 return cpu_to_be64(result);
3700 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
3702 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
3703 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
3704 (mask & MLX5_MKEY_MASK_A &&
3705 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
3710 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
3711 struct mlx5_wqe_umr_ctrl_seg *umr,
3712 struct ib_send_wr *wr, int atomic)
3714 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3716 memset(umr, 0, sizeof(*umr));
3718 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3719 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3721 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3723 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3724 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3725 u64 offset = get_xlt_octo(umrwr->offset);
3727 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3728 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3729 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3731 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3732 umr->mkey_mask |= get_umr_update_translation_mask();
3733 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3734 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3735 umr->mkey_mask |= get_umr_update_pd_mask();
3737 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3738 umr->mkey_mask |= get_umr_enable_mr_mask();
3739 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3740 umr->mkey_mask |= get_umr_disable_mr_mask();
3743 umr->flags |= MLX5_UMR_INLINE;
3745 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
3748 static u8 get_umr_flags(int acc)
3750 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3751 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3752 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3753 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3754 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3757 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3758 struct mlx5_ib_mr *mr,
3759 u32 key, int access)
3761 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3763 memset(seg, 0, sizeof(*seg));
3765 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3766 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3767 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3768 /* KLMs take twice the size of MTTs */
3771 seg->flags = get_umr_flags(access) | mr->access_mode;
3772 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3773 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3774 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3775 seg->len = cpu_to_be64(mr->ibmr.length);
3776 seg->xlt_oct_size = cpu_to_be32(ndescs);
3779 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3781 memset(seg, 0, sizeof(*seg));
3782 seg->status = MLX5_MKEY_STATUS_FREE;
3785 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3787 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3789 memset(seg, 0, sizeof(*seg));
3790 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3791 seg->status = MLX5_MKEY_STATUS_FREE;
3793 seg->flags = convert_access(umrwr->access_flags);
3795 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3796 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3798 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3800 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3801 seg->len = cpu_to_be64(umrwr->length);
3802 seg->log2_page_size = umrwr->page_shift;
3803 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3804 mlx5_mkey_variant(umrwr->mkey));
3807 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3808 struct mlx5_ib_mr *mr,
3809 struct mlx5_ib_pd *pd)
3811 int bcount = mr->desc_size * mr->ndescs;
3813 dseg->addr = cpu_to_be64(mr->desc_map);
3814 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3815 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3818 static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp,
3819 struct mlx5_ib_mr *mr, int mr_list_size)
3821 void *qend = qp->sq.qend;
3822 void *addr = mr->descs;
3825 if (unlikely(seg + mr_list_size > qend)) {
3827 memcpy(seg, addr, copy);
3829 mr_list_size -= copy;
3830 seg = mlx5_get_send_wqe(qp, 0);
3832 memcpy(seg, addr, mr_list_size);
3833 seg += mr_list_size;
3836 static __be32 send_ieth(struct ib_send_wr *wr)
3838 switch (wr->opcode) {
3839 case IB_WR_SEND_WITH_IMM:
3840 case IB_WR_RDMA_WRITE_WITH_IMM:
3841 return wr->ex.imm_data;
3843 case IB_WR_SEND_WITH_INV:
3844 return cpu_to_be32(wr->ex.invalidate_rkey);
3851 static u8 calc_sig(void *wqe, int size)
3857 for (i = 0; i < size; i++)
3863 static u8 wq_sig(void *wqe)
3865 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3868 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3871 struct mlx5_wqe_inline_seg *seg;
3872 void *qend = qp->sq.qend;
3880 wqe += sizeof(*seg);
3881 for (i = 0; i < wr->num_sge; i++) {
3882 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3883 len = wr->sg_list[i].length;
3886 if (unlikely(inl > qp->max_inline_data))
3889 if (unlikely(wqe + len > qend)) {
3891 memcpy(wqe, addr, copy);
3894 wqe = mlx5_get_send_wqe(qp, 0);
3896 memcpy(wqe, addr, len);
3900 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3902 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3907 static u16 prot_field_size(enum ib_signature_type type)
3910 case IB_SIG_TYPE_T10_DIF:
3911 return MLX5_DIF_SIZE;
3917 static u8 bs_selector(int block_size)
3919 switch (block_size) {
3920 case 512: return 0x1;
3921 case 520: return 0x2;
3922 case 4096: return 0x3;
3923 case 4160: return 0x4;
3924 case 1073741824: return 0x5;
3929 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3930 struct mlx5_bsf_inl *inl)
3932 /* Valid inline section and allow BSF refresh */
3933 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3934 MLX5_BSF_REFRESH_DIF);
3935 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3936 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3937 /* repeating block */
3938 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3939 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3940 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3942 if (domain->sig.dif.ref_remap)
3943 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3945 if (domain->sig.dif.app_escape) {
3946 if (domain->sig.dif.ref_escape)
3947 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3949 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3952 inl->dif_app_bitmask_check =
3953 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3956 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3957 struct ib_sig_attrs *sig_attrs,
3958 struct mlx5_bsf *bsf, u32 data_size)
3960 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3961 struct mlx5_bsf_basic *basic = &bsf->basic;
3962 struct ib_sig_domain *mem = &sig_attrs->mem;
3963 struct ib_sig_domain *wire = &sig_attrs->wire;
3965 memset(bsf, 0, sizeof(*bsf));
3967 /* Basic + Extended + Inline */
3968 basic->bsf_size_sbs = 1 << 7;
3969 /* Input domain check byte mask */
3970 basic->check_byte_mask = sig_attrs->check_mask;
3971 basic->raw_data_size = cpu_to_be32(data_size);
3974 switch (sig_attrs->mem.sig_type) {
3975 case IB_SIG_TYPE_NONE:
3977 case IB_SIG_TYPE_T10_DIF:
3978 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3979 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3980 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3987 switch (sig_attrs->wire.sig_type) {
3988 case IB_SIG_TYPE_NONE:
3990 case IB_SIG_TYPE_T10_DIF:
3991 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3992 mem->sig_type == wire->sig_type) {
3993 /* Same block structure */
3994 basic->bsf_size_sbs |= 1 << 4;
3995 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3996 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3997 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3998 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3999 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4000 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4002 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4004 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4005 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4014 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
4015 struct mlx5_ib_qp *qp, void **seg, int *size)
4017 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4018 struct ib_mr *sig_mr = wr->sig_mr;
4019 struct mlx5_bsf *bsf;
4020 u32 data_len = wr->wr.sg_list->length;
4021 u32 data_key = wr->wr.sg_list->lkey;
4022 u64 data_va = wr->wr.sg_list->addr;
4027 (data_key == wr->prot->lkey &&
4028 data_va == wr->prot->addr &&
4029 data_len == wr->prot->length)) {
4031 * Source domain doesn't contain signature information
4032 * or data and protection are interleaved in memory.
4033 * So need construct:
4034 * ------------------
4036 * ------------------
4038 * ------------------
4040 struct mlx5_klm *data_klm = *seg;
4042 data_klm->bcount = cpu_to_be32(data_len);
4043 data_klm->key = cpu_to_be32(data_key);
4044 data_klm->va = cpu_to_be64(data_va);
4045 wqe_size = ALIGN(sizeof(*data_klm), 64);
4048 * Source domain contains signature information
4049 * So need construct a strided block format:
4050 * ---------------------------
4051 * | stride_block_ctrl |
4052 * ---------------------------
4054 * ---------------------------
4056 * ---------------------------
4058 * ---------------------------
4060 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4061 struct mlx5_stride_block_entry *data_sentry;
4062 struct mlx5_stride_block_entry *prot_sentry;
4063 u32 prot_key = wr->prot->lkey;
4064 u64 prot_va = wr->prot->addr;
4065 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4069 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4070 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4072 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4074 pr_err("Bad block size given: %u\n", block_size);
4077 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4079 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4080 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4081 sblock_ctrl->num_entries = cpu_to_be16(2);
4083 data_sentry->bcount = cpu_to_be16(block_size);
4084 data_sentry->key = cpu_to_be32(data_key);
4085 data_sentry->va = cpu_to_be64(data_va);
4086 data_sentry->stride = cpu_to_be16(block_size);
4088 prot_sentry->bcount = cpu_to_be16(prot_size);
4089 prot_sentry->key = cpu_to_be32(prot_key);
4090 prot_sentry->va = cpu_to_be64(prot_va);
4091 prot_sentry->stride = cpu_to_be16(prot_size);
4093 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4094 sizeof(*prot_sentry), 64);
4098 *size += wqe_size / 16;
4099 if (unlikely((*seg == qp->sq.qend)))
4100 *seg = mlx5_get_send_wqe(qp, 0);
4103 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4107 *seg += sizeof(*bsf);
4108 *size += sizeof(*bsf) / 16;
4109 if (unlikely((*seg == qp->sq.qend)))
4110 *seg = mlx5_get_send_wqe(qp, 0);
4115 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4116 struct ib_sig_handover_wr *wr, u32 size,
4117 u32 length, u32 pdn)
4119 struct ib_mr *sig_mr = wr->sig_mr;
4120 u32 sig_key = sig_mr->rkey;
4121 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4123 memset(seg, 0, sizeof(*seg));
4125 seg->flags = get_umr_flags(wr->access_flags) |
4126 MLX5_MKC_ACCESS_MODE_KLMS;
4127 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4128 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4129 MLX5_MKEY_BSF_EN | pdn);
4130 seg->len = cpu_to_be64(length);
4131 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4132 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4135 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4138 memset(umr, 0, sizeof(*umr));
4140 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4141 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4142 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4143 umr->mkey_mask = sig_mkey_mask();
4147 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
4148 void **seg, int *size)
4150 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4151 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4152 u32 pdn = get_pd(qp)->pdn;
4154 int region_len, ret;
4156 if (unlikely(wr->wr.num_sge != 1) ||
4157 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4158 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4159 unlikely(!sig_mr->sig->sig_status_checked))
4162 /* length of the protected region, data + protection */
4163 region_len = wr->wr.sg_list->length;
4165 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4166 wr->prot->addr != wr->wr.sg_list->addr ||
4167 wr->prot->length != wr->wr.sg_list->length))
4168 region_len += wr->prot->length;
4171 * KLM octoword size - if protection was provided
4172 * then we use strided block format (3 octowords),
4173 * else we use single KLM (1 octoword)
4175 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4177 set_sig_umr_segment(*seg, xlt_size);
4178 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4179 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4180 if (unlikely((*seg == qp->sq.qend)))
4181 *seg = mlx5_get_send_wqe(qp, 0);
4183 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4184 *seg += sizeof(struct mlx5_mkey_seg);
4185 *size += sizeof(struct mlx5_mkey_seg) / 16;
4186 if (unlikely((*seg == qp->sq.qend)))
4187 *seg = mlx5_get_send_wqe(qp, 0);
4189 ret = set_sig_data_segment(wr, qp, seg, size);
4193 sig_mr->sig->sig_status_checked = false;
4197 static int set_psv_wr(struct ib_sig_domain *domain,
4198 u32 psv_idx, void **seg, int *size)
4200 struct mlx5_seg_set_psv *psv_seg = *seg;
4202 memset(psv_seg, 0, sizeof(*psv_seg));
4203 psv_seg->psv_num = cpu_to_be32(psv_idx);
4204 switch (domain->sig_type) {
4205 case IB_SIG_TYPE_NONE:
4207 case IB_SIG_TYPE_T10_DIF:
4208 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4209 domain->sig.dif.app_tag);
4210 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4213 pr_err("Bad signature type (%d) is given.\n",
4218 *seg += sizeof(*psv_seg);
4219 *size += sizeof(*psv_seg) / 16;
4224 static int set_reg_wr(struct mlx5_ib_qp *qp,
4225 struct ib_reg_wr *wr,
4226 void **seg, int *size)
4228 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4229 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4230 int mr_list_size = mr->ndescs * mr->desc_size;
4231 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4233 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4234 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4235 "Invalid IB_SEND_INLINE send flag\n");
4239 set_reg_umr_seg(*seg, mr, umr_inline);
4240 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4241 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4242 if (unlikely((*seg == qp->sq.qend)))
4243 *seg = mlx5_get_send_wqe(qp, 0);
4245 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4246 *seg += sizeof(struct mlx5_mkey_seg);
4247 *size += sizeof(struct mlx5_mkey_seg) / 16;
4248 if (unlikely((*seg == qp->sq.qend)))
4249 *seg = mlx5_get_send_wqe(qp, 0);
4252 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size);
4253 *size += get_xlt_octo(mr_list_size);
4255 set_reg_data_seg(*seg, mr, pd);
4256 *seg += sizeof(struct mlx5_wqe_data_seg);
4257 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4262 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
4264 set_linv_umr_seg(*seg);
4265 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4266 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4267 if (unlikely((*seg == qp->sq.qend)))
4268 *seg = mlx5_get_send_wqe(qp, 0);
4269 set_linv_mkey_seg(*seg);
4270 *seg += sizeof(struct mlx5_mkey_seg);
4271 *size += sizeof(struct mlx5_mkey_seg) / 16;
4272 if (unlikely((*seg == qp->sq.qend)))
4273 *seg = mlx5_get_send_wqe(qp, 0);
4276 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4282 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4283 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4284 if ((i & 0xf) == 0) {
4285 void *buf = mlx5_get_send_wqe(qp, tidx);
4286 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4290 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4291 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4292 be32_to_cpu(p[j + 3]));
4296 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4297 struct mlx5_wqe_ctrl_seg **ctrl,
4298 struct ib_send_wr *wr, unsigned *idx,
4299 int *size, int nreq)
4301 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4304 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4305 *seg = mlx5_get_send_wqe(qp, *idx);
4307 *(uint32_t *)(*seg + 8) = 0;
4308 (*ctrl)->imm = send_ieth(wr);
4309 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4310 (wr->send_flags & IB_SEND_SIGNALED ?
4311 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4312 (wr->send_flags & IB_SEND_SOLICITED ?
4313 MLX5_WQE_CTRL_SOLICITED : 0);
4315 *seg += sizeof(**ctrl);
4316 *size = sizeof(**ctrl) / 16;
4321 static void finish_wqe(struct mlx5_ib_qp *qp,
4322 struct mlx5_wqe_ctrl_seg *ctrl,
4323 u8 size, unsigned idx, u64 wr_id,
4324 int nreq, u8 fence, u32 mlx5_opcode)
4328 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4329 mlx5_opcode | ((u32)opmod << 24));
4330 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4331 ctrl->fm_ce_se |= fence;
4332 if (unlikely(qp->wq_sig))
4333 ctrl->signature = wq_sig(ctrl);
4335 qp->sq.wrid[idx] = wr_id;
4336 qp->sq.w_list[idx].opcode = mlx5_opcode;
4337 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4338 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4339 qp->sq.w_list[idx].next = qp->sq.cur_post;
4342 static int _mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4343 struct ib_send_wr **bad_wr, bool drain)
4345 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4346 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4347 struct mlx5_core_dev *mdev = dev->mdev;
4348 struct mlx5_ib_qp *qp;
4349 struct mlx5_ib_mr *mr;
4350 struct mlx5_wqe_data_seg *dpseg;
4351 struct mlx5_wqe_xrc_seg *xrc;
4353 int uninitialized_var(size);
4355 unsigned long flags;
4365 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4366 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4372 spin_lock_irqsave(&qp->sq.lock, flags);
4374 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && !drain) {
4381 for (nreq = 0; wr; nreq++, wr = wr->next) {
4382 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4383 mlx5_ib_warn(dev, "\n");
4389 num_sge = wr->num_sge;
4390 if (unlikely(num_sge > qp->sq.max_gs)) {
4391 mlx5_ib_warn(dev, "\n");
4397 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4399 mlx5_ib_warn(dev, "\n");
4405 if (wr->opcode == IB_WR_LOCAL_INV ||
4406 wr->opcode == IB_WR_REG_MR) {
4407 fence = dev->umr_fence;
4408 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4409 } else if (wr->send_flags & IB_SEND_FENCE) {
4411 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4413 fence = MLX5_FENCE_MODE_FENCE;
4415 fence = qp->next_fence;
4418 switch (ibqp->qp_type) {
4419 case IB_QPT_XRC_INI:
4421 seg += sizeof(*xrc);
4422 size += sizeof(*xrc) / 16;
4425 switch (wr->opcode) {
4426 case IB_WR_RDMA_READ:
4427 case IB_WR_RDMA_WRITE:
4428 case IB_WR_RDMA_WRITE_WITH_IMM:
4429 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4431 seg += sizeof(struct mlx5_wqe_raddr_seg);
4432 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4435 case IB_WR_ATOMIC_CMP_AND_SWP:
4436 case IB_WR_ATOMIC_FETCH_AND_ADD:
4437 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4438 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4443 case IB_WR_LOCAL_INV:
4444 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4445 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4446 set_linv_wr(qp, &seg, &size);
4451 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4452 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4453 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4461 case IB_WR_REG_SIG_MR:
4462 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4463 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4465 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4466 err = set_sig_umr_wr(wr, qp, &seg, &size);
4468 mlx5_ib_warn(dev, "\n");
4473 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4474 fence, MLX5_OPCODE_UMR);
4476 * SET_PSV WQEs are not signaled and solicited
4479 wr->send_flags &= ~IB_SEND_SIGNALED;
4480 wr->send_flags |= IB_SEND_SOLICITED;
4481 err = begin_wqe(qp, &seg, &ctrl, wr,
4484 mlx5_ib_warn(dev, "\n");
4490 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4491 mr->sig->psv_memory.psv_idx, &seg,
4494 mlx5_ib_warn(dev, "\n");
4499 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4500 fence, MLX5_OPCODE_SET_PSV);
4501 err = begin_wqe(qp, &seg, &ctrl, wr,
4504 mlx5_ib_warn(dev, "\n");
4510 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4511 mr->sig->psv_wire.psv_idx, &seg,
4514 mlx5_ib_warn(dev, "\n");
4519 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4520 fence, MLX5_OPCODE_SET_PSV);
4521 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4531 switch (wr->opcode) {
4532 case IB_WR_RDMA_WRITE:
4533 case IB_WR_RDMA_WRITE_WITH_IMM:
4534 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4536 seg += sizeof(struct mlx5_wqe_raddr_seg);
4537 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4546 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4547 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4553 case MLX5_IB_QPT_HW_GSI:
4554 set_datagram_seg(seg, wr);
4555 seg += sizeof(struct mlx5_wqe_datagram_seg);
4556 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4557 if (unlikely((seg == qend)))
4558 seg = mlx5_get_send_wqe(qp, 0);
4561 set_datagram_seg(seg, wr);
4562 seg += sizeof(struct mlx5_wqe_datagram_seg);
4563 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4565 if (unlikely((seg == qend)))
4566 seg = mlx5_get_send_wqe(qp, 0);
4568 /* handle qp that supports ud offload */
4569 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4570 struct mlx5_wqe_eth_pad *pad;
4573 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4574 seg += sizeof(struct mlx5_wqe_eth_pad);
4575 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4577 seg = set_eth_seg(seg, wr, qend, qp, &size);
4579 if (unlikely((seg == qend)))
4580 seg = mlx5_get_send_wqe(qp, 0);
4583 case MLX5_IB_QPT_REG_UMR:
4584 if (wr->opcode != MLX5_IB_WR_UMR) {
4586 mlx5_ib_warn(dev, "bad opcode\n");
4589 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4590 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4591 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4594 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4595 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4596 if (unlikely((seg == qend)))
4597 seg = mlx5_get_send_wqe(qp, 0);
4598 set_reg_mkey_segment(seg, wr);
4599 seg += sizeof(struct mlx5_mkey_seg);
4600 size += sizeof(struct mlx5_mkey_seg) / 16;
4601 if (unlikely((seg == qend)))
4602 seg = mlx5_get_send_wqe(qp, 0);
4609 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4610 int uninitialized_var(sz);
4612 err = set_data_inl_seg(qp, wr, seg, &sz);
4613 if (unlikely(err)) {
4614 mlx5_ib_warn(dev, "\n");
4621 for (i = 0; i < num_sge; i++) {
4622 if (unlikely(dpseg == qend)) {
4623 seg = mlx5_get_send_wqe(qp, 0);
4626 if (likely(wr->sg_list[i].length)) {
4627 set_data_ptr_seg(dpseg, wr->sg_list + i);
4628 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4634 qp->next_fence = next_fence;
4635 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4636 mlx5_ib_opcode[wr->opcode]);
4639 dump_wqe(qp, idx, size);
4644 qp->sq.head += nreq;
4646 /* Make sure that descriptors are written before
4647 * updating doorbell record and ringing the doorbell
4651 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4653 /* Make sure doorbell record is visible to the HCA before
4654 * we hit doorbell */
4657 /* currently we support only regular doorbells */
4658 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4659 /* Make sure doorbells don't leak out of SQ spinlock
4660 * and reach the HCA out of order.
4663 bf->offset ^= bf->buf_size;
4666 spin_unlock_irqrestore(&qp->sq.lock, flags);
4671 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4672 struct ib_send_wr **bad_wr)
4674 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
4677 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4679 sig->signature = calc_sig(sig, size);
4682 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4683 struct ib_recv_wr **bad_wr, bool drain)
4685 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4686 struct mlx5_wqe_data_seg *scat;
4687 struct mlx5_rwqe_sig *sig;
4688 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4689 struct mlx5_core_dev *mdev = dev->mdev;
4690 unsigned long flags;
4696 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4697 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4699 spin_lock_irqsave(&qp->rq.lock, flags);
4701 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && !drain) {
4708 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4710 for (nreq = 0; wr; nreq++, wr = wr->next) {
4711 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4717 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4723 scat = get_recv_wqe(qp, ind);
4727 for (i = 0; i < wr->num_sge; i++)
4728 set_data_ptr_seg(scat + i, wr->sg_list + i);
4730 if (i < qp->rq.max_gs) {
4731 scat[i].byte_count = 0;
4732 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4737 sig = (struct mlx5_rwqe_sig *)scat;
4738 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4741 qp->rq.wrid[ind] = wr->wr_id;
4743 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4748 qp->rq.head += nreq;
4750 /* Make sure that descriptors are written before
4755 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4758 spin_unlock_irqrestore(&qp->rq.lock, flags);
4763 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4764 struct ib_recv_wr **bad_wr)
4766 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
4769 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4771 switch (mlx5_state) {
4772 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4773 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4774 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4775 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4776 case MLX5_QP_STATE_SQ_DRAINING:
4777 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4778 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4779 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4784 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4786 switch (mlx5_mig_state) {
4787 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4788 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4789 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4794 static int to_ib_qp_access_flags(int mlx5_flags)
4798 if (mlx5_flags & MLX5_QP_BIT_RRE)
4799 ib_flags |= IB_ACCESS_REMOTE_READ;
4800 if (mlx5_flags & MLX5_QP_BIT_RWE)
4801 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4802 if (mlx5_flags & MLX5_QP_BIT_RAE)
4803 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4808 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4809 struct rdma_ah_attr *ah_attr,
4810 struct mlx5_qp_path *path)
4813 memset(ah_attr, 0, sizeof(*ah_attr));
4815 if (!path->port || path->port > ibdev->num_ports)
4818 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4820 rdma_ah_set_port_num(ah_attr, path->port);
4821 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4823 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4824 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4825 rdma_ah_set_static_rate(ah_attr,
4826 path->static_rate ? path->static_rate - 5 : 0);
4827 if (path->grh_mlid & (1 << 7)) {
4828 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4830 rdma_ah_set_grh(ah_attr, NULL,
4834 (tc_fl >> 20) & 0xff);
4835 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4839 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4840 struct mlx5_ib_sq *sq,
4845 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4848 sq->state = *sq_state;
4854 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4855 struct mlx5_ib_rq *rq,
4863 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4864 out = kvzalloc(inlen, GFP_KERNEL);
4868 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4872 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4873 *rq_state = MLX5_GET(rqc, rqc, state);
4874 rq->state = *rq_state;
4881 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4882 struct mlx5_ib_qp *qp, u8 *qp_state)
4884 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4885 [MLX5_RQC_STATE_RST] = {
4886 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4887 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4888 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4889 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4891 [MLX5_RQC_STATE_RDY] = {
4892 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4893 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4894 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4895 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4897 [MLX5_RQC_STATE_ERR] = {
4898 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4899 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4900 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4901 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4903 [MLX5_RQ_STATE_NA] = {
4904 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4905 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4906 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4907 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4911 *qp_state = sqrq_trans[rq_state][sq_state];
4913 if (*qp_state == MLX5_QP_STATE_BAD) {
4914 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4915 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4916 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4920 if (*qp_state == MLX5_QP_STATE)
4921 *qp_state = qp->state;
4926 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4927 struct mlx5_ib_qp *qp,
4928 u8 *raw_packet_qp_state)
4930 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4931 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4932 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4934 u8 sq_state = MLX5_SQ_STATE_NA;
4935 u8 rq_state = MLX5_RQ_STATE_NA;
4937 if (qp->sq.wqe_cnt) {
4938 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4943 if (qp->rq.wqe_cnt) {
4944 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4949 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4950 raw_packet_qp_state);
4953 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4954 struct ib_qp_attr *qp_attr)
4956 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4957 struct mlx5_qp_context *context;
4962 outb = kzalloc(outlen, GFP_KERNEL);
4966 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4971 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4972 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4974 mlx5_state = be32_to_cpu(context->flags) >> 28;
4976 qp->state = to_ib_qp_state(mlx5_state);
4977 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4978 qp_attr->path_mig_state =
4979 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4980 qp_attr->qkey = be32_to_cpu(context->qkey);
4981 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4982 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4983 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4984 qp_attr->qp_access_flags =
4985 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4987 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4988 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4989 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4990 qp_attr->alt_pkey_index =
4991 be16_to_cpu(context->alt_path.pkey_index);
4992 qp_attr->alt_port_num =
4993 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4996 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4997 qp_attr->port_num = context->pri_path.port;
4999 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5000 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5002 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5004 qp_attr->max_dest_rd_atomic =
5005 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5006 qp_attr->min_rnr_timer =
5007 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5008 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5009 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5010 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5011 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
5018 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5019 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5020 struct ib_qp_init_attr *qp_init_attr)
5022 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5024 u32 access_flags = 0;
5025 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5028 int supported_mask = IB_QP_STATE |
5029 IB_QP_ACCESS_FLAGS |
5031 IB_QP_MIN_RNR_TIMER |
5036 if (qp_attr_mask & ~supported_mask)
5038 if (mqp->state != IB_QPS_RTR)
5041 out = kzalloc(outlen, GFP_KERNEL);
5045 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5049 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5051 if (qp_attr_mask & IB_QP_STATE)
5052 qp_attr->qp_state = IB_QPS_RTR;
5054 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5055 if (MLX5_GET(dctc, dctc, rre))
5056 access_flags |= IB_ACCESS_REMOTE_READ;
5057 if (MLX5_GET(dctc, dctc, rwe))
5058 access_flags |= IB_ACCESS_REMOTE_WRITE;
5059 if (MLX5_GET(dctc, dctc, rae))
5060 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5061 qp_attr->qp_access_flags = access_flags;
5064 if (qp_attr_mask & IB_QP_PORT)
5065 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5066 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5067 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5068 if (qp_attr_mask & IB_QP_AV) {
5069 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5070 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5071 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5072 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5074 if (qp_attr_mask & IB_QP_PATH_MTU)
5075 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5076 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5077 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5083 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5084 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5086 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5087 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5089 u8 raw_packet_qp_state;
5091 if (ibqp->rwq_ind_tbl)
5094 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5095 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5098 /* Not all of output fields are applicable, make sure to zero them */
5099 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5100 memset(qp_attr, 0, sizeof(*qp_attr));
5102 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5103 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5104 qp_attr_mask, qp_init_attr);
5106 mutex_lock(&qp->mutex);
5108 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5109 qp->flags & MLX5_IB_QP_UNDERLAY) {
5110 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5113 qp->state = raw_packet_qp_state;
5114 qp_attr->port_num = 1;
5116 err = query_qp_attr(dev, qp, qp_attr);
5121 qp_attr->qp_state = qp->state;
5122 qp_attr->cur_qp_state = qp_attr->qp_state;
5123 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5124 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5126 if (!ibqp->uobject) {
5127 qp_attr->cap.max_send_wr = qp->sq.max_post;
5128 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5129 qp_init_attr->qp_context = ibqp->qp_context;
5131 qp_attr->cap.max_send_wr = 0;
5132 qp_attr->cap.max_send_sge = 0;
5135 qp_init_attr->qp_type = ibqp->qp_type;
5136 qp_init_attr->recv_cq = ibqp->recv_cq;
5137 qp_init_attr->send_cq = ibqp->send_cq;
5138 qp_init_attr->srq = ibqp->srq;
5139 qp_attr->cap.max_inline_data = qp->max_inline_data;
5141 qp_init_attr->cap = qp_attr->cap;
5143 qp_init_attr->create_flags = 0;
5144 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5145 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5147 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5148 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5149 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5150 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5151 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5152 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5153 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5154 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5156 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5157 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5160 mutex_unlock(&qp->mutex);
5164 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5165 struct ib_ucontext *context,
5166 struct ib_udata *udata)
5168 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5169 struct mlx5_ib_xrcd *xrcd;
5172 if (!MLX5_CAP_GEN(dev->mdev, xrc))
5173 return ERR_PTR(-ENOSYS);
5175 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5177 return ERR_PTR(-ENOMEM);
5179 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
5182 return ERR_PTR(-ENOMEM);
5185 return &xrcd->ibxrcd;
5188 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5190 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5191 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5194 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
5196 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5202 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5204 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5205 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5206 struct ib_event event;
5208 if (rwq->ibwq.event_handler) {
5209 event.device = rwq->ibwq.device;
5210 event.element.wq = &rwq->ibwq;
5212 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5213 event.event = IB_EVENT_WQ_FATAL;
5216 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5220 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5224 static int set_delay_drop(struct mlx5_ib_dev *dev)
5228 mutex_lock(&dev->delay_drop.lock);
5229 if (dev->delay_drop.activate)
5232 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5236 dev->delay_drop.activate = true;
5238 mutex_unlock(&dev->delay_drop.lock);
5241 atomic_inc(&dev->delay_drop.rqs_cnt);
5245 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5246 struct ib_wq_init_attr *init_attr)
5248 struct mlx5_ib_dev *dev;
5249 int has_net_offloads;
5257 dev = to_mdev(pd->device);
5259 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5260 in = kvzalloc(inlen, GFP_KERNEL);
5264 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5265 MLX5_SET(rqc, rqc, mem_rq_type,
5266 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5267 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5268 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5269 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5270 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5271 wq = MLX5_ADDR_OF(rqc, rqc, wq);
5272 MLX5_SET(wq, wq, wq_type,
5273 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5274 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5275 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5276 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5277 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5281 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5284 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5285 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5286 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5287 MLX5_SET(wq, wq, log_wqe_stride_size,
5288 rwq->single_stride_log_num_of_bytes -
5289 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5290 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5291 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5293 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5294 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5295 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5296 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5297 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5298 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5299 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5300 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5301 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5302 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5307 MLX5_SET(rqc, rqc, vsd, 1);
5309 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5310 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5311 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5315 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5317 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5318 if (!(dev->ib_dev.attrs.raw_packet_caps &
5319 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5320 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5324 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5326 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5327 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5328 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5329 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5330 err = set_delay_drop(dev);
5332 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5334 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5336 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5344 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5345 struct ib_wq_init_attr *wq_init_attr,
5346 struct mlx5_ib_create_wq *ucmd,
5347 struct mlx5_ib_rwq *rwq)
5349 /* Sanity check RQ size before proceeding */
5350 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5353 if (!ucmd->rq_wqe_count)
5356 rwq->wqe_count = ucmd->rq_wqe_count;
5357 rwq->wqe_shift = ucmd->rq_wqe_shift;
5358 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
5359 rwq->log_rq_stride = rwq->wqe_shift;
5360 rwq->log_rq_size = ilog2(rwq->wqe_count);
5364 static int prepare_user_rq(struct ib_pd *pd,
5365 struct ib_wq_init_attr *init_attr,
5366 struct ib_udata *udata,
5367 struct mlx5_ib_rwq *rwq)
5369 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5370 struct mlx5_ib_create_wq ucmd = {};
5372 size_t required_cmd_sz;
5374 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5375 + sizeof(ucmd.single_stride_log_num_of_bytes);
5376 if (udata->inlen < required_cmd_sz) {
5377 mlx5_ib_dbg(dev, "invalid inlen\n");
5381 if (udata->inlen > sizeof(ucmd) &&
5382 !ib_is_udata_cleared(udata, sizeof(ucmd),
5383 udata->inlen - sizeof(ucmd))) {
5384 mlx5_ib_dbg(dev, "inlen is not supported\n");
5388 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5389 mlx5_ib_dbg(dev, "copy failed\n");
5393 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5394 mlx5_ib_dbg(dev, "invalid comp mask\n");
5396 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5397 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5398 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5401 if ((ucmd.single_stride_log_num_of_bytes <
5402 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5403 (ucmd.single_stride_log_num_of_bytes >
5404 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5405 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5406 ucmd.single_stride_log_num_of_bytes,
5407 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5408 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5411 if ((ucmd.single_wqe_log_num_of_strides >
5412 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5413 (ucmd.single_wqe_log_num_of_strides <
5414 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5415 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5416 ucmd.single_wqe_log_num_of_strides,
5417 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5418 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5421 rwq->single_stride_log_num_of_bytes =
5422 ucmd.single_stride_log_num_of_bytes;
5423 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5424 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5425 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5428 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5430 mlx5_ib_dbg(dev, "err %d\n", err);
5434 err = create_user_rq(dev, pd, rwq, &ucmd);
5436 mlx5_ib_dbg(dev, "err %d\n", err);
5441 rwq->user_index = ucmd.user_index;
5445 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5446 struct ib_wq_init_attr *init_attr,
5447 struct ib_udata *udata)
5449 struct mlx5_ib_dev *dev;
5450 struct mlx5_ib_rwq *rwq;
5451 struct mlx5_ib_create_wq_resp resp = {};
5452 size_t min_resp_len;
5456 return ERR_PTR(-ENOSYS);
5458 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5459 if (udata->outlen && udata->outlen < min_resp_len)
5460 return ERR_PTR(-EINVAL);
5462 dev = to_mdev(pd->device);
5463 switch (init_attr->wq_type) {
5465 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5467 return ERR_PTR(-ENOMEM);
5468 err = prepare_user_rq(pd, init_attr, udata, rwq);
5471 err = create_rq(rwq, pd, init_attr);
5476 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5477 init_attr->wq_type);
5478 return ERR_PTR(-EINVAL);
5481 rwq->ibwq.wq_num = rwq->core_qp.qpn;
5482 rwq->ibwq.state = IB_WQS_RESET;
5483 if (udata->outlen) {
5484 resp.response_length = offsetof(typeof(resp), response_length) +
5485 sizeof(resp.response_length);
5486 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5491 rwq->core_qp.event = mlx5_ib_wq_event;
5492 rwq->ibwq.event_handler = init_attr->event_handler;
5496 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5498 destroy_user_rq(dev, pd, rwq);
5501 return ERR_PTR(err);
5504 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5506 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5507 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5509 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5510 destroy_user_rq(dev, wq->pd, rwq);
5516 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5517 struct ib_rwq_ind_table_init_attr *init_attr,
5518 struct ib_udata *udata)
5520 struct mlx5_ib_dev *dev = to_mdev(device);
5521 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5522 int sz = 1 << init_attr->log_ind_tbl_size;
5523 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5524 size_t min_resp_len;
5531 if (udata->inlen > 0 &&
5532 !ib_is_udata_cleared(udata, 0,
5534 return ERR_PTR(-EOPNOTSUPP);
5536 if (init_attr->log_ind_tbl_size >
5537 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5538 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5539 init_attr->log_ind_tbl_size,
5540 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5541 return ERR_PTR(-EINVAL);
5544 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5545 if (udata->outlen && udata->outlen < min_resp_len)
5546 return ERR_PTR(-EINVAL);
5548 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5550 return ERR_PTR(-ENOMEM);
5552 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5553 in = kvzalloc(inlen, GFP_KERNEL);
5559 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5561 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5562 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5564 for (i = 0; i < sz; i++)
5565 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5567 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5573 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5574 if (udata->outlen) {
5575 resp.response_length = offsetof(typeof(resp), response_length) +
5576 sizeof(resp.response_length);
5577 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5582 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5585 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5588 return ERR_PTR(err);
5591 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5593 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5594 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5596 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5602 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5603 u32 wq_attr_mask, struct ib_udata *udata)
5605 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5606 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5607 struct mlx5_ib_modify_wq ucmd = {};
5608 size_t required_cmd_sz;
5616 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5617 if (udata->inlen < required_cmd_sz)
5620 if (udata->inlen > sizeof(ucmd) &&
5621 !ib_is_udata_cleared(udata, sizeof(ucmd),
5622 udata->inlen - sizeof(ucmd)))
5625 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5628 if (ucmd.comp_mask || ucmd.reserved)
5631 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5632 in = kvzalloc(inlen, GFP_KERNEL);
5636 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5638 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5639 wq_attr->curr_wq_state : wq->state;
5640 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5641 wq_attr->wq_state : curr_wq_state;
5642 if (curr_wq_state == IB_WQS_ERR)
5643 curr_wq_state = MLX5_RQC_STATE_ERR;
5644 if (wq_state == IB_WQS_ERR)
5645 wq_state = MLX5_RQC_STATE_ERR;
5646 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5647 MLX5_SET(rqc, rqc, state, wq_state);
5649 if (wq_attr_mask & IB_WQ_FLAGS) {
5650 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5651 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5652 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5653 mlx5_ib_dbg(dev, "VLAN offloads are not "
5658 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5659 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5660 MLX5_SET(rqc, rqc, vsd,
5661 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5664 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5665 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5671 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5672 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5673 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5674 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5675 MLX5_SET(rqc, rqc, counter_set_id,
5676 dev->port->cnts.set_id);
5678 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5682 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5684 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5691 struct mlx5_ib_drain_cqe {
5693 struct completion done;
5696 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5698 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5699 struct mlx5_ib_drain_cqe,
5702 complete(&cqe->done);
5705 /* This function returns only once the drained WR was completed */
5706 static void handle_drain_completion(struct ib_cq *cq,
5707 struct mlx5_ib_drain_cqe *sdrain,
5708 struct mlx5_ib_dev *dev)
5710 struct mlx5_core_dev *mdev = dev->mdev;
5712 if (cq->poll_ctx == IB_POLL_DIRECT) {
5713 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5714 ib_process_cq_direct(cq, -1);
5718 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5719 struct mlx5_ib_cq *mcq = to_mcq(cq);
5720 bool triggered = false;
5721 unsigned long flags;
5723 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5724 /* Make sure that the CQ handler won't run if wasn't run yet */
5725 if (!mcq->mcq.reset_notify_added)
5726 mcq->mcq.reset_notify_added = 1;
5729 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5732 /* Wait for any scheduled/running task to be ended */
5733 switch (cq->poll_ctx) {
5734 case IB_POLL_SOFTIRQ:
5735 irq_poll_disable(&cq->iop);
5736 irq_poll_enable(&cq->iop);
5738 case IB_POLL_WORKQUEUE:
5739 cancel_work_sync(&cq->work);
5746 /* Run the CQ handler - this makes sure that the drain WR will
5747 * be processed if wasn't processed yet.
5749 mcq->mcq.comp(&mcq->mcq);
5752 wait_for_completion(&sdrain->done);
5755 void mlx5_ib_drain_sq(struct ib_qp *qp)
5757 struct ib_cq *cq = qp->send_cq;
5758 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5759 struct mlx5_ib_drain_cqe sdrain;
5760 struct ib_send_wr *bad_swr;
5761 struct ib_rdma_wr swr = {
5764 { .wr_cqe = &sdrain.cqe, },
5765 .opcode = IB_WR_RDMA_WRITE,
5769 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5770 struct mlx5_core_dev *mdev = dev->mdev;
5772 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5773 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5774 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5778 sdrain.cqe.done = mlx5_ib_drain_qp_done;
5779 init_completion(&sdrain.done);
5781 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
5783 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5787 handle_drain_completion(cq, &sdrain, dev);
5790 void mlx5_ib_drain_rq(struct ib_qp *qp)
5792 struct ib_cq *cq = qp->recv_cq;
5793 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5794 struct mlx5_ib_drain_cqe rdrain;
5795 struct ib_recv_wr rwr = {}, *bad_rwr;
5797 struct mlx5_ib_dev *dev = to_mdev(qp->device);
5798 struct mlx5_core_dev *mdev = dev->mdev;
5800 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5801 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5802 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5806 rwr.wr_cqe = &rdrain.cqe;
5807 rdrain.cqe.done = mlx5_ib_drain_qp_done;
5808 init_completion(&rdrain.done);
5810 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
5812 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5816 handle_drain_completion(cq, &rdrain, dev);