drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <linux/mlx5/fs.h>
  38 #include "mlx5_ib.h"
  39 #include "ib_rep.h"
  40 #include "cmd.h"
  41
  42 /* not supported currently */
  43 static int wq_signature;
  44
  45 enum {
  46         MLX5_IB_ACK_REQ_FREQ    = 8,
  47 };
  48
  49 enum {
  50         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  51         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  52         MLX5_IB_LINK_TYPE_IB            = 0,
  53         MLX5_IB_LINK_TYPE_ETH           = 1
  54 };
  55
  56 enum {
  57         MLX5_IB_SQ_STRIDE       = 6,
  58         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  59 };
  60
  61 static const u32 mlx5_ib_opcode[] = {
  62         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  63         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  64         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  65         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  66         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  67         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  68         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  69         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  70         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  71         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  72         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  73         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  74         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  75         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  76 };
  77
  78 struct mlx5_wqe_eth_pad {
  79         u8 rsvd0[16];
  80 };
  81
  82 enum raw_qp_set_mask_map {
  83         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  84         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  85 };
  86
  87 struct mlx5_modify_raw_qp_param {
  88         u16 operation;
  89
  90         u32 set_mask; /* raw_qp_set_mask_map */
  91
  92         struct mlx5_rate_limit rl;
  93
  94         u8 rq_q_ctr_id;
  95 };
  96
  97 static void get_cqs(enum ib_qp_type qp_type,
  98                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  99                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
 100
 101 static int is_qp0(enum ib_qp_type qp_type)
 102 {
 103         return qp_type == IB_QPT_SMI;
 104 }
 105
 106 static int is_sqp(enum ib_qp_type qp_type)
 107 {
 108         return is_qp0(qp_type) || is_qp1(qp_type);
 109 }
 110
 111 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
 112 {
 113         return mlx5_buf_offset(&qp->buf, offset);
 114 }
 115
 116 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 117 {
 118         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 119 }
 120
 121 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 122 {
 123         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 124 }
 125
 126 /**
 127  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 128  *
 129  * @qp: QP to copy from.
 130  * @send: copy from the send queue when non-zero, use the receive queue
 131  *        otherwise.
 132  * @wqe_index:  index to start copying from. For send work queues, the
 133  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 134  *              For receive work queue, it is the number of work queue
 135  *              element in the queue.
 136  * @buffer: destination buffer.
 137  * @length: maximum number of bytes to copy.
 138  *
 139  * Copies at least a single WQE, but may copy more data.
 140  *
 141  * Return: the number of bytes copied, or an error code.
 142  */
 143 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 144                           void *buffer, u32 length,
 145                           struct mlx5_ib_qp_base *base)
 146 {
 147         struct ib_device *ibdev = qp->ibqp.device;
 148         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 149         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 150         size_t offset;
 151         size_t wq_end;
 152         struct ib_umem *umem = base->ubuffer.umem;
 153         u32 first_copy_length;
 154         int wqe_length;
 155         int ret;
 156
 157         if (wq->wqe_cnt == 0) {
 158                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 159                             qp->ibqp.qp_type);
 160                 return -EINVAL;
 161         }
 162
 163         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 164         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 165
 166         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 167                 return -EINVAL;
 168
 169         if (offset > umem->length ||
 170             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 171                 return -EINVAL;
 172
 173         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 174         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 175         if (ret)
 176                 return ret;
 177
 178         if (send) {
 179                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 180                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 181
 182                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 183         } else {
 184                 wqe_length = 1 << wq->wqe_shift;
 185         }
 186
 187         if (wqe_length <= first_copy_length)
 188                 return first_copy_length;
 189
 190         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 191                                 wqe_length - first_copy_length);
 192         if (ret)
 193                 return ret;
 194
 195         return wqe_length;
 196 }
 197
 198 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 199 {
 200         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 201         struct ib_event event;
 202
 203         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 204                 /* This event is only valid for trans_qps */
 205                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 206         }
 207
 208         if (ibqp->event_handler) {
 209                 event.device     = ibqp->device;
 210                 event.element.qp = ibqp;
 211                 switch (type) {
 212                 case MLX5_EVENT_TYPE_PATH_MIG:
 213                         event.event = IB_EVENT_PATH_MIG;
 214                         break;
 215                 case MLX5_EVENT_TYPE_COMM_EST:
 216                         event.event = IB_EVENT_COMM_EST;
 217                         break;
 218                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 219                         event.event = IB_EVENT_SQ_DRAINED;
 220                         break;
 221                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 222                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 223                         break;
 224                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 225                         event.event = IB_EVENT_QP_FATAL;
 226                         break;
 227                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 228                         event.event = IB_EVENT_PATH_MIG_ERR;
 229                         break;
 230                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 231                         event.event = IB_EVENT_QP_REQ_ERR;
 232                         break;
 233                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 234                         event.event = IB_EVENT_QP_ACCESS_ERR;
 235                         break;
 236                 default:
 237                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 238                         return;
 239                 }
 240
 241                 ibqp->event_handler(&event, ibqp->qp_context);
 242         }
 243 }
 244
 245 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 246                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 247 {
 248         int wqe_size;
 249         int wq_size;
 250
 251         /* Sanity check RQ size before proceeding */
 252         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 253                 return -EINVAL;
 254
 255         if (!has_rq) {
 256                 qp->rq.max_gs = 0;
 257                 qp->rq.wqe_cnt = 0;
 258                 qp->rq.wqe_shift = 0;
 259                 cap->max_recv_wr = 0;
 260                 cap->max_recv_sge = 0;
 261         } else {
 262                 if (ucmd) {
 263                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 264                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 265                                 return -EINVAL;
 266                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 267                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 268                                 return -EINVAL;
 269                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 270                         qp->rq.max_post = qp->rq.wqe_cnt;
 271                 } else {
 272                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 273                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 274                         wqe_size = roundup_pow_of_two(wqe_size);
 275                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 276                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 277                         qp->rq.wqe_cnt = wq_size / wqe_size;
 278                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 279                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 280                                             wqe_size,
 281                                             MLX5_CAP_GEN(dev->mdev,
 282                                                          max_wqe_sz_rq));
 283                                 return -EINVAL;
 284                         }
 285                         qp->rq.wqe_shift = ilog2(wqe_size);
 286                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 287                         qp->rq.max_post = qp->rq.wqe_cnt;
 288                 }
 289         }
 290
 291         return 0;
 292 }
 293
 294 static int sq_overhead(struct ib_qp_init_attr *attr)
 295 {
 296         int size = 0;
 297
 298         switch (attr->qp_type) {
 299         case IB_QPT_XRC_INI:
 300                 size += sizeof(struct mlx5_wqe_xrc_seg);
 301                 /* fall through */
 302         case IB_QPT_RC:
 303                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 304                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 305                             sizeof(struct mlx5_wqe_raddr_seg),
 306                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 307                             sizeof(struct mlx5_mkey_seg) +
 308                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 309                             MLX5_IB_UMR_OCTOWORD);
 310                 break;
 311
 312         case IB_QPT_XRC_TGT:
 313                 return 0;
 314
 315         case IB_QPT_UC:
 316                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 317                         max(sizeof(struct mlx5_wqe_raddr_seg),
 318                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 319                             sizeof(struct mlx5_mkey_seg));
 320                 break;
 321
 322         case IB_QPT_UD:
 323                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 324                         size += sizeof(struct mlx5_wqe_eth_pad) +
 325                                 sizeof(struct mlx5_wqe_eth_seg);
 326                 /* fall through */
 327         case IB_QPT_SMI:
 328         case MLX5_IB_QPT_HW_GSI:
 329                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 330                         sizeof(struct mlx5_wqe_datagram_seg);
 331                 break;
 332
 333         case MLX5_IB_QPT_REG_UMR:
 334                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 335                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 336                         sizeof(struct mlx5_mkey_seg);
 337                 break;
 338
 339         default:
 340                 return -EINVAL;
 341         }
 342
 343         return size;
 344 }
 345
 346 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 347 {
 348         int inl_size = 0;
 349         int size;
 350
 351         size = sq_overhead(attr);
 352         if (size < 0)
 353                 return size;
 354
 355         if (attr->cap.max_inline_data) {
 356                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 357                         attr->cap.max_inline_data;
 358         }
 359
 360         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 361         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 362             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 363                         return MLX5_SIG_WQE_SIZE;
 364         else
 365                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 366 }
 367
 368 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 369 {
 370         int max_sge;
 371
 372         if (attr->qp_type == IB_QPT_RC)
 373                 max_sge = (min_t(int, wqe_size, 512) -
 374                            sizeof(struct mlx5_wqe_ctrl_seg) -
 375                            sizeof(struct mlx5_wqe_raddr_seg)) /
 376                         sizeof(struct mlx5_wqe_data_seg);
 377         else if (attr->qp_type == IB_QPT_XRC_INI)
 378                 max_sge = (min_t(int, wqe_size, 512) -
 379                            sizeof(struct mlx5_wqe_ctrl_seg) -
 380                            sizeof(struct mlx5_wqe_xrc_seg) -
 381                            sizeof(struct mlx5_wqe_raddr_seg)) /
 382                         sizeof(struct mlx5_wqe_data_seg);
 383         else
 384                 max_sge = (wqe_size - sq_overhead(attr)) /
 385                         sizeof(struct mlx5_wqe_data_seg);
 386
 387         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 388                      sizeof(struct mlx5_wqe_data_seg));
 389 }
 390
 391 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 392                         struct mlx5_ib_qp *qp)
 393 {
 394         int wqe_size;
 395         int wq_size;
 396
 397         if (!attr->cap.max_send_wr)
 398                 return 0;
 399
 400         wqe_size = calc_send_wqe(attr);
 401         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 402         if (wqe_size < 0)
 403                 return wqe_size;
 404
 405         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 406                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 407                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 408                 return -EINVAL;
 409         }
 410
 411         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 412                               sizeof(struct mlx5_wqe_inline_seg);
 413         attr->cap.max_inline_data = qp->max_inline_data;
 414
 415         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 416                 qp->signature_en = true;
 417
 418         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 419         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 420         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 421                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 422                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 423                             qp->sq.wqe_cnt,
 424                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 425                 return -ENOMEM;
 426         }
 427         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 428         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 429         if (qp->sq.max_gs < attr->cap.max_send_sge)
 430                 return -ENOMEM;
 431
 432         attr->cap.max_send_sge = qp->sq.max_gs;
 433         qp->sq.max_post = wq_size / wqe_size;
 434         attr->cap.max_send_wr = qp->sq.max_post;
 435
 436         return wq_size;
 437 }
 438
 439 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 440                             struct mlx5_ib_qp *qp,
 441                             struct mlx5_ib_create_qp *ucmd,
 442                             struct mlx5_ib_qp_base *base,
 443                             struct ib_qp_init_attr *attr)
 444 {
 445         int desc_sz = 1 << qp->sq.wqe_shift;
 446
 447         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 448                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 449                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 450                 return -EINVAL;
 451         }
 452
 453         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 454                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 455                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 456                 return -EINVAL;
 457         }
 458
 459         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 460
 461         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 462                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 463                              qp->sq.wqe_cnt,
 464                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 465                 return -EINVAL;
 466         }
 467
 468         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 469             qp->flags & MLX5_IB_QP_UNDERLAY) {
 470                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 471                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 472         } else {
 473                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 474                                          (qp->sq.wqe_cnt << 6);
 475         }
 476
 477         return 0;
 478 }
 479
 480 static int qp_has_rq(struct ib_qp_init_attr *attr)
 481 {
 482         if (attr->qp_type == IB_QPT_XRC_INI ||
 483             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 484             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 485             !attr->cap.max_recv_wr)
 486                 return 0;
 487
 488         return 1;
 489 }
 490
 491 enum {
 492         /* this is the first blue flame register in the array of bfregs assigned
 493          * to a processes. Since we do not use it for blue flame but rather
 494          * regular 64 bit doorbells, we do not need a lock for maintaiing
 495          * "odd/even" order
 496          */
 497         NUM_NON_BLUE_FLAME_BFREGS = 1,
 498 };
 499
 500 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 501 {
 502         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 503 }
 504
 505 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 506                          struct mlx5_bfreg_info *bfregi)
 507 {
 508         int n;
 509
 510         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 511             NUM_NON_BLUE_FLAME_BFREGS;
 512
 513         return n >= 0 ? n : 0;
 514 }
 515
 516 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 517                            struct mlx5_bfreg_info *bfregi)
 518 {
 519         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 520 }
 521
 522 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 523                           struct mlx5_bfreg_info *bfregi)
 524 {
 525         int med;
 526
 527         med = num_med_bfreg(dev, bfregi);
 528         return ++med;
 529 }
 530
 531 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 532                                   struct mlx5_bfreg_info *bfregi)
 533 {
 534         int i;
 535
 536         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 537                 if (!bfregi->count[i]) {
 538                         bfregi->count[i]++;
 539                         return i;
 540                 }
 541         }
 542
 543         return -ENOMEM;
 544 }
 545
 546 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 547                                  struct mlx5_bfreg_info *bfregi)
 548 {
 549         int minidx = first_med_bfreg(dev, bfregi);
 550         int i;
 551
 552         if (minidx < 0)
 553                 return minidx;
 554
 555         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 556                 if (bfregi->count[i] < bfregi->count[minidx])
 557                         minidx = i;
 558                 if (!bfregi->count[minidx])
 559                         break;
 560         }
 561
 562         bfregi->count[minidx]++;
 563         return minidx;
 564 }
 565
 566 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 567                        struct mlx5_bfreg_info *bfregi)
 568 {
 569         int bfregn = -ENOMEM;
 570
 571         mutex_lock(&bfregi->lock);
 572         if (bfregi->ver >= 2) {
 573                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 574                 if (bfregn < 0)
 575                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 576         }
 577
 578         if (bfregn < 0) {
 579                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 580                 bfregn = 0;
 581                 bfregi->count[bfregn]++;
 582         }
 583         mutex_unlock(&bfregi->lock);
 584
 585         return bfregn;
 586 }
 587
 588 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 589 {
 590         mutex_lock(&bfregi->lock);
 591         bfregi->count[bfregn]--;
 592         mutex_unlock(&bfregi->lock);
 593 }
 594
 595 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 596 {
 597         switch (state) {
 598         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 599         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 600         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 601         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 602         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 603         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 604         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 605         default:                return -1;
 606         }
 607 }
 608
 609 static int to_mlx5_st(enum ib_qp_type type)
 610 {
 611         switch (type) {
 612         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 613         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 614         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 615         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 616         case IB_QPT_XRC_INI:
 617         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 618         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 619         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 620         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 621         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 622         case IB_QPT_RAW_PACKET:
 623         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 624         case IB_QPT_MAX:
 625         default:                return -EINVAL;
 626         }
 627 }
 628
 629 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 630                              struct mlx5_ib_cq *recv_cq);
 631 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 632                                struct mlx5_ib_cq *recv_cq);
 633
 634 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 635                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 636                         bool dyn_bfreg)
 637 {
 638         unsigned int bfregs_per_sys_page;
 639         u32 index_of_sys_page;
 640         u32 offset;
 641
 642         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 643                                 MLX5_NON_FP_BFREGS_PER_UAR;
 644         index_of_sys_page = bfregn / bfregs_per_sys_page;
 645
 646         if (dyn_bfreg) {
 647                 index_of_sys_page += bfregi->num_static_sys_pages;
 648
 649                 if (index_of_sys_page >= bfregi->num_sys_pages)
 650                         return -EINVAL;
 651
 652                 if (bfregn > bfregi->num_dyn_bfregs ||
 653                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 654                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 655                         return -EINVAL;
 656                 }
 657         }
 658
 659         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 660         return bfregi->sys_pages[index_of_sys_page] + offset;
 661 }
 662
 663 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 664                             struct ib_pd *pd,
 665                             unsigned long addr, size_t size,
 666                             struct ib_umem **umem,
 667                             int *npages, int *page_shift, int *ncont,
 668                             u32 *offset)
 669 {
 670         int err;
 671
 672         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 673         if (IS_ERR(*umem)) {
 674                 mlx5_ib_dbg(dev, "umem_get failed\n");
 675                 return PTR_ERR(*umem);
 676         }
 677
 678         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 679
 680         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 681         if (err) {
 682                 mlx5_ib_warn(dev, "bad offset\n");
 683                 goto err_umem;
 684         }
 685
 686         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 687                     addr, size, *npages, *page_shift, *ncont, *offset);
 688
 689         return 0;
 690
 691 err_umem:
 692         ib_umem_release(*umem);
 693         *umem = NULL;
 694
 695         return err;
 696 }
 697
 698 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 699                             struct mlx5_ib_rwq *rwq)
 700 {
 701         struct mlx5_ib_ucontext *context;
 702
 703         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 704                 atomic_dec(&dev->delay_drop.rqs_cnt);
 705
 706         context = to_mucontext(pd->uobject->context);
 707         mlx5_ib_db_unmap_user(context, &rwq->db);
 708         if (rwq->umem)
 709                 ib_umem_release(rwq->umem);
 710 }
 711
 712 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 713                           struct mlx5_ib_rwq *rwq,
 714                           struct mlx5_ib_create_wq *ucmd)
 715 {
 716         struct mlx5_ib_ucontext *context;
 717         int page_shift = 0;
 718         int npages;
 719         u32 offset = 0;
 720         int ncont = 0;
 721         int err;
 722
 723         if (!ucmd->buf_addr)
 724                 return -EINVAL;
 725
 726         context = to_mucontext(pd->uobject->context);
 727         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 728                                rwq->buf_size, 0, 0);
 729         if (IS_ERR(rwq->umem)) {
 730                 mlx5_ib_dbg(dev, "umem_get failed\n");
 731                 err = PTR_ERR(rwq->umem);
 732                 return err;
 733         }
 734
 735         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 736                            &ncont, NULL);
 737         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 738                                      &rwq->rq_page_offset);
 739         if (err) {
 740                 mlx5_ib_warn(dev, "bad offset\n");
 741                 goto err_umem;
 742         }
 743
 744         rwq->rq_num_pas = ncont;
 745         rwq->page_shift = page_shift;
 746         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 747         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 748
 749         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 750                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 751                     npages, page_shift, ncont, offset);
 752
 753         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 754         if (err) {
 755                 mlx5_ib_dbg(dev, "map failed\n");
 756                 goto err_umem;
 757         }
 758
 759         rwq->create_type = MLX5_WQ_USER;
 760         return 0;
 761
 762 err_umem:
 763         ib_umem_release(rwq->umem);
 764         return err;
 765 }
 766
 767 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 768                          struct mlx5_bfreg_info *bfregi, int bfregn)
 769 {
 770         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 771                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 772 }
 773
 774 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 775                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 776                           struct ib_qp_init_attr *attr,
 777                           u32 **in,
 778                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 779                           struct mlx5_ib_qp_base *base)
 780 {
 781         struct mlx5_ib_ucontext *context;
 782         struct mlx5_ib_create_qp ucmd;
 783         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 784         int page_shift = 0;
 785         int uar_index = 0;
 786         int npages;
 787         u32 offset = 0;
 788         int bfregn;
 789         int ncont = 0;
 790         __be64 *pas;
 791         void *qpc;
 792         int err;
 793
 794         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 795         if (err) {
 796                 mlx5_ib_dbg(dev, "copy failed\n");
 797                 return err;
 798         }
 799
 800         context = to_mucontext(pd->uobject->context);
 801         if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
 802                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 803                                                 ucmd.bfreg_index, true);
 804                 if (uar_index < 0)
 805                         return uar_index;
 806
 807                 bfregn = MLX5_IB_INVALID_BFREG;
 808         } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
 809                 /*
 810                  * TBD: should come from the verbs when we have the API
 811                  */
 812                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 813                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
 814         }
 815         else {
 816                 bfregn = alloc_bfreg(dev, &context->bfregi);
 817                 if (bfregn < 0)
 818                         return bfregn;
 819         }
 820
 821         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 822         if (bfregn != MLX5_IB_INVALID_BFREG)
 823                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 824                                                 false);
 825
 826         qp->rq.offset = 0;
 827         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 828         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 829
 830         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 831         if (err)
 832                 goto err_bfreg;
 833
 834         if (ucmd.buf_addr && ubuffer->buf_size) {
 835                 ubuffer->buf_addr = ucmd.buf_addr;
 836                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 837                                        ubuffer->buf_size,
 838                                        &ubuffer->umem, &npages, &page_shift,
 839                                        &ncont, &offset);
 840                 if (err)
 841                         goto err_bfreg;
 842         } else {
 843                 ubuffer->umem = NULL;
 844         }
 845
 846         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 847                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 848         *in = kvzalloc(*inlen, GFP_KERNEL);
 849         if (!*in) {
 850                 err = -ENOMEM;
 851                 goto err_umem;
 852         }
 853
 854         MLX5_SET(create_qp_in, *in, uid, to_mpd(pd)->uid);
 855         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 856         if (ubuffer->umem)
 857                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 858
 859         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 860
 861         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 862         MLX5_SET(qpc, qpc, page_offset, offset);
 863
 864         MLX5_SET(qpc, qpc, uar_page, uar_index);
 865         if (bfregn != MLX5_IB_INVALID_BFREG)
 866                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 867         else
 868                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
 869         qp->bfregn = bfregn;
 870
 871         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 872         if (err) {
 873                 mlx5_ib_dbg(dev, "map failed\n");
 874                 goto err_free;
 875         }
 876
 877         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
 878         if (err) {
 879                 mlx5_ib_dbg(dev, "copy failed\n");
 880                 goto err_unmap;
 881         }
 882         qp->create_type = MLX5_QP_USER;
 883
 884         return 0;
 885
 886 err_unmap:
 887         mlx5_ib_db_unmap_user(context, &qp->db);
 888
 889 err_free:
 890         kvfree(*in);
 891
 892 err_umem:
 893         if (ubuffer->umem)
 894                 ib_umem_release(ubuffer->umem);
 895
 896 err_bfreg:
 897         if (bfregn != MLX5_IB_INVALID_BFREG)
 898                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
 899         return err;
 900 }
 901
 902 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 903                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
 904 {
 905         struct mlx5_ib_ucontext *context;
 906
 907         context = to_mucontext(pd->uobject->context);
 908         mlx5_ib_db_unmap_user(context, &qp->db);
 909         if (base->ubuffer.umem)
 910                 ib_umem_release(base->ubuffer.umem);
 911
 912         /*
 913          * Free only the BFREGs which are handled by the kernel.
 914          * BFREGs of UARs allocated dynamically are handled by user.
 915          */
 916         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
 917                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
 918 }
 919
 920 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 921                             struct ib_qp_init_attr *init_attr,
 922                             struct mlx5_ib_qp *qp,
 923                             u32 **in, int *inlen,
 924                             struct mlx5_ib_qp_base *base)
 925 {
 926         int uar_index;
 927         void *qpc;
 928         int err;
 929
 930         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 931                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 932                                         IB_QP_CREATE_IPOIB_UD_LSO |
 933                                         IB_QP_CREATE_NETIF_QP |
 934                                         mlx5_ib_create_qp_sqpn_qp1()))
 935                 return -EINVAL;
 936
 937         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 938                 qp->bf.bfreg = &dev->fp_bfreg;
 939         else
 940                 qp->bf.bfreg = &dev->bfreg;
 941
 942         /* We need to divide by two since each register is comprised of
 943          * two buffers of identical size, namely odd and even
 944          */
 945         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
 946         uar_index = qp->bf.bfreg->index;
 947
 948         err = calc_sq_size(dev, init_attr, qp);
 949         if (err < 0) {
 950                 mlx5_ib_dbg(dev, "err %d\n", err);
 951                 return err;
 952         }
 953
 954         qp->rq.offset = 0;
 955         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 956         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 957
 958         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 959         if (err) {
 960                 mlx5_ib_dbg(dev, "err %d\n", err);
 961                 return err;
 962         }
 963
 964         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 965         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 966                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 967         *in = kvzalloc(*inlen, GFP_KERNEL);
 968         if (!*in) {
 969                 err = -ENOMEM;
 970                 goto err_buf;
 971         }
 972
 973         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 974         MLX5_SET(qpc, qpc, uar_page, uar_index);
 975         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 976
 977         /* Set "fast registration enabled" for all kernel QPs */
 978         MLX5_SET(qpc, qpc, fre, 1);
 979         MLX5_SET(qpc, qpc, rlky, 1);
 980
 981         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 982                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
 983                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 984         }
 985
 986         mlx5_fill_page_array(&qp->buf,
 987                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
 988
 989         err = mlx5_db_alloc(dev->mdev, &qp->db);
 990         if (err) {
 991                 mlx5_ib_dbg(dev, "err %d\n", err);
 992                 goto err_free;
 993         }
 994
 995         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
 996                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
 997         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
 998                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
 999         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1000                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1001         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1002                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1003         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1004                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1005
1006         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1007             !qp->sq.w_list || !qp->sq.wqe_head) {
1008                 err = -ENOMEM;
1009                 goto err_wrid;
1010         }
1011         qp->create_type = MLX5_QP_KERNEL;
1012
1013         return 0;
1014
1015 err_wrid:
1016         kvfree(qp->sq.wqe_head);
1017         kvfree(qp->sq.w_list);
1018         kvfree(qp->sq.wrid);
1019         kvfree(qp->sq.wr_data);
1020         kvfree(qp->rq.wrid);
1021         mlx5_db_free(dev->mdev, &qp->db);
1022
1023 err_free:
1024         kvfree(*in);
1025
1026 err_buf:
1027         mlx5_buf_free(dev->mdev, &qp->buf);
1028         return err;
1029 }
1030
1031 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1032 {
1033         kvfree(qp->sq.wqe_head);
1034         kvfree(qp->sq.w_list);
1035         kvfree(qp->sq.wrid);
1036         kvfree(qp->sq.wr_data);
1037         kvfree(qp->rq.wrid);
1038         mlx5_db_free(dev->mdev, &qp->db);
1039         mlx5_buf_free(dev->mdev, &qp->buf);
1040 }
1041
1042 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1043 {
1044         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1045             (attr->qp_type == MLX5_IB_QPT_DCI) ||
1046             (attr->qp_type == IB_QPT_XRC_INI))
1047                 return MLX5_SRQ_RQ;
1048         else if (!qp->has_rq)
1049                 return MLX5_ZERO_LEN_RQ;
1050         else
1051                 return MLX5_NON_ZERO_RQ;
1052 }
1053
1054 static int is_connected(enum ib_qp_type qp_type)
1055 {
1056         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1057                 return 1;
1058
1059         return 0;
1060 }
1061
1062 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1063                                     struct mlx5_ib_qp *qp,
1064                                     struct mlx5_ib_sq *sq, u32 tdn,
1065                                     struct ib_pd *pd)
1066 {
1067         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1068         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1069
1070         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1071         MLX5_SET(tisc, tisc, transport_domain, tdn);
1072         if (qp->flags & MLX5_IB_QP_UNDERLAY)
1073                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1074
1075         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1076 }
1077
1078 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1079                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1080 {
1081         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1082 }
1083
1084 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1085                                        struct mlx5_ib_sq *sq)
1086 {
1087         if (sq->flow_rule)
1088                 mlx5_del_flow_rules(sq->flow_rule);
1089 }
1090
1091 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1092                                    struct mlx5_ib_sq *sq, void *qpin,
1093                                    struct ib_pd *pd)
1094 {
1095         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1096         __be64 *pas;
1097         void *in;
1098         void *sqc;
1099         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1100         void *wq;
1101         int inlen;
1102         int err;
1103         int page_shift = 0;
1104         int npages;
1105         int ncont = 0;
1106         u32 offset = 0;
1107
1108         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1109                                &sq->ubuffer.umem, &npages, &page_shift,
1110                                &ncont, &offset);
1111         if (err)
1112                 return err;
1113
1114         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1115         in = kvzalloc(inlen, GFP_KERNEL);
1116         if (!in) {
1117                 err = -ENOMEM;
1118                 goto err_umem;
1119         }
1120
1121         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1122         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1123         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1124         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1125                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1126         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1127         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1128         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1129         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1130         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1131         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1132             MLX5_CAP_ETH(dev->mdev, swp))
1133                 MLX5_SET(sqc, sqc, allow_swp, 1);
1134
1135         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1136         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1137         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1138         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1139         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1140         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1141         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1142         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1143         MLX5_SET(wq, wq, page_offset, offset);
1144
1145         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1146         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1147
1148         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1149
1150         kvfree(in);
1151
1152         if (err)
1153                 goto err_umem;
1154
1155         err = create_flow_rule_vport_sq(dev, sq);
1156         if (err)
1157                 goto err_flow;
1158
1159         return 0;
1160
1161 err_flow:
1162         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1163
1164 err_umem:
1165         ib_umem_release(sq->ubuffer.umem);
1166         sq->ubuffer.umem = NULL;
1167
1168         return err;
1169 }
1170
1171 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1172                                      struct mlx5_ib_sq *sq)
1173 {
1174         destroy_flow_rule_vport_sq(dev, sq);
1175         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1176         ib_umem_release(sq->ubuffer.umem);
1177 }
1178
1179 static size_t get_rq_pas_size(void *qpc)
1180 {
1181         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1182         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1183         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1184         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1185         u32 po_quanta     = 1 << (log_page_size - 6);
1186         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1187         u32 page_size     = 1 << log_page_size;
1188         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1189         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1190
1191         return rq_num_pas * sizeof(u64);
1192 }
1193
1194 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1195                                    struct mlx5_ib_rq *rq, void *qpin,
1196                                    size_t qpinlen, struct ib_pd *pd)
1197 {
1198         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1199         __be64 *pas;
1200         __be64 *qp_pas;
1201         void *in;
1202         void *rqc;
1203         void *wq;
1204         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1205         size_t rq_pas_size = get_rq_pas_size(qpc);
1206         size_t inlen;
1207         int err;
1208
1209         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1210                 return -EINVAL;
1211
1212         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1213         in = kvzalloc(inlen, GFP_KERNEL);
1214         if (!in)
1215                 return -ENOMEM;
1216
1217         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1218         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1219         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1220                 MLX5_SET(rqc, rqc, vsd, 1);
1221         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1222         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1223         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1224         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1225         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1226
1227         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1228                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1229
1230         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1231         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1232         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1233                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1234         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1235         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1236         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1237         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1238         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1239         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1240
1241         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1242         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1243         memcpy(pas, qp_pas, rq_pas_size);
1244
1245         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1246
1247         kvfree(in);
1248
1249         return err;
1250 }
1251
1252 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1253                                      struct mlx5_ib_rq *rq)
1254 {
1255         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1256 }
1257
1258 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1259 {
1260         return  (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1261                  MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1262                  MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1263 }
1264
1265 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1266                                       struct mlx5_ib_rq *rq,
1267                                       u32 qp_flags_en,
1268                                       struct ib_pd *pd)
1269 {
1270         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1271                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1272                 mlx5_ib_disable_lb(dev, false, true);
1273         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1274 }
1275
1276 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1277                                     struct mlx5_ib_rq *rq, u32 tdn,
1278                                     u32 *qp_flags_en,
1279                                     struct ib_pd *pd)
1280 {
1281         u8 lb_flag = 0;
1282         u32 *in;
1283         void *tirc;
1284         int inlen;
1285         int err;
1286
1287         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1288         in = kvzalloc(inlen, GFP_KERNEL);
1289         if (!in)
1290                 return -ENOMEM;
1291
1292         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1293         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1294         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1295         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1296         MLX5_SET(tirc, tirc, transport_domain, tdn);
1297         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1298                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1299
1300         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1301                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1302
1303         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1304                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1305
1306         if (dev->rep) {
1307                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1308                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1309         }
1310
1311         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1312
1313         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1314
1315         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1316                 err = mlx5_ib_enable_lb(dev, false, true);
1317
1318                 if (err)
1319                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1320         }
1321         kvfree(in);
1322
1323         return err;
1324 }
1325
1326 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1327                                 u32 *in, size_t inlen,
1328                                 struct ib_pd *pd,
1329                                 struct ib_udata *udata,
1330                                 struct mlx5_ib_create_qp_resp *resp)
1331 {
1332         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1333         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1334         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1335         struct ib_uobject *uobj = pd->uobject;
1336         struct ib_ucontext *ucontext = uobj->context;
1337         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1338         int err;
1339         u32 tdn = mucontext->tdn;
1340         u16 uid = to_mpd(pd)->uid;
1341
1342         if (qp->sq.wqe_cnt) {
1343                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1344                 if (err)
1345                         return err;
1346
1347                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1348                 if (err)
1349                         goto err_destroy_tis;
1350
1351                 if (uid) {
1352                         resp->tisn = sq->tisn;
1353                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1354                         resp->sqn = sq->base.mqp.qpn;
1355                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1356                 }
1357
1358                 sq->base.container_mibqp = qp;
1359                 sq->base.mqp.event = mlx5_ib_qp_event;
1360         }
1361
1362         if (qp->rq.wqe_cnt) {
1363                 rq->base.container_mibqp = qp;
1364
1365                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1366                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1367                 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1368                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1369                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1370                 if (err)
1371                         goto err_destroy_sq;
1372
1373                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd);
1374                 if (err)
1375                         goto err_destroy_rq;
1376
1377                 if (uid) {
1378                         resp->rqn = rq->base.mqp.qpn;
1379                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1380                         resp->tirn = rq->tirn;
1381                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1382                 }
1383         }
1384
1385         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1386                                                      rq->base.mqp.qpn;
1387         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1388         if (err)
1389                 goto err_destroy_tir;
1390
1391         return 0;
1392
1393 err_destroy_tir:
1394         destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1395 err_destroy_rq:
1396         destroy_raw_packet_qp_rq(dev, rq);
1397 err_destroy_sq:
1398         if (!qp->sq.wqe_cnt)
1399                 return err;
1400         destroy_raw_packet_qp_sq(dev, sq);
1401 err_destroy_tis:
1402         destroy_raw_packet_qp_tis(dev, sq, pd);
1403
1404         return err;
1405 }
1406
1407 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1408                                   struct mlx5_ib_qp *qp)
1409 {
1410         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1411         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1412         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1413
1414         if (qp->rq.wqe_cnt) {
1415                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1416                 destroy_raw_packet_qp_rq(dev, rq);
1417         }
1418
1419         if (qp->sq.wqe_cnt) {
1420                 destroy_raw_packet_qp_sq(dev, sq);
1421                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1422         }
1423 }
1424
1425 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1426                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1427 {
1428         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1429         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1430
1431         sq->sq = &qp->sq;
1432         rq->rq = &qp->rq;
1433         sq->doorbell = &qp->db;
1434         rq->doorbell = &qp->db;
1435 }
1436
1437 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1438 {
1439         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1440                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1441                 mlx5_ib_disable_lb(dev, false, true);
1442         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1443                              to_mpd(qp->ibqp.pd)->uid);
1444 }
1445
1446 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1447                                  struct ib_pd *pd,
1448                                  struct ib_qp_init_attr *init_attr,
1449                                  struct ib_udata *udata)
1450 {
1451         struct ib_uobject *uobj = pd->uobject;
1452         struct ib_ucontext *ucontext = uobj->context;
1453         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1454         struct mlx5_ib_create_qp_resp resp = {};
1455         int inlen;
1456         int err;
1457         u32 *in;
1458         void *tirc;
1459         void *hfso;
1460         u32 selected_fields = 0;
1461         u32 outer_l4;
1462         size_t min_resp_len;
1463         u32 tdn = mucontext->tdn;
1464         struct mlx5_ib_create_qp_rss ucmd = {};
1465         size_t required_cmd_sz;
1466         u8 lb_flag = 0;
1467
1468         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1469                 return -EOPNOTSUPP;
1470
1471         if (init_attr->create_flags || init_attr->send_cq)
1472                 return -EINVAL;
1473
1474         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1475         if (udata->outlen < min_resp_len)
1476                 return -EINVAL;
1477
1478         required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1479         if (udata->inlen < required_cmd_sz) {
1480                 mlx5_ib_dbg(dev, "invalid inlen\n");
1481                 return -EINVAL;
1482         }
1483
1484         if (udata->inlen > sizeof(ucmd) &&
1485             !ib_is_udata_cleared(udata, sizeof(ucmd),
1486                                  udata->inlen - sizeof(ucmd))) {
1487                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1488                 return -EOPNOTSUPP;
1489         }
1490
1491         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1492                 mlx5_ib_dbg(dev, "copy failed\n");
1493                 return -EFAULT;
1494         }
1495
1496         if (ucmd.comp_mask) {
1497                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1498                 return -EOPNOTSUPP;
1499         }
1500
1501         if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1502                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1503                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1504                 mlx5_ib_dbg(dev, "invalid flags\n");
1505                 return -EOPNOTSUPP;
1506         }
1507
1508         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1509             !tunnel_offload_supported(dev->mdev)) {
1510                 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1511                 return -EOPNOTSUPP;
1512         }
1513
1514         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1515             !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1516                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1517                 return -EOPNOTSUPP;
1518         }
1519
1520         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) {
1521                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1522                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1523         }
1524
1525         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1526                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1527                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1528         }
1529
1530         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1531         if (err) {
1532                 mlx5_ib_dbg(dev, "copy failed\n");
1533                 return -EINVAL;
1534         }
1535
1536         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1537         in = kvzalloc(inlen, GFP_KERNEL);
1538         if (!in)
1539                 return -ENOMEM;
1540
1541         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1542         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1543         MLX5_SET(tirc, tirc, disp_type,
1544                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1545         MLX5_SET(tirc, tirc, indirect_table,
1546                  init_attr->rwq_ind_tbl->ind_tbl_num);
1547         MLX5_SET(tirc, tirc, transport_domain, tdn);
1548
1549         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1550
1551         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1552                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1553
1554         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1555
1556         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1557                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1558         else
1559                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1560
1561         switch (ucmd.rx_hash_function) {
1562         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1563         {
1564                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1565                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1566
1567                 if (len != ucmd.rx_key_len) {
1568                         err = -EINVAL;
1569                         goto err;
1570                 }
1571
1572                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1573                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1574                 memcpy(rss_key, ucmd.rx_hash_key, len);
1575                 break;
1576         }
1577         default:
1578                 err = -EOPNOTSUPP;
1579                 goto err;
1580         }
1581
1582         if (!ucmd.rx_hash_fields_mask) {
1583                 /* special case when this TIR serves as steering entry without hashing */
1584                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1585                         goto create_tir;
1586                 err = -EINVAL;
1587                 goto err;
1588         }
1589
1590         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1591              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1592              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1593              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1594                 err = -EINVAL;
1595                 goto err;
1596         }
1597
1598         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1599         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1600             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1601                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1602                          MLX5_L3_PROT_TYPE_IPV4);
1603         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1604                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1605                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1606                          MLX5_L3_PROT_TYPE_IPV6);
1607
1608         outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1609                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1610                    ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1611                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1612                    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1613
1614         /* Check that only one l4 protocol is set */
1615         if (outer_l4 & (outer_l4 - 1)) {
1616                 err = -EINVAL;
1617                 goto err;
1618         }
1619
1620         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1621         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1622             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1623                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1624                          MLX5_L4_PROT_TYPE_TCP);
1625         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1626                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1627                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1628                          MLX5_L4_PROT_TYPE_UDP);
1629
1630         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1631             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1632                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1633
1634         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1635             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1636                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1637
1638         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1639             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1640                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1641
1642         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1643             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1644                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1645
1646         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1647                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1648
1649         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1650
1651 create_tir:
1652         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1653
1654         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1655                 err = mlx5_ib_enable_lb(dev, false, true);
1656
1657                 if (err)
1658                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1659                                              to_mpd(pd)->uid);
1660         }
1661
1662         if (err)
1663                 goto err;
1664
1665         if (mucontext->devx_uid) {
1666                 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1667                 resp.tirn = qp->rss_qp.tirn;
1668         }
1669
1670         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1671         if (err)
1672                 goto err_copy;
1673
1674         kvfree(in);
1675         /* qpn is reserved for that QP */
1676         qp->trans_qp.base.mqp.qpn = 0;
1677         qp->flags |= MLX5_IB_QP_RSS;
1678         return 0;
1679
1680 err_copy:
1681         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1682 err:
1683         kvfree(in);
1684         return err;
1685 }
1686
1687 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1688                             struct ib_qp_init_attr *init_attr,
1689                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1690 {
1691         struct mlx5_ib_resources *devr = &dev->devr;
1692         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1693         struct mlx5_core_dev *mdev = dev->mdev;
1694         struct mlx5_ib_create_qp_resp resp = {};
1695         struct mlx5_ib_cq *send_cq;
1696         struct mlx5_ib_cq *recv_cq;
1697         unsigned long flags;
1698         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1699         struct mlx5_ib_create_qp ucmd;
1700         struct mlx5_ib_qp_base *base;
1701         int mlx5_st;
1702         void *qpc;
1703         u32 *in;
1704         int err;
1705
1706         mutex_init(&qp->mutex);
1707         spin_lock_init(&qp->sq.lock);
1708         spin_lock_init(&qp->rq.lock);
1709
1710         mlx5_st = to_mlx5_st(init_attr->qp_type);
1711         if (mlx5_st < 0)
1712                 return -EINVAL;
1713
1714         if (init_attr->rwq_ind_tbl) {
1715                 if (!udata)
1716                         return -ENOSYS;
1717
1718                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1719                 return err;
1720         }
1721
1722         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1723                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1724                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1725                         return -EINVAL;
1726                 } else {
1727                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1728                 }
1729         }
1730
1731         if (init_attr->create_flags &
1732                         (IB_QP_CREATE_CROSS_CHANNEL |
1733                          IB_QP_CREATE_MANAGED_SEND |
1734                          IB_QP_CREATE_MANAGED_RECV)) {
1735                 if (!MLX5_CAP_GEN(mdev, cd)) {
1736                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1737                         return -EINVAL;
1738                 }
1739                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1740                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1741                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1742                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1743                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1744                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1745         }
1746
1747         if (init_attr->qp_type == IB_QPT_UD &&
1748             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1749                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1750                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1751                         return -EOPNOTSUPP;
1752                 }
1753
1754         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1755                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1756                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1757                         return -EOPNOTSUPP;
1758                 }
1759                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1760                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1761                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1762                         return -EOPNOTSUPP;
1763                 }
1764                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1765         }
1766
1767         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1768                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1769
1770         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1771                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1772                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1773                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
1774                         return -EOPNOTSUPP;
1775                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1776         }
1777
1778         if (pd && pd->uobject) {
1779                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1780                         mlx5_ib_dbg(dev, "copy failed\n");
1781                         return -EFAULT;
1782                 }
1783
1784                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1785                                         &ucmd, udata->inlen, &uidx);
1786                 if (err)
1787                         return err;
1788
1789                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1790                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1791                 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1792                         if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1793                             !tunnel_offload_supported(mdev)) {
1794                                 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1795                                 return -EOPNOTSUPP;
1796                         }
1797                         qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
1798                 }
1799
1800                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
1801                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1802                                 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
1803                                 return -EOPNOTSUPP;
1804                         }
1805                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1806                 }
1807
1808                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1809                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1810                                 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
1811                                 return -EOPNOTSUPP;
1812                         }
1813                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1814                 }
1815
1816                 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1817                         if (init_attr->qp_type != IB_QPT_UD ||
1818                             (MLX5_CAP_GEN(dev->mdev, port_type) !=
1819                              MLX5_CAP_PORT_TYPE_IB) ||
1820                             !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1821                                 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1822                                 return -EOPNOTSUPP;
1823                         }
1824
1825                         qp->flags |= MLX5_IB_QP_UNDERLAY;
1826                         qp->underlay_qpn = init_attr->source_qpn;
1827                 }
1828         } else {
1829                 qp->wq_sig = !!wq_signature;
1830         }
1831
1832         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1833                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1834                &qp->raw_packet_qp.rq.base :
1835                &qp->trans_qp.base;
1836
1837         qp->has_rq = qp_has_rq(init_attr);
1838         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1839                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1840         if (err) {
1841                 mlx5_ib_dbg(dev, "err %d\n", err);
1842                 return err;
1843         }
1844
1845         if (pd) {
1846                 if (pd->uobject) {
1847                         __u32 max_wqes =
1848                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1849                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1850                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1851                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1852                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1853                                 return -EINVAL;
1854                         }
1855                         if (ucmd.sq_wqe_count > max_wqes) {
1856                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1857                                             ucmd.sq_wqe_count, max_wqes);
1858                                 return -EINVAL;
1859                         }
1860                         if (init_attr->create_flags &
1861                             mlx5_ib_create_qp_sqpn_qp1()) {
1862                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1863                                 return -EINVAL;
1864                         }
1865                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1866                                              &resp, &inlen, base);
1867                         if (err)
1868                                 mlx5_ib_dbg(dev, "err %d\n", err);
1869                 } else {
1870                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1871                                                base);
1872                         if (err)
1873                                 mlx5_ib_dbg(dev, "err %d\n", err);
1874                 }
1875
1876                 if (err)
1877                         return err;
1878         } else {
1879                 in = kvzalloc(inlen, GFP_KERNEL);
1880                 if (!in)
1881                         return -ENOMEM;
1882
1883                 qp->create_type = MLX5_QP_EMPTY;
1884         }
1885
1886         if (is_sqp(init_attr->qp_type))
1887                 qp->port = init_attr->port_num;
1888
1889         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1890
1891         MLX5_SET(qpc, qpc, st, mlx5_st);
1892         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1893
1894         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1895                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1896         else
1897                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1898
1899
1900         if (qp->wq_sig)
1901                 MLX5_SET(qpc, qpc, wq_signature, 1);
1902
1903         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1904                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1905
1906         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1907                 MLX5_SET(qpc, qpc, cd_master, 1);
1908         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1909                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1910         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1911                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1912
1913         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1914                 int rcqe_sz;
1915                 int scqe_sz;
1916
1917                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1918                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1919
1920                 if (rcqe_sz == 128)
1921                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1922                 else
1923                         MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1924
1925                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1926                         if (scqe_sz == 128)
1927                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1928                         else
1929                                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1930                 }
1931         }
1932
1933         if (qp->rq.wqe_cnt) {
1934                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1935                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1936         }
1937
1938         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1939
1940         if (qp->sq.wqe_cnt) {
1941                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1942         } else {
1943                 MLX5_SET(qpc, qpc, no_sq, 1);
1944                 if (init_attr->srq &&
1945                     init_attr->srq->srq_type == IB_SRQT_TM)
1946                         MLX5_SET(qpc, qpc, offload_type,
1947                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
1948         }
1949
1950         /* Set default resources */
1951         switch (init_attr->qp_type) {
1952         case IB_QPT_XRC_TGT:
1953                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1954                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1955                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1956                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1957                 break;
1958         case IB_QPT_XRC_INI:
1959                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1960                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1961                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1962                 break;
1963         default:
1964                 if (init_attr->srq) {
1965                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1966                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1967                 } else {
1968                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1969                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1970                 }
1971         }
1972
1973         if (init_attr->send_cq)
1974                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1975
1976         if (init_attr->recv_cq)
1977                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1978
1979         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1980
1981         /* 0xffffff means we ask to work with cqe version 0 */
1982         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1983                 MLX5_SET(qpc, qpc, user_index, uidx);
1984
1985         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1986         if (init_attr->qp_type == IB_QPT_UD &&
1987             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1988                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1989                 qp->flags |= MLX5_IB_QP_LSO;
1990         }
1991
1992         if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1993                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1994                         mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1995                         err = -EOPNOTSUPP;
1996                         goto err;
1997                 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1998                         MLX5_SET(qpc, qpc, end_padding_mode,
1999                                  MLX5_WQ_END_PAD_MODE_ALIGN);
2000                 } else {
2001                         qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2002                 }
2003         }
2004
2005         if (inlen < 0) {
2006                 err = -EINVAL;
2007                 goto err;
2008         }
2009
2010         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2011             qp->flags & MLX5_IB_QP_UNDERLAY) {
2012                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2013                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2014                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2015                                            &resp);
2016         } else {
2017                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2018         }
2019
2020         if (err) {
2021                 mlx5_ib_dbg(dev, "create qp failed\n");
2022                 goto err_create;
2023         }
2024
2025         kvfree(in);
2026
2027         base->container_mibqp = qp;
2028         base->mqp.event = mlx5_ib_qp_event;
2029
2030         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2031                 &send_cq, &recv_cq);
2032         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2033         mlx5_ib_lock_cqs(send_cq, recv_cq);
2034         /* Maintain device to QPs access, needed for further handling via reset
2035          * flow
2036          */
2037         list_add_tail(&qp->qps_list, &dev->qp_list);
2038         /* Maintain CQ to QPs access, needed for further handling via reset flow
2039          */
2040         if (send_cq)
2041                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2042         if (recv_cq)
2043                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2044         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2045         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2046
2047         return 0;
2048
2049 err_create:
2050         if (qp->create_type == MLX5_QP_USER)
2051                 destroy_qp_user(dev, pd, qp, base);
2052         else if (qp->create_type == MLX5_QP_KERNEL)
2053                 destroy_qp_kernel(dev, qp);
2054
2055 err:
2056         kvfree(in);
2057         return err;
2058 }
2059
2060 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2061         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2062 {
2063         if (send_cq) {
2064                 if (recv_cq) {
2065                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2066                                 spin_lock(&send_cq->lock);
2067                                 spin_lock_nested(&recv_cq->lock,
2068                                                  SINGLE_DEPTH_NESTING);
2069                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2070                                 spin_lock(&send_cq->lock);
2071                                 __acquire(&recv_cq->lock);
2072                         } else {
2073                                 spin_lock(&recv_cq->lock);
2074                                 spin_lock_nested(&send_cq->lock,
2075                                                  SINGLE_DEPTH_NESTING);
2076                         }
2077                 } else {
2078                         spin_lock(&send_cq->lock);
2079                         __acquire(&recv_cq->lock);
2080                 }
2081         } else if (recv_cq) {
2082                 spin_lock(&recv_cq->lock);
2083                 __acquire(&send_cq->lock);
2084         } else {
2085                 __acquire(&send_cq->lock);
2086                 __acquire(&recv_cq->lock);
2087         }
2088 }
2089
2090 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2091         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2092 {
2093         if (send_cq) {
2094                 if (recv_cq) {
2095                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2096                                 spin_unlock(&recv_cq->lock);
2097                                 spin_unlock(&send_cq->lock);
2098                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2099                                 __release(&recv_cq->lock);
2100                                 spin_unlock(&send_cq->lock);
2101                         } else {
2102                                 spin_unlock(&send_cq->lock);
2103                                 spin_unlock(&recv_cq->lock);
2104                         }
2105                 } else {
2106                         __release(&recv_cq->lock);
2107                         spin_unlock(&send_cq->lock);
2108                 }
2109         } else if (recv_cq) {
2110                 __release(&send_cq->lock);
2111                 spin_unlock(&recv_cq->lock);
2112         } else {
2113                 __release(&recv_cq->lock);
2114                 __release(&send_cq->lock);
2115         }
2116 }
2117
2118 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2119 {
2120         return to_mpd(qp->ibqp.pd);
2121 }
2122
2123 static void get_cqs(enum ib_qp_type qp_type,
2124                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2125                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2126 {
2127         switch (qp_type) {
2128         case IB_QPT_XRC_TGT:
2129                 *send_cq = NULL;
2130                 *recv_cq = NULL;
2131                 break;
2132         case MLX5_IB_QPT_REG_UMR:
2133         case IB_QPT_XRC_INI:
2134                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2135                 *recv_cq = NULL;
2136                 break;
2137
2138         case IB_QPT_SMI:
2139         case MLX5_IB_QPT_HW_GSI:
2140         case IB_QPT_RC:
2141         case IB_QPT_UC:
2142         case IB_QPT_UD:
2143         case IB_QPT_RAW_IPV6:
2144         case IB_QPT_RAW_ETHERTYPE:
2145         case IB_QPT_RAW_PACKET:
2146                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2147                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2148                 break;
2149
2150         case IB_QPT_MAX:
2151         default:
2152                 *send_cq = NULL;
2153                 *recv_cq = NULL;
2154                 break;
2155         }
2156 }
2157
2158 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2159                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2160                                 u8 lag_tx_affinity);
2161
2162 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2163 {
2164         struct mlx5_ib_cq *send_cq, *recv_cq;
2165         struct mlx5_ib_qp_base *base;
2166         unsigned long flags;
2167         int err;
2168
2169         if (qp->ibqp.rwq_ind_tbl) {
2170                 destroy_rss_raw_qp_tir(dev, qp);
2171                 return;
2172         }
2173
2174         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2175                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2176                &qp->raw_packet_qp.rq.base :
2177                &qp->trans_qp.base;
2178
2179         if (qp->state != IB_QPS_RESET) {
2180                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2181                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2182                         err = mlx5_core_qp_modify(dev->mdev,
2183                                                   MLX5_CMD_OP_2RST_QP, 0,
2184                                                   NULL, &base->mqp);
2185                 } else {
2186                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2187                                 .operation = MLX5_CMD_OP_2RST_QP
2188                         };
2189
2190                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2191                 }
2192                 if (err)
2193                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2194                                      base->mqp.qpn);
2195         }
2196
2197         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2198                 &send_cq, &recv_cq);
2199
2200         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2201         mlx5_ib_lock_cqs(send_cq, recv_cq);
2202         /* del from lists under both locks above to protect reset flow paths */
2203         list_del(&qp->qps_list);
2204         if (send_cq)
2205                 list_del(&qp->cq_send_list);
2206
2207         if (recv_cq)
2208                 list_del(&qp->cq_recv_list);
2209
2210         if (qp->create_type == MLX5_QP_KERNEL) {
2211                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2212                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2213                 if (send_cq != recv_cq)
2214                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2215                                            NULL);
2216         }
2217         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2218         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2219
2220         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2221             qp->flags & MLX5_IB_QP_UNDERLAY) {
2222                 destroy_raw_packet_qp(dev, qp);
2223         } else {
2224                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2225                 if (err)
2226                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2227                                      base->mqp.qpn);
2228         }
2229
2230         if (qp->create_type == MLX5_QP_KERNEL)
2231                 destroy_qp_kernel(dev, qp);
2232         else if (qp->create_type == MLX5_QP_USER)
2233                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2234 }
2235
2236 static const char *ib_qp_type_str(enum ib_qp_type type)
2237 {
2238         switch (type) {
2239         case IB_QPT_SMI:
2240                 return "IB_QPT_SMI";
2241         case IB_QPT_GSI:
2242                 return "IB_QPT_GSI";
2243         case IB_QPT_RC:
2244                 return "IB_QPT_RC";
2245         case IB_QPT_UC:
2246                 return "IB_QPT_UC";
2247         case IB_QPT_UD:
2248                 return "IB_QPT_UD";
2249         case IB_QPT_RAW_IPV6:
2250                 return "IB_QPT_RAW_IPV6";
2251         case IB_QPT_RAW_ETHERTYPE:
2252                 return "IB_QPT_RAW_ETHERTYPE";
2253         case IB_QPT_XRC_INI:
2254                 return "IB_QPT_XRC_INI";
2255         case IB_QPT_XRC_TGT:
2256                 return "IB_QPT_XRC_TGT";
2257         case IB_QPT_RAW_PACKET:
2258                 return "IB_QPT_RAW_PACKET";
2259         case MLX5_IB_QPT_REG_UMR:
2260                 return "MLX5_IB_QPT_REG_UMR";
2261         case IB_QPT_DRIVER:
2262                 return "IB_QPT_DRIVER";
2263         case IB_QPT_MAX:
2264         default:
2265                 return "Invalid QP type";
2266         }
2267 }
2268
2269 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2270                                         struct ib_qp_init_attr *attr,
2271                                         struct mlx5_ib_create_qp *ucmd)
2272 {
2273         struct mlx5_ib_qp *qp;
2274         int err = 0;
2275         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2276         void *dctc;
2277
2278         if (!attr->srq || !attr->recv_cq)
2279                 return ERR_PTR(-EINVAL);
2280
2281         err = get_qp_user_index(to_mucontext(pd->uobject->context),
2282                                 ucmd, sizeof(*ucmd), &uidx);
2283         if (err)
2284                 return ERR_PTR(err);
2285
2286         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2287         if (!qp)
2288                 return ERR_PTR(-ENOMEM);
2289
2290         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2291         if (!qp->dct.in) {
2292                 err = -ENOMEM;
2293                 goto err_free;
2294         }
2295
2296         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2297         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2298         qp->qp_sub_type = MLX5_IB_QPT_DCT;
2299         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2300         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2301         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2302         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2303         MLX5_SET(dctc, dctc, user_index, uidx);
2304
2305         qp->state = IB_QPS_RESET;
2306
2307         return &qp->ibqp;
2308 err_free:
2309         kfree(qp);
2310         return ERR_PTR(err);
2311 }
2312
2313 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2314                            struct ib_qp_init_attr *init_attr,
2315                            struct mlx5_ib_create_qp *ucmd,
2316                            struct ib_udata *udata)
2317 {
2318         enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2319         int err;
2320
2321         if (!udata)
2322                 return -EINVAL;
2323
2324         if (udata->inlen < sizeof(*ucmd)) {
2325                 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2326                 return -EINVAL;
2327         }
2328         err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2329         if (err)
2330                 return err;
2331
2332         if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2333                 init_attr->qp_type = MLX5_IB_QPT_DCI;
2334         } else {
2335                 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2336                         init_attr->qp_type = MLX5_IB_QPT_DCT;
2337                 } else {
2338                         mlx5_ib_dbg(dev, "Invalid QP flags\n");
2339                         return -EINVAL;
2340                 }
2341         }
2342
2343         if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2344                 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2345                 return -EOPNOTSUPP;
2346         }
2347
2348         return 0;
2349 }
2350
2351 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2352                                 struct ib_qp_init_attr *verbs_init_attr,
2353                                 struct ib_udata *udata)
2354 {
2355         struct mlx5_ib_dev *dev;
2356         struct mlx5_ib_qp *qp;
2357         u16 xrcdn = 0;
2358         int err;
2359         struct ib_qp_init_attr mlx_init_attr;
2360         struct ib_qp_init_attr *init_attr = verbs_init_attr;
2361
2362         if (pd) {
2363                 dev = to_mdev(pd->device);
2364
2365                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2366                         if (!pd->uobject) {
2367                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2368                                 return ERR_PTR(-EINVAL);
2369                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2370                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2371                                 return ERR_PTR(-EINVAL);
2372                         }
2373                 }
2374         } else {
2375                 /* being cautious here */
2376                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2377                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2378                         pr_warn("%s: no PD for transport %s\n", __func__,
2379                                 ib_qp_type_str(init_attr->qp_type));
2380                         return ERR_PTR(-EINVAL);
2381                 }
2382                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2383         }
2384
2385         if (init_attr->qp_type == IB_QPT_DRIVER) {
2386                 struct mlx5_ib_create_qp ucmd;
2387
2388                 init_attr = &mlx_init_attr;
2389                 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2390                 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2391                 if (err)
2392                         return ERR_PTR(err);
2393
2394                 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2395                         if (init_attr->cap.max_recv_wr ||
2396                             init_attr->cap.max_recv_sge) {
2397                                 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2398                                 return ERR_PTR(-EINVAL);
2399                         }
2400                 } else {
2401                         return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2402                 }
2403         }
2404
2405         switch (init_attr->qp_type) {
2406         case IB_QPT_XRC_TGT:
2407         case IB_QPT_XRC_INI:
2408                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2409                         mlx5_ib_dbg(dev, "XRC not supported\n");
2410                         return ERR_PTR(-ENOSYS);
2411                 }
2412                 init_attr->recv_cq = NULL;
2413                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2414                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2415                         init_attr->send_cq = NULL;
2416                 }
2417
2418                 /* fall through */
2419         case IB_QPT_RAW_PACKET:
2420         case IB_QPT_RC:
2421         case IB_QPT_UC:
2422         case IB_QPT_UD:
2423         case IB_QPT_SMI:
2424         case MLX5_IB_QPT_HW_GSI:
2425         case MLX5_IB_QPT_REG_UMR:
2426         case MLX5_IB_QPT_DCI:
2427                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2428                 if (!qp)
2429                         return ERR_PTR(-ENOMEM);
2430
2431                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2432                 if (err) {
2433                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2434                         kfree(qp);
2435                         return ERR_PTR(err);
2436                 }
2437
2438                 if (is_qp0(init_attr->qp_type))
2439                         qp->ibqp.qp_num = 0;
2440                 else if (is_qp1(init_attr->qp_type))
2441                         qp->ibqp.qp_num = 1;
2442                 else
2443                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2444
2445                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2446                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2447                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2448                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2449
2450                 qp->trans_qp.xrcdn = xrcdn;
2451
2452                 break;
2453
2454         case IB_QPT_GSI:
2455                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2456
2457         case IB_QPT_RAW_IPV6:
2458         case IB_QPT_RAW_ETHERTYPE:
2459         case IB_QPT_MAX:
2460         default:
2461                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2462                             init_attr->qp_type);
2463                 /* Don't support raw QPs */
2464                 return ERR_PTR(-EINVAL);
2465         }
2466
2467         if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2468                 qp->qp_sub_type = init_attr->qp_type;
2469
2470         return &qp->ibqp;
2471 }
2472
2473 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2474 {
2475         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2476
2477         if (mqp->state == IB_QPS_RTR) {
2478                 int err;
2479
2480                 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2481                 if (err) {
2482                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2483                         return err;
2484                 }
2485         }
2486
2487         kfree(mqp->dct.in);
2488         kfree(mqp);
2489         return 0;
2490 }
2491
2492 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2493 {
2494         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2495         struct mlx5_ib_qp *mqp = to_mqp(qp);
2496
2497         if (unlikely(qp->qp_type == IB_QPT_GSI))
2498                 return mlx5_ib_gsi_destroy_qp(qp);
2499
2500         if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2501                 return mlx5_ib_destroy_dct(mqp);
2502
2503         destroy_qp_common(dev, mqp);
2504
2505         kfree(mqp);
2506
2507         return 0;
2508 }
2509
2510 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2511                                    int attr_mask)
2512 {
2513         u32 hw_access_flags = 0;
2514         u8 dest_rd_atomic;
2515         u32 access_flags;
2516
2517         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2518                 dest_rd_atomic = attr->max_dest_rd_atomic;
2519         else
2520                 dest_rd_atomic = qp->trans_qp.resp_depth;
2521
2522         if (attr_mask & IB_QP_ACCESS_FLAGS)
2523                 access_flags = attr->qp_access_flags;
2524         else
2525                 access_flags = qp->trans_qp.atomic_rd_en;
2526
2527         if (!dest_rd_atomic)
2528                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2529
2530         if (access_flags & IB_ACCESS_REMOTE_READ)
2531                 hw_access_flags |= MLX5_QP_BIT_RRE;
2532         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2533                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2534         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2535                 hw_access_flags |= MLX5_QP_BIT_RWE;
2536
2537         return cpu_to_be32(hw_access_flags);
2538 }
2539
2540 enum {
2541         MLX5_PATH_FLAG_FL       = 1 << 0,
2542         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2543         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2544 };
2545
2546 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2547 {
2548         if (rate == IB_RATE_PORT_CURRENT)
2549                 return 0;
2550
2551         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2552                 return -EINVAL;
2553
2554         while (rate != IB_RATE_PORT_CURRENT &&
2555                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2556                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2557                 --rate;
2558
2559         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2560 }
2561
2562 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2563                                       struct mlx5_ib_sq *sq, u8 sl,
2564                                       struct ib_pd *pd)
2565 {
2566         void *in;
2567         void *tisc;
2568         int inlen;
2569         int err;
2570
2571         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2572         in = kvzalloc(inlen, GFP_KERNEL);
2573         if (!in)
2574                 return -ENOMEM;
2575
2576         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2577         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2578
2579         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2580         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2581
2582         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2583
2584         kvfree(in);
2585
2586         return err;
2587 }
2588
2589 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2590                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
2591                                          struct ib_pd *pd)
2592 {
2593         void *in;
2594         void *tisc;
2595         int inlen;
2596         int err;
2597
2598         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2599         in = kvzalloc(inlen, GFP_KERNEL);
2600         if (!in)
2601                 return -ENOMEM;
2602
2603         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2604         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2605
2606         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2607         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2608
2609         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2610
2611         kvfree(in);
2612
2613         return err;
2614 }
2615
2616 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2617                          const struct rdma_ah_attr *ah,
2618                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2619                          u32 path_flags, const struct ib_qp_attr *attr,
2620                          bool alt)
2621 {
2622         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2623         int err;
2624         enum ib_gid_type gid_type;
2625         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2626         u8 sl = rdma_ah_get_sl(ah);
2627
2628         if (attr_mask & IB_QP_PKEY_INDEX)
2629                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2630                                                      attr->pkey_index);
2631
2632         if (ah_flags & IB_AH_GRH) {
2633                 if (grh->sgid_index >=
2634                     dev->mdev->port_caps[port - 1].gid_table_len) {
2635                         pr_err("sgid_index (%u) too large. max is %d\n",
2636                                grh->sgid_index,
2637                                dev->mdev->port_caps[port - 1].gid_table_len);
2638                         return -EINVAL;
2639                 }
2640         }
2641
2642         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2643                 if (!(ah_flags & IB_AH_GRH))
2644                         return -EINVAL;
2645
2646                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2647                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2648                     qp->ibqp.qp_type == IB_QPT_UC ||
2649                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2650                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2651                         path->udp_sport =
2652                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2653                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2654                 gid_type = ah->grh.sgid_attr->gid_type;
2655                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2656                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2657         } else {
2658                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2659                 path->fl_free_ar |=
2660                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2661                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2662                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2663                 if (ah_flags & IB_AH_GRH)
2664                         path->grh_mlid  |= 1 << 7;
2665                 path->dci_cfi_prio_sl = sl & 0xf;
2666         }
2667
2668         if (ah_flags & IB_AH_GRH) {
2669                 path->mgid_index = grh->sgid_index;
2670                 path->hop_limit  = grh->hop_limit;
2671                 path->tclass_flowlabel =
2672                         cpu_to_be32((grh->traffic_class << 20) |
2673                                     (grh->flow_label));
2674                 memcpy(path->rgid, grh->dgid.raw, 16);
2675         }
2676
2677         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2678         if (err < 0)
2679                 return err;
2680         path->static_rate = err;
2681         path->port = port;
2682
2683         if (attr_mask & IB_QP_TIMEOUT)
2684                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2685
2686         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2687                 return modify_raw_packet_eth_prio(dev->mdev,
2688                                                   &qp->raw_packet_qp.sq,
2689                                                   sl & 0xf, qp->ibqp.pd);
2690
2691         return 0;
2692 }
2693
2694 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2695         [MLX5_QP_STATE_INIT] = {
2696                 [MLX5_QP_STATE_INIT] = {
2697                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2698                                           MLX5_QP_OPTPAR_RAE            |
2699                                           MLX5_QP_OPTPAR_RWE            |
2700                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2701                                           MLX5_QP_OPTPAR_PRI_PORT,
2702                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2703                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2704                                           MLX5_QP_OPTPAR_PRI_PORT,
2705                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2706                                           MLX5_QP_OPTPAR_Q_KEY          |
2707                                           MLX5_QP_OPTPAR_PRI_PORT,
2708                 },
2709                 [MLX5_QP_STATE_RTR] = {
2710                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2711                                           MLX5_QP_OPTPAR_RRE            |
2712                                           MLX5_QP_OPTPAR_RAE            |
2713                                           MLX5_QP_OPTPAR_RWE            |
2714                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2715                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2716                                           MLX5_QP_OPTPAR_RWE            |
2717                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2718                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2719                                           MLX5_QP_OPTPAR_Q_KEY,
2720                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2721                                            MLX5_QP_OPTPAR_Q_KEY,
2722                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2723                                           MLX5_QP_OPTPAR_RRE            |
2724                                           MLX5_QP_OPTPAR_RAE            |
2725                                           MLX5_QP_OPTPAR_RWE            |
2726                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2727                 },
2728         },
2729         [MLX5_QP_STATE_RTR] = {
2730                 [MLX5_QP_STATE_RTS] = {
2731                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2732                                           MLX5_QP_OPTPAR_RRE            |
2733                                           MLX5_QP_OPTPAR_RAE            |
2734                                           MLX5_QP_OPTPAR_RWE            |
2735                                           MLX5_QP_OPTPAR_PM_STATE       |
2736                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2737                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2738                                           MLX5_QP_OPTPAR_RWE            |
2739                                           MLX5_QP_OPTPAR_PM_STATE,
2740                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2741                 },
2742         },
2743         [MLX5_QP_STATE_RTS] = {
2744                 [MLX5_QP_STATE_RTS] = {
2745                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2746                                           MLX5_QP_OPTPAR_RAE            |
2747                                           MLX5_QP_OPTPAR_RWE            |
2748                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2749                                           MLX5_QP_OPTPAR_PM_STATE       |
2750                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2751                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2752                                           MLX5_QP_OPTPAR_PM_STATE       |
2753                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2754                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2755                                           MLX5_QP_OPTPAR_SRQN           |
2756                                           MLX5_QP_OPTPAR_CQN_RCV,
2757                 },
2758         },
2759         [MLX5_QP_STATE_SQER] = {
2760                 [MLX5_QP_STATE_RTS] = {
2761                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2762                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2763                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2764                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2765                                            MLX5_QP_OPTPAR_RWE           |
2766                                            MLX5_QP_OPTPAR_RAE           |
2767                                            MLX5_QP_OPTPAR_RRE,
2768                 },
2769         },
2770 };
2771
2772 static int ib_nr_to_mlx5_nr(int ib_mask)
2773 {
2774         switch (ib_mask) {
2775         case IB_QP_STATE:
2776                 return 0;
2777         case IB_QP_CUR_STATE:
2778                 return 0;
2779         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2780                 return 0;
2781         case IB_QP_ACCESS_FLAGS:
2782                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2783                         MLX5_QP_OPTPAR_RAE;
2784         case IB_QP_PKEY_INDEX:
2785                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2786         case IB_QP_PORT:
2787                 return MLX5_QP_OPTPAR_PRI_PORT;
2788         case IB_QP_QKEY:
2789                 return MLX5_QP_OPTPAR_Q_KEY;
2790         case IB_QP_AV:
2791                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2792                         MLX5_QP_OPTPAR_PRI_PORT;
2793         case IB_QP_PATH_MTU:
2794                 return 0;
2795         case IB_QP_TIMEOUT:
2796                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2797         case IB_QP_RETRY_CNT:
2798                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2799         case IB_QP_RNR_RETRY:
2800                 return MLX5_QP_OPTPAR_RNR_RETRY;
2801         case IB_QP_RQ_PSN:
2802                 return 0;
2803         case IB_QP_MAX_QP_RD_ATOMIC:
2804                 return MLX5_QP_OPTPAR_SRA_MAX;
2805         case IB_QP_ALT_PATH:
2806                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2807         case IB_QP_MIN_RNR_TIMER:
2808                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2809         case IB_QP_SQ_PSN:
2810                 return 0;
2811         case IB_QP_MAX_DEST_RD_ATOMIC:
2812                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2813                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2814         case IB_QP_PATH_MIG_STATE:
2815                 return MLX5_QP_OPTPAR_PM_STATE;
2816         case IB_QP_CAP:
2817                 return 0;
2818         case IB_QP_DEST_QPN:
2819                 return 0;
2820         }
2821         return 0;
2822 }
2823
2824 static int ib_mask_to_mlx5_opt(int ib_mask)
2825 {
2826         int result = 0;
2827         int i;
2828
2829         for (i = 0; i < 8 * sizeof(int); i++) {
2830                 if ((1 << i) & ib_mask)
2831                         result |= ib_nr_to_mlx5_nr(1 << i);
2832         }
2833
2834         return result;
2835 }
2836
2837 static int modify_raw_packet_qp_rq(
2838         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
2839         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
2840 {
2841         void *in;
2842         void *rqc;
2843         int inlen;
2844         int err;
2845
2846         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2847         in = kvzalloc(inlen, GFP_KERNEL);
2848         if (!in)
2849                 return -ENOMEM;
2850
2851         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2852         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
2853
2854         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2855         MLX5_SET(rqc, rqc, state, new_state);
2856
2857         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2858                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2859                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2860                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2861                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2862                 } else
2863                         dev_info_once(
2864                                 &dev->ib_dev.dev,
2865                                 "RAW PACKET QP counters are not supported on current FW\n");
2866         }
2867
2868         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2869         if (err)
2870                 goto out;
2871
2872         rq->state = new_state;
2873
2874 out:
2875         kvfree(in);
2876         return err;
2877 }
2878
2879 static int modify_raw_packet_qp_sq(
2880         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
2881         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
2882 {
2883         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2884         struct mlx5_rate_limit old_rl = ibqp->rl;
2885         struct mlx5_rate_limit new_rl = old_rl;
2886         bool new_rate_added = false;
2887         u16 rl_index = 0;
2888         void *in;
2889         void *sqc;
2890         int inlen;
2891         int err;
2892
2893         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2894         in = kvzalloc(inlen, GFP_KERNEL);
2895         if (!in)
2896                 return -ENOMEM;
2897
2898         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
2899         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2900
2901         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2902         MLX5_SET(sqc, sqc, state, new_state);
2903
2904         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2905                 if (new_state != MLX5_SQC_STATE_RDY)
2906                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2907                                 __func__);
2908                 else
2909                         new_rl = raw_qp_param->rl;
2910         }
2911
2912         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2913                 if (new_rl.rate) {
2914                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
2915                         if (err) {
2916                                 pr_err("Failed configuring rate limit(err %d): \
2917                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2918                                        err, new_rl.rate, new_rl.max_burst_sz,
2919                                        new_rl.typical_pkt_sz);
2920
2921                                 goto out;
2922                         }
2923                         new_rate_added = true;
2924                 }
2925
2926                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2927                 /* index 0 means no limit */
2928                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2929         }
2930
2931         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2932         if (err) {
2933                 /* Remove new rate from table if failed */
2934                 if (new_rate_added)
2935                         mlx5_rl_remove_rate(dev, &new_rl);
2936                 goto out;
2937         }
2938
2939         /* Only remove the old rate after new rate was set */
2940         if ((old_rl.rate &&
2941              !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
2942             (new_state != MLX5_SQC_STATE_RDY))
2943                 mlx5_rl_remove_rate(dev, &old_rl);
2944
2945         ibqp->rl = new_rl;
2946         sq->state = new_state;
2947
2948 out:
2949         kvfree(in);
2950         return err;
2951 }
2952
2953 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2954                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2955                                 u8 tx_affinity)
2956 {
2957         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2958         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2959         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2960         int modify_rq = !!qp->rq.wqe_cnt;
2961         int modify_sq = !!qp->sq.wqe_cnt;
2962         int rq_state;
2963         int sq_state;
2964         int err;
2965
2966         switch (raw_qp_param->operation) {
2967         case MLX5_CMD_OP_RST2INIT_QP:
2968                 rq_state = MLX5_RQC_STATE_RDY;
2969                 sq_state = MLX5_SQC_STATE_RDY;
2970                 break;
2971         case MLX5_CMD_OP_2ERR_QP:
2972                 rq_state = MLX5_RQC_STATE_ERR;
2973                 sq_state = MLX5_SQC_STATE_ERR;
2974                 break;
2975         case MLX5_CMD_OP_2RST_QP:
2976                 rq_state = MLX5_RQC_STATE_RST;
2977                 sq_state = MLX5_SQC_STATE_RST;
2978                 break;
2979         case MLX5_CMD_OP_RTR2RTS_QP:
2980         case MLX5_CMD_OP_RTS2RTS_QP:
2981                 if (raw_qp_param->set_mask ==
2982                     MLX5_RAW_QP_RATE_LIMIT) {
2983                         modify_rq = 0;
2984                         sq_state = sq->state;
2985                 } else {
2986                         return raw_qp_param->set_mask ? -EINVAL : 0;
2987                 }
2988                 break;
2989         case MLX5_CMD_OP_INIT2INIT_QP:
2990         case MLX5_CMD_OP_INIT2RTR_QP:
2991                 if (raw_qp_param->set_mask)
2992                         return -EINVAL;
2993                 else
2994                         return 0;
2995         default:
2996                 WARN_ON(1);
2997                 return -EINVAL;
2998         }
2999
3000         if (modify_rq) {
3001                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3002                                                qp->ibqp.pd);
3003                 if (err)
3004                         return err;
3005         }
3006
3007         if (modify_sq) {
3008                 if (tx_affinity) {
3009                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3010                                                             tx_affinity,
3011                                                             qp->ibqp.pd);
3012                         if (err)
3013                                 return err;
3014                 }
3015
3016                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3017                                                raw_qp_param, qp->ibqp.pd);
3018         }
3019
3020         return 0;
3021 }
3022
3023 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3024                                     struct mlx5_ib_pd *pd,
3025                                     struct mlx5_ib_qp_base *qp_base,
3026                                     u8 port_num)
3027 {
3028         struct mlx5_ib_ucontext *ucontext = NULL;
3029         unsigned int tx_port_affinity;
3030
3031         if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
3032                 ucontext = to_mucontext(pd->ibpd.uobject->context);
3033
3034         if (ucontext) {
3035                 tx_port_affinity = (unsigned int)atomic_add_return(
3036                                            1, &ucontext->tx_port_affinity) %
3037                                            MLX5_MAX_PORTS +
3038                                    1;
3039                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3040                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3041         } else {
3042                 tx_port_affinity =
3043                         (unsigned int)atomic_add_return(
3044                                 1, &dev->roce[port_num].tx_port_affinity) %
3045                                 MLX5_MAX_PORTS +
3046                         1;
3047                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3048                                 tx_port_affinity, qp_base->mqp.qpn);
3049         }
3050
3051         return tx_port_affinity;
3052 }
3053
3054 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3055                                const struct ib_qp_attr *attr, int attr_mask,
3056                                enum ib_qp_state cur_state, enum ib_qp_state new_state,
3057                                const struct mlx5_ib_modify_qp *ucmd)
3058 {
3059         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3060                 [MLX5_QP_STATE_RST] = {
3061                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3062                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3063                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3064                 },
3065                 [MLX5_QP_STATE_INIT]  = {
3066                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3067                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3068                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3069                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3070                 },
3071                 [MLX5_QP_STATE_RTR]   = {
3072                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3073                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3074                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3075                 },
3076                 [MLX5_QP_STATE_RTS]   = {
3077                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3078                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3079                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3080                 },
3081                 [MLX5_QP_STATE_SQD] = {
3082                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3083                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3084                 },
3085                 [MLX5_QP_STATE_SQER] = {
3086                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3087                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3088                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3089                 },
3090                 [MLX5_QP_STATE_ERR] = {
3091                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3092                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3093                 }
3094         };
3095
3096         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3097         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3098         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3099         struct mlx5_ib_cq *send_cq, *recv_cq;
3100         struct mlx5_qp_context *context;
3101         struct mlx5_ib_pd *pd;
3102         struct mlx5_ib_port *mibport = NULL;
3103         enum mlx5_qp_state mlx5_cur, mlx5_new;
3104         enum mlx5_qp_optpar optpar;
3105         int mlx5_st;
3106         int err;
3107         u16 op;
3108         u8 tx_affinity = 0;
3109
3110         mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3111                              qp->qp_sub_type : ibqp->qp_type);
3112         if (mlx5_st < 0)
3113                 return -EINVAL;
3114
3115         context = kzalloc(sizeof(*context), GFP_KERNEL);
3116         if (!context)
3117                 return -ENOMEM;
3118
3119         pd = get_pd(qp);
3120         context->flags = cpu_to_be32(mlx5_st << 16);
3121
3122         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3123                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3124         } else {
3125                 switch (attr->path_mig_state) {
3126                 case IB_MIG_MIGRATED:
3127                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3128                         break;
3129                 case IB_MIG_REARM:
3130                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3131                         break;
3132                 case IB_MIG_ARMED:
3133                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3134                         break;
3135                 }
3136         }
3137
3138         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3139                 if ((ibqp->qp_type == IB_QPT_RC) ||
3140                     (ibqp->qp_type == IB_QPT_UD &&
3141                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3142                     (ibqp->qp_type == IB_QPT_UC) ||
3143                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3144                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3145                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3146                         if (mlx5_lag_is_active(dev->mdev)) {
3147                                 u8 p = mlx5_core_native_port_num(dev->mdev);
3148                                 tx_affinity = get_tx_affinity(dev, pd, base, p);
3149                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3150                         }
3151                 }
3152         }
3153
3154         if (is_sqp(ibqp->qp_type)) {
3155                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3156         } else if ((ibqp->qp_type == IB_QPT_UD &&
3157                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3158                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3159                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3160         } else if (attr_mask & IB_QP_PATH_MTU) {
3161                 if (attr->path_mtu < IB_MTU_256 ||
3162                     attr->path_mtu > IB_MTU_4096) {
3163                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3164                         err = -EINVAL;
3165                         goto out;
3166                 }
3167                 context->mtu_msgmax = (attr->path_mtu << 5) |
3168                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3169         }
3170
3171         if (attr_mask & IB_QP_DEST_QPN)
3172                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3173
3174         if (attr_mask & IB_QP_PKEY_INDEX)
3175                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3176
3177         /* todo implement counter_index functionality */
3178
3179         if (is_sqp(ibqp->qp_type))
3180                 context->pri_path.port = qp->port;
3181
3182         if (attr_mask & IB_QP_PORT)
3183                 context->pri_path.port = attr->port_num;
3184
3185         if (attr_mask & IB_QP_AV) {
3186                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3187                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3188                                     attr_mask, 0, attr, false);
3189                 if (err)
3190                         goto out;
3191         }
3192
3193         if (attr_mask & IB_QP_TIMEOUT)
3194                 context->pri_path.ackto_lt |= attr->timeout << 3;
3195
3196         if (attr_mask & IB_QP_ALT_PATH) {
3197                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3198                                     &context->alt_path,
3199                                     attr->alt_port_num,
3200                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3201                                     0, attr, true);
3202                 if (err)
3203                         goto out;
3204         }
3205
3206         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3207                 &send_cq, &recv_cq);
3208
3209         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3210         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3211         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3212         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3213
3214         if (attr_mask & IB_QP_RNR_RETRY)
3215                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3216
3217         if (attr_mask & IB_QP_RETRY_CNT)
3218                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3219
3220         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3221                 if (attr->max_rd_atomic)
3222                         context->params1 |=
3223                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3224         }
3225
3226         if (attr_mask & IB_QP_SQ_PSN)
3227                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3228
3229         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3230                 if (attr->max_dest_rd_atomic)
3231                         context->params2 |=
3232                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3233         }
3234
3235         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3236                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3237
3238         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3239                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3240
3241         if (attr_mask & IB_QP_RQ_PSN)
3242                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3243
3244         if (attr_mask & IB_QP_QKEY)
3245                 context->qkey = cpu_to_be32(attr->qkey);
3246
3247         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3248                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3249
3250         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3251                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3252                                qp->port) - 1;
3253
3254                 /* Underlay port should be used - index 0 function per port */
3255                 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3256                         port_num = 0;
3257
3258                 mibport = &dev->port[port_num];
3259                 context->qp_counter_set_usr_page |=
3260                         cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3261         }
3262
3263         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3264                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3265
3266         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3267                 context->deth_sqpn = cpu_to_be32(1);
3268
3269         mlx5_cur = to_mlx5_state(cur_state);
3270         mlx5_new = to_mlx5_state(new_state);
3271
3272         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3273             !optab[mlx5_cur][mlx5_new]) {
3274                 err = -EINVAL;
3275                 goto out;
3276         }
3277
3278         op = optab[mlx5_cur][mlx5_new];
3279         optpar = ib_mask_to_mlx5_opt(attr_mask);
3280         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3281
3282         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3283             qp->flags & MLX5_IB_QP_UNDERLAY) {
3284                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3285
3286                 raw_qp_param.operation = op;
3287                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3288                         raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3289                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3290                 }
3291
3292                 if (attr_mask & IB_QP_RATE_LIMIT) {
3293                         raw_qp_param.rl.rate = attr->rate_limit;
3294
3295                         if (ucmd->burst_info.max_burst_sz) {
3296                                 if (attr->rate_limit &&
3297                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3298                                         raw_qp_param.rl.max_burst_sz =
3299                                                 ucmd->burst_info.max_burst_sz;
3300                                 } else {
3301                                         err = -EINVAL;
3302                                         goto out;
3303                                 }
3304                         }
3305
3306                         if (ucmd->burst_info.typical_pkt_sz) {
3307                                 if (attr->rate_limit &&
3308                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3309                                         raw_qp_param.rl.typical_pkt_sz =
3310                                                 ucmd->burst_info.typical_pkt_sz;
3311                                 } else {
3312                                         err = -EINVAL;
3313                                         goto out;
3314                                 }
3315                         }
3316
3317                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3318                 }
3319
3320                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3321         } else {
3322                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3323                                           &base->mqp);
3324         }
3325
3326         if (err)
3327                 goto out;
3328
3329         qp->state = new_state;
3330
3331         if (attr_mask & IB_QP_ACCESS_FLAGS)
3332                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3333         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3334                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3335         if (attr_mask & IB_QP_PORT)
3336                 qp->port = attr->port_num;
3337         if (attr_mask & IB_QP_ALT_PATH)
3338                 qp->trans_qp.alt_port = attr->alt_port_num;
3339
3340         /*
3341          * If we moved a kernel QP to RESET, clean up all old CQ
3342          * entries and reinitialize the QP.
3343          */
3344         if (new_state == IB_QPS_RESET &&
3345             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3346                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3347                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3348                 if (send_cq != recv_cq)
3349                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3350
3351                 qp->rq.head = 0;
3352                 qp->rq.tail = 0;
3353                 qp->sq.head = 0;
3354                 qp->sq.tail = 0;
3355                 qp->sq.cur_post = 0;
3356                 qp->sq.last_poll = 0;
3357                 qp->db.db[MLX5_RCV_DBR] = 0;
3358                 qp->db.db[MLX5_SND_DBR] = 0;
3359         }
3360
3361 out:
3362         kfree(context);
3363         return err;
3364 }
3365
3366 static inline bool is_valid_mask(int mask, int req, int opt)
3367 {
3368         if ((mask & req) != req)
3369                 return false;
3370
3371         if (mask & ~(req | opt))
3372                 return false;
3373
3374         return true;
3375 }
3376
3377 /* check valid transition for driver QP types
3378  * for now the only QP type that this function supports is DCI
3379  */
3380 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3381                                 enum ib_qp_attr_mask attr_mask)
3382 {
3383         int req = IB_QP_STATE;
3384         int opt = 0;
3385
3386         if (new_state == IB_QPS_RESET) {
3387                 return is_valid_mask(attr_mask, req, opt);
3388         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3389                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3390                 return is_valid_mask(attr_mask, req, opt);
3391         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3392                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3393                 return is_valid_mask(attr_mask, req, opt);
3394         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3395                 req |= IB_QP_PATH_MTU;
3396                 opt = IB_QP_PKEY_INDEX;
3397                 return is_valid_mask(attr_mask, req, opt);
3398         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3399                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3400                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3401                 opt = IB_QP_MIN_RNR_TIMER;
3402                 return is_valid_mask(attr_mask, req, opt);
3403         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3404                 opt = IB_QP_MIN_RNR_TIMER;
3405                 return is_valid_mask(attr_mask, req, opt);
3406         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3407                 return is_valid_mask(attr_mask, req, opt);
3408         }
3409         return false;
3410 }
3411
3412 /* mlx5_ib_modify_dct: modify a DCT QP
3413  * valid transitions are:
3414  * RESET to INIT: must set access_flags, pkey_index and port
3415  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3416  *                         mtu, gid_index and hop_limit
3417  * Other transitions and attributes are illegal
3418  */
3419 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3420                               int attr_mask, struct ib_udata *udata)
3421 {
3422         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3423         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3424         enum ib_qp_state cur_state, new_state;
3425         int err = 0;
3426         int required = IB_QP_STATE;
3427         void *dctc;
3428
3429         if (!(attr_mask & IB_QP_STATE))
3430                 return -EINVAL;
3431
3432         cur_state = qp->state;
3433         new_state = attr->qp_state;
3434
3435         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3436         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3437                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3438                 if (!is_valid_mask(attr_mask, required, 0))
3439                         return -EINVAL;
3440
3441                 if (attr->port_num == 0 ||
3442                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3443                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3444                                     attr->port_num, dev->num_ports);
3445                         return -EINVAL;
3446                 }
3447                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3448                         MLX5_SET(dctc, dctc, rre, 1);
3449                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3450                         MLX5_SET(dctc, dctc, rwe, 1);
3451                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3452                         if (!mlx5_ib_dc_atomic_is_supported(dev))
3453                                 return -EOPNOTSUPP;
3454                         MLX5_SET(dctc, dctc, rae, 1);
3455                         MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3456                 }
3457                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3458                 MLX5_SET(dctc, dctc, port, attr->port_num);
3459                 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3460
3461         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3462                 struct mlx5_ib_modify_qp_resp resp = {};
3463                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3464                                    sizeof(resp.dctn);
3465
3466                 if (udata->outlen < min_resp_len)
3467                         return -EINVAL;
3468                 resp.response_length = min_resp_len;
3469
3470                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3471                 if (!is_valid_mask(attr_mask, required, 0))
3472                         return -EINVAL;
3473                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3474                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3475                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3476                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3477                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3478                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3479
3480                 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3481                                            MLX5_ST_SZ_BYTES(create_dct_in));
3482                 if (err)
3483                         return err;
3484                 resp.dctn = qp->dct.mdct.mqp.qpn;
3485                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3486                 if (err) {
3487                         mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3488                         return err;
3489                 }
3490         } else {
3491                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3492                 return -EINVAL;
3493         }
3494         if (err)
3495                 qp->state = IB_QPS_ERR;
3496         else
3497                 qp->state = new_state;
3498         return err;
3499 }
3500
3501 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3502                       int attr_mask, struct ib_udata *udata)
3503 {
3504         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3505         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3506         struct mlx5_ib_modify_qp ucmd = {};
3507         enum ib_qp_type qp_type;
3508         enum ib_qp_state cur_state, new_state;
3509         size_t required_cmd_sz;
3510         int err = -EINVAL;
3511         int port;
3512
3513         if (ibqp->rwq_ind_tbl)
3514                 return -ENOSYS;
3515
3516         if (udata && udata->inlen) {
3517                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3518                         sizeof(ucmd.reserved);
3519                 if (udata->inlen < required_cmd_sz)
3520                         return -EINVAL;
3521
3522                 if (udata->inlen > sizeof(ucmd) &&
3523                     !ib_is_udata_cleared(udata, sizeof(ucmd),
3524                                          udata->inlen - sizeof(ucmd)))
3525                         return -EOPNOTSUPP;
3526
3527                 if (ib_copy_from_udata(&ucmd, udata,
3528                                        min(udata->inlen, sizeof(ucmd))))
3529                         return -EFAULT;
3530
3531                 if (ucmd.comp_mask ||
3532                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3533                     memchr_inv(&ucmd.burst_info.reserved, 0,
3534                                sizeof(ucmd.burst_info.reserved)))
3535                         return -EOPNOTSUPP;
3536         }
3537
3538         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3539                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3540
3541         if (ibqp->qp_type == IB_QPT_DRIVER)
3542                 qp_type = qp->qp_sub_type;
3543         else
3544                 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3545                         IB_QPT_GSI : ibqp->qp_type;
3546
3547         if (qp_type == MLX5_IB_QPT_DCT)
3548                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3549
3550         mutex_lock(&qp->mutex);
3551
3552         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3553         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3554
3555         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3556                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3557         }
3558
3559         if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3560                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3561                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3562                                     attr_mask);
3563                         goto out;
3564                 }
3565         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3566                    qp_type != MLX5_IB_QPT_DCI &&
3567                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3568                                        attr_mask)) {
3569                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3570                             cur_state, new_state, ibqp->qp_type, attr_mask);
3571                 goto out;
3572         } else if (qp_type == MLX5_IB_QPT_DCI &&
3573                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3574                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3575                             cur_state, new_state, qp_type, attr_mask);
3576                 goto out;
3577         }
3578
3579         if ((attr_mask & IB_QP_PORT) &&
3580             (attr->port_num == 0 ||
3581              attr->port_num > dev->num_ports)) {
3582                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3583                             attr->port_num, dev->num_ports);
3584                 goto out;
3585         }
3586
3587         if (attr_mask & IB_QP_PKEY_INDEX) {
3588                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3589                 if (attr->pkey_index >=
3590                     dev->mdev->port_caps[port - 1].pkey_table_len) {
3591                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3592                                     attr->pkey_index);
3593                         goto out;
3594                 }
3595         }
3596
3597         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3598             attr->max_rd_atomic >
3599             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3600                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3601                             attr->max_rd_atomic);
3602                 goto out;
3603         }
3604
3605         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3606             attr->max_dest_rd_atomic >
3607             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3608                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3609                             attr->max_dest_rd_atomic);
3610                 goto out;
3611         }
3612
3613         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3614                 err = 0;
3615                 goto out;
3616         }
3617
3618         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3619                                   new_state, &ucmd);
3620
3621 out:
3622         mutex_unlock(&qp->mutex);
3623         return err;
3624 }
3625
3626 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3627 {
3628         struct mlx5_ib_cq *cq;
3629         unsigned cur;
3630
3631         cur = wq->head - wq->tail;
3632         if (likely(cur + nreq < wq->max_post))
3633                 return 0;
3634
3635         cq = to_mcq(ib_cq);
3636         spin_lock(&cq->lock);
3637         cur = wq->head - wq->tail;
3638         spin_unlock(&cq->lock);
3639
3640         return cur + nreq >= wq->max_post;
3641 }
3642
3643 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3644                                           u64 remote_addr, u32 rkey)
3645 {
3646         rseg->raddr    = cpu_to_be64(remote_addr);
3647         rseg->rkey     = cpu_to_be32(rkey);
3648         rseg->reserved = 0;
3649 }
3650
3651 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3652                          const struct ib_send_wr *wr, void *qend,
3653                          struct mlx5_ib_qp *qp, int *size)
3654 {
3655         void *seg = eseg;
3656
3657         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3658
3659         if (wr->send_flags & IB_SEND_IP_CSUM)
3660                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3661                                  MLX5_ETH_WQE_L4_CSUM;
3662
3663         seg += sizeof(struct mlx5_wqe_eth_seg);
3664         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3665
3666         if (wr->opcode == IB_WR_LSO) {
3667                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3668                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3669                 u64 left, leftlen, copysz;
3670                 void *pdata = ud_wr->header;
3671
3672                 left = ud_wr->hlen;
3673                 eseg->mss = cpu_to_be16(ud_wr->mss);
3674                 eseg->inline_hdr.sz = cpu_to_be16(left);
3675
3676                 /*
3677                  * check if there is space till the end of queue, if yes,
3678                  * copy all in one shot, otherwise copy till the end of queue,
3679                  * rollback and than the copy the left
3680                  */
3681                 leftlen = qend - (void *)eseg->inline_hdr.start;
3682                 copysz = min_t(u64, leftlen, left);
3683
3684                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3685
3686                 if (likely(copysz > size_of_inl_hdr_start)) {
3687                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3688                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3689                 }
3690
3691                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3692                         seg = mlx5_get_send_wqe(qp, 0);
3693                         left -= copysz;
3694                         pdata += copysz;
3695                         memcpy(seg, pdata, left);
3696                         seg += ALIGN(left, 16);
3697                         *size += ALIGN(left, 16) / 16;
3698                 }
3699         }
3700
3701         return seg;
3702 }
3703
3704 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3705                              const struct ib_send_wr *wr)
3706 {
3707         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3708         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3709         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3710 }
3711
3712 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3713 {
3714         dseg->byte_count = cpu_to_be32(sg->length);
3715         dseg->lkey       = cpu_to_be32(sg->lkey);
3716         dseg->addr       = cpu_to_be64(sg->addr);
3717 }
3718
3719 static u64 get_xlt_octo(u64 bytes)
3720 {
3721         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3722                MLX5_IB_UMR_OCTOWORD;
3723 }
3724
3725 static __be64 frwr_mkey_mask(void)
3726 {
3727         u64 result;
3728
3729         result = MLX5_MKEY_MASK_LEN             |
3730                 MLX5_MKEY_MASK_PAGE_SIZE        |
3731                 MLX5_MKEY_MASK_START_ADDR       |
3732                 MLX5_MKEY_MASK_EN_RINVAL        |
3733                 MLX5_MKEY_MASK_KEY              |
3734                 MLX5_MKEY_MASK_LR               |
3735                 MLX5_MKEY_MASK_LW               |
3736                 MLX5_MKEY_MASK_RR               |
3737                 MLX5_MKEY_MASK_RW               |
3738                 MLX5_MKEY_MASK_A                |
3739                 MLX5_MKEY_MASK_SMALL_FENCE      |
3740                 MLX5_MKEY_MASK_FREE;
3741
3742         return cpu_to_be64(result);
3743 }
3744
3745 static __be64 sig_mkey_mask(void)
3746 {
3747         u64 result;
3748
3749         result = MLX5_MKEY_MASK_LEN             |
3750                 MLX5_MKEY_MASK_PAGE_SIZE        |
3751                 MLX5_MKEY_MASK_START_ADDR       |
3752                 MLX5_MKEY_MASK_EN_SIGERR        |
3753                 MLX5_MKEY_MASK_EN_RINVAL        |
3754                 MLX5_MKEY_MASK_KEY              |
3755                 MLX5_MKEY_MASK_LR               |
3756                 MLX5_MKEY_MASK_LW               |
3757                 MLX5_MKEY_MASK_RR               |
3758                 MLX5_MKEY_MASK_RW               |
3759                 MLX5_MKEY_MASK_SMALL_FENCE      |
3760                 MLX5_MKEY_MASK_FREE             |
3761                 MLX5_MKEY_MASK_BSF_EN;
3762
3763         return cpu_to_be64(result);
3764 }
3765
3766 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3767                             struct mlx5_ib_mr *mr, bool umr_inline)
3768 {
3769         int size = mr->ndescs * mr->desc_size;
3770
3771         memset(umr, 0, sizeof(*umr));
3772
3773         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3774         if (umr_inline)
3775                 umr->flags |= MLX5_UMR_INLINE;
3776         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3777         umr->mkey_mask = frwr_mkey_mask();
3778 }
3779
3780 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3781 {
3782         memset(umr, 0, sizeof(*umr));
3783         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3784         umr->flags = MLX5_UMR_INLINE;
3785 }
3786
3787 static __be64 get_umr_enable_mr_mask(void)
3788 {
3789         u64 result;
3790
3791         result = MLX5_MKEY_MASK_KEY |
3792                  MLX5_MKEY_MASK_FREE;
3793
3794         return cpu_to_be64(result);
3795 }
3796
3797 static __be64 get_umr_disable_mr_mask(void)
3798 {
3799         u64 result;
3800
3801         result = MLX5_MKEY_MASK_FREE;
3802
3803         return cpu_to_be64(result);
3804 }
3805
3806 static __be64 get_umr_update_translation_mask(void)
3807 {
3808         u64 result;
3809
3810         result = MLX5_MKEY_MASK_LEN |
3811                  MLX5_MKEY_MASK_PAGE_SIZE |
3812                  MLX5_MKEY_MASK_START_ADDR;
3813
3814         return cpu_to_be64(result);
3815 }
3816
3817 static __be64 get_umr_update_access_mask(int atomic)
3818 {
3819         u64 result;
3820
3821         result = MLX5_MKEY_MASK_LR |
3822                  MLX5_MKEY_MASK_LW |
3823                  MLX5_MKEY_MASK_RR |
3824                  MLX5_MKEY_MASK_RW;
3825
3826         if (atomic)
3827                 result |= MLX5_MKEY_MASK_A;
3828
3829         return cpu_to_be64(result);
3830 }
3831
3832 static __be64 get_umr_update_pd_mask(void)
3833 {
3834         u64 result;
3835
3836         result = MLX5_MKEY_MASK_PD;
3837
3838         return cpu_to_be64(result);
3839 }
3840
3841 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
3842 {
3843         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
3844              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
3845             (mask & MLX5_MKEY_MASK_A &&
3846              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
3847                 return -EPERM;
3848         return 0;
3849 }
3850
3851 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
3852                                struct mlx5_wqe_umr_ctrl_seg *umr,
3853                                const struct ib_send_wr *wr, int atomic)
3854 {
3855         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
3856
3857         memset(umr, 0, sizeof(*umr));
3858
3859         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3860                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3861         else
3862                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3863
3864         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3865         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3866                 u64 offset = get_xlt_octo(umrwr->offset);
3867
3868                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3869                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3870                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3871         }
3872         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3873                 umr->mkey_mask |= get_umr_update_translation_mask();
3874         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3875                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3876                 umr->mkey_mask |= get_umr_update_pd_mask();
3877         }
3878         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3879                 umr->mkey_mask |= get_umr_enable_mr_mask();
3880         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3881                 umr->mkey_mask |= get_umr_disable_mr_mask();
3882
3883         if (!wr->num_sge)
3884                 umr->flags |= MLX5_UMR_INLINE;
3885
3886         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
3887 }
3888
3889 static u8 get_umr_flags(int acc)
3890 {
3891         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3892                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3893                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3894                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3895                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3896 }
3897
3898 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3899                              struct mlx5_ib_mr *mr,
3900                              u32 key, int access)
3901 {
3902         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3903
3904         memset(seg, 0, sizeof(*seg));
3905
3906         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3907                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3908         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3909                 /* KLMs take twice the size of MTTs */
3910                 ndescs *= 2;
3911
3912         seg->flags = get_umr_flags(access) | mr->access_mode;
3913         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3914         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3915         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3916         seg->len = cpu_to_be64(mr->ibmr.length);
3917         seg->xlt_oct_size = cpu_to_be32(ndescs);
3918 }
3919
3920 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3921 {
3922         memset(seg, 0, sizeof(*seg));
3923         seg->status = MLX5_MKEY_STATUS_FREE;
3924 }
3925
3926 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
3927                                  const struct ib_send_wr *wr)
3928 {
3929         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
3930
3931         memset(seg, 0, sizeof(*seg));
3932         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3933                 seg->status = MLX5_MKEY_STATUS_FREE;
3934
3935         seg->flags = convert_access(umrwr->access_flags);
3936         if (umrwr->pd)
3937                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3938         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3939             !umrwr->length)
3940                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3941
3942         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3943         seg->len = cpu_to_be64(umrwr->length);
3944         seg->log2_page_size = umrwr->page_shift;
3945         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3946                                        mlx5_mkey_variant(umrwr->mkey));
3947 }
3948
3949 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3950                              struct mlx5_ib_mr *mr,
3951                              struct mlx5_ib_pd *pd)
3952 {
3953         int bcount = mr->desc_size * mr->ndescs;
3954
3955         dseg->addr = cpu_to_be64(mr->desc_map);
3956         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3957         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3958 }
3959
3960 static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp,
3961                                    struct mlx5_ib_mr *mr, int mr_list_size)
3962 {
3963         void *qend = qp->sq.qend;
3964         void *addr = mr->descs;
3965         int copy;
3966
3967         if (unlikely(seg + mr_list_size > qend)) {
3968                 copy = qend - seg;
3969                 memcpy(seg, addr, copy);
3970                 addr += copy;
3971                 mr_list_size -= copy;
3972                 seg = mlx5_get_send_wqe(qp, 0);
3973         }
3974         memcpy(seg, addr, mr_list_size);
3975         seg += mr_list_size;
3976 }
3977
3978 static __be32 send_ieth(const struct ib_send_wr *wr)
3979 {
3980         switch (wr->opcode) {
3981         case IB_WR_SEND_WITH_IMM:
3982         case IB_WR_RDMA_WRITE_WITH_IMM:
3983                 return wr->ex.imm_data;
3984
3985         case IB_WR_SEND_WITH_INV:
3986                 return cpu_to_be32(wr->ex.invalidate_rkey);
3987
3988         default:
3989                 return 0;
3990         }
3991 }
3992
3993 static u8 calc_sig(void *wqe, int size)
3994 {
3995         u8 *p = wqe;
3996         u8 res = 0;
3997         int i;
3998
3999         for (i = 0; i < size; i++)
4000                 res ^= p[i];
4001
4002         return ~res;
4003 }
4004
4005 static u8 wq_sig(void *wqe)
4006 {
4007         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4008 }
4009
4010 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4011                             void *wqe, int *sz)
4012 {
4013         struct mlx5_wqe_inline_seg *seg;
4014         void *qend = qp->sq.qend;
4015         void *addr;
4016         int inl = 0;
4017         int copy;
4018         int len;
4019         int i;
4020
4021         seg = wqe;
4022         wqe += sizeof(*seg);
4023         for (i = 0; i < wr->num_sge; i++) {
4024                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4025                 len  = wr->sg_list[i].length;
4026                 inl += len;
4027
4028                 if (unlikely(inl > qp->max_inline_data))
4029                         return -ENOMEM;
4030
4031                 if (unlikely(wqe + len > qend)) {
4032                         copy = qend - wqe;
4033                         memcpy(wqe, addr, copy);
4034                         addr += copy;
4035                         len -= copy;
4036                         wqe = mlx5_get_send_wqe(qp, 0);
4037                 }
4038                 memcpy(wqe, addr, len);
4039                 wqe += len;
4040         }
4041
4042         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4043
4044         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4045
4046         return 0;
4047 }
4048
4049 static u16 prot_field_size(enum ib_signature_type type)
4050 {
4051         switch (type) {
4052         case IB_SIG_TYPE_T10_DIF:
4053                 return MLX5_DIF_SIZE;
4054         default:
4055                 return 0;
4056         }
4057 }
4058
4059 static u8 bs_selector(int block_size)
4060 {
4061         switch (block_size) {
4062         case 512:           return 0x1;
4063         case 520:           return 0x2;
4064         case 4096:          return 0x3;
4065         case 4160:          return 0x4;
4066         case 1073741824:    return 0x5;
4067         default:            return 0;
4068         }
4069 }
4070
4071 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4072                               struct mlx5_bsf_inl *inl)
4073 {
4074         /* Valid inline section and allow BSF refresh */
4075         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4076                                        MLX5_BSF_REFRESH_DIF);
4077         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4078         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4079         /* repeating block */
4080         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4081         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4082                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
4083
4084         if (domain->sig.dif.ref_remap)
4085                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4086
4087         if (domain->sig.dif.app_escape) {
4088                 if (domain->sig.dif.ref_escape)
4089                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4090                 else
4091                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4092         }
4093
4094         inl->dif_app_bitmask_check =
4095                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4096 }
4097
4098 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4099                         struct ib_sig_attrs *sig_attrs,
4100                         struct mlx5_bsf *bsf, u32 data_size)
4101 {
4102         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4103         struct mlx5_bsf_basic *basic = &bsf->basic;
4104         struct ib_sig_domain *mem = &sig_attrs->mem;
4105         struct ib_sig_domain *wire = &sig_attrs->wire;
4106
4107         memset(bsf, 0, sizeof(*bsf));
4108
4109         /* Basic + Extended + Inline */
4110         basic->bsf_size_sbs = 1 << 7;
4111         /* Input domain check byte mask */
4112         basic->check_byte_mask = sig_attrs->check_mask;
4113         basic->raw_data_size = cpu_to_be32(data_size);
4114
4115         /* Memory domain */
4116         switch (sig_attrs->mem.sig_type) {
4117         case IB_SIG_TYPE_NONE:
4118                 break;
4119         case IB_SIG_TYPE_T10_DIF:
4120                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4121                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4122                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4123                 break;
4124         default:
4125                 return -EINVAL;
4126         }
4127
4128         /* Wire domain */
4129         switch (sig_attrs->wire.sig_type) {
4130         case IB_SIG_TYPE_NONE:
4131                 break;
4132         case IB_SIG_TYPE_T10_DIF:
4133                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4134                     mem->sig_type == wire->sig_type) {
4135                         /* Same block structure */
4136                         basic->bsf_size_sbs |= 1 << 4;
4137                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4138                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4139                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4140                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4141                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4142                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4143                 } else
4144                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4145
4146                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4147                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4148                 break;
4149         default:
4150                 return -EINVAL;
4151         }
4152
4153         return 0;
4154 }
4155
4156 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
4157                                 struct mlx5_ib_qp *qp, void **seg, int *size)
4158 {
4159         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4160         struct ib_mr *sig_mr = wr->sig_mr;
4161         struct mlx5_bsf *bsf;
4162         u32 data_len = wr->wr.sg_list->length;
4163         u32 data_key = wr->wr.sg_list->lkey;
4164         u64 data_va = wr->wr.sg_list->addr;
4165         int ret;
4166         int wqe_size;
4167
4168         if (!wr->prot ||
4169             (data_key == wr->prot->lkey &&
4170              data_va == wr->prot->addr &&
4171              data_len == wr->prot->length)) {
4172                 /**
4173                  * Source domain doesn't contain signature information
4174                  * or data and protection are interleaved in memory.
4175                  * So need construct:
4176                  *                  ------------------
4177                  *                 |     data_klm     |
4178                  *                  ------------------
4179                  *                 |       BSF        |
4180                  *                  ------------------
4181                  **/
4182                 struct mlx5_klm *data_klm = *seg;
4183
4184                 data_klm->bcount = cpu_to_be32(data_len);
4185                 data_klm->key = cpu_to_be32(data_key);
4186                 data_klm->va = cpu_to_be64(data_va);
4187                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4188         } else {
4189                 /**
4190                  * Source domain contains signature information
4191                  * So need construct a strided block format:
4192                  *               ---------------------------
4193                  *              |     stride_block_ctrl     |
4194                  *               ---------------------------
4195                  *              |          data_klm         |
4196                  *               ---------------------------
4197                  *              |          prot_klm         |
4198                  *               ---------------------------
4199                  *              |             BSF           |
4200                  *               ---------------------------
4201                  **/
4202                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4203                 struct mlx5_stride_block_entry *data_sentry;
4204                 struct mlx5_stride_block_entry *prot_sentry;
4205                 u32 prot_key = wr->prot->lkey;
4206                 u64 prot_va = wr->prot->addr;
4207                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4208                 int prot_size;
4209
4210                 sblock_ctrl = *seg;
4211                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4212                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4213
4214                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4215                 if (!prot_size) {
4216                         pr_err("Bad block size given: %u\n", block_size);
4217                         return -EINVAL;
4218                 }
4219                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4220                                                             prot_size);
4221                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4222                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4223                 sblock_ctrl->num_entries = cpu_to_be16(2);
4224
4225                 data_sentry->bcount = cpu_to_be16(block_size);
4226                 data_sentry->key = cpu_to_be32(data_key);
4227                 data_sentry->va = cpu_to_be64(data_va);
4228                 data_sentry->stride = cpu_to_be16(block_size);
4229
4230                 prot_sentry->bcount = cpu_to_be16(prot_size);
4231                 prot_sentry->key = cpu_to_be32(prot_key);
4232                 prot_sentry->va = cpu_to_be64(prot_va);
4233                 prot_sentry->stride = cpu_to_be16(prot_size);
4234
4235                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4236                                  sizeof(*prot_sentry), 64);
4237         }
4238
4239         *seg += wqe_size;
4240         *size += wqe_size / 16;
4241         if (unlikely((*seg == qp->sq.qend)))
4242                 *seg = mlx5_get_send_wqe(qp, 0);
4243
4244         bsf = *seg;
4245         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4246         if (ret)
4247                 return -EINVAL;
4248
4249         *seg += sizeof(*bsf);
4250         *size += sizeof(*bsf) / 16;
4251         if (unlikely((*seg == qp->sq.qend)))
4252                 *seg = mlx5_get_send_wqe(qp, 0);
4253
4254         return 0;
4255 }
4256
4257 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4258                                  const struct ib_sig_handover_wr *wr, u32 size,
4259                                  u32 length, u32 pdn)
4260 {
4261         struct ib_mr *sig_mr = wr->sig_mr;
4262         u32 sig_key = sig_mr->rkey;
4263         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4264
4265         memset(seg, 0, sizeof(*seg));
4266
4267         seg->flags = get_umr_flags(wr->access_flags) |
4268                                    MLX5_MKC_ACCESS_MODE_KLMS;
4269         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4270         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4271                                     MLX5_MKEY_BSF_EN | pdn);
4272         seg->len = cpu_to_be64(length);
4273         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4274         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4275 }
4276
4277 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4278                                 u32 size)
4279 {
4280         memset(umr, 0, sizeof(*umr));
4281
4282         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4283         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4284         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4285         umr->mkey_mask = sig_mkey_mask();
4286 }
4287
4288
4289 static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
4290                           struct mlx5_ib_qp *qp, void **seg, int *size)
4291 {
4292         const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4293         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4294         u32 pdn = get_pd(qp)->pdn;
4295         u32 xlt_size;
4296         int region_len, ret;
4297
4298         if (unlikely(wr->wr.num_sge != 1) ||
4299             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4300             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4301             unlikely(!sig_mr->sig->sig_status_checked))
4302                 return -EINVAL;
4303
4304         /* length of the protected region, data + protection */
4305         region_len = wr->wr.sg_list->length;
4306         if (wr->prot &&
4307             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
4308              wr->prot->addr != wr->wr.sg_list->addr  ||
4309              wr->prot->length != wr->wr.sg_list->length))
4310                 region_len += wr->prot->length;
4311
4312         /**
4313          * KLM octoword size - if protection was provided
4314          * then we use strided block format (3 octowords),
4315          * else we use single KLM (1 octoword)
4316          **/
4317         xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4318
4319         set_sig_umr_segment(*seg, xlt_size);
4320         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4321         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4322         if (unlikely((*seg == qp->sq.qend)))
4323                 *seg = mlx5_get_send_wqe(qp, 0);
4324
4325         set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4326         *seg += sizeof(struct mlx5_mkey_seg);
4327         *size += sizeof(struct mlx5_mkey_seg) / 16;
4328         if (unlikely((*seg == qp->sq.qend)))
4329                 *seg = mlx5_get_send_wqe(qp, 0);
4330
4331         ret = set_sig_data_segment(wr, qp, seg, size);
4332         if (ret)
4333                 return ret;
4334
4335         sig_mr->sig->sig_status_checked = false;
4336         return 0;
4337 }
4338
4339 static int set_psv_wr(struct ib_sig_domain *domain,
4340                       u32 psv_idx, void **seg, int *size)
4341 {
4342         struct mlx5_seg_set_psv *psv_seg = *seg;
4343
4344         memset(psv_seg, 0, sizeof(*psv_seg));
4345         psv_seg->psv_num = cpu_to_be32(psv_idx);
4346         switch (domain->sig_type) {
4347         case IB_SIG_TYPE_NONE:
4348                 break;
4349         case IB_SIG_TYPE_T10_DIF:
4350                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4351                                                      domain->sig.dif.app_tag);
4352                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4353                 break;
4354         default:
4355                 pr_err("Bad signature type (%d) is given.\n",
4356                        domain->sig_type);
4357                 return -EINVAL;
4358         }
4359
4360         *seg += sizeof(*psv_seg);
4361         *size += sizeof(*psv_seg) / 16;
4362
4363         return 0;
4364 }
4365
4366 static int set_reg_wr(struct mlx5_ib_qp *qp,
4367                       const struct ib_reg_wr *wr,
4368                       void **seg, int *size)
4369 {
4370         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4371         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4372         int mr_list_size = mr->ndescs * mr->desc_size;
4373         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4374
4375         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4376                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4377                              "Invalid IB_SEND_INLINE send flag\n");
4378                 return -EINVAL;
4379         }
4380
4381         set_reg_umr_seg(*seg, mr, umr_inline);
4382         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4383         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4384         if (unlikely((*seg == qp->sq.qend)))
4385                 *seg = mlx5_get_send_wqe(qp, 0);
4386
4387         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4388         *seg += sizeof(struct mlx5_mkey_seg);
4389         *size += sizeof(struct mlx5_mkey_seg) / 16;
4390         if (unlikely((*seg == qp->sq.qend)))
4391                 *seg = mlx5_get_send_wqe(qp, 0);
4392
4393         if (umr_inline) {
4394                 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size);
4395                 *size += get_xlt_octo(mr_list_size);
4396         } else {
4397                 set_reg_data_seg(*seg, mr, pd);
4398                 *seg += sizeof(struct mlx5_wqe_data_seg);
4399                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4400         }
4401         return 0;
4402 }
4403
4404 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
4405 {
4406         set_linv_umr_seg(*seg);
4407         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4408         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4409         if (unlikely((*seg == qp->sq.qend)))
4410                 *seg = mlx5_get_send_wqe(qp, 0);
4411         set_linv_mkey_seg(*seg);
4412         *seg += sizeof(struct mlx5_mkey_seg);
4413         *size += sizeof(struct mlx5_mkey_seg) / 16;
4414         if (unlikely((*seg == qp->sq.qend)))
4415                 *seg = mlx5_get_send_wqe(qp, 0);
4416 }
4417
4418 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4419 {
4420         __be32 *p = NULL;
4421         int tidx = idx;
4422         int i, j;
4423
4424         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4425         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4426                 if ((i & 0xf) == 0) {
4427                         void *buf = mlx5_get_send_wqe(qp, tidx);
4428                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4429                         p = buf;
4430                         j = 0;
4431                 }
4432                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4433                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4434                          be32_to_cpu(p[j + 3]));
4435         }
4436 }
4437
4438 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4439                      struct mlx5_wqe_ctrl_seg **ctrl,
4440                      const struct ib_send_wr *wr, unsigned *idx,
4441                      int *size, int nreq, bool send_signaled, bool solicited)
4442 {
4443         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4444                 return -ENOMEM;
4445
4446         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4447         *seg = mlx5_get_send_wqe(qp, *idx);
4448         *ctrl = *seg;
4449         *(uint32_t *)(*seg + 8) = 0;
4450         (*ctrl)->imm = send_ieth(wr);
4451         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4452                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4453                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4454
4455         *seg += sizeof(**ctrl);
4456         *size = sizeof(**ctrl) / 16;
4457
4458         return 0;
4459 }
4460
4461 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4462                      struct mlx5_wqe_ctrl_seg **ctrl,
4463                      const struct ib_send_wr *wr, unsigned *idx,
4464                      int *size, int nreq)
4465 {
4466         return __begin_wqe(qp, seg, ctrl, wr, idx, size, nreq,
4467                            wr->send_flags & IB_SEND_SIGNALED,
4468                            wr->send_flags & IB_SEND_SOLICITED);
4469 }
4470
4471 static void finish_wqe(struct mlx5_ib_qp *qp,
4472                        struct mlx5_wqe_ctrl_seg *ctrl,
4473                        u8 size, unsigned idx, u64 wr_id,
4474                        int nreq, u8 fence, u32 mlx5_opcode)
4475 {
4476         u8 opmod = 0;
4477
4478         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4479                                              mlx5_opcode | ((u32)opmod << 24));
4480         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4481         ctrl->fm_ce_se |= fence;
4482         if (unlikely(qp->wq_sig))
4483                 ctrl->signature = wq_sig(ctrl);
4484
4485         qp->sq.wrid[idx] = wr_id;
4486         qp->sq.w_list[idx].opcode = mlx5_opcode;
4487         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4488         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4489         qp->sq.w_list[idx].next = qp->sq.cur_post;
4490 }
4491
4492 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4493                               const struct ib_send_wr **bad_wr, bool drain)
4494 {
4495         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
4496         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4497         struct mlx5_core_dev *mdev = dev->mdev;
4498         struct mlx5_ib_qp *qp;
4499         struct mlx5_ib_mr *mr;
4500         struct mlx5_wqe_data_seg *dpseg;
4501         struct mlx5_wqe_xrc_seg *xrc;
4502         struct mlx5_bf *bf;
4503         int uninitialized_var(size);
4504         void *qend;
4505         unsigned long flags;
4506         unsigned idx;
4507         int err = 0;
4508         int num_sge;
4509         void *seg;
4510         int nreq;
4511         int i;
4512         u8 next_fence = 0;
4513         u8 fence;
4514
4515         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4516                      !drain)) {
4517                 *bad_wr = wr;
4518                 return -EIO;
4519         }
4520
4521         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4522                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4523
4524         qp = to_mqp(ibqp);
4525         bf = &qp->bf;
4526         qend = qp->sq.qend;
4527
4528         spin_lock_irqsave(&qp->sq.lock, flags);
4529
4530         for (nreq = 0; wr; nreq++, wr = wr->next) {
4531                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4532                         mlx5_ib_warn(dev, "\n");
4533                         err = -EINVAL;
4534                         *bad_wr = wr;
4535                         goto out;
4536                 }
4537
4538                 num_sge = wr->num_sge;
4539                 if (unlikely(num_sge > qp->sq.max_gs)) {
4540                         mlx5_ib_warn(dev, "\n");
4541                         err = -EINVAL;
4542                         *bad_wr = wr;
4543                         goto out;
4544                 }
4545
4546                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4547                 if (err) {
4548                         mlx5_ib_warn(dev, "\n");
4549                         err = -ENOMEM;
4550                         *bad_wr = wr;
4551                         goto out;
4552                 }
4553
4554                 if (wr->opcode == IB_WR_LOCAL_INV ||
4555                     wr->opcode == IB_WR_REG_MR) {
4556                         fence = dev->umr_fence;
4557                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4558                 } else if (wr->send_flags & IB_SEND_FENCE) {
4559                         if (qp->next_fence)
4560                                 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4561                         else
4562                                 fence = MLX5_FENCE_MODE_FENCE;
4563                 } else {
4564                         fence = qp->next_fence;
4565                 }
4566
4567                 switch (ibqp->qp_type) {
4568                 case IB_QPT_XRC_INI:
4569                         xrc = seg;
4570                         seg += sizeof(*xrc);
4571                         size += sizeof(*xrc) / 16;
4572                         /* fall through */
4573                 case IB_QPT_RC:
4574                         switch (wr->opcode) {
4575                         case IB_WR_RDMA_READ:
4576                         case IB_WR_RDMA_WRITE:
4577                         case IB_WR_RDMA_WRITE_WITH_IMM:
4578                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4579                                               rdma_wr(wr)->rkey);
4580                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
4581                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4582                                 break;
4583
4584                         case IB_WR_ATOMIC_CMP_AND_SWP:
4585                         case IB_WR_ATOMIC_FETCH_AND_ADD:
4586                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4587                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4588                                 err = -ENOSYS;
4589                                 *bad_wr = wr;
4590                                 goto out;
4591
4592                         case IB_WR_LOCAL_INV:
4593                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4594                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4595                                 set_linv_wr(qp, &seg, &size);
4596                                 num_sge = 0;
4597                                 break;
4598
4599                         case IB_WR_REG_MR:
4600                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4601                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4602                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4603                                 if (err) {
4604                                         *bad_wr = wr;
4605                                         goto out;
4606                                 }
4607                                 num_sge = 0;
4608                                 break;
4609
4610                         case IB_WR_REG_SIG_MR:
4611                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4612                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4613
4614                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4615                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
4616                                 if (err) {
4617                                         mlx5_ib_warn(dev, "\n");
4618                                         *bad_wr = wr;
4619                                         goto out;
4620                                 }
4621
4622                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4623                                            fence, MLX5_OPCODE_UMR);
4624                                 /*
4625                                  * SET_PSV WQEs are not signaled and solicited
4626                                  * on error
4627                                  */
4628                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4629                                                   &size, nreq, false, true);
4630                                 if (err) {
4631                                         mlx5_ib_warn(dev, "\n");
4632                                         err = -ENOMEM;
4633                                         *bad_wr = wr;
4634                                         goto out;
4635                                 }
4636
4637                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4638                                                  mr->sig->psv_memory.psv_idx, &seg,
4639                                                  &size);
4640                                 if (err) {
4641                                         mlx5_ib_warn(dev, "\n");
4642                                         *bad_wr = wr;
4643                                         goto out;
4644                                 }
4645
4646                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4647                                            fence, MLX5_OPCODE_SET_PSV);
4648                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4649                                                   &size, nreq, false, true);
4650                                 if (err) {
4651                                         mlx5_ib_warn(dev, "\n");
4652                                         err = -ENOMEM;
4653                                         *bad_wr = wr;
4654                                         goto out;
4655                                 }
4656
4657                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4658                                                  mr->sig->psv_wire.psv_idx, &seg,
4659                                                  &size);
4660                                 if (err) {
4661                                         mlx5_ib_warn(dev, "\n");
4662                                         *bad_wr = wr;
4663                                         goto out;
4664                                 }
4665
4666                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4667                                            fence, MLX5_OPCODE_SET_PSV);
4668                                 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4669                                 num_sge = 0;
4670                                 goto skip_psv;
4671
4672                         default:
4673                                 break;
4674                         }
4675                         break;
4676
4677                 case IB_QPT_UC:
4678                         switch (wr->opcode) {
4679                         case IB_WR_RDMA_WRITE:
4680                         case IB_WR_RDMA_WRITE_WITH_IMM:
4681                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4682                                               rdma_wr(wr)->rkey);
4683                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
4684                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4685                                 break;
4686
4687                         default:
4688                                 break;
4689                         }
4690                         break;
4691
4692                 case IB_QPT_SMI:
4693                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4694                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4695                                 err = -EPERM;
4696                                 *bad_wr = wr;
4697                                 goto out;
4698                         }
4699                         /* fall through */
4700                 case MLX5_IB_QPT_HW_GSI:
4701                         set_datagram_seg(seg, wr);
4702                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4703                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4704                         if (unlikely((seg == qend)))
4705                                 seg = mlx5_get_send_wqe(qp, 0);
4706                         break;
4707                 case IB_QPT_UD:
4708                         set_datagram_seg(seg, wr);
4709                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4710                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4711
4712                         if (unlikely((seg == qend)))
4713                                 seg = mlx5_get_send_wqe(qp, 0);
4714
4715                         /* handle qp that supports ud offload */
4716                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4717                                 struct mlx5_wqe_eth_pad *pad;
4718
4719                                 pad = seg;
4720                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4721                                 seg += sizeof(struct mlx5_wqe_eth_pad);
4722                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4723
4724                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
4725
4726                                 if (unlikely((seg == qend)))
4727                                         seg = mlx5_get_send_wqe(qp, 0);
4728                         }
4729                         break;
4730                 case MLX5_IB_QPT_REG_UMR:
4731                         if (wr->opcode != MLX5_IB_WR_UMR) {
4732                                 err = -EINVAL;
4733                                 mlx5_ib_warn(dev, "bad opcode\n");
4734                                 goto out;
4735                         }
4736                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4737                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4738                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4739                         if (unlikely(err))
4740                                 goto out;
4741                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4742                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4743                         if (unlikely((seg == qend)))
4744                                 seg = mlx5_get_send_wqe(qp, 0);
4745                         set_reg_mkey_segment(seg, wr);
4746                         seg += sizeof(struct mlx5_mkey_seg);
4747                         size += sizeof(struct mlx5_mkey_seg) / 16;
4748                         if (unlikely((seg == qend)))
4749                                 seg = mlx5_get_send_wqe(qp, 0);
4750                         break;
4751
4752                 default:
4753                         break;
4754                 }
4755
4756                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4757                         int uninitialized_var(sz);
4758
4759                         err = set_data_inl_seg(qp, wr, seg, &sz);
4760                         if (unlikely(err)) {
4761                                 mlx5_ib_warn(dev, "\n");
4762                                 *bad_wr = wr;
4763                                 goto out;
4764                         }
4765                         size += sz;
4766                 } else {
4767                         dpseg = seg;
4768                         for (i = 0; i < num_sge; i++) {
4769                                 if (unlikely(dpseg == qend)) {
4770                                         seg = mlx5_get_send_wqe(qp, 0);
4771                                         dpseg = seg;
4772                                 }
4773                                 if (likely(wr->sg_list[i].length)) {
4774                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
4775                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
4776                                         dpseg++;
4777                                 }
4778                         }
4779                 }
4780
4781                 qp->next_fence = next_fence;
4782                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4783                            mlx5_ib_opcode[wr->opcode]);
4784 skip_psv:
4785                 if (0)
4786                         dump_wqe(qp, idx, size);
4787         }
4788
4789 out:
4790         if (likely(nreq)) {
4791                 qp->sq.head += nreq;
4792
4793                 /* Make sure that descriptors are written before
4794                  * updating doorbell record and ringing the doorbell
4795                  */
4796                 wmb();
4797
4798                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4799
4800                 /* Make sure doorbell record is visible to the HCA before
4801                  * we hit doorbell */
4802                 wmb();
4803
4804                 /* currently we support only regular doorbells */
4805                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4806                 /* Make sure doorbells don't leak out of SQ spinlock
4807                  * and reach the HCA out of order.
4808                  */
4809                 mmiowb();
4810                 bf->offset ^= bf->buf_size;
4811         }
4812
4813         spin_unlock_irqrestore(&qp->sq.lock, flags);
4814
4815         return err;
4816 }
4817
4818 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4819                       const struct ib_send_wr **bad_wr)
4820 {
4821         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
4822 }
4823
4824 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4825 {
4826         sig->signature = calc_sig(sig, size);
4827 }
4828
4829 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4830                       const struct ib_recv_wr **bad_wr, bool drain)
4831 {
4832         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4833         struct mlx5_wqe_data_seg *scat;
4834         struct mlx5_rwqe_sig *sig;
4835         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4836         struct mlx5_core_dev *mdev = dev->mdev;
4837         unsigned long flags;
4838         int err = 0;
4839         int nreq;
4840         int ind;
4841         int i;
4842
4843         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4844                      !drain)) {
4845                 *bad_wr = wr;
4846                 return -EIO;
4847         }
4848
4849         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4850                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4851
4852         spin_lock_irqsave(&qp->rq.lock, flags);
4853
4854         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4855
4856         for (nreq = 0; wr; nreq++, wr = wr->next) {
4857                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4858                         err = -ENOMEM;
4859                         *bad_wr = wr;
4860                         goto out;
4861                 }
4862
4863                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4864                         err = -EINVAL;
4865                         *bad_wr = wr;
4866                         goto out;
4867                 }
4868
4869                 scat = get_recv_wqe(qp, ind);
4870                 if (qp->wq_sig)
4871                         scat++;
4872
4873                 for (i = 0; i < wr->num_sge; i++)
4874                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4875
4876                 if (i < qp->rq.max_gs) {
4877                         scat[i].byte_count = 0;
4878                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4879                         scat[i].addr       = 0;
4880                 }
4881
4882                 if (qp->wq_sig) {
4883                         sig = (struct mlx5_rwqe_sig *)scat;
4884                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4885                 }
4886
4887                 qp->rq.wrid[ind] = wr->wr_id;
4888
4889                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4890         }
4891
4892 out:
4893         if (likely(nreq)) {
4894                 qp->rq.head += nreq;
4895
4896                 /* Make sure that descriptors are written before
4897                  * doorbell record.
4898                  */
4899                 wmb();
4900
4901                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4902         }
4903
4904         spin_unlock_irqrestore(&qp->rq.lock, flags);
4905
4906         return err;
4907 }
4908
4909 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4910                       const struct ib_recv_wr **bad_wr)
4911 {
4912         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
4913 }
4914
4915 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4916 {
4917         switch (mlx5_state) {
4918         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4919         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4920         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4921         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4922         case MLX5_QP_STATE_SQ_DRAINING:
4923         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4924         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4925         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4926         default:                     return -1;
4927         }
4928 }
4929
4930 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4931 {
4932         switch (mlx5_mig_state) {
4933         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4934         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4935         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4936         default: return -1;
4937         }
4938 }
4939
4940 static int to_ib_qp_access_flags(int mlx5_flags)
4941 {
4942         int ib_flags = 0;
4943
4944         if (mlx5_flags & MLX5_QP_BIT_RRE)
4945                 ib_flags |= IB_ACCESS_REMOTE_READ;
4946         if (mlx5_flags & MLX5_QP_BIT_RWE)
4947                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4948         if (mlx5_flags & MLX5_QP_BIT_RAE)
4949                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4950
4951         return ib_flags;
4952 }
4953
4954 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4955                             struct rdma_ah_attr *ah_attr,
4956                             struct mlx5_qp_path *path)
4957 {
4958
4959         memset(ah_attr, 0, sizeof(*ah_attr));
4960
4961         if (!path->port || path->port > ibdev->num_ports)
4962                 return;
4963
4964         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4965
4966         rdma_ah_set_port_num(ah_attr, path->port);
4967         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4968
4969         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4970         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4971         rdma_ah_set_static_rate(ah_attr,
4972                                 path->static_rate ? path->static_rate - 5 : 0);
4973         if (path->grh_mlid & (1 << 7)) {
4974                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4975
4976                 rdma_ah_set_grh(ah_attr, NULL,
4977                                 tc_fl & 0xfffff,
4978                                 path->mgid_index,
4979                                 path->hop_limit,
4980                                 (tc_fl >> 20) & 0xff);
4981                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4982         }
4983 }
4984
4985 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4986                                         struct mlx5_ib_sq *sq,
4987                                         u8 *sq_state)
4988 {
4989         int err;
4990
4991         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4992         if (err)
4993                 goto out;
4994         sq->state = *sq_state;
4995
4996 out:
4997         return err;
4998 }
4999
5000 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5001                                         struct mlx5_ib_rq *rq,
5002                                         u8 *rq_state)
5003 {
5004         void *out;
5005         void *rqc;
5006         int inlen;
5007         int err;
5008
5009         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5010         out = kvzalloc(inlen, GFP_KERNEL);
5011         if (!out)
5012                 return -ENOMEM;
5013
5014         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5015         if (err)
5016                 goto out;
5017
5018         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5019         *rq_state = MLX5_GET(rqc, rqc, state);
5020         rq->state = *rq_state;
5021
5022 out:
5023         kvfree(out);
5024         return err;
5025 }
5026
5027 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5028                                   struct mlx5_ib_qp *qp, u8 *qp_state)
5029 {
5030         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5031                 [MLX5_RQC_STATE_RST] = {
5032                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5033                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5034                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
5035                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
5036                 },
5037                 [MLX5_RQC_STATE_RDY] = {
5038                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5039                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5040                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
5041                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
5042                 },
5043                 [MLX5_RQC_STATE_ERR] = {
5044                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5045                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5046                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
5047                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
5048                 },
5049                 [MLX5_RQ_STATE_NA] = {
5050                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5051                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5052                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
5053                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
5054                 },
5055         };
5056
5057         *qp_state = sqrq_trans[rq_state][sq_state];
5058
5059         if (*qp_state == MLX5_QP_STATE_BAD) {
5060                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5061                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5062                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5063                 return -EINVAL;
5064         }
5065
5066         if (*qp_state == MLX5_QP_STATE)
5067                 *qp_state = qp->state;
5068
5069         return 0;
5070 }
5071
5072 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5073                                      struct mlx5_ib_qp *qp,
5074                                      u8 *raw_packet_qp_state)
5075 {
5076         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5077         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5078         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5079         int err;
5080         u8 sq_state = MLX5_SQ_STATE_NA;
5081         u8 rq_state = MLX5_RQ_STATE_NA;
5082
5083         if (qp->sq.wqe_cnt) {
5084                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5085                 if (err)
5086                         return err;
5087         }
5088
5089         if (qp->rq.wqe_cnt) {
5090                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5091                 if (err)
5092                         return err;
5093         }
5094
5095         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5096                                       raw_packet_qp_state);
5097 }
5098
5099 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5100                          struct ib_qp_attr *qp_attr)
5101 {
5102         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5103         struct mlx5_qp_context *context;
5104         int mlx5_state;
5105         u32 *outb;
5106         int err = 0;
5107
5108         outb = kzalloc(outlen, GFP_KERNEL);
5109         if (!outb)
5110                 return -ENOMEM;
5111
5112         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
5113                                  outlen);
5114         if (err)
5115                 goto out;
5116
5117         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5118         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5119
5120         mlx5_state = be32_to_cpu(context->flags) >> 28;
5121
5122         qp->state                    = to_ib_qp_state(mlx5_state);
5123         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5124         qp_attr->path_mig_state      =
5125                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5126         qp_attr->qkey                = be32_to_cpu(context->qkey);
5127         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5128         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5129         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5130         qp_attr->qp_access_flags     =
5131                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5132
5133         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5134                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5135                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5136                 qp_attr->alt_pkey_index =
5137                         be16_to_cpu(context->alt_path.pkey_index);
5138                 qp_attr->alt_port_num   =
5139                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5140         }
5141
5142         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5143         qp_attr->port_num = context->pri_path.port;
5144
5145         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5146         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5147
5148         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5149
5150         qp_attr->max_dest_rd_atomic =
5151                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5152         qp_attr->min_rnr_timer      =
5153                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5154         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5155         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5156         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5157         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5158
5159 out:
5160         kfree(outb);
5161         return err;
5162 }
5163
5164 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5165                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5166                                 struct ib_qp_init_attr *qp_init_attr)
5167 {
5168         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5169         u32 *out;
5170         u32 access_flags = 0;
5171         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5172         void *dctc;
5173         int err;
5174         int supported_mask = IB_QP_STATE |
5175                              IB_QP_ACCESS_FLAGS |
5176                              IB_QP_PORT |
5177                              IB_QP_MIN_RNR_TIMER |
5178                              IB_QP_AV |
5179                              IB_QP_PATH_MTU |
5180                              IB_QP_PKEY_INDEX;
5181
5182         if (qp_attr_mask & ~supported_mask)
5183                 return -EINVAL;
5184         if (mqp->state != IB_QPS_RTR)
5185                 return -EINVAL;
5186
5187         out = kzalloc(outlen, GFP_KERNEL);
5188         if (!out)
5189                 return -ENOMEM;
5190
5191         err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5192         if (err)
5193                 goto out;
5194
5195         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5196
5197         if (qp_attr_mask & IB_QP_STATE)
5198                 qp_attr->qp_state = IB_QPS_RTR;
5199
5200         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5201                 if (MLX5_GET(dctc, dctc, rre))
5202                         access_flags |= IB_ACCESS_REMOTE_READ;
5203                 if (MLX5_GET(dctc, dctc, rwe))
5204                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5205                 if (MLX5_GET(dctc, dctc, rae))
5206                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5207                 qp_attr->qp_access_flags = access_flags;
5208         }
5209
5210         if (qp_attr_mask & IB_QP_PORT)
5211                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5212         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5213                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5214         if (qp_attr_mask & IB_QP_AV) {
5215                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5216                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5217                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5218                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5219         }
5220         if (qp_attr_mask & IB_QP_PATH_MTU)
5221                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5222         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5223                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5224 out:
5225         kfree(out);
5226         return err;
5227 }
5228
5229 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5230                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5231 {
5232         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5233         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5234         int err = 0;
5235         u8 raw_packet_qp_state;
5236
5237         if (ibqp->rwq_ind_tbl)
5238                 return -ENOSYS;
5239
5240         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5241                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5242                                             qp_init_attr);
5243
5244         /* Not all of output fields are applicable, make sure to zero them */
5245         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5246         memset(qp_attr, 0, sizeof(*qp_attr));
5247
5248         if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5249                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5250                                             qp_attr_mask, qp_init_attr);
5251
5252         mutex_lock(&qp->mutex);
5253
5254         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5255             qp->flags & MLX5_IB_QP_UNDERLAY) {
5256                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5257                 if (err)
5258                         goto out;
5259                 qp->state = raw_packet_qp_state;
5260                 qp_attr->port_num = 1;
5261         } else {
5262                 err = query_qp_attr(dev, qp, qp_attr);
5263                 if (err)
5264                         goto out;
5265         }
5266
5267         qp_attr->qp_state            = qp->state;
5268         qp_attr->cur_qp_state        = qp_attr->qp_state;
5269         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5270         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5271
5272         if (!ibqp->uobject) {
5273                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5274                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5275                 qp_init_attr->qp_context = ibqp->qp_context;
5276         } else {
5277                 qp_attr->cap.max_send_wr  = 0;
5278                 qp_attr->cap.max_send_sge = 0;
5279         }
5280
5281         qp_init_attr->qp_type = ibqp->qp_type;
5282         qp_init_attr->recv_cq = ibqp->recv_cq;
5283         qp_init_attr->send_cq = ibqp->send_cq;
5284         qp_init_attr->srq = ibqp->srq;
5285         qp_attr->cap.max_inline_data = qp->max_inline_data;
5286
5287         qp_init_attr->cap            = qp_attr->cap;
5288
5289         qp_init_attr->create_flags = 0;
5290         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5291                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5292
5293         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5294                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5295         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5296                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5297         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5298                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5299         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5300                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5301
5302         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5303                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5304
5305 out:
5306         mutex_unlock(&qp->mutex);
5307         return err;
5308 }
5309
5310 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5311                                           struct ib_ucontext *context,
5312                                           struct ib_udata *udata)
5313 {
5314         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5315         struct mlx5_ib_xrcd *xrcd;
5316         int err;
5317         u16 uid;
5318
5319         if (!MLX5_CAP_GEN(dev->mdev, xrc))
5320                 return ERR_PTR(-ENOSYS);
5321
5322         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5323         if (!xrcd)
5324                 return ERR_PTR(-ENOMEM);
5325
5326         uid = context ? to_mucontext(context)->devx_uid : 0;
5327         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, uid);
5328         if (err) {
5329                 kfree(xrcd);
5330                 return ERR_PTR(-ENOMEM);
5331         }
5332
5333         xrcd->uid = uid;
5334         return &xrcd->ibxrcd;
5335 }
5336
5337 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5338 {
5339         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5340         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5341         u16 uid =  to_mxrcd(xrcd)->uid;
5342         int err;
5343
5344         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, uid);
5345         if (err)
5346                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5347
5348         kfree(xrcd);
5349         return 0;
5350 }
5351
5352 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5353 {
5354         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5355         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5356         struct ib_event event;
5357
5358         if (rwq->ibwq.event_handler) {
5359                 event.device     = rwq->ibwq.device;
5360                 event.element.wq = &rwq->ibwq;
5361                 switch (type) {
5362                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5363                         event.event = IB_EVENT_WQ_FATAL;
5364                         break;
5365                 default:
5366                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5367                         return;
5368                 }
5369
5370                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5371         }
5372 }
5373
5374 static int set_delay_drop(struct mlx5_ib_dev *dev)
5375 {
5376         int err = 0;
5377
5378         mutex_lock(&dev->delay_drop.lock);
5379         if (dev->delay_drop.activate)
5380                 goto out;
5381
5382         err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5383         if (err)
5384                 goto out;
5385
5386         dev->delay_drop.activate = true;
5387 out:
5388         mutex_unlock(&dev->delay_drop.lock);
5389
5390         if (!err)
5391                 atomic_inc(&dev->delay_drop.rqs_cnt);
5392         return err;
5393 }
5394
5395 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5396                       struct ib_wq_init_attr *init_attr)
5397 {
5398         struct mlx5_ib_dev *dev;
5399         int has_net_offloads;
5400         __be64 *rq_pas0;
5401         void *in;
5402         void *rqc;
5403         void *wq;
5404         int inlen;
5405         int err;
5406
5407         dev = to_mdev(pd->device);
5408
5409         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5410         in = kvzalloc(inlen, GFP_KERNEL);
5411         if (!in)
5412                 return -ENOMEM;
5413
5414         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5415         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5416         MLX5_SET(rqc,  rqc, mem_rq_type,
5417                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5418         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5419         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5420         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
5421         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
5422         wq = MLX5_ADDR_OF(rqc, rqc, wq);
5423         MLX5_SET(wq, wq, wq_type,
5424                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5425                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5426         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5427                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5428                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5429                         err = -EOPNOTSUPP;
5430                         goto out;
5431                 } else {
5432                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5433                 }
5434         }
5435         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5436         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5437                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5438                 MLX5_SET(wq, wq, log_wqe_stride_size,
5439                          rwq->single_stride_log_num_of_bytes -
5440                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5441                 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5442                          MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5443         }
5444         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5445         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5446         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5447         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5448         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5449         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5450         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5451         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5452                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5453                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5454                         err = -EOPNOTSUPP;
5455                         goto out;
5456                 }
5457         } else {
5458                 MLX5_SET(rqc, rqc, vsd, 1);
5459         }
5460         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5461                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5462                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5463                         err = -EOPNOTSUPP;
5464                         goto out;
5465                 }
5466                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5467         }
5468         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5469                 if (!(dev->ib_dev.attrs.raw_packet_caps &
5470                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
5471                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5472                         err = -EOPNOTSUPP;
5473                         goto out;
5474                 }
5475                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5476         }
5477         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5478         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5479         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5480         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5481                 err = set_delay_drop(dev);
5482                 if (err) {
5483                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5484                                      err);
5485                         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5486                 } else {
5487                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5488                 }
5489         }
5490 out:
5491         kvfree(in);
5492         return err;
5493 }
5494
5495 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5496                             struct ib_wq_init_attr *wq_init_attr,
5497                             struct mlx5_ib_create_wq *ucmd,
5498                             struct mlx5_ib_rwq *rwq)
5499 {
5500         /* Sanity check RQ size before proceeding */
5501         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5502                 return -EINVAL;
5503
5504         if (!ucmd->rq_wqe_count)
5505                 return -EINVAL;
5506
5507         rwq->wqe_count = ucmd->rq_wqe_count;
5508         rwq->wqe_shift = ucmd->rq_wqe_shift;
5509         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5510                 return -EINVAL;
5511
5512         rwq->log_rq_stride = rwq->wqe_shift;
5513         rwq->log_rq_size = ilog2(rwq->wqe_count);
5514         return 0;
5515 }
5516
5517 static int prepare_user_rq(struct ib_pd *pd,
5518                            struct ib_wq_init_attr *init_attr,
5519                            struct ib_udata *udata,
5520                            struct mlx5_ib_rwq *rwq)
5521 {
5522         struct mlx5_ib_dev *dev = to_mdev(pd->device);
5523         struct mlx5_ib_create_wq ucmd = {};
5524         int err;
5525         size_t required_cmd_sz;
5526
5527         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5528                 + sizeof(ucmd.single_stride_log_num_of_bytes);
5529         if (udata->inlen < required_cmd_sz) {
5530                 mlx5_ib_dbg(dev, "invalid inlen\n");
5531                 return -EINVAL;
5532         }
5533
5534         if (udata->inlen > sizeof(ucmd) &&
5535             !ib_is_udata_cleared(udata, sizeof(ucmd),
5536                                  udata->inlen - sizeof(ucmd))) {
5537                 mlx5_ib_dbg(dev, "inlen is not supported\n");
5538                 return -EOPNOTSUPP;
5539         }
5540
5541         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5542                 mlx5_ib_dbg(dev, "copy failed\n");
5543                 return -EFAULT;
5544         }
5545
5546         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5547                 mlx5_ib_dbg(dev, "invalid comp mask\n");
5548                 return -EOPNOTSUPP;
5549         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5550                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5551                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5552                         return -EOPNOTSUPP;
5553                 }
5554                 if ((ucmd.single_stride_log_num_of_bytes <
5555                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5556                     (ucmd.single_stride_log_num_of_bytes >
5557                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5558                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5559                                     ucmd.single_stride_log_num_of_bytes,
5560                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5561                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5562                         return -EINVAL;
5563                 }
5564                 if ((ucmd.single_wqe_log_num_of_strides >
5565                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5566                      (ucmd.single_wqe_log_num_of_strides <
5567                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5568                         mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5569                                     ucmd.single_wqe_log_num_of_strides,
5570                                     MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5571                                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5572                         return -EINVAL;
5573                 }
5574                 rwq->single_stride_log_num_of_bytes =
5575                         ucmd.single_stride_log_num_of_bytes;
5576                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5577                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5578                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5579         }
5580
5581         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5582         if (err) {
5583                 mlx5_ib_dbg(dev, "err %d\n", err);
5584                 return err;
5585         }
5586
5587         err = create_user_rq(dev, pd, rwq, &ucmd);
5588         if (err) {
5589                 mlx5_ib_dbg(dev, "err %d\n", err);
5590                 return err;
5591         }
5592
5593         rwq->user_index = ucmd.user_index;
5594         return 0;
5595 }
5596
5597 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5598                                 struct ib_wq_init_attr *init_attr,
5599                                 struct ib_udata *udata)
5600 {
5601         struct mlx5_ib_dev *dev;
5602         struct mlx5_ib_rwq *rwq;
5603         struct mlx5_ib_create_wq_resp resp = {};
5604         size_t min_resp_len;
5605         int err;
5606
5607         if (!udata)
5608                 return ERR_PTR(-ENOSYS);
5609
5610         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5611         if (udata->outlen && udata->outlen < min_resp_len)
5612                 return ERR_PTR(-EINVAL);
5613
5614         dev = to_mdev(pd->device);
5615         switch (init_attr->wq_type) {
5616         case IB_WQT_RQ:
5617                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5618                 if (!rwq)
5619                         return ERR_PTR(-ENOMEM);
5620                 err = prepare_user_rq(pd, init_attr, udata, rwq);
5621                 if (err)
5622                         goto err;
5623                 err = create_rq(rwq, pd, init_attr);
5624                 if (err)
5625                         goto err_user_rq;
5626                 break;
5627         default:
5628                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5629                             init_attr->wq_type);
5630                 return ERR_PTR(-EINVAL);
5631         }
5632
5633         rwq->ibwq.wq_num = rwq->core_qp.qpn;
5634         rwq->ibwq.state = IB_WQS_RESET;
5635         if (udata->outlen) {
5636                 resp.response_length = offsetof(typeof(resp), response_length) +
5637                                 sizeof(resp.response_length);
5638                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5639                 if (err)
5640                         goto err_copy;
5641         }
5642
5643         rwq->core_qp.event = mlx5_ib_wq_event;
5644         rwq->ibwq.event_handler = init_attr->event_handler;
5645         return &rwq->ibwq;
5646
5647 err_copy:
5648         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5649 err_user_rq:
5650         destroy_user_rq(dev, pd, rwq);
5651 err:
5652         kfree(rwq);
5653         return ERR_PTR(err);
5654 }
5655
5656 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5657 {
5658         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5659         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5660
5661         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5662         destroy_user_rq(dev, wq->pd, rwq);
5663         kfree(rwq);
5664
5665         return 0;
5666 }
5667
5668 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5669                                                       struct ib_rwq_ind_table_init_attr *init_attr,
5670                                                       struct ib_udata *udata)
5671 {
5672         struct mlx5_ib_dev *dev = to_mdev(device);
5673         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5674         int sz = 1 << init_attr->log_ind_tbl_size;
5675         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5676         size_t min_resp_len;
5677         int inlen;
5678         int err;
5679         int i;
5680         u32 *in;
5681         void *rqtc;
5682
5683         if (udata->inlen > 0 &&
5684             !ib_is_udata_cleared(udata, 0,
5685                                  udata->inlen))
5686                 return ERR_PTR(-EOPNOTSUPP);
5687
5688         if (init_attr->log_ind_tbl_size >
5689             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5690                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5691                             init_attr->log_ind_tbl_size,
5692                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5693                 return ERR_PTR(-EINVAL);
5694         }
5695
5696         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5697         if (udata->outlen && udata->outlen < min_resp_len)
5698                 return ERR_PTR(-EINVAL);
5699
5700         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5701         if (!rwq_ind_tbl)
5702                 return ERR_PTR(-ENOMEM);
5703
5704         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5705         in = kvzalloc(inlen, GFP_KERNEL);
5706         if (!in) {
5707                 err = -ENOMEM;
5708                 goto err;
5709         }
5710
5711         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5712
5713         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5714         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5715
5716         for (i = 0; i < sz; i++)
5717                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5718
5719         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5720         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5721
5722         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5723         kvfree(in);
5724
5725         if (err)
5726                 goto err;
5727
5728         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5729         if (udata->outlen) {
5730                 resp.response_length = offsetof(typeof(resp), response_length) +
5731                                         sizeof(resp.response_length);
5732                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5733                 if (err)
5734                         goto err_copy;
5735         }
5736
5737         return &rwq_ind_tbl->ib_rwq_ind_tbl;
5738
5739 err_copy:
5740         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5741 err:
5742         kfree(rwq_ind_tbl);
5743         return ERR_PTR(err);
5744 }
5745
5746 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5747 {
5748         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5749         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5750
5751         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5752
5753         kfree(rwq_ind_tbl);
5754         return 0;
5755 }
5756
5757 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5758                       u32 wq_attr_mask, struct ib_udata *udata)
5759 {
5760         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5761         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5762         struct mlx5_ib_modify_wq ucmd = {};
5763         size_t required_cmd_sz;
5764         int curr_wq_state;
5765         int wq_state;
5766         int inlen;
5767         int err;
5768         void *rqc;
5769         void *in;
5770
5771         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5772         if (udata->inlen < required_cmd_sz)
5773                 return -EINVAL;
5774
5775         if (udata->inlen > sizeof(ucmd) &&
5776             !ib_is_udata_cleared(udata, sizeof(ucmd),
5777                                  udata->inlen - sizeof(ucmd)))
5778                 return -EOPNOTSUPP;
5779
5780         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5781                 return -EFAULT;
5782
5783         if (ucmd.comp_mask || ucmd.reserved)
5784                 return -EOPNOTSUPP;
5785
5786         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5787         in = kvzalloc(inlen, GFP_KERNEL);
5788         if (!in)
5789                 return -ENOMEM;
5790
5791         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5792
5793         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5794                 wq_attr->curr_wq_state : wq->state;
5795         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5796                 wq_attr->wq_state : curr_wq_state;
5797         if (curr_wq_state == IB_WQS_ERR)
5798                 curr_wq_state = MLX5_RQC_STATE_ERR;
5799         if (wq_state == IB_WQS_ERR)
5800                 wq_state = MLX5_RQC_STATE_ERR;
5801         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5802         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
5803         MLX5_SET(rqc, rqc, state, wq_state);
5804
5805         if (wq_attr_mask & IB_WQ_FLAGS) {
5806                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5807                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5808                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5809                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
5810                                             "supported\n");
5811                                 err = -EOPNOTSUPP;
5812                                 goto out;
5813                         }
5814                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5815                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5816                         MLX5_SET(rqc, rqc, vsd,
5817                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5818                 }
5819
5820                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5821                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5822                         err = -EOPNOTSUPP;
5823                         goto out;
5824                 }
5825         }
5826
5827         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5828                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5829                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5830                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5831                         MLX5_SET(rqc, rqc, counter_set_id,
5832                                  dev->port->cnts.set_id);
5833                 } else
5834                         dev_info_once(
5835                                 &dev->ib_dev.dev,
5836                                 "Receive WQ counters are not supported on current FW\n");
5837         }
5838
5839         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5840         if (!err)
5841                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5842
5843 out:
5844         kvfree(in);
5845         return err;
5846 }
5847
5848 struct mlx5_ib_drain_cqe {
5849         struct ib_cqe cqe;
5850         struct completion done;
5851 };
5852
5853 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5854 {
5855         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5856                                                      struct mlx5_ib_drain_cqe,
5857                                                      cqe);
5858
5859         complete(&cqe->done);
5860 }
5861
5862 /* This function returns only once the drained WR was completed */
5863 static void handle_drain_completion(struct ib_cq *cq,
5864                                     struct mlx5_ib_drain_cqe *sdrain,
5865                                     struct mlx5_ib_dev *dev)
5866 {
5867         struct mlx5_core_dev *mdev = dev->mdev;
5868
5869         if (cq->poll_ctx == IB_POLL_DIRECT) {
5870                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5871                         ib_process_cq_direct(cq, -1);
5872                 return;
5873         }
5874
5875         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5876                 struct mlx5_ib_cq *mcq = to_mcq(cq);
5877                 bool triggered = false;
5878                 unsigned long flags;
5879
5880                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5881                 /* Make sure that the CQ handler won't run if wasn't run yet */
5882                 if (!mcq->mcq.reset_notify_added)
5883                         mcq->mcq.reset_notify_added = 1;
5884                 else
5885                         triggered = true;
5886                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5887
5888                 if (triggered) {
5889                         /* Wait for any scheduled/running task to be ended */
5890                         switch (cq->poll_ctx) {
5891                         case IB_POLL_SOFTIRQ:
5892                                 irq_poll_disable(&cq->iop);
5893                                 irq_poll_enable(&cq->iop);
5894                                 break;
5895                         case IB_POLL_WORKQUEUE:
5896                                 cancel_work_sync(&cq->work);
5897                                 break;
5898                         default:
5899                                 WARN_ON_ONCE(1);
5900                         }
5901                 }
5902
5903                 /* Run the CQ handler - this makes sure that the drain WR will
5904                  * be processed if wasn't processed yet.
5905                  */
5906                 mcq->mcq.comp(&mcq->mcq);
5907         }
5908
5909         wait_for_completion(&sdrain->done);
5910 }
5911
5912 void mlx5_ib_drain_sq(struct ib_qp *qp)
5913 {
5914         struct ib_cq *cq = qp->send_cq;
5915         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5916         struct mlx5_ib_drain_cqe sdrain;
5917         const struct ib_send_wr *bad_swr;
5918         struct ib_rdma_wr swr = {
5919                 .wr = {
5920                         .next = NULL,
5921                         { .wr_cqe       = &sdrain.cqe, },
5922                         .opcode = IB_WR_RDMA_WRITE,
5923                 },
5924         };
5925         int ret;
5926         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5927         struct mlx5_core_dev *mdev = dev->mdev;
5928
5929         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5930         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5931                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5932                 return;
5933         }
5934
5935         sdrain.cqe.done = mlx5_ib_drain_qp_done;
5936         init_completion(&sdrain.done);
5937
5938         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
5939         if (ret) {
5940                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5941                 return;
5942         }
5943
5944         handle_drain_completion(cq, &sdrain, dev);
5945 }
5946
5947 void mlx5_ib_drain_rq(struct ib_qp *qp)
5948 {
5949         struct ib_cq *cq = qp->recv_cq;
5950         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5951         struct mlx5_ib_drain_cqe rdrain;
5952         struct ib_recv_wr rwr = {};
5953         const struct ib_recv_wr *bad_rwr;
5954         int ret;
5955         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5956         struct mlx5_core_dev *mdev = dev->mdev;
5957
5958         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5959         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5960                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5961                 return;
5962         }
5963
5964         rwr.wr_cqe = &rdrain.cqe;
5965         rdrain.cqe.done = mlx5_ib_drain_qp_done;
5966         init_completion(&rdrain.done);
5967
5968         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
5969         if (ret) {
5970                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
5971                 return;
5972         }
5973
5974         handle_drain_completion(cq, &rdrain, dev);
5975 }