drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <linux/mlx5/fs.h>
  38 #include "mlx5_ib.h"
  39 #include "ib_rep.h"
  40 #include "cmd.h"
  41
  42 /* not supported currently */
  43 static int wq_signature;
  44
  45 enum {
  46         MLX5_IB_ACK_REQ_FREQ    = 8,
  47 };
  48
  49 enum {
  50         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  51         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  52         MLX5_IB_LINK_TYPE_IB            = 0,
  53         MLX5_IB_LINK_TYPE_ETH           = 1
  54 };
  55
  56 enum {
  57         MLX5_IB_SQ_STRIDE       = 6,
  58         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  59 };
  60
  61 static const u32 mlx5_ib_opcode[] = {
  62         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  63         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  64         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  65         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  66         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  67         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  68         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  69         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  70         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  71         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  72         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  73         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  74         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  75         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  76 };
  77
  78 struct mlx5_wqe_eth_pad {
  79         u8 rsvd0[16];
  80 };
  81
  82 enum raw_qp_set_mask_map {
  83         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  84         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  85 };
  86
  87 struct mlx5_modify_raw_qp_param {
  88         u16 operation;
  89
  90         u32 set_mask; /* raw_qp_set_mask_map */
  91
  92         struct mlx5_rate_limit rl;
  93
  94         u8 rq_q_ctr_id;
  95 };
  96
  97 static void get_cqs(enum ib_qp_type qp_type,
  98                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  99                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
 100
 101 static int is_qp0(enum ib_qp_type qp_type)
 102 {
 103         return qp_type == IB_QPT_SMI;
 104 }
 105
 106 static int is_sqp(enum ib_qp_type qp_type)
 107 {
 108         return is_qp0(qp_type) || is_qp1(qp_type);
 109 }
 110
 111 /**
 112  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 113  *
 114  * @qp: QP to copy from.
 115  * @send: copy from the send queue when non-zero, use the receive queue
 116  *        otherwise.
 117  * @wqe_index:  index to start copying from. For send work queues, the
 118  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 119  *              For receive work queue, it is the number of work queue
 120  *              element in the queue.
 121  * @buffer: destination buffer.
 122  * @length: maximum number of bytes to copy.
 123  *
 124  * Copies at least a single WQE, but may copy more data.
 125  *
 126  * Return: the number of bytes copied, or an error code.
 127  */
 128 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 129                           void *buffer, u32 length,
 130                           struct mlx5_ib_qp_base *base)
 131 {
 132         struct ib_device *ibdev = qp->ibqp.device;
 133         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 134         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 135         size_t offset;
 136         size_t wq_end;
 137         struct ib_umem *umem = base->ubuffer.umem;
 138         u32 first_copy_length;
 139         int wqe_length;
 140         int ret;
 141
 142         if (wq->wqe_cnt == 0) {
 143                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 144                             qp->ibqp.qp_type);
 145                 return -EINVAL;
 146         }
 147
 148         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 149         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 150
 151         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 152                 return -EINVAL;
 153
 154         if (offset > umem->length ||
 155             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 156                 return -EINVAL;
 157
 158         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 159         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 160         if (ret)
 161                 return ret;
 162
 163         if (send) {
 164                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 165                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 166
 167                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 168         } else {
 169                 wqe_length = 1 << wq->wqe_shift;
 170         }
 171
 172         if (wqe_length <= first_copy_length)
 173                 return first_copy_length;
 174
 175         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 176                                 wqe_length - first_copy_length);
 177         if (ret)
 178                 return ret;
 179
 180         return wqe_length;
 181 }
 182
 183 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 184 {
 185         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 186         struct ib_event event;
 187
 188         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 189                 /* This event is only valid for trans_qps */
 190                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 191         }
 192
 193         if (ibqp->event_handler) {
 194                 event.device     = ibqp->device;
 195                 event.element.qp = ibqp;
 196                 switch (type) {
 197                 case MLX5_EVENT_TYPE_PATH_MIG:
 198                         event.event = IB_EVENT_PATH_MIG;
 199                         break;
 200                 case MLX5_EVENT_TYPE_COMM_EST:
 201                         event.event = IB_EVENT_COMM_EST;
 202                         break;
 203                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 204                         event.event = IB_EVENT_SQ_DRAINED;
 205                         break;
 206                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 207                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 208                         break;
 209                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 210                         event.event = IB_EVENT_QP_FATAL;
 211                         break;
 212                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 213                         event.event = IB_EVENT_PATH_MIG_ERR;
 214                         break;
 215                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 216                         event.event = IB_EVENT_QP_REQ_ERR;
 217                         break;
 218                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 219                         event.event = IB_EVENT_QP_ACCESS_ERR;
 220                         break;
 221                 default:
 222                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 223                         return;
 224                 }
 225
 226                 ibqp->event_handler(&event, ibqp->qp_context);
 227         }
 228 }
 229
 230 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 231                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 232 {
 233         int wqe_size;
 234         int wq_size;
 235
 236         /* Sanity check RQ size before proceeding */
 237         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 238                 return -EINVAL;
 239
 240         if (!has_rq) {
 241                 qp->rq.max_gs = 0;
 242                 qp->rq.wqe_cnt = 0;
 243                 qp->rq.wqe_shift = 0;
 244                 cap->max_recv_wr = 0;
 245                 cap->max_recv_sge = 0;
 246         } else {
 247                 if (ucmd) {
 248                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 249                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 250                                 return -EINVAL;
 251                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 252                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 253                                 return -EINVAL;
 254                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 255                         qp->rq.max_post = qp->rq.wqe_cnt;
 256                 } else {
 257                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 258                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 259                         wqe_size = roundup_pow_of_two(wqe_size);
 260                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 261                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 262                         qp->rq.wqe_cnt = wq_size / wqe_size;
 263                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 264                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 265                                             wqe_size,
 266                                             MLX5_CAP_GEN(dev->mdev,
 267                                                          max_wqe_sz_rq));
 268                                 return -EINVAL;
 269                         }
 270                         qp->rq.wqe_shift = ilog2(wqe_size);
 271                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 272                         qp->rq.max_post = qp->rq.wqe_cnt;
 273                 }
 274         }
 275
 276         return 0;
 277 }
 278
 279 static int sq_overhead(struct ib_qp_init_attr *attr)
 280 {
 281         int size = 0;
 282
 283         switch (attr->qp_type) {
 284         case IB_QPT_XRC_INI:
 285                 size += sizeof(struct mlx5_wqe_xrc_seg);
 286                 /* fall through */
 287         case IB_QPT_RC:
 288                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 289                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 290                             sizeof(struct mlx5_wqe_raddr_seg),
 291                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 292                             sizeof(struct mlx5_mkey_seg) +
 293                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 294                             MLX5_IB_UMR_OCTOWORD);
 295                 break;
 296
 297         case IB_QPT_XRC_TGT:
 298                 return 0;
 299
 300         case IB_QPT_UC:
 301                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 302                         max(sizeof(struct mlx5_wqe_raddr_seg),
 303                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 304                             sizeof(struct mlx5_mkey_seg));
 305                 break;
 306
 307         case IB_QPT_UD:
 308                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 309                         size += sizeof(struct mlx5_wqe_eth_pad) +
 310                                 sizeof(struct mlx5_wqe_eth_seg);
 311                 /* fall through */
 312         case IB_QPT_SMI:
 313         case MLX5_IB_QPT_HW_GSI:
 314                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 315                         sizeof(struct mlx5_wqe_datagram_seg);
 316                 break;
 317
 318         case MLX5_IB_QPT_REG_UMR:
 319                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 320                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 321                         sizeof(struct mlx5_mkey_seg);
 322                 break;
 323
 324         default:
 325                 return -EINVAL;
 326         }
 327
 328         return size;
 329 }
 330
 331 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 332 {
 333         int inl_size = 0;
 334         int size;
 335
 336         size = sq_overhead(attr);
 337         if (size < 0)
 338                 return size;
 339
 340         if (attr->cap.max_inline_data) {
 341                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 342                         attr->cap.max_inline_data;
 343         }
 344
 345         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 346         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 347             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 348                         return MLX5_SIG_WQE_SIZE;
 349         else
 350                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 351 }
 352
 353 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 354 {
 355         int max_sge;
 356
 357         if (attr->qp_type == IB_QPT_RC)
 358                 max_sge = (min_t(int, wqe_size, 512) -
 359                            sizeof(struct mlx5_wqe_ctrl_seg) -
 360                            sizeof(struct mlx5_wqe_raddr_seg)) /
 361                         sizeof(struct mlx5_wqe_data_seg);
 362         else if (attr->qp_type == IB_QPT_XRC_INI)
 363                 max_sge = (min_t(int, wqe_size, 512) -
 364                            sizeof(struct mlx5_wqe_ctrl_seg) -
 365                            sizeof(struct mlx5_wqe_xrc_seg) -
 366                            sizeof(struct mlx5_wqe_raddr_seg)) /
 367                         sizeof(struct mlx5_wqe_data_seg);
 368         else
 369                 max_sge = (wqe_size - sq_overhead(attr)) /
 370                         sizeof(struct mlx5_wqe_data_seg);
 371
 372         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 373                      sizeof(struct mlx5_wqe_data_seg));
 374 }
 375
 376 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 377                         struct mlx5_ib_qp *qp)
 378 {
 379         int wqe_size;
 380         int wq_size;
 381
 382         if (!attr->cap.max_send_wr)
 383                 return 0;
 384
 385         wqe_size = calc_send_wqe(attr);
 386         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 387         if (wqe_size < 0)
 388                 return wqe_size;
 389
 390         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 391                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 392                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 393                 return -EINVAL;
 394         }
 395
 396         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 397                               sizeof(struct mlx5_wqe_inline_seg);
 398         attr->cap.max_inline_data = qp->max_inline_data;
 399
 400         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 401                 qp->signature_en = true;
 402
 403         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 404         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 405         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 406                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 407                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 408                             qp->sq.wqe_cnt,
 409                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 410                 return -ENOMEM;
 411         }
 412         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 413         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 414         if (qp->sq.max_gs < attr->cap.max_send_sge)
 415                 return -ENOMEM;
 416
 417         attr->cap.max_send_sge = qp->sq.max_gs;
 418         qp->sq.max_post = wq_size / wqe_size;
 419         attr->cap.max_send_wr = qp->sq.max_post;
 420
 421         return wq_size;
 422 }
 423
 424 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 425                             struct mlx5_ib_qp *qp,
 426                             struct mlx5_ib_create_qp *ucmd,
 427                             struct mlx5_ib_qp_base *base,
 428                             struct ib_qp_init_attr *attr)
 429 {
 430         int desc_sz = 1 << qp->sq.wqe_shift;
 431
 432         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 433                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 434                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 435                 return -EINVAL;
 436         }
 437
 438         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 439                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 440                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 441                 return -EINVAL;
 442         }
 443
 444         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 445
 446         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 447                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 448                              qp->sq.wqe_cnt,
 449                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 450                 return -EINVAL;
 451         }
 452
 453         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 454             qp->flags & MLX5_IB_QP_UNDERLAY) {
 455                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 456                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 457         } else {
 458                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 459                                          (qp->sq.wqe_cnt << 6);
 460         }
 461
 462         return 0;
 463 }
 464
 465 static int qp_has_rq(struct ib_qp_init_attr *attr)
 466 {
 467         if (attr->qp_type == IB_QPT_XRC_INI ||
 468             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 469             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 470             !attr->cap.max_recv_wr)
 471                 return 0;
 472
 473         return 1;
 474 }
 475
 476 enum {
 477         /* this is the first blue flame register in the array of bfregs assigned
 478          * to a processes. Since we do not use it for blue flame but rather
 479          * regular 64 bit doorbells, we do not need a lock for maintaiing
 480          * "odd/even" order
 481          */
 482         NUM_NON_BLUE_FLAME_BFREGS = 1,
 483 };
 484
 485 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 486 {
 487         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 488 }
 489
 490 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 491                          struct mlx5_bfreg_info *bfregi)
 492 {
 493         int n;
 494
 495         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 496             NUM_NON_BLUE_FLAME_BFREGS;
 497
 498         return n >= 0 ? n : 0;
 499 }
 500
 501 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 502                            struct mlx5_bfreg_info *bfregi)
 503 {
 504         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 505 }
 506
 507 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 508                           struct mlx5_bfreg_info *bfregi)
 509 {
 510         int med;
 511
 512         med = num_med_bfreg(dev, bfregi);
 513         return ++med;
 514 }
 515
 516 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 517                                   struct mlx5_bfreg_info *bfregi)
 518 {
 519         int i;
 520
 521         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 522                 if (!bfregi->count[i]) {
 523                         bfregi->count[i]++;
 524                         return i;
 525                 }
 526         }
 527
 528         return -ENOMEM;
 529 }
 530
 531 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 532                                  struct mlx5_bfreg_info *bfregi)
 533 {
 534         int minidx = first_med_bfreg(dev, bfregi);
 535         int i;
 536
 537         if (minidx < 0)
 538                 return minidx;
 539
 540         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 541                 if (bfregi->count[i] < bfregi->count[minidx])
 542                         minidx = i;
 543                 if (!bfregi->count[minidx])
 544                         break;
 545         }
 546
 547         bfregi->count[minidx]++;
 548         return minidx;
 549 }
 550
 551 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 552                        struct mlx5_bfreg_info *bfregi)
 553 {
 554         int bfregn = -ENOMEM;
 555
 556         mutex_lock(&bfregi->lock);
 557         if (bfregi->ver >= 2) {
 558                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 559                 if (bfregn < 0)
 560                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 561         }
 562
 563         if (bfregn < 0) {
 564                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 565                 bfregn = 0;
 566                 bfregi->count[bfregn]++;
 567         }
 568         mutex_unlock(&bfregi->lock);
 569
 570         return bfregn;
 571 }
 572
 573 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 574 {
 575         mutex_lock(&bfregi->lock);
 576         bfregi->count[bfregn]--;
 577         mutex_unlock(&bfregi->lock);
 578 }
 579
 580 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 581 {
 582         switch (state) {
 583         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 584         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 585         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 586         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 587         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 588         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 589         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 590         default:                return -1;
 591         }
 592 }
 593
 594 static int to_mlx5_st(enum ib_qp_type type)
 595 {
 596         switch (type) {
 597         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 598         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 599         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 600         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 601         case IB_QPT_XRC_INI:
 602         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 603         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 604         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 605         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 606         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 607         case IB_QPT_RAW_PACKET:
 608         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 609         case IB_QPT_MAX:
 610         default:                return -EINVAL;
 611         }
 612 }
 613
 614 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 615                              struct mlx5_ib_cq *recv_cq);
 616 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 617                                struct mlx5_ib_cq *recv_cq);
 618
 619 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 620                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 621                         bool dyn_bfreg)
 622 {
 623         unsigned int bfregs_per_sys_page;
 624         u32 index_of_sys_page;
 625         u32 offset;
 626
 627         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 628                                 MLX5_NON_FP_BFREGS_PER_UAR;
 629         index_of_sys_page = bfregn / bfregs_per_sys_page;
 630
 631         if (dyn_bfreg) {
 632                 index_of_sys_page += bfregi->num_static_sys_pages;
 633
 634                 if (index_of_sys_page >= bfregi->num_sys_pages)
 635                         return -EINVAL;
 636
 637                 if (bfregn > bfregi->num_dyn_bfregs ||
 638                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 639                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 640                         return -EINVAL;
 641                 }
 642         }
 643
 644         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 645         return bfregi->sys_pages[index_of_sys_page] + offset;
 646 }
 647
 648 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 649                             struct ib_pd *pd,
 650                             unsigned long addr, size_t size,
 651                             struct ib_umem **umem,
 652                             int *npages, int *page_shift, int *ncont,
 653                             u32 *offset)
 654 {
 655         int err;
 656
 657         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 658         if (IS_ERR(*umem)) {
 659                 mlx5_ib_dbg(dev, "umem_get failed\n");
 660                 return PTR_ERR(*umem);
 661         }
 662
 663         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 664
 665         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 666         if (err) {
 667                 mlx5_ib_warn(dev, "bad offset\n");
 668                 goto err_umem;
 669         }
 670
 671         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 672                     addr, size, *npages, *page_shift, *ncont, *offset);
 673
 674         return 0;
 675
 676 err_umem:
 677         ib_umem_release(*umem);
 678         *umem = NULL;
 679
 680         return err;
 681 }
 682
 683 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 684                             struct mlx5_ib_rwq *rwq)
 685 {
 686         struct mlx5_ib_ucontext *context;
 687
 688         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 689                 atomic_dec(&dev->delay_drop.rqs_cnt);
 690
 691         context = to_mucontext(pd->uobject->context);
 692         mlx5_ib_db_unmap_user(context, &rwq->db);
 693         if (rwq->umem)
 694                 ib_umem_release(rwq->umem);
 695 }
 696
 697 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 698                           struct mlx5_ib_rwq *rwq,
 699                           struct mlx5_ib_create_wq *ucmd)
 700 {
 701         struct mlx5_ib_ucontext *context;
 702         int page_shift = 0;
 703         int npages;
 704         u32 offset = 0;
 705         int ncont = 0;
 706         int err;
 707
 708         if (!ucmd->buf_addr)
 709                 return -EINVAL;
 710
 711         context = to_mucontext(pd->uobject->context);
 712         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 713                                rwq->buf_size, 0, 0);
 714         if (IS_ERR(rwq->umem)) {
 715                 mlx5_ib_dbg(dev, "umem_get failed\n");
 716                 err = PTR_ERR(rwq->umem);
 717                 return err;
 718         }
 719
 720         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 721                            &ncont, NULL);
 722         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 723                                      &rwq->rq_page_offset);
 724         if (err) {
 725                 mlx5_ib_warn(dev, "bad offset\n");
 726                 goto err_umem;
 727         }
 728
 729         rwq->rq_num_pas = ncont;
 730         rwq->page_shift = page_shift;
 731         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 732         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 733
 734         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 735                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 736                     npages, page_shift, ncont, offset);
 737
 738         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 739         if (err) {
 740                 mlx5_ib_dbg(dev, "map failed\n");
 741                 goto err_umem;
 742         }
 743
 744         rwq->create_type = MLX5_WQ_USER;
 745         return 0;
 746
 747 err_umem:
 748         ib_umem_release(rwq->umem);
 749         return err;
 750 }
 751
 752 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 753                          struct mlx5_bfreg_info *bfregi, int bfregn)
 754 {
 755         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 756                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 757 }
 758
 759 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 760                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 761                           struct ib_qp_init_attr *attr,
 762                           u32 **in,
 763                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 764                           struct mlx5_ib_qp_base *base)
 765 {
 766         struct mlx5_ib_ucontext *context;
 767         struct mlx5_ib_create_qp ucmd;
 768         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 769         int page_shift = 0;
 770         int uar_index = 0;
 771         int npages;
 772         u32 offset = 0;
 773         int bfregn;
 774         int ncont = 0;
 775         __be64 *pas;
 776         void *qpc;
 777         int err;
 778         u16 uid;
 779
 780         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 781         if (err) {
 782                 mlx5_ib_dbg(dev, "copy failed\n");
 783                 return err;
 784         }
 785
 786         context = to_mucontext(pd->uobject->context);
 787         if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
 788                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 789                                                 ucmd.bfreg_index, true);
 790                 if (uar_index < 0)
 791                         return uar_index;
 792
 793                 bfregn = MLX5_IB_INVALID_BFREG;
 794         } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
 795                 /*
 796                  * TBD: should come from the verbs when we have the API
 797                  */
 798                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 799                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
 800         }
 801         else {
 802                 bfregn = alloc_bfreg(dev, &context->bfregi);
 803                 if (bfregn < 0)
 804                         return bfregn;
 805         }
 806
 807         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 808         if (bfregn != MLX5_IB_INVALID_BFREG)
 809                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 810                                                 false);
 811
 812         qp->rq.offset = 0;
 813         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 814         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 815
 816         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 817         if (err)
 818                 goto err_bfreg;
 819
 820         if (ucmd.buf_addr && ubuffer->buf_size) {
 821                 ubuffer->buf_addr = ucmd.buf_addr;
 822                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 823                                        ubuffer->buf_size,
 824                                        &ubuffer->umem, &npages, &page_shift,
 825                                        &ncont, &offset);
 826                 if (err)
 827                         goto err_bfreg;
 828         } else {
 829                 ubuffer->umem = NULL;
 830         }
 831
 832         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 833                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 834         *in = kvzalloc(*inlen, GFP_KERNEL);
 835         if (!*in) {
 836                 err = -ENOMEM;
 837                 goto err_umem;
 838         }
 839
 840         uid = (attr->qp_type != IB_QPT_XRC_TGT) ? to_mpd(pd)->uid : 0;
 841         MLX5_SET(create_qp_in, *in, uid, uid);
 842         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 843         if (ubuffer->umem)
 844                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 845
 846         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 847
 848         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 849         MLX5_SET(qpc, qpc, page_offset, offset);
 850
 851         MLX5_SET(qpc, qpc, uar_page, uar_index);
 852         if (bfregn != MLX5_IB_INVALID_BFREG)
 853                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 854         else
 855                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
 856         qp->bfregn = bfregn;
 857
 858         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 859         if (err) {
 860                 mlx5_ib_dbg(dev, "map failed\n");
 861                 goto err_free;
 862         }
 863
 864         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
 865         if (err) {
 866                 mlx5_ib_dbg(dev, "copy failed\n");
 867                 goto err_unmap;
 868         }
 869         qp->create_type = MLX5_QP_USER;
 870
 871         return 0;
 872
 873 err_unmap:
 874         mlx5_ib_db_unmap_user(context, &qp->db);
 875
 876 err_free:
 877         kvfree(*in);
 878
 879 err_umem:
 880         if (ubuffer->umem)
 881                 ib_umem_release(ubuffer->umem);
 882
 883 err_bfreg:
 884         if (bfregn != MLX5_IB_INVALID_BFREG)
 885                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
 886         return err;
 887 }
 888
 889 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 890                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
 891 {
 892         struct mlx5_ib_ucontext *context;
 893
 894         context = to_mucontext(pd->uobject->context);
 895         mlx5_ib_db_unmap_user(context, &qp->db);
 896         if (base->ubuffer.umem)
 897                 ib_umem_release(base->ubuffer.umem);
 898
 899         /*
 900          * Free only the BFREGs which are handled by the kernel.
 901          * BFREGs of UARs allocated dynamically are handled by user.
 902          */
 903         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
 904                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
 905 }
 906
 907 /* get_sq_edge - Get the next nearby edge.
 908  *
 909  * An 'edge' is defined as the first following address after the end
 910  * of the fragment or the SQ. Accordingly, during the WQE construction
 911  * which repetitively increases the pointer to write the next data, it
 912  * simply should check if it gets to an edge.
 913  *
 914  * @sq - SQ buffer.
 915  * @idx - Stride index in the SQ buffer.
 916  *
 917  * Return:
 918  *      The new edge.
 919  */
 920 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
 921 {
 922         void *fragment_end;
 923
 924         fragment_end = mlx5_frag_buf_get_wqe
 925                 (&sq->fbc,
 926                  mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
 927
 928         return fragment_end + MLX5_SEND_WQE_BB;
 929 }
 930
 931 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 932                             struct ib_qp_init_attr *init_attr,
 933                             struct mlx5_ib_qp *qp,
 934                             u32 **in, int *inlen,
 935                             struct mlx5_ib_qp_base *base)
 936 {
 937         int uar_index;
 938         void *qpc;
 939         int err;
 940
 941         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 942                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 943                                         IB_QP_CREATE_IPOIB_UD_LSO |
 944                                         IB_QP_CREATE_NETIF_QP |
 945                                         mlx5_ib_create_qp_sqpn_qp1()))
 946                 return -EINVAL;
 947
 948         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 949                 qp->bf.bfreg = &dev->fp_bfreg;
 950         else
 951                 qp->bf.bfreg = &dev->bfreg;
 952
 953         /* We need to divide by two since each register is comprised of
 954          * two buffers of identical size, namely odd and even
 955          */
 956         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
 957         uar_index = qp->bf.bfreg->index;
 958
 959         err = calc_sq_size(dev, init_attr, qp);
 960         if (err < 0) {
 961                 mlx5_ib_dbg(dev, "err %d\n", err);
 962                 return err;
 963         }
 964
 965         qp->rq.offset = 0;
 966         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 967         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 968
 969         err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
 970                                        &qp->buf, dev->mdev->priv.numa_node);
 971         if (err) {
 972                 mlx5_ib_dbg(dev, "err %d\n", err);
 973                 return err;
 974         }
 975
 976         if (qp->rq.wqe_cnt)
 977                 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
 978                               ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
 979
 980         if (qp->sq.wqe_cnt) {
 981                 int sq_strides_offset = (qp->sq.offset  & (PAGE_SIZE - 1)) /
 982                                         MLX5_SEND_WQE_BB;
 983                 mlx5_init_fbc_offset(qp->buf.frags +
 984                                      (qp->sq.offset / PAGE_SIZE),
 985                                      ilog2(MLX5_SEND_WQE_BB),
 986                                      ilog2(qp->sq.wqe_cnt),
 987                                      sq_strides_offset, &qp->sq.fbc);
 988
 989                 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
 990         }
 991
 992         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 993                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 994         *in = kvzalloc(*inlen, GFP_KERNEL);
 995         if (!*in) {
 996                 err = -ENOMEM;
 997                 goto err_buf;
 998         }
 999
1000         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1001         MLX5_SET(qpc, qpc, uar_page, uar_index);
1002         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1003
1004         /* Set "fast registration enabled" for all kernel QPs */
1005         MLX5_SET(qpc, qpc, fre, 1);
1006         MLX5_SET(qpc, qpc, rlky, 1);
1007
1008         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
1009                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1010                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1011         }
1012
1013         mlx5_fill_page_frag_array(&qp->buf,
1014                                   (__be64 *)MLX5_ADDR_OF(create_qp_in,
1015                                                          *in, pas));
1016
1017         err = mlx5_db_alloc(dev->mdev, &qp->db);
1018         if (err) {
1019                 mlx5_ib_dbg(dev, "err %d\n", err);
1020                 goto err_free;
1021         }
1022
1023         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1024                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
1025         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1026                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
1027         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1028                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1029         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1030                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1031         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1032                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1033
1034         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1035             !qp->sq.w_list || !qp->sq.wqe_head) {
1036                 err = -ENOMEM;
1037                 goto err_wrid;
1038         }
1039         qp->create_type = MLX5_QP_KERNEL;
1040
1041         return 0;
1042
1043 err_wrid:
1044         kvfree(qp->sq.wqe_head);
1045         kvfree(qp->sq.w_list);
1046         kvfree(qp->sq.wrid);
1047         kvfree(qp->sq.wr_data);
1048         kvfree(qp->rq.wrid);
1049         mlx5_db_free(dev->mdev, &qp->db);
1050
1051 err_free:
1052         kvfree(*in);
1053
1054 err_buf:
1055         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1056         return err;
1057 }
1058
1059 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1060 {
1061         kvfree(qp->sq.wqe_head);
1062         kvfree(qp->sq.w_list);
1063         kvfree(qp->sq.wrid);
1064         kvfree(qp->sq.wr_data);
1065         kvfree(qp->rq.wrid);
1066         mlx5_db_free(dev->mdev, &qp->db);
1067         mlx5_frag_buf_free(dev->mdev, &qp->buf);
1068 }
1069
1070 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1071 {
1072         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1073             (attr->qp_type == MLX5_IB_QPT_DCI) ||
1074             (attr->qp_type == IB_QPT_XRC_INI))
1075                 return MLX5_SRQ_RQ;
1076         else if (!qp->has_rq)
1077                 return MLX5_ZERO_LEN_RQ;
1078         else
1079                 return MLX5_NON_ZERO_RQ;
1080 }
1081
1082 static int is_connected(enum ib_qp_type qp_type)
1083 {
1084         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1085             qp_type == MLX5_IB_QPT_DCI)
1086                 return 1;
1087
1088         return 0;
1089 }
1090
1091 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1092                                     struct mlx5_ib_qp *qp,
1093                                     struct mlx5_ib_sq *sq, u32 tdn,
1094                                     struct ib_pd *pd)
1095 {
1096         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1097         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1098
1099         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1100         MLX5_SET(tisc, tisc, transport_domain, tdn);
1101         if (qp->flags & MLX5_IB_QP_UNDERLAY)
1102                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1103
1104         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1105 }
1106
1107 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1108                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1109 {
1110         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1111 }
1112
1113 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1114                                        struct mlx5_ib_sq *sq)
1115 {
1116         if (sq->flow_rule)
1117                 mlx5_del_flow_rules(sq->flow_rule);
1118 }
1119
1120 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1121                                    struct mlx5_ib_sq *sq, void *qpin,
1122                                    struct ib_pd *pd)
1123 {
1124         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1125         __be64 *pas;
1126         void *in;
1127         void *sqc;
1128         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1129         void *wq;
1130         int inlen;
1131         int err;
1132         int page_shift = 0;
1133         int npages;
1134         int ncont = 0;
1135         u32 offset = 0;
1136
1137         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1138                                &sq->ubuffer.umem, &npages, &page_shift,
1139                                &ncont, &offset);
1140         if (err)
1141                 return err;
1142
1143         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1144         in = kvzalloc(inlen, GFP_KERNEL);
1145         if (!in) {
1146                 err = -ENOMEM;
1147                 goto err_umem;
1148         }
1149
1150         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1151         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1152         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1153         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1154                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1155         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1156         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1157         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1158         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1159         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1160         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1161             MLX5_CAP_ETH(dev->mdev, swp))
1162                 MLX5_SET(sqc, sqc, allow_swp, 1);
1163
1164         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1165         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1166         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1167         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1168         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1169         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1170         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1171         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1172         MLX5_SET(wq, wq, page_offset, offset);
1173
1174         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1175         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1176
1177         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1178
1179         kvfree(in);
1180
1181         if (err)
1182                 goto err_umem;
1183
1184         err = create_flow_rule_vport_sq(dev, sq);
1185         if (err)
1186                 goto err_flow;
1187
1188         return 0;
1189
1190 err_flow:
1191         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1192
1193 err_umem:
1194         ib_umem_release(sq->ubuffer.umem);
1195         sq->ubuffer.umem = NULL;
1196
1197         return err;
1198 }
1199
1200 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1201                                      struct mlx5_ib_sq *sq)
1202 {
1203         destroy_flow_rule_vport_sq(dev, sq);
1204         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1205         ib_umem_release(sq->ubuffer.umem);
1206 }
1207
1208 static size_t get_rq_pas_size(void *qpc)
1209 {
1210         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1211         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1212         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1213         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1214         u32 po_quanta     = 1 << (log_page_size - 6);
1215         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1216         u32 page_size     = 1 << log_page_size;
1217         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1218         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1219
1220         return rq_num_pas * sizeof(u64);
1221 }
1222
1223 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1224                                    struct mlx5_ib_rq *rq, void *qpin,
1225                                    size_t qpinlen, struct ib_pd *pd)
1226 {
1227         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1228         __be64 *pas;
1229         __be64 *qp_pas;
1230         void *in;
1231         void *rqc;
1232         void *wq;
1233         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1234         size_t rq_pas_size = get_rq_pas_size(qpc);
1235         size_t inlen;
1236         int err;
1237
1238         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1239                 return -EINVAL;
1240
1241         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1242         in = kvzalloc(inlen, GFP_KERNEL);
1243         if (!in)
1244                 return -ENOMEM;
1245
1246         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1247         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1248         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1249                 MLX5_SET(rqc, rqc, vsd, 1);
1250         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1251         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1252         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1253         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1254         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1255
1256         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1257                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1258
1259         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1260         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1261         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1262                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1263         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1264         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1265         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1266         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1267         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1268         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1269
1270         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1271         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1272         memcpy(pas, qp_pas, rq_pas_size);
1273
1274         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1275
1276         kvfree(in);
1277
1278         return err;
1279 }
1280
1281 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1282                                      struct mlx5_ib_rq *rq)
1283 {
1284         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1285 }
1286
1287 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1288 {
1289         return  (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1290                  MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1291                  MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1292 }
1293
1294 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1295                                       struct mlx5_ib_rq *rq,
1296                                       u32 qp_flags_en,
1297                                       struct ib_pd *pd)
1298 {
1299         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1300                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1301                 mlx5_ib_disable_lb(dev, false, true);
1302         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1303 }
1304
1305 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1306                                     struct mlx5_ib_rq *rq, u32 tdn,
1307                                     u32 *qp_flags_en,
1308                                     struct ib_pd *pd)
1309 {
1310         u8 lb_flag = 0;
1311         u32 *in;
1312         void *tirc;
1313         int inlen;
1314         int err;
1315
1316         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1317         in = kvzalloc(inlen, GFP_KERNEL);
1318         if (!in)
1319                 return -ENOMEM;
1320
1321         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1322         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1323         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1324         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1325         MLX5_SET(tirc, tirc, transport_domain, tdn);
1326         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1327                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1328
1329         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1330                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1331
1332         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1333                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1334
1335         if (dev->rep) {
1336                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1337                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1338         }
1339
1340         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1341
1342         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1343
1344         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1345                 err = mlx5_ib_enable_lb(dev, false, true);
1346
1347                 if (err)
1348                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1349         }
1350         kvfree(in);
1351
1352         return err;
1353 }
1354
1355 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1356                                 u32 *in, size_t inlen,
1357                                 struct ib_pd *pd,
1358                                 struct ib_udata *udata,
1359                                 struct mlx5_ib_create_qp_resp *resp)
1360 {
1361         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1362         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1363         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1364         struct ib_uobject *uobj = pd->uobject;
1365         struct ib_ucontext *ucontext = uobj->context;
1366         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1367         int err;
1368         u32 tdn = mucontext->tdn;
1369         u16 uid = to_mpd(pd)->uid;
1370
1371         if (qp->sq.wqe_cnt) {
1372                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1373                 if (err)
1374                         return err;
1375
1376                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1377                 if (err)
1378                         goto err_destroy_tis;
1379
1380                 if (uid) {
1381                         resp->tisn = sq->tisn;
1382                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1383                         resp->sqn = sq->base.mqp.qpn;
1384                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1385                 }
1386
1387                 sq->base.container_mibqp = qp;
1388                 sq->base.mqp.event = mlx5_ib_qp_event;
1389         }
1390
1391         if (qp->rq.wqe_cnt) {
1392                 rq->base.container_mibqp = qp;
1393
1394                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1395                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1396                 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1397                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1398                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1399                 if (err)
1400                         goto err_destroy_sq;
1401
1402                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd);
1403                 if (err)
1404                         goto err_destroy_rq;
1405
1406                 if (uid) {
1407                         resp->rqn = rq->base.mqp.qpn;
1408                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1409                         resp->tirn = rq->tirn;
1410                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1411                 }
1412         }
1413
1414         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1415                                                      rq->base.mqp.qpn;
1416         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1417         if (err)
1418                 goto err_destroy_tir;
1419
1420         return 0;
1421
1422 err_destroy_tir:
1423         destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1424 err_destroy_rq:
1425         destroy_raw_packet_qp_rq(dev, rq);
1426 err_destroy_sq:
1427         if (!qp->sq.wqe_cnt)
1428                 return err;
1429         destroy_raw_packet_qp_sq(dev, sq);
1430 err_destroy_tis:
1431         destroy_raw_packet_qp_tis(dev, sq, pd);
1432
1433         return err;
1434 }
1435
1436 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1437                                   struct mlx5_ib_qp *qp)
1438 {
1439         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1440         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1441         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1442
1443         if (qp->rq.wqe_cnt) {
1444                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1445                 destroy_raw_packet_qp_rq(dev, rq);
1446         }
1447
1448         if (qp->sq.wqe_cnt) {
1449                 destroy_raw_packet_qp_sq(dev, sq);
1450                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1451         }
1452 }
1453
1454 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1455                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1456 {
1457         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1458         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1459
1460         sq->sq = &qp->sq;
1461         rq->rq = &qp->rq;
1462         sq->doorbell = &qp->db;
1463         rq->doorbell = &qp->db;
1464 }
1465
1466 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1467 {
1468         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1469                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1470                 mlx5_ib_disable_lb(dev, false, true);
1471         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1472                              to_mpd(qp->ibqp.pd)->uid);
1473 }
1474
1475 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1476                                  struct ib_pd *pd,
1477                                  struct ib_qp_init_attr *init_attr,
1478                                  struct ib_udata *udata)
1479 {
1480         struct ib_uobject *uobj = pd->uobject;
1481         struct ib_ucontext *ucontext = uobj->context;
1482         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1483         struct mlx5_ib_create_qp_resp resp = {};
1484         int inlen;
1485         int err;
1486         u32 *in;
1487         void *tirc;
1488         void *hfso;
1489         u32 selected_fields = 0;
1490         u32 outer_l4;
1491         size_t min_resp_len;
1492         u32 tdn = mucontext->tdn;
1493         struct mlx5_ib_create_qp_rss ucmd = {};
1494         size_t required_cmd_sz;
1495         u8 lb_flag = 0;
1496
1497         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1498                 return -EOPNOTSUPP;
1499
1500         if (init_attr->create_flags || init_attr->send_cq)
1501                 return -EINVAL;
1502
1503         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1504         if (udata->outlen < min_resp_len)
1505                 return -EINVAL;
1506
1507         required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1508         if (udata->inlen < required_cmd_sz) {
1509                 mlx5_ib_dbg(dev, "invalid inlen\n");
1510                 return -EINVAL;
1511         }
1512
1513         if (udata->inlen > sizeof(ucmd) &&
1514             !ib_is_udata_cleared(udata, sizeof(ucmd),
1515                                  udata->inlen - sizeof(ucmd))) {
1516                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1517                 return -EOPNOTSUPP;
1518         }
1519
1520         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1521                 mlx5_ib_dbg(dev, "copy failed\n");
1522                 return -EFAULT;
1523         }
1524
1525         if (ucmd.comp_mask) {
1526                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1527                 return -EOPNOTSUPP;
1528         }
1529
1530         if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1531                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1532                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1533                 mlx5_ib_dbg(dev, "invalid flags\n");
1534                 return -EOPNOTSUPP;
1535         }
1536
1537         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1538             !tunnel_offload_supported(dev->mdev)) {
1539                 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1540                 return -EOPNOTSUPP;
1541         }
1542
1543         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1544             !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1545                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1546                 return -EOPNOTSUPP;
1547         }
1548
1549         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) {
1550                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1551                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1552         }
1553
1554         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1555                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1556                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1557         }
1558
1559         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1560         if (err) {
1561                 mlx5_ib_dbg(dev, "copy failed\n");
1562                 return -EINVAL;
1563         }
1564
1565         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1566         in = kvzalloc(inlen, GFP_KERNEL);
1567         if (!in)
1568                 return -ENOMEM;
1569
1570         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1571         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1572         MLX5_SET(tirc, tirc, disp_type,
1573                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1574         MLX5_SET(tirc, tirc, indirect_table,
1575                  init_attr->rwq_ind_tbl->ind_tbl_num);
1576         MLX5_SET(tirc, tirc, transport_domain, tdn);
1577
1578         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1579
1580         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1581                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1582
1583         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1584
1585         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1586                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1587         else
1588                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1589
1590         switch (ucmd.rx_hash_function) {
1591         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1592         {
1593                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1594                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1595
1596                 if (len != ucmd.rx_key_len) {
1597                         err = -EINVAL;
1598                         goto err;
1599                 }
1600
1601                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1602                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1603                 memcpy(rss_key, ucmd.rx_hash_key, len);
1604                 break;
1605         }
1606         default:
1607                 err = -EOPNOTSUPP;
1608                 goto err;
1609         }
1610
1611         if (!ucmd.rx_hash_fields_mask) {
1612                 /* special case when this TIR serves as steering entry without hashing */
1613                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1614                         goto create_tir;
1615                 err = -EINVAL;
1616                 goto err;
1617         }
1618
1619         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1620              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1621              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1622              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1623                 err = -EINVAL;
1624                 goto err;
1625         }
1626
1627         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1628         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1629             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1630                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1631                          MLX5_L3_PROT_TYPE_IPV4);
1632         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1633                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1634                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1635                          MLX5_L3_PROT_TYPE_IPV6);
1636
1637         outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1638                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1639                    ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1640                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1641                    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1642
1643         /* Check that only one l4 protocol is set */
1644         if (outer_l4 & (outer_l4 - 1)) {
1645                 err = -EINVAL;
1646                 goto err;
1647         }
1648
1649         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1650         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1651             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1652                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1653                          MLX5_L4_PROT_TYPE_TCP);
1654         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1655                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1656                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1657                          MLX5_L4_PROT_TYPE_UDP);
1658
1659         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1660             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1661                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1662
1663         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1664             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1665                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1666
1667         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1668             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1669                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1670
1671         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1672             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1673                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1674
1675         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1676                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1677
1678         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1679
1680 create_tir:
1681         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1682
1683         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1684                 err = mlx5_ib_enable_lb(dev, false, true);
1685
1686                 if (err)
1687                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1688                                              to_mpd(pd)->uid);
1689         }
1690
1691         if (err)
1692                 goto err;
1693
1694         if (mucontext->devx_uid) {
1695                 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1696                 resp.tirn = qp->rss_qp.tirn;
1697         }
1698
1699         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1700         if (err)
1701                 goto err_copy;
1702
1703         kvfree(in);
1704         /* qpn is reserved for that QP */
1705         qp->trans_qp.base.mqp.qpn = 0;
1706         qp->flags |= MLX5_IB_QP_RSS;
1707         return 0;
1708
1709 err_copy:
1710         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1711 err:
1712         kvfree(in);
1713         return err;
1714 }
1715
1716 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1717                                          void *qpc)
1718 {
1719         int rcqe_sz;
1720
1721         if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1722                 return;
1723
1724         rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1725
1726         if (rcqe_sz == 128) {
1727                 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1728                 return;
1729         }
1730
1731         if (init_attr->qp_type != MLX5_IB_QPT_DCT)
1732                 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1733 }
1734
1735 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1736                                          struct ib_qp_init_attr *init_attr,
1737                                          struct mlx5_ib_create_qp *ucmd,
1738                                          void *qpc)
1739 {
1740         enum ib_qp_type qpt = init_attr->qp_type;
1741         int scqe_sz;
1742         bool allow_scat_cqe = 0;
1743
1744         if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1745                 return;
1746
1747         if (ucmd)
1748                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1749
1750         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1751                 return;
1752
1753         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1754         if (scqe_sz == 128) {
1755                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1756                 return;
1757         }
1758
1759         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1760             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1761                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1762 }
1763
1764 static int atomic_size_to_mode(int size_mask)
1765 {
1766         /* driver does not support atomic_size > 256B
1767          * and does not know how to translate bigger sizes
1768          */
1769         int supported_size_mask = size_mask & 0x1ff;
1770         int log_max_size;
1771
1772         if (!supported_size_mask)
1773                 return -EOPNOTSUPP;
1774
1775         log_max_size = __fls(supported_size_mask);
1776
1777         if (log_max_size > 3)
1778                 return log_max_size;
1779
1780         return MLX5_ATOMIC_MODE_8B;
1781 }
1782
1783 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1784                            enum ib_qp_type qp_type)
1785 {
1786         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1787         u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1788         int atomic_mode = -EOPNOTSUPP;
1789         int atomic_size_mask;
1790
1791         if (!atomic)
1792                 return -EOPNOTSUPP;
1793
1794         if (qp_type == MLX5_IB_QPT_DCT)
1795                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1796         else
1797                 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1798
1799         if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1800             (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1801                 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1802
1803         if (atomic_mode <= 0 &&
1804             (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1805              atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1806                 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1807
1808         return atomic_mode;
1809 }
1810
1811 static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1812 {
1813         return (input & ~supported) == 0;
1814 }
1815
1816 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1817                             struct ib_qp_init_attr *init_attr,
1818                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1819 {
1820         struct mlx5_ib_resources *devr = &dev->devr;
1821         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1822         struct mlx5_core_dev *mdev = dev->mdev;
1823         struct mlx5_ib_create_qp_resp resp = {};
1824         struct mlx5_ib_cq *send_cq;
1825         struct mlx5_ib_cq *recv_cq;
1826         unsigned long flags;
1827         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1828         struct mlx5_ib_create_qp ucmd;
1829         struct mlx5_ib_qp_base *base;
1830         int mlx5_st;
1831         void *qpc;
1832         u32 *in;
1833         int err;
1834
1835         mutex_init(&qp->mutex);
1836         spin_lock_init(&qp->sq.lock);
1837         spin_lock_init(&qp->rq.lock);
1838
1839         mlx5_st = to_mlx5_st(init_attr->qp_type);
1840         if (mlx5_st < 0)
1841                 return -EINVAL;
1842
1843         if (init_attr->rwq_ind_tbl) {
1844                 if (!udata)
1845                         return -ENOSYS;
1846
1847                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1848                 return err;
1849         }
1850
1851         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1852                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1853                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1854                         return -EINVAL;
1855                 } else {
1856                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1857                 }
1858         }
1859
1860         if (init_attr->create_flags &
1861                         (IB_QP_CREATE_CROSS_CHANNEL |
1862                          IB_QP_CREATE_MANAGED_SEND |
1863                          IB_QP_CREATE_MANAGED_RECV)) {
1864                 if (!MLX5_CAP_GEN(mdev, cd)) {
1865                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1866                         return -EINVAL;
1867                 }
1868                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1869                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1870                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1871                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1872                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1873                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1874         }
1875
1876         if (init_attr->qp_type == IB_QPT_UD &&
1877             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1878                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1879                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1880                         return -EOPNOTSUPP;
1881                 }
1882
1883         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1884                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1885                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1886                         return -EOPNOTSUPP;
1887                 }
1888                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1889                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1890                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1891                         return -EOPNOTSUPP;
1892                 }
1893                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1894         }
1895
1896         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1897                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1898
1899         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1900                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1901                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1902                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
1903                         return -EOPNOTSUPP;
1904                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1905         }
1906
1907         if (pd && pd->uobject) {
1908                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1909                         mlx5_ib_dbg(dev, "copy failed\n");
1910                         return -EFAULT;
1911                 }
1912
1913                 if (!check_flags_mask(ucmd.flags,
1914                                       MLX5_QP_FLAG_SIGNATURE |
1915                                               MLX5_QP_FLAG_SCATTER_CQE |
1916                                               MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1917                                               MLX5_QP_FLAG_BFREG_INDEX |
1918                                               MLX5_QP_FLAG_TYPE_DCT |
1919                                               MLX5_QP_FLAG_TYPE_DCI |
1920                                               MLX5_QP_FLAG_ALLOW_SCATTER_CQE |
1921                                               MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE))
1922                         return -EINVAL;
1923
1924                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1925                                         &ucmd, udata->inlen, &uidx);
1926                 if (err)
1927                         return err;
1928
1929                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1930                 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
1931                         qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1932                 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1933                         if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1934                             !tunnel_offload_supported(mdev)) {
1935                                 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1936                                 return -EOPNOTSUPP;
1937                         }
1938                         qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
1939                 }
1940
1941                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
1942                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1943                                 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
1944                                 return -EOPNOTSUPP;
1945                         }
1946                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1947                 }
1948
1949                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1950                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1951                                 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
1952                                 return -EOPNOTSUPP;
1953                         }
1954                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1955                 }
1956
1957                 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) {
1958                         if (init_attr->qp_type != IB_QPT_RC ||
1959                                 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) {
1960                                 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n");
1961                                 return -EOPNOTSUPP;
1962                         }
1963                         qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT;
1964                 }
1965
1966                 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1967                         if (init_attr->qp_type != IB_QPT_UD ||
1968                             (MLX5_CAP_GEN(dev->mdev, port_type) !=
1969                              MLX5_CAP_PORT_TYPE_IB) ||
1970                             !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1971                                 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1972                                 return -EOPNOTSUPP;
1973                         }
1974
1975                         qp->flags |= MLX5_IB_QP_UNDERLAY;
1976                         qp->underlay_qpn = init_attr->source_qpn;
1977                 }
1978         } else {
1979                 qp->wq_sig = !!wq_signature;
1980         }
1981
1982         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1983                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1984                &qp->raw_packet_qp.rq.base :
1985                &qp->trans_qp.base;
1986
1987         qp->has_rq = qp_has_rq(init_attr);
1988         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1989                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1990         if (err) {
1991                 mlx5_ib_dbg(dev, "err %d\n", err);
1992                 return err;
1993         }
1994
1995         if (pd) {
1996                 if (pd->uobject) {
1997                         __u32 max_wqes =
1998                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1999                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
2000                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
2001                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
2002                                 mlx5_ib_dbg(dev, "invalid rq params\n");
2003                                 return -EINVAL;
2004                         }
2005                         if (ucmd.sq_wqe_count > max_wqes) {
2006                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
2007                                             ucmd.sq_wqe_count, max_wqes);
2008                                 return -EINVAL;
2009                         }
2010                         if (init_attr->create_flags &
2011                             mlx5_ib_create_qp_sqpn_qp1()) {
2012                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
2013                                 return -EINVAL;
2014                         }
2015                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
2016                                              &resp, &inlen, base);
2017                         if (err)
2018                                 mlx5_ib_dbg(dev, "err %d\n", err);
2019                 } else {
2020                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
2021                                                base);
2022                         if (err)
2023                                 mlx5_ib_dbg(dev, "err %d\n", err);
2024                 }
2025
2026                 if (err)
2027                         return err;
2028         } else {
2029                 in = kvzalloc(inlen, GFP_KERNEL);
2030                 if (!in)
2031                         return -ENOMEM;
2032
2033                 qp->create_type = MLX5_QP_EMPTY;
2034         }
2035
2036         if (is_sqp(init_attr->qp_type))
2037                 qp->port = init_attr->port_num;
2038
2039         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2040
2041         MLX5_SET(qpc, qpc, st, mlx5_st);
2042         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2043
2044         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
2045                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2046         else
2047                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2048
2049
2050         if (qp->wq_sig)
2051                 MLX5_SET(qpc, qpc, wq_signature, 1);
2052
2053         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2054                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2055
2056         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
2057                 MLX5_SET(qpc, qpc, cd_master, 1);
2058         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
2059                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2060         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
2061                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2062         if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT)
2063                 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2064         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
2065                 configure_responder_scat_cqe(init_attr, qpc);
2066                 configure_requester_scat_cqe(dev, init_attr,
2067                                              (pd && pd->uobject) ? &ucmd : NULL,
2068                                              qpc);
2069         }
2070
2071         if (qp->rq.wqe_cnt) {
2072                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2073                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2074         }
2075
2076         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2077
2078         if (qp->sq.wqe_cnt) {
2079                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2080         } else {
2081                 MLX5_SET(qpc, qpc, no_sq, 1);
2082                 if (init_attr->srq &&
2083                     init_attr->srq->srq_type == IB_SRQT_TM)
2084                         MLX5_SET(qpc, qpc, offload_type,
2085                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2086         }
2087
2088         /* Set default resources */
2089         switch (init_attr->qp_type) {
2090         case IB_QPT_XRC_TGT:
2091                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2092                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2093                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2094                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
2095                 break;
2096         case IB_QPT_XRC_INI:
2097                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2098                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2099                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2100                 break;
2101         default:
2102                 if (init_attr->srq) {
2103                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2104                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2105                 } else {
2106                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2107                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2108                 }
2109         }
2110
2111         if (init_attr->send_cq)
2112                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2113
2114         if (init_attr->recv_cq)
2115                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2116
2117         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2118
2119         /* 0xffffff means we ask to work with cqe version 0 */
2120         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2121                 MLX5_SET(qpc, qpc, user_index, uidx);
2122
2123         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2124         if (init_attr->qp_type == IB_QPT_UD &&
2125             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
2126                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2127                 qp->flags |= MLX5_IB_QP_LSO;
2128         }
2129
2130         if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2131                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2132                         mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2133                         err = -EOPNOTSUPP;
2134                         goto err;
2135                 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2136                         MLX5_SET(qpc, qpc, end_padding_mode,
2137                                  MLX5_WQ_END_PAD_MODE_ALIGN);
2138                 } else {
2139                         qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2140                 }
2141         }
2142
2143         if (inlen < 0) {
2144                 err = -EINVAL;
2145                 goto err;
2146         }
2147
2148         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2149             qp->flags & MLX5_IB_QP_UNDERLAY) {
2150                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2151                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2152                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2153                                            &resp);
2154         } else {
2155                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2156         }
2157
2158         if (err) {
2159                 mlx5_ib_dbg(dev, "create qp failed\n");
2160                 goto err_create;
2161         }
2162
2163         kvfree(in);
2164
2165         base->container_mibqp = qp;
2166         base->mqp.event = mlx5_ib_qp_event;
2167
2168         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2169                 &send_cq, &recv_cq);
2170         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2171         mlx5_ib_lock_cqs(send_cq, recv_cq);
2172         /* Maintain device to QPs access, needed for further handling via reset
2173          * flow
2174          */
2175         list_add_tail(&qp->qps_list, &dev->qp_list);
2176         /* Maintain CQ to QPs access, needed for further handling via reset flow
2177          */
2178         if (send_cq)
2179                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2180         if (recv_cq)
2181                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2182         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2183         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2184
2185         return 0;
2186
2187 err_create:
2188         if (qp->create_type == MLX5_QP_USER)
2189                 destroy_qp_user(dev, pd, qp, base);
2190         else if (qp->create_type == MLX5_QP_KERNEL)
2191                 destroy_qp_kernel(dev, qp);
2192
2193 err:
2194         kvfree(in);
2195         return err;
2196 }
2197
2198 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2199         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2200 {
2201         if (send_cq) {
2202                 if (recv_cq) {
2203                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2204                                 spin_lock(&send_cq->lock);
2205                                 spin_lock_nested(&recv_cq->lock,
2206                                                  SINGLE_DEPTH_NESTING);
2207                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2208                                 spin_lock(&send_cq->lock);
2209                                 __acquire(&recv_cq->lock);
2210                         } else {
2211                                 spin_lock(&recv_cq->lock);
2212                                 spin_lock_nested(&send_cq->lock,
2213                                                  SINGLE_DEPTH_NESTING);
2214                         }
2215                 } else {
2216                         spin_lock(&send_cq->lock);
2217                         __acquire(&recv_cq->lock);
2218                 }
2219         } else if (recv_cq) {
2220                 spin_lock(&recv_cq->lock);
2221                 __acquire(&send_cq->lock);
2222         } else {
2223                 __acquire(&send_cq->lock);
2224                 __acquire(&recv_cq->lock);
2225         }
2226 }
2227
2228 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2229         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2230 {
2231         if (send_cq) {
2232                 if (recv_cq) {
2233                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2234                                 spin_unlock(&recv_cq->lock);
2235                                 spin_unlock(&send_cq->lock);
2236                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2237                                 __release(&recv_cq->lock);
2238                                 spin_unlock(&send_cq->lock);
2239                         } else {
2240                                 spin_unlock(&send_cq->lock);
2241                                 spin_unlock(&recv_cq->lock);
2242                         }
2243                 } else {
2244                         __release(&recv_cq->lock);
2245                         spin_unlock(&send_cq->lock);
2246                 }
2247         } else if (recv_cq) {
2248                 __release(&send_cq->lock);
2249                 spin_unlock(&recv_cq->lock);
2250         } else {
2251                 __release(&recv_cq->lock);
2252                 __release(&send_cq->lock);
2253         }
2254 }
2255
2256 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2257 {
2258         return to_mpd(qp->ibqp.pd);
2259 }
2260
2261 static void get_cqs(enum ib_qp_type qp_type,
2262                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2263                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2264 {
2265         switch (qp_type) {
2266         case IB_QPT_XRC_TGT:
2267                 *send_cq = NULL;
2268                 *recv_cq = NULL;
2269                 break;
2270         case MLX5_IB_QPT_REG_UMR:
2271         case IB_QPT_XRC_INI:
2272                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2273                 *recv_cq = NULL;
2274                 break;
2275
2276         case IB_QPT_SMI:
2277         case MLX5_IB_QPT_HW_GSI:
2278         case IB_QPT_RC:
2279         case IB_QPT_UC:
2280         case IB_QPT_UD:
2281         case IB_QPT_RAW_IPV6:
2282         case IB_QPT_RAW_ETHERTYPE:
2283         case IB_QPT_RAW_PACKET:
2284                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2285                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2286                 break;
2287
2288         case IB_QPT_MAX:
2289         default:
2290                 *send_cq = NULL;
2291                 *recv_cq = NULL;
2292                 break;
2293         }
2294 }
2295
2296 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2297                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2298                                 u8 lag_tx_affinity);
2299
2300 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2301 {
2302         struct mlx5_ib_cq *send_cq, *recv_cq;
2303         struct mlx5_ib_qp_base *base;
2304         unsigned long flags;
2305         int err;
2306
2307         if (qp->ibqp.rwq_ind_tbl) {
2308                 destroy_rss_raw_qp_tir(dev, qp);
2309                 return;
2310         }
2311
2312         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2313                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2314                &qp->raw_packet_qp.rq.base :
2315                &qp->trans_qp.base;
2316
2317         if (qp->state != IB_QPS_RESET) {
2318                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2319                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2320                         err = mlx5_core_qp_modify(dev->mdev,
2321                                                   MLX5_CMD_OP_2RST_QP, 0,
2322                                                   NULL, &base->mqp);
2323                 } else {
2324                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2325                                 .operation = MLX5_CMD_OP_2RST_QP
2326                         };
2327
2328                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2329                 }
2330                 if (err)
2331                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2332                                      base->mqp.qpn);
2333         }
2334
2335         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2336                 &send_cq, &recv_cq);
2337
2338         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2339         mlx5_ib_lock_cqs(send_cq, recv_cq);
2340         /* del from lists under both locks above to protect reset flow paths */
2341         list_del(&qp->qps_list);
2342         if (send_cq)
2343                 list_del(&qp->cq_send_list);
2344
2345         if (recv_cq)
2346                 list_del(&qp->cq_recv_list);
2347
2348         if (qp->create_type == MLX5_QP_KERNEL) {
2349                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2350                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2351                 if (send_cq != recv_cq)
2352                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2353                                            NULL);
2354         }
2355         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2356         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2357
2358         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2359             qp->flags & MLX5_IB_QP_UNDERLAY) {
2360                 destroy_raw_packet_qp(dev, qp);
2361         } else {
2362                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2363                 if (err)
2364                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2365                                      base->mqp.qpn);
2366         }
2367
2368         if (qp->create_type == MLX5_QP_KERNEL)
2369                 destroy_qp_kernel(dev, qp);
2370         else if (qp->create_type == MLX5_QP_USER)
2371                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2372 }
2373
2374 static const char *ib_qp_type_str(enum ib_qp_type type)
2375 {
2376         switch (type) {
2377         case IB_QPT_SMI:
2378                 return "IB_QPT_SMI";
2379         case IB_QPT_GSI:
2380                 return "IB_QPT_GSI";
2381         case IB_QPT_RC:
2382                 return "IB_QPT_RC";
2383         case IB_QPT_UC:
2384                 return "IB_QPT_UC";
2385         case IB_QPT_UD:
2386                 return "IB_QPT_UD";
2387         case IB_QPT_RAW_IPV6:
2388                 return "IB_QPT_RAW_IPV6";
2389         case IB_QPT_RAW_ETHERTYPE:
2390                 return "IB_QPT_RAW_ETHERTYPE";
2391         case IB_QPT_XRC_INI:
2392                 return "IB_QPT_XRC_INI";
2393         case IB_QPT_XRC_TGT:
2394                 return "IB_QPT_XRC_TGT";
2395         case IB_QPT_RAW_PACKET:
2396                 return "IB_QPT_RAW_PACKET";
2397         case MLX5_IB_QPT_REG_UMR:
2398                 return "MLX5_IB_QPT_REG_UMR";
2399         case IB_QPT_DRIVER:
2400                 return "IB_QPT_DRIVER";
2401         case IB_QPT_MAX:
2402         default:
2403                 return "Invalid QP type";
2404         }
2405 }
2406
2407 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2408                                         struct ib_qp_init_attr *attr,
2409                                         struct mlx5_ib_create_qp *ucmd)
2410 {
2411         struct mlx5_ib_qp *qp;
2412         int err = 0;
2413         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2414         void *dctc;
2415
2416         if (!attr->srq || !attr->recv_cq)
2417                 return ERR_PTR(-EINVAL);
2418
2419         err = get_qp_user_index(to_mucontext(pd->uobject->context),
2420                                 ucmd, sizeof(*ucmd), &uidx);
2421         if (err)
2422                 return ERR_PTR(err);
2423
2424         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2425         if (!qp)
2426                 return ERR_PTR(-ENOMEM);
2427
2428         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2429         if (!qp->dct.in) {
2430                 err = -ENOMEM;
2431                 goto err_free;
2432         }
2433
2434         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2435         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2436         qp->qp_sub_type = MLX5_IB_QPT_DCT;
2437         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2438         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2439         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2440         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2441         MLX5_SET(dctc, dctc, user_index, uidx);
2442
2443         if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2444                 configure_responder_scat_cqe(attr, dctc);
2445
2446         qp->state = IB_QPS_RESET;
2447
2448         return &qp->ibqp;
2449 err_free:
2450         kfree(qp);
2451         return ERR_PTR(err);
2452 }
2453
2454 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2455                            struct ib_qp_init_attr *init_attr,
2456                            struct mlx5_ib_create_qp *ucmd,
2457                            struct ib_udata *udata)
2458 {
2459         enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2460         int err;
2461
2462         if (!udata)
2463                 return -EINVAL;
2464
2465         if (udata->inlen < sizeof(*ucmd)) {
2466                 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2467                 return -EINVAL;
2468         }
2469         err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2470         if (err)
2471                 return err;
2472
2473         if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2474                 init_attr->qp_type = MLX5_IB_QPT_DCI;
2475         } else {
2476                 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2477                         init_attr->qp_type = MLX5_IB_QPT_DCT;
2478                 } else {
2479                         mlx5_ib_dbg(dev, "Invalid QP flags\n");
2480                         return -EINVAL;
2481                 }
2482         }
2483
2484         if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2485                 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2486                 return -EOPNOTSUPP;
2487         }
2488
2489         return 0;
2490 }
2491
2492 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2493                                 struct ib_qp_init_attr *verbs_init_attr,
2494                                 struct ib_udata *udata)
2495 {
2496         struct mlx5_ib_dev *dev;
2497         struct mlx5_ib_qp *qp;
2498         u16 xrcdn = 0;
2499         int err;
2500         struct ib_qp_init_attr mlx_init_attr;
2501         struct ib_qp_init_attr *init_attr = verbs_init_attr;
2502
2503         if (pd) {
2504                 dev = to_mdev(pd->device);
2505
2506                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2507                         if (!pd->uobject) {
2508                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2509                                 return ERR_PTR(-EINVAL);
2510                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2511                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2512                                 return ERR_PTR(-EINVAL);
2513                         }
2514                 }
2515         } else {
2516                 /* being cautious here */
2517                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2518                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2519                         pr_warn("%s: no PD for transport %s\n", __func__,
2520                                 ib_qp_type_str(init_attr->qp_type));
2521                         return ERR_PTR(-EINVAL);
2522                 }
2523                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2524         }
2525
2526         if (init_attr->qp_type == IB_QPT_DRIVER) {
2527                 struct mlx5_ib_create_qp ucmd;
2528
2529                 init_attr = &mlx_init_attr;
2530                 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2531                 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2532                 if (err)
2533                         return ERR_PTR(err);
2534
2535                 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2536                         if (init_attr->cap.max_recv_wr ||
2537                             init_attr->cap.max_recv_sge) {
2538                                 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2539                                 return ERR_PTR(-EINVAL);
2540                         }
2541                 } else {
2542                         return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2543                 }
2544         }
2545
2546         switch (init_attr->qp_type) {
2547         case IB_QPT_XRC_TGT:
2548         case IB_QPT_XRC_INI:
2549                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2550                         mlx5_ib_dbg(dev, "XRC not supported\n");
2551                         return ERR_PTR(-ENOSYS);
2552                 }
2553                 init_attr->recv_cq = NULL;
2554                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2555                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2556                         init_attr->send_cq = NULL;
2557                 }
2558
2559                 /* fall through */
2560         case IB_QPT_RAW_PACKET:
2561         case IB_QPT_RC:
2562         case IB_QPT_UC:
2563         case IB_QPT_UD:
2564         case IB_QPT_SMI:
2565         case MLX5_IB_QPT_HW_GSI:
2566         case MLX5_IB_QPT_REG_UMR:
2567         case MLX5_IB_QPT_DCI:
2568                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2569                 if (!qp)
2570                         return ERR_PTR(-ENOMEM);
2571
2572                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2573                 if (err) {
2574                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2575                         kfree(qp);
2576                         return ERR_PTR(err);
2577                 }
2578
2579                 if (is_qp0(init_attr->qp_type))
2580                         qp->ibqp.qp_num = 0;
2581                 else if (is_qp1(init_attr->qp_type))
2582                         qp->ibqp.qp_num = 1;
2583                 else
2584                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2585
2586                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2587                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2588                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2589                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2590
2591                 qp->trans_qp.xrcdn = xrcdn;
2592
2593                 break;
2594
2595         case IB_QPT_GSI:
2596                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2597
2598         case IB_QPT_RAW_IPV6:
2599         case IB_QPT_RAW_ETHERTYPE:
2600         case IB_QPT_MAX:
2601         default:
2602                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2603                             init_attr->qp_type);
2604                 /* Don't support raw QPs */
2605                 return ERR_PTR(-EINVAL);
2606         }
2607
2608         if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2609                 qp->qp_sub_type = init_attr->qp_type;
2610
2611         return &qp->ibqp;
2612 }
2613
2614 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2615 {
2616         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2617
2618         if (mqp->state == IB_QPS_RTR) {
2619                 int err;
2620
2621                 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2622                 if (err) {
2623                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2624                         return err;
2625                 }
2626         }
2627
2628         kfree(mqp->dct.in);
2629         kfree(mqp);
2630         return 0;
2631 }
2632
2633 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2634 {
2635         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2636         struct mlx5_ib_qp *mqp = to_mqp(qp);
2637
2638         if (unlikely(qp->qp_type == IB_QPT_GSI))
2639                 return mlx5_ib_gsi_destroy_qp(qp);
2640
2641         if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2642                 return mlx5_ib_destroy_dct(mqp);
2643
2644         destroy_qp_common(dev, mqp);
2645
2646         kfree(mqp);
2647
2648         return 0;
2649 }
2650
2651 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2652                                 const struct ib_qp_attr *attr,
2653                                 int attr_mask, __be32 *hw_access_flags)
2654 {
2655         u8 dest_rd_atomic;
2656         u32 access_flags;
2657
2658         struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2659
2660         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2661                 dest_rd_atomic = attr->max_dest_rd_atomic;
2662         else
2663                 dest_rd_atomic = qp->trans_qp.resp_depth;
2664
2665         if (attr_mask & IB_QP_ACCESS_FLAGS)
2666                 access_flags = attr->qp_access_flags;
2667         else
2668                 access_flags = qp->trans_qp.atomic_rd_en;
2669
2670         if (!dest_rd_atomic)
2671                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2672
2673         if (access_flags & IB_ACCESS_REMOTE_READ)
2674                 *hw_access_flags |= MLX5_QP_BIT_RRE;
2675         if ((access_flags & IB_ACCESS_REMOTE_ATOMIC) &&
2676             qp->ibqp.qp_type == IB_QPT_RC) {
2677                 int atomic_mode;
2678
2679                 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2680                 if (atomic_mode < 0)
2681                         return -EOPNOTSUPP;
2682
2683                 *hw_access_flags |= MLX5_QP_BIT_RAE;
2684                 *hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2685         }
2686
2687         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2688                 *hw_access_flags |= MLX5_QP_BIT_RWE;
2689
2690         *hw_access_flags = cpu_to_be32(*hw_access_flags);
2691
2692         return 0;
2693 }
2694
2695 enum {
2696         MLX5_PATH_FLAG_FL       = 1 << 0,
2697         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2698         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2699 };
2700
2701 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2702 {
2703         if (rate == IB_RATE_PORT_CURRENT)
2704                 return 0;
2705
2706         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2707                 return -EINVAL;
2708
2709         while (rate != IB_RATE_PORT_CURRENT &&
2710                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2711                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2712                 --rate;
2713
2714         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2715 }
2716
2717 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2718                                       struct mlx5_ib_sq *sq, u8 sl,
2719                                       struct ib_pd *pd)
2720 {
2721         void *in;
2722         void *tisc;
2723         int inlen;
2724         int err;
2725
2726         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2727         in = kvzalloc(inlen, GFP_KERNEL);
2728         if (!in)
2729                 return -ENOMEM;
2730
2731         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2732         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2733
2734         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2735         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2736
2737         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2738
2739         kvfree(in);
2740
2741         return err;
2742 }
2743
2744 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2745                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
2746                                          struct ib_pd *pd)
2747 {
2748         void *in;
2749         void *tisc;
2750         int inlen;
2751         int err;
2752
2753         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2754         in = kvzalloc(inlen, GFP_KERNEL);
2755         if (!in)
2756                 return -ENOMEM;
2757
2758         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2759         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2760
2761         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2762         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2763
2764         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2765
2766         kvfree(in);
2767
2768         return err;
2769 }
2770
2771 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2772                          const struct rdma_ah_attr *ah,
2773                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2774                          u32 path_flags, const struct ib_qp_attr *attr,
2775                          bool alt)
2776 {
2777         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2778         int err;
2779         enum ib_gid_type gid_type;
2780         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2781         u8 sl = rdma_ah_get_sl(ah);
2782
2783         if (attr_mask & IB_QP_PKEY_INDEX)
2784                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2785                                                      attr->pkey_index);
2786
2787         if (ah_flags & IB_AH_GRH) {
2788                 if (grh->sgid_index >=
2789                     dev->mdev->port_caps[port - 1].gid_table_len) {
2790                         pr_err("sgid_index (%u) too large. max is %d\n",
2791                                grh->sgid_index,
2792                                dev->mdev->port_caps[port - 1].gid_table_len);
2793                         return -EINVAL;
2794                 }
2795         }
2796
2797         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2798                 if (!(ah_flags & IB_AH_GRH))
2799                         return -EINVAL;
2800
2801                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2802                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2803                     qp->ibqp.qp_type == IB_QPT_UC ||
2804                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2805                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2806                         path->udp_sport =
2807                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2808                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2809                 gid_type = ah->grh.sgid_attr->gid_type;
2810                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2811                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2812         } else {
2813                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2814                 path->fl_free_ar |=
2815                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2816                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2817                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2818                 if (ah_flags & IB_AH_GRH)
2819                         path->grh_mlid  |= 1 << 7;
2820                 path->dci_cfi_prio_sl = sl & 0xf;
2821         }
2822
2823         if (ah_flags & IB_AH_GRH) {
2824                 path->mgid_index = grh->sgid_index;
2825                 path->hop_limit  = grh->hop_limit;
2826                 path->tclass_flowlabel =
2827                         cpu_to_be32((grh->traffic_class << 20) |
2828                                     (grh->flow_label));
2829                 memcpy(path->rgid, grh->dgid.raw, 16);
2830         }
2831
2832         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2833         if (err < 0)
2834                 return err;
2835         path->static_rate = err;
2836         path->port = port;
2837
2838         if (attr_mask & IB_QP_TIMEOUT)
2839                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2840
2841         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2842                 return modify_raw_packet_eth_prio(dev->mdev,
2843                                                   &qp->raw_packet_qp.sq,
2844                                                   sl & 0xf, qp->ibqp.pd);
2845
2846         return 0;
2847 }
2848
2849 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2850         [MLX5_QP_STATE_INIT] = {
2851                 [MLX5_QP_STATE_INIT] = {
2852                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2853                                           MLX5_QP_OPTPAR_RAE            |
2854                                           MLX5_QP_OPTPAR_RWE            |
2855                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2856                                           MLX5_QP_OPTPAR_PRI_PORT,
2857                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2858                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2859                                           MLX5_QP_OPTPAR_PRI_PORT,
2860                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2861                                           MLX5_QP_OPTPAR_Q_KEY          |
2862                                           MLX5_QP_OPTPAR_PRI_PORT,
2863                 },
2864                 [MLX5_QP_STATE_RTR] = {
2865                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2866                                           MLX5_QP_OPTPAR_RRE            |
2867                                           MLX5_QP_OPTPAR_RAE            |
2868                                           MLX5_QP_OPTPAR_RWE            |
2869                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2870                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2871                                           MLX5_QP_OPTPAR_RWE            |
2872                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2873                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2874                                           MLX5_QP_OPTPAR_Q_KEY,
2875                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2876                                            MLX5_QP_OPTPAR_Q_KEY,
2877                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2878                                           MLX5_QP_OPTPAR_RRE            |
2879                                           MLX5_QP_OPTPAR_RAE            |
2880                                           MLX5_QP_OPTPAR_RWE            |
2881                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2882                 },
2883         },
2884         [MLX5_QP_STATE_RTR] = {
2885                 [MLX5_QP_STATE_RTS] = {
2886                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2887                                           MLX5_QP_OPTPAR_RRE            |
2888                                           MLX5_QP_OPTPAR_RAE            |
2889                                           MLX5_QP_OPTPAR_RWE            |
2890                                           MLX5_QP_OPTPAR_PM_STATE       |
2891                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2892                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2893                                           MLX5_QP_OPTPAR_RWE            |
2894                                           MLX5_QP_OPTPAR_PM_STATE,
2895                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2896                 },
2897         },
2898         [MLX5_QP_STATE_RTS] = {
2899                 [MLX5_QP_STATE_RTS] = {
2900                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2901                                           MLX5_QP_OPTPAR_RAE            |
2902                                           MLX5_QP_OPTPAR_RWE            |
2903                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2904                                           MLX5_QP_OPTPAR_PM_STATE       |
2905                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2906                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2907                                           MLX5_QP_OPTPAR_PM_STATE       |
2908                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2909                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2910                                           MLX5_QP_OPTPAR_SRQN           |
2911                                           MLX5_QP_OPTPAR_CQN_RCV,
2912                 },
2913         },
2914         [MLX5_QP_STATE_SQER] = {
2915                 [MLX5_QP_STATE_RTS] = {
2916                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2917                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2918                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2919                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2920                                            MLX5_QP_OPTPAR_RWE           |
2921                                            MLX5_QP_OPTPAR_RAE           |
2922                                            MLX5_QP_OPTPAR_RRE,
2923                 },
2924         },
2925 };
2926
2927 static int ib_nr_to_mlx5_nr(int ib_mask)
2928 {
2929         switch (ib_mask) {
2930         case IB_QP_STATE:
2931                 return 0;
2932         case IB_QP_CUR_STATE:
2933                 return 0;
2934         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2935                 return 0;
2936         case IB_QP_ACCESS_FLAGS:
2937                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2938                         MLX5_QP_OPTPAR_RAE;
2939         case IB_QP_PKEY_INDEX:
2940                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2941         case IB_QP_PORT:
2942                 return MLX5_QP_OPTPAR_PRI_PORT;
2943         case IB_QP_QKEY:
2944                 return MLX5_QP_OPTPAR_Q_KEY;
2945         case IB_QP_AV:
2946                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2947                         MLX5_QP_OPTPAR_PRI_PORT;
2948         case IB_QP_PATH_MTU:
2949                 return 0;
2950         case IB_QP_TIMEOUT:
2951                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2952         case IB_QP_RETRY_CNT:
2953                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2954         case IB_QP_RNR_RETRY:
2955                 return MLX5_QP_OPTPAR_RNR_RETRY;
2956         case IB_QP_RQ_PSN:
2957                 return 0;
2958         case IB_QP_MAX_QP_RD_ATOMIC:
2959                 return MLX5_QP_OPTPAR_SRA_MAX;
2960         case IB_QP_ALT_PATH:
2961                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2962         case IB_QP_MIN_RNR_TIMER:
2963                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2964         case IB_QP_SQ_PSN:
2965                 return 0;
2966         case IB_QP_MAX_DEST_RD_ATOMIC:
2967                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2968                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2969         case IB_QP_PATH_MIG_STATE:
2970                 return MLX5_QP_OPTPAR_PM_STATE;
2971         case IB_QP_CAP:
2972                 return 0;
2973         case IB_QP_DEST_QPN:
2974                 return 0;
2975         }
2976         return 0;
2977 }
2978
2979 static int ib_mask_to_mlx5_opt(int ib_mask)
2980 {
2981         int result = 0;
2982         int i;
2983
2984         for (i = 0; i < 8 * sizeof(int); i++) {
2985                 if ((1 << i) & ib_mask)
2986                         result |= ib_nr_to_mlx5_nr(1 << i);
2987         }
2988
2989         return result;
2990 }
2991
2992 static int modify_raw_packet_qp_rq(
2993         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
2994         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
2995 {
2996         void *in;
2997         void *rqc;
2998         int inlen;
2999         int err;
3000
3001         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3002         in = kvzalloc(inlen, GFP_KERNEL);
3003         if (!in)
3004                 return -ENOMEM;
3005
3006         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3007         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3008
3009         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3010         MLX5_SET(rqc, rqc, state, new_state);
3011
3012         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3013                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3014                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
3015                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3016                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3017                 } else
3018                         dev_info_once(
3019                                 &dev->ib_dev.dev,
3020                                 "RAW PACKET QP counters are not supported on current FW\n");
3021         }
3022
3023         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
3024         if (err)
3025                 goto out;
3026
3027         rq->state = new_state;
3028
3029 out:
3030         kvfree(in);
3031         return err;
3032 }
3033
3034 static int modify_raw_packet_qp_sq(
3035         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3036         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3037 {
3038         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3039         struct mlx5_rate_limit old_rl = ibqp->rl;
3040         struct mlx5_rate_limit new_rl = old_rl;
3041         bool new_rate_added = false;
3042         u16 rl_index = 0;
3043         void *in;
3044         void *sqc;
3045         int inlen;
3046         int err;
3047
3048         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3049         in = kvzalloc(inlen, GFP_KERNEL);
3050         if (!in)
3051                 return -ENOMEM;
3052
3053         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3054         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3055
3056         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3057         MLX5_SET(sqc, sqc, state, new_state);
3058
3059         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3060                 if (new_state != MLX5_SQC_STATE_RDY)
3061                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3062                                 __func__);
3063                 else
3064                         new_rl = raw_qp_param->rl;
3065         }
3066
3067         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3068                 if (new_rl.rate) {
3069                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3070                         if (err) {
3071                                 pr_err("Failed configuring rate limit(err %d): \
3072                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3073                                        err, new_rl.rate, new_rl.max_burst_sz,
3074                                        new_rl.typical_pkt_sz);
3075
3076                                 goto out;
3077                         }
3078                         new_rate_added = true;
3079                 }
3080
3081                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3082                 /* index 0 means no limit */
3083                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3084         }
3085
3086         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
3087         if (err) {
3088                 /* Remove new rate from table if failed */
3089                 if (new_rate_added)
3090                         mlx5_rl_remove_rate(dev, &new_rl);
3091                 goto out;
3092         }
3093
3094         /* Only remove the old rate after new rate was set */
3095         if ((old_rl.rate &&
3096              !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3097             (new_state != MLX5_SQC_STATE_RDY))
3098                 mlx5_rl_remove_rate(dev, &old_rl);
3099
3100         ibqp->rl = new_rl;
3101         sq->state = new_state;
3102
3103 out:
3104         kvfree(in);
3105         return err;
3106 }
3107
3108 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3109                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3110                                 u8 tx_affinity)
3111 {
3112         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3113         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3114         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3115         int modify_rq = !!qp->rq.wqe_cnt;
3116         int modify_sq = !!qp->sq.wqe_cnt;
3117         int rq_state;
3118         int sq_state;
3119         int err;
3120
3121         switch (raw_qp_param->operation) {
3122         case MLX5_CMD_OP_RST2INIT_QP:
3123                 rq_state = MLX5_RQC_STATE_RDY;
3124                 sq_state = MLX5_SQC_STATE_RDY;
3125                 break;
3126         case MLX5_CMD_OP_2ERR_QP:
3127                 rq_state = MLX5_RQC_STATE_ERR;
3128                 sq_state = MLX5_SQC_STATE_ERR;
3129                 break;
3130         case MLX5_CMD_OP_2RST_QP:
3131                 rq_state = MLX5_RQC_STATE_RST;
3132                 sq_state = MLX5_SQC_STATE_RST;
3133                 break;
3134         case MLX5_CMD_OP_RTR2RTS_QP:
3135         case MLX5_CMD_OP_RTS2RTS_QP:
3136                 if (raw_qp_param->set_mask ==
3137                     MLX5_RAW_QP_RATE_LIMIT) {
3138                         modify_rq = 0;
3139                         sq_state = sq->state;
3140                 } else {
3141                         return raw_qp_param->set_mask ? -EINVAL : 0;
3142                 }
3143                 break;
3144         case MLX5_CMD_OP_INIT2INIT_QP:
3145         case MLX5_CMD_OP_INIT2RTR_QP:
3146                 if (raw_qp_param->set_mask)
3147                         return -EINVAL;
3148                 else
3149                         return 0;
3150         default:
3151                 WARN_ON(1);
3152                 return -EINVAL;
3153         }
3154
3155         if (modify_rq) {
3156                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3157                                                qp->ibqp.pd);
3158                 if (err)
3159                         return err;
3160         }
3161
3162         if (modify_sq) {
3163                 if (tx_affinity) {
3164                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3165                                                             tx_affinity,
3166                                                             qp->ibqp.pd);
3167                         if (err)
3168                                 return err;
3169                 }
3170
3171                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3172                                                raw_qp_param, qp->ibqp.pd);
3173         }
3174
3175         return 0;
3176 }
3177
3178 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3179                                     struct mlx5_ib_pd *pd,
3180                                     struct mlx5_ib_qp_base *qp_base,
3181                                     u8 port_num)
3182 {
3183         struct mlx5_ib_ucontext *ucontext = NULL;
3184         unsigned int tx_port_affinity;
3185
3186         if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
3187                 ucontext = to_mucontext(pd->ibpd.uobject->context);
3188
3189         if (ucontext) {
3190                 tx_port_affinity = (unsigned int)atomic_add_return(
3191                                            1, &ucontext->tx_port_affinity) %
3192                                            MLX5_MAX_PORTS +
3193                                    1;
3194                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3195                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3196         } else {
3197                 tx_port_affinity =
3198                         (unsigned int)atomic_add_return(
3199                                 1, &dev->roce[port_num].tx_port_affinity) %
3200                                 MLX5_MAX_PORTS +
3201                         1;
3202                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3203                                 tx_port_affinity, qp_base->mqp.qpn);
3204         }
3205
3206         return tx_port_affinity;
3207 }
3208
3209 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3210                                const struct ib_qp_attr *attr, int attr_mask,
3211                                enum ib_qp_state cur_state, enum ib_qp_state new_state,
3212                                const struct mlx5_ib_modify_qp *ucmd)
3213 {
3214         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3215                 [MLX5_QP_STATE_RST] = {
3216                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3217                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3218                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3219                 },
3220                 [MLX5_QP_STATE_INIT]  = {
3221                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3222                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3223                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3224                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3225                 },
3226                 [MLX5_QP_STATE_RTR]   = {
3227                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3228                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3229                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3230                 },
3231                 [MLX5_QP_STATE_RTS]   = {
3232                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3233                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3234                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3235                 },
3236                 [MLX5_QP_STATE_SQD] = {
3237                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3238                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3239                 },
3240                 [MLX5_QP_STATE_SQER] = {
3241                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3242                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3243                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3244                 },
3245                 [MLX5_QP_STATE_ERR] = {
3246                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3247                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3248                 }
3249         };
3250
3251         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3252         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3253         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3254         struct mlx5_ib_cq *send_cq, *recv_cq;
3255         struct mlx5_qp_context *context;
3256         struct mlx5_ib_pd *pd;
3257         struct mlx5_ib_port *mibport = NULL;
3258         enum mlx5_qp_state mlx5_cur, mlx5_new;
3259         enum mlx5_qp_optpar optpar;
3260         int mlx5_st;
3261         int err;
3262         u16 op;
3263         u8 tx_affinity = 0;
3264
3265         mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3266                              qp->qp_sub_type : ibqp->qp_type);
3267         if (mlx5_st < 0)
3268                 return -EINVAL;
3269
3270         context = kzalloc(sizeof(*context), GFP_KERNEL);
3271         if (!context)
3272                 return -ENOMEM;
3273
3274         pd = get_pd(qp);
3275         context->flags = cpu_to_be32(mlx5_st << 16);
3276
3277         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3278                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3279         } else {
3280                 switch (attr->path_mig_state) {
3281                 case IB_MIG_MIGRATED:
3282                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3283                         break;
3284                 case IB_MIG_REARM:
3285                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3286                         break;
3287                 case IB_MIG_ARMED:
3288                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3289                         break;
3290                 }
3291         }
3292
3293         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3294                 if ((ibqp->qp_type == IB_QPT_RC) ||
3295                     (ibqp->qp_type == IB_QPT_UD &&
3296                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3297                     (ibqp->qp_type == IB_QPT_UC) ||
3298                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3299                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3300                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3301                         if (mlx5_lag_is_active(dev->mdev)) {
3302                                 u8 p = mlx5_core_native_port_num(dev->mdev);
3303                                 tx_affinity = get_tx_affinity(dev, pd, base, p);
3304                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3305                         }
3306                 }
3307         }
3308
3309         if (is_sqp(ibqp->qp_type)) {
3310                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3311         } else if ((ibqp->qp_type == IB_QPT_UD &&
3312                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3313                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3314                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3315         } else if (attr_mask & IB_QP_PATH_MTU) {
3316                 if (attr->path_mtu < IB_MTU_256 ||
3317                     attr->path_mtu > IB_MTU_4096) {
3318                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3319                         err = -EINVAL;
3320                         goto out;
3321                 }
3322                 context->mtu_msgmax = (attr->path_mtu << 5) |
3323                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3324         }
3325
3326         if (attr_mask & IB_QP_DEST_QPN)
3327                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3328
3329         if (attr_mask & IB_QP_PKEY_INDEX)
3330                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3331
3332         /* todo implement counter_index functionality */
3333
3334         if (is_sqp(ibqp->qp_type))
3335                 context->pri_path.port = qp->port;
3336
3337         if (attr_mask & IB_QP_PORT)
3338                 context->pri_path.port = attr->port_num;
3339
3340         if (attr_mask & IB_QP_AV) {
3341                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3342                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3343                                     attr_mask, 0, attr, false);
3344                 if (err)
3345                         goto out;
3346         }
3347
3348         if (attr_mask & IB_QP_TIMEOUT)
3349                 context->pri_path.ackto_lt |= attr->timeout << 3;
3350
3351         if (attr_mask & IB_QP_ALT_PATH) {
3352                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3353                                     &context->alt_path,
3354                                     attr->alt_port_num,
3355                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3356                                     0, attr, true);
3357                 if (err)
3358                         goto out;
3359         }
3360
3361         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3362                 &send_cq, &recv_cq);
3363
3364         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3365         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3366         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3367         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3368
3369         if (attr_mask & IB_QP_RNR_RETRY)
3370                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3371
3372         if (attr_mask & IB_QP_RETRY_CNT)
3373                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3374
3375         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3376                 if (attr->max_rd_atomic)
3377                         context->params1 |=
3378                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3379         }
3380
3381         if (attr_mask & IB_QP_SQ_PSN)
3382                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3383
3384         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3385                 if (attr->max_dest_rd_atomic)
3386                         context->params2 |=
3387                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3388         }
3389
3390         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3391                 __be32 access_flags = 0;
3392
3393                 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3394                 if (err)
3395                         goto out;
3396
3397                 context->params2 |= access_flags;
3398         }
3399
3400         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3401                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3402
3403         if (attr_mask & IB_QP_RQ_PSN)
3404                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3405
3406         if (attr_mask & IB_QP_QKEY)
3407                 context->qkey = cpu_to_be32(attr->qkey);
3408
3409         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3410                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3411
3412         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3413                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3414                                qp->port) - 1;
3415
3416                 /* Underlay port should be used - index 0 function per port */
3417                 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3418                         port_num = 0;
3419
3420                 mibport = &dev->port[port_num];
3421                 context->qp_counter_set_usr_page |=
3422                         cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3423         }
3424
3425         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3426                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3427
3428         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3429                 context->deth_sqpn = cpu_to_be32(1);
3430
3431         mlx5_cur = to_mlx5_state(cur_state);
3432         mlx5_new = to_mlx5_state(new_state);
3433
3434         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3435             !optab[mlx5_cur][mlx5_new]) {
3436                 err = -EINVAL;
3437                 goto out;
3438         }
3439
3440         op = optab[mlx5_cur][mlx5_new];
3441         optpar = ib_mask_to_mlx5_opt(attr_mask);
3442         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3443
3444         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3445             qp->flags & MLX5_IB_QP_UNDERLAY) {
3446                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3447
3448                 raw_qp_param.operation = op;
3449                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3450                         raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3451                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3452                 }
3453
3454                 if (attr_mask & IB_QP_RATE_LIMIT) {
3455                         raw_qp_param.rl.rate = attr->rate_limit;
3456
3457                         if (ucmd->burst_info.max_burst_sz) {
3458                                 if (attr->rate_limit &&
3459                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3460                                         raw_qp_param.rl.max_burst_sz =
3461                                                 ucmd->burst_info.max_burst_sz;
3462                                 } else {
3463                                         err = -EINVAL;
3464                                         goto out;
3465                                 }
3466                         }
3467
3468                         if (ucmd->burst_info.typical_pkt_sz) {
3469                                 if (attr->rate_limit &&
3470                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3471                                         raw_qp_param.rl.typical_pkt_sz =
3472                                                 ucmd->burst_info.typical_pkt_sz;
3473                                 } else {
3474                                         err = -EINVAL;
3475                                         goto out;
3476                                 }
3477                         }
3478
3479                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3480                 }
3481
3482                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3483         } else {
3484                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3485                                           &base->mqp);
3486         }
3487
3488         if (err)
3489                 goto out;
3490
3491         qp->state = new_state;
3492
3493         if (attr_mask & IB_QP_ACCESS_FLAGS)
3494                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3495         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3496                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3497         if (attr_mask & IB_QP_PORT)
3498                 qp->port = attr->port_num;
3499         if (attr_mask & IB_QP_ALT_PATH)
3500                 qp->trans_qp.alt_port = attr->alt_port_num;
3501
3502         /*
3503          * If we moved a kernel QP to RESET, clean up all old CQ
3504          * entries and reinitialize the QP.
3505          */
3506         if (new_state == IB_QPS_RESET &&
3507             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3508                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3509                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3510                 if (send_cq != recv_cq)
3511                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3512
3513                 qp->rq.head = 0;
3514                 qp->rq.tail = 0;
3515                 qp->sq.head = 0;
3516                 qp->sq.tail = 0;
3517                 qp->sq.cur_post = 0;
3518                 if (qp->sq.wqe_cnt)
3519                         qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
3520                 qp->sq.last_poll = 0;
3521                 qp->db.db[MLX5_RCV_DBR] = 0;
3522                 qp->db.db[MLX5_SND_DBR] = 0;
3523         }
3524
3525 out:
3526         kfree(context);
3527         return err;
3528 }
3529
3530 static inline bool is_valid_mask(int mask, int req, int opt)
3531 {
3532         if ((mask & req) != req)
3533                 return false;
3534
3535         if (mask & ~(req | opt))
3536                 return false;
3537
3538         return true;
3539 }
3540
3541 /* check valid transition for driver QP types
3542  * for now the only QP type that this function supports is DCI
3543  */
3544 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3545                                 enum ib_qp_attr_mask attr_mask)
3546 {
3547         int req = IB_QP_STATE;
3548         int opt = 0;
3549
3550         if (new_state == IB_QPS_RESET) {
3551                 return is_valid_mask(attr_mask, req, opt);
3552         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3553                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3554                 return is_valid_mask(attr_mask, req, opt);
3555         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3556                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3557                 return is_valid_mask(attr_mask, req, opt);
3558         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3559                 req |= IB_QP_PATH_MTU;
3560                 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
3561                 return is_valid_mask(attr_mask, req, opt);
3562         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3563                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3564                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3565                 opt = IB_QP_MIN_RNR_TIMER;
3566                 return is_valid_mask(attr_mask, req, opt);
3567         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3568                 opt = IB_QP_MIN_RNR_TIMER;
3569                 return is_valid_mask(attr_mask, req, opt);
3570         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3571                 return is_valid_mask(attr_mask, req, opt);
3572         }
3573         return false;
3574 }
3575
3576 /* mlx5_ib_modify_dct: modify a DCT QP
3577  * valid transitions are:
3578  * RESET to INIT: must set access_flags, pkey_index and port
3579  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3580  *                         mtu, gid_index and hop_limit
3581  * Other transitions and attributes are illegal
3582  */
3583 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3584                               int attr_mask, struct ib_udata *udata)
3585 {
3586         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3587         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3588         enum ib_qp_state cur_state, new_state;
3589         int err = 0;
3590         int required = IB_QP_STATE;
3591         void *dctc;
3592
3593         if (!(attr_mask & IB_QP_STATE))
3594                 return -EINVAL;
3595
3596         cur_state = qp->state;
3597         new_state = attr->qp_state;
3598
3599         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3600         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3601                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3602                 if (!is_valid_mask(attr_mask, required, 0))
3603                         return -EINVAL;
3604
3605                 if (attr->port_num == 0 ||
3606                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3607                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3608                                     attr->port_num, dev->num_ports);
3609                         return -EINVAL;
3610                 }
3611                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3612                         MLX5_SET(dctc, dctc, rre, 1);
3613                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3614                         MLX5_SET(dctc, dctc, rwe, 1);
3615                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3616                         int atomic_mode;
3617
3618                         atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3619                         if (atomic_mode < 0)
3620                                 return -EOPNOTSUPP;
3621
3622                         MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
3623                         MLX5_SET(dctc, dctc, rae, 1);
3624                 }
3625                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3626                 MLX5_SET(dctc, dctc, port, attr->port_num);
3627                 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3628
3629         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3630                 struct mlx5_ib_modify_qp_resp resp = {};
3631                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3632                                    sizeof(resp.dctn);
3633
3634                 if (udata->outlen < min_resp_len)
3635                         return -EINVAL;
3636                 resp.response_length = min_resp_len;
3637
3638                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3639                 if (!is_valid_mask(attr_mask, required, 0))
3640                         return -EINVAL;
3641                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3642                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3643                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3644                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3645                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3646                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3647
3648                 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3649                                            MLX5_ST_SZ_BYTES(create_dct_in));
3650                 if (err)
3651                         return err;
3652                 resp.dctn = qp->dct.mdct.mqp.qpn;
3653                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3654                 if (err) {
3655                         mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3656                         return err;
3657                 }
3658         } else {
3659                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3660                 return -EINVAL;
3661         }
3662         if (err)
3663                 qp->state = IB_QPS_ERR;
3664         else
3665                 qp->state = new_state;
3666         return err;
3667 }
3668
3669 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3670                       int attr_mask, struct ib_udata *udata)
3671 {
3672         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3673         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3674         struct mlx5_ib_modify_qp ucmd = {};
3675         enum ib_qp_type qp_type;
3676         enum ib_qp_state cur_state, new_state;
3677         size_t required_cmd_sz;
3678         int err = -EINVAL;
3679         int port;
3680
3681         if (ibqp->rwq_ind_tbl)
3682                 return -ENOSYS;
3683
3684         if (udata && udata->inlen) {
3685                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3686                         sizeof(ucmd.reserved);
3687                 if (udata->inlen < required_cmd_sz)
3688                         return -EINVAL;
3689
3690                 if (udata->inlen > sizeof(ucmd) &&
3691                     !ib_is_udata_cleared(udata, sizeof(ucmd),
3692                                          udata->inlen - sizeof(ucmd)))
3693                         return -EOPNOTSUPP;
3694
3695                 if (ib_copy_from_udata(&ucmd, udata,
3696                                        min(udata->inlen, sizeof(ucmd))))
3697                         return -EFAULT;
3698
3699                 if (ucmd.comp_mask ||
3700                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3701                     memchr_inv(&ucmd.burst_info.reserved, 0,
3702                                sizeof(ucmd.burst_info.reserved)))
3703                         return -EOPNOTSUPP;
3704         }
3705
3706         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3707                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3708
3709         if (ibqp->qp_type == IB_QPT_DRIVER)
3710                 qp_type = qp->qp_sub_type;
3711         else
3712                 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3713                         IB_QPT_GSI : ibqp->qp_type;
3714
3715         if (qp_type == MLX5_IB_QPT_DCT)
3716                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3717
3718         mutex_lock(&qp->mutex);
3719
3720         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3721         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3722
3723         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3724                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3725         }
3726
3727         if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3728                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3729                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3730                                     attr_mask);
3731                         goto out;
3732                 }
3733         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3734                    qp_type != MLX5_IB_QPT_DCI &&
3735                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3736                                        attr_mask)) {
3737                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3738                             cur_state, new_state, ibqp->qp_type, attr_mask);
3739                 goto out;
3740         } else if (qp_type == MLX5_IB_QPT_DCI &&
3741                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3742                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3743                             cur_state, new_state, qp_type, attr_mask);
3744                 goto out;
3745         }
3746
3747         if ((attr_mask & IB_QP_PORT) &&
3748             (attr->port_num == 0 ||
3749              attr->port_num > dev->num_ports)) {
3750                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3751                             attr->port_num, dev->num_ports);
3752                 goto out;
3753         }
3754
3755         if (attr_mask & IB_QP_PKEY_INDEX) {
3756                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3757                 if (attr->pkey_index >=
3758                     dev->mdev->port_caps[port - 1].pkey_table_len) {
3759                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3760                                     attr->pkey_index);
3761                         goto out;
3762                 }
3763         }
3764
3765         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3766             attr->max_rd_atomic >
3767             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3768                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3769                             attr->max_rd_atomic);
3770                 goto out;
3771         }
3772
3773         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3774             attr->max_dest_rd_atomic >
3775             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3776                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3777                             attr->max_dest_rd_atomic);
3778                 goto out;
3779         }
3780
3781         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3782                 err = 0;
3783                 goto out;
3784         }
3785
3786         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3787                                   new_state, &ucmd);
3788
3789 out:
3790         mutex_unlock(&qp->mutex);
3791         return err;
3792 }
3793
3794 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3795                                    u32 wqe_sz, void **cur_edge)
3796 {
3797         u32 idx;
3798
3799         idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
3800         *cur_edge = get_sq_edge(sq, idx);
3801
3802         *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
3803 }
3804
3805 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
3806  * next nearby edge and get new address translation for current WQE position.
3807  * @sq - SQ buffer.
3808  * @seg: Current WQE position (16B aligned).
3809  * @wqe_sz: Total current WQE size [16B].
3810  * @cur_edge: Updated current edge.
3811  */
3812 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3813                                          u32 wqe_sz, void **cur_edge)
3814 {
3815         if (likely(*seg != *cur_edge))
3816                 return;
3817
3818         _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
3819 }
3820
3821 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
3822  * pointers. At the end @seg is aligned to 16B regardless the copied size.
3823  * @sq - SQ buffer.
3824  * @cur_edge: Updated current edge.
3825  * @seg: Current WQE position (16B aligned).
3826  * @wqe_sz: Total current WQE size [16B].
3827  * @src: Pointer to copy from.
3828  * @n: Number of bytes to copy.
3829  */
3830 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
3831                                    void **seg, u32 *wqe_sz, const void *src,
3832                                    size_t n)
3833 {
3834         while (likely(n)) {
3835                 size_t leftlen = *cur_edge - *seg;
3836                 size_t copysz = min_t(size_t, leftlen, n);
3837                 size_t stride;
3838
3839                 memcpy(*seg, src, copysz);
3840
3841                 n -= copysz;
3842                 src += copysz;
3843                 stride = !n ? ALIGN(copysz, 16) : copysz;
3844                 *seg += stride;
3845                 *wqe_sz += stride >> 4;
3846                 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
3847         }
3848 }
3849
3850 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3851 {
3852         struct mlx5_ib_cq *cq;
3853         unsigned cur;
3854
3855         cur = wq->head - wq->tail;
3856         if (likely(cur + nreq < wq->max_post))
3857                 return 0;
3858
3859         cq = to_mcq(ib_cq);
3860         spin_lock(&cq->lock);
3861         cur = wq->head - wq->tail;
3862         spin_unlock(&cq->lock);
3863
3864         return cur + nreq >= wq->max_post;
3865 }
3866
3867 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3868                                           u64 remote_addr, u32 rkey)
3869 {
3870         rseg->raddr    = cpu_to_be64(remote_addr);
3871         rseg->rkey     = cpu_to_be32(rkey);
3872         rseg->reserved = 0;
3873 }
3874
3875 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
3876                         void **seg, int *size, void **cur_edge)
3877 {
3878         struct mlx5_wqe_eth_seg *eseg = *seg;
3879
3880         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3881
3882         if (wr->send_flags & IB_SEND_IP_CSUM)
3883                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3884                                  MLX5_ETH_WQE_L4_CSUM;
3885
3886         if (wr->opcode == IB_WR_LSO) {
3887                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3888                 size_t left, copysz;
3889                 void *pdata = ud_wr->header;
3890                 size_t stride;
3891
3892                 left = ud_wr->hlen;
3893                 eseg->mss = cpu_to_be16(ud_wr->mss);
3894                 eseg->inline_hdr.sz = cpu_to_be16(left);
3895
3896                 /* memcpy_send_wqe should get a 16B align address. Hence, we
3897                  * first copy up to the current edge and then, if needed,
3898                  * fall-through to memcpy_send_wqe.
3899                  */
3900                 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
3901                                left);
3902                 memcpy(eseg->inline_hdr.start, pdata, copysz);
3903                 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
3904                                sizeof(eseg->inline_hdr.start) + copysz, 16);
3905                 *size += stride / 16;
3906                 *seg += stride;
3907
3908                 if (copysz < left) {
3909                         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
3910                         left -= copysz;
3911                         pdata += copysz;
3912                         memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
3913                                         left);
3914                 }
3915
3916                 return;
3917         }
3918
3919         *seg += sizeof(struct mlx5_wqe_eth_seg);
3920         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3921 }
3922
3923 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3924                              const struct ib_send_wr *wr)
3925 {
3926         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3927         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3928         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3929 }
3930
3931 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3932 {
3933         dseg->byte_count = cpu_to_be32(sg->length);
3934         dseg->lkey       = cpu_to_be32(sg->lkey);
3935         dseg->addr       = cpu_to_be64(sg->addr);
3936 }
3937
3938 static u64 get_xlt_octo(u64 bytes)
3939 {
3940         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3941                MLX5_IB_UMR_OCTOWORD;
3942 }
3943
3944 static __be64 frwr_mkey_mask(void)
3945 {
3946         u64 result;
3947
3948         result = MLX5_MKEY_MASK_LEN             |
3949                 MLX5_MKEY_MASK_PAGE_SIZE        |
3950                 MLX5_MKEY_MASK_START_ADDR       |
3951                 MLX5_MKEY_MASK_EN_RINVAL        |
3952                 MLX5_MKEY_MASK_KEY              |
3953                 MLX5_MKEY_MASK_LR               |
3954                 MLX5_MKEY_MASK_LW               |
3955                 MLX5_MKEY_MASK_RR               |
3956                 MLX5_MKEY_MASK_RW               |
3957                 MLX5_MKEY_MASK_A                |
3958                 MLX5_MKEY_MASK_SMALL_FENCE      |
3959                 MLX5_MKEY_MASK_FREE;
3960
3961         return cpu_to_be64(result);
3962 }
3963
3964 static __be64 sig_mkey_mask(void)
3965 {
3966         u64 result;
3967
3968         result = MLX5_MKEY_MASK_LEN             |
3969                 MLX5_MKEY_MASK_PAGE_SIZE        |
3970                 MLX5_MKEY_MASK_START_ADDR       |
3971                 MLX5_MKEY_MASK_EN_SIGERR        |
3972                 MLX5_MKEY_MASK_EN_RINVAL        |
3973                 MLX5_MKEY_MASK_KEY              |
3974                 MLX5_MKEY_MASK_LR               |
3975                 MLX5_MKEY_MASK_LW               |
3976                 MLX5_MKEY_MASK_RR               |
3977                 MLX5_MKEY_MASK_RW               |
3978                 MLX5_MKEY_MASK_SMALL_FENCE      |
3979                 MLX5_MKEY_MASK_FREE             |
3980                 MLX5_MKEY_MASK_BSF_EN;
3981
3982         return cpu_to_be64(result);
3983 }
3984
3985 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3986                             struct mlx5_ib_mr *mr, bool umr_inline)
3987 {
3988         int size = mr->ndescs * mr->desc_size;
3989
3990         memset(umr, 0, sizeof(*umr));
3991
3992         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3993         if (umr_inline)
3994                 umr->flags |= MLX5_UMR_INLINE;
3995         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3996         umr->mkey_mask = frwr_mkey_mask();
3997 }
3998
3999 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
4000 {
4001         memset(umr, 0, sizeof(*umr));
4002         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
4003         umr->flags = MLX5_UMR_INLINE;
4004 }
4005
4006 static __be64 get_umr_enable_mr_mask(void)
4007 {
4008         u64 result;
4009
4010         result = MLX5_MKEY_MASK_KEY |
4011                  MLX5_MKEY_MASK_FREE;
4012
4013         return cpu_to_be64(result);
4014 }
4015
4016 static __be64 get_umr_disable_mr_mask(void)
4017 {
4018         u64 result;
4019
4020         result = MLX5_MKEY_MASK_FREE;
4021
4022         return cpu_to_be64(result);
4023 }
4024
4025 static __be64 get_umr_update_translation_mask(void)
4026 {
4027         u64 result;
4028
4029         result = MLX5_MKEY_MASK_LEN |
4030                  MLX5_MKEY_MASK_PAGE_SIZE |
4031                  MLX5_MKEY_MASK_START_ADDR;
4032
4033         return cpu_to_be64(result);
4034 }
4035
4036 static __be64 get_umr_update_access_mask(int atomic)
4037 {
4038         u64 result;
4039
4040         result = MLX5_MKEY_MASK_LR |
4041                  MLX5_MKEY_MASK_LW |
4042                  MLX5_MKEY_MASK_RR |
4043                  MLX5_MKEY_MASK_RW;
4044
4045         if (atomic)
4046                 result |= MLX5_MKEY_MASK_A;
4047
4048         return cpu_to_be64(result);
4049 }
4050
4051 static __be64 get_umr_update_pd_mask(void)
4052 {
4053         u64 result;
4054
4055         result = MLX5_MKEY_MASK_PD;
4056
4057         return cpu_to_be64(result);
4058 }
4059
4060 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4061 {
4062         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4063              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4064             (mask & MLX5_MKEY_MASK_A &&
4065              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4066                 return -EPERM;
4067         return 0;
4068 }
4069
4070 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4071                                struct mlx5_wqe_umr_ctrl_seg *umr,
4072                                const struct ib_send_wr *wr, int atomic)
4073 {
4074         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4075
4076         memset(umr, 0, sizeof(*umr));
4077
4078         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4079                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
4080         else
4081                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
4082
4083         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4084         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4085                 u64 offset = get_xlt_octo(umrwr->offset);
4086
4087                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4088                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4089                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
4090         }
4091         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4092                 umr->mkey_mask |= get_umr_update_translation_mask();
4093         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4094                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4095                 umr->mkey_mask |= get_umr_update_pd_mask();
4096         }
4097         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4098                 umr->mkey_mask |= get_umr_enable_mr_mask();
4099         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4100                 umr->mkey_mask |= get_umr_disable_mr_mask();
4101
4102         if (!wr->num_sge)
4103                 umr->flags |= MLX5_UMR_INLINE;
4104
4105         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
4106 }
4107
4108 static u8 get_umr_flags(int acc)
4109 {
4110         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
4111                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
4112                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
4113                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
4114                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
4115 }
4116
4117 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4118                              struct mlx5_ib_mr *mr,
4119                              u32 key, int access)
4120 {
4121         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
4122
4123         memset(seg, 0, sizeof(*seg));
4124
4125         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
4126                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
4127         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
4128                 /* KLMs take twice the size of MTTs */
4129                 ndescs *= 2;
4130
4131         seg->flags = get_umr_flags(access) | mr->access_mode;
4132         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4133         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4134         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4135         seg->len = cpu_to_be64(mr->ibmr.length);
4136         seg->xlt_oct_size = cpu_to_be32(ndescs);
4137 }
4138
4139 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
4140 {
4141         memset(seg, 0, sizeof(*seg));
4142         seg->status = MLX5_MKEY_STATUS_FREE;
4143 }
4144
4145 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4146                                  const struct ib_send_wr *wr)
4147 {
4148         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4149
4150         memset(seg, 0, sizeof(*seg));
4151         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4152                 seg->status = MLX5_MKEY_STATUS_FREE;
4153
4154         seg->flags = convert_access(umrwr->access_flags);
4155         if (umrwr->pd)
4156                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4157         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4158             !umrwr->length)
4159                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4160
4161         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
4162         seg->len = cpu_to_be64(umrwr->length);
4163         seg->log2_page_size = umrwr->page_shift;
4164         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4165                                        mlx5_mkey_variant(umrwr->mkey));
4166 }
4167
4168 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4169                              struct mlx5_ib_mr *mr,
4170                              struct mlx5_ib_pd *pd)
4171 {
4172         int bcount = mr->desc_size * mr->ndescs;
4173
4174         dseg->addr = cpu_to_be64(mr->desc_map);
4175         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4176         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4177 }
4178
4179 static __be32 send_ieth(const struct ib_send_wr *wr)
4180 {
4181         switch (wr->opcode) {
4182         case IB_WR_SEND_WITH_IMM:
4183         case IB_WR_RDMA_WRITE_WITH_IMM:
4184                 return wr->ex.imm_data;
4185
4186         case IB_WR_SEND_WITH_INV:
4187                 return cpu_to_be32(wr->ex.invalidate_rkey);
4188
4189         default:
4190                 return 0;
4191         }
4192 }
4193
4194 static u8 calc_sig(void *wqe, int size)
4195 {
4196         u8 *p = wqe;
4197         u8 res = 0;
4198         int i;
4199
4200         for (i = 0; i < size; i++)
4201                 res ^= p[i];
4202
4203         return ~res;
4204 }
4205
4206 static u8 wq_sig(void *wqe)
4207 {
4208         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4209 }
4210
4211 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4212                             void **wqe, int *wqe_sz, void **cur_edge)
4213 {
4214         struct mlx5_wqe_inline_seg *seg;
4215         size_t offset;
4216         int inl = 0;
4217         int i;
4218
4219         seg = *wqe;
4220         *wqe += sizeof(*seg);
4221         offset = sizeof(*seg);
4222
4223         for (i = 0; i < wr->num_sge; i++) {
4224                 size_t len  = wr->sg_list[i].length;
4225                 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4226
4227                 inl += len;
4228
4229                 if (unlikely(inl > qp->max_inline_data))
4230                         return -ENOMEM;
4231
4232                 while (likely(len)) {
4233                         size_t leftlen;
4234                         size_t copysz;
4235
4236                         handle_post_send_edge(&qp->sq, wqe,
4237                                               *wqe_sz + (offset >> 4),
4238                                               cur_edge);
4239
4240                         leftlen = *cur_edge - *wqe;
4241                         copysz = min_t(size_t, leftlen, len);
4242
4243                         memcpy(*wqe, addr, copysz);
4244                         len -= copysz;
4245                         addr += copysz;
4246                         *wqe += copysz;
4247                         offset += copysz;
4248                 }
4249         }
4250
4251         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4252
4253         *wqe_sz +=  ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4254
4255         return 0;
4256 }
4257
4258 static u16 prot_field_size(enum ib_signature_type type)
4259 {
4260         switch (type) {
4261         case IB_SIG_TYPE_T10_DIF:
4262                 return MLX5_DIF_SIZE;
4263         default:
4264                 return 0;
4265         }
4266 }
4267
4268 static u8 bs_selector(int block_size)
4269 {
4270         switch (block_size) {
4271         case 512:           return 0x1;
4272         case 520:           return 0x2;
4273         case 4096:          return 0x3;
4274         case 4160:          return 0x4;
4275         case 1073741824:    return 0x5;
4276         default:            return 0;
4277         }
4278 }
4279
4280 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4281                               struct mlx5_bsf_inl *inl)
4282 {
4283         /* Valid inline section and allow BSF refresh */
4284         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4285                                        MLX5_BSF_REFRESH_DIF);
4286         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4287         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4288         /* repeating block */
4289         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4290         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4291                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
4292
4293         if (domain->sig.dif.ref_remap)
4294                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4295
4296         if (domain->sig.dif.app_escape) {
4297                 if (domain->sig.dif.ref_escape)
4298                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4299                 else
4300                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4301         }
4302
4303         inl->dif_app_bitmask_check =
4304                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4305 }
4306
4307 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4308                         struct ib_sig_attrs *sig_attrs,
4309                         struct mlx5_bsf *bsf, u32 data_size)
4310 {
4311         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4312         struct mlx5_bsf_basic *basic = &bsf->basic;
4313         struct ib_sig_domain *mem = &sig_attrs->mem;
4314         struct ib_sig_domain *wire = &sig_attrs->wire;
4315
4316         memset(bsf, 0, sizeof(*bsf));
4317
4318         /* Basic + Extended + Inline */
4319         basic->bsf_size_sbs = 1 << 7;
4320         /* Input domain check byte mask */
4321         basic->check_byte_mask = sig_attrs->check_mask;
4322         basic->raw_data_size = cpu_to_be32(data_size);
4323
4324         /* Memory domain */
4325         switch (sig_attrs->mem.sig_type) {
4326         case IB_SIG_TYPE_NONE:
4327                 break;
4328         case IB_SIG_TYPE_T10_DIF:
4329                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4330                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4331                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4332                 break;
4333         default:
4334                 return -EINVAL;
4335         }
4336
4337         /* Wire domain */
4338         switch (sig_attrs->wire.sig_type) {
4339         case IB_SIG_TYPE_NONE:
4340                 break;
4341         case IB_SIG_TYPE_T10_DIF:
4342                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4343                     mem->sig_type == wire->sig_type) {
4344                         /* Same block structure */
4345                         basic->bsf_size_sbs |= 1 << 4;
4346                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4347                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4348                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4349                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4350                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4351                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4352                 } else
4353                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4354
4355                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4356                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4357                 break;
4358         default:
4359                 return -EINVAL;
4360         }
4361
4362         return 0;
4363 }
4364
4365 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
4366                                 struct mlx5_ib_qp *qp, void **seg,
4367                                 int *size, void **cur_edge)
4368 {
4369         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4370         struct ib_mr *sig_mr = wr->sig_mr;
4371         struct mlx5_bsf *bsf;
4372         u32 data_len = wr->wr.sg_list->length;
4373         u32 data_key = wr->wr.sg_list->lkey;
4374         u64 data_va = wr->wr.sg_list->addr;
4375         int ret;
4376         int wqe_size;
4377
4378         if (!wr->prot ||
4379             (data_key == wr->prot->lkey &&
4380              data_va == wr->prot->addr &&
4381              data_len == wr->prot->length)) {
4382                 /**
4383                  * Source domain doesn't contain signature information
4384                  * or data and protection are interleaved in memory.
4385                  * So need construct:
4386                  *                  ------------------
4387                  *                 |     data_klm     |
4388                  *                  ------------------
4389                  *                 |       BSF        |
4390                  *                  ------------------
4391                  **/
4392                 struct mlx5_klm *data_klm = *seg;
4393
4394                 data_klm->bcount = cpu_to_be32(data_len);
4395                 data_klm->key = cpu_to_be32(data_key);
4396                 data_klm->va = cpu_to_be64(data_va);
4397                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4398         } else {
4399                 /**
4400                  * Source domain contains signature information
4401                  * So need construct a strided block format:
4402                  *               ---------------------------
4403                  *              |     stride_block_ctrl     |
4404                  *               ---------------------------
4405                  *              |          data_klm         |
4406                  *               ---------------------------
4407                  *              |          prot_klm         |
4408                  *               ---------------------------
4409                  *              |             BSF           |
4410                  *               ---------------------------
4411                  **/
4412                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4413                 struct mlx5_stride_block_entry *data_sentry;
4414                 struct mlx5_stride_block_entry *prot_sentry;
4415                 u32 prot_key = wr->prot->lkey;
4416                 u64 prot_va = wr->prot->addr;
4417                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4418                 int prot_size;
4419
4420                 sblock_ctrl = *seg;
4421                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4422                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4423
4424                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4425                 if (!prot_size) {
4426                         pr_err("Bad block size given: %u\n", block_size);
4427                         return -EINVAL;
4428                 }
4429                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4430                                                             prot_size);
4431                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4432                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4433                 sblock_ctrl->num_entries = cpu_to_be16(2);
4434
4435                 data_sentry->bcount = cpu_to_be16(block_size);
4436                 data_sentry->key = cpu_to_be32(data_key);
4437                 data_sentry->va = cpu_to_be64(data_va);
4438                 data_sentry->stride = cpu_to_be16(block_size);
4439
4440                 prot_sentry->bcount = cpu_to_be16(prot_size);
4441                 prot_sentry->key = cpu_to_be32(prot_key);
4442                 prot_sentry->va = cpu_to_be64(prot_va);
4443                 prot_sentry->stride = cpu_to_be16(prot_size);
4444
4445                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4446                                  sizeof(*prot_sentry), 64);
4447         }
4448
4449         *seg += wqe_size;
4450         *size += wqe_size / 16;
4451         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4452
4453         bsf = *seg;
4454         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4455         if (ret)
4456                 return -EINVAL;
4457
4458         *seg += sizeof(*bsf);
4459         *size += sizeof(*bsf) / 16;
4460         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4461
4462         return 0;
4463 }
4464
4465 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4466                                  const struct ib_sig_handover_wr *wr, u32 size,
4467                                  u32 length, u32 pdn)
4468 {
4469         struct ib_mr *sig_mr = wr->sig_mr;
4470         u32 sig_key = sig_mr->rkey;
4471         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4472
4473         memset(seg, 0, sizeof(*seg));
4474
4475         seg->flags = get_umr_flags(wr->access_flags) |
4476                                    MLX5_MKC_ACCESS_MODE_KLMS;
4477         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4478         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4479                                     MLX5_MKEY_BSF_EN | pdn);
4480         seg->len = cpu_to_be64(length);
4481         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4482         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4483 }
4484
4485 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4486                                 u32 size)
4487 {
4488         memset(umr, 0, sizeof(*umr));
4489
4490         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4491         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4492         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4493         umr->mkey_mask = sig_mkey_mask();
4494 }
4495
4496
4497 static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
4498                           struct mlx5_ib_qp *qp, void **seg, int *size,
4499                           void **cur_edge)
4500 {
4501         const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4502         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4503         u32 pdn = get_pd(qp)->pdn;
4504         u32 xlt_size;
4505         int region_len, ret;
4506
4507         if (unlikely(wr->wr.num_sge != 1) ||
4508             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4509             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4510             unlikely(!sig_mr->sig->sig_status_checked))
4511                 return -EINVAL;
4512
4513         /* length of the protected region, data + protection */
4514         region_len = wr->wr.sg_list->length;
4515         if (wr->prot &&
4516             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
4517              wr->prot->addr != wr->wr.sg_list->addr  ||
4518              wr->prot->length != wr->wr.sg_list->length))
4519                 region_len += wr->prot->length;
4520
4521         /**
4522          * KLM octoword size - if protection was provided
4523          * then we use strided block format (3 octowords),
4524          * else we use single KLM (1 octoword)
4525          **/
4526         xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4527
4528         set_sig_umr_segment(*seg, xlt_size);
4529         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4530         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4531         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4532
4533         set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4534         *seg += sizeof(struct mlx5_mkey_seg);
4535         *size += sizeof(struct mlx5_mkey_seg) / 16;
4536         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4537
4538         ret = set_sig_data_segment(wr, qp, seg, size, cur_edge);
4539         if (ret)
4540                 return ret;
4541
4542         sig_mr->sig->sig_status_checked = false;
4543         return 0;
4544 }
4545
4546 static int set_psv_wr(struct ib_sig_domain *domain,
4547                       u32 psv_idx, void **seg, int *size)
4548 {
4549         struct mlx5_seg_set_psv *psv_seg = *seg;
4550
4551         memset(psv_seg, 0, sizeof(*psv_seg));
4552         psv_seg->psv_num = cpu_to_be32(psv_idx);
4553         switch (domain->sig_type) {
4554         case IB_SIG_TYPE_NONE:
4555                 break;
4556         case IB_SIG_TYPE_T10_DIF:
4557                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4558                                                      domain->sig.dif.app_tag);
4559                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4560                 break;
4561         default:
4562                 pr_err("Bad signature type (%d) is given.\n",
4563                        domain->sig_type);
4564                 return -EINVAL;
4565         }
4566
4567         *seg += sizeof(*psv_seg);
4568         *size += sizeof(*psv_seg) / 16;
4569
4570         return 0;
4571 }
4572
4573 static int set_reg_wr(struct mlx5_ib_qp *qp,
4574                       const struct ib_reg_wr *wr,
4575                       void **seg, int *size, void **cur_edge)
4576 {
4577         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4578         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4579         size_t mr_list_size = mr->ndescs * mr->desc_size;
4580         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4581
4582         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4583                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4584                              "Invalid IB_SEND_INLINE send flag\n");
4585                 return -EINVAL;
4586         }
4587
4588         set_reg_umr_seg(*seg, mr, umr_inline);
4589         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4590         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4591         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4592
4593         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4594         *seg += sizeof(struct mlx5_mkey_seg);
4595         *size += sizeof(struct mlx5_mkey_seg) / 16;
4596         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4597
4598         if (umr_inline) {
4599                 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4600                                 mr_list_size);
4601                 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
4602         } else {
4603                 set_reg_data_seg(*seg, mr, pd);
4604                 *seg += sizeof(struct mlx5_wqe_data_seg);
4605                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4606         }
4607         return 0;
4608 }
4609
4610 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4611                         void **cur_edge)
4612 {
4613         set_linv_umr_seg(*seg);
4614         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4615         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4616         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4617         set_linv_mkey_seg(*seg);
4618         *seg += sizeof(struct mlx5_mkey_seg);
4619         *size += sizeof(struct mlx5_mkey_seg) / 16;
4620         handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4621 }
4622
4623 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
4624 {
4625         __be32 *p = NULL;
4626         u32 tidx = idx;
4627         int i, j;
4628
4629         pr_debug("dump WQE index %u:\n", idx);
4630         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4631                 if ((i & 0xf) == 0) {
4632                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4633                         p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, tidx);
4634                         pr_debug("WQBB at %p:\n", (void *)p);
4635                         j = 0;
4636                 }
4637                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4638                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4639                          be32_to_cpu(p[j + 3]));
4640         }
4641 }
4642
4643 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4644                        struct mlx5_wqe_ctrl_seg **ctrl,
4645                        const struct ib_send_wr *wr, unsigned int *idx,
4646                        int *size, void **cur_edge, int nreq,
4647                        bool send_signaled, bool solicited)
4648 {
4649         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4650                 return -ENOMEM;
4651
4652         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4653         *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
4654         *ctrl = *seg;
4655         *(uint32_t *)(*seg + 8) = 0;
4656         (*ctrl)->imm = send_ieth(wr);
4657         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4658                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4659                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4660
4661         *seg += sizeof(**ctrl);
4662         *size = sizeof(**ctrl) / 16;
4663         *cur_edge = qp->sq.cur_edge;
4664
4665         return 0;
4666 }
4667
4668 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4669                      struct mlx5_wqe_ctrl_seg **ctrl,
4670                      const struct ib_send_wr *wr, unsigned *idx,
4671                      int *size, void **cur_edge, int nreq)
4672 {
4673         return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
4674                            wr->send_flags & IB_SEND_SIGNALED,
4675                            wr->send_flags & IB_SEND_SOLICITED);
4676 }
4677
4678 static void finish_wqe(struct mlx5_ib_qp *qp,
4679                        struct mlx5_wqe_ctrl_seg *ctrl,
4680                        void *seg, u8 size, void *cur_edge,
4681                        unsigned int idx, u64 wr_id, int nreq, u8 fence,
4682                        u32 mlx5_opcode)
4683 {
4684         u8 opmod = 0;
4685
4686         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4687                                              mlx5_opcode | ((u32)opmod << 24));
4688         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4689         ctrl->fm_ce_se |= fence;
4690         if (unlikely(qp->wq_sig))
4691                 ctrl->signature = wq_sig(ctrl);
4692
4693         qp->sq.wrid[idx] = wr_id;
4694         qp->sq.w_list[idx].opcode = mlx5_opcode;
4695         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4696         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4697         qp->sq.w_list[idx].next = qp->sq.cur_post;
4698
4699         /* We save the edge which was possibly updated during the WQE
4700          * construction, into SQ's cache.
4701          */
4702         seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
4703         qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
4704                           get_sq_edge(&qp->sq, qp->sq.cur_post &
4705                                       (qp->sq.wqe_cnt - 1)) :
4706                           cur_edge;
4707 }
4708
4709 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4710                               const struct ib_send_wr **bad_wr, bool drain)
4711 {
4712         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
4713         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4714         struct mlx5_core_dev *mdev = dev->mdev;
4715         struct mlx5_ib_qp *qp;
4716         struct mlx5_ib_mr *mr;
4717         struct mlx5_wqe_xrc_seg *xrc;
4718         struct mlx5_bf *bf;
4719         void *cur_edge;
4720         int uninitialized_var(size);
4721         unsigned long flags;
4722         unsigned idx;
4723         int err = 0;
4724         int num_sge;
4725         void *seg;
4726         int nreq;
4727         int i;
4728         u8 next_fence = 0;
4729         u8 fence;
4730
4731         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4732                      !drain)) {
4733                 *bad_wr = wr;
4734                 return -EIO;
4735         }
4736
4737         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4738                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4739
4740         qp = to_mqp(ibqp);
4741         bf = &qp->bf;
4742
4743         spin_lock_irqsave(&qp->sq.lock, flags);
4744
4745         for (nreq = 0; wr; nreq++, wr = wr->next) {
4746                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4747                         mlx5_ib_warn(dev, "\n");
4748                         err = -EINVAL;
4749                         *bad_wr = wr;
4750                         goto out;
4751                 }
4752
4753                 num_sge = wr->num_sge;
4754                 if (unlikely(num_sge > qp->sq.max_gs)) {
4755                         mlx5_ib_warn(dev, "\n");
4756                         err = -EINVAL;
4757                         *bad_wr = wr;
4758                         goto out;
4759                 }
4760
4761                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
4762                                 nreq);
4763                 if (err) {
4764                         mlx5_ib_warn(dev, "\n");
4765                         err = -ENOMEM;
4766                         *bad_wr = wr;
4767                         goto out;
4768                 }
4769
4770                 if (wr->opcode == IB_WR_LOCAL_INV ||
4771                     wr->opcode == IB_WR_REG_MR) {
4772                         fence = dev->umr_fence;
4773                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4774                 } else if (wr->send_flags & IB_SEND_FENCE) {
4775                         if (qp->next_fence)
4776                                 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4777                         else
4778                                 fence = MLX5_FENCE_MODE_FENCE;
4779                 } else {
4780                         fence = qp->next_fence;
4781                 }
4782
4783                 switch (ibqp->qp_type) {
4784                 case IB_QPT_XRC_INI:
4785                         xrc = seg;
4786                         seg += sizeof(*xrc);
4787                         size += sizeof(*xrc) / 16;
4788                         /* fall through */
4789                 case IB_QPT_RC:
4790                         switch (wr->opcode) {
4791                         case IB_WR_RDMA_READ:
4792                         case IB_WR_RDMA_WRITE:
4793                         case IB_WR_RDMA_WRITE_WITH_IMM:
4794                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4795                                               rdma_wr(wr)->rkey);
4796                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
4797                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4798                                 break;
4799
4800                         case IB_WR_ATOMIC_CMP_AND_SWP:
4801                         case IB_WR_ATOMIC_FETCH_AND_ADD:
4802                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4803                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4804                                 err = -ENOSYS;
4805                                 *bad_wr = wr;
4806                                 goto out;
4807
4808                         case IB_WR_LOCAL_INV:
4809                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4810                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4811                                 set_linv_wr(qp, &seg, &size, &cur_edge);
4812                                 num_sge = 0;
4813                                 break;
4814
4815                         case IB_WR_REG_MR:
4816                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4817                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4818                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
4819                                                  &cur_edge);
4820                                 if (err) {
4821                                         *bad_wr = wr;
4822                                         goto out;
4823                                 }
4824                                 num_sge = 0;
4825                                 break;
4826
4827                         case IB_WR_REG_SIG_MR:
4828                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4829                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4830
4831                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4832                                 err = set_sig_umr_wr(wr, qp, &seg, &size,
4833                                                      &cur_edge);
4834                                 if (err) {
4835                                         mlx5_ib_warn(dev, "\n");
4836                                         *bad_wr = wr;
4837                                         goto out;
4838                                 }
4839
4840                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4841                                            wr->wr_id, nreq, fence,
4842                                            MLX5_OPCODE_UMR);
4843                                 /*
4844                                  * SET_PSV WQEs are not signaled and solicited
4845                                  * on error
4846                                  */
4847                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4848                                                   &size, &cur_edge, nreq, false,
4849                                                   true);
4850                                 if (err) {
4851                                         mlx5_ib_warn(dev, "\n");
4852                                         err = -ENOMEM;
4853                                         *bad_wr = wr;
4854                                         goto out;
4855                                 }
4856
4857                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4858                                                  mr->sig->psv_memory.psv_idx, &seg,
4859                                                  &size);
4860                                 if (err) {
4861                                         mlx5_ib_warn(dev, "\n");
4862                                         *bad_wr = wr;
4863                                         goto out;
4864                                 }
4865
4866                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4867                                            wr->wr_id, nreq, fence,
4868                                            MLX5_OPCODE_SET_PSV);
4869                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4870                                                   &size, &cur_edge, nreq, false,
4871                                                   true);
4872                                 if (err) {
4873                                         mlx5_ib_warn(dev, "\n");
4874                                         err = -ENOMEM;
4875                                         *bad_wr = wr;
4876                                         goto out;
4877                                 }
4878
4879                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4880                                                  mr->sig->psv_wire.psv_idx, &seg,
4881                                                  &size);
4882                                 if (err) {
4883                                         mlx5_ib_warn(dev, "\n");
4884                                         *bad_wr = wr;
4885                                         goto out;
4886                                 }
4887
4888                                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4889                                            wr->wr_id, nreq, fence,
4890                                            MLX5_OPCODE_SET_PSV);
4891                                 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4892                                 num_sge = 0;
4893                                 goto skip_psv;
4894
4895                         default:
4896                                 break;
4897                         }
4898                         break;
4899
4900                 case IB_QPT_UC:
4901                         switch (wr->opcode) {
4902                         case IB_WR_RDMA_WRITE:
4903                         case IB_WR_RDMA_WRITE_WITH_IMM:
4904                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4905                                               rdma_wr(wr)->rkey);
4906                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
4907                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4908                                 break;
4909
4910                         default:
4911                                 break;
4912                         }
4913                         break;
4914
4915                 case IB_QPT_SMI:
4916                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4917                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4918                                 err = -EPERM;
4919                                 *bad_wr = wr;
4920                                 goto out;
4921                         }
4922                         /* fall through */
4923                 case MLX5_IB_QPT_HW_GSI:
4924                         set_datagram_seg(seg, wr);
4925                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4926                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4927                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
4928
4929                         break;
4930                 case IB_QPT_UD:
4931                         set_datagram_seg(seg, wr);
4932                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4933                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4934                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
4935
4936                         /* handle qp that supports ud offload */
4937                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4938                                 struct mlx5_wqe_eth_pad *pad;
4939
4940                                 pad = seg;
4941                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4942                                 seg += sizeof(struct mlx5_wqe_eth_pad);
4943                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4944                                 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
4945                                 handle_post_send_edge(&qp->sq, &seg, size,
4946                                                       &cur_edge);
4947                         }
4948                         break;
4949                 case MLX5_IB_QPT_REG_UMR:
4950                         if (wr->opcode != MLX5_IB_WR_UMR) {
4951                                 err = -EINVAL;
4952                                 mlx5_ib_warn(dev, "bad opcode\n");
4953                                 goto out;
4954                         }
4955                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4956                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4957                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4958                         if (unlikely(err))
4959                                 goto out;
4960                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4961                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4962                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
4963                         set_reg_mkey_segment(seg, wr);
4964                         seg += sizeof(struct mlx5_mkey_seg);
4965                         size += sizeof(struct mlx5_mkey_seg) / 16;
4966                         handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
4967                         break;
4968
4969                 default:
4970                         break;
4971                 }
4972
4973                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4974                         err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
4975                         if (unlikely(err)) {
4976                                 mlx5_ib_warn(dev, "\n");
4977                                 *bad_wr = wr;
4978                                 goto out;
4979                         }
4980                 } else {
4981                         for (i = 0; i < num_sge; i++) {
4982                                 handle_post_send_edge(&qp->sq, &seg, size,
4983                                                       &cur_edge);
4984                                 if (likely(wr->sg_list[i].length)) {
4985                                         set_data_ptr_seg
4986                                         ((struct mlx5_wqe_data_seg *)seg,
4987                                          wr->sg_list + i);
4988                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
4989                                         seg += sizeof(struct mlx5_wqe_data_seg);
4990                                 }
4991                         }
4992                 }
4993
4994                 qp->next_fence = next_fence;
4995                 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
4996                            fence, mlx5_ib_opcode[wr->opcode]);
4997 skip_psv:
4998                 if (0)
4999                         dump_wqe(qp, idx, size);
5000         }
5001
5002 out:
5003         if (likely(nreq)) {
5004                 qp->sq.head += nreq;
5005
5006                 /* Make sure that descriptors are written before
5007                  * updating doorbell record and ringing the doorbell
5008                  */
5009                 wmb();
5010
5011                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5012
5013                 /* Make sure doorbell record is visible to the HCA before
5014                  * we hit doorbell */
5015                 wmb();
5016
5017                 /* currently we support only regular doorbells */
5018                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
5019                 /* Make sure doorbells don't leak out of SQ spinlock
5020                  * and reach the HCA out of order.
5021                  */
5022                 mmiowb();
5023                 bf->offset ^= bf->buf_size;
5024         }
5025
5026         spin_unlock_irqrestore(&qp->sq.lock, flags);
5027
5028         return err;
5029 }
5030
5031 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5032                       const struct ib_send_wr **bad_wr)
5033 {
5034         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5035 }
5036
5037 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5038 {
5039         sig->signature = calc_sig(sig, size);
5040 }
5041
5042 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5043                       const struct ib_recv_wr **bad_wr, bool drain)
5044 {
5045         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5046         struct mlx5_wqe_data_seg *scat;
5047         struct mlx5_rwqe_sig *sig;
5048         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5049         struct mlx5_core_dev *mdev = dev->mdev;
5050         unsigned long flags;
5051         int err = 0;
5052         int nreq;
5053         int ind;
5054         int i;
5055
5056         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5057                      !drain)) {
5058                 *bad_wr = wr;
5059                 return -EIO;
5060         }
5061
5062         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5063                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5064
5065         spin_lock_irqsave(&qp->rq.lock, flags);
5066
5067         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5068
5069         for (nreq = 0; wr; nreq++, wr = wr->next) {
5070                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5071                         err = -ENOMEM;
5072                         *bad_wr = wr;
5073                         goto out;
5074                 }
5075
5076                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5077                         err = -EINVAL;
5078                         *bad_wr = wr;
5079                         goto out;
5080                 }
5081
5082                 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
5083                 if (qp->wq_sig)
5084                         scat++;
5085
5086                 for (i = 0; i < wr->num_sge; i++)
5087                         set_data_ptr_seg(scat + i, wr->sg_list + i);
5088
5089                 if (i < qp->rq.max_gs) {
5090                         scat[i].byte_count = 0;
5091                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
5092                         scat[i].addr       = 0;
5093                 }
5094
5095                 if (qp->wq_sig) {
5096                         sig = (struct mlx5_rwqe_sig *)scat;
5097                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5098                 }
5099
5100                 qp->rq.wrid[ind] = wr->wr_id;
5101
5102                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5103         }
5104
5105 out:
5106         if (likely(nreq)) {
5107                 qp->rq.head += nreq;
5108
5109                 /* Make sure that descriptors are written before
5110                  * doorbell record.
5111                  */
5112                 wmb();
5113
5114                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5115         }
5116
5117         spin_unlock_irqrestore(&qp->rq.lock, flags);
5118
5119         return err;
5120 }
5121
5122 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5123                       const struct ib_recv_wr **bad_wr)
5124 {
5125         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5126 }
5127
5128 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5129 {
5130         switch (mlx5_state) {
5131         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
5132         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
5133         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
5134         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
5135         case MLX5_QP_STATE_SQ_DRAINING:
5136         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
5137         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
5138         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
5139         default:                     return -1;
5140         }
5141 }
5142
5143 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5144 {
5145         switch (mlx5_mig_state) {
5146         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
5147         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
5148         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
5149         default: return -1;
5150         }
5151 }
5152
5153 static int to_ib_qp_access_flags(int mlx5_flags)
5154 {
5155         int ib_flags = 0;
5156
5157         if (mlx5_flags & MLX5_QP_BIT_RRE)
5158                 ib_flags |= IB_ACCESS_REMOTE_READ;
5159         if (mlx5_flags & MLX5_QP_BIT_RWE)
5160                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5161         if (mlx5_flags & MLX5_QP_BIT_RAE)
5162                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5163
5164         return ib_flags;
5165 }
5166
5167 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5168                             struct rdma_ah_attr *ah_attr,
5169                             struct mlx5_qp_path *path)
5170 {
5171
5172         memset(ah_attr, 0, sizeof(*ah_attr));
5173
5174         if (!path->port || path->port > ibdev->num_ports)
5175                 return;
5176
5177         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5178
5179         rdma_ah_set_port_num(ah_attr, path->port);
5180         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5181
5182         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5183         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5184         rdma_ah_set_static_rate(ah_attr,
5185                                 path->static_rate ? path->static_rate - 5 : 0);
5186         if (path->grh_mlid & (1 << 7)) {
5187                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5188
5189                 rdma_ah_set_grh(ah_attr, NULL,
5190                                 tc_fl & 0xfffff,
5191                                 path->mgid_index,
5192                                 path->hop_limit,
5193                                 (tc_fl >> 20) & 0xff);
5194                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5195         }
5196 }
5197
5198 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5199                                         struct mlx5_ib_sq *sq,
5200                                         u8 *sq_state)
5201 {
5202         int err;
5203
5204         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5205         if (err)
5206                 goto out;
5207         sq->state = *sq_state;
5208
5209 out:
5210         return err;
5211 }
5212
5213 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5214                                         struct mlx5_ib_rq *rq,
5215                                         u8 *rq_state)
5216 {
5217         void *out;
5218         void *rqc;
5219         int inlen;
5220         int err;
5221
5222         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5223         out = kvzalloc(inlen, GFP_KERNEL);
5224         if (!out)
5225                 return -ENOMEM;
5226
5227         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5228         if (err)
5229                 goto out;
5230
5231         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5232         *rq_state = MLX5_GET(rqc, rqc, state);
5233         rq->state = *rq_state;
5234
5235 out:
5236         kvfree(out);
5237         return err;
5238 }
5239
5240 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5241                                   struct mlx5_ib_qp *qp, u8 *qp_state)
5242 {
5243         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5244                 [MLX5_RQC_STATE_RST] = {
5245                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5246                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5247                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
5248                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
5249                 },
5250                 [MLX5_RQC_STATE_RDY] = {
5251                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5252                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5253                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
5254                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
5255                 },
5256                 [MLX5_RQC_STATE_ERR] = {
5257                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5258                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5259                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
5260                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
5261                 },
5262                 [MLX5_RQ_STATE_NA] = {
5263                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5264                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5265                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
5266                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
5267                 },
5268         };
5269
5270         *qp_state = sqrq_trans[rq_state][sq_state];
5271
5272         if (*qp_state == MLX5_QP_STATE_BAD) {
5273                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5274                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5275                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5276                 return -EINVAL;
5277         }
5278
5279         if (*qp_state == MLX5_QP_STATE)
5280                 *qp_state = qp->state;
5281
5282         return 0;
5283 }
5284
5285 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5286                                      struct mlx5_ib_qp *qp,
5287                                      u8 *raw_packet_qp_state)
5288 {
5289         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5290         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5291         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5292         int err;
5293         u8 sq_state = MLX5_SQ_STATE_NA;
5294         u8 rq_state = MLX5_RQ_STATE_NA;
5295
5296         if (qp->sq.wqe_cnt) {
5297                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5298                 if (err)
5299                         return err;
5300         }
5301
5302         if (qp->rq.wqe_cnt) {
5303                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5304                 if (err)
5305                         return err;
5306         }
5307
5308         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5309                                       raw_packet_qp_state);
5310 }
5311
5312 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5313                          struct ib_qp_attr *qp_attr)
5314 {
5315         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5316         struct mlx5_qp_context *context;
5317         int mlx5_state;
5318         u32 *outb;
5319         int err = 0;
5320
5321         outb = kzalloc(outlen, GFP_KERNEL);
5322         if (!outb)
5323                 return -ENOMEM;
5324
5325         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
5326                                  outlen);
5327         if (err)
5328                 goto out;
5329
5330         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5331         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5332
5333         mlx5_state = be32_to_cpu(context->flags) >> 28;
5334
5335         qp->state                    = to_ib_qp_state(mlx5_state);
5336         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5337         qp_attr->path_mig_state      =
5338                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5339         qp_attr->qkey                = be32_to_cpu(context->qkey);
5340         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5341         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5342         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5343         qp_attr->qp_access_flags     =
5344                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5345
5346         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5347                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5348                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5349                 qp_attr->alt_pkey_index =
5350                         be16_to_cpu(context->alt_path.pkey_index);
5351                 qp_attr->alt_port_num   =
5352                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5353         }
5354
5355         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5356         qp_attr->port_num = context->pri_path.port;
5357
5358         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5359         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5360
5361         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5362
5363         qp_attr->max_dest_rd_atomic =
5364                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5365         qp_attr->min_rnr_timer      =
5366                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5367         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5368         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5369         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5370         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5371
5372 out:
5373         kfree(outb);
5374         return err;
5375 }
5376
5377 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5378                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5379                                 struct ib_qp_init_attr *qp_init_attr)
5380 {
5381         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5382         u32 *out;
5383         u32 access_flags = 0;
5384         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5385         void *dctc;
5386         int err;
5387         int supported_mask = IB_QP_STATE |
5388                              IB_QP_ACCESS_FLAGS |
5389                              IB_QP_PORT |
5390                              IB_QP_MIN_RNR_TIMER |
5391                              IB_QP_AV |
5392                              IB_QP_PATH_MTU |
5393                              IB_QP_PKEY_INDEX;
5394
5395         if (qp_attr_mask & ~supported_mask)
5396                 return -EINVAL;
5397         if (mqp->state != IB_QPS_RTR)
5398                 return -EINVAL;
5399
5400         out = kzalloc(outlen, GFP_KERNEL);
5401         if (!out)
5402                 return -ENOMEM;
5403
5404         err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5405         if (err)
5406                 goto out;
5407
5408         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5409
5410         if (qp_attr_mask & IB_QP_STATE)
5411                 qp_attr->qp_state = IB_QPS_RTR;
5412
5413         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5414                 if (MLX5_GET(dctc, dctc, rre))
5415                         access_flags |= IB_ACCESS_REMOTE_READ;
5416                 if (MLX5_GET(dctc, dctc, rwe))
5417                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5418                 if (MLX5_GET(dctc, dctc, rae))
5419                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5420                 qp_attr->qp_access_flags = access_flags;
5421         }
5422
5423         if (qp_attr_mask & IB_QP_PORT)
5424                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5425         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5426                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5427         if (qp_attr_mask & IB_QP_AV) {
5428                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5429                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5430                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5431                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5432         }
5433         if (qp_attr_mask & IB_QP_PATH_MTU)
5434                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5435         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5436                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5437 out:
5438         kfree(out);
5439         return err;
5440 }
5441
5442 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5443                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5444 {
5445         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5446         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5447         int err = 0;
5448         u8 raw_packet_qp_state;
5449
5450         if (ibqp->rwq_ind_tbl)
5451                 return -ENOSYS;
5452
5453         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5454                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5455                                             qp_init_attr);
5456
5457         /* Not all of output fields are applicable, make sure to zero them */
5458         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5459         memset(qp_attr, 0, sizeof(*qp_attr));
5460
5461         if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5462                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5463                                             qp_attr_mask, qp_init_attr);
5464
5465         mutex_lock(&qp->mutex);
5466
5467         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5468             qp->flags & MLX5_IB_QP_UNDERLAY) {
5469                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5470                 if (err)
5471                         goto out;
5472                 qp->state = raw_packet_qp_state;
5473                 qp_attr->port_num = 1;
5474         } else {
5475                 err = query_qp_attr(dev, qp, qp_attr);
5476                 if (err)
5477                         goto out;
5478         }
5479
5480         qp_attr->qp_state            = qp->state;
5481         qp_attr->cur_qp_state        = qp_attr->qp_state;
5482         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5483         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5484
5485         if (!ibqp->uobject) {
5486                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5487                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5488                 qp_init_attr->qp_context = ibqp->qp_context;
5489         } else {
5490                 qp_attr->cap.max_send_wr  = 0;
5491                 qp_attr->cap.max_send_sge = 0;
5492         }
5493
5494         qp_init_attr->qp_type = ibqp->qp_type;
5495         qp_init_attr->recv_cq = ibqp->recv_cq;
5496         qp_init_attr->send_cq = ibqp->send_cq;
5497         qp_init_attr->srq = ibqp->srq;
5498         qp_attr->cap.max_inline_data = qp->max_inline_data;
5499
5500         qp_init_attr->cap            = qp_attr->cap;
5501
5502         qp_init_attr->create_flags = 0;
5503         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5504                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5505
5506         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5507                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5508         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5509                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5510         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5511                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5512         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5513                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5514
5515         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5516                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5517
5518 out:
5519         mutex_unlock(&qp->mutex);
5520         return err;
5521 }
5522
5523 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5524                                           struct ib_ucontext *context,
5525                                           struct ib_udata *udata)
5526 {
5527         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5528         struct mlx5_ib_xrcd *xrcd;
5529         int err;
5530
5531         if (!MLX5_CAP_GEN(dev->mdev, xrc))
5532                 return ERR_PTR(-ENOSYS);
5533
5534         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5535         if (!xrcd)
5536                 return ERR_PTR(-ENOMEM);
5537
5538         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
5539         if (err) {
5540                 kfree(xrcd);
5541                 return ERR_PTR(-ENOMEM);
5542         }
5543
5544         return &xrcd->ibxrcd;
5545 }
5546
5547 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5548 {
5549         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5550         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5551         int err;
5552
5553         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
5554         if (err)
5555                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5556
5557         kfree(xrcd);
5558         return 0;
5559 }
5560
5561 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5562 {
5563         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5564         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5565         struct ib_event event;
5566
5567         if (rwq->ibwq.event_handler) {
5568                 event.device     = rwq->ibwq.device;
5569                 event.element.wq = &rwq->ibwq;
5570                 switch (type) {
5571                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5572                         event.event = IB_EVENT_WQ_FATAL;
5573                         break;
5574                 default:
5575                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5576                         return;
5577                 }
5578
5579                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5580         }
5581 }
5582
5583 static int set_delay_drop(struct mlx5_ib_dev *dev)
5584 {
5585         int err = 0;
5586
5587         mutex_lock(&dev->delay_drop.lock);
5588         if (dev->delay_drop.activate)
5589                 goto out;
5590
5591         err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5592         if (err)
5593                 goto out;
5594
5595         dev->delay_drop.activate = true;
5596 out:
5597         mutex_unlock(&dev->delay_drop.lock);
5598
5599         if (!err)
5600                 atomic_inc(&dev->delay_drop.rqs_cnt);
5601         return err;
5602 }
5603
5604 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5605                       struct ib_wq_init_attr *init_attr)
5606 {
5607         struct mlx5_ib_dev *dev;
5608         int has_net_offloads;
5609         __be64 *rq_pas0;
5610         void *in;
5611         void *rqc;
5612         void *wq;
5613         int inlen;
5614         int err;
5615
5616         dev = to_mdev(pd->device);
5617
5618         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5619         in = kvzalloc(inlen, GFP_KERNEL);
5620         if (!in)
5621                 return -ENOMEM;
5622
5623         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5624         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5625         MLX5_SET(rqc,  rqc, mem_rq_type,
5626                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5627         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5628         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5629         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
5630         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
5631         wq = MLX5_ADDR_OF(rqc, rqc, wq);
5632         MLX5_SET(wq, wq, wq_type,
5633                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5634                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5635         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5636                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5637                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5638                         err = -EOPNOTSUPP;
5639                         goto out;
5640                 } else {
5641                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5642                 }
5643         }
5644         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5645         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5646                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5647                 MLX5_SET(wq, wq, log_wqe_stride_size,
5648                          rwq->single_stride_log_num_of_bytes -
5649                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5650                 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5651                          MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5652         }
5653         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5654         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5655         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5656         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5657         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5658         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5659         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5660         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5661                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5662                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5663                         err = -EOPNOTSUPP;
5664                         goto out;
5665                 }
5666         } else {
5667                 MLX5_SET(rqc, rqc, vsd, 1);
5668         }
5669         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5670                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5671                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5672                         err = -EOPNOTSUPP;
5673                         goto out;
5674                 }
5675                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5676         }
5677         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5678                 if (!(dev->ib_dev.attrs.raw_packet_caps &
5679                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
5680                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5681                         err = -EOPNOTSUPP;
5682                         goto out;
5683                 }
5684                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5685         }
5686         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5687         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5688         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5689         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5690                 err = set_delay_drop(dev);
5691                 if (err) {
5692                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5693                                      err);
5694                         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5695                 } else {
5696                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5697                 }
5698         }
5699 out:
5700         kvfree(in);
5701         return err;
5702 }
5703
5704 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5705                             struct ib_wq_init_attr *wq_init_attr,
5706                             struct mlx5_ib_create_wq *ucmd,
5707                             struct mlx5_ib_rwq *rwq)
5708 {
5709         /* Sanity check RQ size before proceeding */
5710         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5711                 return -EINVAL;
5712
5713         if (!ucmd->rq_wqe_count)
5714                 return -EINVAL;
5715
5716         rwq->wqe_count = ucmd->rq_wqe_count;
5717         rwq->wqe_shift = ucmd->rq_wqe_shift;
5718         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5719                 return -EINVAL;
5720
5721         rwq->log_rq_stride = rwq->wqe_shift;
5722         rwq->log_rq_size = ilog2(rwq->wqe_count);
5723         return 0;
5724 }
5725
5726 static int prepare_user_rq(struct ib_pd *pd,
5727                            struct ib_wq_init_attr *init_attr,
5728                            struct ib_udata *udata,
5729                            struct mlx5_ib_rwq *rwq)
5730 {
5731         struct mlx5_ib_dev *dev = to_mdev(pd->device);
5732         struct mlx5_ib_create_wq ucmd = {};
5733         int err;
5734         size_t required_cmd_sz;
5735
5736         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5737                 + sizeof(ucmd.single_stride_log_num_of_bytes);
5738         if (udata->inlen < required_cmd_sz) {
5739                 mlx5_ib_dbg(dev, "invalid inlen\n");
5740                 return -EINVAL;
5741         }
5742
5743         if (udata->inlen > sizeof(ucmd) &&
5744             !ib_is_udata_cleared(udata, sizeof(ucmd),
5745                                  udata->inlen - sizeof(ucmd))) {
5746                 mlx5_ib_dbg(dev, "inlen is not supported\n");
5747                 return -EOPNOTSUPP;
5748         }
5749
5750         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5751                 mlx5_ib_dbg(dev, "copy failed\n");
5752                 return -EFAULT;
5753         }
5754
5755         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5756                 mlx5_ib_dbg(dev, "invalid comp mask\n");
5757                 return -EOPNOTSUPP;
5758         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5759                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5760                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5761                         return -EOPNOTSUPP;
5762                 }
5763                 if ((ucmd.single_stride_log_num_of_bytes <
5764                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5765                     (ucmd.single_stride_log_num_of_bytes >
5766                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5767                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5768                                     ucmd.single_stride_log_num_of_bytes,
5769                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5770                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5771                         return -EINVAL;
5772                 }
5773                 if ((ucmd.single_wqe_log_num_of_strides >
5774                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5775                      (ucmd.single_wqe_log_num_of_strides <
5776                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5777                         mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5778                                     ucmd.single_wqe_log_num_of_strides,
5779                                     MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5780                                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5781                         return -EINVAL;
5782                 }
5783                 rwq->single_stride_log_num_of_bytes =
5784                         ucmd.single_stride_log_num_of_bytes;
5785                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5786                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5787                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5788         }
5789
5790         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5791         if (err) {
5792                 mlx5_ib_dbg(dev, "err %d\n", err);
5793                 return err;
5794         }
5795
5796         err = create_user_rq(dev, pd, rwq, &ucmd);
5797         if (err) {
5798                 mlx5_ib_dbg(dev, "err %d\n", err);
5799                 return err;
5800         }
5801
5802         rwq->user_index = ucmd.user_index;
5803         return 0;
5804 }
5805
5806 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5807                                 struct ib_wq_init_attr *init_attr,
5808                                 struct ib_udata *udata)
5809 {
5810         struct mlx5_ib_dev *dev;
5811         struct mlx5_ib_rwq *rwq;
5812         struct mlx5_ib_create_wq_resp resp = {};
5813         size_t min_resp_len;
5814         int err;
5815
5816         if (!udata)
5817                 return ERR_PTR(-ENOSYS);
5818
5819         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5820         if (udata->outlen && udata->outlen < min_resp_len)
5821                 return ERR_PTR(-EINVAL);
5822
5823         dev = to_mdev(pd->device);
5824         switch (init_attr->wq_type) {
5825         case IB_WQT_RQ:
5826                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5827                 if (!rwq)
5828                         return ERR_PTR(-ENOMEM);
5829                 err = prepare_user_rq(pd, init_attr, udata, rwq);
5830                 if (err)
5831                         goto err;
5832                 err = create_rq(rwq, pd, init_attr);
5833                 if (err)
5834                         goto err_user_rq;
5835                 break;
5836         default:
5837                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5838                             init_attr->wq_type);
5839                 return ERR_PTR(-EINVAL);
5840         }
5841
5842         rwq->ibwq.wq_num = rwq->core_qp.qpn;
5843         rwq->ibwq.state = IB_WQS_RESET;
5844         if (udata->outlen) {
5845                 resp.response_length = offsetof(typeof(resp), response_length) +
5846                                 sizeof(resp.response_length);
5847                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5848                 if (err)
5849                         goto err_copy;
5850         }
5851
5852         rwq->core_qp.event = mlx5_ib_wq_event;
5853         rwq->ibwq.event_handler = init_attr->event_handler;
5854         return &rwq->ibwq;
5855
5856 err_copy:
5857         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5858 err_user_rq:
5859         destroy_user_rq(dev, pd, rwq);
5860 err:
5861         kfree(rwq);
5862         return ERR_PTR(err);
5863 }
5864
5865 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5866 {
5867         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5868         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5869
5870         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5871         destroy_user_rq(dev, wq->pd, rwq);
5872         kfree(rwq);
5873
5874         return 0;
5875 }
5876
5877 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5878                                                       struct ib_rwq_ind_table_init_attr *init_attr,
5879                                                       struct ib_udata *udata)
5880 {
5881         struct mlx5_ib_dev *dev = to_mdev(device);
5882         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5883         int sz = 1 << init_attr->log_ind_tbl_size;
5884         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5885         size_t min_resp_len;
5886         int inlen;
5887         int err;
5888         int i;
5889         u32 *in;
5890         void *rqtc;
5891
5892         if (udata->inlen > 0 &&
5893             !ib_is_udata_cleared(udata, 0,
5894                                  udata->inlen))
5895                 return ERR_PTR(-EOPNOTSUPP);
5896
5897         if (init_attr->log_ind_tbl_size >
5898             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5899                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5900                             init_attr->log_ind_tbl_size,
5901                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5902                 return ERR_PTR(-EINVAL);
5903         }
5904
5905         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5906         if (udata->outlen && udata->outlen < min_resp_len)
5907                 return ERR_PTR(-EINVAL);
5908
5909         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5910         if (!rwq_ind_tbl)
5911                 return ERR_PTR(-ENOMEM);
5912
5913         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5914         in = kvzalloc(inlen, GFP_KERNEL);
5915         if (!in) {
5916                 err = -ENOMEM;
5917                 goto err;
5918         }
5919
5920         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5921
5922         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5923         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5924
5925         for (i = 0; i < sz; i++)
5926                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5927
5928         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5929         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5930
5931         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5932         kvfree(in);
5933
5934         if (err)
5935                 goto err;
5936
5937         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5938         if (udata->outlen) {
5939                 resp.response_length = offsetof(typeof(resp), response_length) +
5940                                         sizeof(resp.response_length);
5941                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5942                 if (err)
5943                         goto err_copy;
5944         }
5945
5946         return &rwq_ind_tbl->ib_rwq_ind_tbl;
5947
5948 err_copy:
5949         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5950 err:
5951         kfree(rwq_ind_tbl);
5952         return ERR_PTR(err);
5953 }
5954
5955 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5956 {
5957         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5958         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5959
5960         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5961
5962         kfree(rwq_ind_tbl);
5963         return 0;
5964 }
5965
5966 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5967                       u32 wq_attr_mask, struct ib_udata *udata)
5968 {
5969         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5970         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5971         struct mlx5_ib_modify_wq ucmd = {};
5972         size_t required_cmd_sz;
5973         int curr_wq_state;
5974         int wq_state;
5975         int inlen;
5976         int err;
5977         void *rqc;
5978         void *in;
5979
5980         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5981         if (udata->inlen < required_cmd_sz)
5982                 return -EINVAL;
5983
5984         if (udata->inlen > sizeof(ucmd) &&
5985             !ib_is_udata_cleared(udata, sizeof(ucmd),
5986                                  udata->inlen - sizeof(ucmd)))
5987                 return -EOPNOTSUPP;
5988
5989         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5990                 return -EFAULT;
5991
5992         if (ucmd.comp_mask || ucmd.reserved)
5993                 return -EOPNOTSUPP;
5994
5995         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5996         in = kvzalloc(inlen, GFP_KERNEL);
5997         if (!in)
5998                 return -ENOMEM;
5999
6000         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
6001
6002         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
6003                 wq_attr->curr_wq_state : wq->state;
6004         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6005                 wq_attr->wq_state : curr_wq_state;
6006         if (curr_wq_state == IB_WQS_ERR)
6007                 curr_wq_state = MLX5_RQC_STATE_ERR;
6008         if (wq_state == IB_WQS_ERR)
6009                 wq_state = MLX5_RQC_STATE_ERR;
6010         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
6011         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
6012         MLX5_SET(rqc, rqc, state, wq_state);
6013
6014         if (wq_attr_mask & IB_WQ_FLAGS) {
6015                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6016                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6017                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6018                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
6019                                             "supported\n");
6020                                 err = -EOPNOTSUPP;
6021                                 goto out;
6022                         }
6023                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6024                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6025                         MLX5_SET(rqc, rqc, vsd,
6026                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6027                 }
6028
6029                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6030                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6031                         err = -EOPNOTSUPP;
6032                         goto out;
6033                 }
6034         }
6035
6036         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6037                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6038                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
6039                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
6040                         MLX5_SET(rqc, rqc, counter_set_id,
6041                                  dev->port->cnts.set_id);
6042                 } else
6043                         dev_info_once(
6044                                 &dev->ib_dev.dev,
6045                                 "Receive WQ counters are not supported on current FW\n");
6046         }
6047
6048         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
6049         if (!err)
6050                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6051
6052 out:
6053         kvfree(in);
6054         return err;
6055 }
6056
6057 struct mlx5_ib_drain_cqe {
6058         struct ib_cqe cqe;
6059         struct completion done;
6060 };
6061
6062 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6063 {
6064         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6065                                                      struct mlx5_ib_drain_cqe,
6066                                                      cqe);
6067
6068         complete(&cqe->done);
6069 }
6070
6071 /* This function returns only once the drained WR was completed */
6072 static void handle_drain_completion(struct ib_cq *cq,
6073                                     struct mlx5_ib_drain_cqe *sdrain,
6074                                     struct mlx5_ib_dev *dev)
6075 {
6076         struct mlx5_core_dev *mdev = dev->mdev;
6077
6078         if (cq->poll_ctx == IB_POLL_DIRECT) {
6079                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6080                         ib_process_cq_direct(cq, -1);
6081                 return;
6082         }
6083
6084         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6085                 struct mlx5_ib_cq *mcq = to_mcq(cq);
6086                 bool triggered = false;
6087                 unsigned long flags;
6088
6089                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6090                 /* Make sure that the CQ handler won't run if wasn't run yet */
6091                 if (!mcq->mcq.reset_notify_added)
6092                         mcq->mcq.reset_notify_added = 1;
6093                 else
6094                         triggered = true;
6095                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6096
6097                 if (triggered) {
6098                         /* Wait for any scheduled/running task to be ended */
6099                         switch (cq->poll_ctx) {
6100                         case IB_POLL_SOFTIRQ:
6101                                 irq_poll_disable(&cq->iop);
6102                                 irq_poll_enable(&cq->iop);
6103                                 break;
6104                         case IB_POLL_WORKQUEUE:
6105                                 cancel_work_sync(&cq->work);
6106                                 break;
6107                         default:
6108                                 WARN_ON_ONCE(1);
6109                         }
6110                 }
6111
6112                 /* Run the CQ handler - this makes sure that the drain WR will
6113                  * be processed if wasn't processed yet.
6114                  */
6115                 mcq->mcq.comp(&mcq->mcq);
6116         }
6117
6118         wait_for_completion(&sdrain->done);
6119 }
6120
6121 void mlx5_ib_drain_sq(struct ib_qp *qp)
6122 {
6123         struct ib_cq *cq = qp->send_cq;
6124         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6125         struct mlx5_ib_drain_cqe sdrain;
6126         const struct ib_send_wr *bad_swr;
6127         struct ib_rdma_wr swr = {
6128                 .wr = {
6129                         .next = NULL,
6130                         { .wr_cqe       = &sdrain.cqe, },
6131                         .opcode = IB_WR_RDMA_WRITE,
6132                 },
6133         };
6134         int ret;
6135         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6136         struct mlx5_core_dev *mdev = dev->mdev;
6137
6138         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6139         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6140                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6141                 return;
6142         }
6143
6144         sdrain.cqe.done = mlx5_ib_drain_qp_done;
6145         init_completion(&sdrain.done);
6146
6147         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6148         if (ret) {
6149                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6150                 return;
6151         }
6152
6153         handle_drain_completion(cq, &sdrain, dev);
6154 }
6155
6156 void mlx5_ib_drain_rq(struct ib_qp *qp)
6157 {
6158         struct ib_cq *cq = qp->recv_cq;
6159         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6160         struct mlx5_ib_drain_cqe rdrain;
6161         struct ib_recv_wr rwr = {};
6162         const struct ib_recv_wr *bad_rwr;
6163         int ret;
6164         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6165         struct mlx5_core_dev *mdev = dev->mdev;
6166
6167         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6168         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6169                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6170                 return;
6171         }
6172
6173         rwr.wr_cqe = &rdrain.cqe;
6174         rdrain.cqe.done = mlx5_ib_drain_qp_done;
6175         init_completion(&rdrain.done);
6176
6177         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6178         if (ret) {
6179                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6180                 return;
6181         }
6182
6183         handle_drain_completion(cq, &rdrain, dev);
6184 }