drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include <rdma/ib_cache.h>
  36 #include <rdma/ib_user_verbs.h>
  37 #include <linux/mlx5/fs.h>
  38 #include "mlx5_ib.h"
  39 #include "ib_rep.h"
  40 #include "cmd.h"
  41
  42 /* not supported currently */
  43 static int wq_signature;
  44
  45 enum {
  46         MLX5_IB_ACK_REQ_FREQ    = 8,
  47 };
  48
  49 enum {
  50         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  51         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  52         MLX5_IB_LINK_TYPE_IB            = 0,
  53         MLX5_IB_LINK_TYPE_ETH           = 1
  54 };
  55
  56 enum {
  57         MLX5_IB_SQ_STRIDE       = 6,
  58         MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
  59 };
  60
  61 static const u32 mlx5_ib_opcode[] = {
  62         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  63         [IB_WR_LSO]                             = MLX5_OPCODE_LSO,
  64         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  65         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  66         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  67         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  68         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  69         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  70         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  71         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  72         [IB_WR_REG_MR]                          = MLX5_OPCODE_UMR,
  73         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  74         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  75         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  76 };
  77
  78 struct mlx5_wqe_eth_pad {
  79         u8 rsvd0[16];
  80 };
  81
  82 enum raw_qp_set_mask_map {
  83         MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID         = 1UL << 0,
  84         MLX5_RAW_QP_RATE_LIMIT                  = 1UL << 1,
  85 };
  86
  87 struct mlx5_modify_raw_qp_param {
  88         u16 operation;
  89
  90         u32 set_mask; /* raw_qp_set_mask_map */
  91
  92         struct mlx5_rate_limit rl;
  93
  94         u8 rq_q_ctr_id;
  95 };
  96
  97 static void get_cqs(enum ib_qp_type qp_type,
  98                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
  99                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
 100
 101 static int is_qp0(enum ib_qp_type qp_type)
 102 {
 103         return qp_type == IB_QPT_SMI;
 104 }
 105
 106 static int is_sqp(enum ib_qp_type qp_type)
 107 {
 108         return is_qp0(qp_type) || is_qp1(qp_type);
 109 }
 110
 111 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
 112 {
 113         return mlx5_buf_offset(&qp->buf, offset);
 114 }
 115
 116 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 117 {
 118         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 119 }
 120
 121 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 122 {
 123         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 124 }
 125
 126 /**
 127  * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
 128  *
 129  * @qp: QP to copy from.
 130  * @send: copy from the send queue when non-zero, use the receive queue
 131  *        otherwise.
 132  * @wqe_index:  index to start copying from. For send work queues, the
 133  *              wqe_index is in units of MLX5_SEND_WQE_BB.
 134  *              For receive work queue, it is the number of work queue
 135  *              element in the queue.
 136  * @buffer: destination buffer.
 137  * @length: maximum number of bytes to copy.
 138  *
 139  * Copies at least a single WQE, but may copy more data.
 140  *
 141  * Return: the number of bytes copied, or an error code.
 142  */
 143 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
 144                           void *buffer, u32 length,
 145                           struct mlx5_ib_qp_base *base)
 146 {
 147         struct ib_device *ibdev = qp->ibqp.device;
 148         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 149         struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
 150         size_t offset;
 151         size_t wq_end;
 152         struct ib_umem *umem = base->ubuffer.umem;
 153         u32 first_copy_length;
 154         int wqe_length;
 155         int ret;
 156
 157         if (wq->wqe_cnt == 0) {
 158                 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
 159                             qp->ibqp.qp_type);
 160                 return -EINVAL;
 161         }
 162
 163         offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
 164         wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
 165
 166         if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
 167                 return -EINVAL;
 168
 169         if (offset > umem->length ||
 170             (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
 171                 return -EINVAL;
 172
 173         first_copy_length = min_t(u32, offset + length, wq_end) - offset;
 174         ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
 175         if (ret)
 176                 return ret;
 177
 178         if (send) {
 179                 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
 180                 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
 181
 182                 wqe_length = ds * MLX5_WQE_DS_UNITS;
 183         } else {
 184                 wqe_length = 1 << wq->wqe_shift;
 185         }
 186
 187         if (wqe_length <= first_copy_length)
 188                 return first_copy_length;
 189
 190         ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
 191                                 wqe_length - first_copy_length);
 192         if (ret)
 193                 return ret;
 194
 195         return wqe_length;
 196 }
 197
 198 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 199 {
 200         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 201         struct ib_event event;
 202
 203         if (type == MLX5_EVENT_TYPE_PATH_MIG) {
 204                 /* This event is only valid for trans_qps */
 205                 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
 206         }
 207
 208         if (ibqp->event_handler) {
 209                 event.device     = ibqp->device;
 210                 event.element.qp = ibqp;
 211                 switch (type) {
 212                 case MLX5_EVENT_TYPE_PATH_MIG:
 213                         event.event = IB_EVENT_PATH_MIG;
 214                         break;
 215                 case MLX5_EVENT_TYPE_COMM_EST:
 216                         event.event = IB_EVENT_COMM_EST;
 217                         break;
 218                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 219                         event.event = IB_EVENT_SQ_DRAINED;
 220                         break;
 221                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 222                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 223                         break;
 224                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 225                         event.event = IB_EVENT_QP_FATAL;
 226                         break;
 227                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 228                         event.event = IB_EVENT_PATH_MIG_ERR;
 229                         break;
 230                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 231                         event.event = IB_EVENT_QP_REQ_ERR;
 232                         break;
 233                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 234                         event.event = IB_EVENT_QP_ACCESS_ERR;
 235                         break;
 236                 default:
 237                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 238                         return;
 239                 }
 240
 241                 ibqp->event_handler(&event, ibqp->qp_context);
 242         }
 243 }
 244
 245 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 246                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 247 {
 248         int wqe_size;
 249         int wq_size;
 250
 251         /* Sanity check RQ size before proceeding */
 252         if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
 253                 return -EINVAL;
 254
 255         if (!has_rq) {
 256                 qp->rq.max_gs = 0;
 257                 qp->rq.wqe_cnt = 0;
 258                 qp->rq.wqe_shift = 0;
 259                 cap->max_recv_wr = 0;
 260                 cap->max_recv_sge = 0;
 261         } else {
 262                 if (ucmd) {
 263                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 264                         if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
 265                                 return -EINVAL;
 266                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 267                         if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
 268                                 return -EINVAL;
 269                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 270                         qp->rq.max_post = qp->rq.wqe_cnt;
 271                 } else {
 272                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 273                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 274                         wqe_size = roundup_pow_of_two(wqe_size);
 275                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 276                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 277                         qp->rq.wqe_cnt = wq_size / wqe_size;
 278                         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
 279                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 280                                             wqe_size,
 281                                             MLX5_CAP_GEN(dev->mdev,
 282                                                          max_wqe_sz_rq));
 283                                 return -EINVAL;
 284                         }
 285                         qp->rq.wqe_shift = ilog2(wqe_size);
 286                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 287                         qp->rq.max_post = qp->rq.wqe_cnt;
 288                 }
 289         }
 290
 291         return 0;
 292 }
 293
 294 static int sq_overhead(struct ib_qp_init_attr *attr)
 295 {
 296         int size = 0;
 297
 298         switch (attr->qp_type) {
 299         case IB_QPT_XRC_INI:
 300                 size += sizeof(struct mlx5_wqe_xrc_seg);
 301                 /* fall through */
 302         case IB_QPT_RC:
 303                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 304                         max(sizeof(struct mlx5_wqe_atomic_seg) +
 305                             sizeof(struct mlx5_wqe_raddr_seg),
 306                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 307                             sizeof(struct mlx5_mkey_seg) +
 308                             MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
 309                             MLX5_IB_UMR_OCTOWORD);
 310                 break;
 311
 312         case IB_QPT_XRC_TGT:
 313                 return 0;
 314
 315         case IB_QPT_UC:
 316                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 317                         max(sizeof(struct mlx5_wqe_raddr_seg),
 318                             sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 319                             sizeof(struct mlx5_mkey_seg));
 320                 break;
 321
 322         case IB_QPT_UD:
 323                 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 324                         size += sizeof(struct mlx5_wqe_eth_pad) +
 325                                 sizeof(struct mlx5_wqe_eth_seg);
 326                 /* fall through */
 327         case IB_QPT_SMI:
 328         case MLX5_IB_QPT_HW_GSI:
 329                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 330                         sizeof(struct mlx5_wqe_datagram_seg);
 331                 break;
 332
 333         case MLX5_IB_QPT_REG_UMR:
 334                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 335                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 336                         sizeof(struct mlx5_mkey_seg);
 337                 break;
 338
 339         default:
 340                 return -EINVAL;
 341         }
 342
 343         return size;
 344 }
 345
 346 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 347 {
 348         int inl_size = 0;
 349         int size;
 350
 351         size = sq_overhead(attr);
 352         if (size < 0)
 353                 return size;
 354
 355         if (attr->cap.max_inline_data) {
 356                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 357                         attr->cap.max_inline_data;
 358         }
 359
 360         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 361         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
 362             ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
 363                         return MLX5_SIG_WQE_SIZE;
 364         else
 365                 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 366 }
 367
 368 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
 369 {
 370         int max_sge;
 371
 372         if (attr->qp_type == IB_QPT_RC)
 373                 max_sge = (min_t(int, wqe_size, 512) -
 374                            sizeof(struct mlx5_wqe_ctrl_seg) -
 375                            sizeof(struct mlx5_wqe_raddr_seg)) /
 376                         sizeof(struct mlx5_wqe_data_seg);
 377         else if (attr->qp_type == IB_QPT_XRC_INI)
 378                 max_sge = (min_t(int, wqe_size, 512) -
 379                            sizeof(struct mlx5_wqe_ctrl_seg) -
 380                            sizeof(struct mlx5_wqe_xrc_seg) -
 381                            sizeof(struct mlx5_wqe_raddr_seg)) /
 382                         sizeof(struct mlx5_wqe_data_seg);
 383         else
 384                 max_sge = (wqe_size - sq_overhead(attr)) /
 385                         sizeof(struct mlx5_wqe_data_seg);
 386
 387         return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
 388                      sizeof(struct mlx5_wqe_data_seg));
 389 }
 390
 391 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 392                         struct mlx5_ib_qp *qp)
 393 {
 394         int wqe_size;
 395         int wq_size;
 396
 397         if (!attr->cap.max_send_wr)
 398                 return 0;
 399
 400         wqe_size = calc_send_wqe(attr);
 401         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 402         if (wqe_size < 0)
 403                 return wqe_size;
 404
 405         if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 406                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 407                             wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 408                 return -EINVAL;
 409         }
 410
 411         qp->max_inline_data = wqe_size - sq_overhead(attr) -
 412                               sizeof(struct mlx5_wqe_inline_seg);
 413         attr->cap.max_inline_data = qp->max_inline_data;
 414
 415         if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
 416                 qp->signature_en = true;
 417
 418         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 419         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 420         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 421                 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
 422                             attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
 423                             qp->sq.wqe_cnt,
 424                             1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 425                 return -ENOMEM;
 426         }
 427         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 428         qp->sq.max_gs = get_send_sge(attr, wqe_size);
 429         if (qp->sq.max_gs < attr->cap.max_send_sge)
 430                 return -ENOMEM;
 431
 432         attr->cap.max_send_sge = qp->sq.max_gs;
 433         qp->sq.max_post = wq_size / wqe_size;
 434         attr->cap.max_send_wr = qp->sq.max_post;
 435
 436         return wq_size;
 437 }
 438
 439 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 440                             struct mlx5_ib_qp *qp,
 441                             struct mlx5_ib_create_qp *ucmd,
 442                             struct mlx5_ib_qp_base *base,
 443                             struct ib_qp_init_attr *attr)
 444 {
 445         int desc_sz = 1 << qp->sq.wqe_shift;
 446
 447         if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
 448                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 449                              desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
 450                 return -EINVAL;
 451         }
 452
 453         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 454                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 455                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 456                 return -EINVAL;
 457         }
 458
 459         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 460
 461         if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
 462                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 463                              qp->sq.wqe_cnt,
 464                              1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
 465                 return -EINVAL;
 466         }
 467
 468         if (attr->qp_type == IB_QPT_RAW_PACKET ||
 469             qp->flags & MLX5_IB_QP_UNDERLAY) {
 470                 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 471                 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
 472         } else {
 473                 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 474                                          (qp->sq.wqe_cnt << 6);
 475         }
 476
 477         return 0;
 478 }
 479
 480 static int qp_has_rq(struct ib_qp_init_attr *attr)
 481 {
 482         if (attr->qp_type == IB_QPT_XRC_INI ||
 483             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 484             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 485             !attr->cap.max_recv_wr)
 486                 return 0;
 487
 488         return 1;
 489 }
 490
 491 enum {
 492         /* this is the first blue flame register in the array of bfregs assigned
 493          * to a processes. Since we do not use it for blue flame but rather
 494          * regular 64 bit doorbells, we do not need a lock for maintaiing
 495          * "odd/even" order
 496          */
 497         NUM_NON_BLUE_FLAME_BFREGS = 1,
 498 };
 499
 500 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
 501 {
 502         return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
 503 }
 504
 505 static int num_med_bfreg(struct mlx5_ib_dev *dev,
 506                          struct mlx5_bfreg_info *bfregi)
 507 {
 508         int n;
 509
 510         n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
 511             NUM_NON_BLUE_FLAME_BFREGS;
 512
 513         return n >= 0 ? n : 0;
 514 }
 515
 516 static int first_med_bfreg(struct mlx5_ib_dev *dev,
 517                            struct mlx5_bfreg_info *bfregi)
 518 {
 519         return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
 520 }
 521
 522 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
 523                           struct mlx5_bfreg_info *bfregi)
 524 {
 525         int med;
 526
 527         med = num_med_bfreg(dev, bfregi);
 528         return ++med;
 529 }
 530
 531 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
 532                                   struct mlx5_bfreg_info *bfregi)
 533 {
 534         int i;
 535
 536         for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
 537                 if (!bfregi->count[i]) {
 538                         bfregi->count[i]++;
 539                         return i;
 540                 }
 541         }
 542
 543         return -ENOMEM;
 544 }
 545
 546 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
 547                                  struct mlx5_bfreg_info *bfregi)
 548 {
 549         int minidx = first_med_bfreg(dev, bfregi);
 550         int i;
 551
 552         if (minidx < 0)
 553                 return minidx;
 554
 555         for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
 556                 if (bfregi->count[i] < bfregi->count[minidx])
 557                         minidx = i;
 558                 if (!bfregi->count[minidx])
 559                         break;
 560         }
 561
 562         bfregi->count[minidx]++;
 563         return minidx;
 564 }
 565
 566 static int alloc_bfreg(struct mlx5_ib_dev *dev,
 567                        struct mlx5_bfreg_info *bfregi)
 568 {
 569         int bfregn = -ENOMEM;
 570
 571         mutex_lock(&bfregi->lock);
 572         if (bfregi->ver >= 2) {
 573                 bfregn = alloc_high_class_bfreg(dev, bfregi);
 574                 if (bfregn < 0)
 575                         bfregn = alloc_med_class_bfreg(dev, bfregi);
 576         }
 577
 578         if (bfregn < 0) {
 579                 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
 580                 bfregn = 0;
 581                 bfregi->count[bfregn]++;
 582         }
 583         mutex_unlock(&bfregi->lock);
 584
 585         return bfregn;
 586 }
 587
 588 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
 589 {
 590         mutex_lock(&bfregi->lock);
 591         bfregi->count[bfregn]--;
 592         mutex_unlock(&bfregi->lock);
 593 }
 594
 595 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 596 {
 597         switch (state) {
 598         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 599         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 600         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 601         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 602         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 603         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 604         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 605         default:                return -1;
 606         }
 607 }
 608
 609 static int to_mlx5_st(enum ib_qp_type type)
 610 {
 611         switch (type) {
 612         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 613         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 614         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 615         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 616         case IB_QPT_XRC_INI:
 617         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 618         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 619         case MLX5_IB_QPT_HW_GSI:        return MLX5_QP_ST_QP1;
 620         case MLX5_IB_QPT_DCI:           return MLX5_QP_ST_DCI;
 621         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 622         case IB_QPT_RAW_PACKET:
 623         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 624         case IB_QPT_MAX:
 625         default:                return -EINVAL;
 626         }
 627 }
 628
 629 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
 630                              struct mlx5_ib_cq *recv_cq);
 631 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
 632                                struct mlx5_ib_cq *recv_cq);
 633
 634 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
 635                         struct mlx5_bfreg_info *bfregi, u32 bfregn,
 636                         bool dyn_bfreg)
 637 {
 638         unsigned int bfregs_per_sys_page;
 639         u32 index_of_sys_page;
 640         u32 offset;
 641
 642         bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
 643                                 MLX5_NON_FP_BFREGS_PER_UAR;
 644         index_of_sys_page = bfregn / bfregs_per_sys_page;
 645
 646         if (dyn_bfreg) {
 647                 index_of_sys_page += bfregi->num_static_sys_pages;
 648
 649                 if (index_of_sys_page >= bfregi->num_sys_pages)
 650                         return -EINVAL;
 651
 652                 if (bfregn > bfregi->num_dyn_bfregs ||
 653                     bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
 654                         mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
 655                         return -EINVAL;
 656                 }
 657         }
 658
 659         offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
 660         return bfregi->sys_pages[index_of_sys_page] + offset;
 661 }
 662
 663 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
 664                             struct ib_pd *pd,
 665                             unsigned long addr, size_t size,
 666                             struct ib_umem **umem,
 667                             int *npages, int *page_shift, int *ncont,
 668                             u32 *offset)
 669 {
 670         int err;
 671
 672         *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
 673         if (IS_ERR(*umem)) {
 674                 mlx5_ib_dbg(dev, "umem_get failed\n");
 675                 return PTR_ERR(*umem);
 676         }
 677
 678         mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
 679
 680         err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
 681         if (err) {
 682                 mlx5_ib_warn(dev, "bad offset\n");
 683                 goto err_umem;
 684         }
 685
 686         mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
 687                     addr, size, *npages, *page_shift, *ncont, *offset);
 688
 689         return 0;
 690
 691 err_umem:
 692         ib_umem_release(*umem);
 693         *umem = NULL;
 694
 695         return err;
 696 }
 697
 698 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 699                             struct mlx5_ib_rwq *rwq)
 700 {
 701         struct mlx5_ib_ucontext *context;
 702
 703         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
 704                 atomic_dec(&dev->delay_drop.rqs_cnt);
 705
 706         context = to_mucontext(pd->uobject->context);
 707         mlx5_ib_db_unmap_user(context, &rwq->db);
 708         if (rwq->umem)
 709                 ib_umem_release(rwq->umem);
 710 }
 711
 712 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 713                           struct mlx5_ib_rwq *rwq,
 714                           struct mlx5_ib_create_wq *ucmd)
 715 {
 716         struct mlx5_ib_ucontext *context;
 717         int page_shift = 0;
 718         int npages;
 719         u32 offset = 0;
 720         int ncont = 0;
 721         int err;
 722
 723         if (!ucmd->buf_addr)
 724                 return -EINVAL;
 725
 726         context = to_mucontext(pd->uobject->context);
 727         rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
 728                                rwq->buf_size, 0, 0);
 729         if (IS_ERR(rwq->umem)) {
 730                 mlx5_ib_dbg(dev, "umem_get failed\n");
 731                 err = PTR_ERR(rwq->umem);
 732                 return err;
 733         }
 734
 735         mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
 736                            &ncont, NULL);
 737         err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
 738                                      &rwq->rq_page_offset);
 739         if (err) {
 740                 mlx5_ib_warn(dev, "bad offset\n");
 741                 goto err_umem;
 742         }
 743
 744         rwq->rq_num_pas = ncont;
 745         rwq->page_shift = page_shift;
 746         rwq->log_page_size =  page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 747         rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
 748
 749         mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
 750                     (unsigned long long)ucmd->buf_addr, rwq->buf_size,
 751                     npages, page_shift, ncont, offset);
 752
 753         err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
 754         if (err) {
 755                 mlx5_ib_dbg(dev, "map failed\n");
 756                 goto err_umem;
 757         }
 758
 759         rwq->create_type = MLX5_WQ_USER;
 760         return 0;
 761
 762 err_umem:
 763         ib_umem_release(rwq->umem);
 764         return err;
 765 }
 766
 767 static int adjust_bfregn(struct mlx5_ib_dev *dev,
 768                          struct mlx5_bfreg_info *bfregi, int bfregn)
 769 {
 770         return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
 771                                 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
 772 }
 773
 774 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 775                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 776                           struct ib_qp_init_attr *attr,
 777                           u32 **in,
 778                           struct mlx5_ib_create_qp_resp *resp, int *inlen,
 779                           struct mlx5_ib_qp_base *base)
 780 {
 781         struct mlx5_ib_ucontext *context;
 782         struct mlx5_ib_create_qp ucmd;
 783         struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
 784         int page_shift = 0;
 785         int uar_index = 0;
 786         int npages;
 787         u32 offset = 0;
 788         int bfregn;
 789         int ncont = 0;
 790         __be64 *pas;
 791         void *qpc;
 792         int err;
 793
 794         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 795         if (err) {
 796                 mlx5_ib_dbg(dev, "copy failed\n");
 797                 return err;
 798         }
 799
 800         context = to_mucontext(pd->uobject->context);
 801         if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
 802                 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
 803                                                 ucmd.bfreg_index, true);
 804                 if (uar_index < 0)
 805                         return uar_index;
 806
 807                 bfregn = MLX5_IB_INVALID_BFREG;
 808         } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
 809                 /*
 810                  * TBD: should come from the verbs when we have the API
 811                  */
 812                 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
 813                 bfregn = MLX5_CROSS_CHANNEL_BFREG;
 814         }
 815         else {
 816                 bfregn = alloc_bfreg(dev, &context->bfregi);
 817                 if (bfregn < 0)
 818                         return bfregn;
 819         }
 820
 821         mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
 822         if (bfregn != MLX5_IB_INVALID_BFREG)
 823                 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
 824                                                 false);
 825
 826         qp->rq.offset = 0;
 827         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 828         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 829
 830         err = set_user_buf_size(dev, qp, &ucmd, base, attr);
 831         if (err)
 832                 goto err_bfreg;
 833
 834         if (ucmd.buf_addr && ubuffer->buf_size) {
 835                 ubuffer->buf_addr = ucmd.buf_addr;
 836                 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
 837                                        ubuffer->buf_size,
 838                                        &ubuffer->umem, &npages, &page_shift,
 839                                        &ncont, &offset);
 840                 if (err)
 841                         goto err_bfreg;
 842         } else {
 843                 ubuffer->umem = NULL;
 844         }
 845
 846         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 847                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
 848         *in = kvzalloc(*inlen, GFP_KERNEL);
 849         if (!*in) {
 850                 err = -ENOMEM;
 851                 goto err_umem;
 852         }
 853
 854         MLX5_SET(create_qp_in, *in, uid, to_mpd(pd)->uid);
 855         pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
 856         if (ubuffer->umem)
 857                 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
 858
 859         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 860
 861         MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 862         MLX5_SET(qpc, qpc, page_offset, offset);
 863
 864         MLX5_SET(qpc, qpc, uar_page, uar_index);
 865         if (bfregn != MLX5_IB_INVALID_BFREG)
 866                 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
 867         else
 868                 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
 869         qp->bfregn = bfregn;
 870
 871         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 872         if (err) {
 873                 mlx5_ib_dbg(dev, "map failed\n");
 874                 goto err_free;
 875         }
 876
 877         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
 878         if (err) {
 879                 mlx5_ib_dbg(dev, "copy failed\n");
 880                 goto err_unmap;
 881         }
 882         qp->create_type = MLX5_QP_USER;
 883
 884         return 0;
 885
 886 err_unmap:
 887         mlx5_ib_db_unmap_user(context, &qp->db);
 888
 889 err_free:
 890         kvfree(*in);
 891
 892 err_umem:
 893         if (ubuffer->umem)
 894                 ib_umem_release(ubuffer->umem);
 895
 896 err_bfreg:
 897         if (bfregn != MLX5_IB_INVALID_BFREG)
 898                 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
 899         return err;
 900 }
 901
 902 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 903                             struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
 904 {
 905         struct mlx5_ib_ucontext *context;
 906
 907         context = to_mucontext(pd->uobject->context);
 908         mlx5_ib_db_unmap_user(context, &qp->db);
 909         if (base->ubuffer.umem)
 910                 ib_umem_release(base->ubuffer.umem);
 911
 912         /*
 913          * Free only the BFREGs which are handled by the kernel.
 914          * BFREGs of UARs allocated dynamically are handled by user.
 915          */
 916         if (qp->bfregn != MLX5_IB_INVALID_BFREG)
 917                 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
 918 }
 919
 920 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 921                             struct ib_qp_init_attr *init_attr,
 922                             struct mlx5_ib_qp *qp,
 923                             u32 **in, int *inlen,
 924                             struct mlx5_ib_qp_base *base)
 925 {
 926         int uar_index;
 927         void *qpc;
 928         int err;
 929
 930         if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
 931                                         IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
 932                                         IB_QP_CREATE_IPOIB_UD_LSO |
 933                                         IB_QP_CREATE_NETIF_QP |
 934                                         mlx5_ib_create_qp_sqpn_qp1()))
 935                 return -EINVAL;
 936
 937         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 938                 qp->bf.bfreg = &dev->fp_bfreg;
 939         else
 940                 qp->bf.bfreg = &dev->bfreg;
 941
 942         /* We need to divide by two since each register is comprised of
 943          * two buffers of identical size, namely odd and even
 944          */
 945         qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
 946         uar_index = qp->bf.bfreg->index;
 947
 948         err = calc_sq_size(dev, init_attr, qp);
 949         if (err < 0) {
 950                 mlx5_ib_dbg(dev, "err %d\n", err);
 951                 return err;
 952         }
 953
 954         qp->rq.offset = 0;
 955         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 956         base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 957
 958         err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
 959         if (err) {
 960                 mlx5_ib_dbg(dev, "err %d\n", err);
 961                 return err;
 962         }
 963
 964         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 965         *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
 966                  MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
 967         *in = kvzalloc(*inlen, GFP_KERNEL);
 968         if (!*in) {
 969                 err = -ENOMEM;
 970                 goto err_buf;
 971         }
 972
 973         qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
 974         MLX5_SET(qpc, qpc, uar_page, uar_index);
 975         MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 976
 977         /* Set "fast registration enabled" for all kernel QPs */
 978         MLX5_SET(qpc, qpc, fre, 1);
 979         MLX5_SET(qpc, qpc, rlky, 1);
 980
 981         if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
 982                 MLX5_SET(qpc, qpc, deth_sqpn, 1);
 983                 qp->flags |= MLX5_IB_QP_SQPN_QP1;
 984         }
 985
 986         mlx5_fill_page_array(&qp->buf,
 987                              (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
 988
 989         err = mlx5_db_alloc(dev->mdev, &qp->db);
 990         if (err) {
 991                 mlx5_ib_dbg(dev, "err %d\n", err);
 992                 goto err_free;
 993         }
 994
 995         qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
 996                                      sizeof(*qp->sq.wrid), GFP_KERNEL);
 997         qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
 998                                         sizeof(*qp->sq.wr_data), GFP_KERNEL);
 999         qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1000                                      sizeof(*qp->rq.wrid), GFP_KERNEL);
1001         qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1002                                        sizeof(*qp->sq.w_list), GFP_KERNEL);
1003         qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1004                                          sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1005
1006         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1007             !qp->sq.w_list || !qp->sq.wqe_head) {
1008                 err = -ENOMEM;
1009                 goto err_wrid;
1010         }
1011         qp->create_type = MLX5_QP_KERNEL;
1012
1013         return 0;
1014
1015 err_wrid:
1016         kvfree(qp->sq.wqe_head);
1017         kvfree(qp->sq.w_list);
1018         kvfree(qp->sq.wrid);
1019         kvfree(qp->sq.wr_data);
1020         kvfree(qp->rq.wrid);
1021         mlx5_db_free(dev->mdev, &qp->db);
1022
1023 err_free:
1024         kvfree(*in);
1025
1026 err_buf:
1027         mlx5_buf_free(dev->mdev, &qp->buf);
1028         return err;
1029 }
1030
1031 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1032 {
1033         kvfree(qp->sq.wqe_head);
1034         kvfree(qp->sq.w_list);
1035         kvfree(qp->sq.wrid);
1036         kvfree(qp->sq.wr_data);
1037         kvfree(qp->rq.wrid);
1038         mlx5_db_free(dev->mdev, &qp->db);
1039         mlx5_buf_free(dev->mdev, &qp->buf);
1040 }
1041
1042 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1043 {
1044         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1045             (attr->qp_type == MLX5_IB_QPT_DCI) ||
1046             (attr->qp_type == IB_QPT_XRC_INI))
1047                 return MLX5_SRQ_RQ;
1048         else if (!qp->has_rq)
1049                 return MLX5_ZERO_LEN_RQ;
1050         else
1051                 return MLX5_NON_ZERO_RQ;
1052 }
1053
1054 static int is_connected(enum ib_qp_type qp_type)
1055 {
1056         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1057             qp_type == MLX5_IB_QPT_DCI)
1058                 return 1;
1059
1060         return 0;
1061 }
1062
1063 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1064                                     struct mlx5_ib_qp *qp,
1065                                     struct mlx5_ib_sq *sq, u32 tdn,
1066                                     struct ib_pd *pd)
1067 {
1068         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1069         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1070
1071         MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1072         MLX5_SET(tisc, tisc, transport_domain, tdn);
1073         if (qp->flags & MLX5_IB_QP_UNDERLAY)
1074                 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1075
1076         return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1077 }
1078
1079 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1080                                       struct mlx5_ib_sq *sq, struct ib_pd *pd)
1081 {
1082         mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1083 }
1084
1085 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1086                                        struct mlx5_ib_sq *sq)
1087 {
1088         if (sq->flow_rule)
1089                 mlx5_del_flow_rules(sq->flow_rule);
1090 }
1091
1092 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1093                                    struct mlx5_ib_sq *sq, void *qpin,
1094                                    struct ib_pd *pd)
1095 {
1096         struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1097         __be64 *pas;
1098         void *in;
1099         void *sqc;
1100         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1101         void *wq;
1102         int inlen;
1103         int err;
1104         int page_shift = 0;
1105         int npages;
1106         int ncont = 0;
1107         u32 offset = 0;
1108
1109         err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1110                                &sq->ubuffer.umem, &npages, &page_shift,
1111                                &ncont, &offset);
1112         if (err)
1113                 return err;
1114
1115         inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1116         in = kvzalloc(inlen, GFP_KERNEL);
1117         if (!in) {
1118                 err = -ENOMEM;
1119                 goto err_umem;
1120         }
1121
1122         MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1123         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1124         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1125         if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1126                 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1127         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1128         MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1129         MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1130         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1131         MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1132         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1133             MLX5_CAP_ETH(dev->mdev, swp))
1134                 MLX5_SET(sqc, sqc, allow_swp, 1);
1135
1136         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1137         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1138         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1139         MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1140         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1141         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1142         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1143         MLX5_SET(wq, wq, log_wq_pg_sz,  page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1144         MLX5_SET(wq, wq, page_offset, offset);
1145
1146         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1147         mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1148
1149         err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1150
1151         kvfree(in);
1152
1153         if (err)
1154                 goto err_umem;
1155
1156         err = create_flow_rule_vport_sq(dev, sq);
1157         if (err)
1158                 goto err_flow;
1159
1160         return 0;
1161
1162 err_flow:
1163         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1164
1165 err_umem:
1166         ib_umem_release(sq->ubuffer.umem);
1167         sq->ubuffer.umem = NULL;
1168
1169         return err;
1170 }
1171
1172 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1173                                      struct mlx5_ib_sq *sq)
1174 {
1175         destroy_flow_rule_vport_sq(dev, sq);
1176         mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1177         ib_umem_release(sq->ubuffer.umem);
1178 }
1179
1180 static size_t get_rq_pas_size(void *qpc)
1181 {
1182         u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1183         u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1184         u32 log_rq_size   = MLX5_GET(qpc, qpc, log_rq_size);
1185         u32 page_offset   = MLX5_GET(qpc, qpc, page_offset);
1186         u32 po_quanta     = 1 << (log_page_size - 6);
1187         u32 rq_sz         = 1 << (log_rq_size + 4 + log_rq_stride);
1188         u32 page_size     = 1 << log_page_size;
1189         u32 rq_sz_po      = rq_sz + (page_offset * po_quanta);
1190         u32 rq_num_pas    = (rq_sz_po + page_size - 1) / page_size;
1191
1192         return rq_num_pas * sizeof(u64);
1193 }
1194
1195 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1196                                    struct mlx5_ib_rq *rq, void *qpin,
1197                                    size_t qpinlen, struct ib_pd *pd)
1198 {
1199         struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1200         __be64 *pas;
1201         __be64 *qp_pas;
1202         void *in;
1203         void *rqc;
1204         void *wq;
1205         void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1206         size_t rq_pas_size = get_rq_pas_size(qpc);
1207         size_t inlen;
1208         int err;
1209
1210         if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1211                 return -EINVAL;
1212
1213         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1214         in = kvzalloc(inlen, GFP_KERNEL);
1215         if (!in)
1216                 return -ENOMEM;
1217
1218         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1219         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1220         if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1221                 MLX5_SET(rqc, rqc, vsd, 1);
1222         MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1223         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1224         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1225         MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1226         MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1227
1228         if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1229                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1230
1231         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1232         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1233         if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1234                 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1235         MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1236         MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1237         MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1238         MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1239         MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1240         MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1241
1242         pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1243         qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1244         memcpy(pas, qp_pas, rq_pas_size);
1245
1246         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1247
1248         kvfree(in);
1249
1250         return err;
1251 }
1252
1253 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1254                                      struct mlx5_ib_rq *rq)
1255 {
1256         mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1257 }
1258
1259 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1260 {
1261         return  (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1262                  MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1263                  MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1264 }
1265
1266 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1267                                       struct mlx5_ib_rq *rq,
1268                                       u32 qp_flags_en,
1269                                       struct ib_pd *pd)
1270 {
1271         if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1272                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1273                 mlx5_ib_disable_lb(dev, false, true);
1274         mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1275 }
1276
1277 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1278                                     struct mlx5_ib_rq *rq, u32 tdn,
1279                                     u32 *qp_flags_en,
1280                                     struct ib_pd *pd)
1281 {
1282         u8 lb_flag = 0;
1283         u32 *in;
1284         void *tirc;
1285         int inlen;
1286         int err;
1287
1288         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1289         in = kvzalloc(inlen, GFP_KERNEL);
1290         if (!in)
1291                 return -ENOMEM;
1292
1293         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1294         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1295         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1296         MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1297         MLX5_SET(tirc, tirc, transport_domain, tdn);
1298         if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1299                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1300
1301         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1302                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1303
1304         if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1305                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1306
1307         if (dev->rep) {
1308                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1309                 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1310         }
1311
1312         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1313
1314         err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1315
1316         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1317                 err = mlx5_ib_enable_lb(dev, false, true);
1318
1319                 if (err)
1320                         destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1321         }
1322         kvfree(in);
1323
1324         return err;
1325 }
1326
1327 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1328                                 u32 *in, size_t inlen,
1329                                 struct ib_pd *pd,
1330                                 struct ib_udata *udata,
1331                                 struct mlx5_ib_create_qp_resp *resp)
1332 {
1333         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1334         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1335         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1336         struct ib_uobject *uobj = pd->uobject;
1337         struct ib_ucontext *ucontext = uobj->context;
1338         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1339         int err;
1340         u32 tdn = mucontext->tdn;
1341         u16 uid = to_mpd(pd)->uid;
1342
1343         if (qp->sq.wqe_cnt) {
1344                 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1345                 if (err)
1346                         return err;
1347
1348                 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1349                 if (err)
1350                         goto err_destroy_tis;
1351
1352                 if (uid) {
1353                         resp->tisn = sq->tisn;
1354                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1355                         resp->sqn = sq->base.mqp.qpn;
1356                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1357                 }
1358
1359                 sq->base.container_mibqp = qp;
1360                 sq->base.mqp.event = mlx5_ib_qp_event;
1361         }
1362
1363         if (qp->rq.wqe_cnt) {
1364                 rq->base.container_mibqp = qp;
1365
1366                 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1367                         rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1368                 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1369                         rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1370                 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1371                 if (err)
1372                         goto err_destroy_sq;
1373
1374                 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd);
1375                 if (err)
1376                         goto err_destroy_rq;
1377
1378                 if (uid) {
1379                         resp->rqn = rq->base.mqp.qpn;
1380                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1381                         resp->tirn = rq->tirn;
1382                         resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1383                 }
1384         }
1385
1386         qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1387                                                      rq->base.mqp.qpn;
1388         err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1389         if (err)
1390                 goto err_destroy_tir;
1391
1392         return 0;
1393
1394 err_destroy_tir:
1395         destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1396 err_destroy_rq:
1397         destroy_raw_packet_qp_rq(dev, rq);
1398 err_destroy_sq:
1399         if (!qp->sq.wqe_cnt)
1400                 return err;
1401         destroy_raw_packet_qp_sq(dev, sq);
1402 err_destroy_tis:
1403         destroy_raw_packet_qp_tis(dev, sq, pd);
1404
1405         return err;
1406 }
1407
1408 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1409                                   struct mlx5_ib_qp *qp)
1410 {
1411         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1412         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1413         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1414
1415         if (qp->rq.wqe_cnt) {
1416                 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1417                 destroy_raw_packet_qp_rq(dev, rq);
1418         }
1419
1420         if (qp->sq.wqe_cnt) {
1421                 destroy_raw_packet_qp_sq(dev, sq);
1422                 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1423         }
1424 }
1425
1426 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1427                                     struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1428 {
1429         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1430         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1431
1432         sq->sq = &qp->sq;
1433         rq->rq = &qp->rq;
1434         sq->doorbell = &qp->db;
1435         rq->doorbell = &qp->db;
1436 }
1437
1438 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1439 {
1440         if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1441                             MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1442                 mlx5_ib_disable_lb(dev, false, true);
1443         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1444                              to_mpd(qp->ibqp.pd)->uid);
1445 }
1446
1447 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1448                                  struct ib_pd *pd,
1449                                  struct ib_qp_init_attr *init_attr,
1450                                  struct ib_udata *udata)
1451 {
1452         struct ib_uobject *uobj = pd->uobject;
1453         struct ib_ucontext *ucontext = uobj->context;
1454         struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1455         struct mlx5_ib_create_qp_resp resp = {};
1456         int inlen;
1457         int err;
1458         u32 *in;
1459         void *tirc;
1460         void *hfso;
1461         u32 selected_fields = 0;
1462         u32 outer_l4;
1463         size_t min_resp_len;
1464         u32 tdn = mucontext->tdn;
1465         struct mlx5_ib_create_qp_rss ucmd = {};
1466         size_t required_cmd_sz;
1467         u8 lb_flag = 0;
1468
1469         if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1470                 return -EOPNOTSUPP;
1471
1472         if (init_attr->create_flags || init_attr->send_cq)
1473                 return -EINVAL;
1474
1475         min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1476         if (udata->outlen < min_resp_len)
1477                 return -EINVAL;
1478
1479         required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1480         if (udata->inlen < required_cmd_sz) {
1481                 mlx5_ib_dbg(dev, "invalid inlen\n");
1482                 return -EINVAL;
1483         }
1484
1485         if (udata->inlen > sizeof(ucmd) &&
1486             !ib_is_udata_cleared(udata, sizeof(ucmd),
1487                                  udata->inlen - sizeof(ucmd))) {
1488                 mlx5_ib_dbg(dev, "inlen is not supported\n");
1489                 return -EOPNOTSUPP;
1490         }
1491
1492         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1493                 mlx5_ib_dbg(dev, "copy failed\n");
1494                 return -EFAULT;
1495         }
1496
1497         if (ucmd.comp_mask) {
1498                 mlx5_ib_dbg(dev, "invalid comp mask\n");
1499                 return -EOPNOTSUPP;
1500         }
1501
1502         if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1503                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1504                            MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1505                 mlx5_ib_dbg(dev, "invalid flags\n");
1506                 return -EOPNOTSUPP;
1507         }
1508
1509         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1510             !tunnel_offload_supported(dev->mdev)) {
1511                 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1512                 return -EOPNOTSUPP;
1513         }
1514
1515         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1516             !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1517                 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1518                 return -EOPNOTSUPP;
1519         }
1520
1521         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) {
1522                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1523                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1524         }
1525
1526         if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1527                 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1528                 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1529         }
1530
1531         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1532         if (err) {
1533                 mlx5_ib_dbg(dev, "copy failed\n");
1534                 return -EINVAL;
1535         }
1536
1537         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1538         in = kvzalloc(inlen, GFP_KERNEL);
1539         if (!in)
1540                 return -ENOMEM;
1541
1542         MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1543         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1544         MLX5_SET(tirc, tirc, disp_type,
1545                  MLX5_TIRC_DISP_TYPE_INDIRECT);
1546         MLX5_SET(tirc, tirc, indirect_table,
1547                  init_attr->rwq_ind_tbl->ind_tbl_num);
1548         MLX5_SET(tirc, tirc, transport_domain, tdn);
1549
1550         hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1551
1552         if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1553                 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1554
1555         MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1556
1557         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1558                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1559         else
1560                 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1561
1562         switch (ucmd.rx_hash_function) {
1563         case MLX5_RX_HASH_FUNC_TOEPLITZ:
1564         {
1565                 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1566                 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1567
1568                 if (len != ucmd.rx_key_len) {
1569                         err = -EINVAL;
1570                         goto err;
1571                 }
1572
1573                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1574                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1575                 memcpy(rss_key, ucmd.rx_hash_key, len);
1576                 break;
1577         }
1578         default:
1579                 err = -EOPNOTSUPP;
1580                 goto err;
1581         }
1582
1583         if (!ucmd.rx_hash_fields_mask) {
1584                 /* special case when this TIR serves as steering entry without hashing */
1585                 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1586                         goto create_tir;
1587                 err = -EINVAL;
1588                 goto err;
1589         }
1590
1591         if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1592              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1593              ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1594              (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1595                 err = -EINVAL;
1596                 goto err;
1597         }
1598
1599         /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1600         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1601             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1602                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1603                          MLX5_L3_PROT_TYPE_IPV4);
1604         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1605                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1606                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1607                          MLX5_L3_PROT_TYPE_IPV6);
1608
1609         outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1610                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1611                    ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1612                     (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1613                    (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1614
1615         /* Check that only one l4 protocol is set */
1616         if (outer_l4 & (outer_l4 - 1)) {
1617                 err = -EINVAL;
1618                 goto err;
1619         }
1620
1621         /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1622         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1623             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1624                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1625                          MLX5_L4_PROT_TYPE_TCP);
1626         else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1627                  (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1628                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1629                          MLX5_L4_PROT_TYPE_UDP);
1630
1631         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1632             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1633                 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1634
1635         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1636             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1637                 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1638
1639         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1640             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1641                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1642
1643         if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1644             (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1645                 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1646
1647         if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1648                 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1649
1650         MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1651
1652 create_tir:
1653         err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1654
1655         if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1656                 err = mlx5_ib_enable_lb(dev, false, true);
1657
1658                 if (err)
1659                         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1660                                              to_mpd(pd)->uid);
1661         }
1662
1663         if (err)
1664                 goto err;
1665
1666         if (mucontext->devx_uid) {
1667                 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1668                 resp.tirn = qp->rss_qp.tirn;
1669         }
1670
1671         err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1672         if (err)
1673                 goto err_copy;
1674
1675         kvfree(in);
1676         /* qpn is reserved for that QP */
1677         qp->trans_qp.base.mqp.qpn = 0;
1678         qp->flags |= MLX5_IB_QP_RSS;
1679         return 0;
1680
1681 err_copy:
1682         mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1683 err:
1684         kvfree(in);
1685         return err;
1686 }
1687
1688 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1689                                          void *qpc)
1690 {
1691         int rcqe_sz;
1692
1693         if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1694                 return;
1695
1696         rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1697
1698         if (rcqe_sz == 128) {
1699                 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1700                 return;
1701         }
1702
1703         if (init_attr->qp_type != MLX5_IB_QPT_DCT)
1704                 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1705 }
1706
1707 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1708                                          struct ib_qp_init_attr *init_attr,
1709                                          struct mlx5_ib_create_qp *ucmd,
1710                                          void *qpc)
1711 {
1712         enum ib_qp_type qpt = init_attr->qp_type;
1713         int scqe_sz;
1714         bool allow_scat_cqe = 0;
1715
1716         if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1717                 return;
1718
1719         if (ucmd)
1720                 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1721
1722         if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1723                 return;
1724
1725         scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1726         if (scqe_sz == 128) {
1727                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1728                 return;
1729         }
1730
1731         if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1732             MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1733                 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1734 }
1735
1736 static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1737 {
1738         return (input & ~supported) == 0;
1739 }
1740
1741 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1742                             struct ib_qp_init_attr *init_attr,
1743                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
1744 {
1745         struct mlx5_ib_resources *devr = &dev->devr;
1746         int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1747         struct mlx5_core_dev *mdev = dev->mdev;
1748         struct mlx5_ib_create_qp_resp resp = {};
1749         struct mlx5_ib_cq *send_cq;
1750         struct mlx5_ib_cq *recv_cq;
1751         unsigned long flags;
1752         u32 uidx = MLX5_IB_DEFAULT_UIDX;
1753         struct mlx5_ib_create_qp ucmd;
1754         struct mlx5_ib_qp_base *base;
1755         int mlx5_st;
1756         void *qpc;
1757         u32 *in;
1758         int err;
1759
1760         mutex_init(&qp->mutex);
1761         spin_lock_init(&qp->sq.lock);
1762         spin_lock_init(&qp->rq.lock);
1763
1764         mlx5_st = to_mlx5_st(init_attr->qp_type);
1765         if (mlx5_st < 0)
1766                 return -EINVAL;
1767
1768         if (init_attr->rwq_ind_tbl) {
1769                 if (!udata)
1770                         return -ENOSYS;
1771
1772                 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1773                 return err;
1774         }
1775
1776         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1777                 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1778                         mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1779                         return -EINVAL;
1780                 } else {
1781                         qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1782                 }
1783         }
1784
1785         if (init_attr->create_flags &
1786                         (IB_QP_CREATE_CROSS_CHANNEL |
1787                          IB_QP_CREATE_MANAGED_SEND |
1788                          IB_QP_CREATE_MANAGED_RECV)) {
1789                 if (!MLX5_CAP_GEN(mdev, cd)) {
1790                         mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1791                         return -EINVAL;
1792                 }
1793                 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1794                         qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1795                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1796                         qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1797                 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1798                         qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1799         }
1800
1801         if (init_attr->qp_type == IB_QPT_UD &&
1802             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1803                 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1804                         mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1805                         return -EOPNOTSUPP;
1806                 }
1807
1808         if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1809                 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1810                         mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1811                         return -EOPNOTSUPP;
1812                 }
1813                 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1814                     !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1815                         mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1816                         return -EOPNOTSUPP;
1817                 }
1818                 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1819         }
1820
1821         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1822                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1823
1824         if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1825                 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1826                       MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1827                     (init_attr->qp_type != IB_QPT_RAW_PACKET))
1828                         return -EOPNOTSUPP;
1829                 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1830         }
1831
1832         if (pd && pd->uobject) {
1833                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1834                         mlx5_ib_dbg(dev, "copy failed\n");
1835                         return -EFAULT;
1836                 }
1837
1838                 if (!check_flags_mask(ucmd.flags,
1839                                       MLX5_QP_FLAG_SIGNATURE |
1840                                               MLX5_QP_FLAG_SCATTER_CQE |
1841                                               MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1842                                               MLX5_QP_FLAG_BFREG_INDEX |
1843                                               MLX5_QP_FLAG_TYPE_DCT |
1844                                               MLX5_QP_FLAG_TYPE_DCI |
1845                                               MLX5_QP_FLAG_ALLOW_SCATTER_CQE))
1846                         return -EINVAL;
1847
1848                 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1849                                         &ucmd, udata->inlen, &uidx);
1850                 if (err)
1851                         return err;
1852
1853                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1854                 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
1855                         qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1856                 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1857                         if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1858                             !tunnel_offload_supported(mdev)) {
1859                                 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1860                                 return -EOPNOTSUPP;
1861                         }
1862                         qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
1863                 }
1864
1865                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
1866                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1867                                 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
1868                                 return -EOPNOTSUPP;
1869                         }
1870                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1871                 }
1872
1873                 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1874                         if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1875                                 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
1876                                 return -EOPNOTSUPP;
1877                         }
1878                         qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1879                 }
1880
1881                 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1882                         if (init_attr->qp_type != IB_QPT_UD ||
1883                             (MLX5_CAP_GEN(dev->mdev, port_type) !=
1884                              MLX5_CAP_PORT_TYPE_IB) ||
1885                             !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1886                                 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1887                                 return -EOPNOTSUPP;
1888                         }
1889
1890                         qp->flags |= MLX5_IB_QP_UNDERLAY;
1891                         qp->underlay_qpn = init_attr->source_qpn;
1892                 }
1893         } else {
1894                 qp->wq_sig = !!wq_signature;
1895         }
1896
1897         base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1898                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1899                &qp->raw_packet_qp.rq.base :
1900                &qp->trans_qp.base;
1901
1902         qp->has_rq = qp_has_rq(init_attr);
1903         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1904                           qp, (pd && pd->uobject) ? &ucmd : NULL);
1905         if (err) {
1906                 mlx5_ib_dbg(dev, "err %d\n", err);
1907                 return err;
1908         }
1909
1910         if (pd) {
1911                 if (pd->uobject) {
1912                         __u32 max_wqes =
1913                                 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1914                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1915                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1916                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1917                                 mlx5_ib_dbg(dev, "invalid rq params\n");
1918                                 return -EINVAL;
1919                         }
1920                         if (ucmd.sq_wqe_count > max_wqes) {
1921                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1922                                             ucmd.sq_wqe_count, max_wqes);
1923                                 return -EINVAL;
1924                         }
1925                         if (init_attr->create_flags &
1926                             mlx5_ib_create_qp_sqpn_qp1()) {
1927                                 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1928                                 return -EINVAL;
1929                         }
1930                         err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1931                                              &resp, &inlen, base);
1932                         if (err)
1933                                 mlx5_ib_dbg(dev, "err %d\n", err);
1934                 } else {
1935                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1936                                                base);
1937                         if (err)
1938                                 mlx5_ib_dbg(dev, "err %d\n", err);
1939                 }
1940
1941                 if (err)
1942                         return err;
1943         } else {
1944                 in = kvzalloc(inlen, GFP_KERNEL);
1945                 if (!in)
1946                         return -ENOMEM;
1947
1948                 qp->create_type = MLX5_QP_EMPTY;
1949         }
1950
1951         if (is_sqp(init_attr->qp_type))
1952                 qp->port = init_attr->port_num;
1953
1954         qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1955
1956         MLX5_SET(qpc, qpc, st, mlx5_st);
1957         MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1958
1959         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1960                 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1961         else
1962                 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1963
1964
1965         if (qp->wq_sig)
1966                 MLX5_SET(qpc, qpc, wq_signature, 1);
1967
1968         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1969                 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1970
1971         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1972                 MLX5_SET(qpc, qpc, cd_master, 1);
1973         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1974                 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1975         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1976                 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1977
1978         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1979                 configure_responder_scat_cqe(init_attr, qpc);
1980                 configure_requester_scat_cqe(dev, init_attr,
1981                                              (pd && pd->uobject) ? &ucmd : NULL,
1982                                              qpc);
1983         }
1984
1985         if (qp->rq.wqe_cnt) {
1986                 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1987                 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1988         }
1989
1990         MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1991
1992         if (qp->sq.wqe_cnt) {
1993                 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1994         } else {
1995                 MLX5_SET(qpc, qpc, no_sq, 1);
1996                 if (init_attr->srq &&
1997                     init_attr->srq->srq_type == IB_SRQT_TM)
1998                         MLX5_SET(qpc, qpc, offload_type,
1999                                  MLX5_QPC_OFFLOAD_TYPE_RNDV);
2000         }
2001
2002         /* Set default resources */
2003         switch (init_attr->qp_type) {
2004         case IB_QPT_XRC_TGT:
2005                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2006                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2007                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2008                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
2009                 break;
2010         case IB_QPT_XRC_INI:
2011                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2012                 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2013                 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2014                 break;
2015         default:
2016                 if (init_attr->srq) {
2017                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2018                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2019                 } else {
2020                         MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2021                         MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2022                 }
2023         }
2024
2025         if (init_attr->send_cq)
2026                 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2027
2028         if (init_attr->recv_cq)
2029                 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2030
2031         MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2032
2033         /* 0xffffff means we ask to work with cqe version 0 */
2034         if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2035                 MLX5_SET(qpc, qpc, user_index, uidx);
2036
2037         /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2038         if (init_attr->qp_type == IB_QPT_UD &&
2039             (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
2040                 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2041                 qp->flags |= MLX5_IB_QP_LSO;
2042         }
2043
2044         if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2045                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2046                         mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2047                         err = -EOPNOTSUPP;
2048                         goto err;
2049                 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2050                         MLX5_SET(qpc, qpc, end_padding_mode,
2051                                  MLX5_WQ_END_PAD_MODE_ALIGN);
2052                 } else {
2053                         qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2054                 }
2055         }
2056
2057         if (inlen < 0) {
2058                 err = -EINVAL;
2059                 goto err;
2060         }
2061
2062         if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2063             qp->flags & MLX5_IB_QP_UNDERLAY) {
2064                 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2065                 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2066                 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2067                                            &resp);
2068         } else {
2069                 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2070         }
2071
2072         if (err) {
2073                 mlx5_ib_dbg(dev, "create qp failed\n");
2074                 goto err_create;
2075         }
2076
2077         kvfree(in);
2078
2079         base->container_mibqp = qp;
2080         base->mqp.event = mlx5_ib_qp_event;
2081
2082         get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2083                 &send_cq, &recv_cq);
2084         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2085         mlx5_ib_lock_cqs(send_cq, recv_cq);
2086         /* Maintain device to QPs access, needed for further handling via reset
2087          * flow
2088          */
2089         list_add_tail(&qp->qps_list, &dev->qp_list);
2090         /* Maintain CQ to QPs access, needed for further handling via reset flow
2091          */
2092         if (send_cq)
2093                 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2094         if (recv_cq)
2095                 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2096         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2097         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2098
2099         return 0;
2100
2101 err_create:
2102         if (qp->create_type == MLX5_QP_USER)
2103                 destroy_qp_user(dev, pd, qp, base);
2104         else if (qp->create_type == MLX5_QP_KERNEL)
2105                 destroy_qp_kernel(dev, qp);
2106
2107 err:
2108         kvfree(in);
2109         return err;
2110 }
2111
2112 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2113         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2114 {
2115         if (send_cq) {
2116                 if (recv_cq) {
2117                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2118                                 spin_lock(&send_cq->lock);
2119                                 spin_lock_nested(&recv_cq->lock,
2120                                                  SINGLE_DEPTH_NESTING);
2121                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2122                                 spin_lock(&send_cq->lock);
2123                                 __acquire(&recv_cq->lock);
2124                         } else {
2125                                 spin_lock(&recv_cq->lock);
2126                                 spin_lock_nested(&send_cq->lock,
2127                                                  SINGLE_DEPTH_NESTING);
2128                         }
2129                 } else {
2130                         spin_lock(&send_cq->lock);
2131                         __acquire(&recv_cq->lock);
2132                 }
2133         } else if (recv_cq) {
2134                 spin_lock(&recv_cq->lock);
2135                 __acquire(&send_cq->lock);
2136         } else {
2137                 __acquire(&send_cq->lock);
2138                 __acquire(&recv_cq->lock);
2139         }
2140 }
2141
2142 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2143         __releases(&send_cq->lock) __releases(&recv_cq->lock)
2144 {
2145         if (send_cq) {
2146                 if (recv_cq) {
2147                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
2148                                 spin_unlock(&recv_cq->lock);
2149                                 spin_unlock(&send_cq->lock);
2150                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2151                                 __release(&recv_cq->lock);
2152                                 spin_unlock(&send_cq->lock);
2153                         } else {
2154                                 spin_unlock(&send_cq->lock);
2155                                 spin_unlock(&recv_cq->lock);
2156                         }
2157                 } else {
2158                         __release(&recv_cq->lock);
2159                         spin_unlock(&send_cq->lock);
2160                 }
2161         } else if (recv_cq) {
2162                 __release(&send_cq->lock);
2163                 spin_unlock(&recv_cq->lock);
2164         } else {
2165                 __release(&recv_cq->lock);
2166                 __release(&send_cq->lock);
2167         }
2168 }
2169
2170 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2171 {
2172         return to_mpd(qp->ibqp.pd);
2173 }
2174
2175 static void get_cqs(enum ib_qp_type qp_type,
2176                     struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2177                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2178 {
2179         switch (qp_type) {
2180         case IB_QPT_XRC_TGT:
2181                 *send_cq = NULL;
2182                 *recv_cq = NULL;
2183                 break;
2184         case MLX5_IB_QPT_REG_UMR:
2185         case IB_QPT_XRC_INI:
2186                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2187                 *recv_cq = NULL;
2188                 break;
2189
2190         case IB_QPT_SMI:
2191         case MLX5_IB_QPT_HW_GSI:
2192         case IB_QPT_RC:
2193         case IB_QPT_UC:
2194         case IB_QPT_UD:
2195         case IB_QPT_RAW_IPV6:
2196         case IB_QPT_RAW_ETHERTYPE:
2197         case IB_QPT_RAW_PACKET:
2198                 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2199                 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2200                 break;
2201
2202         case IB_QPT_MAX:
2203         default:
2204                 *send_cq = NULL;
2205                 *recv_cq = NULL;
2206                 break;
2207         }
2208 }
2209
2210 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2211                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2212                                 u8 lag_tx_affinity);
2213
2214 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2215 {
2216         struct mlx5_ib_cq *send_cq, *recv_cq;
2217         struct mlx5_ib_qp_base *base;
2218         unsigned long flags;
2219         int err;
2220
2221         if (qp->ibqp.rwq_ind_tbl) {
2222                 destroy_rss_raw_qp_tir(dev, qp);
2223                 return;
2224         }
2225
2226         base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2227                 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2228                &qp->raw_packet_qp.rq.base :
2229                &qp->trans_qp.base;
2230
2231         if (qp->state != IB_QPS_RESET) {
2232                 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2233                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2234                         err = mlx5_core_qp_modify(dev->mdev,
2235                                                   MLX5_CMD_OP_2RST_QP, 0,
2236                                                   NULL, &base->mqp);
2237                 } else {
2238                         struct mlx5_modify_raw_qp_param raw_qp_param = {
2239                                 .operation = MLX5_CMD_OP_2RST_QP
2240                         };
2241
2242                         err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2243                 }
2244                 if (err)
2245                         mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2246                                      base->mqp.qpn);
2247         }
2248
2249         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2250                 &send_cq, &recv_cq);
2251
2252         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2253         mlx5_ib_lock_cqs(send_cq, recv_cq);
2254         /* del from lists under both locks above to protect reset flow paths */
2255         list_del(&qp->qps_list);
2256         if (send_cq)
2257                 list_del(&qp->cq_send_list);
2258
2259         if (recv_cq)
2260                 list_del(&qp->cq_recv_list);
2261
2262         if (qp->create_type == MLX5_QP_KERNEL) {
2263                 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2264                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2265                 if (send_cq != recv_cq)
2266                         __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2267                                            NULL);
2268         }
2269         mlx5_ib_unlock_cqs(send_cq, recv_cq);
2270         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2271
2272         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2273             qp->flags & MLX5_IB_QP_UNDERLAY) {
2274                 destroy_raw_packet_qp(dev, qp);
2275         } else {
2276                 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2277                 if (err)
2278                         mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2279                                      base->mqp.qpn);
2280         }
2281
2282         if (qp->create_type == MLX5_QP_KERNEL)
2283                 destroy_qp_kernel(dev, qp);
2284         else if (qp->create_type == MLX5_QP_USER)
2285                 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2286 }
2287
2288 static const char *ib_qp_type_str(enum ib_qp_type type)
2289 {
2290         switch (type) {
2291         case IB_QPT_SMI:
2292                 return "IB_QPT_SMI";
2293         case IB_QPT_GSI:
2294                 return "IB_QPT_GSI";
2295         case IB_QPT_RC:
2296                 return "IB_QPT_RC";
2297         case IB_QPT_UC:
2298                 return "IB_QPT_UC";
2299         case IB_QPT_UD:
2300                 return "IB_QPT_UD";
2301         case IB_QPT_RAW_IPV6:
2302                 return "IB_QPT_RAW_IPV6";
2303         case IB_QPT_RAW_ETHERTYPE:
2304                 return "IB_QPT_RAW_ETHERTYPE";
2305         case IB_QPT_XRC_INI:
2306                 return "IB_QPT_XRC_INI";
2307         case IB_QPT_XRC_TGT:
2308                 return "IB_QPT_XRC_TGT";
2309         case IB_QPT_RAW_PACKET:
2310                 return "IB_QPT_RAW_PACKET";
2311         case MLX5_IB_QPT_REG_UMR:
2312                 return "MLX5_IB_QPT_REG_UMR";
2313         case IB_QPT_DRIVER:
2314                 return "IB_QPT_DRIVER";
2315         case IB_QPT_MAX:
2316         default:
2317                 return "Invalid QP type";
2318         }
2319 }
2320
2321 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2322                                         struct ib_qp_init_attr *attr,
2323                                         struct mlx5_ib_create_qp *ucmd)
2324 {
2325         struct mlx5_ib_qp *qp;
2326         int err = 0;
2327         u32 uidx = MLX5_IB_DEFAULT_UIDX;
2328         void *dctc;
2329
2330         if (!attr->srq || !attr->recv_cq)
2331                 return ERR_PTR(-EINVAL);
2332
2333         err = get_qp_user_index(to_mucontext(pd->uobject->context),
2334                                 ucmd, sizeof(*ucmd), &uidx);
2335         if (err)
2336                 return ERR_PTR(err);
2337
2338         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2339         if (!qp)
2340                 return ERR_PTR(-ENOMEM);
2341
2342         qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2343         if (!qp->dct.in) {
2344                 err = -ENOMEM;
2345                 goto err_free;
2346         }
2347
2348         MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2349         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2350         qp->qp_sub_type = MLX5_IB_QPT_DCT;
2351         MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2352         MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2353         MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2354         MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2355         MLX5_SET(dctc, dctc, user_index, uidx);
2356
2357         if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2358                 configure_responder_scat_cqe(attr, dctc);
2359
2360         qp->state = IB_QPS_RESET;
2361
2362         return &qp->ibqp;
2363 err_free:
2364         kfree(qp);
2365         return ERR_PTR(err);
2366 }
2367
2368 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2369                            struct ib_qp_init_attr *init_attr,
2370                            struct mlx5_ib_create_qp *ucmd,
2371                            struct ib_udata *udata)
2372 {
2373         enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2374         int err;
2375
2376         if (!udata)
2377                 return -EINVAL;
2378
2379         if (udata->inlen < sizeof(*ucmd)) {
2380                 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2381                 return -EINVAL;
2382         }
2383         err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2384         if (err)
2385                 return err;
2386
2387         if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2388                 init_attr->qp_type = MLX5_IB_QPT_DCI;
2389         } else {
2390                 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2391                         init_attr->qp_type = MLX5_IB_QPT_DCT;
2392                 } else {
2393                         mlx5_ib_dbg(dev, "Invalid QP flags\n");
2394                         return -EINVAL;
2395                 }
2396         }
2397
2398         if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2399                 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2400                 return -EOPNOTSUPP;
2401         }
2402
2403         return 0;
2404 }
2405
2406 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2407                                 struct ib_qp_init_attr *verbs_init_attr,
2408                                 struct ib_udata *udata)
2409 {
2410         struct mlx5_ib_dev *dev;
2411         struct mlx5_ib_qp *qp;
2412         u16 xrcdn = 0;
2413         int err;
2414         struct ib_qp_init_attr mlx_init_attr;
2415         struct ib_qp_init_attr *init_attr = verbs_init_attr;
2416
2417         if (pd) {
2418                 dev = to_mdev(pd->device);
2419
2420                 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2421                         if (!pd->uobject) {
2422                                 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2423                                 return ERR_PTR(-EINVAL);
2424                         } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2425                                 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2426                                 return ERR_PTR(-EINVAL);
2427                         }
2428                 }
2429         } else {
2430                 /* being cautious here */
2431                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2432                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2433                         pr_warn("%s: no PD for transport %s\n", __func__,
2434                                 ib_qp_type_str(init_attr->qp_type));
2435                         return ERR_PTR(-EINVAL);
2436                 }
2437                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2438         }
2439
2440         if (init_attr->qp_type == IB_QPT_DRIVER) {
2441                 struct mlx5_ib_create_qp ucmd;
2442
2443                 init_attr = &mlx_init_attr;
2444                 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2445                 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2446                 if (err)
2447                         return ERR_PTR(err);
2448
2449                 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2450                         if (init_attr->cap.max_recv_wr ||
2451                             init_attr->cap.max_recv_sge) {
2452                                 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2453                                 return ERR_PTR(-EINVAL);
2454                         }
2455                 } else {
2456                         return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2457                 }
2458         }
2459
2460         switch (init_attr->qp_type) {
2461         case IB_QPT_XRC_TGT:
2462         case IB_QPT_XRC_INI:
2463                 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2464                         mlx5_ib_dbg(dev, "XRC not supported\n");
2465                         return ERR_PTR(-ENOSYS);
2466                 }
2467                 init_attr->recv_cq = NULL;
2468                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2469                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2470                         init_attr->send_cq = NULL;
2471                 }
2472
2473                 /* fall through */
2474         case IB_QPT_RAW_PACKET:
2475         case IB_QPT_RC:
2476         case IB_QPT_UC:
2477         case IB_QPT_UD:
2478         case IB_QPT_SMI:
2479         case MLX5_IB_QPT_HW_GSI:
2480         case MLX5_IB_QPT_REG_UMR:
2481         case MLX5_IB_QPT_DCI:
2482                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2483                 if (!qp)
2484                         return ERR_PTR(-ENOMEM);
2485
2486                 err = create_qp_common(dev, pd, init_attr, udata, qp);
2487                 if (err) {
2488                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
2489                         kfree(qp);
2490                         return ERR_PTR(err);
2491                 }
2492
2493                 if (is_qp0(init_attr->qp_type))
2494                         qp->ibqp.qp_num = 0;
2495                 else if (is_qp1(init_attr->qp_type))
2496                         qp->ibqp.qp_num = 1;
2497                 else
2498                         qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2499
2500                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2501                             qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2502                             init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2503                             init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2504
2505                 qp->trans_qp.xrcdn = xrcdn;
2506
2507                 break;
2508
2509         case IB_QPT_GSI:
2510                 return mlx5_ib_gsi_create_qp(pd, init_attr);
2511
2512         case IB_QPT_RAW_IPV6:
2513         case IB_QPT_RAW_ETHERTYPE:
2514         case IB_QPT_MAX:
2515         default:
2516                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2517                             init_attr->qp_type);
2518                 /* Don't support raw QPs */
2519                 return ERR_PTR(-EINVAL);
2520         }
2521
2522         if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2523                 qp->qp_sub_type = init_attr->qp_type;
2524
2525         return &qp->ibqp;
2526 }
2527
2528 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2529 {
2530         struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2531
2532         if (mqp->state == IB_QPS_RTR) {
2533                 int err;
2534
2535                 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2536                 if (err) {
2537                         mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2538                         return err;
2539                 }
2540         }
2541
2542         kfree(mqp->dct.in);
2543         kfree(mqp);
2544         return 0;
2545 }
2546
2547 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2548 {
2549         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2550         struct mlx5_ib_qp *mqp = to_mqp(qp);
2551
2552         if (unlikely(qp->qp_type == IB_QPT_GSI))
2553                 return mlx5_ib_gsi_destroy_qp(qp);
2554
2555         if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2556                 return mlx5_ib_destroy_dct(mqp);
2557
2558         destroy_qp_common(dev, mqp);
2559
2560         kfree(mqp);
2561
2562         return 0;
2563 }
2564
2565 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2566                                    int attr_mask)
2567 {
2568         u32 hw_access_flags = 0;
2569         u8 dest_rd_atomic;
2570         u32 access_flags;
2571
2572         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2573                 dest_rd_atomic = attr->max_dest_rd_atomic;
2574         else
2575                 dest_rd_atomic = qp->trans_qp.resp_depth;
2576
2577         if (attr_mask & IB_QP_ACCESS_FLAGS)
2578                 access_flags = attr->qp_access_flags;
2579         else
2580                 access_flags = qp->trans_qp.atomic_rd_en;
2581
2582         if (!dest_rd_atomic)
2583                 access_flags &= IB_ACCESS_REMOTE_WRITE;
2584
2585         if (access_flags & IB_ACCESS_REMOTE_READ)
2586                 hw_access_flags |= MLX5_QP_BIT_RRE;
2587         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2588                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2589         if (access_flags & IB_ACCESS_REMOTE_WRITE)
2590                 hw_access_flags |= MLX5_QP_BIT_RWE;
2591
2592         return cpu_to_be32(hw_access_flags);
2593 }
2594
2595 enum {
2596         MLX5_PATH_FLAG_FL       = 1 << 0,
2597         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
2598         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
2599 };
2600
2601 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2602 {
2603         if (rate == IB_RATE_PORT_CURRENT)
2604                 return 0;
2605
2606         if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2607                 return -EINVAL;
2608
2609         while (rate != IB_RATE_PORT_CURRENT &&
2610                !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2611                  MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2612                 --rate;
2613
2614         return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2615 }
2616
2617 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2618                                       struct mlx5_ib_sq *sq, u8 sl,
2619                                       struct ib_pd *pd)
2620 {
2621         void *in;
2622         void *tisc;
2623         int inlen;
2624         int err;
2625
2626         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2627         in = kvzalloc(inlen, GFP_KERNEL);
2628         if (!in)
2629                 return -ENOMEM;
2630
2631         MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2632         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2633
2634         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2635         MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2636
2637         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2638
2639         kvfree(in);
2640
2641         return err;
2642 }
2643
2644 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2645                                          struct mlx5_ib_sq *sq, u8 tx_affinity,
2646                                          struct ib_pd *pd)
2647 {
2648         void *in;
2649         void *tisc;
2650         int inlen;
2651         int err;
2652
2653         inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2654         in = kvzalloc(inlen, GFP_KERNEL);
2655         if (!in)
2656                 return -ENOMEM;
2657
2658         MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2659         MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2660
2661         tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2662         MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2663
2664         err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2665
2666         kvfree(in);
2667
2668         return err;
2669 }
2670
2671 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2672                          const struct rdma_ah_attr *ah,
2673                          struct mlx5_qp_path *path, u8 port, int attr_mask,
2674                          u32 path_flags, const struct ib_qp_attr *attr,
2675                          bool alt)
2676 {
2677         const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2678         int err;
2679         enum ib_gid_type gid_type;
2680         u8 ah_flags = rdma_ah_get_ah_flags(ah);
2681         u8 sl = rdma_ah_get_sl(ah);
2682
2683         if (attr_mask & IB_QP_PKEY_INDEX)
2684                 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2685                                                      attr->pkey_index);
2686
2687         if (ah_flags & IB_AH_GRH) {
2688                 if (grh->sgid_index >=
2689                     dev->mdev->port_caps[port - 1].gid_table_len) {
2690                         pr_err("sgid_index (%u) too large. max is %d\n",
2691                                grh->sgid_index,
2692                                dev->mdev->port_caps[port - 1].gid_table_len);
2693                         return -EINVAL;
2694                 }
2695         }
2696
2697         if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2698                 if (!(ah_flags & IB_AH_GRH))
2699                         return -EINVAL;
2700
2701                 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2702                 if (qp->ibqp.qp_type == IB_QPT_RC ||
2703                     qp->ibqp.qp_type == IB_QPT_UC ||
2704                     qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2705                     qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2706                         path->udp_sport =
2707                                 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2708                 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2709                 gid_type = ah->grh.sgid_attr->gid_type;
2710                 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2711                         path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2712         } else {
2713                 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2714                 path->fl_free_ar |=
2715                         (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2716                 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2717                 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2718                 if (ah_flags & IB_AH_GRH)
2719                         path->grh_mlid  |= 1 << 7;
2720                 path->dci_cfi_prio_sl = sl & 0xf;
2721         }
2722
2723         if (ah_flags & IB_AH_GRH) {
2724                 path->mgid_index = grh->sgid_index;
2725                 path->hop_limit  = grh->hop_limit;
2726                 path->tclass_flowlabel =
2727                         cpu_to_be32((grh->traffic_class << 20) |
2728                                     (grh->flow_label));
2729                 memcpy(path->rgid, grh->dgid.raw, 16);
2730         }
2731
2732         err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2733         if (err < 0)
2734                 return err;
2735         path->static_rate = err;
2736         path->port = port;
2737
2738         if (attr_mask & IB_QP_TIMEOUT)
2739                 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2740
2741         if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2742                 return modify_raw_packet_eth_prio(dev->mdev,
2743                                                   &qp->raw_packet_qp.sq,
2744                                                   sl & 0xf, qp->ibqp.pd);
2745
2746         return 0;
2747 }
2748
2749 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2750         [MLX5_QP_STATE_INIT] = {
2751                 [MLX5_QP_STATE_INIT] = {
2752                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2753                                           MLX5_QP_OPTPAR_RAE            |
2754                                           MLX5_QP_OPTPAR_RWE            |
2755                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2756                                           MLX5_QP_OPTPAR_PRI_PORT,
2757                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2758                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
2759                                           MLX5_QP_OPTPAR_PRI_PORT,
2760                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2761                                           MLX5_QP_OPTPAR_Q_KEY          |
2762                                           MLX5_QP_OPTPAR_PRI_PORT,
2763                 },
2764                 [MLX5_QP_STATE_RTR] = {
2765                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2766                                           MLX5_QP_OPTPAR_RRE            |
2767                                           MLX5_QP_OPTPAR_RAE            |
2768                                           MLX5_QP_OPTPAR_RWE            |
2769                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2770                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2771                                           MLX5_QP_OPTPAR_RWE            |
2772                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2773                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
2774                                           MLX5_QP_OPTPAR_Q_KEY,
2775                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
2776                                            MLX5_QP_OPTPAR_Q_KEY,
2777                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2778                                           MLX5_QP_OPTPAR_RRE            |
2779                                           MLX5_QP_OPTPAR_RAE            |
2780                                           MLX5_QP_OPTPAR_RWE            |
2781                                           MLX5_QP_OPTPAR_PKEY_INDEX,
2782                 },
2783         },
2784         [MLX5_QP_STATE_RTR] = {
2785                 [MLX5_QP_STATE_RTS] = {
2786                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2787                                           MLX5_QP_OPTPAR_RRE            |
2788                                           MLX5_QP_OPTPAR_RAE            |
2789                                           MLX5_QP_OPTPAR_RWE            |
2790                                           MLX5_QP_OPTPAR_PM_STATE       |
2791                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
2792                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
2793                                           MLX5_QP_OPTPAR_RWE            |
2794                                           MLX5_QP_OPTPAR_PM_STATE,
2795                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2796                 },
2797         },
2798         [MLX5_QP_STATE_RTS] = {
2799                 [MLX5_QP_STATE_RTS] = {
2800                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
2801                                           MLX5_QP_OPTPAR_RAE            |
2802                                           MLX5_QP_OPTPAR_RWE            |
2803                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
2804                                           MLX5_QP_OPTPAR_PM_STATE       |
2805                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2806                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
2807                                           MLX5_QP_OPTPAR_PM_STATE       |
2808                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2809                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
2810                                           MLX5_QP_OPTPAR_SRQN           |
2811                                           MLX5_QP_OPTPAR_CQN_RCV,
2812                 },
2813         },
2814         [MLX5_QP_STATE_SQER] = {
2815                 [MLX5_QP_STATE_RTS] = {
2816                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
2817                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2818                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
2819                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
2820                                            MLX5_QP_OPTPAR_RWE           |
2821                                            MLX5_QP_OPTPAR_RAE           |
2822                                            MLX5_QP_OPTPAR_RRE,
2823                 },
2824         },
2825 };
2826
2827 static int ib_nr_to_mlx5_nr(int ib_mask)
2828 {
2829         switch (ib_mask) {
2830         case IB_QP_STATE:
2831                 return 0;
2832         case IB_QP_CUR_STATE:
2833                 return 0;
2834         case IB_QP_EN_SQD_ASYNC_NOTIFY:
2835                 return 0;
2836         case IB_QP_ACCESS_FLAGS:
2837                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2838                         MLX5_QP_OPTPAR_RAE;
2839         case IB_QP_PKEY_INDEX:
2840                 return MLX5_QP_OPTPAR_PKEY_INDEX;
2841         case IB_QP_PORT:
2842                 return MLX5_QP_OPTPAR_PRI_PORT;
2843         case IB_QP_QKEY:
2844                 return MLX5_QP_OPTPAR_Q_KEY;
2845         case IB_QP_AV:
2846                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2847                         MLX5_QP_OPTPAR_PRI_PORT;
2848         case IB_QP_PATH_MTU:
2849                 return 0;
2850         case IB_QP_TIMEOUT:
2851                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2852         case IB_QP_RETRY_CNT:
2853                 return MLX5_QP_OPTPAR_RETRY_COUNT;
2854         case IB_QP_RNR_RETRY:
2855                 return MLX5_QP_OPTPAR_RNR_RETRY;
2856         case IB_QP_RQ_PSN:
2857                 return 0;
2858         case IB_QP_MAX_QP_RD_ATOMIC:
2859                 return MLX5_QP_OPTPAR_SRA_MAX;
2860         case IB_QP_ALT_PATH:
2861                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2862         case IB_QP_MIN_RNR_TIMER:
2863                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2864         case IB_QP_SQ_PSN:
2865                 return 0;
2866         case IB_QP_MAX_DEST_RD_ATOMIC:
2867                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2868                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2869         case IB_QP_PATH_MIG_STATE:
2870                 return MLX5_QP_OPTPAR_PM_STATE;
2871         case IB_QP_CAP:
2872                 return 0;
2873         case IB_QP_DEST_QPN:
2874                 return 0;
2875         }
2876         return 0;
2877 }
2878
2879 static int ib_mask_to_mlx5_opt(int ib_mask)
2880 {
2881         int result = 0;
2882         int i;
2883
2884         for (i = 0; i < 8 * sizeof(int); i++) {
2885                 if ((1 << i) & ib_mask)
2886                         result |= ib_nr_to_mlx5_nr(1 << i);
2887         }
2888
2889         return result;
2890 }
2891
2892 static int modify_raw_packet_qp_rq(
2893         struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
2894         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
2895 {
2896         void *in;
2897         void *rqc;
2898         int inlen;
2899         int err;
2900
2901         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2902         in = kvzalloc(inlen, GFP_KERNEL);
2903         if (!in)
2904                 return -ENOMEM;
2905
2906         MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2907         MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
2908
2909         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2910         MLX5_SET(rqc, rqc, state, new_state);
2911
2912         if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2913                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2914                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
2915                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2916                         MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2917                 } else
2918                         dev_info_once(
2919                                 &dev->ib_dev.dev,
2920                                 "RAW PACKET QP counters are not supported on current FW\n");
2921         }
2922
2923         err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2924         if (err)
2925                 goto out;
2926
2927         rq->state = new_state;
2928
2929 out:
2930         kvfree(in);
2931         return err;
2932 }
2933
2934 static int modify_raw_packet_qp_sq(
2935         struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
2936         const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
2937 {
2938         struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2939         struct mlx5_rate_limit old_rl = ibqp->rl;
2940         struct mlx5_rate_limit new_rl = old_rl;
2941         bool new_rate_added = false;
2942         u16 rl_index = 0;
2943         void *in;
2944         void *sqc;
2945         int inlen;
2946         int err;
2947
2948         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2949         in = kvzalloc(inlen, GFP_KERNEL);
2950         if (!in)
2951                 return -ENOMEM;
2952
2953         MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
2954         MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2955
2956         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2957         MLX5_SET(sqc, sqc, state, new_state);
2958
2959         if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2960                 if (new_state != MLX5_SQC_STATE_RDY)
2961                         pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2962                                 __func__);
2963                 else
2964                         new_rl = raw_qp_param->rl;
2965         }
2966
2967         if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2968                 if (new_rl.rate) {
2969                         err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
2970                         if (err) {
2971                                 pr_err("Failed configuring rate limit(err %d): \
2972                                        rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2973                                        err, new_rl.rate, new_rl.max_burst_sz,
2974                                        new_rl.typical_pkt_sz);
2975
2976                                 goto out;
2977                         }
2978                         new_rate_added = true;
2979                 }
2980
2981                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2982                 /* index 0 means no limit */
2983                 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2984         }
2985
2986         err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2987         if (err) {
2988                 /* Remove new rate from table if failed */
2989                 if (new_rate_added)
2990                         mlx5_rl_remove_rate(dev, &new_rl);
2991                 goto out;
2992         }
2993
2994         /* Only remove the old rate after new rate was set */
2995         if ((old_rl.rate &&
2996              !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
2997             (new_state != MLX5_SQC_STATE_RDY))
2998                 mlx5_rl_remove_rate(dev, &old_rl);
2999
3000         ibqp->rl = new_rl;
3001         sq->state = new_state;
3002
3003 out:
3004         kvfree(in);
3005         return err;
3006 }
3007
3008 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3009                                 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3010                                 u8 tx_affinity)
3011 {
3012         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3013         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3014         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3015         int modify_rq = !!qp->rq.wqe_cnt;
3016         int modify_sq = !!qp->sq.wqe_cnt;
3017         int rq_state;
3018         int sq_state;
3019         int err;
3020
3021         switch (raw_qp_param->operation) {
3022         case MLX5_CMD_OP_RST2INIT_QP:
3023                 rq_state = MLX5_RQC_STATE_RDY;
3024                 sq_state = MLX5_SQC_STATE_RDY;
3025                 break;
3026         case MLX5_CMD_OP_2ERR_QP:
3027                 rq_state = MLX5_RQC_STATE_ERR;
3028                 sq_state = MLX5_SQC_STATE_ERR;
3029                 break;
3030         case MLX5_CMD_OP_2RST_QP:
3031                 rq_state = MLX5_RQC_STATE_RST;
3032                 sq_state = MLX5_SQC_STATE_RST;
3033                 break;
3034         case MLX5_CMD_OP_RTR2RTS_QP:
3035         case MLX5_CMD_OP_RTS2RTS_QP:
3036                 if (raw_qp_param->set_mask ==
3037                     MLX5_RAW_QP_RATE_LIMIT) {
3038                         modify_rq = 0;
3039                         sq_state = sq->state;
3040                 } else {
3041                         return raw_qp_param->set_mask ? -EINVAL : 0;
3042                 }
3043                 break;
3044         case MLX5_CMD_OP_INIT2INIT_QP:
3045         case MLX5_CMD_OP_INIT2RTR_QP:
3046                 if (raw_qp_param->set_mask)
3047                         return -EINVAL;
3048                 else
3049                         return 0;
3050         default:
3051                 WARN_ON(1);
3052                 return -EINVAL;
3053         }
3054
3055         if (modify_rq) {
3056                 err =  modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3057                                                qp->ibqp.pd);
3058                 if (err)
3059                         return err;
3060         }
3061
3062         if (modify_sq) {
3063                 if (tx_affinity) {
3064                         err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3065                                                             tx_affinity,
3066                                                             qp->ibqp.pd);
3067                         if (err)
3068                                 return err;
3069                 }
3070
3071                 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3072                                                raw_qp_param, qp->ibqp.pd);
3073         }
3074
3075         return 0;
3076 }
3077
3078 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3079                                     struct mlx5_ib_pd *pd,
3080                                     struct mlx5_ib_qp_base *qp_base,
3081                                     u8 port_num)
3082 {
3083         struct mlx5_ib_ucontext *ucontext = NULL;
3084         unsigned int tx_port_affinity;
3085
3086         if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
3087                 ucontext = to_mucontext(pd->ibpd.uobject->context);
3088
3089         if (ucontext) {
3090                 tx_port_affinity = (unsigned int)atomic_add_return(
3091                                            1, &ucontext->tx_port_affinity) %
3092                                            MLX5_MAX_PORTS +
3093                                    1;
3094                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3095                                 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3096         } else {
3097                 tx_port_affinity =
3098                         (unsigned int)atomic_add_return(
3099                                 1, &dev->roce[port_num].tx_port_affinity) %
3100                                 MLX5_MAX_PORTS +
3101                         1;
3102                 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3103                                 tx_port_affinity, qp_base->mqp.qpn);
3104         }
3105
3106         return tx_port_affinity;
3107 }
3108
3109 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3110                                const struct ib_qp_attr *attr, int attr_mask,
3111                                enum ib_qp_state cur_state, enum ib_qp_state new_state,
3112                                const struct mlx5_ib_modify_qp *ucmd)
3113 {
3114         static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3115                 [MLX5_QP_STATE_RST] = {
3116                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3117                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3118                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_RST2INIT_QP,
3119                 },
3120                 [MLX5_QP_STATE_INIT]  = {
3121                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3122                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3123                         [MLX5_QP_STATE_INIT]    = MLX5_CMD_OP_INIT2INIT_QP,
3124                         [MLX5_QP_STATE_RTR]     = MLX5_CMD_OP_INIT2RTR_QP,
3125                 },
3126                 [MLX5_QP_STATE_RTR]   = {
3127                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3128                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3129                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTR2RTS_QP,
3130                 },
3131                 [MLX5_QP_STATE_RTS]   = {
3132                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3133                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3134                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_RTS2RTS_QP,
3135                 },
3136                 [MLX5_QP_STATE_SQD] = {
3137                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3138                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3139                 },
3140                 [MLX5_QP_STATE_SQER] = {
3141                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3142                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3143                         [MLX5_QP_STATE_RTS]     = MLX5_CMD_OP_SQERR2RTS_QP,
3144                 },
3145                 [MLX5_QP_STATE_ERR] = {
3146                         [MLX5_QP_STATE_RST]     = MLX5_CMD_OP_2RST_QP,
3147                         [MLX5_QP_STATE_ERR]     = MLX5_CMD_OP_2ERR_QP,
3148                 }
3149         };
3150
3151         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3152         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3153         struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3154         struct mlx5_ib_cq *send_cq, *recv_cq;
3155         struct mlx5_qp_context *context;
3156         struct mlx5_ib_pd *pd;
3157         struct mlx5_ib_port *mibport = NULL;
3158         enum mlx5_qp_state mlx5_cur, mlx5_new;
3159         enum mlx5_qp_optpar optpar;
3160         int mlx5_st;
3161         int err;
3162         u16 op;
3163         u8 tx_affinity = 0;
3164
3165         mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3166                              qp->qp_sub_type : ibqp->qp_type);
3167         if (mlx5_st < 0)
3168                 return -EINVAL;
3169
3170         context = kzalloc(sizeof(*context), GFP_KERNEL);
3171         if (!context)
3172                 return -ENOMEM;
3173
3174         pd = get_pd(qp);
3175         context->flags = cpu_to_be32(mlx5_st << 16);
3176
3177         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3178                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3179         } else {
3180                 switch (attr->path_mig_state) {
3181                 case IB_MIG_MIGRATED:
3182                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3183                         break;
3184                 case IB_MIG_REARM:
3185                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3186                         break;
3187                 case IB_MIG_ARMED:
3188                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3189                         break;
3190                 }
3191         }
3192
3193         if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3194                 if ((ibqp->qp_type == IB_QPT_RC) ||
3195                     (ibqp->qp_type == IB_QPT_UD &&
3196                      !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3197                     (ibqp->qp_type == IB_QPT_UC) ||
3198                     (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3199                     (ibqp->qp_type == IB_QPT_XRC_INI) ||
3200                     (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3201                         if (mlx5_lag_is_active(dev->mdev)) {
3202                                 u8 p = mlx5_core_native_port_num(dev->mdev);
3203                                 tx_affinity = get_tx_affinity(dev, pd, base, p);
3204                                 context->flags |= cpu_to_be32(tx_affinity << 24);
3205                         }
3206                 }
3207         }
3208
3209         if (is_sqp(ibqp->qp_type)) {
3210                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3211         } else if ((ibqp->qp_type == IB_QPT_UD &&
3212                     !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3213                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3214                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3215         } else if (attr_mask & IB_QP_PATH_MTU) {
3216                 if (attr->path_mtu < IB_MTU_256 ||
3217                     attr->path_mtu > IB_MTU_4096) {
3218                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3219                         err = -EINVAL;
3220                         goto out;
3221                 }
3222                 context->mtu_msgmax = (attr->path_mtu << 5) |
3223                                       (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3224         }
3225
3226         if (attr_mask & IB_QP_DEST_QPN)
3227                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3228
3229         if (attr_mask & IB_QP_PKEY_INDEX)
3230                 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3231
3232         /* todo implement counter_index functionality */
3233
3234         if (is_sqp(ibqp->qp_type))
3235                 context->pri_path.port = qp->port;
3236
3237         if (attr_mask & IB_QP_PORT)
3238                 context->pri_path.port = attr->port_num;
3239
3240         if (attr_mask & IB_QP_AV) {
3241                 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3242                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3243                                     attr_mask, 0, attr, false);
3244                 if (err)
3245                         goto out;
3246         }
3247
3248         if (attr_mask & IB_QP_TIMEOUT)
3249                 context->pri_path.ackto_lt |= attr->timeout << 3;
3250
3251         if (attr_mask & IB_QP_ALT_PATH) {
3252                 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3253                                     &context->alt_path,
3254                                     attr->alt_port_num,
3255                                     attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3256                                     0, attr, true);
3257                 if (err)
3258                         goto out;
3259         }
3260
3261         get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3262                 &send_cq, &recv_cq);
3263
3264         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3265         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3266         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3267         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3268
3269         if (attr_mask & IB_QP_RNR_RETRY)
3270                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3271
3272         if (attr_mask & IB_QP_RETRY_CNT)
3273                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3274
3275         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3276                 if (attr->max_rd_atomic)
3277                         context->params1 |=
3278                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3279         }
3280
3281         if (attr_mask & IB_QP_SQ_PSN)
3282                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3283
3284         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3285                 if (attr->max_dest_rd_atomic)
3286                         context->params2 |=
3287                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3288         }
3289
3290         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3291                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3292
3293         if (attr_mask & IB_QP_MIN_RNR_TIMER)
3294                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3295
3296         if (attr_mask & IB_QP_RQ_PSN)
3297                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3298
3299         if (attr_mask & IB_QP_QKEY)
3300                 context->qkey = cpu_to_be32(attr->qkey);
3301
3302         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3303                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3304
3305         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3306                 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3307                                qp->port) - 1;
3308
3309                 /* Underlay port should be used - index 0 function per port */
3310                 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3311                         port_num = 0;
3312
3313                 mibport = &dev->port[port_num];
3314                 context->qp_counter_set_usr_page |=
3315                         cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3316         }
3317
3318         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3319                 context->sq_crq_size |= cpu_to_be16(1 << 4);
3320
3321         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3322                 context->deth_sqpn = cpu_to_be32(1);
3323
3324         mlx5_cur = to_mlx5_state(cur_state);
3325         mlx5_new = to_mlx5_state(new_state);
3326
3327         if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3328             !optab[mlx5_cur][mlx5_new]) {
3329                 err = -EINVAL;
3330                 goto out;
3331         }
3332
3333         op = optab[mlx5_cur][mlx5_new];
3334         optpar = ib_mask_to_mlx5_opt(attr_mask);
3335         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3336
3337         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3338             qp->flags & MLX5_IB_QP_UNDERLAY) {
3339                 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3340
3341                 raw_qp_param.operation = op;
3342                 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3343                         raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3344                         raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3345                 }
3346
3347                 if (attr_mask & IB_QP_RATE_LIMIT) {
3348                         raw_qp_param.rl.rate = attr->rate_limit;
3349
3350                         if (ucmd->burst_info.max_burst_sz) {
3351                                 if (attr->rate_limit &&
3352                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3353                                         raw_qp_param.rl.max_burst_sz =
3354                                                 ucmd->burst_info.max_burst_sz;
3355                                 } else {
3356                                         err = -EINVAL;
3357                                         goto out;
3358                                 }
3359                         }
3360
3361                         if (ucmd->burst_info.typical_pkt_sz) {
3362                                 if (attr->rate_limit &&
3363                                     MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3364                                         raw_qp_param.rl.typical_pkt_sz =
3365                                                 ucmd->burst_info.typical_pkt_sz;
3366                                 } else {
3367                                         err = -EINVAL;
3368                                         goto out;
3369                                 }
3370                         }
3371
3372                         raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3373                 }
3374
3375                 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3376         } else {
3377                 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3378                                           &base->mqp);
3379         }
3380
3381         if (err)
3382                 goto out;
3383
3384         qp->state = new_state;
3385
3386         if (attr_mask & IB_QP_ACCESS_FLAGS)
3387                 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3388         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3389                 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3390         if (attr_mask & IB_QP_PORT)
3391                 qp->port = attr->port_num;
3392         if (attr_mask & IB_QP_ALT_PATH)
3393                 qp->trans_qp.alt_port = attr->alt_port_num;
3394
3395         /*
3396          * If we moved a kernel QP to RESET, clean up all old CQ
3397          * entries and reinitialize the QP.
3398          */
3399         if (new_state == IB_QPS_RESET &&
3400             !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3401                 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3402                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3403                 if (send_cq != recv_cq)
3404                         mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3405
3406                 qp->rq.head = 0;
3407                 qp->rq.tail = 0;
3408                 qp->sq.head = 0;
3409                 qp->sq.tail = 0;
3410                 qp->sq.cur_post = 0;
3411                 qp->sq.last_poll = 0;
3412                 qp->db.db[MLX5_RCV_DBR] = 0;
3413                 qp->db.db[MLX5_SND_DBR] = 0;
3414         }
3415
3416 out:
3417         kfree(context);
3418         return err;
3419 }
3420
3421 static inline bool is_valid_mask(int mask, int req, int opt)
3422 {
3423         if ((mask & req) != req)
3424                 return false;
3425
3426         if (mask & ~(req | opt))
3427                 return false;
3428
3429         return true;
3430 }
3431
3432 /* check valid transition for driver QP types
3433  * for now the only QP type that this function supports is DCI
3434  */
3435 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3436                                 enum ib_qp_attr_mask attr_mask)
3437 {
3438         int req = IB_QP_STATE;
3439         int opt = 0;
3440
3441         if (new_state == IB_QPS_RESET) {
3442                 return is_valid_mask(attr_mask, req, opt);
3443         } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3444                 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3445                 return is_valid_mask(attr_mask, req, opt);
3446         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3447                 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3448                 return is_valid_mask(attr_mask, req, opt);
3449         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3450                 req |= IB_QP_PATH_MTU;
3451                 opt = IB_QP_PKEY_INDEX;
3452                 return is_valid_mask(attr_mask, req, opt);
3453         } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3454                 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3455                        IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3456                 opt = IB_QP_MIN_RNR_TIMER;
3457                 return is_valid_mask(attr_mask, req, opt);
3458         } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3459                 opt = IB_QP_MIN_RNR_TIMER;
3460                 return is_valid_mask(attr_mask, req, opt);
3461         } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3462                 return is_valid_mask(attr_mask, req, opt);
3463         }
3464         return false;
3465 }
3466
3467 /* mlx5_ib_modify_dct: modify a DCT QP
3468  * valid transitions are:
3469  * RESET to INIT: must set access_flags, pkey_index and port
3470  * INIT  to RTR : must set min_rnr_timer, tclass, flow_label,
3471  *                         mtu, gid_index and hop_limit
3472  * Other transitions and attributes are illegal
3473  */
3474 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3475                               int attr_mask, struct ib_udata *udata)
3476 {
3477         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3478         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3479         enum ib_qp_state cur_state, new_state;
3480         int err = 0;
3481         int required = IB_QP_STATE;
3482         void *dctc;
3483
3484         if (!(attr_mask & IB_QP_STATE))
3485                 return -EINVAL;
3486
3487         cur_state = qp->state;
3488         new_state = attr->qp_state;
3489
3490         dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3491         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3492                 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3493                 if (!is_valid_mask(attr_mask, required, 0))
3494                         return -EINVAL;
3495
3496                 if (attr->port_num == 0 ||
3497                     attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3498                         mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3499                                     attr->port_num, dev->num_ports);
3500                         return -EINVAL;
3501                 }
3502                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3503                         MLX5_SET(dctc, dctc, rre, 1);
3504                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3505                         MLX5_SET(dctc, dctc, rwe, 1);
3506                 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3507                         if (!mlx5_ib_dc_atomic_is_supported(dev))
3508                                 return -EOPNOTSUPP;
3509                         MLX5_SET(dctc, dctc, rae, 1);
3510                         MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3511                 }
3512                 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3513                 MLX5_SET(dctc, dctc, port, attr->port_num);
3514                 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3515
3516         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3517                 struct mlx5_ib_modify_qp_resp resp = {};
3518                 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3519                                    sizeof(resp.dctn);
3520
3521                 if (udata->outlen < min_resp_len)
3522                         return -EINVAL;
3523                 resp.response_length = min_resp_len;
3524
3525                 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3526                 if (!is_valid_mask(attr_mask, required, 0))
3527                         return -EINVAL;
3528                 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3529                 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3530                 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3531                 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3532                 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3533                 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3534
3535                 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3536                                            MLX5_ST_SZ_BYTES(create_dct_in));
3537                 if (err)
3538                         return err;
3539                 resp.dctn = qp->dct.mdct.mqp.qpn;
3540                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3541                 if (err) {
3542                         mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3543                         return err;
3544                 }
3545         } else {
3546                 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3547                 return -EINVAL;
3548         }
3549         if (err)
3550                 qp->state = IB_QPS_ERR;
3551         else
3552                 qp->state = new_state;
3553         return err;
3554 }
3555
3556 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3557                       int attr_mask, struct ib_udata *udata)
3558 {
3559         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3560         struct mlx5_ib_qp *qp = to_mqp(ibqp);
3561         struct mlx5_ib_modify_qp ucmd = {};
3562         enum ib_qp_type qp_type;
3563         enum ib_qp_state cur_state, new_state;
3564         size_t required_cmd_sz;
3565         int err = -EINVAL;
3566         int port;
3567
3568         if (ibqp->rwq_ind_tbl)
3569                 return -ENOSYS;
3570
3571         if (udata && udata->inlen) {
3572                 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3573                         sizeof(ucmd.reserved);
3574                 if (udata->inlen < required_cmd_sz)
3575                         return -EINVAL;
3576
3577                 if (udata->inlen > sizeof(ucmd) &&
3578                     !ib_is_udata_cleared(udata, sizeof(ucmd),
3579                                          udata->inlen - sizeof(ucmd)))
3580                         return -EOPNOTSUPP;
3581
3582                 if (ib_copy_from_udata(&ucmd, udata,
3583                                        min(udata->inlen, sizeof(ucmd))))
3584                         return -EFAULT;
3585
3586                 if (ucmd.comp_mask ||
3587                     memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3588                     memchr_inv(&ucmd.burst_info.reserved, 0,
3589                                sizeof(ucmd.burst_info.reserved)))
3590                         return -EOPNOTSUPP;
3591         }
3592
3593         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3594                 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3595
3596         if (ibqp->qp_type == IB_QPT_DRIVER)
3597                 qp_type = qp->qp_sub_type;
3598         else
3599                 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3600                         IB_QPT_GSI : ibqp->qp_type;
3601
3602         if (qp_type == MLX5_IB_QPT_DCT)
3603                 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3604
3605         mutex_lock(&qp->mutex);
3606
3607         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3608         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3609
3610         if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3611                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3612         }
3613
3614         if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3615                 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3616                         mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3617                                     attr_mask);
3618                         goto out;
3619                 }
3620         } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3621                    qp_type != MLX5_IB_QPT_DCI &&
3622                    !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3623                                        attr_mask)) {
3624                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3625                             cur_state, new_state, ibqp->qp_type, attr_mask);
3626                 goto out;
3627         } else if (qp_type == MLX5_IB_QPT_DCI &&
3628                    !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3629                 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3630                             cur_state, new_state, qp_type, attr_mask);
3631                 goto out;
3632         }
3633
3634         if ((attr_mask & IB_QP_PORT) &&
3635             (attr->port_num == 0 ||
3636              attr->port_num > dev->num_ports)) {
3637                 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3638                             attr->port_num, dev->num_ports);
3639                 goto out;
3640         }
3641
3642         if (attr_mask & IB_QP_PKEY_INDEX) {
3643                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3644                 if (attr->pkey_index >=
3645                     dev->mdev->port_caps[port - 1].pkey_table_len) {
3646                         mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3647                                     attr->pkey_index);
3648                         goto out;
3649                 }
3650         }
3651
3652         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3653             attr->max_rd_atomic >
3654             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3655                 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3656                             attr->max_rd_atomic);
3657                 goto out;
3658         }
3659
3660         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3661             attr->max_dest_rd_atomic >
3662             (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3663                 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3664                             attr->max_dest_rd_atomic);
3665                 goto out;
3666         }
3667
3668         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3669                 err = 0;
3670                 goto out;
3671         }
3672
3673         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3674                                   new_state, &ucmd);
3675
3676 out:
3677         mutex_unlock(&qp->mutex);
3678         return err;
3679 }
3680
3681 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3682 {
3683         struct mlx5_ib_cq *cq;
3684         unsigned cur;
3685
3686         cur = wq->head - wq->tail;
3687         if (likely(cur + nreq < wq->max_post))
3688                 return 0;
3689
3690         cq = to_mcq(ib_cq);
3691         spin_lock(&cq->lock);
3692         cur = wq->head - wq->tail;
3693         spin_unlock(&cq->lock);
3694
3695         return cur + nreq >= wq->max_post;
3696 }
3697
3698 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3699                                           u64 remote_addr, u32 rkey)
3700 {
3701         rseg->raddr    = cpu_to_be64(remote_addr);
3702         rseg->rkey     = cpu_to_be32(rkey);
3703         rseg->reserved = 0;
3704 }
3705
3706 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3707                          const struct ib_send_wr *wr, void *qend,
3708                          struct mlx5_ib_qp *qp, int *size)
3709 {
3710         void *seg = eseg;
3711
3712         memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3713
3714         if (wr->send_flags & IB_SEND_IP_CSUM)
3715                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3716                                  MLX5_ETH_WQE_L4_CSUM;
3717
3718         seg += sizeof(struct mlx5_wqe_eth_seg);
3719         *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3720
3721         if (wr->opcode == IB_WR_LSO) {
3722                 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3723                 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3724                 u64 left, leftlen, copysz;
3725                 void *pdata = ud_wr->header;
3726
3727                 left = ud_wr->hlen;
3728                 eseg->mss = cpu_to_be16(ud_wr->mss);
3729                 eseg->inline_hdr.sz = cpu_to_be16(left);
3730
3731                 /*
3732                  * check if there is space till the end of queue, if yes,
3733                  * copy all in one shot, otherwise copy till the end of queue,
3734                  * rollback and than the copy the left
3735                  */
3736                 leftlen = qend - (void *)eseg->inline_hdr.start;
3737                 copysz = min_t(u64, leftlen, left);
3738
3739                 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3740
3741                 if (likely(copysz > size_of_inl_hdr_start)) {
3742                         seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3743                         *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3744                 }
3745
3746                 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3747                         seg = mlx5_get_send_wqe(qp, 0);
3748                         left -= copysz;
3749                         pdata += copysz;
3750                         memcpy(seg, pdata, left);
3751                         seg += ALIGN(left, 16);
3752                         *size += ALIGN(left, 16) / 16;
3753                 }
3754         }
3755
3756         return seg;
3757 }
3758
3759 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3760                              const struct ib_send_wr *wr)
3761 {
3762         memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3763         dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3764         dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3765 }
3766
3767 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3768 {
3769         dseg->byte_count = cpu_to_be32(sg->length);
3770         dseg->lkey       = cpu_to_be32(sg->lkey);
3771         dseg->addr       = cpu_to_be64(sg->addr);
3772 }
3773
3774 static u64 get_xlt_octo(u64 bytes)
3775 {
3776         return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3777                MLX5_IB_UMR_OCTOWORD;
3778 }
3779
3780 static __be64 frwr_mkey_mask(void)
3781 {
3782         u64 result;
3783
3784         result = MLX5_MKEY_MASK_LEN             |
3785                 MLX5_MKEY_MASK_PAGE_SIZE        |
3786                 MLX5_MKEY_MASK_START_ADDR       |
3787                 MLX5_MKEY_MASK_EN_RINVAL        |
3788                 MLX5_MKEY_MASK_KEY              |
3789                 MLX5_MKEY_MASK_LR               |
3790                 MLX5_MKEY_MASK_LW               |
3791                 MLX5_MKEY_MASK_RR               |
3792                 MLX5_MKEY_MASK_RW               |
3793                 MLX5_MKEY_MASK_A                |
3794                 MLX5_MKEY_MASK_SMALL_FENCE      |
3795                 MLX5_MKEY_MASK_FREE;
3796
3797         return cpu_to_be64(result);
3798 }
3799
3800 static __be64 sig_mkey_mask(void)
3801 {
3802         u64 result;
3803
3804         result = MLX5_MKEY_MASK_LEN             |
3805                 MLX5_MKEY_MASK_PAGE_SIZE        |
3806                 MLX5_MKEY_MASK_START_ADDR       |
3807                 MLX5_MKEY_MASK_EN_SIGERR        |
3808                 MLX5_MKEY_MASK_EN_RINVAL        |
3809                 MLX5_MKEY_MASK_KEY              |
3810                 MLX5_MKEY_MASK_LR               |
3811                 MLX5_MKEY_MASK_LW               |
3812                 MLX5_MKEY_MASK_RR               |
3813                 MLX5_MKEY_MASK_RW               |
3814                 MLX5_MKEY_MASK_SMALL_FENCE      |
3815                 MLX5_MKEY_MASK_FREE             |
3816                 MLX5_MKEY_MASK_BSF_EN;
3817
3818         return cpu_to_be64(result);
3819 }
3820
3821 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3822                             struct mlx5_ib_mr *mr, bool umr_inline)
3823 {
3824         int size = mr->ndescs * mr->desc_size;
3825
3826         memset(umr, 0, sizeof(*umr));
3827
3828         umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3829         if (umr_inline)
3830                 umr->flags |= MLX5_UMR_INLINE;
3831         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3832         umr->mkey_mask = frwr_mkey_mask();
3833 }
3834
3835 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3836 {
3837         memset(umr, 0, sizeof(*umr));
3838         umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3839         umr->flags = MLX5_UMR_INLINE;
3840 }
3841
3842 static __be64 get_umr_enable_mr_mask(void)
3843 {
3844         u64 result;
3845
3846         result = MLX5_MKEY_MASK_KEY |
3847                  MLX5_MKEY_MASK_FREE;
3848
3849         return cpu_to_be64(result);
3850 }
3851
3852 static __be64 get_umr_disable_mr_mask(void)
3853 {
3854         u64 result;
3855
3856         result = MLX5_MKEY_MASK_FREE;
3857
3858         return cpu_to_be64(result);
3859 }
3860
3861 static __be64 get_umr_update_translation_mask(void)
3862 {
3863         u64 result;
3864
3865         result = MLX5_MKEY_MASK_LEN |
3866                  MLX5_MKEY_MASK_PAGE_SIZE |
3867                  MLX5_MKEY_MASK_START_ADDR;
3868
3869         return cpu_to_be64(result);
3870 }
3871
3872 static __be64 get_umr_update_access_mask(int atomic)
3873 {
3874         u64 result;
3875
3876         result = MLX5_MKEY_MASK_LR |
3877                  MLX5_MKEY_MASK_LW |
3878                  MLX5_MKEY_MASK_RR |
3879                  MLX5_MKEY_MASK_RW;
3880
3881         if (atomic)
3882                 result |= MLX5_MKEY_MASK_A;
3883
3884         return cpu_to_be64(result);
3885 }
3886
3887 static __be64 get_umr_update_pd_mask(void)
3888 {
3889         u64 result;
3890
3891         result = MLX5_MKEY_MASK_PD;
3892
3893         return cpu_to_be64(result);
3894 }
3895
3896 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
3897 {
3898         if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
3899              MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
3900             (mask & MLX5_MKEY_MASK_A &&
3901              MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
3902                 return -EPERM;
3903         return 0;
3904 }
3905
3906 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
3907                                struct mlx5_wqe_umr_ctrl_seg *umr,
3908                                const struct ib_send_wr *wr, int atomic)
3909 {
3910         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
3911
3912         memset(umr, 0, sizeof(*umr));
3913
3914         if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3915                 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3916         else
3917                 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3918
3919         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3920         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3921                 u64 offset = get_xlt_octo(umrwr->offset);
3922
3923                 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3924                 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3925                 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3926         }
3927         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3928                 umr->mkey_mask |= get_umr_update_translation_mask();
3929         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3930                 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3931                 umr->mkey_mask |= get_umr_update_pd_mask();
3932         }
3933         if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3934                 umr->mkey_mask |= get_umr_enable_mr_mask();
3935         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3936                 umr->mkey_mask |= get_umr_disable_mr_mask();
3937
3938         if (!wr->num_sge)
3939                 umr->flags |= MLX5_UMR_INLINE;
3940
3941         return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
3942 }
3943
3944 static u8 get_umr_flags(int acc)
3945 {
3946         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
3947                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
3948                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
3949                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
3950                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3951 }
3952
3953 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3954                              struct mlx5_ib_mr *mr,
3955                              u32 key, int access)
3956 {
3957         int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3958
3959         memset(seg, 0, sizeof(*seg));
3960
3961         if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3962                 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3963         else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3964                 /* KLMs take twice the size of MTTs */
3965                 ndescs *= 2;
3966
3967         seg->flags = get_umr_flags(access) | mr->access_mode;
3968         seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3969         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3970         seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3971         seg->len = cpu_to_be64(mr->ibmr.length);
3972         seg->xlt_oct_size = cpu_to_be32(ndescs);
3973 }
3974
3975 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3976 {
3977         memset(seg, 0, sizeof(*seg));
3978         seg->status = MLX5_MKEY_STATUS_FREE;
3979 }
3980
3981 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
3982                                  const struct ib_send_wr *wr)
3983 {
3984         const struct mlx5_umr_wr *umrwr = umr_wr(wr);
3985
3986         memset(seg, 0, sizeof(*seg));
3987         if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3988                 seg->status = MLX5_MKEY_STATUS_FREE;
3989
3990         seg->flags = convert_access(umrwr->access_flags);
3991         if (umrwr->pd)
3992                 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3993         if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3994             !umrwr->length)
3995                 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3996
3997         seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3998         seg->len = cpu_to_be64(umrwr->length);
3999         seg->log2_page_size = umrwr->page_shift;
4000         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4001                                        mlx5_mkey_variant(umrwr->mkey));
4002 }
4003
4004 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4005                              struct mlx5_ib_mr *mr,
4006                              struct mlx5_ib_pd *pd)
4007 {
4008         int bcount = mr->desc_size * mr->ndescs;
4009
4010         dseg->addr = cpu_to_be64(mr->desc_map);
4011         dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4012         dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4013 }
4014
4015 static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp,
4016                                    struct mlx5_ib_mr *mr, int mr_list_size)
4017 {
4018         void *qend = qp->sq.qend;
4019         void *addr = mr->descs;
4020         int copy;
4021
4022         if (unlikely(seg + mr_list_size > qend)) {
4023                 copy = qend - seg;
4024                 memcpy(seg, addr, copy);
4025                 addr += copy;
4026                 mr_list_size -= copy;
4027                 seg = mlx5_get_send_wqe(qp, 0);
4028         }
4029         memcpy(seg, addr, mr_list_size);
4030         seg += mr_list_size;
4031 }
4032
4033 static __be32 send_ieth(const struct ib_send_wr *wr)
4034 {
4035         switch (wr->opcode) {
4036         case IB_WR_SEND_WITH_IMM:
4037         case IB_WR_RDMA_WRITE_WITH_IMM:
4038                 return wr->ex.imm_data;
4039
4040         case IB_WR_SEND_WITH_INV:
4041                 return cpu_to_be32(wr->ex.invalidate_rkey);
4042
4043         default:
4044                 return 0;
4045         }
4046 }
4047
4048 static u8 calc_sig(void *wqe, int size)
4049 {
4050         u8 *p = wqe;
4051         u8 res = 0;
4052         int i;
4053
4054         for (i = 0; i < size; i++)
4055                 res ^= p[i];
4056
4057         return ~res;
4058 }
4059
4060 static u8 wq_sig(void *wqe)
4061 {
4062         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4063 }
4064
4065 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4066                             void *wqe, int *sz)
4067 {
4068         struct mlx5_wqe_inline_seg *seg;
4069         void *qend = qp->sq.qend;
4070         void *addr;
4071         int inl = 0;
4072         int copy;
4073         int len;
4074         int i;
4075
4076         seg = wqe;
4077         wqe += sizeof(*seg);
4078         for (i = 0; i < wr->num_sge; i++) {
4079                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4080                 len  = wr->sg_list[i].length;
4081                 inl += len;
4082
4083                 if (unlikely(inl > qp->max_inline_data))
4084                         return -ENOMEM;
4085
4086                 if (unlikely(wqe + len > qend)) {
4087                         copy = qend - wqe;
4088                         memcpy(wqe, addr, copy);
4089                         addr += copy;
4090                         len -= copy;
4091                         wqe = mlx5_get_send_wqe(qp, 0);
4092                 }
4093                 memcpy(wqe, addr, len);
4094                 wqe += len;
4095         }
4096
4097         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4098
4099         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4100
4101         return 0;
4102 }
4103
4104 static u16 prot_field_size(enum ib_signature_type type)
4105 {
4106         switch (type) {
4107         case IB_SIG_TYPE_T10_DIF:
4108                 return MLX5_DIF_SIZE;
4109         default:
4110                 return 0;
4111         }
4112 }
4113
4114 static u8 bs_selector(int block_size)
4115 {
4116         switch (block_size) {
4117         case 512:           return 0x1;
4118         case 520:           return 0x2;
4119         case 4096:          return 0x3;
4120         case 4160:          return 0x4;
4121         case 1073741824:    return 0x5;
4122         default:            return 0;
4123         }
4124 }
4125
4126 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4127                               struct mlx5_bsf_inl *inl)
4128 {
4129         /* Valid inline section and allow BSF refresh */
4130         inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4131                                        MLX5_BSF_REFRESH_DIF);
4132         inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4133         inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4134         /* repeating block */
4135         inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4136         inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4137                         MLX5_DIF_CRC : MLX5_DIF_IPCS;
4138
4139         if (domain->sig.dif.ref_remap)
4140                 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4141
4142         if (domain->sig.dif.app_escape) {
4143                 if (domain->sig.dif.ref_escape)
4144                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4145                 else
4146                         inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4147         }
4148
4149         inl->dif_app_bitmask_check =
4150                 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4151 }
4152
4153 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4154                         struct ib_sig_attrs *sig_attrs,
4155                         struct mlx5_bsf *bsf, u32 data_size)
4156 {
4157         struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4158         struct mlx5_bsf_basic *basic = &bsf->basic;
4159         struct ib_sig_domain *mem = &sig_attrs->mem;
4160         struct ib_sig_domain *wire = &sig_attrs->wire;
4161
4162         memset(bsf, 0, sizeof(*bsf));
4163
4164         /* Basic + Extended + Inline */
4165         basic->bsf_size_sbs = 1 << 7;
4166         /* Input domain check byte mask */
4167         basic->check_byte_mask = sig_attrs->check_mask;
4168         basic->raw_data_size = cpu_to_be32(data_size);
4169
4170         /* Memory domain */
4171         switch (sig_attrs->mem.sig_type) {
4172         case IB_SIG_TYPE_NONE:
4173                 break;
4174         case IB_SIG_TYPE_T10_DIF:
4175                 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4176                 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4177                 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4178                 break;
4179         default:
4180                 return -EINVAL;
4181         }
4182
4183         /* Wire domain */
4184         switch (sig_attrs->wire.sig_type) {
4185         case IB_SIG_TYPE_NONE:
4186                 break;
4187         case IB_SIG_TYPE_T10_DIF:
4188                 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4189                     mem->sig_type == wire->sig_type) {
4190                         /* Same block structure */
4191                         basic->bsf_size_sbs |= 1 << 4;
4192                         if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4193                                 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4194                         if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4195                                 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4196                         if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4197                                 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4198                 } else
4199                         basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4200
4201                 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4202                 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4203                 break;
4204         default:
4205                 return -EINVAL;
4206         }
4207
4208         return 0;
4209 }
4210
4211 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
4212                                 struct mlx5_ib_qp *qp, void **seg, int *size)
4213 {
4214         struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4215         struct ib_mr *sig_mr = wr->sig_mr;
4216         struct mlx5_bsf *bsf;
4217         u32 data_len = wr->wr.sg_list->length;
4218         u32 data_key = wr->wr.sg_list->lkey;
4219         u64 data_va = wr->wr.sg_list->addr;
4220         int ret;
4221         int wqe_size;
4222
4223         if (!wr->prot ||
4224             (data_key == wr->prot->lkey &&
4225              data_va == wr->prot->addr &&
4226              data_len == wr->prot->length)) {
4227                 /**
4228                  * Source domain doesn't contain signature information
4229                  * or data and protection are interleaved in memory.
4230                  * So need construct:
4231                  *                  ------------------
4232                  *                 |     data_klm     |
4233                  *                  ------------------
4234                  *                 |       BSF        |
4235                  *                  ------------------
4236                  **/
4237                 struct mlx5_klm *data_klm = *seg;
4238
4239                 data_klm->bcount = cpu_to_be32(data_len);
4240                 data_klm->key = cpu_to_be32(data_key);
4241                 data_klm->va = cpu_to_be64(data_va);
4242                 wqe_size = ALIGN(sizeof(*data_klm), 64);
4243         } else {
4244                 /**
4245                  * Source domain contains signature information
4246                  * So need construct a strided block format:
4247                  *               ---------------------------
4248                  *              |     stride_block_ctrl     |
4249                  *               ---------------------------
4250                  *              |          data_klm         |
4251                  *               ---------------------------
4252                  *              |          prot_klm         |
4253                  *               ---------------------------
4254                  *              |             BSF           |
4255                  *               ---------------------------
4256                  **/
4257                 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4258                 struct mlx5_stride_block_entry *data_sentry;
4259                 struct mlx5_stride_block_entry *prot_sentry;
4260                 u32 prot_key = wr->prot->lkey;
4261                 u64 prot_va = wr->prot->addr;
4262                 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4263                 int prot_size;
4264
4265                 sblock_ctrl = *seg;
4266                 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4267                 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4268
4269                 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4270                 if (!prot_size) {
4271                         pr_err("Bad block size given: %u\n", block_size);
4272                         return -EINVAL;
4273                 }
4274                 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4275                                                             prot_size);
4276                 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4277                 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4278                 sblock_ctrl->num_entries = cpu_to_be16(2);
4279
4280                 data_sentry->bcount = cpu_to_be16(block_size);
4281                 data_sentry->key = cpu_to_be32(data_key);
4282                 data_sentry->va = cpu_to_be64(data_va);
4283                 data_sentry->stride = cpu_to_be16(block_size);
4284
4285                 prot_sentry->bcount = cpu_to_be16(prot_size);
4286                 prot_sentry->key = cpu_to_be32(prot_key);
4287                 prot_sentry->va = cpu_to_be64(prot_va);
4288                 prot_sentry->stride = cpu_to_be16(prot_size);
4289
4290                 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4291                                  sizeof(*prot_sentry), 64);
4292         }
4293
4294         *seg += wqe_size;
4295         *size += wqe_size / 16;
4296         if (unlikely((*seg == qp->sq.qend)))
4297                 *seg = mlx5_get_send_wqe(qp, 0);
4298
4299         bsf = *seg;
4300         ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4301         if (ret)
4302                 return -EINVAL;
4303
4304         *seg += sizeof(*bsf);
4305         *size += sizeof(*bsf) / 16;
4306         if (unlikely((*seg == qp->sq.qend)))
4307                 *seg = mlx5_get_send_wqe(qp, 0);
4308
4309         return 0;
4310 }
4311
4312 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4313                                  const struct ib_sig_handover_wr *wr, u32 size,
4314                                  u32 length, u32 pdn)
4315 {
4316         struct ib_mr *sig_mr = wr->sig_mr;
4317         u32 sig_key = sig_mr->rkey;
4318         u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4319
4320         memset(seg, 0, sizeof(*seg));
4321
4322         seg->flags = get_umr_flags(wr->access_flags) |
4323                                    MLX5_MKC_ACCESS_MODE_KLMS;
4324         seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4325         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4326                                     MLX5_MKEY_BSF_EN | pdn);
4327         seg->len = cpu_to_be64(length);
4328         seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4329         seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4330 }
4331
4332 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4333                                 u32 size)
4334 {
4335         memset(umr, 0, sizeof(*umr));
4336
4337         umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4338         umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4339         umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4340         umr->mkey_mask = sig_mkey_mask();
4341 }
4342
4343
4344 static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
4345                           struct mlx5_ib_qp *qp, void **seg, int *size)
4346 {
4347         const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4348         struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4349         u32 pdn = get_pd(qp)->pdn;
4350         u32 xlt_size;
4351         int region_len, ret;
4352
4353         if (unlikely(wr->wr.num_sge != 1) ||
4354             unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4355             unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4356             unlikely(!sig_mr->sig->sig_status_checked))
4357                 return -EINVAL;
4358
4359         /* length of the protected region, data + protection */
4360         region_len = wr->wr.sg_list->length;
4361         if (wr->prot &&
4362             (wr->prot->lkey != wr->wr.sg_list->lkey  ||
4363              wr->prot->addr != wr->wr.sg_list->addr  ||
4364              wr->prot->length != wr->wr.sg_list->length))
4365                 region_len += wr->prot->length;
4366
4367         /**
4368          * KLM octoword size - if protection was provided
4369          * then we use strided block format (3 octowords),
4370          * else we use single KLM (1 octoword)
4371          **/
4372         xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4373
4374         set_sig_umr_segment(*seg, xlt_size);
4375         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4376         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4377         if (unlikely((*seg == qp->sq.qend)))
4378                 *seg = mlx5_get_send_wqe(qp, 0);
4379
4380         set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4381         *seg += sizeof(struct mlx5_mkey_seg);
4382         *size += sizeof(struct mlx5_mkey_seg) / 16;
4383         if (unlikely((*seg == qp->sq.qend)))
4384                 *seg = mlx5_get_send_wqe(qp, 0);
4385
4386         ret = set_sig_data_segment(wr, qp, seg, size);
4387         if (ret)
4388                 return ret;
4389
4390         sig_mr->sig->sig_status_checked = false;
4391         return 0;
4392 }
4393
4394 static int set_psv_wr(struct ib_sig_domain *domain,
4395                       u32 psv_idx, void **seg, int *size)
4396 {
4397         struct mlx5_seg_set_psv *psv_seg = *seg;
4398
4399         memset(psv_seg, 0, sizeof(*psv_seg));
4400         psv_seg->psv_num = cpu_to_be32(psv_idx);
4401         switch (domain->sig_type) {
4402         case IB_SIG_TYPE_NONE:
4403                 break;
4404         case IB_SIG_TYPE_T10_DIF:
4405                 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4406                                                      domain->sig.dif.app_tag);
4407                 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4408                 break;
4409         default:
4410                 pr_err("Bad signature type (%d) is given.\n",
4411                        domain->sig_type);
4412                 return -EINVAL;
4413         }
4414
4415         *seg += sizeof(*psv_seg);
4416         *size += sizeof(*psv_seg) / 16;
4417
4418         return 0;
4419 }
4420
4421 static int set_reg_wr(struct mlx5_ib_qp *qp,
4422                       const struct ib_reg_wr *wr,
4423                       void **seg, int *size)
4424 {
4425         struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4426         struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4427         int mr_list_size = mr->ndescs * mr->desc_size;
4428         bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4429
4430         if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4431                 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4432                              "Invalid IB_SEND_INLINE send flag\n");
4433                 return -EINVAL;
4434         }
4435
4436         set_reg_umr_seg(*seg, mr, umr_inline);
4437         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4438         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4439         if (unlikely((*seg == qp->sq.qend)))
4440                 *seg = mlx5_get_send_wqe(qp, 0);
4441
4442         set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4443         *seg += sizeof(struct mlx5_mkey_seg);
4444         *size += sizeof(struct mlx5_mkey_seg) / 16;
4445         if (unlikely((*seg == qp->sq.qend)))
4446                 *seg = mlx5_get_send_wqe(qp, 0);
4447
4448         if (umr_inline) {
4449                 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size);
4450                 *size += get_xlt_octo(mr_list_size);
4451         } else {
4452                 set_reg_data_seg(*seg, mr, pd);
4453                 *seg += sizeof(struct mlx5_wqe_data_seg);
4454                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4455         }
4456         return 0;
4457 }
4458
4459 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
4460 {
4461         set_linv_umr_seg(*seg);
4462         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4463         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4464         if (unlikely((*seg == qp->sq.qend)))
4465                 *seg = mlx5_get_send_wqe(qp, 0);
4466         set_linv_mkey_seg(*seg);
4467         *seg += sizeof(struct mlx5_mkey_seg);
4468         *size += sizeof(struct mlx5_mkey_seg) / 16;
4469         if (unlikely((*seg == qp->sq.qend)))
4470                 *seg = mlx5_get_send_wqe(qp, 0);
4471 }
4472
4473 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4474 {
4475         __be32 *p = NULL;
4476         int tidx = idx;
4477         int i, j;
4478
4479         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4480         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4481                 if ((i & 0xf) == 0) {
4482                         void *buf = mlx5_get_send_wqe(qp, tidx);
4483                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4484                         p = buf;
4485                         j = 0;
4486                 }
4487                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4488                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4489                          be32_to_cpu(p[j + 3]));
4490         }
4491 }
4492
4493 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4494                      struct mlx5_wqe_ctrl_seg **ctrl,
4495                      const struct ib_send_wr *wr, unsigned *idx,
4496                      int *size, int nreq, bool send_signaled, bool solicited)
4497 {
4498         if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4499                 return -ENOMEM;
4500
4501         *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4502         *seg = mlx5_get_send_wqe(qp, *idx);
4503         *ctrl = *seg;
4504         *(uint32_t *)(*seg + 8) = 0;
4505         (*ctrl)->imm = send_ieth(wr);
4506         (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4507                 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4508                 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4509
4510         *seg += sizeof(**ctrl);
4511         *size = sizeof(**ctrl) / 16;
4512
4513         return 0;
4514 }
4515
4516 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4517                      struct mlx5_wqe_ctrl_seg **ctrl,
4518                      const struct ib_send_wr *wr, unsigned *idx,
4519                      int *size, int nreq)
4520 {
4521         return __begin_wqe(qp, seg, ctrl, wr, idx, size, nreq,
4522                            wr->send_flags & IB_SEND_SIGNALED,
4523                            wr->send_flags & IB_SEND_SOLICITED);
4524 }
4525
4526 static void finish_wqe(struct mlx5_ib_qp *qp,
4527                        struct mlx5_wqe_ctrl_seg *ctrl,
4528                        u8 size, unsigned idx, u64 wr_id,
4529                        int nreq, u8 fence, u32 mlx5_opcode)
4530 {
4531         u8 opmod = 0;
4532
4533         ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4534                                              mlx5_opcode | ((u32)opmod << 24));
4535         ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4536         ctrl->fm_ce_se |= fence;
4537         if (unlikely(qp->wq_sig))
4538                 ctrl->signature = wq_sig(ctrl);
4539
4540         qp->sq.wrid[idx] = wr_id;
4541         qp->sq.w_list[idx].opcode = mlx5_opcode;
4542         qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4543         qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4544         qp->sq.w_list[idx].next = qp->sq.cur_post;
4545 }
4546
4547 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4548                               const struct ib_send_wr **bad_wr, bool drain)
4549 {
4550         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
4551         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4552         struct mlx5_core_dev *mdev = dev->mdev;
4553         struct mlx5_ib_qp *qp;
4554         struct mlx5_ib_mr *mr;
4555         struct mlx5_wqe_data_seg *dpseg;
4556         struct mlx5_wqe_xrc_seg *xrc;
4557         struct mlx5_bf *bf;
4558         int uninitialized_var(size);
4559         void *qend;
4560         unsigned long flags;
4561         unsigned idx;
4562         int err = 0;
4563         int num_sge;
4564         void *seg;
4565         int nreq;
4566         int i;
4567         u8 next_fence = 0;
4568         u8 fence;
4569
4570         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4571                      !drain)) {
4572                 *bad_wr = wr;
4573                 return -EIO;
4574         }
4575
4576         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4577                 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4578
4579         qp = to_mqp(ibqp);
4580         bf = &qp->bf;
4581         qend = qp->sq.qend;
4582
4583         spin_lock_irqsave(&qp->sq.lock, flags);
4584
4585         for (nreq = 0; wr; nreq++, wr = wr->next) {
4586                 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4587                         mlx5_ib_warn(dev, "\n");
4588                         err = -EINVAL;
4589                         *bad_wr = wr;
4590                         goto out;
4591                 }
4592
4593                 num_sge = wr->num_sge;
4594                 if (unlikely(num_sge > qp->sq.max_gs)) {
4595                         mlx5_ib_warn(dev, "\n");
4596                         err = -EINVAL;
4597                         *bad_wr = wr;
4598                         goto out;
4599                 }
4600
4601                 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4602                 if (err) {
4603                         mlx5_ib_warn(dev, "\n");
4604                         err = -ENOMEM;
4605                         *bad_wr = wr;
4606                         goto out;
4607                 }
4608
4609                 if (wr->opcode == IB_WR_LOCAL_INV ||
4610                     wr->opcode == IB_WR_REG_MR) {
4611                         fence = dev->umr_fence;
4612                         next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4613                 } else if (wr->send_flags & IB_SEND_FENCE) {
4614                         if (qp->next_fence)
4615                                 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4616                         else
4617                                 fence = MLX5_FENCE_MODE_FENCE;
4618                 } else {
4619                         fence = qp->next_fence;
4620                 }
4621
4622                 switch (ibqp->qp_type) {
4623                 case IB_QPT_XRC_INI:
4624                         xrc = seg;
4625                         seg += sizeof(*xrc);
4626                         size += sizeof(*xrc) / 16;
4627                         /* fall through */
4628                 case IB_QPT_RC:
4629                         switch (wr->opcode) {
4630                         case IB_WR_RDMA_READ:
4631                         case IB_WR_RDMA_WRITE:
4632                         case IB_WR_RDMA_WRITE_WITH_IMM:
4633                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4634                                               rdma_wr(wr)->rkey);
4635                                 seg += sizeof(struct mlx5_wqe_raddr_seg);
4636                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4637                                 break;
4638
4639                         case IB_WR_ATOMIC_CMP_AND_SWP:
4640                         case IB_WR_ATOMIC_FETCH_AND_ADD:
4641                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4642                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4643                                 err = -ENOSYS;
4644                                 *bad_wr = wr;
4645                                 goto out;
4646
4647                         case IB_WR_LOCAL_INV:
4648                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4649                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4650                                 set_linv_wr(qp, &seg, &size);
4651                                 num_sge = 0;
4652                                 break;
4653
4654                         case IB_WR_REG_MR:
4655                                 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4656                                 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4657                                 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4658                                 if (err) {
4659                                         *bad_wr = wr;
4660                                         goto out;
4661                                 }
4662                                 num_sge = 0;
4663                                 break;
4664
4665                         case IB_WR_REG_SIG_MR:
4666                                 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4667                                 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4668
4669                                 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4670                                 err = set_sig_umr_wr(wr, qp, &seg, &size);
4671                                 if (err) {
4672                                         mlx5_ib_warn(dev, "\n");
4673                                         *bad_wr = wr;
4674                                         goto out;
4675                                 }
4676
4677                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4678                                            fence, MLX5_OPCODE_UMR);
4679                                 /*
4680                                  * SET_PSV WQEs are not signaled and solicited
4681                                  * on error
4682                                  */
4683                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4684                                                   &size, nreq, false, true);
4685                                 if (err) {
4686                                         mlx5_ib_warn(dev, "\n");
4687                                         err = -ENOMEM;
4688                                         *bad_wr = wr;
4689                                         goto out;
4690                                 }
4691
4692                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4693                                                  mr->sig->psv_memory.psv_idx, &seg,
4694                                                  &size);
4695                                 if (err) {
4696                                         mlx5_ib_warn(dev, "\n");
4697                                         *bad_wr = wr;
4698                                         goto out;
4699                                 }
4700
4701                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4702                                            fence, MLX5_OPCODE_SET_PSV);
4703                                 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4704                                                   &size, nreq, false, true);
4705                                 if (err) {
4706                                         mlx5_ib_warn(dev, "\n");
4707                                         err = -ENOMEM;
4708                                         *bad_wr = wr;
4709                                         goto out;
4710                                 }
4711
4712                                 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4713                                                  mr->sig->psv_wire.psv_idx, &seg,
4714                                                  &size);
4715                                 if (err) {
4716                                         mlx5_ib_warn(dev, "\n");
4717                                         *bad_wr = wr;
4718                                         goto out;
4719                                 }
4720
4721                                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4722                                            fence, MLX5_OPCODE_SET_PSV);
4723                                 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4724                                 num_sge = 0;
4725                                 goto skip_psv;
4726
4727                         default:
4728                                 break;
4729                         }
4730                         break;
4731
4732                 case IB_QPT_UC:
4733                         switch (wr->opcode) {
4734                         case IB_WR_RDMA_WRITE:
4735                         case IB_WR_RDMA_WRITE_WITH_IMM:
4736                                 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4737                                               rdma_wr(wr)->rkey);
4738                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
4739                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4740                                 break;
4741
4742                         default:
4743                                 break;
4744                         }
4745                         break;
4746
4747                 case IB_QPT_SMI:
4748                         if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4749                                 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4750                                 err = -EPERM;
4751                                 *bad_wr = wr;
4752                                 goto out;
4753                         }
4754                         /* fall through */
4755                 case MLX5_IB_QPT_HW_GSI:
4756                         set_datagram_seg(seg, wr);
4757                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4758                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4759                         if (unlikely((seg == qend)))
4760                                 seg = mlx5_get_send_wqe(qp, 0);
4761                         break;
4762                 case IB_QPT_UD:
4763                         set_datagram_seg(seg, wr);
4764                         seg += sizeof(struct mlx5_wqe_datagram_seg);
4765                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4766
4767                         if (unlikely((seg == qend)))
4768                                 seg = mlx5_get_send_wqe(qp, 0);
4769
4770                         /* handle qp that supports ud offload */
4771                         if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4772                                 struct mlx5_wqe_eth_pad *pad;
4773
4774                                 pad = seg;
4775                                 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4776                                 seg += sizeof(struct mlx5_wqe_eth_pad);
4777                                 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4778
4779                                 seg = set_eth_seg(seg, wr, qend, qp, &size);
4780
4781                                 if (unlikely((seg == qend)))
4782                                         seg = mlx5_get_send_wqe(qp, 0);
4783                         }
4784                         break;
4785                 case MLX5_IB_QPT_REG_UMR:
4786                         if (wr->opcode != MLX5_IB_WR_UMR) {
4787                                 err = -EINVAL;
4788                                 mlx5_ib_warn(dev, "bad opcode\n");
4789                                 goto out;
4790                         }
4791                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4792                         ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4793                         err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4794                         if (unlikely(err))
4795                                 goto out;
4796                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4797                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4798                         if (unlikely((seg == qend)))
4799                                 seg = mlx5_get_send_wqe(qp, 0);
4800                         set_reg_mkey_segment(seg, wr);
4801                         seg += sizeof(struct mlx5_mkey_seg);
4802                         size += sizeof(struct mlx5_mkey_seg) / 16;
4803                         if (unlikely((seg == qend)))
4804                                 seg = mlx5_get_send_wqe(qp, 0);
4805                         break;
4806
4807                 default:
4808                         break;
4809                 }
4810
4811                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4812                         int uninitialized_var(sz);
4813
4814                         err = set_data_inl_seg(qp, wr, seg, &sz);
4815                         if (unlikely(err)) {
4816                                 mlx5_ib_warn(dev, "\n");
4817                                 *bad_wr = wr;
4818                                 goto out;
4819                         }
4820                         size += sz;
4821                 } else {
4822                         dpseg = seg;
4823                         for (i = 0; i < num_sge; i++) {
4824                                 if (unlikely(dpseg == qend)) {
4825                                         seg = mlx5_get_send_wqe(qp, 0);
4826                                         dpseg = seg;
4827                                 }
4828                                 if (likely(wr->sg_list[i].length)) {
4829                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
4830                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
4831                                         dpseg++;
4832                                 }
4833                         }
4834                 }
4835
4836                 qp->next_fence = next_fence;
4837                 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4838                            mlx5_ib_opcode[wr->opcode]);
4839 skip_psv:
4840                 if (0)
4841                         dump_wqe(qp, idx, size);
4842         }
4843
4844 out:
4845         if (likely(nreq)) {
4846                 qp->sq.head += nreq;
4847
4848                 /* Make sure that descriptors are written before
4849                  * updating doorbell record and ringing the doorbell
4850                  */
4851                 wmb();
4852
4853                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4854
4855                 /* Make sure doorbell record is visible to the HCA before
4856                  * we hit doorbell */
4857                 wmb();
4858
4859                 /* currently we support only regular doorbells */
4860                 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4861                 /* Make sure doorbells don't leak out of SQ spinlock
4862                  * and reach the HCA out of order.
4863                  */
4864                 mmiowb();
4865                 bf->offset ^= bf->buf_size;
4866         }
4867
4868         spin_unlock_irqrestore(&qp->sq.lock, flags);
4869
4870         return err;
4871 }
4872
4873 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4874                       const struct ib_send_wr **bad_wr)
4875 {
4876         return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
4877 }
4878
4879 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4880 {
4881         sig->signature = calc_sig(sig, size);
4882 }
4883
4884 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4885                       const struct ib_recv_wr **bad_wr, bool drain)
4886 {
4887         struct mlx5_ib_qp *qp = to_mqp(ibqp);
4888         struct mlx5_wqe_data_seg *scat;
4889         struct mlx5_rwqe_sig *sig;
4890         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4891         struct mlx5_core_dev *mdev = dev->mdev;
4892         unsigned long flags;
4893         int err = 0;
4894         int nreq;
4895         int ind;
4896         int i;
4897
4898         if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4899                      !drain)) {
4900                 *bad_wr = wr;
4901                 return -EIO;
4902         }
4903
4904         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4905                 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4906
4907         spin_lock_irqsave(&qp->rq.lock, flags);
4908
4909         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4910
4911         for (nreq = 0; wr; nreq++, wr = wr->next) {
4912                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4913                         err = -ENOMEM;
4914                         *bad_wr = wr;
4915                         goto out;
4916                 }
4917
4918                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4919                         err = -EINVAL;
4920                         *bad_wr = wr;
4921                         goto out;
4922                 }
4923
4924                 scat = get_recv_wqe(qp, ind);
4925                 if (qp->wq_sig)
4926                         scat++;
4927
4928                 for (i = 0; i < wr->num_sge; i++)
4929                         set_data_ptr_seg(scat + i, wr->sg_list + i);
4930
4931                 if (i < qp->rq.max_gs) {
4932                         scat[i].byte_count = 0;
4933                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
4934                         scat[i].addr       = 0;
4935                 }
4936
4937                 if (qp->wq_sig) {
4938                         sig = (struct mlx5_rwqe_sig *)scat;
4939                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4940                 }
4941
4942                 qp->rq.wrid[ind] = wr->wr_id;
4943
4944                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4945         }
4946
4947 out:
4948         if (likely(nreq)) {
4949                 qp->rq.head += nreq;
4950
4951                 /* Make sure that descriptors are written before
4952                  * doorbell record.
4953                  */
4954                 wmb();
4955
4956                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4957         }
4958
4959         spin_unlock_irqrestore(&qp->rq.lock, flags);
4960
4961         return err;
4962 }
4963
4964 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4965                       const struct ib_recv_wr **bad_wr)
4966 {
4967         return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
4968 }
4969
4970 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4971 {
4972         switch (mlx5_state) {
4973         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
4974         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
4975         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
4976         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
4977         case MLX5_QP_STATE_SQ_DRAINING:
4978         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
4979         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
4980         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
4981         default:                     return -1;
4982         }
4983 }
4984
4985 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4986 {
4987         switch (mlx5_mig_state) {
4988         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
4989         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
4990         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
4991         default: return -1;
4992         }
4993 }
4994
4995 static int to_ib_qp_access_flags(int mlx5_flags)
4996 {
4997         int ib_flags = 0;
4998
4999         if (mlx5_flags & MLX5_QP_BIT_RRE)
5000                 ib_flags |= IB_ACCESS_REMOTE_READ;
5001         if (mlx5_flags & MLX5_QP_BIT_RWE)
5002                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5003         if (mlx5_flags & MLX5_QP_BIT_RAE)
5004                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5005
5006         return ib_flags;
5007 }
5008
5009 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5010                             struct rdma_ah_attr *ah_attr,
5011                             struct mlx5_qp_path *path)
5012 {
5013
5014         memset(ah_attr, 0, sizeof(*ah_attr));
5015
5016         if (!path->port || path->port > ibdev->num_ports)
5017                 return;
5018
5019         ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5020
5021         rdma_ah_set_port_num(ah_attr, path->port);
5022         rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5023
5024         rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5025         rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5026         rdma_ah_set_static_rate(ah_attr,
5027                                 path->static_rate ? path->static_rate - 5 : 0);
5028         if (path->grh_mlid & (1 << 7)) {
5029                 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5030
5031                 rdma_ah_set_grh(ah_attr, NULL,
5032                                 tc_fl & 0xfffff,
5033                                 path->mgid_index,
5034                                 path->hop_limit,
5035                                 (tc_fl >> 20) & 0xff);
5036                 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5037         }
5038 }
5039
5040 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5041                                         struct mlx5_ib_sq *sq,
5042                                         u8 *sq_state)
5043 {
5044         int err;
5045
5046         err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5047         if (err)
5048                 goto out;
5049         sq->state = *sq_state;
5050
5051 out:
5052         return err;
5053 }
5054
5055 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5056                                         struct mlx5_ib_rq *rq,
5057                                         u8 *rq_state)
5058 {
5059         void *out;
5060         void *rqc;
5061         int inlen;
5062         int err;
5063
5064         inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5065         out = kvzalloc(inlen, GFP_KERNEL);
5066         if (!out)
5067                 return -ENOMEM;
5068
5069         err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5070         if (err)
5071                 goto out;
5072
5073         rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5074         *rq_state = MLX5_GET(rqc, rqc, state);
5075         rq->state = *rq_state;
5076
5077 out:
5078         kvfree(out);
5079         return err;
5080 }
5081
5082 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5083                                   struct mlx5_ib_qp *qp, u8 *qp_state)
5084 {
5085         static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5086                 [MLX5_RQC_STATE_RST] = {
5087                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5088                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5089                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE_BAD,
5090                         [MLX5_SQ_STATE_NA]      = IB_QPS_RESET,
5091                 },
5092                 [MLX5_RQC_STATE_RDY] = {
5093                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5094                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5095                         [MLX5_SQC_STATE_ERR]    = IB_QPS_SQE,
5096                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE,
5097                 },
5098                 [MLX5_RQC_STATE_ERR] = {
5099                         [MLX5_SQC_STATE_RST]    = MLX5_QP_STATE_BAD,
5100                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE_BAD,
5101                         [MLX5_SQC_STATE_ERR]    = IB_QPS_ERR,
5102                         [MLX5_SQ_STATE_NA]      = IB_QPS_ERR,
5103                 },
5104                 [MLX5_RQ_STATE_NA] = {
5105                         [MLX5_SQC_STATE_RST]    = IB_QPS_RESET,
5106                         [MLX5_SQC_STATE_RDY]    = MLX5_QP_STATE,
5107                         [MLX5_SQC_STATE_ERR]    = MLX5_QP_STATE,
5108                         [MLX5_SQ_STATE_NA]      = MLX5_QP_STATE_BAD,
5109                 },
5110         };
5111
5112         *qp_state = sqrq_trans[rq_state][sq_state];
5113
5114         if (*qp_state == MLX5_QP_STATE_BAD) {
5115                 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5116                      qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5117                      qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5118                 return -EINVAL;
5119         }
5120
5121         if (*qp_state == MLX5_QP_STATE)
5122                 *qp_state = qp->state;
5123
5124         return 0;
5125 }
5126
5127 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5128                                      struct mlx5_ib_qp *qp,
5129                                      u8 *raw_packet_qp_state)
5130 {
5131         struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5132         struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5133         struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5134         int err;
5135         u8 sq_state = MLX5_SQ_STATE_NA;
5136         u8 rq_state = MLX5_RQ_STATE_NA;
5137
5138         if (qp->sq.wqe_cnt) {
5139                 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5140                 if (err)
5141                         return err;
5142         }
5143
5144         if (qp->rq.wqe_cnt) {
5145                 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5146                 if (err)
5147                         return err;
5148         }
5149
5150         return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5151                                       raw_packet_qp_state);
5152 }
5153
5154 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5155                          struct ib_qp_attr *qp_attr)
5156 {
5157         int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5158         struct mlx5_qp_context *context;
5159         int mlx5_state;
5160         u32 *outb;
5161         int err = 0;
5162
5163         outb = kzalloc(outlen, GFP_KERNEL);
5164         if (!outb)
5165                 return -ENOMEM;
5166
5167         err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
5168                                  outlen);
5169         if (err)
5170                 goto out;
5171
5172         /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5173         context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5174
5175         mlx5_state = be32_to_cpu(context->flags) >> 28;
5176
5177         qp->state                    = to_ib_qp_state(mlx5_state);
5178         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
5179         qp_attr->path_mig_state      =
5180                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5181         qp_attr->qkey                = be32_to_cpu(context->qkey);
5182         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5183         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
5184         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5185         qp_attr->qp_access_flags     =
5186                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5187
5188         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5189                 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5190                 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5191                 qp_attr->alt_pkey_index =
5192                         be16_to_cpu(context->alt_path.pkey_index);
5193                 qp_attr->alt_port_num   =
5194                         rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5195         }
5196
5197         qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5198         qp_attr->port_num = context->pri_path.port;
5199
5200         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5201         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5202
5203         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5204
5205         qp_attr->max_dest_rd_atomic =
5206                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5207         qp_attr->min_rnr_timer      =
5208                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5209         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
5210         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
5211         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
5212         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
5213
5214 out:
5215         kfree(outb);
5216         return err;
5217 }
5218
5219 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5220                                 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5221                                 struct ib_qp_init_attr *qp_init_attr)
5222 {
5223         struct mlx5_core_dct    *dct = &mqp->dct.mdct;
5224         u32 *out;
5225         u32 access_flags = 0;
5226         int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5227         void *dctc;
5228         int err;
5229         int supported_mask = IB_QP_STATE |
5230                              IB_QP_ACCESS_FLAGS |
5231                              IB_QP_PORT |
5232                              IB_QP_MIN_RNR_TIMER |
5233                              IB_QP_AV |
5234                              IB_QP_PATH_MTU |
5235                              IB_QP_PKEY_INDEX;
5236
5237         if (qp_attr_mask & ~supported_mask)
5238                 return -EINVAL;
5239         if (mqp->state != IB_QPS_RTR)
5240                 return -EINVAL;
5241
5242         out = kzalloc(outlen, GFP_KERNEL);
5243         if (!out)
5244                 return -ENOMEM;
5245
5246         err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5247         if (err)
5248                 goto out;
5249
5250         dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5251
5252         if (qp_attr_mask & IB_QP_STATE)
5253                 qp_attr->qp_state = IB_QPS_RTR;
5254
5255         if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5256                 if (MLX5_GET(dctc, dctc, rre))
5257                         access_flags |= IB_ACCESS_REMOTE_READ;
5258                 if (MLX5_GET(dctc, dctc, rwe))
5259                         access_flags |= IB_ACCESS_REMOTE_WRITE;
5260                 if (MLX5_GET(dctc, dctc, rae))
5261                         access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5262                 qp_attr->qp_access_flags = access_flags;
5263         }
5264
5265         if (qp_attr_mask & IB_QP_PORT)
5266                 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5267         if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5268                 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5269         if (qp_attr_mask & IB_QP_AV) {
5270                 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5271                 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5272                 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5273                 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5274         }
5275         if (qp_attr_mask & IB_QP_PATH_MTU)
5276                 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5277         if (qp_attr_mask & IB_QP_PKEY_INDEX)
5278                 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5279 out:
5280         kfree(out);
5281         return err;
5282 }
5283
5284 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5285                      int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5286 {
5287         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5288         struct mlx5_ib_qp *qp = to_mqp(ibqp);
5289         int err = 0;
5290         u8 raw_packet_qp_state;
5291
5292         if (ibqp->rwq_ind_tbl)
5293                 return -ENOSYS;
5294
5295         if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5296                 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5297                                             qp_init_attr);
5298
5299         /* Not all of output fields are applicable, make sure to zero them */
5300         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5301         memset(qp_attr, 0, sizeof(*qp_attr));
5302
5303         if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5304                 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5305                                             qp_attr_mask, qp_init_attr);
5306
5307         mutex_lock(&qp->mutex);
5308
5309         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5310             qp->flags & MLX5_IB_QP_UNDERLAY) {
5311                 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5312                 if (err)
5313                         goto out;
5314                 qp->state = raw_packet_qp_state;
5315                 qp_attr->port_num = 1;
5316         } else {
5317                 err = query_qp_attr(dev, qp, qp_attr);
5318                 if (err)
5319                         goto out;
5320         }
5321
5322         qp_attr->qp_state            = qp->state;
5323         qp_attr->cur_qp_state        = qp_attr->qp_state;
5324         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
5325         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
5326
5327         if (!ibqp->uobject) {
5328                 qp_attr->cap.max_send_wr  = qp->sq.max_post;
5329                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5330                 qp_init_attr->qp_context = ibqp->qp_context;
5331         } else {
5332                 qp_attr->cap.max_send_wr  = 0;
5333                 qp_attr->cap.max_send_sge = 0;
5334         }
5335
5336         qp_init_attr->qp_type = ibqp->qp_type;
5337         qp_init_attr->recv_cq = ibqp->recv_cq;
5338         qp_init_attr->send_cq = ibqp->send_cq;
5339         qp_init_attr->srq = ibqp->srq;
5340         qp_attr->cap.max_inline_data = qp->max_inline_data;
5341
5342         qp_init_attr->cap            = qp_attr->cap;
5343
5344         qp_init_attr->create_flags = 0;
5345         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5346                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5347
5348         if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5349                 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5350         if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5351                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5352         if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5353                 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5354         if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5355                 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5356
5357         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5358                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5359
5360 out:
5361         mutex_unlock(&qp->mutex);
5362         return err;
5363 }
5364
5365 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5366                                           struct ib_ucontext *context,
5367                                           struct ib_udata *udata)
5368 {
5369         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5370         struct mlx5_ib_xrcd *xrcd;
5371         int err;
5372         u16 uid;
5373
5374         if (!MLX5_CAP_GEN(dev->mdev, xrc))
5375                 return ERR_PTR(-ENOSYS);
5376
5377         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5378         if (!xrcd)
5379                 return ERR_PTR(-ENOMEM);
5380
5381         uid = context ? to_mucontext(context)->devx_uid : 0;
5382         err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, uid);
5383         if (err) {
5384                 kfree(xrcd);
5385                 return ERR_PTR(-ENOMEM);
5386         }
5387
5388         xrcd->uid = uid;
5389         return &xrcd->ibxrcd;
5390 }
5391
5392 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5393 {
5394         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5395         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5396         u16 uid =  to_mxrcd(xrcd)->uid;
5397         int err;
5398
5399         err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, uid);
5400         if (err)
5401                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5402
5403         kfree(xrcd);
5404         return 0;
5405 }
5406
5407 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5408 {
5409         struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5410         struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5411         struct ib_event event;
5412
5413         if (rwq->ibwq.event_handler) {
5414                 event.device     = rwq->ibwq.device;
5415                 event.element.wq = &rwq->ibwq;
5416                 switch (type) {
5417                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5418                         event.event = IB_EVENT_WQ_FATAL;
5419                         break;
5420                 default:
5421                         mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5422                         return;
5423                 }
5424
5425                 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5426         }
5427 }
5428
5429 static int set_delay_drop(struct mlx5_ib_dev *dev)
5430 {
5431         int err = 0;
5432
5433         mutex_lock(&dev->delay_drop.lock);
5434         if (dev->delay_drop.activate)
5435                 goto out;
5436
5437         err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5438         if (err)
5439                 goto out;
5440
5441         dev->delay_drop.activate = true;
5442 out:
5443         mutex_unlock(&dev->delay_drop.lock);
5444
5445         if (!err)
5446                 atomic_inc(&dev->delay_drop.rqs_cnt);
5447         return err;
5448 }
5449
5450 static int  create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5451                       struct ib_wq_init_attr *init_attr)
5452 {
5453         struct mlx5_ib_dev *dev;
5454         int has_net_offloads;
5455         __be64 *rq_pas0;
5456         void *in;
5457         void *rqc;
5458         void *wq;
5459         int inlen;
5460         int err;
5461
5462         dev = to_mdev(pd->device);
5463
5464         inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5465         in = kvzalloc(inlen, GFP_KERNEL);
5466         if (!in)
5467                 return -ENOMEM;
5468
5469         MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5470         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5471         MLX5_SET(rqc,  rqc, mem_rq_type,
5472                  MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5473         MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5474         MLX5_SET(rqc,  rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5475         MLX5_SET(rqc,  rqc, state, MLX5_RQC_STATE_RST);
5476         MLX5_SET(rqc,  rqc, flush_in_error_en, 1);
5477         wq = MLX5_ADDR_OF(rqc, rqc, wq);
5478         MLX5_SET(wq, wq, wq_type,
5479                  rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5480                  MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5481         if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5482                 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5483                         mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5484                         err = -EOPNOTSUPP;
5485                         goto out;
5486                 } else {
5487                         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5488                 }
5489         }
5490         MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5491         if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5492                 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5493                 MLX5_SET(wq, wq, log_wqe_stride_size,
5494                          rwq->single_stride_log_num_of_bytes -
5495                          MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5496                 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5497                          MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5498         }
5499         MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5500         MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5501         MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5502         MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5503         MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5504         MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5505         has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5506         if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5507                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5508                         mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5509                         err = -EOPNOTSUPP;
5510                         goto out;
5511                 }
5512         } else {
5513                 MLX5_SET(rqc, rqc, vsd, 1);
5514         }
5515         if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5516                 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5517                         mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5518                         err = -EOPNOTSUPP;
5519                         goto out;
5520                 }
5521                 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5522         }
5523         if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5524                 if (!(dev->ib_dev.attrs.raw_packet_caps &
5525                       IB_RAW_PACKET_CAP_DELAY_DROP)) {
5526                         mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5527                         err = -EOPNOTSUPP;
5528                         goto out;
5529                 }
5530                 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5531         }
5532         rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5533         mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5534         err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5535         if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5536                 err = set_delay_drop(dev);
5537                 if (err) {
5538                         mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5539                                      err);
5540                         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5541                 } else {
5542                         rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5543                 }
5544         }
5545 out:
5546         kvfree(in);
5547         return err;
5548 }
5549
5550 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5551                             struct ib_wq_init_attr *wq_init_attr,
5552                             struct mlx5_ib_create_wq *ucmd,
5553                             struct mlx5_ib_rwq *rwq)
5554 {
5555         /* Sanity check RQ size before proceeding */
5556         if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5557                 return -EINVAL;
5558
5559         if (!ucmd->rq_wqe_count)
5560                 return -EINVAL;
5561
5562         rwq->wqe_count = ucmd->rq_wqe_count;
5563         rwq->wqe_shift = ucmd->rq_wqe_shift;
5564         if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5565                 return -EINVAL;
5566
5567         rwq->log_rq_stride = rwq->wqe_shift;
5568         rwq->log_rq_size = ilog2(rwq->wqe_count);
5569         return 0;
5570 }
5571
5572 static int prepare_user_rq(struct ib_pd *pd,
5573                            struct ib_wq_init_attr *init_attr,
5574                            struct ib_udata *udata,
5575                            struct mlx5_ib_rwq *rwq)
5576 {
5577         struct mlx5_ib_dev *dev = to_mdev(pd->device);
5578         struct mlx5_ib_create_wq ucmd = {};
5579         int err;
5580         size_t required_cmd_sz;
5581
5582         required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5583                 + sizeof(ucmd.single_stride_log_num_of_bytes);
5584         if (udata->inlen < required_cmd_sz) {
5585                 mlx5_ib_dbg(dev, "invalid inlen\n");
5586                 return -EINVAL;
5587         }
5588
5589         if (udata->inlen > sizeof(ucmd) &&
5590             !ib_is_udata_cleared(udata, sizeof(ucmd),
5591                                  udata->inlen - sizeof(ucmd))) {
5592                 mlx5_ib_dbg(dev, "inlen is not supported\n");
5593                 return -EOPNOTSUPP;
5594         }
5595
5596         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5597                 mlx5_ib_dbg(dev, "copy failed\n");
5598                 return -EFAULT;
5599         }
5600
5601         if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5602                 mlx5_ib_dbg(dev, "invalid comp mask\n");
5603                 return -EOPNOTSUPP;
5604         } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5605                 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5606                         mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5607                         return -EOPNOTSUPP;
5608                 }
5609                 if ((ucmd.single_stride_log_num_of_bytes <
5610                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5611                     (ucmd.single_stride_log_num_of_bytes >
5612                      MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5613                         mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5614                                     ucmd.single_stride_log_num_of_bytes,
5615                                     MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5616                                     MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5617                         return -EINVAL;
5618                 }
5619                 if ((ucmd.single_wqe_log_num_of_strides >
5620                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5621                      (ucmd.single_wqe_log_num_of_strides <
5622                         MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5623                         mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5624                                     ucmd.single_wqe_log_num_of_strides,
5625                                     MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5626                                     MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5627                         return -EINVAL;
5628                 }
5629                 rwq->single_stride_log_num_of_bytes =
5630                         ucmd.single_stride_log_num_of_bytes;
5631                 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5632                 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5633                 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5634         }
5635
5636         err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5637         if (err) {
5638                 mlx5_ib_dbg(dev, "err %d\n", err);
5639                 return err;
5640         }
5641
5642         err = create_user_rq(dev, pd, rwq, &ucmd);
5643         if (err) {
5644                 mlx5_ib_dbg(dev, "err %d\n", err);
5645                 return err;
5646         }
5647
5648         rwq->user_index = ucmd.user_index;
5649         return 0;
5650 }
5651
5652 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5653                                 struct ib_wq_init_attr *init_attr,
5654                                 struct ib_udata *udata)
5655 {
5656         struct mlx5_ib_dev *dev;
5657         struct mlx5_ib_rwq *rwq;
5658         struct mlx5_ib_create_wq_resp resp = {};
5659         size_t min_resp_len;
5660         int err;
5661
5662         if (!udata)
5663                 return ERR_PTR(-ENOSYS);
5664
5665         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5666         if (udata->outlen && udata->outlen < min_resp_len)
5667                 return ERR_PTR(-EINVAL);
5668
5669         dev = to_mdev(pd->device);
5670         switch (init_attr->wq_type) {
5671         case IB_WQT_RQ:
5672                 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5673                 if (!rwq)
5674                         return ERR_PTR(-ENOMEM);
5675                 err = prepare_user_rq(pd, init_attr, udata, rwq);
5676                 if (err)
5677                         goto err;
5678                 err = create_rq(rwq, pd, init_attr);
5679                 if (err)
5680                         goto err_user_rq;
5681                 break;
5682         default:
5683                 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5684                             init_attr->wq_type);
5685                 return ERR_PTR(-EINVAL);
5686         }
5687
5688         rwq->ibwq.wq_num = rwq->core_qp.qpn;
5689         rwq->ibwq.state = IB_WQS_RESET;
5690         if (udata->outlen) {
5691                 resp.response_length = offsetof(typeof(resp), response_length) +
5692                                 sizeof(resp.response_length);
5693                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5694                 if (err)
5695                         goto err_copy;
5696         }
5697
5698         rwq->core_qp.event = mlx5_ib_wq_event;
5699         rwq->ibwq.event_handler = init_attr->event_handler;
5700         return &rwq->ibwq;
5701
5702 err_copy:
5703         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5704 err_user_rq:
5705         destroy_user_rq(dev, pd, rwq);
5706 err:
5707         kfree(rwq);
5708         return ERR_PTR(err);
5709 }
5710
5711 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5712 {
5713         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5714         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5715
5716         mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5717         destroy_user_rq(dev, wq->pd, rwq);
5718         kfree(rwq);
5719
5720         return 0;
5721 }
5722
5723 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5724                                                       struct ib_rwq_ind_table_init_attr *init_attr,
5725                                                       struct ib_udata *udata)
5726 {
5727         struct mlx5_ib_dev *dev = to_mdev(device);
5728         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5729         int sz = 1 << init_attr->log_ind_tbl_size;
5730         struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5731         size_t min_resp_len;
5732         int inlen;
5733         int err;
5734         int i;
5735         u32 *in;
5736         void *rqtc;
5737
5738         if (udata->inlen > 0 &&
5739             !ib_is_udata_cleared(udata, 0,
5740                                  udata->inlen))
5741                 return ERR_PTR(-EOPNOTSUPP);
5742
5743         if (init_attr->log_ind_tbl_size >
5744             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5745                 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5746                             init_attr->log_ind_tbl_size,
5747                             MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5748                 return ERR_PTR(-EINVAL);
5749         }
5750
5751         min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5752         if (udata->outlen && udata->outlen < min_resp_len)
5753                 return ERR_PTR(-EINVAL);
5754
5755         rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5756         if (!rwq_ind_tbl)
5757                 return ERR_PTR(-ENOMEM);
5758
5759         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5760         in = kvzalloc(inlen, GFP_KERNEL);
5761         if (!in) {
5762                 err = -ENOMEM;
5763                 goto err;
5764         }
5765
5766         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5767
5768         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5769         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5770
5771         for (i = 0; i < sz; i++)
5772                 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5773
5774         rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5775         MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5776
5777         err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5778         kvfree(in);
5779
5780         if (err)
5781                 goto err;
5782
5783         rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5784         if (udata->outlen) {
5785                 resp.response_length = offsetof(typeof(resp), response_length) +
5786                                         sizeof(resp.response_length);
5787                 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5788                 if (err)
5789                         goto err_copy;
5790         }
5791
5792         return &rwq_ind_tbl->ib_rwq_ind_tbl;
5793
5794 err_copy:
5795         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5796 err:
5797         kfree(rwq_ind_tbl);
5798         return ERR_PTR(err);
5799 }
5800
5801 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5802 {
5803         struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5804         struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5805
5806         mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5807
5808         kfree(rwq_ind_tbl);
5809         return 0;
5810 }
5811
5812 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5813                       u32 wq_attr_mask, struct ib_udata *udata)
5814 {
5815         struct mlx5_ib_dev *dev = to_mdev(wq->device);
5816         struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5817         struct mlx5_ib_modify_wq ucmd = {};
5818         size_t required_cmd_sz;
5819         int curr_wq_state;
5820         int wq_state;
5821         int inlen;
5822         int err;
5823         void *rqc;
5824         void *in;
5825
5826         required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5827         if (udata->inlen < required_cmd_sz)
5828                 return -EINVAL;
5829
5830         if (udata->inlen > sizeof(ucmd) &&
5831             !ib_is_udata_cleared(udata, sizeof(ucmd),
5832                                  udata->inlen - sizeof(ucmd)))
5833                 return -EOPNOTSUPP;
5834
5835         if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5836                 return -EFAULT;
5837
5838         if (ucmd.comp_mask || ucmd.reserved)
5839                 return -EOPNOTSUPP;
5840
5841         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5842         in = kvzalloc(inlen, GFP_KERNEL);
5843         if (!in)
5844                 return -ENOMEM;
5845
5846         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5847
5848         curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5849                 wq_attr->curr_wq_state : wq->state;
5850         wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5851                 wq_attr->wq_state : curr_wq_state;
5852         if (curr_wq_state == IB_WQS_ERR)
5853                 curr_wq_state = MLX5_RQC_STATE_ERR;
5854         if (wq_state == IB_WQS_ERR)
5855                 wq_state = MLX5_RQC_STATE_ERR;
5856         MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5857         MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
5858         MLX5_SET(rqc, rqc, state, wq_state);
5859
5860         if (wq_attr_mask & IB_WQ_FLAGS) {
5861                 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5862                         if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5863                               MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5864                                 mlx5_ib_dbg(dev, "VLAN offloads are not "
5865                                             "supported\n");
5866                                 err = -EOPNOTSUPP;
5867                                 goto out;
5868                         }
5869                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5870                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5871                         MLX5_SET(rqc, rqc, vsd,
5872                                  (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5873                 }
5874
5875                 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5876                         mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5877                         err = -EOPNOTSUPP;
5878                         goto out;
5879                 }
5880         }
5881
5882         if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5883                 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5884                         MLX5_SET64(modify_rq_in, in, modify_bitmask,
5885                                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5886                         MLX5_SET(rqc, rqc, counter_set_id,
5887                                  dev->port->cnts.set_id);
5888                 } else
5889                         dev_info_once(
5890                                 &dev->ib_dev.dev,
5891                                 "Receive WQ counters are not supported on current FW\n");
5892         }
5893
5894         err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5895         if (!err)
5896                 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5897
5898 out:
5899         kvfree(in);
5900         return err;
5901 }
5902
5903 struct mlx5_ib_drain_cqe {
5904         struct ib_cqe cqe;
5905         struct completion done;
5906 };
5907
5908 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
5909 {
5910         struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
5911                                                      struct mlx5_ib_drain_cqe,
5912                                                      cqe);
5913
5914         complete(&cqe->done);
5915 }
5916
5917 /* This function returns only once the drained WR was completed */
5918 static void handle_drain_completion(struct ib_cq *cq,
5919                                     struct mlx5_ib_drain_cqe *sdrain,
5920                                     struct mlx5_ib_dev *dev)
5921 {
5922         struct mlx5_core_dev *mdev = dev->mdev;
5923
5924         if (cq->poll_ctx == IB_POLL_DIRECT) {
5925                 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
5926                         ib_process_cq_direct(cq, -1);
5927                 return;
5928         }
5929
5930         if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5931                 struct mlx5_ib_cq *mcq = to_mcq(cq);
5932                 bool triggered = false;
5933                 unsigned long flags;
5934
5935                 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
5936                 /* Make sure that the CQ handler won't run if wasn't run yet */
5937                 if (!mcq->mcq.reset_notify_added)
5938                         mcq->mcq.reset_notify_added = 1;
5939                 else
5940                         triggered = true;
5941                 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
5942
5943                 if (triggered) {
5944                         /* Wait for any scheduled/running task to be ended */
5945                         switch (cq->poll_ctx) {
5946                         case IB_POLL_SOFTIRQ:
5947                                 irq_poll_disable(&cq->iop);
5948                                 irq_poll_enable(&cq->iop);
5949                                 break;
5950                         case IB_POLL_WORKQUEUE:
5951                                 cancel_work_sync(&cq->work);
5952                                 break;
5953                         default:
5954                                 WARN_ON_ONCE(1);
5955                         }
5956                 }
5957
5958                 /* Run the CQ handler - this makes sure that the drain WR will
5959                  * be processed if wasn't processed yet.
5960                  */
5961                 mcq->mcq.comp(&mcq->mcq);
5962         }
5963
5964         wait_for_completion(&sdrain->done);
5965 }
5966
5967 void mlx5_ib_drain_sq(struct ib_qp *qp)
5968 {
5969         struct ib_cq *cq = qp->send_cq;
5970         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
5971         struct mlx5_ib_drain_cqe sdrain;
5972         const struct ib_send_wr *bad_swr;
5973         struct ib_rdma_wr swr = {
5974                 .wr = {
5975                         .next = NULL,
5976                         { .wr_cqe       = &sdrain.cqe, },
5977                         .opcode = IB_WR_RDMA_WRITE,
5978                 },
5979         };
5980         int ret;
5981         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5982         struct mlx5_core_dev *mdev = dev->mdev;
5983
5984         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
5985         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
5986                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5987                 return;
5988         }
5989
5990         sdrain.cqe.done = mlx5_ib_drain_qp_done;
5991         init_completion(&sdrain.done);
5992
5993         ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
5994         if (ret) {
5995                 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
5996                 return;
5997         }
5998
5999         handle_drain_completion(cq, &sdrain, dev);
6000 }
6001
6002 void mlx5_ib_drain_rq(struct ib_qp *qp)
6003 {
6004         struct ib_cq *cq = qp->recv_cq;
6005         struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6006         struct mlx5_ib_drain_cqe rdrain;
6007         struct ib_recv_wr rwr = {};
6008         const struct ib_recv_wr *bad_rwr;
6009         int ret;
6010         struct mlx5_ib_dev *dev = to_mdev(qp->device);
6011         struct mlx5_core_dev *mdev = dev->mdev;
6012
6013         ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6014         if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6015                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6016                 return;
6017         }
6018
6019         rwr.wr_cqe = &rdrain.cqe;
6020         rdrain.cqe.done = mlx5_ib_drain_qp_done;
6021         init_completion(&rdrain.done);
6022
6023         ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6024         if (ret) {
6025                 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6026                 return;
6027         }
6028
6029         handle_drain_completion(cq, &rdrain, dev);
6030 }