2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
42 /* not supported currently */
43 static int wq_signature;
46 MLX5_IB_ACK_REQ_FREQ = 8,
50 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
51 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
52 MLX5_IB_LINK_TYPE_IB = 0,
53 MLX5_IB_LINK_TYPE_ETH = 1
57 MLX5_IB_SQ_STRIDE = 6,
58 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
61 static const u32 mlx5_ib_opcode[] = {
62 [IB_WR_SEND] = MLX5_OPCODE_SEND,
63 [IB_WR_LSO] = MLX5_OPCODE_LSO,
64 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
65 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
66 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
67 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
68 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
69 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
70 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
71 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
72 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
73 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
74 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
75 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
78 struct mlx5_wqe_eth_pad {
82 enum raw_qp_set_mask_map {
83 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
84 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
87 struct mlx5_modify_raw_qp_param {
90 u32 set_mask; /* raw_qp_set_mask_map */
92 struct mlx5_rate_limit rl;
97 static void get_cqs(enum ib_qp_type qp_type,
98 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
99 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
101 static int is_qp0(enum ib_qp_type qp_type)
103 return qp_type == IB_QPT_SMI;
106 static int is_sqp(enum ib_qp_type qp_type)
108 return is_qp0(qp_type) || is_qp1(qp_type);
112 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
114 * @qp: QP to copy from.
115 * @send: copy from the send queue when non-zero, use the receive queue
117 * @wqe_index: index to start copying from. For send work queues, the
118 * wqe_index is in units of MLX5_SEND_WQE_BB.
119 * For receive work queue, it is the number of work queue
120 * element in the queue.
121 * @buffer: destination buffer.
122 * @length: maximum number of bytes to copy.
124 * Copies at least a single WQE, but may copy more data.
126 * Return: the number of bytes copied, or an error code.
128 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
129 void *buffer, u32 length,
130 struct mlx5_ib_qp_base *base)
132 struct ib_device *ibdev = qp->ibqp.device;
133 struct mlx5_ib_dev *dev = to_mdev(ibdev);
134 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
137 struct ib_umem *umem = base->ubuffer.umem;
138 u32 first_copy_length;
142 if (wq->wqe_cnt == 0) {
143 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
148 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
149 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
151 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
154 if (offset > umem->length ||
155 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
158 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
159 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
164 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
165 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
167 wqe_length = ds * MLX5_WQE_DS_UNITS;
169 wqe_length = 1 << wq->wqe_shift;
172 if (wqe_length <= first_copy_length)
173 return first_copy_length;
175 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
176 wqe_length - first_copy_length);
183 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
185 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
186 struct ib_event event;
188 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
189 /* This event is only valid for trans_qps */
190 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
193 if (ibqp->event_handler) {
194 event.device = ibqp->device;
195 event.element.qp = ibqp;
197 case MLX5_EVENT_TYPE_PATH_MIG:
198 event.event = IB_EVENT_PATH_MIG;
200 case MLX5_EVENT_TYPE_COMM_EST:
201 event.event = IB_EVENT_COMM_EST;
203 case MLX5_EVENT_TYPE_SQ_DRAINED:
204 event.event = IB_EVENT_SQ_DRAINED;
206 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
207 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
209 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
210 event.event = IB_EVENT_QP_FATAL;
212 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
213 event.event = IB_EVENT_PATH_MIG_ERR;
215 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
216 event.event = IB_EVENT_QP_REQ_ERR;
218 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
219 event.event = IB_EVENT_QP_ACCESS_ERR;
222 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
226 ibqp->event_handler(&event, ibqp->qp_context);
230 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
231 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
236 /* Sanity check RQ size before proceeding */
237 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
243 qp->rq.wqe_shift = 0;
244 cap->max_recv_wr = 0;
245 cap->max_recv_sge = 0;
248 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
249 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
251 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
252 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
254 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
255 qp->rq.max_post = qp->rq.wqe_cnt;
257 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
258 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
259 wqe_size = roundup_pow_of_two(wqe_size);
260 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
261 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
262 qp->rq.wqe_cnt = wq_size / wqe_size;
263 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
264 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
266 MLX5_CAP_GEN(dev->mdev,
270 qp->rq.wqe_shift = ilog2(wqe_size);
271 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
272 qp->rq.max_post = qp->rq.wqe_cnt;
279 static int sq_overhead(struct ib_qp_init_attr *attr)
283 switch (attr->qp_type) {
285 size += sizeof(struct mlx5_wqe_xrc_seg);
288 size += sizeof(struct mlx5_wqe_ctrl_seg) +
289 max(sizeof(struct mlx5_wqe_atomic_seg) +
290 sizeof(struct mlx5_wqe_raddr_seg),
291 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
292 sizeof(struct mlx5_mkey_seg) +
293 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
294 MLX5_IB_UMR_OCTOWORD);
301 size += sizeof(struct mlx5_wqe_ctrl_seg) +
302 max(sizeof(struct mlx5_wqe_raddr_seg),
303 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
304 sizeof(struct mlx5_mkey_seg));
308 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
309 size += sizeof(struct mlx5_wqe_eth_pad) +
310 sizeof(struct mlx5_wqe_eth_seg);
313 case MLX5_IB_QPT_HW_GSI:
314 size += sizeof(struct mlx5_wqe_ctrl_seg) +
315 sizeof(struct mlx5_wqe_datagram_seg);
318 case MLX5_IB_QPT_REG_UMR:
319 size += sizeof(struct mlx5_wqe_ctrl_seg) +
320 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
321 sizeof(struct mlx5_mkey_seg);
331 static int calc_send_wqe(struct ib_qp_init_attr *attr)
336 size = sq_overhead(attr);
340 if (attr->cap.max_inline_data) {
341 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
342 attr->cap.max_inline_data;
345 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
346 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
347 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
348 return MLX5_SIG_WQE_SIZE;
350 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
353 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
357 if (attr->qp_type == IB_QPT_RC)
358 max_sge = (min_t(int, wqe_size, 512) -
359 sizeof(struct mlx5_wqe_ctrl_seg) -
360 sizeof(struct mlx5_wqe_raddr_seg)) /
361 sizeof(struct mlx5_wqe_data_seg);
362 else if (attr->qp_type == IB_QPT_XRC_INI)
363 max_sge = (min_t(int, wqe_size, 512) -
364 sizeof(struct mlx5_wqe_ctrl_seg) -
365 sizeof(struct mlx5_wqe_xrc_seg) -
366 sizeof(struct mlx5_wqe_raddr_seg)) /
367 sizeof(struct mlx5_wqe_data_seg);
369 max_sge = (wqe_size - sq_overhead(attr)) /
370 sizeof(struct mlx5_wqe_data_seg);
372 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
373 sizeof(struct mlx5_wqe_data_seg));
376 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
377 struct mlx5_ib_qp *qp)
382 if (!attr->cap.max_send_wr)
385 wqe_size = calc_send_wqe(attr);
386 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
390 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
391 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
392 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
396 qp->max_inline_data = wqe_size - sq_overhead(attr) -
397 sizeof(struct mlx5_wqe_inline_seg);
398 attr->cap.max_inline_data = qp->max_inline_data;
400 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
401 qp->signature_en = true;
403 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
404 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
405 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
406 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
407 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
409 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
412 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
413 qp->sq.max_gs = get_send_sge(attr, wqe_size);
414 if (qp->sq.max_gs < attr->cap.max_send_sge)
417 attr->cap.max_send_sge = qp->sq.max_gs;
418 qp->sq.max_post = wq_size / wqe_size;
419 attr->cap.max_send_wr = qp->sq.max_post;
424 static int set_user_buf_size(struct mlx5_ib_dev *dev,
425 struct mlx5_ib_qp *qp,
426 struct mlx5_ib_create_qp *ucmd,
427 struct mlx5_ib_qp_base *base,
428 struct ib_qp_init_attr *attr)
430 int desc_sz = 1 << qp->sq.wqe_shift;
432 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
433 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
434 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
438 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
439 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
440 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
444 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
446 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
447 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
449 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
453 if (attr->qp_type == IB_QPT_RAW_PACKET ||
454 qp->flags & MLX5_IB_QP_UNDERLAY) {
455 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
456 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
458 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
459 (qp->sq.wqe_cnt << 6);
465 static int qp_has_rq(struct ib_qp_init_attr *attr)
467 if (attr->qp_type == IB_QPT_XRC_INI ||
468 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
469 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
470 !attr->cap.max_recv_wr)
477 /* this is the first blue flame register in the array of bfregs assigned
478 * to a processes. Since we do not use it for blue flame but rather
479 * regular 64 bit doorbells, we do not need a lock for maintaiing
482 NUM_NON_BLUE_FLAME_BFREGS = 1,
485 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
487 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
490 static int num_med_bfreg(struct mlx5_ib_dev *dev,
491 struct mlx5_bfreg_info *bfregi)
495 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
496 NUM_NON_BLUE_FLAME_BFREGS;
498 return n >= 0 ? n : 0;
501 static int first_med_bfreg(struct mlx5_ib_dev *dev,
502 struct mlx5_bfreg_info *bfregi)
504 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
507 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
508 struct mlx5_bfreg_info *bfregi)
512 med = num_med_bfreg(dev, bfregi);
516 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
517 struct mlx5_bfreg_info *bfregi)
521 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
522 if (!bfregi->count[i]) {
531 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
532 struct mlx5_bfreg_info *bfregi)
534 int minidx = first_med_bfreg(dev, bfregi);
540 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
541 if (bfregi->count[i] < bfregi->count[minidx])
543 if (!bfregi->count[minidx])
547 bfregi->count[minidx]++;
551 static int alloc_bfreg(struct mlx5_ib_dev *dev,
552 struct mlx5_bfreg_info *bfregi)
554 int bfregn = -ENOMEM;
556 mutex_lock(&bfregi->lock);
557 if (bfregi->ver >= 2) {
558 bfregn = alloc_high_class_bfreg(dev, bfregi);
560 bfregn = alloc_med_class_bfreg(dev, bfregi);
564 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
566 bfregi->count[bfregn]++;
568 mutex_unlock(&bfregi->lock);
573 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
575 mutex_lock(&bfregi->lock);
576 bfregi->count[bfregn]--;
577 mutex_unlock(&bfregi->lock);
580 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
583 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
584 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
585 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
586 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
587 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
588 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
589 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
594 static int to_mlx5_st(enum ib_qp_type type)
597 case IB_QPT_RC: return MLX5_QP_ST_RC;
598 case IB_QPT_UC: return MLX5_QP_ST_UC;
599 case IB_QPT_UD: return MLX5_QP_ST_UD;
600 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
602 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
603 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
604 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
605 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
606 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
607 case IB_QPT_RAW_PACKET:
608 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
610 default: return -EINVAL;
614 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
615 struct mlx5_ib_cq *recv_cq);
616 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
617 struct mlx5_ib_cq *recv_cq);
619 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
620 struct mlx5_bfreg_info *bfregi, u32 bfregn,
623 unsigned int bfregs_per_sys_page;
624 u32 index_of_sys_page;
627 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
628 MLX5_NON_FP_BFREGS_PER_UAR;
629 index_of_sys_page = bfregn / bfregs_per_sys_page;
632 index_of_sys_page += bfregi->num_static_sys_pages;
634 if (index_of_sys_page >= bfregi->num_sys_pages)
637 if (bfregn > bfregi->num_dyn_bfregs ||
638 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
639 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
644 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
645 return bfregi->sys_pages[index_of_sys_page] + offset;
648 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
650 unsigned long addr, size_t size,
651 struct ib_umem **umem,
652 int *npages, int *page_shift, int *ncont,
657 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
659 mlx5_ib_dbg(dev, "umem_get failed\n");
660 return PTR_ERR(*umem);
663 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
665 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
667 mlx5_ib_warn(dev, "bad offset\n");
671 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
672 addr, size, *npages, *page_shift, *ncont, *offset);
677 ib_umem_release(*umem);
683 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
684 struct mlx5_ib_rwq *rwq)
686 struct mlx5_ib_ucontext *context;
688 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
689 atomic_dec(&dev->delay_drop.rqs_cnt);
691 context = to_mucontext(pd->uobject->context);
692 mlx5_ib_db_unmap_user(context, &rwq->db);
694 ib_umem_release(rwq->umem);
697 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
698 struct mlx5_ib_rwq *rwq,
699 struct mlx5_ib_create_wq *ucmd)
701 struct mlx5_ib_ucontext *context;
711 context = to_mucontext(pd->uobject->context);
712 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
713 rwq->buf_size, 0, 0);
714 if (IS_ERR(rwq->umem)) {
715 mlx5_ib_dbg(dev, "umem_get failed\n");
716 err = PTR_ERR(rwq->umem);
720 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
722 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
723 &rwq->rq_page_offset);
725 mlx5_ib_warn(dev, "bad offset\n");
729 rwq->rq_num_pas = ncont;
730 rwq->page_shift = page_shift;
731 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
732 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
734 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
735 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
736 npages, page_shift, ncont, offset);
738 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
740 mlx5_ib_dbg(dev, "map failed\n");
744 rwq->create_type = MLX5_WQ_USER;
748 ib_umem_release(rwq->umem);
752 static int adjust_bfregn(struct mlx5_ib_dev *dev,
753 struct mlx5_bfreg_info *bfregi, int bfregn)
755 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
756 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
759 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
760 struct mlx5_ib_qp *qp, struct ib_udata *udata,
761 struct ib_qp_init_attr *attr,
763 struct mlx5_ib_create_qp_resp *resp, int *inlen,
764 struct mlx5_ib_qp_base *base)
766 struct mlx5_ib_ucontext *context;
767 struct mlx5_ib_create_qp ucmd;
768 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
780 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
782 mlx5_ib_dbg(dev, "copy failed\n");
786 context = to_mucontext(pd->uobject->context);
787 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
788 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
789 ucmd.bfreg_index, true);
793 bfregn = MLX5_IB_INVALID_BFREG;
794 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
796 * TBD: should come from the verbs when we have the API
798 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
799 bfregn = MLX5_CROSS_CHANNEL_BFREG;
802 bfregn = alloc_bfreg(dev, &context->bfregi);
807 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
808 if (bfregn != MLX5_IB_INVALID_BFREG)
809 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
813 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
814 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
816 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
820 if (ucmd.buf_addr && ubuffer->buf_size) {
821 ubuffer->buf_addr = ucmd.buf_addr;
822 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
824 &ubuffer->umem, &npages, &page_shift,
829 ubuffer->umem = NULL;
832 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
833 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
834 *in = kvzalloc(*inlen, GFP_KERNEL);
840 uid = (attr->qp_type != IB_QPT_XRC_TGT) ? to_mpd(pd)->uid : 0;
841 MLX5_SET(create_qp_in, *in, uid, uid);
842 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
844 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
846 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
848 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
849 MLX5_SET(qpc, qpc, page_offset, offset);
851 MLX5_SET(qpc, qpc, uar_page, uar_index);
852 if (bfregn != MLX5_IB_INVALID_BFREG)
853 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
855 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
858 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
860 mlx5_ib_dbg(dev, "map failed\n");
864 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
866 mlx5_ib_dbg(dev, "copy failed\n");
869 qp->create_type = MLX5_QP_USER;
874 mlx5_ib_db_unmap_user(context, &qp->db);
881 ib_umem_release(ubuffer->umem);
884 if (bfregn != MLX5_IB_INVALID_BFREG)
885 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
889 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
890 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
892 struct mlx5_ib_ucontext *context;
894 context = to_mucontext(pd->uobject->context);
895 mlx5_ib_db_unmap_user(context, &qp->db);
896 if (base->ubuffer.umem)
897 ib_umem_release(base->ubuffer.umem);
900 * Free only the BFREGs which are handled by the kernel.
901 * BFREGs of UARs allocated dynamically are handled by user.
903 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
904 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
907 /* get_sq_edge - Get the next nearby edge.
909 * An 'edge' is defined as the first following address after the end
910 * of the fragment or the SQ. Accordingly, during the WQE construction
911 * which repetitively increases the pointer to write the next data, it
912 * simply should check if it gets to an edge.
915 * @idx - Stride index in the SQ buffer.
920 static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
924 fragment_end = mlx5_frag_buf_get_wqe
926 mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
928 return fragment_end + MLX5_SEND_WQE_BB;
931 static int create_kernel_qp(struct mlx5_ib_dev *dev,
932 struct ib_qp_init_attr *init_attr,
933 struct mlx5_ib_qp *qp,
934 u32 **in, int *inlen,
935 struct mlx5_ib_qp_base *base)
941 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
942 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
943 IB_QP_CREATE_IPOIB_UD_LSO |
944 IB_QP_CREATE_NETIF_QP |
945 mlx5_ib_create_qp_sqpn_qp1()))
948 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
949 qp->bf.bfreg = &dev->fp_bfreg;
951 qp->bf.bfreg = &dev->bfreg;
953 /* We need to divide by two since each register is comprised of
954 * two buffers of identical size, namely odd and even
956 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
957 uar_index = qp->bf.bfreg->index;
959 err = calc_sq_size(dev, init_attr, qp);
961 mlx5_ib_dbg(dev, "err %d\n", err);
966 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
967 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
969 err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size,
970 &qp->buf, dev->mdev->priv.numa_node);
972 mlx5_ib_dbg(dev, "err %d\n", err);
977 mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift,
978 ilog2(qp->rq.wqe_cnt), &qp->rq.fbc);
980 if (qp->sq.wqe_cnt) {
981 int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) /
983 mlx5_init_fbc_offset(qp->buf.frags +
984 (qp->sq.offset / PAGE_SIZE),
985 ilog2(MLX5_SEND_WQE_BB),
986 ilog2(qp->sq.wqe_cnt),
987 sq_strides_offset, &qp->sq.fbc);
989 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
992 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
993 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
994 *in = kvzalloc(*inlen, GFP_KERNEL);
1000 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
1001 MLX5_SET(qpc, qpc, uar_page, uar_index);
1002 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1004 /* Set "fast registration enabled" for all kernel QPs */
1005 MLX5_SET(qpc, qpc, fre, 1);
1006 MLX5_SET(qpc, qpc, rlky, 1);
1008 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
1009 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1010 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1013 mlx5_fill_page_frag_array(&qp->buf,
1014 (__be64 *)MLX5_ADDR_OF(create_qp_in,
1017 err = mlx5_db_alloc(dev->mdev, &qp->db);
1019 mlx5_ib_dbg(dev, "err %d\n", err);
1023 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1024 sizeof(*qp->sq.wrid), GFP_KERNEL);
1025 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1026 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1027 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1028 sizeof(*qp->rq.wrid), GFP_KERNEL);
1029 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1030 sizeof(*qp->sq.w_list), GFP_KERNEL);
1031 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1032 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1034 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1035 !qp->sq.w_list || !qp->sq.wqe_head) {
1039 qp->create_type = MLX5_QP_KERNEL;
1044 kvfree(qp->sq.wqe_head);
1045 kvfree(qp->sq.w_list);
1046 kvfree(qp->sq.wrid);
1047 kvfree(qp->sq.wr_data);
1048 kvfree(qp->rq.wrid);
1049 mlx5_db_free(dev->mdev, &qp->db);
1055 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1059 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1061 kvfree(qp->sq.wqe_head);
1062 kvfree(qp->sq.w_list);
1063 kvfree(qp->sq.wrid);
1064 kvfree(qp->sq.wr_data);
1065 kvfree(qp->rq.wrid);
1066 mlx5_db_free(dev->mdev, &qp->db);
1067 mlx5_frag_buf_free(dev->mdev, &qp->buf);
1070 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1072 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1073 (attr->qp_type == MLX5_IB_QPT_DCI) ||
1074 (attr->qp_type == IB_QPT_XRC_INI))
1076 else if (!qp->has_rq)
1077 return MLX5_ZERO_LEN_RQ;
1079 return MLX5_NON_ZERO_RQ;
1082 static int is_connected(enum ib_qp_type qp_type)
1084 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC ||
1085 qp_type == MLX5_IB_QPT_DCI)
1091 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1092 struct mlx5_ib_qp *qp,
1093 struct mlx5_ib_sq *sq, u32 tdn,
1096 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1097 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1099 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1100 MLX5_SET(tisc, tisc, transport_domain, tdn);
1101 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1102 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1104 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1107 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1108 struct mlx5_ib_sq *sq, struct ib_pd *pd)
1110 mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1113 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1114 struct mlx5_ib_sq *sq)
1117 mlx5_del_flow_rules(sq->flow_rule);
1120 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1121 struct mlx5_ib_sq *sq, void *qpin,
1124 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1128 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1137 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1138 &sq->ubuffer.umem, &npages, &page_shift,
1143 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1144 in = kvzalloc(inlen, GFP_KERNEL);
1150 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1151 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1152 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1153 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1154 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1155 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1156 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1157 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1158 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1159 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1160 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1161 MLX5_CAP_ETH(dev->mdev, swp))
1162 MLX5_SET(sqc, sqc, allow_swp, 1);
1164 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1165 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1166 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1167 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1168 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1169 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1170 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1171 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1172 MLX5_SET(wq, wq, page_offset, offset);
1174 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1175 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1177 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1184 err = create_flow_rule_vport_sq(dev, sq);
1191 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1194 ib_umem_release(sq->ubuffer.umem);
1195 sq->ubuffer.umem = NULL;
1200 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1201 struct mlx5_ib_sq *sq)
1203 destroy_flow_rule_vport_sq(dev, sq);
1204 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1205 ib_umem_release(sq->ubuffer.umem);
1208 static size_t get_rq_pas_size(void *qpc)
1210 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1211 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1212 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1213 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1214 u32 po_quanta = 1 << (log_page_size - 6);
1215 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1216 u32 page_size = 1 << log_page_size;
1217 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1218 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1220 return rq_num_pas * sizeof(u64);
1223 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1224 struct mlx5_ib_rq *rq, void *qpin,
1225 size_t qpinlen, struct ib_pd *pd)
1227 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1233 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1234 size_t rq_pas_size = get_rq_pas_size(qpc);
1238 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1241 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1242 in = kvzalloc(inlen, GFP_KERNEL);
1246 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1247 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1248 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1249 MLX5_SET(rqc, rqc, vsd, 1);
1250 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1251 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1252 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1253 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1254 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1256 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1257 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1259 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1260 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1261 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1262 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1263 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1264 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1265 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1266 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1267 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1268 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1270 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1271 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1272 memcpy(pas, qp_pas, rq_pas_size);
1274 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1281 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1282 struct mlx5_ib_rq *rq)
1284 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1287 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1289 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1290 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1291 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1294 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1295 struct mlx5_ib_rq *rq,
1299 if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1300 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1301 mlx5_ib_disable_lb(dev, false, true);
1302 mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1305 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1306 struct mlx5_ib_rq *rq, u32 tdn,
1316 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1317 in = kvzalloc(inlen, GFP_KERNEL);
1321 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1322 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1323 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1324 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1325 MLX5_SET(tirc, tirc, transport_domain, tdn);
1326 if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1327 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1329 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC)
1330 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1332 if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)
1333 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1336 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1337 *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1340 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1342 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1344 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1345 err = mlx5_ib_enable_lb(dev, false, true);
1348 destroy_raw_packet_qp_tir(dev, rq, 0, pd);
1355 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1356 u32 *in, size_t inlen,
1358 struct ib_udata *udata,
1359 struct mlx5_ib_create_qp_resp *resp)
1361 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1362 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1363 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1364 struct ib_uobject *uobj = pd->uobject;
1365 struct ib_ucontext *ucontext = uobj->context;
1366 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1368 u32 tdn = mucontext->tdn;
1369 u16 uid = to_mpd(pd)->uid;
1371 if (qp->sq.wqe_cnt) {
1372 err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd);
1376 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1378 goto err_destroy_tis;
1381 resp->tisn = sq->tisn;
1382 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN;
1383 resp->sqn = sq->base.mqp.qpn;
1384 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN;
1387 sq->base.container_mibqp = qp;
1388 sq->base.mqp.event = mlx5_ib_qp_event;
1391 if (qp->rq.wqe_cnt) {
1392 rq->base.container_mibqp = qp;
1394 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1395 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1396 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1397 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1398 err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd);
1400 goto err_destroy_sq;
1402 err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd);
1404 goto err_destroy_rq;
1407 resp->rqn = rq->base.mqp.qpn;
1408 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
1409 resp->tirn = rq->tirn;
1410 resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1414 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1416 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
1418 goto err_destroy_tir;
1423 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd);
1425 destroy_raw_packet_qp_rq(dev, rq);
1427 if (!qp->sq.wqe_cnt)
1429 destroy_raw_packet_qp_sq(dev, sq);
1431 destroy_raw_packet_qp_tis(dev, sq, pd);
1436 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1437 struct mlx5_ib_qp *qp)
1439 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1440 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1441 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1443 if (qp->rq.wqe_cnt) {
1444 destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd);
1445 destroy_raw_packet_qp_rq(dev, rq);
1448 if (qp->sq.wqe_cnt) {
1449 destroy_raw_packet_qp_sq(dev, sq);
1450 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1454 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1455 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1457 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1458 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1462 sq->doorbell = &qp->db;
1463 rq->doorbell = &qp->db;
1466 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1468 if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1469 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC))
1470 mlx5_ib_disable_lb(dev, false, true);
1471 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1472 to_mpd(qp->ibqp.pd)->uid);
1475 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1477 struct ib_qp_init_attr *init_attr,
1478 struct ib_udata *udata)
1480 struct ib_uobject *uobj = pd->uobject;
1481 struct ib_ucontext *ucontext = uobj->context;
1482 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1483 struct mlx5_ib_create_qp_resp resp = {};
1489 u32 selected_fields = 0;
1491 size_t min_resp_len;
1492 u32 tdn = mucontext->tdn;
1493 struct mlx5_ib_create_qp_rss ucmd = {};
1494 size_t required_cmd_sz;
1497 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1500 if (init_attr->create_flags || init_attr->send_cq)
1503 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1504 if (udata->outlen < min_resp_len)
1507 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1508 if (udata->inlen < required_cmd_sz) {
1509 mlx5_ib_dbg(dev, "invalid inlen\n");
1513 if (udata->inlen > sizeof(ucmd) &&
1514 !ib_is_udata_cleared(udata, sizeof(ucmd),
1515 udata->inlen - sizeof(ucmd))) {
1516 mlx5_ib_dbg(dev, "inlen is not supported\n");
1520 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1521 mlx5_ib_dbg(dev, "copy failed\n");
1525 if (ucmd.comp_mask) {
1526 mlx5_ib_dbg(dev, "invalid comp mask\n");
1530 if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1531 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC |
1532 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) {
1533 mlx5_ib_dbg(dev, "invalid flags\n");
1537 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1538 !tunnel_offload_supported(dev->mdev)) {
1539 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1543 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1544 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1545 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1549 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) {
1550 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
1551 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1554 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1555 lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
1556 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1559 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1561 mlx5_ib_dbg(dev, "copy failed\n");
1565 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1566 in = kvzalloc(inlen, GFP_KERNEL);
1570 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1571 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1572 MLX5_SET(tirc, tirc, disp_type,
1573 MLX5_TIRC_DISP_TYPE_INDIRECT);
1574 MLX5_SET(tirc, tirc, indirect_table,
1575 init_attr->rwq_ind_tbl->ind_tbl_num);
1576 MLX5_SET(tirc, tirc, transport_domain, tdn);
1578 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1580 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1581 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1583 MLX5_SET(tirc, tirc, self_lb_block, lb_flag);
1585 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1586 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1588 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1590 switch (ucmd.rx_hash_function) {
1591 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1593 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1594 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1596 if (len != ucmd.rx_key_len) {
1601 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1602 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1603 memcpy(rss_key, ucmd.rx_hash_key, len);
1611 if (!ucmd.rx_hash_fields_mask) {
1612 /* special case when this TIR serves as steering entry without hashing */
1613 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1619 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1620 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1621 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1622 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1627 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1628 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1629 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1630 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1631 MLX5_L3_PROT_TYPE_IPV4);
1632 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1633 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1634 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1635 MLX5_L3_PROT_TYPE_IPV6);
1637 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1638 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1639 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1640 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1641 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1643 /* Check that only one l4 protocol is set */
1644 if (outer_l4 & (outer_l4 - 1)) {
1649 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1650 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1651 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1652 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1653 MLX5_L4_PROT_TYPE_TCP);
1654 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1655 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1656 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1657 MLX5_L4_PROT_TYPE_UDP);
1659 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1660 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1661 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1663 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1664 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1665 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1667 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1668 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1669 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1671 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1672 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1673 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1675 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1676 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1678 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1681 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1683 if (!err && MLX5_GET(tirc, tirc, self_lb_block)) {
1684 err = mlx5_ib_enable_lb(dev, false, true);
1687 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1694 if (mucontext->devx_uid) {
1695 resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
1696 resp.tirn = qp->rss_qp.tirn;
1699 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1704 /* qpn is reserved for that QP */
1705 qp->trans_qp.base.mqp.qpn = 0;
1706 qp->flags |= MLX5_IB_QP_RSS;
1710 mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid);
1716 static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr,
1721 if (init_attr->qp_type == MLX5_IB_QPT_DCI)
1724 rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq);
1726 if (rcqe_sz == 128) {
1727 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1731 if (init_attr->qp_type != MLX5_IB_QPT_DCT)
1732 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1735 static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev,
1736 struct ib_qp_init_attr *init_attr,
1737 struct mlx5_ib_create_qp *ucmd,
1740 enum ib_qp_type qpt = init_attr->qp_type;
1742 bool allow_scat_cqe = 0;
1744 if (qpt == IB_QPT_UC || qpt == IB_QPT_UD)
1748 allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE;
1750 if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR)
1753 scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq);
1754 if (scqe_sz == 128) {
1755 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1759 if (init_attr->qp_type != MLX5_IB_QPT_DCI ||
1760 MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe))
1761 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1764 static int atomic_size_to_mode(int size_mask)
1766 /* driver does not support atomic_size > 256B
1767 * and does not know how to translate bigger sizes
1769 int supported_size_mask = size_mask & 0x1ff;
1772 if (!supported_size_mask)
1775 log_max_size = __fls(supported_size_mask);
1777 if (log_max_size > 3)
1778 return log_max_size;
1780 return MLX5_ATOMIC_MODE_8B;
1783 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1784 enum ib_qp_type qp_type)
1786 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1787 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1788 int atomic_mode = -EOPNOTSUPP;
1789 int atomic_size_mask;
1794 if (qp_type == MLX5_IB_QPT_DCT)
1795 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1797 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1799 if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) ||
1800 (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD))
1801 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1803 if (atomic_mode <= 0 &&
1804 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1805 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1806 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1811 static inline bool check_flags_mask(uint64_t input, uint64_t supported)
1813 return (input & ~supported) == 0;
1816 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1817 struct ib_qp_init_attr *init_attr,
1818 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1820 struct mlx5_ib_resources *devr = &dev->devr;
1821 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1822 struct mlx5_core_dev *mdev = dev->mdev;
1823 struct mlx5_ib_create_qp_resp resp = {};
1824 struct mlx5_ib_cq *send_cq;
1825 struct mlx5_ib_cq *recv_cq;
1826 unsigned long flags;
1827 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1828 struct mlx5_ib_create_qp ucmd;
1829 struct mlx5_ib_qp_base *base;
1835 mutex_init(&qp->mutex);
1836 spin_lock_init(&qp->sq.lock);
1837 spin_lock_init(&qp->rq.lock);
1839 mlx5_st = to_mlx5_st(init_attr->qp_type);
1843 if (init_attr->rwq_ind_tbl) {
1847 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1851 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1852 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1853 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1856 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1860 if (init_attr->create_flags &
1861 (IB_QP_CREATE_CROSS_CHANNEL |
1862 IB_QP_CREATE_MANAGED_SEND |
1863 IB_QP_CREATE_MANAGED_RECV)) {
1864 if (!MLX5_CAP_GEN(mdev, cd)) {
1865 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1868 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1869 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1870 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1871 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1872 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1873 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1876 if (init_attr->qp_type == IB_QPT_UD &&
1877 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1878 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1879 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1883 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1884 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1885 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1888 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1889 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1890 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1893 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1896 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1897 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1899 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1900 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1901 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1902 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1904 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1907 if (pd && pd->uobject) {
1908 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1909 mlx5_ib_dbg(dev, "copy failed\n");
1913 if (!check_flags_mask(ucmd.flags,
1914 MLX5_QP_FLAG_SIGNATURE |
1915 MLX5_QP_FLAG_SCATTER_CQE |
1916 MLX5_QP_FLAG_TUNNEL_OFFLOADS |
1917 MLX5_QP_FLAG_BFREG_INDEX |
1918 MLX5_QP_FLAG_TYPE_DCT |
1919 MLX5_QP_FLAG_TYPE_DCI |
1920 MLX5_QP_FLAG_ALLOW_SCATTER_CQE |
1921 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE))
1924 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1925 &ucmd, udata->inlen, &uidx);
1929 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1930 if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe))
1931 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1932 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1933 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1934 !tunnel_offload_supported(mdev)) {
1935 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1938 qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS;
1941 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) {
1942 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1943 mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n");
1946 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC;
1949 if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) {
1950 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1951 mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n");
1954 qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC;
1957 if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) {
1958 if (init_attr->qp_type != IB_QPT_RC ||
1959 !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) {
1960 mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n");
1963 qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT;
1966 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1967 if (init_attr->qp_type != IB_QPT_UD ||
1968 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1969 MLX5_CAP_PORT_TYPE_IB) ||
1970 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1971 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1975 qp->flags |= MLX5_IB_QP_UNDERLAY;
1976 qp->underlay_qpn = init_attr->source_qpn;
1979 qp->wq_sig = !!wq_signature;
1982 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1983 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1984 &qp->raw_packet_qp.rq.base :
1987 qp->has_rq = qp_has_rq(init_attr);
1988 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1989 qp, (pd && pd->uobject) ? &ucmd : NULL);
1991 mlx5_ib_dbg(dev, "err %d\n", err);
1998 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1999 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
2000 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
2001 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
2002 mlx5_ib_dbg(dev, "invalid rq params\n");
2005 if (ucmd.sq_wqe_count > max_wqes) {
2006 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
2007 ucmd.sq_wqe_count, max_wqes);
2010 if (init_attr->create_flags &
2011 mlx5_ib_create_qp_sqpn_qp1()) {
2012 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
2015 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
2016 &resp, &inlen, base);
2018 mlx5_ib_dbg(dev, "err %d\n", err);
2020 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
2023 mlx5_ib_dbg(dev, "err %d\n", err);
2029 in = kvzalloc(inlen, GFP_KERNEL);
2033 qp->create_type = MLX5_QP_EMPTY;
2036 if (is_sqp(init_attr->qp_type))
2037 qp->port = init_attr->port_num;
2039 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2041 MLX5_SET(qpc, qpc, st, mlx5_st);
2042 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2044 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
2045 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
2047 MLX5_SET(qpc, qpc, latency_sensitive, 1);
2051 MLX5_SET(qpc, qpc, wq_signature, 1);
2053 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2054 MLX5_SET(qpc, qpc, block_lb_mc, 1);
2056 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
2057 MLX5_SET(qpc, qpc, cd_master, 1);
2058 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
2059 MLX5_SET(qpc, qpc, cd_slave_send, 1);
2060 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
2061 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
2062 if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT)
2063 MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1);
2064 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
2065 configure_responder_scat_cqe(init_attr, qpc);
2066 configure_requester_scat_cqe(dev, init_attr,
2067 (pd && pd->uobject) ? &ucmd : NULL,
2071 if (qp->rq.wqe_cnt) {
2072 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
2073 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
2076 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
2078 if (qp->sq.wqe_cnt) {
2079 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
2081 MLX5_SET(qpc, qpc, no_sq, 1);
2082 if (init_attr->srq &&
2083 init_attr->srq->srq_type == IB_SRQT_TM)
2084 MLX5_SET(qpc, qpc, offload_type,
2085 MLX5_QPC_OFFLOAD_TYPE_RNDV);
2088 /* Set default resources */
2089 switch (init_attr->qp_type) {
2090 case IB_QPT_XRC_TGT:
2091 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2092 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
2093 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2094 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
2096 case IB_QPT_XRC_INI:
2097 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
2098 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2099 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
2102 if (init_attr->srq) {
2103 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
2104 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
2106 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
2107 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
2111 if (init_attr->send_cq)
2112 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
2114 if (init_attr->recv_cq)
2115 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
2117 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
2119 /* 0xffffff means we ask to work with cqe version 0 */
2120 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
2121 MLX5_SET(qpc, qpc, user_index, uidx);
2123 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
2124 if (init_attr->qp_type == IB_QPT_UD &&
2125 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
2126 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
2127 qp->flags |= MLX5_IB_QP_LSO;
2130 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
2131 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
2132 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
2135 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
2136 MLX5_SET(qpc, qpc, end_padding_mode,
2137 MLX5_WQ_END_PAD_MODE_ALIGN);
2139 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
2148 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
2149 qp->flags & MLX5_IB_QP_UNDERLAY) {
2150 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
2151 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
2152 err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata,
2155 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
2159 mlx5_ib_dbg(dev, "create qp failed\n");
2165 base->container_mibqp = qp;
2166 base->mqp.event = mlx5_ib_qp_event;
2168 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
2169 &send_cq, &recv_cq);
2170 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2171 mlx5_ib_lock_cqs(send_cq, recv_cq);
2172 /* Maintain device to QPs access, needed for further handling via reset
2175 list_add_tail(&qp->qps_list, &dev->qp_list);
2176 /* Maintain CQ to QPs access, needed for further handling via reset flow
2179 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
2181 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
2182 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2183 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2188 if (qp->create_type == MLX5_QP_USER)
2189 destroy_qp_user(dev, pd, qp, base);
2190 else if (qp->create_type == MLX5_QP_KERNEL)
2191 destroy_qp_kernel(dev, qp);
2198 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2199 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
2203 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2204 spin_lock(&send_cq->lock);
2205 spin_lock_nested(&recv_cq->lock,
2206 SINGLE_DEPTH_NESTING);
2207 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2208 spin_lock(&send_cq->lock);
2209 __acquire(&recv_cq->lock);
2211 spin_lock(&recv_cq->lock);
2212 spin_lock_nested(&send_cq->lock,
2213 SINGLE_DEPTH_NESTING);
2216 spin_lock(&send_cq->lock);
2217 __acquire(&recv_cq->lock);
2219 } else if (recv_cq) {
2220 spin_lock(&recv_cq->lock);
2221 __acquire(&send_cq->lock);
2223 __acquire(&send_cq->lock);
2224 __acquire(&recv_cq->lock);
2228 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2229 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2233 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2234 spin_unlock(&recv_cq->lock);
2235 spin_unlock(&send_cq->lock);
2236 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2237 __release(&recv_cq->lock);
2238 spin_unlock(&send_cq->lock);
2240 spin_unlock(&send_cq->lock);
2241 spin_unlock(&recv_cq->lock);
2244 __release(&recv_cq->lock);
2245 spin_unlock(&send_cq->lock);
2247 } else if (recv_cq) {
2248 __release(&send_cq->lock);
2249 spin_unlock(&recv_cq->lock);
2251 __release(&recv_cq->lock);
2252 __release(&send_cq->lock);
2256 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2258 return to_mpd(qp->ibqp.pd);
2261 static void get_cqs(enum ib_qp_type qp_type,
2262 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2263 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2266 case IB_QPT_XRC_TGT:
2270 case MLX5_IB_QPT_REG_UMR:
2271 case IB_QPT_XRC_INI:
2272 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2277 case MLX5_IB_QPT_HW_GSI:
2281 case IB_QPT_RAW_IPV6:
2282 case IB_QPT_RAW_ETHERTYPE:
2283 case IB_QPT_RAW_PACKET:
2284 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2285 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2296 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2297 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2298 u8 lag_tx_affinity);
2300 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2302 struct mlx5_ib_cq *send_cq, *recv_cq;
2303 struct mlx5_ib_qp_base *base;
2304 unsigned long flags;
2307 if (qp->ibqp.rwq_ind_tbl) {
2308 destroy_rss_raw_qp_tir(dev, qp);
2312 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2313 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2314 &qp->raw_packet_qp.rq.base :
2317 if (qp->state != IB_QPS_RESET) {
2318 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2319 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2320 err = mlx5_core_qp_modify(dev->mdev,
2321 MLX5_CMD_OP_2RST_QP, 0,
2324 struct mlx5_modify_raw_qp_param raw_qp_param = {
2325 .operation = MLX5_CMD_OP_2RST_QP
2328 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2331 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2335 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2336 &send_cq, &recv_cq);
2338 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2339 mlx5_ib_lock_cqs(send_cq, recv_cq);
2340 /* del from lists under both locks above to protect reset flow paths */
2341 list_del(&qp->qps_list);
2343 list_del(&qp->cq_send_list);
2346 list_del(&qp->cq_recv_list);
2348 if (qp->create_type == MLX5_QP_KERNEL) {
2349 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2350 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2351 if (send_cq != recv_cq)
2352 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2355 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2356 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2358 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2359 qp->flags & MLX5_IB_QP_UNDERLAY) {
2360 destroy_raw_packet_qp(dev, qp);
2362 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2364 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2368 if (qp->create_type == MLX5_QP_KERNEL)
2369 destroy_qp_kernel(dev, qp);
2370 else if (qp->create_type == MLX5_QP_USER)
2371 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2374 static const char *ib_qp_type_str(enum ib_qp_type type)
2378 return "IB_QPT_SMI";
2380 return "IB_QPT_GSI";
2387 case IB_QPT_RAW_IPV6:
2388 return "IB_QPT_RAW_IPV6";
2389 case IB_QPT_RAW_ETHERTYPE:
2390 return "IB_QPT_RAW_ETHERTYPE";
2391 case IB_QPT_XRC_INI:
2392 return "IB_QPT_XRC_INI";
2393 case IB_QPT_XRC_TGT:
2394 return "IB_QPT_XRC_TGT";
2395 case IB_QPT_RAW_PACKET:
2396 return "IB_QPT_RAW_PACKET";
2397 case MLX5_IB_QPT_REG_UMR:
2398 return "MLX5_IB_QPT_REG_UMR";
2400 return "IB_QPT_DRIVER";
2403 return "Invalid QP type";
2407 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2408 struct ib_qp_init_attr *attr,
2409 struct mlx5_ib_create_qp *ucmd)
2411 struct mlx5_ib_qp *qp;
2413 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2416 if (!attr->srq || !attr->recv_cq)
2417 return ERR_PTR(-EINVAL);
2419 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2420 ucmd, sizeof(*ucmd), &uidx);
2422 return ERR_PTR(err);
2424 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2426 return ERR_PTR(-ENOMEM);
2428 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2434 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid);
2435 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2436 qp->qp_sub_type = MLX5_IB_QPT_DCT;
2437 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2438 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2439 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2440 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2441 MLX5_SET(dctc, dctc, user_index, uidx);
2443 if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE)
2444 configure_responder_scat_cqe(attr, dctc);
2446 qp->state = IB_QPS_RESET;
2451 return ERR_PTR(err);
2454 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2455 struct ib_qp_init_attr *init_attr,
2456 struct mlx5_ib_create_qp *ucmd,
2457 struct ib_udata *udata)
2459 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2465 if (udata->inlen < sizeof(*ucmd)) {
2466 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2469 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2473 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2474 init_attr->qp_type = MLX5_IB_QPT_DCI;
2476 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2477 init_attr->qp_type = MLX5_IB_QPT_DCT;
2479 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2484 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2485 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2492 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2493 struct ib_qp_init_attr *verbs_init_attr,
2494 struct ib_udata *udata)
2496 struct mlx5_ib_dev *dev;
2497 struct mlx5_ib_qp *qp;
2500 struct ib_qp_init_attr mlx_init_attr;
2501 struct ib_qp_init_attr *init_attr = verbs_init_attr;
2504 dev = to_mdev(pd->device);
2506 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2508 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2509 return ERR_PTR(-EINVAL);
2510 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2511 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2512 return ERR_PTR(-EINVAL);
2516 /* being cautious here */
2517 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2518 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2519 pr_warn("%s: no PD for transport %s\n", __func__,
2520 ib_qp_type_str(init_attr->qp_type));
2521 return ERR_PTR(-EINVAL);
2523 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2526 if (init_attr->qp_type == IB_QPT_DRIVER) {
2527 struct mlx5_ib_create_qp ucmd;
2529 init_attr = &mlx_init_attr;
2530 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2531 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2533 return ERR_PTR(err);
2535 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2536 if (init_attr->cap.max_recv_wr ||
2537 init_attr->cap.max_recv_sge) {
2538 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2539 return ERR_PTR(-EINVAL);
2542 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2546 switch (init_attr->qp_type) {
2547 case IB_QPT_XRC_TGT:
2548 case IB_QPT_XRC_INI:
2549 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2550 mlx5_ib_dbg(dev, "XRC not supported\n");
2551 return ERR_PTR(-ENOSYS);
2553 init_attr->recv_cq = NULL;
2554 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2555 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2556 init_attr->send_cq = NULL;
2560 case IB_QPT_RAW_PACKET:
2565 case MLX5_IB_QPT_HW_GSI:
2566 case MLX5_IB_QPT_REG_UMR:
2567 case MLX5_IB_QPT_DCI:
2568 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2570 return ERR_PTR(-ENOMEM);
2572 err = create_qp_common(dev, pd, init_attr, udata, qp);
2574 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2576 return ERR_PTR(err);
2579 if (is_qp0(init_attr->qp_type))
2580 qp->ibqp.qp_num = 0;
2581 else if (is_qp1(init_attr->qp_type))
2582 qp->ibqp.qp_num = 1;
2584 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2586 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2587 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2588 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2589 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2591 qp->trans_qp.xrcdn = xrcdn;
2596 return mlx5_ib_gsi_create_qp(pd, init_attr);
2598 case IB_QPT_RAW_IPV6:
2599 case IB_QPT_RAW_ETHERTYPE:
2602 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2603 init_attr->qp_type);
2604 /* Don't support raw QPs */
2605 return ERR_PTR(-EINVAL);
2608 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2609 qp->qp_sub_type = init_attr->qp_type;
2614 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2616 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2618 if (mqp->state == IB_QPS_RTR) {
2621 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2623 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2633 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2635 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2636 struct mlx5_ib_qp *mqp = to_mqp(qp);
2638 if (unlikely(qp->qp_type == IB_QPT_GSI))
2639 return mlx5_ib_gsi_destroy_qp(qp);
2641 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2642 return mlx5_ib_destroy_dct(mqp);
2644 destroy_qp_common(dev, mqp);
2651 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2652 const struct ib_qp_attr *attr,
2653 int attr_mask, __be32 *hw_access_flags)
2658 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2660 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2661 dest_rd_atomic = attr->max_dest_rd_atomic;
2663 dest_rd_atomic = qp->trans_qp.resp_depth;
2665 if (attr_mask & IB_QP_ACCESS_FLAGS)
2666 access_flags = attr->qp_access_flags;
2668 access_flags = qp->trans_qp.atomic_rd_en;
2670 if (!dest_rd_atomic)
2671 access_flags &= IB_ACCESS_REMOTE_WRITE;
2673 if (access_flags & IB_ACCESS_REMOTE_READ)
2674 *hw_access_flags |= MLX5_QP_BIT_RRE;
2675 if ((access_flags & IB_ACCESS_REMOTE_ATOMIC) &&
2676 qp->ibqp.qp_type == IB_QPT_RC) {
2679 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2680 if (atomic_mode < 0)
2683 *hw_access_flags |= MLX5_QP_BIT_RAE;
2684 *hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
2687 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2688 *hw_access_flags |= MLX5_QP_BIT_RWE;
2690 *hw_access_flags = cpu_to_be32(*hw_access_flags);
2696 MLX5_PATH_FLAG_FL = 1 << 0,
2697 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2698 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2701 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2703 if (rate == IB_RATE_PORT_CURRENT)
2706 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS)
2709 while (rate != IB_RATE_PORT_CURRENT &&
2710 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2711 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2714 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2717 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2718 struct mlx5_ib_sq *sq, u8 sl,
2726 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2727 in = kvzalloc(inlen, GFP_KERNEL);
2731 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2732 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2734 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2735 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2737 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2744 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2745 struct mlx5_ib_sq *sq, u8 tx_affinity,
2753 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2754 in = kvzalloc(inlen, GFP_KERNEL);
2758 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2759 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2761 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2762 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2764 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2771 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2772 const struct rdma_ah_attr *ah,
2773 struct mlx5_qp_path *path, u8 port, int attr_mask,
2774 u32 path_flags, const struct ib_qp_attr *attr,
2777 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2779 enum ib_gid_type gid_type;
2780 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2781 u8 sl = rdma_ah_get_sl(ah);
2783 if (attr_mask & IB_QP_PKEY_INDEX)
2784 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2787 if (ah_flags & IB_AH_GRH) {
2788 if (grh->sgid_index >=
2789 dev->mdev->port_caps[port - 1].gid_table_len) {
2790 pr_err("sgid_index (%u) too large. max is %d\n",
2792 dev->mdev->port_caps[port - 1].gid_table_len);
2797 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2798 if (!(ah_flags & IB_AH_GRH))
2801 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2802 if (qp->ibqp.qp_type == IB_QPT_RC ||
2803 qp->ibqp.qp_type == IB_QPT_UC ||
2804 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2805 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2807 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2808 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2809 gid_type = ah->grh.sgid_attr->gid_type;
2810 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2811 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2813 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2815 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2816 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2817 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2818 if (ah_flags & IB_AH_GRH)
2819 path->grh_mlid |= 1 << 7;
2820 path->dci_cfi_prio_sl = sl & 0xf;
2823 if (ah_flags & IB_AH_GRH) {
2824 path->mgid_index = grh->sgid_index;
2825 path->hop_limit = grh->hop_limit;
2826 path->tclass_flowlabel =
2827 cpu_to_be32((grh->traffic_class << 20) |
2829 memcpy(path->rgid, grh->dgid.raw, 16);
2832 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2835 path->static_rate = err;
2838 if (attr_mask & IB_QP_TIMEOUT)
2839 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2841 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2842 return modify_raw_packet_eth_prio(dev->mdev,
2843 &qp->raw_packet_qp.sq,
2844 sl & 0xf, qp->ibqp.pd);
2849 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2850 [MLX5_QP_STATE_INIT] = {
2851 [MLX5_QP_STATE_INIT] = {
2852 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2853 MLX5_QP_OPTPAR_RAE |
2854 MLX5_QP_OPTPAR_RWE |
2855 MLX5_QP_OPTPAR_PKEY_INDEX |
2856 MLX5_QP_OPTPAR_PRI_PORT,
2857 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2858 MLX5_QP_OPTPAR_PKEY_INDEX |
2859 MLX5_QP_OPTPAR_PRI_PORT,
2860 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2861 MLX5_QP_OPTPAR_Q_KEY |
2862 MLX5_QP_OPTPAR_PRI_PORT,
2864 [MLX5_QP_STATE_RTR] = {
2865 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2866 MLX5_QP_OPTPAR_RRE |
2867 MLX5_QP_OPTPAR_RAE |
2868 MLX5_QP_OPTPAR_RWE |
2869 MLX5_QP_OPTPAR_PKEY_INDEX,
2870 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2871 MLX5_QP_OPTPAR_RWE |
2872 MLX5_QP_OPTPAR_PKEY_INDEX,
2873 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2874 MLX5_QP_OPTPAR_Q_KEY,
2875 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2876 MLX5_QP_OPTPAR_Q_KEY,
2877 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2878 MLX5_QP_OPTPAR_RRE |
2879 MLX5_QP_OPTPAR_RAE |
2880 MLX5_QP_OPTPAR_RWE |
2881 MLX5_QP_OPTPAR_PKEY_INDEX,
2884 [MLX5_QP_STATE_RTR] = {
2885 [MLX5_QP_STATE_RTS] = {
2886 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2887 MLX5_QP_OPTPAR_RRE |
2888 MLX5_QP_OPTPAR_RAE |
2889 MLX5_QP_OPTPAR_RWE |
2890 MLX5_QP_OPTPAR_PM_STATE |
2891 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2892 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2893 MLX5_QP_OPTPAR_RWE |
2894 MLX5_QP_OPTPAR_PM_STATE,
2895 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2898 [MLX5_QP_STATE_RTS] = {
2899 [MLX5_QP_STATE_RTS] = {
2900 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2901 MLX5_QP_OPTPAR_RAE |
2902 MLX5_QP_OPTPAR_RWE |
2903 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2904 MLX5_QP_OPTPAR_PM_STATE |
2905 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2906 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2907 MLX5_QP_OPTPAR_PM_STATE |
2908 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2909 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2910 MLX5_QP_OPTPAR_SRQN |
2911 MLX5_QP_OPTPAR_CQN_RCV,
2914 [MLX5_QP_STATE_SQER] = {
2915 [MLX5_QP_STATE_RTS] = {
2916 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2917 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2918 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2919 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2920 MLX5_QP_OPTPAR_RWE |
2921 MLX5_QP_OPTPAR_RAE |
2927 static int ib_nr_to_mlx5_nr(int ib_mask)
2932 case IB_QP_CUR_STATE:
2934 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2936 case IB_QP_ACCESS_FLAGS:
2937 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2939 case IB_QP_PKEY_INDEX:
2940 return MLX5_QP_OPTPAR_PKEY_INDEX;
2942 return MLX5_QP_OPTPAR_PRI_PORT;
2944 return MLX5_QP_OPTPAR_Q_KEY;
2946 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2947 MLX5_QP_OPTPAR_PRI_PORT;
2948 case IB_QP_PATH_MTU:
2951 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2952 case IB_QP_RETRY_CNT:
2953 return MLX5_QP_OPTPAR_RETRY_COUNT;
2954 case IB_QP_RNR_RETRY:
2955 return MLX5_QP_OPTPAR_RNR_RETRY;
2958 case IB_QP_MAX_QP_RD_ATOMIC:
2959 return MLX5_QP_OPTPAR_SRA_MAX;
2960 case IB_QP_ALT_PATH:
2961 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2962 case IB_QP_MIN_RNR_TIMER:
2963 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2966 case IB_QP_MAX_DEST_RD_ATOMIC:
2967 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2968 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2969 case IB_QP_PATH_MIG_STATE:
2970 return MLX5_QP_OPTPAR_PM_STATE;
2973 case IB_QP_DEST_QPN:
2979 static int ib_mask_to_mlx5_opt(int ib_mask)
2984 for (i = 0; i < 8 * sizeof(int); i++) {
2985 if ((1 << i) & ib_mask)
2986 result |= ib_nr_to_mlx5_nr(1 << i);
2992 static int modify_raw_packet_qp_rq(
2993 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
2994 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3001 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
3002 in = kvzalloc(inlen, GFP_KERNEL);
3006 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
3007 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
3009 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
3010 MLX5_SET(rqc, rqc, state, new_state);
3012 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3013 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
3014 MLX5_SET64(modify_rq_in, in, modify_bitmask,
3015 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
3016 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
3020 "RAW PACKET QP counters are not supported on current FW\n");
3023 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
3027 rq->state = new_state;
3034 static int modify_raw_packet_qp_sq(
3035 struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state,
3036 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
3038 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
3039 struct mlx5_rate_limit old_rl = ibqp->rl;
3040 struct mlx5_rate_limit new_rl = old_rl;
3041 bool new_rate_added = false;
3048 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
3049 in = kvzalloc(inlen, GFP_KERNEL);
3053 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
3054 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
3056 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
3057 MLX5_SET(sqc, sqc, state, new_state);
3059 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3060 if (new_state != MLX5_SQC_STATE_RDY)
3061 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
3064 new_rl = raw_qp_param->rl;
3067 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
3069 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
3071 pr_err("Failed configuring rate limit(err %d): \
3072 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
3073 err, new_rl.rate, new_rl.max_burst_sz,
3074 new_rl.typical_pkt_sz);
3078 new_rate_added = true;
3081 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
3082 /* index 0 means no limit */
3083 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
3086 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
3088 /* Remove new rate from table if failed */
3090 mlx5_rl_remove_rate(dev, &new_rl);
3094 /* Only remove the old rate after new rate was set */
3096 !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
3097 (new_state != MLX5_SQC_STATE_RDY))
3098 mlx5_rl_remove_rate(dev, &old_rl);
3101 sq->state = new_state;
3108 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3109 const struct mlx5_modify_raw_qp_param *raw_qp_param,
3112 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3113 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3114 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3115 int modify_rq = !!qp->rq.wqe_cnt;
3116 int modify_sq = !!qp->sq.wqe_cnt;
3121 switch (raw_qp_param->operation) {
3122 case MLX5_CMD_OP_RST2INIT_QP:
3123 rq_state = MLX5_RQC_STATE_RDY;
3124 sq_state = MLX5_SQC_STATE_RDY;
3126 case MLX5_CMD_OP_2ERR_QP:
3127 rq_state = MLX5_RQC_STATE_ERR;
3128 sq_state = MLX5_SQC_STATE_ERR;
3130 case MLX5_CMD_OP_2RST_QP:
3131 rq_state = MLX5_RQC_STATE_RST;
3132 sq_state = MLX5_SQC_STATE_RST;
3134 case MLX5_CMD_OP_RTR2RTS_QP:
3135 case MLX5_CMD_OP_RTS2RTS_QP:
3136 if (raw_qp_param->set_mask ==
3137 MLX5_RAW_QP_RATE_LIMIT) {
3139 sq_state = sq->state;
3141 return raw_qp_param->set_mask ? -EINVAL : 0;
3144 case MLX5_CMD_OP_INIT2INIT_QP:
3145 case MLX5_CMD_OP_INIT2RTR_QP:
3146 if (raw_qp_param->set_mask)
3156 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
3164 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
3171 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state,
3172 raw_qp_param, qp->ibqp.pd);
3178 static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev,
3179 struct mlx5_ib_pd *pd,
3180 struct mlx5_ib_qp_base *qp_base,
3183 struct mlx5_ib_ucontext *ucontext = NULL;
3184 unsigned int tx_port_affinity;
3186 if (pd && pd->ibpd.uobject && pd->ibpd.uobject->context)
3187 ucontext = to_mucontext(pd->ibpd.uobject->context);
3190 tx_port_affinity = (unsigned int)atomic_add_return(
3191 1, &ucontext->tx_port_affinity) %
3194 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n",
3195 tx_port_affinity, qp_base->mqp.qpn, ucontext);
3198 (unsigned int)atomic_add_return(
3199 1, &dev->roce[port_num].tx_port_affinity) %
3202 mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n",
3203 tx_port_affinity, qp_base->mqp.qpn);
3206 return tx_port_affinity;
3209 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
3210 const struct ib_qp_attr *attr, int attr_mask,
3211 enum ib_qp_state cur_state, enum ib_qp_state new_state,
3212 const struct mlx5_ib_modify_qp *ucmd)
3214 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
3215 [MLX5_QP_STATE_RST] = {
3216 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3217 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3218 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
3220 [MLX5_QP_STATE_INIT] = {
3221 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3222 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3223 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
3224 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
3226 [MLX5_QP_STATE_RTR] = {
3227 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3228 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3229 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
3231 [MLX5_QP_STATE_RTS] = {
3232 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3233 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3234 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
3236 [MLX5_QP_STATE_SQD] = {
3237 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3238 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3240 [MLX5_QP_STATE_SQER] = {
3241 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3242 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3243 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
3245 [MLX5_QP_STATE_ERR] = {
3246 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
3247 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
3251 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3252 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3253 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
3254 struct mlx5_ib_cq *send_cq, *recv_cq;
3255 struct mlx5_qp_context *context;
3256 struct mlx5_ib_pd *pd;
3257 struct mlx5_ib_port *mibport = NULL;
3258 enum mlx5_qp_state mlx5_cur, mlx5_new;
3259 enum mlx5_qp_optpar optpar;
3265 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
3266 qp->qp_sub_type : ibqp->qp_type);
3270 context = kzalloc(sizeof(*context), GFP_KERNEL);
3275 context->flags = cpu_to_be32(mlx5_st << 16);
3277 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3278 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3280 switch (attr->path_mig_state) {
3281 case IB_MIG_MIGRATED:
3282 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3285 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3288 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3293 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3294 if ((ibqp->qp_type == IB_QPT_RC) ||
3295 (ibqp->qp_type == IB_QPT_UD &&
3296 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3297 (ibqp->qp_type == IB_QPT_UC) ||
3298 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3299 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3300 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3301 if (mlx5_lag_is_active(dev->mdev)) {
3302 u8 p = mlx5_core_native_port_num(dev->mdev);
3303 tx_affinity = get_tx_affinity(dev, pd, base, p);
3304 context->flags |= cpu_to_be32(tx_affinity << 24);
3309 if (is_sqp(ibqp->qp_type)) {
3310 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3311 } else if ((ibqp->qp_type == IB_QPT_UD &&
3312 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3313 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3314 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3315 } else if (attr_mask & IB_QP_PATH_MTU) {
3316 if (attr->path_mtu < IB_MTU_256 ||
3317 attr->path_mtu > IB_MTU_4096) {
3318 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3322 context->mtu_msgmax = (attr->path_mtu << 5) |
3323 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3326 if (attr_mask & IB_QP_DEST_QPN)
3327 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3329 if (attr_mask & IB_QP_PKEY_INDEX)
3330 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3332 /* todo implement counter_index functionality */
3334 if (is_sqp(ibqp->qp_type))
3335 context->pri_path.port = qp->port;
3337 if (attr_mask & IB_QP_PORT)
3338 context->pri_path.port = attr->port_num;
3340 if (attr_mask & IB_QP_AV) {
3341 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3342 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3343 attr_mask, 0, attr, false);
3348 if (attr_mask & IB_QP_TIMEOUT)
3349 context->pri_path.ackto_lt |= attr->timeout << 3;
3351 if (attr_mask & IB_QP_ALT_PATH) {
3352 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3355 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3361 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3362 &send_cq, &recv_cq);
3364 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3365 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3366 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3367 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3369 if (attr_mask & IB_QP_RNR_RETRY)
3370 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3372 if (attr_mask & IB_QP_RETRY_CNT)
3373 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3375 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3376 if (attr->max_rd_atomic)
3378 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3381 if (attr_mask & IB_QP_SQ_PSN)
3382 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3384 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3385 if (attr->max_dest_rd_atomic)
3387 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3390 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
3391 __be32 access_flags = 0;
3393 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
3397 context->params2 |= access_flags;
3400 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3401 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3403 if (attr_mask & IB_QP_RQ_PSN)
3404 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3406 if (attr_mask & IB_QP_QKEY)
3407 context->qkey = cpu_to_be32(attr->qkey);
3409 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3410 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3412 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3413 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3416 /* Underlay port should be used - index 0 function per port */
3417 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3420 mibport = &dev->port[port_num];
3421 context->qp_counter_set_usr_page |=
3422 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3425 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3426 context->sq_crq_size |= cpu_to_be16(1 << 4);
3428 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3429 context->deth_sqpn = cpu_to_be32(1);
3431 mlx5_cur = to_mlx5_state(cur_state);
3432 mlx5_new = to_mlx5_state(new_state);
3434 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3435 !optab[mlx5_cur][mlx5_new]) {
3440 op = optab[mlx5_cur][mlx5_new];
3441 optpar = ib_mask_to_mlx5_opt(attr_mask);
3442 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3444 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3445 qp->flags & MLX5_IB_QP_UNDERLAY) {
3446 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3448 raw_qp_param.operation = op;
3449 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3450 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3451 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3454 if (attr_mask & IB_QP_RATE_LIMIT) {
3455 raw_qp_param.rl.rate = attr->rate_limit;
3457 if (ucmd->burst_info.max_burst_sz) {
3458 if (attr->rate_limit &&
3459 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3460 raw_qp_param.rl.max_burst_sz =
3461 ucmd->burst_info.max_burst_sz;
3468 if (ucmd->burst_info.typical_pkt_sz) {
3469 if (attr->rate_limit &&
3470 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3471 raw_qp_param.rl.typical_pkt_sz =
3472 ucmd->burst_info.typical_pkt_sz;
3479 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3482 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3484 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3491 qp->state = new_state;
3493 if (attr_mask & IB_QP_ACCESS_FLAGS)
3494 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3495 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3496 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3497 if (attr_mask & IB_QP_PORT)
3498 qp->port = attr->port_num;
3499 if (attr_mask & IB_QP_ALT_PATH)
3500 qp->trans_qp.alt_port = attr->alt_port_num;
3503 * If we moved a kernel QP to RESET, clean up all old CQ
3504 * entries and reinitialize the QP.
3506 if (new_state == IB_QPS_RESET &&
3507 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3508 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3509 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3510 if (send_cq != recv_cq)
3511 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3517 qp->sq.cur_post = 0;
3519 qp->sq.cur_edge = get_sq_edge(&qp->sq, 0);
3520 qp->sq.last_poll = 0;
3521 qp->db.db[MLX5_RCV_DBR] = 0;
3522 qp->db.db[MLX5_SND_DBR] = 0;
3530 static inline bool is_valid_mask(int mask, int req, int opt)
3532 if ((mask & req) != req)
3535 if (mask & ~(req | opt))
3541 /* check valid transition for driver QP types
3542 * for now the only QP type that this function supports is DCI
3544 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3545 enum ib_qp_attr_mask attr_mask)
3547 int req = IB_QP_STATE;
3550 if (new_state == IB_QPS_RESET) {
3551 return is_valid_mask(attr_mask, req, opt);
3552 } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3553 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3554 return is_valid_mask(attr_mask, req, opt);
3555 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3556 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3557 return is_valid_mask(attr_mask, req, opt);
3558 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3559 req |= IB_QP_PATH_MTU;
3560 opt = IB_QP_PKEY_INDEX | IB_QP_AV;
3561 return is_valid_mask(attr_mask, req, opt);
3562 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3563 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3564 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3565 opt = IB_QP_MIN_RNR_TIMER;
3566 return is_valid_mask(attr_mask, req, opt);
3567 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3568 opt = IB_QP_MIN_RNR_TIMER;
3569 return is_valid_mask(attr_mask, req, opt);
3570 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3571 return is_valid_mask(attr_mask, req, opt);
3576 /* mlx5_ib_modify_dct: modify a DCT QP
3577 * valid transitions are:
3578 * RESET to INIT: must set access_flags, pkey_index and port
3579 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3580 * mtu, gid_index and hop_limit
3581 * Other transitions and attributes are illegal
3583 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3584 int attr_mask, struct ib_udata *udata)
3586 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3587 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3588 enum ib_qp_state cur_state, new_state;
3590 int required = IB_QP_STATE;
3593 if (!(attr_mask & IB_QP_STATE))
3596 cur_state = qp->state;
3597 new_state = attr->qp_state;
3599 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3600 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3601 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3602 if (!is_valid_mask(attr_mask, required, 0))
3605 if (attr->port_num == 0 ||
3606 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3607 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3608 attr->port_num, dev->num_ports);
3611 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3612 MLX5_SET(dctc, dctc, rre, 1);
3613 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3614 MLX5_SET(dctc, dctc, rwe, 1);
3615 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3618 atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT);
3619 if (atomic_mode < 0)
3622 MLX5_SET(dctc, dctc, atomic_mode, atomic_mode);
3623 MLX5_SET(dctc, dctc, rae, 1);
3625 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3626 MLX5_SET(dctc, dctc, port, attr->port_num);
3627 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3629 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3630 struct mlx5_ib_modify_qp_resp resp = {};
3631 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3634 if (udata->outlen < min_resp_len)
3636 resp.response_length = min_resp_len;
3638 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3639 if (!is_valid_mask(attr_mask, required, 0))
3641 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3642 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3643 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3644 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3645 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3646 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3648 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3649 MLX5_ST_SZ_BYTES(create_dct_in));
3652 resp.dctn = qp->dct.mdct.mqp.qpn;
3653 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3655 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3659 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3663 qp->state = IB_QPS_ERR;
3665 qp->state = new_state;
3669 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3670 int attr_mask, struct ib_udata *udata)
3672 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3673 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3674 struct mlx5_ib_modify_qp ucmd = {};
3675 enum ib_qp_type qp_type;
3676 enum ib_qp_state cur_state, new_state;
3677 size_t required_cmd_sz;
3681 if (ibqp->rwq_ind_tbl)
3684 if (udata && udata->inlen) {
3685 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3686 sizeof(ucmd.reserved);
3687 if (udata->inlen < required_cmd_sz)
3690 if (udata->inlen > sizeof(ucmd) &&
3691 !ib_is_udata_cleared(udata, sizeof(ucmd),
3692 udata->inlen - sizeof(ucmd)))
3695 if (ib_copy_from_udata(&ucmd, udata,
3696 min(udata->inlen, sizeof(ucmd))))
3699 if (ucmd.comp_mask ||
3700 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3701 memchr_inv(&ucmd.burst_info.reserved, 0,
3702 sizeof(ucmd.burst_info.reserved)))
3706 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3707 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3709 if (ibqp->qp_type == IB_QPT_DRIVER)
3710 qp_type = qp->qp_sub_type;
3712 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3713 IB_QPT_GSI : ibqp->qp_type;
3715 if (qp_type == MLX5_IB_QPT_DCT)
3716 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3718 mutex_lock(&qp->mutex);
3720 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3721 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3723 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3724 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3727 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3728 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3729 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3733 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3734 qp_type != MLX5_IB_QPT_DCI &&
3735 !ib_modify_qp_is_ok(cur_state, new_state, qp_type,
3737 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3738 cur_state, new_state, ibqp->qp_type, attr_mask);
3740 } else if (qp_type == MLX5_IB_QPT_DCI &&
3741 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3742 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3743 cur_state, new_state, qp_type, attr_mask);
3747 if ((attr_mask & IB_QP_PORT) &&
3748 (attr->port_num == 0 ||
3749 attr->port_num > dev->num_ports)) {
3750 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3751 attr->port_num, dev->num_ports);
3755 if (attr_mask & IB_QP_PKEY_INDEX) {
3756 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3757 if (attr->pkey_index >=
3758 dev->mdev->port_caps[port - 1].pkey_table_len) {
3759 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3765 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3766 attr->max_rd_atomic >
3767 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3768 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3769 attr->max_rd_atomic);
3773 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3774 attr->max_dest_rd_atomic >
3775 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3776 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3777 attr->max_dest_rd_atomic);
3781 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3786 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3790 mutex_unlock(&qp->mutex);
3794 static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3795 u32 wqe_sz, void **cur_edge)
3799 idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
3800 *cur_edge = get_sq_edge(sq, idx);
3802 *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
3805 /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
3806 * next nearby edge and get new address translation for current WQE position.
3808 * @seg: Current WQE position (16B aligned).
3809 * @wqe_sz: Total current WQE size [16B].
3810 * @cur_edge: Updated current edge.
3812 static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
3813 u32 wqe_sz, void **cur_edge)
3815 if (likely(*seg != *cur_edge))
3818 _handle_post_send_edge(sq, seg, wqe_sz, cur_edge);
3821 /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's
3822 * pointers. At the end @seg is aligned to 16B regardless the copied size.
3824 * @cur_edge: Updated current edge.
3825 * @seg: Current WQE position (16B aligned).
3826 * @wqe_sz: Total current WQE size [16B].
3827 * @src: Pointer to copy from.
3828 * @n: Number of bytes to copy.
3830 static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
3831 void **seg, u32 *wqe_sz, const void *src,
3835 size_t leftlen = *cur_edge - *seg;
3836 size_t copysz = min_t(size_t, leftlen, n);
3839 memcpy(*seg, src, copysz);
3843 stride = !n ? ALIGN(copysz, 16) : copysz;
3845 *wqe_sz += stride >> 4;
3846 handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
3850 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3852 struct mlx5_ib_cq *cq;
3855 cur = wq->head - wq->tail;
3856 if (likely(cur + nreq < wq->max_post))
3860 spin_lock(&cq->lock);
3861 cur = wq->head - wq->tail;
3862 spin_unlock(&cq->lock);
3864 return cur + nreq >= wq->max_post;
3867 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3868 u64 remote_addr, u32 rkey)
3870 rseg->raddr = cpu_to_be64(remote_addr);
3871 rseg->rkey = cpu_to_be32(rkey);
3875 static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
3876 void **seg, int *size, void **cur_edge)
3878 struct mlx5_wqe_eth_seg *eseg = *seg;
3880 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3882 if (wr->send_flags & IB_SEND_IP_CSUM)
3883 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3884 MLX5_ETH_WQE_L4_CSUM;
3886 if (wr->opcode == IB_WR_LSO) {
3887 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3888 size_t left, copysz;
3889 void *pdata = ud_wr->header;
3893 eseg->mss = cpu_to_be16(ud_wr->mss);
3894 eseg->inline_hdr.sz = cpu_to_be16(left);
3896 /* memcpy_send_wqe should get a 16B align address. Hence, we
3897 * first copy up to the current edge and then, if needed,
3898 * fall-through to memcpy_send_wqe.
3900 copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start,
3902 memcpy(eseg->inline_hdr.start, pdata, copysz);
3903 stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) -
3904 sizeof(eseg->inline_hdr.start) + copysz, 16);
3905 *size += stride / 16;
3908 if (copysz < left) {
3909 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
3912 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata,
3919 *seg += sizeof(struct mlx5_wqe_eth_seg);
3920 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3923 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3924 const struct ib_send_wr *wr)
3926 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3927 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3928 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3931 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3933 dseg->byte_count = cpu_to_be32(sg->length);
3934 dseg->lkey = cpu_to_be32(sg->lkey);
3935 dseg->addr = cpu_to_be64(sg->addr);
3938 static u64 get_xlt_octo(u64 bytes)
3940 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3941 MLX5_IB_UMR_OCTOWORD;
3944 static __be64 frwr_mkey_mask(void)
3948 result = MLX5_MKEY_MASK_LEN |
3949 MLX5_MKEY_MASK_PAGE_SIZE |
3950 MLX5_MKEY_MASK_START_ADDR |
3951 MLX5_MKEY_MASK_EN_RINVAL |
3952 MLX5_MKEY_MASK_KEY |
3958 MLX5_MKEY_MASK_SMALL_FENCE |
3959 MLX5_MKEY_MASK_FREE;
3961 return cpu_to_be64(result);
3964 static __be64 sig_mkey_mask(void)
3968 result = MLX5_MKEY_MASK_LEN |
3969 MLX5_MKEY_MASK_PAGE_SIZE |
3970 MLX5_MKEY_MASK_START_ADDR |
3971 MLX5_MKEY_MASK_EN_SIGERR |
3972 MLX5_MKEY_MASK_EN_RINVAL |
3973 MLX5_MKEY_MASK_KEY |
3978 MLX5_MKEY_MASK_SMALL_FENCE |
3979 MLX5_MKEY_MASK_FREE |
3980 MLX5_MKEY_MASK_BSF_EN;
3982 return cpu_to_be64(result);
3985 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3986 struct mlx5_ib_mr *mr, bool umr_inline)
3988 int size = mr->ndescs * mr->desc_size;
3990 memset(umr, 0, sizeof(*umr));
3992 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3994 umr->flags |= MLX5_UMR_INLINE;
3995 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3996 umr->mkey_mask = frwr_mkey_mask();
3999 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
4001 memset(umr, 0, sizeof(*umr));
4002 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
4003 umr->flags = MLX5_UMR_INLINE;
4006 static __be64 get_umr_enable_mr_mask(void)
4010 result = MLX5_MKEY_MASK_KEY |
4011 MLX5_MKEY_MASK_FREE;
4013 return cpu_to_be64(result);
4016 static __be64 get_umr_disable_mr_mask(void)
4020 result = MLX5_MKEY_MASK_FREE;
4022 return cpu_to_be64(result);
4025 static __be64 get_umr_update_translation_mask(void)
4029 result = MLX5_MKEY_MASK_LEN |
4030 MLX5_MKEY_MASK_PAGE_SIZE |
4031 MLX5_MKEY_MASK_START_ADDR;
4033 return cpu_to_be64(result);
4036 static __be64 get_umr_update_access_mask(int atomic)
4040 result = MLX5_MKEY_MASK_LR |
4046 result |= MLX5_MKEY_MASK_A;
4048 return cpu_to_be64(result);
4051 static __be64 get_umr_update_pd_mask(void)
4055 result = MLX5_MKEY_MASK_PD;
4057 return cpu_to_be64(result);
4060 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
4062 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
4063 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
4064 (mask & MLX5_MKEY_MASK_A &&
4065 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
4070 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
4071 struct mlx5_wqe_umr_ctrl_seg *umr,
4072 const struct ib_send_wr *wr, int atomic)
4074 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4076 memset(umr, 0, sizeof(*umr));
4078 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
4079 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
4081 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
4083 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
4084 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
4085 u64 offset = get_xlt_octo(umrwr->offset);
4087 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
4088 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
4089 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
4091 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
4092 umr->mkey_mask |= get_umr_update_translation_mask();
4093 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
4094 umr->mkey_mask |= get_umr_update_access_mask(atomic);
4095 umr->mkey_mask |= get_umr_update_pd_mask();
4097 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
4098 umr->mkey_mask |= get_umr_enable_mr_mask();
4099 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4100 umr->mkey_mask |= get_umr_disable_mr_mask();
4103 umr->flags |= MLX5_UMR_INLINE;
4105 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
4108 static u8 get_umr_flags(int acc)
4110 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
4111 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
4112 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
4113 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
4114 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
4117 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
4118 struct mlx5_ib_mr *mr,
4119 u32 key, int access)
4121 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
4123 memset(seg, 0, sizeof(*seg));
4125 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
4126 seg->log2_page_size = ilog2(mr->ibmr.page_size);
4127 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
4128 /* KLMs take twice the size of MTTs */
4131 seg->flags = get_umr_flags(access) | mr->access_mode;
4132 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
4133 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
4134 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
4135 seg->len = cpu_to_be64(mr->ibmr.length);
4136 seg->xlt_oct_size = cpu_to_be32(ndescs);
4139 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
4141 memset(seg, 0, sizeof(*seg));
4142 seg->status = MLX5_MKEY_STATUS_FREE;
4145 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg,
4146 const struct ib_send_wr *wr)
4148 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
4150 memset(seg, 0, sizeof(*seg));
4151 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
4152 seg->status = MLX5_MKEY_STATUS_FREE;
4154 seg->flags = convert_access(umrwr->access_flags);
4156 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
4157 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
4159 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
4161 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
4162 seg->len = cpu_to_be64(umrwr->length);
4163 seg->log2_page_size = umrwr->page_shift;
4164 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
4165 mlx5_mkey_variant(umrwr->mkey));
4168 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
4169 struct mlx5_ib_mr *mr,
4170 struct mlx5_ib_pd *pd)
4172 int bcount = mr->desc_size * mr->ndescs;
4174 dseg->addr = cpu_to_be64(mr->desc_map);
4175 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
4176 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
4179 static __be32 send_ieth(const struct ib_send_wr *wr)
4181 switch (wr->opcode) {
4182 case IB_WR_SEND_WITH_IMM:
4183 case IB_WR_RDMA_WRITE_WITH_IMM:
4184 return wr->ex.imm_data;
4186 case IB_WR_SEND_WITH_INV:
4187 return cpu_to_be32(wr->ex.invalidate_rkey);
4194 static u8 calc_sig(void *wqe, int size)
4200 for (i = 0; i < size; i++)
4206 static u8 wq_sig(void *wqe)
4208 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
4211 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
4212 void **wqe, int *wqe_sz, void **cur_edge)
4214 struct mlx5_wqe_inline_seg *seg;
4220 *wqe += sizeof(*seg);
4221 offset = sizeof(*seg);
4223 for (i = 0; i < wr->num_sge; i++) {
4224 size_t len = wr->sg_list[i].length;
4225 void *addr = (void *)(unsigned long)(wr->sg_list[i].addr);
4229 if (unlikely(inl > qp->max_inline_data))
4232 while (likely(len)) {
4236 handle_post_send_edge(&qp->sq, wqe,
4237 *wqe_sz + (offset >> 4),
4240 leftlen = *cur_edge - *wqe;
4241 copysz = min_t(size_t, leftlen, len);
4243 memcpy(*wqe, addr, copysz);
4251 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
4253 *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
4258 static u16 prot_field_size(enum ib_signature_type type)
4261 case IB_SIG_TYPE_T10_DIF:
4262 return MLX5_DIF_SIZE;
4268 static u8 bs_selector(int block_size)
4270 switch (block_size) {
4271 case 512: return 0x1;
4272 case 520: return 0x2;
4273 case 4096: return 0x3;
4274 case 4160: return 0x4;
4275 case 1073741824: return 0x5;
4280 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
4281 struct mlx5_bsf_inl *inl)
4283 /* Valid inline section and allow BSF refresh */
4284 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
4285 MLX5_BSF_REFRESH_DIF);
4286 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
4287 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
4288 /* repeating block */
4289 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
4290 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
4291 MLX5_DIF_CRC : MLX5_DIF_IPCS;
4293 if (domain->sig.dif.ref_remap)
4294 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
4296 if (domain->sig.dif.app_escape) {
4297 if (domain->sig.dif.ref_escape)
4298 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
4300 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
4303 inl->dif_app_bitmask_check =
4304 cpu_to_be16(domain->sig.dif.apptag_check_mask);
4307 static int mlx5_set_bsf(struct ib_mr *sig_mr,
4308 struct ib_sig_attrs *sig_attrs,
4309 struct mlx5_bsf *bsf, u32 data_size)
4311 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
4312 struct mlx5_bsf_basic *basic = &bsf->basic;
4313 struct ib_sig_domain *mem = &sig_attrs->mem;
4314 struct ib_sig_domain *wire = &sig_attrs->wire;
4316 memset(bsf, 0, sizeof(*bsf));
4318 /* Basic + Extended + Inline */
4319 basic->bsf_size_sbs = 1 << 7;
4320 /* Input domain check byte mask */
4321 basic->check_byte_mask = sig_attrs->check_mask;
4322 basic->raw_data_size = cpu_to_be32(data_size);
4325 switch (sig_attrs->mem.sig_type) {
4326 case IB_SIG_TYPE_NONE:
4328 case IB_SIG_TYPE_T10_DIF:
4329 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4330 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4331 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4338 switch (sig_attrs->wire.sig_type) {
4339 case IB_SIG_TYPE_NONE:
4341 case IB_SIG_TYPE_T10_DIF:
4342 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4343 mem->sig_type == wire->sig_type) {
4344 /* Same block structure */
4345 basic->bsf_size_sbs |= 1 << 4;
4346 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4347 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4348 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4349 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4350 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4351 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4353 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4355 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4356 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4365 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
4366 struct mlx5_ib_qp *qp, void **seg,
4367 int *size, void **cur_edge)
4369 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4370 struct ib_mr *sig_mr = wr->sig_mr;
4371 struct mlx5_bsf *bsf;
4372 u32 data_len = wr->wr.sg_list->length;
4373 u32 data_key = wr->wr.sg_list->lkey;
4374 u64 data_va = wr->wr.sg_list->addr;
4379 (data_key == wr->prot->lkey &&
4380 data_va == wr->prot->addr &&
4381 data_len == wr->prot->length)) {
4383 * Source domain doesn't contain signature information
4384 * or data and protection are interleaved in memory.
4385 * So need construct:
4386 * ------------------
4388 * ------------------
4390 * ------------------
4392 struct mlx5_klm *data_klm = *seg;
4394 data_klm->bcount = cpu_to_be32(data_len);
4395 data_klm->key = cpu_to_be32(data_key);
4396 data_klm->va = cpu_to_be64(data_va);
4397 wqe_size = ALIGN(sizeof(*data_klm), 64);
4400 * Source domain contains signature information
4401 * So need construct a strided block format:
4402 * ---------------------------
4403 * | stride_block_ctrl |
4404 * ---------------------------
4406 * ---------------------------
4408 * ---------------------------
4410 * ---------------------------
4412 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4413 struct mlx5_stride_block_entry *data_sentry;
4414 struct mlx5_stride_block_entry *prot_sentry;
4415 u32 prot_key = wr->prot->lkey;
4416 u64 prot_va = wr->prot->addr;
4417 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4421 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4422 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4424 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4426 pr_err("Bad block size given: %u\n", block_size);
4429 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4431 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4432 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4433 sblock_ctrl->num_entries = cpu_to_be16(2);
4435 data_sentry->bcount = cpu_to_be16(block_size);
4436 data_sentry->key = cpu_to_be32(data_key);
4437 data_sentry->va = cpu_to_be64(data_va);
4438 data_sentry->stride = cpu_to_be16(block_size);
4440 prot_sentry->bcount = cpu_to_be16(prot_size);
4441 prot_sentry->key = cpu_to_be32(prot_key);
4442 prot_sentry->va = cpu_to_be64(prot_va);
4443 prot_sentry->stride = cpu_to_be16(prot_size);
4445 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4446 sizeof(*prot_sentry), 64);
4450 *size += wqe_size / 16;
4451 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4454 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4458 *seg += sizeof(*bsf);
4459 *size += sizeof(*bsf) / 16;
4460 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4465 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4466 const struct ib_sig_handover_wr *wr, u32 size,
4467 u32 length, u32 pdn)
4469 struct ib_mr *sig_mr = wr->sig_mr;
4470 u32 sig_key = sig_mr->rkey;
4471 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4473 memset(seg, 0, sizeof(*seg));
4475 seg->flags = get_umr_flags(wr->access_flags) |
4476 MLX5_MKC_ACCESS_MODE_KLMS;
4477 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4478 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4479 MLX5_MKEY_BSF_EN | pdn);
4480 seg->len = cpu_to_be64(length);
4481 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4482 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4485 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4488 memset(umr, 0, sizeof(*umr));
4490 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4491 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4492 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4493 umr->mkey_mask = sig_mkey_mask();
4497 static int set_sig_umr_wr(const struct ib_send_wr *send_wr,
4498 struct mlx5_ib_qp *qp, void **seg, int *size,
4501 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4502 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4503 u32 pdn = get_pd(qp)->pdn;
4505 int region_len, ret;
4507 if (unlikely(wr->wr.num_sge != 1) ||
4508 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4509 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4510 unlikely(!sig_mr->sig->sig_status_checked))
4513 /* length of the protected region, data + protection */
4514 region_len = wr->wr.sg_list->length;
4516 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4517 wr->prot->addr != wr->wr.sg_list->addr ||
4518 wr->prot->length != wr->wr.sg_list->length))
4519 region_len += wr->prot->length;
4522 * KLM octoword size - if protection was provided
4523 * then we use strided block format (3 octowords),
4524 * else we use single KLM (1 octoword)
4526 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4528 set_sig_umr_segment(*seg, xlt_size);
4529 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4530 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4531 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4533 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4534 *seg += sizeof(struct mlx5_mkey_seg);
4535 *size += sizeof(struct mlx5_mkey_seg) / 16;
4536 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4538 ret = set_sig_data_segment(wr, qp, seg, size, cur_edge);
4542 sig_mr->sig->sig_status_checked = false;
4546 static int set_psv_wr(struct ib_sig_domain *domain,
4547 u32 psv_idx, void **seg, int *size)
4549 struct mlx5_seg_set_psv *psv_seg = *seg;
4551 memset(psv_seg, 0, sizeof(*psv_seg));
4552 psv_seg->psv_num = cpu_to_be32(psv_idx);
4553 switch (domain->sig_type) {
4554 case IB_SIG_TYPE_NONE:
4556 case IB_SIG_TYPE_T10_DIF:
4557 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4558 domain->sig.dif.app_tag);
4559 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4562 pr_err("Bad signature type (%d) is given.\n",
4567 *seg += sizeof(*psv_seg);
4568 *size += sizeof(*psv_seg) / 16;
4573 static int set_reg_wr(struct mlx5_ib_qp *qp,
4574 const struct ib_reg_wr *wr,
4575 void **seg, int *size, void **cur_edge)
4577 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4578 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4579 size_t mr_list_size = mr->ndescs * mr->desc_size;
4580 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4582 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4583 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4584 "Invalid IB_SEND_INLINE send flag\n");
4588 set_reg_umr_seg(*seg, mr, umr_inline);
4589 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4590 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4591 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4593 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4594 *seg += sizeof(struct mlx5_mkey_seg);
4595 *size += sizeof(struct mlx5_mkey_seg) / 16;
4596 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4599 memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs,
4601 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4);
4603 set_reg_data_seg(*seg, mr, pd);
4604 *seg += sizeof(struct mlx5_wqe_data_seg);
4605 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4610 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size,
4613 set_linv_umr_seg(*seg);
4614 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4615 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4616 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4617 set_linv_mkey_seg(*seg);
4618 *seg += sizeof(struct mlx5_mkey_seg);
4619 *size += sizeof(struct mlx5_mkey_seg) / 16;
4620 handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
4623 static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16)
4629 pr_debug("dump WQE index %u:\n", idx);
4630 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4631 if ((i & 0xf) == 0) {
4632 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4633 p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, tidx);
4634 pr_debug("WQBB at %p:\n", (void *)p);
4637 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4638 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4639 be32_to_cpu(p[j + 3]));
4643 static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4644 struct mlx5_wqe_ctrl_seg **ctrl,
4645 const struct ib_send_wr *wr, unsigned int *idx,
4646 int *size, void **cur_edge, int nreq,
4647 bool send_signaled, bool solicited)
4649 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4652 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4653 *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx);
4655 *(uint32_t *)(*seg + 8) = 0;
4656 (*ctrl)->imm = send_ieth(wr);
4657 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4658 (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4659 (solicited ? MLX5_WQE_CTRL_SOLICITED : 0);
4661 *seg += sizeof(**ctrl);
4662 *size = sizeof(**ctrl) / 16;
4663 *cur_edge = qp->sq.cur_edge;
4668 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4669 struct mlx5_wqe_ctrl_seg **ctrl,
4670 const struct ib_send_wr *wr, unsigned *idx,
4671 int *size, void **cur_edge, int nreq)
4673 return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq,
4674 wr->send_flags & IB_SEND_SIGNALED,
4675 wr->send_flags & IB_SEND_SOLICITED);
4678 static void finish_wqe(struct mlx5_ib_qp *qp,
4679 struct mlx5_wqe_ctrl_seg *ctrl,
4680 void *seg, u8 size, void *cur_edge,
4681 unsigned int idx, u64 wr_id, int nreq, u8 fence,
4686 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4687 mlx5_opcode | ((u32)opmod << 24));
4688 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4689 ctrl->fm_ce_se |= fence;
4690 if (unlikely(qp->wq_sig))
4691 ctrl->signature = wq_sig(ctrl);
4693 qp->sq.wrid[idx] = wr_id;
4694 qp->sq.w_list[idx].opcode = mlx5_opcode;
4695 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4696 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4697 qp->sq.w_list[idx].next = qp->sq.cur_post;
4699 /* We save the edge which was possibly updated during the WQE
4700 * construction, into SQ's cache.
4702 seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB);
4703 qp->sq.cur_edge = (unlikely(seg == cur_edge)) ?
4704 get_sq_edge(&qp->sq, qp->sq.cur_post &
4705 (qp->sq.wqe_cnt - 1)) :
4709 static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
4710 const struct ib_send_wr **bad_wr, bool drain)
4712 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4713 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4714 struct mlx5_core_dev *mdev = dev->mdev;
4715 struct mlx5_ib_qp *qp;
4716 struct mlx5_ib_mr *mr;
4717 struct mlx5_wqe_xrc_seg *xrc;
4720 int uninitialized_var(size);
4721 unsigned long flags;
4731 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
4737 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4738 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4743 spin_lock_irqsave(&qp->sq.lock, flags);
4745 for (nreq = 0; wr; nreq++, wr = wr->next) {
4746 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4747 mlx5_ib_warn(dev, "\n");
4753 num_sge = wr->num_sge;
4754 if (unlikely(num_sge > qp->sq.max_gs)) {
4755 mlx5_ib_warn(dev, "\n");
4761 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge,
4764 mlx5_ib_warn(dev, "\n");
4770 if (wr->opcode == IB_WR_LOCAL_INV ||
4771 wr->opcode == IB_WR_REG_MR) {
4772 fence = dev->umr_fence;
4773 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4774 } else if (wr->send_flags & IB_SEND_FENCE) {
4776 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4778 fence = MLX5_FENCE_MODE_FENCE;
4780 fence = qp->next_fence;
4783 switch (ibqp->qp_type) {
4784 case IB_QPT_XRC_INI:
4786 seg += sizeof(*xrc);
4787 size += sizeof(*xrc) / 16;
4790 switch (wr->opcode) {
4791 case IB_WR_RDMA_READ:
4792 case IB_WR_RDMA_WRITE:
4793 case IB_WR_RDMA_WRITE_WITH_IMM:
4794 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4796 seg += sizeof(struct mlx5_wqe_raddr_seg);
4797 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4800 case IB_WR_ATOMIC_CMP_AND_SWP:
4801 case IB_WR_ATOMIC_FETCH_AND_ADD:
4802 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4803 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4808 case IB_WR_LOCAL_INV:
4809 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4810 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4811 set_linv_wr(qp, &seg, &size, &cur_edge);
4816 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4817 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4818 err = set_reg_wr(qp, reg_wr(wr), &seg, &size,
4827 case IB_WR_REG_SIG_MR:
4828 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4829 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4831 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4832 err = set_sig_umr_wr(wr, qp, &seg, &size,
4835 mlx5_ib_warn(dev, "\n");
4840 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4841 wr->wr_id, nreq, fence,
4844 * SET_PSV WQEs are not signaled and solicited
4847 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4848 &size, &cur_edge, nreq, false,
4851 mlx5_ib_warn(dev, "\n");
4857 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4858 mr->sig->psv_memory.psv_idx, &seg,
4861 mlx5_ib_warn(dev, "\n");
4866 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4867 wr->wr_id, nreq, fence,
4868 MLX5_OPCODE_SET_PSV);
4869 err = __begin_wqe(qp, &seg, &ctrl, wr, &idx,
4870 &size, &cur_edge, nreq, false,
4873 mlx5_ib_warn(dev, "\n");
4879 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4880 mr->sig->psv_wire.psv_idx, &seg,
4883 mlx5_ib_warn(dev, "\n");
4888 finish_wqe(qp, ctrl, seg, size, cur_edge, idx,
4889 wr->wr_id, nreq, fence,
4890 MLX5_OPCODE_SET_PSV);
4891 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4901 switch (wr->opcode) {
4902 case IB_WR_RDMA_WRITE:
4903 case IB_WR_RDMA_WRITE_WITH_IMM:
4904 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4906 seg += sizeof(struct mlx5_wqe_raddr_seg);
4907 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4916 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4917 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4923 case MLX5_IB_QPT_HW_GSI:
4924 set_datagram_seg(seg, wr);
4925 seg += sizeof(struct mlx5_wqe_datagram_seg);
4926 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4927 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
4931 set_datagram_seg(seg, wr);
4932 seg += sizeof(struct mlx5_wqe_datagram_seg);
4933 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4934 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
4936 /* handle qp that supports ud offload */
4937 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4938 struct mlx5_wqe_eth_pad *pad;
4941 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4942 seg += sizeof(struct mlx5_wqe_eth_pad);
4943 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4944 set_eth_seg(wr, qp, &seg, &size, &cur_edge);
4945 handle_post_send_edge(&qp->sq, &seg, size,
4949 case MLX5_IB_QPT_REG_UMR:
4950 if (wr->opcode != MLX5_IB_WR_UMR) {
4952 mlx5_ib_warn(dev, "bad opcode\n");
4955 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4956 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4957 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4960 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4961 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4962 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
4963 set_reg_mkey_segment(seg, wr);
4964 seg += sizeof(struct mlx5_mkey_seg);
4965 size += sizeof(struct mlx5_mkey_seg) / 16;
4966 handle_post_send_edge(&qp->sq, &seg, size, &cur_edge);
4973 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4974 err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge);
4975 if (unlikely(err)) {
4976 mlx5_ib_warn(dev, "\n");
4981 for (i = 0; i < num_sge; i++) {
4982 handle_post_send_edge(&qp->sq, &seg, size,
4984 if (likely(wr->sg_list[i].length)) {
4986 ((struct mlx5_wqe_data_seg *)seg,
4988 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4989 seg += sizeof(struct mlx5_wqe_data_seg);
4994 qp->next_fence = next_fence;
4995 finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq,
4996 fence, mlx5_ib_opcode[wr->opcode]);
4999 dump_wqe(qp, idx, size);
5004 qp->sq.head += nreq;
5006 /* Make sure that descriptors are written before
5007 * updating doorbell record and ringing the doorbell
5011 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
5013 /* Make sure doorbell record is visible to the HCA before
5014 * we hit doorbell */
5017 /* currently we support only regular doorbells */
5018 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
5019 /* Make sure doorbells don't leak out of SQ spinlock
5020 * and reach the HCA out of order.
5023 bf->offset ^= bf->buf_size;
5026 spin_unlock_irqrestore(&qp->sq.lock, flags);
5031 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
5032 const struct ib_send_wr **bad_wr)
5034 return _mlx5_ib_post_send(ibqp, wr, bad_wr, false);
5037 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
5039 sig->signature = calc_sig(sig, size);
5042 static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5043 const struct ib_recv_wr **bad_wr, bool drain)
5045 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5046 struct mlx5_wqe_data_seg *scat;
5047 struct mlx5_rwqe_sig *sig;
5048 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5049 struct mlx5_core_dev *mdev = dev->mdev;
5050 unsigned long flags;
5056 if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR &&
5062 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5063 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
5065 spin_lock_irqsave(&qp->rq.lock, flags);
5067 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
5069 for (nreq = 0; wr; nreq++, wr = wr->next) {
5070 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
5076 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
5082 scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind);
5086 for (i = 0; i < wr->num_sge; i++)
5087 set_data_ptr_seg(scat + i, wr->sg_list + i);
5089 if (i < qp->rq.max_gs) {
5090 scat[i].byte_count = 0;
5091 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
5096 sig = (struct mlx5_rwqe_sig *)scat;
5097 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
5100 qp->rq.wrid[ind] = wr->wr_id;
5102 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
5107 qp->rq.head += nreq;
5109 /* Make sure that descriptors are written before
5114 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
5117 spin_unlock_irqrestore(&qp->rq.lock, flags);
5122 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
5123 const struct ib_recv_wr **bad_wr)
5125 return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
5128 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
5130 switch (mlx5_state) {
5131 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
5132 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
5133 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
5134 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
5135 case MLX5_QP_STATE_SQ_DRAINING:
5136 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
5137 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
5138 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
5143 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
5145 switch (mlx5_mig_state) {
5146 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
5147 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
5148 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
5153 static int to_ib_qp_access_flags(int mlx5_flags)
5157 if (mlx5_flags & MLX5_QP_BIT_RRE)
5158 ib_flags |= IB_ACCESS_REMOTE_READ;
5159 if (mlx5_flags & MLX5_QP_BIT_RWE)
5160 ib_flags |= IB_ACCESS_REMOTE_WRITE;
5161 if (mlx5_flags & MLX5_QP_BIT_RAE)
5162 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
5167 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
5168 struct rdma_ah_attr *ah_attr,
5169 struct mlx5_qp_path *path)
5172 memset(ah_attr, 0, sizeof(*ah_attr));
5174 if (!path->port || path->port > ibdev->num_ports)
5177 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
5179 rdma_ah_set_port_num(ah_attr, path->port);
5180 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
5182 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
5183 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
5184 rdma_ah_set_static_rate(ah_attr,
5185 path->static_rate ? path->static_rate - 5 : 0);
5186 if (path->grh_mlid & (1 << 7)) {
5187 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
5189 rdma_ah_set_grh(ah_attr, NULL,
5193 (tc_fl >> 20) & 0xff);
5194 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
5198 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
5199 struct mlx5_ib_sq *sq,
5204 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
5207 sq->state = *sq_state;
5213 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
5214 struct mlx5_ib_rq *rq,
5222 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
5223 out = kvzalloc(inlen, GFP_KERNEL);
5227 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
5231 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
5232 *rq_state = MLX5_GET(rqc, rqc, state);
5233 rq->state = *rq_state;
5240 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
5241 struct mlx5_ib_qp *qp, u8 *qp_state)
5243 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
5244 [MLX5_RQC_STATE_RST] = {
5245 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5246 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5247 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
5248 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
5250 [MLX5_RQC_STATE_RDY] = {
5251 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5252 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5253 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
5254 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
5256 [MLX5_RQC_STATE_ERR] = {
5257 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
5258 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
5259 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
5260 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
5262 [MLX5_RQ_STATE_NA] = {
5263 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
5264 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
5265 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
5266 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
5270 *qp_state = sqrq_trans[rq_state][sq_state];
5272 if (*qp_state == MLX5_QP_STATE_BAD) {
5273 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
5274 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
5275 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
5279 if (*qp_state == MLX5_QP_STATE)
5280 *qp_state = qp->state;
5285 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
5286 struct mlx5_ib_qp *qp,
5287 u8 *raw_packet_qp_state)
5289 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
5290 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
5291 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
5293 u8 sq_state = MLX5_SQ_STATE_NA;
5294 u8 rq_state = MLX5_RQ_STATE_NA;
5296 if (qp->sq.wqe_cnt) {
5297 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
5302 if (qp->rq.wqe_cnt) {
5303 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
5308 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
5309 raw_packet_qp_state);
5312 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
5313 struct ib_qp_attr *qp_attr)
5315 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
5316 struct mlx5_qp_context *context;
5321 outb = kzalloc(outlen, GFP_KERNEL);
5325 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
5330 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
5331 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
5333 mlx5_state = be32_to_cpu(context->flags) >> 28;
5335 qp->state = to_ib_qp_state(mlx5_state);
5336 qp_attr->path_mtu = context->mtu_msgmax >> 5;
5337 qp_attr->path_mig_state =
5338 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
5339 qp_attr->qkey = be32_to_cpu(context->qkey);
5340 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
5341 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
5342 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
5343 qp_attr->qp_access_flags =
5344 to_ib_qp_access_flags(be32_to_cpu(context->params2));
5346 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
5347 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5348 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5349 qp_attr->alt_pkey_index =
5350 be16_to_cpu(context->alt_path.pkey_index);
5351 qp_attr->alt_port_num =
5352 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5355 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5356 qp_attr->port_num = context->pri_path.port;
5358 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5359 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5361 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5363 qp_attr->max_dest_rd_atomic =
5364 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5365 qp_attr->min_rnr_timer =
5366 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5367 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5368 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5369 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5370 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
5377 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5378 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5379 struct ib_qp_init_attr *qp_init_attr)
5381 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5383 u32 access_flags = 0;
5384 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5387 int supported_mask = IB_QP_STATE |
5388 IB_QP_ACCESS_FLAGS |
5390 IB_QP_MIN_RNR_TIMER |
5395 if (qp_attr_mask & ~supported_mask)
5397 if (mqp->state != IB_QPS_RTR)
5400 out = kzalloc(outlen, GFP_KERNEL);
5404 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5408 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5410 if (qp_attr_mask & IB_QP_STATE)
5411 qp_attr->qp_state = IB_QPS_RTR;
5413 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5414 if (MLX5_GET(dctc, dctc, rre))
5415 access_flags |= IB_ACCESS_REMOTE_READ;
5416 if (MLX5_GET(dctc, dctc, rwe))
5417 access_flags |= IB_ACCESS_REMOTE_WRITE;
5418 if (MLX5_GET(dctc, dctc, rae))
5419 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5420 qp_attr->qp_access_flags = access_flags;
5423 if (qp_attr_mask & IB_QP_PORT)
5424 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5425 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5426 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5427 if (qp_attr_mask & IB_QP_AV) {
5428 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5429 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5430 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5431 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5433 if (qp_attr_mask & IB_QP_PATH_MTU)
5434 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5435 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5436 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5442 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5443 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5445 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5446 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5448 u8 raw_packet_qp_state;
5450 if (ibqp->rwq_ind_tbl)
5453 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5454 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5457 /* Not all of output fields are applicable, make sure to zero them */
5458 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5459 memset(qp_attr, 0, sizeof(*qp_attr));
5461 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5462 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5463 qp_attr_mask, qp_init_attr);
5465 mutex_lock(&qp->mutex);
5467 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5468 qp->flags & MLX5_IB_QP_UNDERLAY) {
5469 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5472 qp->state = raw_packet_qp_state;
5473 qp_attr->port_num = 1;
5475 err = query_qp_attr(dev, qp, qp_attr);
5480 qp_attr->qp_state = qp->state;
5481 qp_attr->cur_qp_state = qp_attr->qp_state;
5482 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5483 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5485 if (!ibqp->uobject) {
5486 qp_attr->cap.max_send_wr = qp->sq.max_post;
5487 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5488 qp_init_attr->qp_context = ibqp->qp_context;
5490 qp_attr->cap.max_send_wr = 0;
5491 qp_attr->cap.max_send_sge = 0;
5494 qp_init_attr->qp_type = ibqp->qp_type;
5495 qp_init_attr->recv_cq = ibqp->recv_cq;
5496 qp_init_attr->send_cq = ibqp->send_cq;
5497 qp_init_attr->srq = ibqp->srq;
5498 qp_attr->cap.max_inline_data = qp->max_inline_data;
5500 qp_init_attr->cap = qp_attr->cap;
5502 qp_init_attr->create_flags = 0;
5503 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5504 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5506 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5507 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5508 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5509 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5510 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5511 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5512 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5513 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5515 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5516 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5519 mutex_unlock(&qp->mutex);
5523 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5524 struct ib_ucontext *context,
5525 struct ib_udata *udata)
5527 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5528 struct mlx5_ib_xrcd *xrcd;
5531 if (!MLX5_CAP_GEN(dev->mdev, xrc))
5532 return ERR_PTR(-ENOSYS);
5534 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5536 return ERR_PTR(-ENOMEM);
5538 err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0);
5541 return ERR_PTR(-ENOMEM);
5544 return &xrcd->ibxrcd;
5547 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5549 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5550 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5553 err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0);
5555 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5561 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5563 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5564 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5565 struct ib_event event;
5567 if (rwq->ibwq.event_handler) {
5568 event.device = rwq->ibwq.device;
5569 event.element.wq = &rwq->ibwq;
5571 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5572 event.event = IB_EVENT_WQ_FATAL;
5575 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5579 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5583 static int set_delay_drop(struct mlx5_ib_dev *dev)
5587 mutex_lock(&dev->delay_drop.lock);
5588 if (dev->delay_drop.activate)
5591 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5595 dev->delay_drop.activate = true;
5597 mutex_unlock(&dev->delay_drop.lock);
5600 atomic_inc(&dev->delay_drop.rqs_cnt);
5604 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5605 struct ib_wq_init_attr *init_attr)
5607 struct mlx5_ib_dev *dev;
5608 int has_net_offloads;
5616 dev = to_mdev(pd->device);
5618 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5619 in = kvzalloc(inlen, GFP_KERNEL);
5623 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
5624 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5625 MLX5_SET(rqc, rqc, mem_rq_type,
5626 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5627 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5628 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5629 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5630 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5631 wq = MLX5_ADDR_OF(rqc, rqc, wq);
5632 MLX5_SET(wq, wq, wq_type,
5633 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5634 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5635 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5636 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5637 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5641 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5644 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5645 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5646 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5647 MLX5_SET(wq, wq, log_wqe_stride_size,
5648 rwq->single_stride_log_num_of_bytes -
5649 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5650 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5651 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5653 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5654 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5655 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5656 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5657 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5658 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5659 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5660 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5661 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5662 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5667 MLX5_SET(rqc, rqc, vsd, 1);
5669 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5670 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5671 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5675 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5677 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5678 if (!(dev->ib_dev.attrs.raw_packet_caps &
5679 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5680 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5684 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5686 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5687 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5688 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5689 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5690 err = set_delay_drop(dev);
5692 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5694 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5696 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5704 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5705 struct ib_wq_init_attr *wq_init_attr,
5706 struct mlx5_ib_create_wq *ucmd,
5707 struct mlx5_ib_rwq *rwq)
5709 /* Sanity check RQ size before proceeding */
5710 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5713 if (!ucmd->rq_wqe_count)
5716 rwq->wqe_count = ucmd->rq_wqe_count;
5717 rwq->wqe_shift = ucmd->rq_wqe_shift;
5718 if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size))
5721 rwq->log_rq_stride = rwq->wqe_shift;
5722 rwq->log_rq_size = ilog2(rwq->wqe_count);
5726 static int prepare_user_rq(struct ib_pd *pd,
5727 struct ib_wq_init_attr *init_attr,
5728 struct ib_udata *udata,
5729 struct mlx5_ib_rwq *rwq)
5731 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5732 struct mlx5_ib_create_wq ucmd = {};
5734 size_t required_cmd_sz;
5736 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5737 + sizeof(ucmd.single_stride_log_num_of_bytes);
5738 if (udata->inlen < required_cmd_sz) {
5739 mlx5_ib_dbg(dev, "invalid inlen\n");
5743 if (udata->inlen > sizeof(ucmd) &&
5744 !ib_is_udata_cleared(udata, sizeof(ucmd),
5745 udata->inlen - sizeof(ucmd))) {
5746 mlx5_ib_dbg(dev, "inlen is not supported\n");
5750 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5751 mlx5_ib_dbg(dev, "copy failed\n");
5755 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5756 mlx5_ib_dbg(dev, "invalid comp mask\n");
5758 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5759 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5760 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5763 if ((ucmd.single_stride_log_num_of_bytes <
5764 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5765 (ucmd.single_stride_log_num_of_bytes >
5766 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5767 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5768 ucmd.single_stride_log_num_of_bytes,
5769 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5770 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5773 if ((ucmd.single_wqe_log_num_of_strides >
5774 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5775 (ucmd.single_wqe_log_num_of_strides <
5776 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5777 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5778 ucmd.single_wqe_log_num_of_strides,
5779 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5780 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5783 rwq->single_stride_log_num_of_bytes =
5784 ucmd.single_stride_log_num_of_bytes;
5785 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5786 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5787 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5790 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5792 mlx5_ib_dbg(dev, "err %d\n", err);
5796 err = create_user_rq(dev, pd, rwq, &ucmd);
5798 mlx5_ib_dbg(dev, "err %d\n", err);
5802 rwq->user_index = ucmd.user_index;
5806 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5807 struct ib_wq_init_attr *init_attr,
5808 struct ib_udata *udata)
5810 struct mlx5_ib_dev *dev;
5811 struct mlx5_ib_rwq *rwq;
5812 struct mlx5_ib_create_wq_resp resp = {};
5813 size_t min_resp_len;
5817 return ERR_PTR(-ENOSYS);
5819 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5820 if (udata->outlen && udata->outlen < min_resp_len)
5821 return ERR_PTR(-EINVAL);
5823 dev = to_mdev(pd->device);
5824 switch (init_attr->wq_type) {
5826 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5828 return ERR_PTR(-ENOMEM);
5829 err = prepare_user_rq(pd, init_attr, udata, rwq);
5832 err = create_rq(rwq, pd, init_attr);
5837 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5838 init_attr->wq_type);
5839 return ERR_PTR(-EINVAL);
5842 rwq->ibwq.wq_num = rwq->core_qp.qpn;
5843 rwq->ibwq.state = IB_WQS_RESET;
5844 if (udata->outlen) {
5845 resp.response_length = offsetof(typeof(resp), response_length) +
5846 sizeof(resp.response_length);
5847 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5852 rwq->core_qp.event = mlx5_ib_wq_event;
5853 rwq->ibwq.event_handler = init_attr->event_handler;
5857 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5859 destroy_user_rq(dev, pd, rwq);
5862 return ERR_PTR(err);
5865 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5867 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5868 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5870 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5871 destroy_user_rq(dev, wq->pd, rwq);
5877 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5878 struct ib_rwq_ind_table_init_attr *init_attr,
5879 struct ib_udata *udata)
5881 struct mlx5_ib_dev *dev = to_mdev(device);
5882 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5883 int sz = 1 << init_attr->log_ind_tbl_size;
5884 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5885 size_t min_resp_len;
5892 if (udata->inlen > 0 &&
5893 !ib_is_udata_cleared(udata, 0,
5895 return ERR_PTR(-EOPNOTSUPP);
5897 if (init_attr->log_ind_tbl_size >
5898 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5899 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5900 init_attr->log_ind_tbl_size,
5901 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5902 return ERR_PTR(-EINVAL);
5905 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5906 if (udata->outlen && udata->outlen < min_resp_len)
5907 return ERR_PTR(-EINVAL);
5909 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5911 return ERR_PTR(-ENOMEM);
5913 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5914 in = kvzalloc(inlen, GFP_KERNEL);
5920 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5922 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5923 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5925 for (i = 0; i < sz; i++)
5926 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5928 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5929 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5931 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5937 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5938 if (udata->outlen) {
5939 resp.response_length = offsetof(typeof(resp), response_length) +
5940 sizeof(resp.response_length);
5941 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5946 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5949 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5952 return ERR_PTR(err);
5955 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5957 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5958 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5960 mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5966 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5967 u32 wq_attr_mask, struct ib_udata *udata)
5969 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5970 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5971 struct mlx5_ib_modify_wq ucmd = {};
5972 size_t required_cmd_sz;
5980 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5981 if (udata->inlen < required_cmd_sz)
5984 if (udata->inlen > sizeof(ucmd) &&
5985 !ib_is_udata_cleared(udata, sizeof(ucmd),
5986 udata->inlen - sizeof(ucmd)))
5989 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5992 if (ucmd.comp_mask || ucmd.reserved)
5995 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5996 in = kvzalloc(inlen, GFP_KERNEL);
6000 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
6002 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
6003 wq_attr->curr_wq_state : wq->state;
6004 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
6005 wq_attr->wq_state : curr_wq_state;
6006 if (curr_wq_state == IB_WQS_ERR)
6007 curr_wq_state = MLX5_RQC_STATE_ERR;
6008 if (wq_state == IB_WQS_ERR)
6009 wq_state = MLX5_RQC_STATE_ERR;
6010 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
6011 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
6012 MLX5_SET(rqc, rqc, state, wq_state);
6014 if (wq_attr_mask & IB_WQ_FLAGS) {
6015 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
6016 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
6017 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
6018 mlx5_ib_dbg(dev, "VLAN offloads are not "
6023 MLX5_SET64(modify_rq_in, in, modify_bitmask,
6024 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
6025 MLX5_SET(rqc, rqc, vsd,
6026 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
6029 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
6030 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
6036 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
6037 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
6038 MLX5_SET64(modify_rq_in, in, modify_bitmask,
6039 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
6040 MLX5_SET(rqc, rqc, counter_set_id,
6041 dev->port->cnts.set_id);
6045 "Receive WQ counters are not supported on current FW\n");
6048 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
6050 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
6057 struct mlx5_ib_drain_cqe {
6059 struct completion done;
6062 static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
6064 struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
6065 struct mlx5_ib_drain_cqe,
6068 complete(&cqe->done);
6071 /* This function returns only once the drained WR was completed */
6072 static void handle_drain_completion(struct ib_cq *cq,
6073 struct mlx5_ib_drain_cqe *sdrain,
6074 struct mlx5_ib_dev *dev)
6076 struct mlx5_core_dev *mdev = dev->mdev;
6078 if (cq->poll_ctx == IB_POLL_DIRECT) {
6079 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
6080 ib_process_cq_direct(cq, -1);
6084 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6085 struct mlx5_ib_cq *mcq = to_mcq(cq);
6086 bool triggered = false;
6087 unsigned long flags;
6089 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
6090 /* Make sure that the CQ handler won't run if wasn't run yet */
6091 if (!mcq->mcq.reset_notify_added)
6092 mcq->mcq.reset_notify_added = 1;
6095 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
6098 /* Wait for any scheduled/running task to be ended */
6099 switch (cq->poll_ctx) {
6100 case IB_POLL_SOFTIRQ:
6101 irq_poll_disable(&cq->iop);
6102 irq_poll_enable(&cq->iop);
6104 case IB_POLL_WORKQUEUE:
6105 cancel_work_sync(&cq->work);
6112 /* Run the CQ handler - this makes sure that the drain WR will
6113 * be processed if wasn't processed yet.
6115 mcq->mcq.comp(&mcq->mcq);
6118 wait_for_completion(&sdrain->done);
6121 void mlx5_ib_drain_sq(struct ib_qp *qp)
6123 struct ib_cq *cq = qp->send_cq;
6124 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6125 struct mlx5_ib_drain_cqe sdrain;
6126 const struct ib_send_wr *bad_swr;
6127 struct ib_rdma_wr swr = {
6130 { .wr_cqe = &sdrain.cqe, },
6131 .opcode = IB_WR_RDMA_WRITE,
6135 struct mlx5_ib_dev *dev = to_mdev(qp->device);
6136 struct mlx5_core_dev *mdev = dev->mdev;
6138 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6139 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6140 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6144 sdrain.cqe.done = mlx5_ib_drain_qp_done;
6145 init_completion(&sdrain.done);
6147 ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true);
6149 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
6153 handle_drain_completion(cq, &sdrain, dev);
6156 void mlx5_ib_drain_rq(struct ib_qp *qp)
6158 struct ib_cq *cq = qp->recv_cq;
6159 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
6160 struct mlx5_ib_drain_cqe rdrain;
6161 struct ib_recv_wr rwr = {};
6162 const struct ib_recv_wr *bad_rwr;
6164 struct mlx5_ib_dev *dev = to_mdev(qp->device);
6165 struct mlx5_core_dev *mdev = dev->mdev;
6167 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
6168 if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
6169 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6173 rwr.wr_cqe = &rdrain.cqe;
6174 rdrain.cqe.done = mlx5_ib_drain_qp_done;
6175 init_completion(&rdrain.done);
6177 ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true);
6179 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
6183 handle_drain_completion(cq, &rdrain, dev);