2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/kref.h>
35 #include <linux/random.h>
36 #include <linux/debugfs.h>
37 #include <linux/export.h>
38 #include <linux/delay.h>
39 #include <rdma/ib_umem.h>
40 #include <rdma/ib_umem_odp.h>
41 #include <rdma/ib_verbs.h>
45 MAX_PENDING_REG_MR = 8,
48 #define MLX5_UMR_ALIGN 2048
50 static int clean_mr(struct mlx5_ib_mr *mr);
51 static int use_umr(struct mlx5_ib_dev *dev, int order);
52 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
54 static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
56 int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey);
58 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
59 /* Wait until all page fault handlers using the mr complete. */
60 synchronize_srcu(&dev->mr_srcu);
66 static int order2idx(struct mlx5_ib_dev *dev, int order)
68 struct mlx5_mr_cache *cache = &dev->cache;
70 if (order < cache->ent[0].order)
73 return order - cache->ent[0].order;
76 static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length)
78 return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >=
79 length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1));
82 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
83 static void update_odp_mr(struct mlx5_ib_mr *mr)
85 if (mr->umem->odp_data) {
87 * This barrier prevents the compiler from moving the
88 * setting of umem->odp_data->private to point to our
89 * MR, before reg_umr finished, to ensure that the MR
90 * initialization have finished before starting to
91 * handle invalidations.
94 mr->umem->odp_data->private = mr;
96 * Make sure we will see the new
97 * umem->odp_data->private value in the invalidation
98 * routines, before we can get page faults on the
99 * MR. Page faults can happen once we put the MR in
100 * the tree, below this line. Without the barrier,
101 * there can be a fault handling and an invalidation
102 * before umem->odp_data->private == mr is visible to
103 * the invalidation handler.
110 static void reg_mr_callback(int status, void *context)
112 struct mlx5_ib_mr *mr = context;
113 struct mlx5_ib_dev *dev = mr->dev;
114 struct mlx5_mr_cache *cache = &dev->cache;
115 int c = order2idx(dev, mr->order);
116 struct mlx5_cache_ent *ent = &cache->ent[c];
119 struct mlx5_mkey_table *table = &dev->mdev->priv.mkey_table;
122 spin_lock_irqsave(&ent->lock, flags);
124 spin_unlock_irqrestore(&ent->lock, flags);
126 mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status);
129 mod_timer(&dev->delay_timer, jiffies + HZ);
133 mr->mmkey.type = MLX5_MKEY_MR;
134 spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags);
135 key = dev->mdev->priv.mkey_key++;
136 spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags);
137 mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key;
139 cache->last_add = jiffies;
141 spin_lock_irqsave(&ent->lock, flags);
142 list_add_tail(&mr->list, &ent->head);
145 spin_unlock_irqrestore(&ent->lock, flags);
147 write_lock_irqsave(&table->lock, flags);
148 err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmkey.key),
151 pr_err("Error inserting to mkey tree. 0x%x\n", -err);
152 write_unlock_irqrestore(&table->lock, flags);
154 if (!completion_done(&ent->compl))
155 complete(&ent->compl);
158 static int add_keys(struct mlx5_ib_dev *dev, int c, int num)
160 struct mlx5_mr_cache *cache = &dev->cache;
161 struct mlx5_cache_ent *ent = &cache->ent[c];
162 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
163 struct mlx5_ib_mr *mr;
169 in = kzalloc(inlen, GFP_KERNEL);
173 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
174 for (i = 0; i < num; i++) {
175 if (ent->pending >= MAX_PENDING_REG_MR) {
180 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
185 mr->order = ent->order;
189 MLX5_SET(mkc, mkc, free, 1);
190 MLX5_SET(mkc, mkc, umr_en, 1);
191 MLX5_SET(mkc, mkc, access_mode, ent->access_mode);
193 MLX5_SET(mkc, mkc, qpn, 0xffffff);
194 MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt);
195 MLX5_SET(mkc, mkc, log_page_size, ent->page);
197 spin_lock_irq(&ent->lock);
199 spin_unlock_irq(&ent->lock);
200 err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey,
202 mr->out, sizeof(mr->out),
203 reg_mr_callback, mr);
205 spin_lock_irq(&ent->lock);
207 spin_unlock_irq(&ent->lock);
208 mlx5_ib_warn(dev, "create mkey failed %d\n", err);
218 static void remove_keys(struct mlx5_ib_dev *dev, int c, int num)
220 struct mlx5_mr_cache *cache = &dev->cache;
221 struct mlx5_cache_ent *ent = &cache->ent[c];
222 struct mlx5_ib_mr *mr;
226 for (i = 0; i < num; i++) {
227 spin_lock_irq(&ent->lock);
228 if (list_empty(&ent->head)) {
229 spin_unlock_irq(&ent->lock);
232 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
236 spin_unlock_irq(&ent->lock);
237 err = destroy_mkey(dev, mr);
239 mlx5_ib_warn(dev, "failed destroy mkey\n");
245 static ssize_t size_write(struct file *filp, const char __user *buf,
246 size_t count, loff_t *pos)
248 struct mlx5_cache_ent *ent = filp->private_data;
249 struct mlx5_ib_dev *dev = ent->dev;
255 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
258 c = order2idx(dev, ent->order);
259 lbuf[sizeof(lbuf) - 1] = 0;
261 if (sscanf(lbuf, "%u", &var) != 1)
264 if (var < ent->limit)
267 if (var > ent->size) {
269 err = add_keys(dev, c, var - ent->size);
270 if (err && err != -EAGAIN)
273 usleep_range(3000, 5000);
275 } else if (var < ent->size) {
276 remove_keys(dev, c, ent->size - var);
282 static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
285 struct mlx5_cache_ent *ent = filp->private_data;
292 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size);
296 if (copy_to_user(buf, lbuf, err))
304 static const struct file_operations size_fops = {
305 .owner = THIS_MODULE,
311 static ssize_t limit_write(struct file *filp, const char __user *buf,
312 size_t count, loff_t *pos)
314 struct mlx5_cache_ent *ent = filp->private_data;
315 struct mlx5_ib_dev *dev = ent->dev;
321 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
324 c = order2idx(dev, ent->order);
325 lbuf[sizeof(lbuf) - 1] = 0;
327 if (sscanf(lbuf, "%u", &var) != 1)
335 if (ent->cur < ent->limit) {
336 err = add_keys(dev, c, 2 * ent->limit - ent->cur);
344 static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
347 struct mlx5_cache_ent *ent = filp->private_data;
354 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
358 if (copy_to_user(buf, lbuf, err))
366 static const struct file_operations limit_fops = {
367 .owner = THIS_MODULE,
369 .write = limit_write,
373 static int someone_adding(struct mlx5_mr_cache *cache)
377 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
378 if (cache->ent[i].cur < cache->ent[i].limit)
385 static void __cache_work_func(struct mlx5_cache_ent *ent)
387 struct mlx5_ib_dev *dev = ent->dev;
388 struct mlx5_mr_cache *cache = &dev->cache;
389 int i = order2idx(dev, ent->order);
395 ent = &dev->cache.ent[i];
396 if (ent->cur < 2 * ent->limit && !dev->fill_delay) {
397 err = add_keys(dev, i, 1);
398 if (ent->cur < 2 * ent->limit) {
399 if (err == -EAGAIN) {
400 mlx5_ib_dbg(dev, "returned eagain, order %d\n",
402 queue_delayed_work(cache->wq, &ent->dwork,
403 msecs_to_jiffies(3));
405 mlx5_ib_warn(dev, "command failed order %d, err %d\n",
407 queue_delayed_work(cache->wq, &ent->dwork,
408 msecs_to_jiffies(1000));
410 queue_work(cache->wq, &ent->work);
413 } else if (ent->cur > 2 * ent->limit) {
415 * The remove_keys() logic is performed as garbage collection
416 * task. Such task is intended to be run when no other active
417 * processes are running.
419 * The need_resched() will return TRUE if there are user tasks
420 * to be activated in near future.
422 * In such case, we don't execute remove_keys() and postpone
423 * the garbage collection work to try to run in next cycle,
424 * in order to free CPU resources to other tasks.
426 if (!need_resched() && !someone_adding(cache) &&
427 time_after(jiffies, cache->last_add + 300 * HZ)) {
428 remove_keys(dev, i, 1);
429 if (ent->cur > ent->limit)
430 queue_work(cache->wq, &ent->work);
432 queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ);
437 static void delayed_cache_work_func(struct work_struct *work)
439 struct mlx5_cache_ent *ent;
441 ent = container_of(work, struct mlx5_cache_ent, dwork.work);
442 __cache_work_func(ent);
445 static void cache_work_func(struct work_struct *work)
447 struct mlx5_cache_ent *ent;
449 ent = container_of(work, struct mlx5_cache_ent, work);
450 __cache_work_func(ent);
453 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry)
455 struct mlx5_mr_cache *cache = &dev->cache;
456 struct mlx5_cache_ent *ent;
457 struct mlx5_ib_mr *mr;
460 if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) {
461 mlx5_ib_err(dev, "cache entry %d is out of range\n", entry);
465 ent = &cache->ent[entry];
467 spin_lock_irq(&ent->lock);
468 if (list_empty(&ent->head)) {
469 spin_unlock_irq(&ent->lock);
471 err = add_keys(dev, entry, 1);
472 if (err && err != -EAGAIN)
475 wait_for_completion(&ent->compl);
477 mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
481 spin_unlock_irq(&ent->lock);
482 if (ent->cur < ent->limit)
483 queue_work(cache->wq, &ent->work);
489 static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
491 struct mlx5_mr_cache *cache = &dev->cache;
492 struct mlx5_ib_mr *mr = NULL;
493 struct mlx5_cache_ent *ent;
497 c = order2idx(dev, order);
498 if (c < 0 || c > MAX_UMR_CACHE_ENTRY) {
499 mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
503 for (i = c; i < MAX_UMR_CACHE_ENTRY; i++) {
504 ent = &cache->ent[i];
506 mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
508 spin_lock_irq(&ent->lock);
509 if (!list_empty(&ent->head)) {
510 mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
514 spin_unlock_irq(&ent->lock);
515 if (ent->cur < ent->limit)
516 queue_work(cache->wq, &ent->work);
519 spin_unlock_irq(&ent->lock);
521 queue_work(cache->wq, &ent->work);
525 cache->ent[c].miss++;
530 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
532 struct mlx5_mr_cache *cache = &dev->cache;
533 struct mlx5_cache_ent *ent;
537 c = order2idx(dev, mr->order);
538 if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
539 mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c);
543 if (unreg_umr(dev, mr))
546 ent = &cache->ent[c];
547 spin_lock_irq(&ent->lock);
548 list_add_tail(&mr->list, &ent->head);
550 if (ent->cur > 2 * ent->limit)
552 spin_unlock_irq(&ent->lock);
555 queue_work(cache->wq, &ent->work);
558 static void clean_keys(struct mlx5_ib_dev *dev, int c)
560 struct mlx5_mr_cache *cache = &dev->cache;
561 struct mlx5_cache_ent *ent = &cache->ent[c];
562 struct mlx5_ib_mr *mr;
565 cancel_delayed_work(&ent->dwork);
567 spin_lock_irq(&ent->lock);
568 if (list_empty(&ent->head)) {
569 spin_unlock_irq(&ent->lock);
572 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
576 spin_unlock_irq(&ent->lock);
577 err = destroy_mkey(dev, mr);
579 mlx5_ib_warn(dev, "failed destroy mkey\n");
585 static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
587 if (!mlx5_debugfs_root)
590 debugfs_remove_recursive(dev->cache.root);
591 dev->cache.root = NULL;
594 static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev)
596 struct mlx5_mr_cache *cache = &dev->cache;
597 struct mlx5_cache_ent *ent;
600 if (!mlx5_debugfs_root)
603 cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root);
607 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
608 ent = &cache->ent[i];
609 sprintf(ent->name, "%d", ent->order);
610 ent->dir = debugfs_create_dir(ent->name, cache->root);
614 ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent,
619 ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent,
624 ent->fcur = debugfs_create_u32("cur", 0400, ent->dir,
629 ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir,
637 mlx5_mr_cache_debugfs_cleanup(dev);
642 static void delay_time_func(unsigned long ctx)
644 struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx;
649 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
651 struct mlx5_mr_cache *cache = &dev->cache;
652 struct mlx5_cache_ent *ent;
656 mutex_init(&dev->slow_path_mutex);
657 cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM);
659 mlx5_ib_warn(dev, "failed to create work queue\n");
663 setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev);
664 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
665 ent = &cache->ent[i];
666 INIT_LIST_HEAD(&ent->head);
667 spin_lock_init(&ent->lock);
672 init_completion(&ent->compl);
673 INIT_WORK(&ent->work, cache_work_func);
674 INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
675 queue_work(cache->wq, &ent->work);
677 if (i > MAX_UMR_CACHE_ENTRY) {
678 mlx5_odp_init_mr_cache_entry(ent);
682 if (!use_umr(dev, ent->order))
685 ent->page = PAGE_SHIFT;
686 ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) /
687 MLX5_IB_UMR_OCTOWORD;
688 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
689 if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) &&
690 mlx5_core_is_pf(dev->mdev))
691 ent->limit = dev->mdev->profile->mr_cache[i].limit;
696 err = mlx5_mr_cache_debugfs_init(dev);
698 mlx5_ib_warn(dev, "cache debugfs failure\n");
701 * We don't want to fail driver if debugfs failed to initialize,
702 * so we are not forwarding error to the user.
708 static void wait_for_async_commands(struct mlx5_ib_dev *dev)
710 struct mlx5_mr_cache *cache = &dev->cache;
711 struct mlx5_cache_ent *ent;
716 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
717 ent = &cache->ent[i];
718 for (j = 0 ; j < 1000; j++) {
724 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
725 ent = &cache->ent[i];
726 total += ent->pending;
730 mlx5_ib_warn(dev, "aborted while there are %d pending mr requests\n", total);
732 mlx5_ib_warn(dev, "done with all pending requests\n");
735 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
739 dev->cache.stopped = 1;
740 flush_workqueue(dev->cache.wq);
742 mlx5_mr_cache_debugfs_cleanup(dev);
744 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++)
747 destroy_workqueue(dev->cache.wq);
748 wait_for_async_commands(dev);
749 del_timer_sync(&dev->delay_timer);
754 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
756 struct mlx5_ib_dev *dev = to_mdev(pd->device);
757 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
758 struct mlx5_core_dev *mdev = dev->mdev;
759 struct mlx5_ib_mr *mr;
764 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
766 return ERR_PTR(-ENOMEM);
768 in = kzalloc(inlen, GFP_KERNEL);
774 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
776 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_PA);
777 MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC));
778 MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE));
779 MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ));
780 MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE));
781 MLX5_SET(mkc, mkc, lr, 1);
783 MLX5_SET(mkc, mkc, length64, 1);
784 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
785 MLX5_SET(mkc, mkc, qpn, 0xffffff);
786 MLX5_SET64(mkc, mkc, start_addr, 0);
788 err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen);
793 mr->mmkey.type = MLX5_MKEY_MR;
794 mr->ibmr.lkey = mr->mmkey.key;
795 mr->ibmr.rkey = mr->mmkey.key;
809 static int get_octo_len(u64 addr, u64 len, int page_size)
814 offset = addr & (page_size - 1);
815 npages = ALIGN(len + offset, page_size) >> ilog2(page_size);
816 return (npages + 1) / 2;
819 static int use_umr(struct mlx5_ib_dev *dev, int order)
821 if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
822 return order <= MAX_UMR_CACHE_ENTRY + 2;
823 return order <= MLX5_MAX_UMR_SHIFT;
826 static int mr_umem_get(struct ib_pd *pd, u64 start, u64 length,
827 int access_flags, struct ib_umem **umem,
828 int *npages, int *page_shift, int *ncont,
831 struct mlx5_ib_dev *dev = to_mdev(pd->device);
834 *umem = ib_umem_get(pd->uobject->context, start, length,
836 err = PTR_ERR_OR_ZERO(*umem);
838 mlx5_ib_err(dev, "umem get failed (%d)\n", err);
842 mlx5_ib_cont_pages(*umem, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages,
843 page_shift, ncont, order);
845 mlx5_ib_warn(dev, "avoid zero region\n");
846 ib_umem_release(*umem);
850 mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
851 *npages, *ncont, *order, *page_shift);
856 static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc)
858 struct mlx5_ib_umr_context *context =
859 container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe);
861 context->status = wc->status;
862 complete(&context->done);
865 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
867 context->cqe.done = mlx5_ib_umr_done;
868 context->status = -1;
869 init_completion(&context->done);
872 static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev,
873 struct mlx5_umr_wr *umrwr)
875 struct umr_common *umrc = &dev->umrc;
876 struct ib_send_wr *bad;
878 struct mlx5_ib_umr_context umr_context;
880 mlx5_ib_init_umr_context(&umr_context);
881 umrwr->wr.wr_cqe = &umr_context.cqe;
884 err = ib_post_send(umrc->qp, &umrwr->wr, &bad);
886 mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err);
888 wait_for_completion(&umr_context.done);
889 if (umr_context.status != IB_WC_SUCCESS) {
890 mlx5_ib_warn(dev, "reg umr failed (%u)\n",
899 static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem,
900 u64 virt_addr, u64 len, int npages,
901 int page_shift, int order, int access_flags)
903 struct mlx5_ib_dev *dev = to_mdev(pd->device);
904 struct mlx5_ib_mr *mr;
908 for (i = 0; i < 1; i++) {
909 mr = alloc_cached_mr(dev, order);
913 err = add_keys(dev, order2idx(dev, order), 1);
914 if (err && err != -EAGAIN) {
915 mlx5_ib_warn(dev, "add_keys failed, err %d\n", err);
921 return ERR_PTR(-EAGAIN);
925 mr->access_flags = access_flags;
926 mr->desc_size = sizeof(struct mlx5_mtt);
927 mr->mmkey.iova = virt_addr;
928 mr->mmkey.size = len;
929 mr->mmkey.pd = to_mpd(pd)->pdn;
931 err = mlx5_ib_update_xlt(mr, 0, npages, page_shift,
932 MLX5_IB_UPD_XLT_ENABLE);
935 mlx5_mr_cache_free(dev, mr);
944 static inline int populate_xlt(struct mlx5_ib_mr *mr, int idx, int npages,
945 void *xlt, int page_shift, size_t size,
948 struct mlx5_ib_dev *dev = mr->dev;
949 struct ib_umem *umem = mr->umem;
950 if (flags & MLX5_IB_UPD_XLT_INDIRECT) {
951 mlx5_odp_populate_klm(xlt, idx, npages, mr, flags);
955 npages = min_t(size_t, npages, ib_umem_num_pages(umem) - idx);
957 if (!(flags & MLX5_IB_UPD_XLT_ZAP)) {
958 __mlx5_ib_populate_pas(dev, umem, page_shift,
960 MLX5_IB_MTT_PRESENT);
961 /* Clear padding after the pages
962 * brought from the umem.
964 memset(xlt + (npages * sizeof(struct mlx5_mtt)), 0,
965 size - npages * sizeof(struct mlx5_mtt));
971 #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \
972 MLX5_UMR_MTT_ALIGNMENT)
973 #define MLX5_SPARE_UMR_CHUNK 0x10000
975 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
976 int page_shift, int flags)
978 struct mlx5_ib_dev *dev = mr->dev;
979 struct device *ddev = dev->ib_dev.dev.parent;
980 struct mlx5_ib_ucontext *uctx = NULL;
984 struct mlx5_umr_wr wr;
987 int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT)
988 ? sizeof(struct mlx5_klm)
989 : sizeof(struct mlx5_mtt);
990 const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size;
991 const int page_mask = page_align - 1;
992 size_t pages_mapped = 0;
993 size_t pages_to_map = 0;
994 size_t pages_iter = 0;
997 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes,
998 * so we need to align the offset and length accordingly
1000 if (idx & page_mask) {
1001 npages += idx & page_mask;
1005 gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL;
1006 gfp |= __GFP_ZERO | __GFP_NOWARN;
1008 pages_to_map = ALIGN(npages, page_align);
1009 size = desc_size * pages_to_map;
1010 size = min_t(int, size, MLX5_MAX_UMR_CHUNK);
1012 xlt = (void *)__get_free_pages(gfp, get_order(size));
1013 if (!xlt && size > MLX5_SPARE_UMR_CHUNK) {
1014 mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n",
1015 size, get_order(size), MLX5_SPARE_UMR_CHUNK);
1017 size = MLX5_SPARE_UMR_CHUNK;
1018 xlt = (void *)__get_free_pages(gfp, get_order(size));
1022 uctx = to_mucontext(mr->ibmr.pd->uobject->context);
1023 mlx5_ib_warn(dev, "Using XLT emergency buffer\n");
1025 xlt = (void *)uctx->upd_xlt_page;
1026 mutex_lock(&uctx->upd_xlt_page_mutex);
1027 memset(xlt, 0, size);
1029 pages_iter = size / desc_size;
1030 dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE);
1031 if (dma_mapping_error(ddev, dma)) {
1032 mlx5_ib_err(dev, "unable to map DMA during XLT update.\n");
1038 sg.lkey = dev->umrc.pd->local_dma_lkey;
1040 memset(&wr, 0, sizeof(wr));
1041 wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT;
1042 if (!(flags & MLX5_IB_UPD_XLT_ENABLE))
1043 wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE;
1044 wr.wr.sg_list = &sg;
1046 wr.wr.opcode = MLX5_IB_WR_UMR;
1048 wr.pd = mr->ibmr.pd;
1049 wr.mkey = mr->mmkey.key;
1050 wr.length = mr->mmkey.size;
1051 wr.virt_addr = mr->mmkey.iova;
1052 wr.access_flags = mr->access_flags;
1053 wr.page_shift = page_shift;
1055 for (pages_mapped = 0;
1056 pages_mapped < pages_to_map && !err;
1057 pages_mapped += pages_iter, idx += pages_iter) {
1058 npages = min_t(int, pages_iter, pages_to_map - pages_mapped);
1059 dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE);
1060 npages = populate_xlt(mr, idx, npages, xlt,
1061 page_shift, size, flags);
1063 dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE);
1065 sg.length = ALIGN(npages * desc_size,
1066 MLX5_UMR_MTT_ALIGNMENT);
1068 if (pages_mapped + pages_iter >= pages_to_map) {
1069 if (flags & MLX5_IB_UPD_XLT_ENABLE)
1071 MLX5_IB_SEND_UMR_ENABLE_MR |
1072 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS |
1073 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
1074 if (flags & MLX5_IB_UPD_XLT_PD ||
1075 flags & MLX5_IB_UPD_XLT_ACCESS)
1077 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1078 if (flags & MLX5_IB_UPD_XLT_ADDR)
1080 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
1083 wr.offset = idx * desc_size;
1084 wr.xlt_size = sg.length;
1086 err = mlx5_ib_post_send_wait(dev, &wr);
1088 dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE);
1092 mutex_unlock(&uctx->upd_xlt_page_mutex);
1094 free_pages((unsigned long)xlt, get_order(size));
1100 * If ibmr is NULL it will be allocated by reg_create.
1101 * Else, the given ibmr will be used.
1103 static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd,
1104 u64 virt_addr, u64 length,
1105 struct ib_umem *umem, int npages,
1106 int page_shift, int access_flags)
1108 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1109 struct mlx5_ib_mr *mr;
1115 bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg));
1117 mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL);
1119 return ERR_PTR(-ENOMEM);
1121 inlen = MLX5_ST_SZ_BYTES(create_mkey_in) +
1122 sizeof(*pas) * ((npages + 1) / 2) * 2;
1123 in = kvzalloc(inlen, GFP_KERNEL);
1128 pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
1129 if (!(access_flags & IB_ACCESS_ON_DEMAND))
1130 mlx5_ib_populate_pas(dev, umem, page_shift, pas,
1131 pg_cap ? MLX5_IB_MTT_PRESENT : 0);
1133 /* The pg_access bit allows setting the access flags
1134 * in the page list submitted with the command. */
1135 MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap));
1137 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1138 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
1139 MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
1140 MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
1141 MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ));
1142 MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE));
1143 MLX5_SET(mkc, mkc, lr, 1);
1145 MLX5_SET64(mkc, mkc, start_addr, virt_addr);
1146 MLX5_SET64(mkc, mkc, len, length);
1147 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1148 MLX5_SET(mkc, mkc, bsf_octword_size, 0);
1149 MLX5_SET(mkc, mkc, translations_octword_size,
1150 get_octo_len(virt_addr, length, 1 << page_shift));
1151 MLX5_SET(mkc, mkc, log_page_size, page_shift);
1152 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1153 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
1154 get_octo_len(virt_addr, length, 1 << page_shift));
1156 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen);
1158 mlx5_ib_warn(dev, "create mkey failed\n");
1161 mr->mmkey.type = MLX5_MKEY_MR;
1162 mr->desc_size = sizeof(struct mlx5_mtt);
1168 mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key);
1179 return ERR_PTR(err);
1182 static void set_mr_fileds(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr,
1183 int npages, u64 length, int access_flags)
1185 mr->npages = npages;
1186 atomic_add(npages, &dev->mdev->priv.reg_pages);
1187 mr->ibmr.lkey = mr->mmkey.key;
1188 mr->ibmr.rkey = mr->mmkey.key;
1189 mr->ibmr.length = length;
1190 mr->access_flags = access_flags;
1193 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1194 u64 virt_addr, int access_flags,
1195 struct ib_udata *udata)
1197 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1198 struct mlx5_ib_mr *mr = NULL;
1199 struct ib_umem *umem;
1206 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
1207 start, virt_addr, length, access_flags);
1209 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1210 if (!start && length == U64_MAX) {
1211 if (!(access_flags & IB_ACCESS_ON_DEMAND) ||
1212 !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT))
1213 return ERR_PTR(-EINVAL);
1215 mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), access_flags);
1220 err = mr_umem_get(pd, start, length, access_flags, &umem, &npages,
1221 &page_shift, &ncont, &order);
1224 return ERR_PTR(err);
1226 if (use_umr(dev, order)) {
1227 mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift,
1228 order, access_flags);
1229 if (PTR_ERR(mr) == -EAGAIN) {
1230 mlx5_ib_dbg(dev, "cache empty for order %d", order);
1233 } else if (access_flags & IB_ACCESS_ON_DEMAND &&
1234 !MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) {
1236 pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB");
1241 mutex_lock(&dev->slow_path_mutex);
1242 mr = reg_create(NULL, pd, virt_addr, length, umem, ncont,
1243 page_shift, access_flags);
1244 mutex_unlock(&dev->slow_path_mutex);
1252 mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key);
1255 set_mr_fileds(dev, mr, npages, length, access_flags);
1257 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1264 ib_umem_release(umem);
1265 return ERR_PTR(err);
1268 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
1270 struct mlx5_core_dev *mdev = dev->mdev;
1271 struct mlx5_umr_wr umrwr = {};
1273 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
1276 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR |
1277 MLX5_IB_SEND_UMR_FAIL_IF_FREE;
1278 umrwr.wr.opcode = MLX5_IB_WR_UMR;
1279 umrwr.mkey = mr->mmkey.key;
1281 return mlx5_ib_post_send_wait(dev, &umrwr);
1284 static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1285 int access_flags, int flags)
1287 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1288 struct mlx5_umr_wr umrwr = {};
1291 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE;
1293 umrwr.wr.opcode = MLX5_IB_WR_UMR;
1294 umrwr.mkey = mr->mmkey.key;
1296 if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) {
1298 umrwr.access_flags = access_flags;
1299 umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1302 err = mlx5_ib_post_send_wait(dev, &umrwr);
1307 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1308 u64 length, u64 virt_addr, int new_access_flags,
1309 struct ib_pd *new_pd, struct ib_udata *udata)
1311 struct mlx5_ib_dev *dev = to_mdev(ib_mr->device);
1312 struct mlx5_ib_mr *mr = to_mmr(ib_mr);
1313 struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd;
1314 int access_flags = flags & IB_MR_REREG_ACCESS ?
1317 u64 addr = (flags & IB_MR_REREG_TRANS) ? virt_addr : mr->umem->address;
1318 u64 len = (flags & IB_MR_REREG_TRANS) ? length : mr->umem->length;
1326 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
1327 start, virt_addr, length, access_flags);
1329 atomic_sub(mr->npages, &dev->mdev->priv.reg_pages);
1331 if (flags != IB_MR_REREG_PD) {
1333 * Replace umem. This needs to be done whether or not UMR is
1336 flags |= IB_MR_REREG_TRANS;
1337 ib_umem_release(mr->umem);
1338 err = mr_umem_get(pd, addr, len, access_flags, &mr->umem,
1339 &npages, &page_shift, &ncont, &order);
1346 if (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len)) {
1348 * UMR can't be used - MKey needs to be replaced.
1351 err = unreg_umr(dev, mr);
1353 mlx5_ib_warn(dev, "Failed to unregister MR\n");
1355 err = destroy_mkey(dev, mr);
1357 mlx5_ib_warn(dev, "Failed to destroy MKey\n");
1362 mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont,
1363 page_shift, access_flags);
1374 mr->access_flags = access_flags;
1375 mr->mmkey.iova = addr;
1376 mr->mmkey.size = len;
1377 mr->mmkey.pd = to_mpd(pd)->pdn;
1379 if (flags & IB_MR_REREG_TRANS) {
1380 upd_flags = MLX5_IB_UPD_XLT_ADDR;
1381 if (flags & IB_MR_REREG_PD)
1382 upd_flags |= MLX5_IB_UPD_XLT_PD;
1383 if (flags & IB_MR_REREG_ACCESS)
1384 upd_flags |= MLX5_IB_UPD_XLT_ACCESS;
1385 err = mlx5_ib_update_xlt(mr, 0, npages, page_shift,
1388 err = rereg_umr(pd, mr, access_flags, flags);
1392 mlx5_ib_warn(dev, "Failed to rereg UMR\n");
1393 ib_umem_release(mr->umem);
1399 set_mr_fileds(dev, mr, npages, len, access_flags);
1401 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1408 mlx5_alloc_priv_descs(struct ib_device *device,
1409 struct mlx5_ib_mr *mr,
1413 int size = ndescs * desc_size;
1417 add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0);
1419 mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL);
1420 if (!mr->descs_alloc)
1423 mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN);
1425 mr->desc_map = dma_map_single(device->dev.parent, mr->descs,
1426 size, DMA_TO_DEVICE);
1427 if (dma_mapping_error(device->dev.parent, mr->desc_map)) {
1434 kfree(mr->descs_alloc);
1440 mlx5_free_priv_descs(struct mlx5_ib_mr *mr)
1443 struct ib_device *device = mr->ibmr.device;
1444 int size = mr->max_descs * mr->desc_size;
1446 dma_unmap_single(device->dev.parent, mr->desc_map,
1447 size, DMA_TO_DEVICE);
1448 kfree(mr->descs_alloc);
1453 static int clean_mr(struct mlx5_ib_mr *mr)
1455 struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.device);
1456 int umred = mr->umred;
1460 if (mlx5_core_destroy_psv(dev->mdev,
1461 mr->sig->psv_memory.psv_idx))
1462 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
1463 mr->sig->psv_memory.psv_idx);
1464 if (mlx5_core_destroy_psv(dev->mdev,
1465 mr->sig->psv_wire.psv_idx))
1466 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
1467 mr->sig->psv_wire.psv_idx);
1472 mlx5_free_priv_descs(mr);
1475 err = destroy_mkey(dev, mr);
1477 mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n",
1478 mr->mmkey.key, err);
1482 mlx5_mr_cache_free(dev, mr);
1491 int mlx5_ib_dereg_mr(struct ib_mr *ibmr)
1493 struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
1494 struct mlx5_ib_mr *mr = to_mmr(ibmr);
1495 int npages = mr->npages;
1496 struct ib_umem *umem = mr->umem;
1498 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1499 if (umem && umem->odp_data) {
1500 /* Prevent new page faults from succeeding */
1502 /* Wait for all running page-fault handlers to finish. */
1503 synchronize_srcu(&dev->mr_srcu);
1504 /* Destroy all page mappings */
1505 if (umem->odp_data->page_list)
1506 mlx5_ib_invalidate_range(umem, ib_umem_start(umem),
1509 mlx5_ib_free_implicit_mr(mr);
1511 * We kill the umem before the MR for ODP,
1512 * so that there will not be any invalidations in
1513 * flight, looking at the *mr struct.
1515 ib_umem_release(umem);
1516 atomic_sub(npages, &dev->mdev->priv.reg_pages);
1518 /* Avoid double-freeing the umem. */
1526 ib_umem_release(umem);
1527 atomic_sub(npages, &dev->mdev->priv.reg_pages);
1533 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
1534 enum ib_mr_type mr_type,
1537 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1538 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1539 int ndescs = ALIGN(max_num_sg, 4);
1540 struct mlx5_ib_mr *mr;
1545 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1547 return ERR_PTR(-ENOMEM);
1549 in = kzalloc(inlen, GFP_KERNEL);
1555 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1556 MLX5_SET(mkc, mkc, free, 1);
1557 MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
1558 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1559 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1561 if (mr_type == IB_MR_TYPE_MEM_REG) {
1562 mr->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
1563 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
1564 err = mlx5_alloc_priv_descs(pd->device, mr,
1565 ndescs, sizeof(struct mlx5_mtt));
1569 mr->desc_size = sizeof(struct mlx5_mtt);
1570 mr->max_descs = ndescs;
1571 } else if (mr_type == IB_MR_TYPE_SG_GAPS) {
1572 mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS;
1574 err = mlx5_alloc_priv_descs(pd->device, mr,
1575 ndescs, sizeof(struct mlx5_klm));
1578 mr->desc_size = sizeof(struct mlx5_klm);
1579 mr->max_descs = ndescs;
1580 } else if (mr_type == IB_MR_TYPE_SIGNATURE) {
1583 MLX5_SET(mkc, mkc, bsf_en, 1);
1584 MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE);
1585 mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL);
1591 /* create mem & wire PSVs */
1592 err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn,
1597 mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS;
1598 mr->sig->psv_memory.psv_idx = psv_index[0];
1599 mr->sig->psv_wire.psv_idx = psv_index[1];
1601 mr->sig->sig_status_checked = true;
1602 mr->sig->sig_err_exists = false;
1603 /* Next UMR, Arm SIGERR */
1604 ++mr->sig->sigerr_count;
1606 mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type);
1611 MLX5_SET(mkc, mkc, access_mode, mr->access_mode);
1612 MLX5_SET(mkc, mkc, umr_en, 1);
1614 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen);
1616 goto err_destroy_psv;
1618 mr->mmkey.type = MLX5_MKEY_MR;
1619 mr->ibmr.lkey = mr->mmkey.key;
1620 mr->ibmr.rkey = mr->mmkey.key;
1628 if (mlx5_core_destroy_psv(dev->mdev,
1629 mr->sig->psv_memory.psv_idx))
1630 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
1631 mr->sig->psv_memory.psv_idx);
1632 if (mlx5_core_destroy_psv(dev->mdev,
1633 mr->sig->psv_wire.psv_idx))
1634 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
1635 mr->sig->psv_wire.psv_idx);
1637 mlx5_free_priv_descs(mr);
1644 return ERR_PTR(err);
1647 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1648 struct ib_udata *udata)
1650 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1651 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1652 struct mlx5_ib_mw *mw = NULL;
1657 struct mlx5_ib_alloc_mw req = {};
1660 __u32 response_length;
1663 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1665 return ERR_PTR(err);
1667 if (req.comp_mask || req.reserved1 || req.reserved2)
1668 return ERR_PTR(-EOPNOTSUPP);
1670 if (udata->inlen > sizeof(req) &&
1671 !ib_is_udata_cleared(udata, sizeof(req),
1672 udata->inlen - sizeof(req)))
1673 return ERR_PTR(-EOPNOTSUPP);
1675 ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4);
1677 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
1678 in = kzalloc(inlen, GFP_KERNEL);
1684 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1686 MLX5_SET(mkc, mkc, free, 1);
1687 MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
1688 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1689 MLX5_SET(mkc, mkc, umr_en, 1);
1690 MLX5_SET(mkc, mkc, lr, 1);
1691 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_KLMS);
1692 MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2)));
1693 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1695 err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen);
1699 mw->mmkey.type = MLX5_MKEY_MW;
1700 mw->ibmw.rkey = mw->mmkey.key;
1701 mw->ndescs = ndescs;
1703 resp.response_length = min(offsetof(typeof(resp), response_length) +
1704 sizeof(resp.response_length), udata->outlen);
1705 if (resp.response_length) {
1706 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1708 mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey);
1719 return ERR_PTR(err);
1722 int mlx5_ib_dealloc_mw(struct ib_mw *mw)
1724 struct mlx5_ib_mw *mmw = to_mmw(mw);
1727 err = mlx5_core_destroy_mkey((to_mdev(mw->device))->mdev,
1734 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1735 struct ib_mr_status *mr_status)
1737 struct mlx5_ib_mr *mmr = to_mmr(ibmr);
1740 if (check_mask & ~IB_MR_CHECK_SIG_STATUS) {
1741 pr_err("Invalid status check mask\n");
1746 mr_status->fail_status = 0;
1747 if (check_mask & IB_MR_CHECK_SIG_STATUS) {
1750 pr_err("signature status check requested on a non-signature enabled MR\n");
1754 mmr->sig->sig_status_checked = true;
1755 if (!mmr->sig->sig_err_exists)
1758 if (ibmr->lkey == mmr->sig->err_item.key)
1759 memcpy(&mr_status->sig_err, &mmr->sig->err_item,
1760 sizeof(mr_status->sig_err));
1762 mr_status->sig_err.err_type = IB_SIG_BAD_GUARD;
1763 mr_status->sig_err.sig_err_offset = 0;
1764 mr_status->sig_err.key = mmr->sig->err_item.key;
1767 mmr->sig->sig_err_exists = false;
1768 mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS;
1776 mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr,
1777 struct scatterlist *sgl,
1778 unsigned short sg_nents,
1779 unsigned int *sg_offset_p)
1781 struct scatterlist *sg = sgl;
1782 struct mlx5_klm *klms = mr->descs;
1783 unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0;
1784 u32 lkey = mr->ibmr.pd->local_dma_lkey;
1787 mr->ibmr.iova = sg_dma_address(sg) + sg_offset;
1788 mr->ibmr.length = 0;
1789 mr->ndescs = sg_nents;
1791 for_each_sg(sgl, sg, sg_nents, i) {
1792 if (unlikely(i >= mr->max_descs))
1794 klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset);
1795 klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset);
1796 klms[i].key = cpu_to_be32(lkey);
1797 mr->ibmr.length += sg_dma_len(sg) - sg_offset;
1803 *sg_offset_p = sg_offset;
1808 static int mlx5_set_page(struct ib_mr *ibmr, u64 addr)
1810 struct mlx5_ib_mr *mr = to_mmr(ibmr);
1813 if (unlikely(mr->ndescs == mr->max_descs))
1817 descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR);
1822 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1823 unsigned int *sg_offset)
1825 struct mlx5_ib_mr *mr = to_mmr(ibmr);
1830 ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map,
1831 mr->desc_size * mr->max_descs,
1834 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
1835 n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset);
1837 n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset,
1840 ib_dma_sync_single_for_device(ibmr->device, mr->desc_map,
1841 mr->desc_size * mr->max_descs,