drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #if defined(CONFIG_X86)
  42 #include <asm/pat.h>
  43 #endif
  44 #include <linux/sched.h>
  45 #include <linux/sched/mm.h>
  46 #include <linux/sched/task.h>
  47 #include <linux/delay.h>
  48 #include <rdma/ib_user_verbs.h>
  49 #include <rdma/ib_addr.h>
  50 #include <rdma/ib_cache.h>
  51 #include <linux/mlx5/port.h>
  52 #include <linux/mlx5/vport.h>
  53 #include <linux/mlx5/fs.h>
  54 #include <linux/list.h>
  55 #include <rdma/ib_smi.h>
  56 #include <rdma/ib_umem.h>
  57 #include <linux/in.h>
  58 #include <linux/etherdevice.h>
  59 #include "mlx5_ib.h"
  60 #include "cmd.h"
  61
  62 #define DRIVER_NAME "mlx5_ib"
  63 #define DRIVER_VERSION "5.0-0"
  64
  65 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  66 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  67 MODULE_LICENSE("Dual BSD/GPL");
  68
  69 static char mlx5_version[] =
  70         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  71         DRIVER_VERSION "\n";
  72
  73 struct mlx5_ib_event_work {
  74         struct work_struct      work;
  75         struct mlx5_core_dev    *dev;
  76         void                    *context;
  77         enum mlx5_dev_event     event;
  78         unsigned long           param;
  79 };
  80
  81 enum {
  82         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  83 };
  84
  85 static struct workqueue_struct *mlx5_ib_event_wq;
  86 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  87 static LIST_HEAD(mlx5_ib_dev_list);
  88 /*
  89  * This mutex should be held when accessing either of the above lists
  90  */
  91 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
  92
  93 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
  94 {
  95         struct mlx5_ib_dev *dev;
  96
  97         mutex_lock(&mlx5_ib_multiport_mutex);
  98         dev = mpi->ibdev;
  99         mutex_unlock(&mlx5_ib_multiport_mutex);
 100         return dev;
 101 }
 102
 103 static enum rdma_link_layer
 104 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 105 {
 106         switch (port_type_cap) {
 107         case MLX5_CAP_PORT_TYPE_IB:
 108                 return IB_LINK_LAYER_INFINIBAND;
 109         case MLX5_CAP_PORT_TYPE_ETH:
 110                 return IB_LINK_LAYER_ETHERNET;
 111         default:
 112                 return IB_LINK_LAYER_UNSPECIFIED;
 113         }
 114 }
 115
 116 static enum rdma_link_layer
 117 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 118 {
 119         struct mlx5_ib_dev *dev = to_mdev(device);
 120         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 121
 122         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 123 }
 124
 125 static int get_port_state(struct ib_device *ibdev,
 126                           u8 port_num,
 127                           enum ib_port_state *state)
 128 {
 129         struct ib_port_attr attr;
 130         int ret;
 131
 132         memset(&attr, 0, sizeof(attr));
 133         ret = mlx5_ib_query_port(ibdev, port_num, &attr);
 134         if (!ret)
 135                 *state = attr.state;
 136         return ret;
 137 }
 138
 139 static int mlx5_netdev_event(struct notifier_block *this,
 140                              unsigned long event, void *ptr)
 141 {
 142         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 143         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 144         u8 port_num = roce->native_port_num;
 145         struct mlx5_core_dev *mdev;
 146         struct mlx5_ib_dev *ibdev;
 147
 148         ibdev = roce->dev;
 149         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 150         if (!mdev)
 151                 return NOTIFY_DONE;
 152
 153         switch (event) {
 154         case NETDEV_REGISTER:
 155         case NETDEV_UNREGISTER:
 156                 write_lock(&roce->netdev_lock);
 157
 158                 if (ndev->dev.parent == &mdev->pdev->dev)
 159                         roce->netdev = (event == NETDEV_UNREGISTER) ?
 160                                         NULL : ndev;
 161                 write_unlock(&roce->netdev_lock);
 162                 break;
 163
 164         case NETDEV_CHANGE:
 165         case NETDEV_UP:
 166         case NETDEV_DOWN: {
 167                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 168                 struct net_device *upper = NULL;
 169
 170                 if (lag_ndev) {
 171                         upper = netdev_master_upper_dev_get(lag_ndev);
 172                         dev_put(lag_ndev);
 173                 }
 174
 175                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 176                     && ibdev->ib_active) {
 177                         struct ib_event ibev = { };
 178                         enum ib_port_state port_state;
 179
 180                         if (get_port_state(&ibdev->ib_dev, port_num,
 181                                            &port_state))
 182                                 goto done;
 183
 184                         if (roce->last_port_state == port_state)
 185                                 goto done;
 186
 187                         roce->last_port_state = port_state;
 188                         ibev.device = &ibdev->ib_dev;
 189                         if (port_state == IB_PORT_DOWN)
 190                                 ibev.event = IB_EVENT_PORT_ERR;
 191                         else if (port_state == IB_PORT_ACTIVE)
 192                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 193                         else
 194                                 goto done;
 195
 196                         ibev.element.port_num = port_num;
 197                         ib_dispatch_event(&ibev);
 198                 }
 199                 break;
 200         }
 201
 202         default:
 203                 break;
 204         }
 205 done:
 206         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 207         return NOTIFY_DONE;
 208 }
 209
 210 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 211                                              u8 port_num)
 212 {
 213         struct mlx5_ib_dev *ibdev = to_mdev(device);
 214         struct net_device *ndev;
 215         struct mlx5_core_dev *mdev;
 216
 217         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 218         if (!mdev)
 219                 return NULL;
 220
 221         ndev = mlx5_lag_get_roce_netdev(mdev);
 222         if (ndev)
 223                 goto out;
 224
 225         /* Ensure ndev does not disappear before we invoke dev_hold()
 226          */
 227         read_lock(&ibdev->roce[port_num - 1].netdev_lock);
 228         ndev = ibdev->roce[port_num - 1].netdev;
 229         if (ndev)
 230                 dev_hold(ndev);
 231         read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
 232
 233 out:
 234         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 235         return ndev;
 236 }
 237
 238 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 239                                                    u8 ib_port_num,
 240                                                    u8 *native_port_num)
 241 {
 242         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 243                                                           ib_port_num);
 244         struct mlx5_core_dev *mdev = NULL;
 245         struct mlx5_ib_multiport_info *mpi;
 246         struct mlx5_ib_port *port;
 247
 248         if (native_port_num)
 249                 *native_port_num = 1;
 250
 251         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 252                 return ibdev->mdev;
 253
 254         port = &ibdev->port[ib_port_num - 1];
 255         if (!port)
 256                 return NULL;
 257
 258         spin_lock(&port->mp.mpi_lock);
 259         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 260         if (mpi && !mpi->unaffiliate) {
 261                 mdev = mpi->mdev;
 262                 /* If it's the master no need to refcount, it'll exist
 263                  * as long as the ib_dev exists.
 264                  */
 265                 if (!mpi->is_master)
 266                         mpi->mdev_refcnt++;
 267         }
 268         spin_unlock(&port->mp.mpi_lock);
 269
 270         return mdev;
 271 }
 272
 273 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 274 {
 275         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 276                                                           port_num);
 277         struct mlx5_ib_multiport_info *mpi;
 278         struct mlx5_ib_port *port;
 279
 280         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 281                 return;
 282
 283         port = &ibdev->port[port_num - 1];
 284
 285         spin_lock(&port->mp.mpi_lock);
 286         mpi = ibdev->port[port_num - 1].mp.mpi;
 287         if (mpi->is_master)
 288                 goto out;
 289
 290         mpi->mdev_refcnt--;
 291         if (mpi->unaffiliate)
 292                 complete(&mpi->unref_comp);
 293 out:
 294         spin_unlock(&port->mp.mpi_lock);
 295 }
 296
 297 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 298                                     u8 *active_width)
 299 {
 300         switch (eth_proto_oper) {
 301         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 302         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 303         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 304         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 305                 *active_width = IB_WIDTH_1X;
 306                 *active_speed = IB_SPEED_SDR;
 307                 break;
 308         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 309         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 310         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 311         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 312         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 313         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 314         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 315                 *active_width = IB_WIDTH_1X;
 316                 *active_speed = IB_SPEED_QDR;
 317                 break;
 318         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 319         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 320         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 321                 *active_width = IB_WIDTH_1X;
 322                 *active_speed = IB_SPEED_EDR;
 323                 break;
 324         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 325         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 326         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 327         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 328                 *active_width = IB_WIDTH_4X;
 329                 *active_speed = IB_SPEED_QDR;
 330                 break;
 331         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 332         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 333         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 334                 *active_width = IB_WIDTH_1X;
 335                 *active_speed = IB_SPEED_HDR;
 336                 break;
 337         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 338                 *active_width = IB_WIDTH_4X;
 339                 *active_speed = IB_SPEED_FDR;
 340                 break;
 341         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 342         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 343         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 344         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 345                 *active_width = IB_WIDTH_4X;
 346                 *active_speed = IB_SPEED_EDR;
 347                 break;
 348         default:
 349                 return -EINVAL;
 350         }
 351
 352         return 0;
 353 }
 354
 355 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 356                                 struct ib_port_attr *props)
 357 {
 358         struct mlx5_ib_dev *dev = to_mdev(device);
 359         struct mlx5_core_dev *mdev;
 360         struct net_device *ndev, *upper;
 361         enum ib_mtu ndev_ib_mtu;
 362         bool put_mdev = true;
 363         u16 qkey_viol_cntr;
 364         u32 eth_prot_oper;
 365         u8 mdev_port_num;
 366         int err;
 367
 368         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 369         if (!mdev) {
 370                 /* This means the port isn't affiliated yet. Get the
 371                  * info for the master port instead.
 372                  */
 373                 put_mdev = false;
 374                 mdev = dev->mdev;
 375                 mdev_port_num = 1;
 376                 port_num = 1;
 377         }
 378
 379         /* Possible bad flows are checked before filling out props so in case
 380          * of an error it will still be zeroed out.
 381          */
 382         err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
 383                                              mdev_port_num);
 384         if (err)
 385                 goto out;
 386
 387         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 388                                  &props->active_width);
 389
 390         props->port_cap_flags  |= IB_PORT_CM_SUP;
 391         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 392
 393         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 394                                                 roce_address_table_size);
 395         props->max_mtu          = IB_MTU_4096;
 396         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 397         props->pkey_tbl_len     = 1;
 398         props->state            = IB_PORT_DOWN;
 399         props->phys_state       = 3;
 400
 401         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 402         props->qkey_viol_cntr = qkey_viol_cntr;
 403
 404         /* If this is a stub query for an unaffiliated port stop here */
 405         if (!put_mdev)
 406                 goto out;
 407
 408         ndev = mlx5_ib_get_netdev(device, port_num);
 409         if (!ndev)
 410                 goto out;
 411
 412         if (mlx5_lag_is_active(dev->mdev)) {
 413                 rcu_read_lock();
 414                 upper = netdev_master_upper_dev_get_rcu(ndev);
 415                 if (upper) {
 416                         dev_put(ndev);
 417                         ndev = upper;
 418                         dev_hold(ndev);
 419                 }
 420                 rcu_read_unlock();
 421         }
 422
 423         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 424                 props->state      = IB_PORT_ACTIVE;
 425                 props->phys_state = 5;
 426         }
 427
 428         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 429
 430         dev_put(ndev);
 431
 432         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 433 out:
 434         if (put_mdev)
 435                 mlx5_ib_put_native_port_mdev(dev, port_num);
 436         return err;
 437 }
 438
 439 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 440                          unsigned int index, const union ib_gid *gid,
 441                          const struct ib_gid_attr *attr)
 442 {
 443         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 444         u8 roce_version = 0;
 445         u8 roce_l3_type = 0;
 446         bool vlan = false;
 447         u8 mac[ETH_ALEN];
 448         u16 vlan_id = 0;
 449
 450         if (gid) {
 451                 gid_type = attr->gid_type;
 452                 ether_addr_copy(mac, attr->ndev->dev_addr);
 453
 454                 if (is_vlan_dev(attr->ndev)) {
 455                         vlan = true;
 456                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 457                 }
 458         }
 459
 460         switch (gid_type) {
 461         case IB_GID_TYPE_IB:
 462                 roce_version = MLX5_ROCE_VERSION_1;
 463                 break;
 464         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 465                 roce_version = MLX5_ROCE_VERSION_2;
 466                 if (ipv6_addr_v4mapped((void *)gid))
 467                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 468                 else
 469                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 470                 break;
 471
 472         default:
 473                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 474         }
 475
 476         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 477                                       roce_l3_type, gid->raw, mac, vlan,
 478                                       vlan_id, port_num);
 479 }
 480
 481 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 482                            unsigned int index, const union ib_gid *gid,
 483                            const struct ib_gid_attr *attr,
 484                            __always_unused void **context)
 485 {
 486         return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
 487 }
 488
 489 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 490                            unsigned int index, __always_unused void **context)
 491 {
 492         return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
 493 }
 494
 495 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 496                                int index)
 497 {
 498         struct ib_gid_attr attr;
 499         union ib_gid gid;
 500
 501         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 502                 return 0;
 503
 504         if (!attr.ndev)
 505                 return 0;
 506
 507         dev_put(attr.ndev);
 508
 509         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 510                 return 0;
 511
 512         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 513 }
 514
 515 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
 516                            int index, enum ib_gid_type *gid_type)
 517 {
 518         struct ib_gid_attr attr;
 519         union ib_gid gid;
 520         int ret;
 521
 522         ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
 523         if (ret)
 524                 return ret;
 525
 526         if (!attr.ndev)
 527                 return -ENODEV;
 528
 529         dev_put(attr.ndev);
 530
 531         *gid_type = attr.gid_type;
 532
 533         return 0;
 534 }
 535
 536 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 537 {
 538         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 539                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 540         return 0;
 541 }
 542
 543 enum {
 544         MLX5_VPORT_ACCESS_METHOD_MAD,
 545         MLX5_VPORT_ACCESS_METHOD_HCA,
 546         MLX5_VPORT_ACCESS_METHOD_NIC,
 547 };
 548
 549 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 550 {
 551         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 552                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 553
 554         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 555             IB_LINK_LAYER_ETHERNET)
 556                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 557
 558         return MLX5_VPORT_ACCESS_METHOD_HCA;
 559 }
 560
 561 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 562                             u8 atomic_size_qp,
 563                             struct ib_device_attr *props)
 564 {
 565         u8 tmp;
 566         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 567         u8 atomic_req_8B_endianness_mode =
 568                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 569
 570         /* Check if HW supports 8 bytes standard atomic operations and capable
 571          * of host endianness respond
 572          */
 573         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 574         if (((atomic_operations & tmp) == tmp) &&
 575             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 576             (atomic_req_8B_endianness_mode)) {
 577                 props->atomic_cap = IB_ATOMIC_HCA;
 578         } else {
 579                 props->atomic_cap = IB_ATOMIC_NONE;
 580         }
 581 }
 582
 583 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 584                                struct ib_device_attr *props)
 585 {
 586         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 587
 588         get_atomic_caps(dev, atomic_size_qp, props);
 589 }
 590
 591 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 592                                struct ib_device_attr *props)
 593 {
 594         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 595
 596         get_atomic_caps(dev, atomic_size_qp, props);
 597 }
 598
 599 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 600 {
 601         struct ib_device_attr props = {};
 602
 603         get_atomic_caps_dc(dev, &props);
 604         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 605 }
 606 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 607                                         __be64 *sys_image_guid)
 608 {
 609         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 610         struct mlx5_core_dev *mdev = dev->mdev;
 611         u64 tmp;
 612         int err;
 613
 614         switch (mlx5_get_vport_access_method(ibdev)) {
 615         case MLX5_VPORT_ACCESS_METHOD_MAD:
 616                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 617                                                             sys_image_guid);
 618
 619         case MLX5_VPORT_ACCESS_METHOD_HCA:
 620                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 621                 break;
 622
 623         case MLX5_VPORT_ACCESS_METHOD_NIC:
 624                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 625                 break;
 626
 627         default:
 628                 return -EINVAL;
 629         }
 630
 631         if (!err)
 632                 *sys_image_guid = cpu_to_be64(tmp);
 633
 634         return err;
 635
 636 }
 637
 638 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 639                                 u16 *max_pkeys)
 640 {
 641         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 642         struct mlx5_core_dev *mdev = dev->mdev;
 643
 644         switch (mlx5_get_vport_access_method(ibdev)) {
 645         case MLX5_VPORT_ACCESS_METHOD_MAD:
 646                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 647
 648         case MLX5_VPORT_ACCESS_METHOD_HCA:
 649         case MLX5_VPORT_ACCESS_METHOD_NIC:
 650                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 651                                                 pkey_table_size));
 652                 return 0;
 653
 654         default:
 655                 return -EINVAL;
 656         }
 657 }
 658
 659 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 660                                 u32 *vendor_id)
 661 {
 662         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 663
 664         switch (mlx5_get_vport_access_method(ibdev)) {
 665         case MLX5_VPORT_ACCESS_METHOD_MAD:
 666                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 667
 668         case MLX5_VPORT_ACCESS_METHOD_HCA:
 669         case MLX5_VPORT_ACCESS_METHOD_NIC:
 670                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 671
 672         default:
 673                 return -EINVAL;
 674         }
 675 }
 676
 677 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 678                                 __be64 *node_guid)
 679 {
 680         u64 tmp;
 681         int err;
 682
 683         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 684         case MLX5_VPORT_ACCESS_METHOD_MAD:
 685                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 686
 687         case MLX5_VPORT_ACCESS_METHOD_HCA:
 688                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 689                 break;
 690
 691         case MLX5_VPORT_ACCESS_METHOD_NIC:
 692                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 693                 break;
 694
 695         default:
 696                 return -EINVAL;
 697         }
 698
 699         if (!err)
 700                 *node_guid = cpu_to_be64(tmp);
 701
 702         return err;
 703 }
 704
 705 struct mlx5_reg_node_desc {
 706         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 707 };
 708
 709 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 710 {
 711         struct mlx5_reg_node_desc in;
 712
 713         if (mlx5_use_mad_ifc(dev))
 714                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 715
 716         memset(&in, 0, sizeof(in));
 717
 718         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 719                                     sizeof(struct mlx5_reg_node_desc),
 720                                     MLX5_REG_NODE_DESC, 0, 0);
 721 }
 722
 723 static int mlx5_ib_query_device(struct ib_device *ibdev,
 724                                 struct ib_device_attr *props,
 725                                 struct ib_udata *uhw)
 726 {
 727         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 728         struct mlx5_core_dev *mdev = dev->mdev;
 729         int err = -ENOMEM;
 730         int max_sq_desc;
 731         int max_rq_sg;
 732         int max_sq_sg;
 733         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 734         bool raw_support = !mlx5_core_mp_enabled(mdev);
 735         struct mlx5_ib_query_device_resp resp = {};
 736         size_t resp_len;
 737         u64 max_tso;
 738
 739         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 740         if (uhw->outlen && uhw->outlen < resp_len)
 741                 return -EINVAL;
 742         else
 743                 resp.response_length = resp_len;
 744
 745         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 746                 return -EINVAL;
 747
 748         memset(props, 0, sizeof(*props));
 749         err = mlx5_query_system_image_guid(ibdev,
 750                                            &props->sys_image_guid);
 751         if (err)
 752                 return err;
 753
 754         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 755         if (err)
 756                 return err;
 757
 758         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 759         if (err)
 760                 return err;
 761
 762         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 763                 (fw_rev_min(dev->mdev) << 16) |
 764                 fw_rev_sub(dev->mdev);
 765         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 766                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 767                 IB_DEVICE_SYS_IMAGE_GUID                |
 768                 IB_DEVICE_RC_RNR_NAK_GEN;
 769
 770         if (MLX5_CAP_GEN(mdev, pkv))
 771                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 772         if (MLX5_CAP_GEN(mdev, qkv))
 773                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 774         if (MLX5_CAP_GEN(mdev, apm))
 775                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 776         if (MLX5_CAP_GEN(mdev, xrc))
 777                 props->device_cap_flags |= IB_DEVICE_XRC;
 778         if (MLX5_CAP_GEN(mdev, imaicl)) {
 779                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 780                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 781                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 782                 /* We support 'Gappy' memory registration too */
 783                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 784         }
 785         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 786         if (MLX5_CAP_GEN(mdev, sho)) {
 787                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 788                 /* At this stage no support for signature handover */
 789                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 790                                       IB_PROT_T10DIF_TYPE_2 |
 791                                       IB_PROT_T10DIF_TYPE_3;
 792                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 793                                        IB_GUARD_T10DIF_CSUM;
 794         }
 795         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 796                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 797
 798         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 799                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 800                         /* Legacy bit to support old userspace libraries */
 801                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 802                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 803                 }
 804
 805                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 806                         props->raw_packet_caps |=
 807                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 808
 809                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 810                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 811                         if (max_tso) {
 812                                 resp.tso_caps.max_tso = 1 << max_tso;
 813                                 resp.tso_caps.supported_qpts |=
 814                                         1 << IB_QPT_RAW_PACKET;
 815                                 resp.response_length += sizeof(resp.tso_caps);
 816                         }
 817                 }
 818
 819                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 820                         resp.rss_caps.rx_hash_function =
 821                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 822                         resp.rss_caps.rx_hash_fields_mask =
 823                                                 MLX5_RX_HASH_SRC_IPV4 |
 824                                                 MLX5_RX_HASH_DST_IPV4 |
 825                                                 MLX5_RX_HASH_SRC_IPV6 |
 826                                                 MLX5_RX_HASH_DST_IPV6 |
 827                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 828                                                 MLX5_RX_HASH_DST_PORT_TCP |
 829                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 830                                                 MLX5_RX_HASH_DST_PORT_UDP |
 831                                                 MLX5_RX_HASH_INNER;
 832                         resp.response_length += sizeof(resp.rss_caps);
 833                 }
 834         } else {
 835                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 836                         resp.response_length += sizeof(resp.tso_caps);
 837                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 838                         resp.response_length += sizeof(resp.rss_caps);
 839         }
 840
 841         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 842                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 843                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 844         }
 845
 846         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 847             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 848             raw_support)
 849                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 850
 851         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 852             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 853                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 854
 855         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 856             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 857             raw_support) {
 858                 /* Legacy bit to support old userspace libraries */
 859                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 860                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 861         }
 862
 863         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 864                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 865
 866         if (MLX5_CAP_GEN(mdev, end_pad))
 867                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 868
 869         props->vendor_part_id      = mdev->pdev->device;
 870         props->hw_ver              = mdev->pdev->revision;
 871
 872         props->max_mr_size         = ~0ull;
 873         props->page_size_cap       = ~(min_page_size - 1);
 874         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 875         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 876         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 877                      sizeof(struct mlx5_wqe_data_seg);
 878         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 879         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 880                      sizeof(struct mlx5_wqe_raddr_seg)) /
 881                 sizeof(struct mlx5_wqe_data_seg);
 882         props->max_sge = min(max_rq_sg, max_sq_sg);
 883         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 884         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 885         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 886         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 887         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 888         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 889         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 890         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 891         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 892         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 893         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 894         props->max_srq_sge         = max_rq_sg - 1;
 895         props->max_fast_reg_page_list_len =
 896                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 897         get_atomic_caps_qp(dev, props);
 898         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 899         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 900         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 901         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 902                                            props->max_mcast_grp;
 903         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 904         props->max_ah = INT_MAX;
 905         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 906         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 907
 908 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 909         if (MLX5_CAP_GEN(mdev, pg))
 910                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 911         props->odp_caps = dev->odp_caps;
 912 #endif
 913
 914         if (MLX5_CAP_GEN(mdev, cd))
 915                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 916
 917         if (!mlx5_core_is_pf(mdev))
 918                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 919
 920         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 921             IB_LINK_LAYER_ETHERNET && raw_support) {
 922                 props->rss_caps.max_rwq_indirection_tables =
 923                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 924                 props->rss_caps.max_rwq_indirection_table_size =
 925                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 926                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 927                 props->max_wq_type_rq =
 928                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 929         }
 930
 931         if (MLX5_CAP_GEN(mdev, tag_matching)) {
 932                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
 933                 props->tm_caps.max_num_tags =
 934                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
 935                 props->tm_caps.flags = IB_TM_CAP_RC;
 936                 props->tm_caps.max_ops =
 937                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 938                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
 939         }
 940
 941         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
 942                 props->cq_caps.max_cq_moderation_count =
 943                                                 MLX5_MAX_CQ_COUNT;
 944                 props->cq_caps.max_cq_moderation_period =
 945                                                 MLX5_MAX_CQ_PERIOD;
 946         }
 947
 948         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 949                 resp.cqe_comp_caps.max_num =
 950                         MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
 951                         MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
 952                 resp.cqe_comp_caps.supported_format =
 953                         MLX5_IB_CQE_RES_FORMAT_HASH |
 954                         MLX5_IB_CQE_RES_FORMAT_CSUM;
 955                 resp.response_length += sizeof(resp.cqe_comp_caps);
 956         }
 957
 958         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
 959             raw_support) {
 960                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
 961                     MLX5_CAP_GEN(mdev, qos)) {
 962                         resp.packet_pacing_caps.qp_rate_limit_max =
 963                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
 964                         resp.packet_pacing_caps.qp_rate_limit_min =
 965                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
 966                         resp.packet_pacing_caps.supported_qpts |=
 967                                 1 << IB_QPT_RAW_PACKET;
 968                 }
 969                 resp.response_length += sizeof(resp.packet_pacing_caps);
 970         }
 971
 972         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
 973                         uhw->outlen)) {
 974                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
 975                         resp.mlx5_ib_support_multi_pkt_send_wqes =
 976                                 MLX5_IB_ALLOW_MPW;
 977
 978                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
 979                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
 980                                 MLX5_IB_SUPPORT_EMPW;
 981
 982                 resp.response_length +=
 983                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
 984         }
 985
 986         if (field_avail(typeof(resp), flags, uhw->outlen)) {
 987                 resp.response_length += sizeof(resp.flags);
 988
 989                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
 990                         resp.flags |=
 991                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
 992
 993                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
 994                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
 995         }
 996
 997         if (field_avail(typeof(resp), sw_parsing_caps,
 998                         uhw->outlen)) {
 999                 resp.response_length += sizeof(resp.sw_parsing_caps);
1000                 if (MLX5_CAP_ETH(mdev, swp)) {
1001                         resp.sw_parsing_caps.sw_parsing_offloads |=
1002                                 MLX5_IB_SW_PARSING;
1003
1004                         if (MLX5_CAP_ETH(mdev, swp_csum))
1005                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1006                                         MLX5_IB_SW_PARSING_CSUM;
1007
1008                         if (MLX5_CAP_ETH(mdev, swp_lso))
1009                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1010                                         MLX5_IB_SW_PARSING_LSO;
1011
1012                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1013                                 resp.sw_parsing_caps.supported_qpts =
1014                                         BIT(IB_QPT_RAW_PACKET);
1015                 }
1016         }
1017
1018         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1019             raw_support) {
1020                 resp.response_length += sizeof(resp.striding_rq_caps);
1021                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1022                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1023                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1024                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1025                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1026                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1027                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1028                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1029                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1030                         resp.striding_rq_caps.supported_qpts =
1031                                 BIT(IB_QPT_RAW_PACKET);
1032                 }
1033         }
1034
1035         if (field_avail(typeof(resp), tunnel_offloads_caps,
1036                         uhw->outlen)) {
1037                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1038                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1039                         resp.tunnel_offloads_caps |=
1040                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1041                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1042                         resp.tunnel_offloads_caps |=
1043                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1044                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1045                         resp.tunnel_offloads_caps |=
1046                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1047         }
1048
1049         if (uhw->outlen) {
1050                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1051
1052                 if (err)
1053                         return err;
1054         }
1055
1056         return 0;
1057 }
1058
1059 enum mlx5_ib_width {
1060         MLX5_IB_WIDTH_1X        = 1 << 0,
1061         MLX5_IB_WIDTH_2X        = 1 << 1,
1062         MLX5_IB_WIDTH_4X        = 1 << 2,
1063         MLX5_IB_WIDTH_8X        = 1 << 3,
1064         MLX5_IB_WIDTH_12X       = 1 << 4
1065 };
1066
1067 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1068                                   u8 *ib_width)
1069 {
1070         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1071         int err = 0;
1072
1073         if (active_width & MLX5_IB_WIDTH_1X) {
1074                 *ib_width = IB_WIDTH_1X;
1075         } else if (active_width & MLX5_IB_WIDTH_2X) {
1076                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1077                             (int)active_width);
1078                 err = -EINVAL;
1079         } else if (active_width & MLX5_IB_WIDTH_4X) {
1080                 *ib_width = IB_WIDTH_4X;
1081         } else if (active_width & MLX5_IB_WIDTH_8X) {
1082                 *ib_width = IB_WIDTH_8X;
1083         } else if (active_width & MLX5_IB_WIDTH_12X) {
1084                 *ib_width = IB_WIDTH_12X;
1085         } else {
1086                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1087                             (int)active_width);
1088                 err = -EINVAL;
1089         }
1090
1091         return err;
1092 }
1093
1094 static int mlx5_mtu_to_ib_mtu(int mtu)
1095 {
1096         switch (mtu) {
1097         case 256: return 1;
1098         case 512: return 2;
1099         case 1024: return 3;
1100         case 2048: return 4;
1101         case 4096: return 5;
1102         default:
1103                 pr_warn("invalid mtu\n");
1104                 return -1;
1105         }
1106 }
1107
1108 enum ib_max_vl_num {
1109         __IB_MAX_VL_0           = 1,
1110         __IB_MAX_VL_0_1         = 2,
1111         __IB_MAX_VL_0_3         = 3,
1112         __IB_MAX_VL_0_7         = 4,
1113         __IB_MAX_VL_0_14        = 5,
1114 };
1115
1116 enum mlx5_vl_hw_cap {
1117         MLX5_VL_HW_0    = 1,
1118         MLX5_VL_HW_0_1  = 2,
1119         MLX5_VL_HW_0_2  = 3,
1120         MLX5_VL_HW_0_3  = 4,
1121         MLX5_VL_HW_0_4  = 5,
1122         MLX5_VL_HW_0_5  = 6,
1123         MLX5_VL_HW_0_6  = 7,
1124         MLX5_VL_HW_0_7  = 8,
1125         MLX5_VL_HW_0_14 = 15
1126 };
1127
1128 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1129                                 u8 *max_vl_num)
1130 {
1131         switch (vl_hw_cap) {
1132         case MLX5_VL_HW_0:
1133                 *max_vl_num = __IB_MAX_VL_0;
1134                 break;
1135         case MLX5_VL_HW_0_1:
1136                 *max_vl_num = __IB_MAX_VL_0_1;
1137                 break;
1138         case MLX5_VL_HW_0_3:
1139                 *max_vl_num = __IB_MAX_VL_0_3;
1140                 break;
1141         case MLX5_VL_HW_0_7:
1142                 *max_vl_num = __IB_MAX_VL_0_7;
1143                 break;
1144         case MLX5_VL_HW_0_14:
1145                 *max_vl_num = __IB_MAX_VL_0_14;
1146                 break;
1147
1148         default:
1149                 return -EINVAL;
1150         }
1151
1152         return 0;
1153 }
1154
1155 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1156                                struct ib_port_attr *props)
1157 {
1158         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1159         struct mlx5_core_dev *mdev = dev->mdev;
1160         struct mlx5_hca_vport_context *rep;
1161         u16 max_mtu;
1162         u16 oper_mtu;
1163         int err;
1164         u8 ib_link_width_oper;
1165         u8 vl_hw_cap;
1166
1167         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1168         if (!rep) {
1169                 err = -ENOMEM;
1170                 goto out;
1171         }
1172
1173         /* props being zeroed by the caller, avoid zeroing it here */
1174
1175         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1176         if (err)
1177                 goto out;
1178
1179         props->lid              = rep->lid;
1180         props->lmc              = rep->lmc;
1181         props->sm_lid           = rep->sm_lid;
1182         props->sm_sl            = rep->sm_sl;
1183         props->state            = rep->vport_state;
1184         props->phys_state       = rep->port_physical_state;
1185         props->port_cap_flags   = rep->cap_mask1;
1186         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1187         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1188         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1189         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1190         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1191         props->subnet_timeout   = rep->subnet_timeout;
1192         props->init_type_reply  = rep->init_type_reply;
1193         props->grh_required     = rep->grh_required;
1194
1195         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1196         if (err)
1197                 goto out;
1198
1199         err = translate_active_width(ibdev, ib_link_width_oper,
1200                                      &props->active_width);
1201         if (err)
1202                 goto out;
1203         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1204         if (err)
1205                 goto out;
1206
1207         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1208
1209         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1210
1211         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1212
1213         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1214
1215         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1216         if (err)
1217                 goto out;
1218
1219         err = translate_max_vl_num(ibdev, vl_hw_cap,
1220                                    &props->max_vl_num);
1221 out:
1222         kfree(rep);
1223         return err;
1224 }
1225
1226 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1227                        struct ib_port_attr *props)
1228 {
1229         unsigned int count;
1230         int ret;
1231
1232         switch (mlx5_get_vport_access_method(ibdev)) {
1233         case MLX5_VPORT_ACCESS_METHOD_MAD:
1234                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1235                 break;
1236
1237         case MLX5_VPORT_ACCESS_METHOD_HCA:
1238                 ret = mlx5_query_hca_port(ibdev, port, props);
1239                 break;
1240
1241         case MLX5_VPORT_ACCESS_METHOD_NIC:
1242                 ret = mlx5_query_port_roce(ibdev, port, props);
1243                 break;
1244
1245         default:
1246                 ret = -EINVAL;
1247         }
1248
1249         if (!ret && props) {
1250                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1251                 struct mlx5_core_dev *mdev;
1252                 bool put_mdev = true;
1253
1254                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1255                 if (!mdev) {
1256                         /* If the port isn't affiliated yet query the master.
1257                          * The master and slave will have the same values.
1258                          */
1259                         mdev = dev->mdev;
1260                         port = 1;
1261                         put_mdev = false;
1262                 }
1263                 count = mlx5_core_reserved_gids_count(mdev);
1264                 if (put_mdev)
1265                         mlx5_ib_put_native_port_mdev(dev, port);
1266                 props->gid_tbl_len -= count;
1267         }
1268         return ret;
1269 }
1270
1271 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1272                              union ib_gid *gid)
1273 {
1274         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1275         struct mlx5_core_dev *mdev = dev->mdev;
1276
1277         switch (mlx5_get_vport_access_method(ibdev)) {
1278         case MLX5_VPORT_ACCESS_METHOD_MAD:
1279                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1280
1281         case MLX5_VPORT_ACCESS_METHOD_HCA:
1282                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1283
1284         default:
1285                 return -EINVAL;
1286         }
1287
1288 }
1289
1290 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1291                                    u16 index, u16 *pkey)
1292 {
1293         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1294         struct mlx5_core_dev *mdev;
1295         bool put_mdev = true;
1296         u8 mdev_port_num;
1297         int err;
1298
1299         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1300         if (!mdev) {
1301                 /* The port isn't affiliated yet, get the PKey from the master
1302                  * port. For RoCE the PKey tables will be the same.
1303                  */
1304                 put_mdev = false;
1305                 mdev = dev->mdev;
1306                 mdev_port_num = 1;
1307         }
1308
1309         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1310                                         index, pkey);
1311         if (put_mdev)
1312                 mlx5_ib_put_native_port_mdev(dev, port);
1313
1314         return err;
1315 }
1316
1317 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1318                               u16 *pkey)
1319 {
1320         switch (mlx5_get_vport_access_method(ibdev)) {
1321         case MLX5_VPORT_ACCESS_METHOD_MAD:
1322                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1323
1324         case MLX5_VPORT_ACCESS_METHOD_HCA:
1325         case MLX5_VPORT_ACCESS_METHOD_NIC:
1326                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1327         default:
1328                 return -EINVAL;
1329         }
1330 }
1331
1332 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1333                                  struct ib_device_modify *props)
1334 {
1335         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1336         struct mlx5_reg_node_desc in;
1337         struct mlx5_reg_node_desc out;
1338         int err;
1339
1340         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1341                 return -EOPNOTSUPP;
1342
1343         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1344                 return 0;
1345
1346         /*
1347          * If possible, pass node desc to FW, so it can generate
1348          * a 144 trap.  If cmd fails, just ignore.
1349          */
1350         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1351         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1352                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1353         if (err)
1354                 return err;
1355
1356         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1357
1358         return err;
1359 }
1360
1361 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1362                                 u32 value)
1363 {
1364         struct mlx5_hca_vport_context ctx = {};
1365         struct mlx5_core_dev *mdev;
1366         u8 mdev_port_num;
1367         int err;
1368
1369         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1370         if (!mdev)
1371                 return -ENODEV;
1372
1373         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1374         if (err)
1375                 goto out;
1376
1377         if (~ctx.cap_mask1_perm & mask) {
1378                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1379                              mask, ctx.cap_mask1_perm);
1380                 err = -EINVAL;
1381                 goto out;
1382         }
1383
1384         ctx.cap_mask1 = value;
1385         ctx.cap_mask1_perm = mask;
1386         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1387                                                  0, &ctx);
1388
1389 out:
1390         mlx5_ib_put_native_port_mdev(dev, port_num);
1391
1392         return err;
1393 }
1394
1395 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1396                                struct ib_port_modify *props)
1397 {
1398         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1399         struct ib_port_attr attr;
1400         u32 tmp;
1401         int err;
1402         u32 change_mask;
1403         u32 value;
1404         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1405                       IB_LINK_LAYER_INFINIBAND);
1406
1407         /* CM layer calls ib_modify_port() regardless of the link layer. For
1408          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1409          */
1410         if (!is_ib)
1411                 return 0;
1412
1413         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1414                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1415                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1416                 return set_port_caps_atomic(dev, port, change_mask, value);
1417         }
1418
1419         mutex_lock(&dev->cap_mask_mutex);
1420
1421         err = ib_query_port(ibdev, port, &attr);
1422         if (err)
1423                 goto out;
1424
1425         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1426                 ~props->clr_port_cap_mask;
1427
1428         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1429
1430 out:
1431         mutex_unlock(&dev->cap_mask_mutex);
1432         return err;
1433 }
1434
1435 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1436 {
1437         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1438                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1439 }
1440
1441 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1442 {
1443         /* Large page with non 4k uar support might limit the dynamic size */
1444         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1445                 return MLX5_MIN_DYN_BFREGS;
1446
1447         return MLX5_MAX_DYN_BFREGS;
1448 }
1449
1450 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1451                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1452                              struct mlx5_bfreg_info *bfregi)
1453 {
1454         int uars_per_sys_page;
1455         int bfregs_per_sys_page;
1456         int ref_bfregs = req->total_num_bfregs;
1457
1458         if (req->total_num_bfregs == 0)
1459                 return -EINVAL;
1460
1461         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1462         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1463
1464         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1465                 return -ENOMEM;
1466
1467         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1468         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1469         /* This holds the required static allocation asked by the user */
1470         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1471         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1472                 return -EINVAL;
1473
1474         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1475         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1476         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1477         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1478
1479         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1480                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1481                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1482                     req->total_num_bfregs, bfregi->total_num_bfregs,
1483                     bfregi->num_sys_pages);
1484
1485         return 0;
1486 }
1487
1488 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1489 {
1490         struct mlx5_bfreg_info *bfregi;
1491         int err;
1492         int i;
1493
1494         bfregi = &context->bfregi;
1495         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1496                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1497                 if (err)
1498                         goto error;
1499
1500                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1501         }
1502
1503         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1504                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1505
1506         return 0;
1507
1508 error:
1509         for (--i; i >= 0; i--)
1510                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1511                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1512
1513         return err;
1514 }
1515
1516 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1517 {
1518         struct mlx5_bfreg_info *bfregi;
1519         int err;
1520         int i;
1521
1522         bfregi = &context->bfregi;
1523         for (i = 0; i < bfregi->num_sys_pages; i++) {
1524                 if (i < bfregi->num_static_sys_pages ||
1525                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1526                         err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1527                         if (err) {
1528                                 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1529                                 return err;
1530                         }
1531                 }
1532         }
1533
1534         return 0;
1535 }
1536
1537 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1538 {
1539         int err;
1540
1541         err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1542         if (err)
1543                 return err;
1544
1545         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1546             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1547              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1548                 return err;
1549
1550         mutex_lock(&dev->lb_mutex);
1551         dev->user_td++;
1552
1553         if (dev->user_td == 2)
1554                 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1555
1556         mutex_unlock(&dev->lb_mutex);
1557         return err;
1558 }
1559
1560 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1561 {
1562         mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1563
1564         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1565             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1566              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1567                 return;
1568
1569         mutex_lock(&dev->lb_mutex);
1570         dev->user_td--;
1571
1572         if (dev->user_td < 2)
1573                 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1574
1575         mutex_unlock(&dev->lb_mutex);
1576 }
1577
1578 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1579                                                   struct ib_udata *udata)
1580 {
1581         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1582         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1583         struct mlx5_ib_alloc_ucontext_resp resp = {};
1584         struct mlx5_core_dev *mdev = dev->mdev;
1585         struct mlx5_ib_ucontext *context;
1586         struct mlx5_bfreg_info *bfregi;
1587         int ver;
1588         int err;
1589         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1590                                      max_cqe_version);
1591         bool lib_uar_4k;
1592
1593         if (!dev->ib_active)
1594                 return ERR_PTR(-EAGAIN);
1595
1596         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1597                 ver = 0;
1598         else if (udata->inlen >= min_req_v2)
1599                 ver = 2;
1600         else
1601                 return ERR_PTR(-EINVAL);
1602
1603         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1604         if (err)
1605                 return ERR_PTR(err);
1606
1607         if (req.flags)
1608                 return ERR_PTR(-EINVAL);
1609
1610         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1611                 return ERR_PTR(-EOPNOTSUPP);
1612
1613         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1614                                     MLX5_NON_FP_BFREGS_PER_UAR);
1615         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1616                 return ERR_PTR(-EINVAL);
1617
1618         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1619         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1620                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1621         resp.cache_line_size = cache_line_size();
1622         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1623         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1624         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1625         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1626         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1627         resp.cqe_version = min_t(__u8,
1628                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1629                                  req.max_cqe_version);
1630         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1631                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1632         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1633                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1634         resp.response_length = min(offsetof(typeof(resp), response_length) +
1635                                    sizeof(resp.response_length), udata->outlen);
1636
1637         context = kzalloc(sizeof(*context), GFP_KERNEL);
1638         if (!context)
1639                 return ERR_PTR(-ENOMEM);
1640
1641         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1642         bfregi = &context->bfregi;
1643
1644         /* updates req->total_num_bfregs */
1645         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1646         if (err)
1647                 goto out_ctx;
1648
1649         mutex_init(&bfregi->lock);
1650         bfregi->lib_uar_4k = lib_uar_4k;
1651         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1652                                 GFP_KERNEL);
1653         if (!bfregi->count) {
1654                 err = -ENOMEM;
1655                 goto out_ctx;
1656         }
1657
1658         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1659                                     sizeof(*bfregi->sys_pages),
1660                                     GFP_KERNEL);
1661         if (!bfregi->sys_pages) {
1662                 err = -ENOMEM;
1663                 goto out_count;
1664         }
1665
1666         err = allocate_uars(dev, context);
1667         if (err)
1668                 goto out_sys_pages;
1669
1670 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1671         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1672 #endif
1673
1674         context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1675         if (!context->upd_xlt_page) {
1676                 err = -ENOMEM;
1677                 goto out_uars;
1678         }
1679         mutex_init(&context->upd_xlt_page_mutex);
1680
1681         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1682                 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1683                 if (err)
1684                         goto out_page;
1685         }
1686
1687         INIT_LIST_HEAD(&context->vma_private_list);
1688         mutex_init(&context->vma_private_list_mutex);
1689         INIT_LIST_HEAD(&context->db_page_list);
1690         mutex_init(&context->db_page_mutex);
1691
1692         resp.tot_bfregs = req.total_num_bfregs;
1693         resp.num_ports = dev->num_ports;
1694
1695         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1696                 resp.response_length += sizeof(resp.cqe_version);
1697
1698         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1699                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1700                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1701                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1702         }
1703
1704         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1705                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1706                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1707                         resp.eth_min_inline++;
1708                 }
1709                 resp.response_length += sizeof(resp.eth_min_inline);
1710         }
1711
1712         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1713                 if (mdev->clock_info)
1714                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1715                 resp.response_length += sizeof(resp.clock_info_versions);
1716         }
1717
1718         /*
1719          * We don't want to expose information from the PCI bar that is located
1720          * after 4096 bytes, so if the arch only supports larger pages, let's
1721          * pretend we don't support reading the HCA's core clock. This is also
1722          * forced by mmap function.
1723          */
1724         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1725                 if (PAGE_SIZE <= 4096) {
1726                         resp.comp_mask |=
1727                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1728                         resp.hca_core_clock_offset =
1729                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1730                 }
1731                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1732         }
1733
1734         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1735                 resp.response_length += sizeof(resp.log_uar_size);
1736
1737         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1738                 resp.response_length += sizeof(resp.num_uars_per_page);
1739
1740         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1741                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1742                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1743         }
1744
1745         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1746         if (err)
1747                 goto out_td;
1748
1749         bfregi->ver = ver;
1750         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1751         context->cqe_version = resp.cqe_version;
1752         context->lib_caps = req.lib_caps;
1753         print_lib_caps(dev, context->lib_caps);
1754
1755         return &context->ibucontext;
1756
1757 out_td:
1758         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1759                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1760
1761 out_page:
1762         free_page(context->upd_xlt_page);
1763
1764 out_uars:
1765         deallocate_uars(dev, context);
1766
1767 out_sys_pages:
1768         kfree(bfregi->sys_pages);
1769
1770 out_count:
1771         kfree(bfregi->count);
1772
1773 out_ctx:
1774         kfree(context);
1775
1776         return ERR_PTR(err);
1777 }
1778
1779 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1780 {
1781         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1782         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1783         struct mlx5_bfreg_info *bfregi;
1784
1785         bfregi = &context->bfregi;
1786         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1787                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1788
1789         free_page(context->upd_xlt_page);
1790         deallocate_uars(dev, context);
1791         kfree(bfregi->sys_pages);
1792         kfree(bfregi->count);
1793         kfree(context);
1794
1795         return 0;
1796 }
1797
1798 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1799                                  int uar_idx)
1800 {
1801         int fw_uars_per_page;
1802
1803         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1804
1805         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1806 }
1807
1808 static int get_command(unsigned long offset)
1809 {
1810         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1811 }
1812
1813 static int get_arg(unsigned long offset)
1814 {
1815         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1816 }
1817
1818 static int get_index(unsigned long offset)
1819 {
1820         return get_arg(offset);
1821 }
1822
1823 /* Index resides in an extra byte to enable larger values than 255 */
1824 static int get_extended_index(unsigned long offset)
1825 {
1826         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1827 }
1828
1829 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1830 {
1831         /* vma_open is called when a new VMA is created on top of our VMA.  This
1832          * is done through either mremap flow or split_vma (usually due to
1833          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1834          * as this VMA is strongly hardware related.  Therefore we set the
1835          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1836          * calling us again and trying to do incorrect actions.  We assume that
1837          * the original VMA size is exactly a single page, and therefore all
1838          * "splitting" operation will not happen to it.
1839          */
1840         area->vm_ops = NULL;
1841 }
1842
1843 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1844 {
1845         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1846
1847         /* It's guaranteed that all VMAs opened on a FD are closed before the
1848          * file itself is closed, therefore no sync is needed with the regular
1849          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1850          * However need a sync with accessing the vma as part of
1851          * mlx5_ib_disassociate_ucontext.
1852          * The close operation is usually called under mm->mmap_sem except when
1853          * process is exiting.
1854          * The exiting case is handled explicitly as part of
1855          * mlx5_ib_disassociate_ucontext.
1856          */
1857         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1858
1859         /* setting the vma context pointer to null in the mlx5_ib driver's
1860          * private data, to protect a race condition in
1861          * mlx5_ib_disassociate_ucontext().
1862          */
1863         mlx5_ib_vma_priv_data->vma = NULL;
1864         mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1865         list_del(&mlx5_ib_vma_priv_data->list);
1866         mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1867         kfree(mlx5_ib_vma_priv_data);
1868 }
1869
1870 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1871         .open = mlx5_ib_vma_open,
1872         .close = mlx5_ib_vma_close
1873 };
1874
1875 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1876                                 struct mlx5_ib_ucontext *ctx)
1877 {
1878         struct mlx5_ib_vma_private_data *vma_prv;
1879         struct list_head *vma_head = &ctx->vma_private_list;
1880
1881         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1882         if (!vma_prv)
1883                 return -ENOMEM;
1884
1885         vma_prv->vma = vma;
1886         vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1887         vma->vm_private_data = vma_prv;
1888         vma->vm_ops =  &mlx5_ib_vm_ops;
1889
1890         mutex_lock(&ctx->vma_private_list_mutex);
1891         list_add(&vma_prv->list, vma_head);
1892         mutex_unlock(&ctx->vma_private_list_mutex);
1893
1894         return 0;
1895 }
1896
1897 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1898 {
1899         int ret;
1900         struct vm_area_struct *vma;
1901         struct mlx5_ib_vma_private_data *vma_private, *n;
1902         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1903         struct task_struct *owning_process  = NULL;
1904         struct mm_struct   *owning_mm       = NULL;
1905
1906         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1907         if (!owning_process)
1908                 return;
1909
1910         owning_mm = get_task_mm(owning_process);
1911         if (!owning_mm) {
1912                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1913                 while (1) {
1914                         put_task_struct(owning_process);
1915                         usleep_range(1000, 2000);
1916                         owning_process = get_pid_task(ibcontext->tgid,
1917                                                       PIDTYPE_PID);
1918                         if (!owning_process ||
1919                             owning_process->state == TASK_DEAD) {
1920                                 pr_info("disassociate ucontext done, task was terminated\n");
1921                                 /* in case task was dead need to release the
1922                                  * task struct.
1923                                  */
1924                                 if (owning_process)
1925                                         put_task_struct(owning_process);
1926                                 return;
1927                         }
1928                 }
1929         }
1930
1931         /* need to protect from a race on closing the vma as part of
1932          * mlx5_ib_vma_close.
1933          */
1934         down_write(&owning_mm->mmap_sem);
1935         mutex_lock(&context->vma_private_list_mutex);
1936         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1937                                  list) {
1938                 vma = vma_private->vma;
1939                 ret = zap_vma_ptes(vma, vma->vm_start,
1940                                    PAGE_SIZE);
1941                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1942                 /* context going to be destroyed, should
1943                  * not access ops any more.
1944                  */
1945                 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1946                 vma->vm_ops = NULL;
1947                 list_del(&vma_private->list);
1948                 kfree(vma_private);
1949         }
1950         mutex_unlock(&context->vma_private_list_mutex);
1951         up_write(&owning_mm->mmap_sem);
1952         mmput(owning_mm);
1953         put_task_struct(owning_process);
1954 }
1955
1956 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1957 {
1958         switch (cmd) {
1959         case MLX5_IB_MMAP_WC_PAGE:
1960                 return "WC";
1961         case MLX5_IB_MMAP_REGULAR_PAGE:
1962                 return "best effort WC";
1963         case MLX5_IB_MMAP_NC_PAGE:
1964                 return "NC";
1965         default:
1966                 return NULL;
1967         }
1968 }
1969
1970 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1971                                         struct vm_area_struct *vma,
1972                                         struct mlx5_ib_ucontext *context)
1973 {
1974         phys_addr_t pfn;
1975         int err;
1976
1977         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1978                 return -EINVAL;
1979
1980         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
1981                 return -EOPNOTSUPP;
1982
1983         if (vma->vm_flags & VM_WRITE)
1984                 return -EPERM;
1985
1986         if (!dev->mdev->clock_info_page)
1987                 return -EOPNOTSUPP;
1988
1989         pfn = page_to_pfn(dev->mdev->clock_info_page);
1990         err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
1991                               vma->vm_page_prot);
1992         if (err)
1993                 return err;
1994
1995         mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
1996                     vma->vm_start,
1997                     (unsigned long long)pfn << PAGE_SHIFT);
1998
1999         return mlx5_ib_set_vma_data(vma, context);
2000 }
2001
2002 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2003                     struct vm_area_struct *vma,
2004                     struct mlx5_ib_ucontext *context)
2005 {
2006         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2007         int err;
2008         unsigned long idx;
2009         phys_addr_t pfn, pa;
2010         pgprot_t prot;
2011         u32 bfreg_dyn_idx = 0;
2012         u32 uar_index;
2013         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2014         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2015                                 bfregi->num_static_sys_pages;
2016
2017         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2018                 return -EINVAL;
2019
2020         if (dyn_uar)
2021                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2022         else
2023                 idx = get_index(vma->vm_pgoff);
2024
2025         if (idx >= max_valid_idx) {
2026                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2027                              idx, max_valid_idx);
2028                 return -EINVAL;
2029         }
2030
2031         switch (cmd) {
2032         case MLX5_IB_MMAP_WC_PAGE:
2033         case MLX5_IB_MMAP_ALLOC_WC:
2034 /* Some architectures don't support WC memory */
2035 #if defined(CONFIG_X86)
2036                 if (!pat_enabled())
2037                         return -EPERM;
2038 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2039                         return -EPERM;
2040 #endif
2041         /* fall through */
2042         case MLX5_IB_MMAP_REGULAR_PAGE:
2043                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2044                 prot = pgprot_writecombine(vma->vm_page_prot);
2045                 break;
2046         case MLX5_IB_MMAP_NC_PAGE:
2047                 prot = pgprot_noncached(vma->vm_page_prot);
2048                 break;
2049         default:
2050                 return -EINVAL;
2051         }
2052
2053         if (dyn_uar) {
2054                 int uars_per_page;
2055
2056                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2057                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2058                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2059                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2060                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2061                         return -EINVAL;
2062                 }
2063
2064                 mutex_lock(&bfregi->lock);
2065                 /* Fail if uar already allocated, first bfreg index of each
2066                  * page holds its count.
2067                  */
2068                 if (bfregi->count[bfreg_dyn_idx]) {
2069                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2070                         mutex_unlock(&bfregi->lock);
2071                         return -EINVAL;
2072                 }
2073
2074                 bfregi->count[bfreg_dyn_idx]++;
2075                 mutex_unlock(&bfregi->lock);
2076
2077                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2078                 if (err) {
2079                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2080                         goto free_bfreg;
2081                 }
2082         } else {
2083                 uar_index = bfregi->sys_pages[idx];
2084         }
2085
2086         pfn = uar_index2pfn(dev, uar_index);
2087         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2088
2089         vma->vm_page_prot = prot;
2090         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2091                                  PAGE_SIZE, vma->vm_page_prot);
2092         if (err) {
2093                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2094                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
2095                 err = -EAGAIN;
2096                 goto err;
2097         }
2098
2099         pa = pfn << PAGE_SHIFT;
2100         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2101                     vma->vm_start, &pa);
2102
2103         err = mlx5_ib_set_vma_data(vma, context);
2104         if (err)
2105                 goto err;
2106
2107         if (dyn_uar)
2108                 bfregi->sys_pages[idx] = uar_index;
2109         return 0;
2110
2111 err:
2112         if (!dyn_uar)
2113                 return err;
2114
2115         mlx5_cmd_free_uar(dev->mdev, idx);
2116
2117 free_bfreg:
2118         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2119
2120         return err;
2121 }
2122
2123 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2124 {
2125         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2126         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2127         unsigned long command;
2128         phys_addr_t pfn;
2129
2130         command = get_command(vma->vm_pgoff);
2131         switch (command) {
2132         case MLX5_IB_MMAP_WC_PAGE:
2133         case MLX5_IB_MMAP_NC_PAGE:
2134         case MLX5_IB_MMAP_REGULAR_PAGE:
2135         case MLX5_IB_MMAP_ALLOC_WC:
2136                 return uar_mmap(dev, command, vma, context);
2137
2138         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2139                 return -ENOSYS;
2140
2141         case MLX5_IB_MMAP_CORE_CLOCK:
2142                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2143                         return -EINVAL;
2144
2145                 if (vma->vm_flags & VM_WRITE)
2146                         return -EPERM;
2147
2148                 /* Don't expose to user-space information it shouldn't have */
2149                 if (PAGE_SIZE > 4096)
2150                         return -EOPNOTSUPP;
2151
2152                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2153                 pfn = (dev->mdev->iseg_base +
2154                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2155                         PAGE_SHIFT;
2156                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2157                                        PAGE_SIZE, vma->vm_page_prot))
2158                         return -EAGAIN;
2159
2160                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2161                             vma->vm_start,
2162                             (unsigned long long)pfn << PAGE_SHIFT);
2163                 break;
2164         case MLX5_IB_MMAP_CLOCK_INFO:
2165                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2166
2167         default:
2168                 return -EINVAL;
2169         }
2170
2171         return 0;
2172 }
2173
2174 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2175                                       struct ib_ucontext *context,
2176                                       struct ib_udata *udata)
2177 {
2178         struct mlx5_ib_alloc_pd_resp resp;
2179         struct mlx5_ib_pd *pd;
2180         int err;
2181
2182         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2183         if (!pd)
2184                 return ERR_PTR(-ENOMEM);
2185
2186         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2187         if (err) {
2188                 kfree(pd);
2189                 return ERR_PTR(err);
2190         }
2191
2192         if (context) {
2193                 resp.pdn = pd->pdn;
2194                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2195                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2196                         kfree(pd);
2197                         return ERR_PTR(-EFAULT);
2198                 }
2199         }
2200
2201         return &pd->ibpd;
2202 }
2203
2204 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2205 {
2206         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2207         struct mlx5_ib_pd *mpd = to_mpd(pd);
2208
2209         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2210         kfree(mpd);
2211
2212         return 0;
2213 }
2214
2215 enum {
2216         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2217         MATCH_CRITERIA_ENABLE_MISC_BIT,
2218         MATCH_CRITERIA_ENABLE_INNER_BIT
2219 };
2220
2221 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2222         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2223                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2224
2225 static u8 get_match_criteria_enable(u32 *match_criteria)
2226 {
2227         u8 match_criteria_enable;
2228
2229         match_criteria_enable =
2230                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2231                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2232         match_criteria_enable |=
2233                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2234                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2235         match_criteria_enable |=
2236                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2237                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2238
2239         return match_criteria_enable;
2240 }
2241
2242 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2243 {
2244         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2245         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2246 }
2247
2248 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2249                            bool inner)
2250 {
2251         if (inner) {
2252                 MLX5_SET(fte_match_set_misc,
2253                          misc_c, inner_ipv6_flow_label, mask);
2254                 MLX5_SET(fte_match_set_misc,
2255                          misc_v, inner_ipv6_flow_label, val);
2256         } else {
2257                 MLX5_SET(fte_match_set_misc,
2258                          misc_c, outer_ipv6_flow_label, mask);
2259                 MLX5_SET(fte_match_set_misc,
2260                          misc_v, outer_ipv6_flow_label, val);
2261         }
2262 }
2263
2264 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2265 {
2266         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2267         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2268         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2269         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2270 }
2271
2272 #define LAST_ETH_FIELD vlan_tag
2273 #define LAST_IB_FIELD sl
2274 #define LAST_IPV4_FIELD tos
2275 #define LAST_IPV6_FIELD traffic_class
2276 #define LAST_TCP_UDP_FIELD src_port
2277 #define LAST_TUNNEL_FIELD tunnel_id
2278 #define LAST_FLOW_TAG_FIELD tag_id
2279 #define LAST_DROP_FIELD size
2280
2281 /* Field is the last supported field */
2282 #define FIELDS_NOT_SUPPORTED(filter, field)\
2283         memchr_inv((void *)&filter.field  +\
2284                    sizeof(filter.field), 0,\
2285                    sizeof(filter) -\
2286                    offsetof(typeof(filter), field) -\
2287                    sizeof(filter.field))
2288
2289 #define IPV4_VERSION 4
2290 #define IPV6_VERSION 6
2291 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2292                            u32 *match_v, const union ib_flow_spec *ib_spec,
2293                            u32 *tag_id, bool *is_drop)
2294 {
2295         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2296                                            misc_parameters);
2297         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2298                                            misc_parameters);
2299         void *headers_c;
2300         void *headers_v;
2301         int match_ipv;
2302
2303         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2304                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2305                                          inner_headers);
2306                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2307                                          inner_headers);
2308                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2309                                         ft_field_support.inner_ip_version);
2310         } else {
2311                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2312                                          outer_headers);
2313                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2314                                          outer_headers);
2315                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2316                                         ft_field_support.outer_ip_version);
2317         }
2318
2319         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2320         case IB_FLOW_SPEC_ETH:
2321                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2322                         return -EOPNOTSUPP;
2323
2324                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2325                                              dmac_47_16),
2326                                 ib_spec->eth.mask.dst_mac);
2327                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2328                                              dmac_47_16),
2329                                 ib_spec->eth.val.dst_mac);
2330
2331                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2332                                              smac_47_16),
2333                                 ib_spec->eth.mask.src_mac);
2334                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2335                                              smac_47_16),
2336                                 ib_spec->eth.val.src_mac);
2337
2338                 if (ib_spec->eth.mask.vlan_tag) {
2339                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2340                                  cvlan_tag, 1);
2341                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2342                                  cvlan_tag, 1);
2343
2344                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2345                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2346                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2347                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2348
2349                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2350                                  first_cfi,
2351                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2352                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2353                                  first_cfi,
2354                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2355
2356                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2357                                  first_prio,
2358                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2359                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2360                                  first_prio,
2361                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2362                 }
2363                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2364                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2365                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2366                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2367                 break;
2368         case IB_FLOW_SPEC_IPV4:
2369                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2370                         return -EOPNOTSUPP;
2371
2372                 if (match_ipv) {
2373                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2374                                  ip_version, 0xf);
2375                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2376                                  ip_version, IPV4_VERSION);
2377                 } else {
2378                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2379                                  ethertype, 0xffff);
2380                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2381                                  ethertype, ETH_P_IP);
2382                 }
2383
2384                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2385                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2386                        &ib_spec->ipv4.mask.src_ip,
2387                        sizeof(ib_spec->ipv4.mask.src_ip));
2388                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2389                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2390                        &ib_spec->ipv4.val.src_ip,
2391                        sizeof(ib_spec->ipv4.val.src_ip));
2392                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2393                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2394                        &ib_spec->ipv4.mask.dst_ip,
2395                        sizeof(ib_spec->ipv4.mask.dst_ip));
2396                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2397                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2398                        &ib_spec->ipv4.val.dst_ip,
2399                        sizeof(ib_spec->ipv4.val.dst_ip));
2400
2401                 set_tos(headers_c, headers_v,
2402                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2403
2404                 set_proto(headers_c, headers_v,
2405                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2406                 break;
2407         case IB_FLOW_SPEC_IPV6:
2408                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2409                         return -EOPNOTSUPP;
2410
2411                 if (match_ipv) {
2412                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2413                                  ip_version, 0xf);
2414                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2415                                  ip_version, IPV6_VERSION);
2416                 } else {
2417                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2418                                  ethertype, 0xffff);
2419                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2420                                  ethertype, ETH_P_IPV6);
2421                 }
2422
2423                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2424                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2425                        &ib_spec->ipv6.mask.src_ip,
2426                        sizeof(ib_spec->ipv6.mask.src_ip));
2427                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2428                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2429                        &ib_spec->ipv6.val.src_ip,
2430                        sizeof(ib_spec->ipv6.val.src_ip));
2431                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2432                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2433                        &ib_spec->ipv6.mask.dst_ip,
2434                        sizeof(ib_spec->ipv6.mask.dst_ip));
2435                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2436                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2437                        &ib_spec->ipv6.val.dst_ip,
2438                        sizeof(ib_spec->ipv6.val.dst_ip));
2439
2440                 set_tos(headers_c, headers_v,
2441                         ib_spec->ipv6.mask.traffic_class,
2442                         ib_spec->ipv6.val.traffic_class);
2443
2444                 set_proto(headers_c, headers_v,
2445                           ib_spec->ipv6.mask.next_hdr,
2446                           ib_spec->ipv6.val.next_hdr);
2447
2448                 set_flow_label(misc_params_c, misc_params_v,
2449                                ntohl(ib_spec->ipv6.mask.flow_label),
2450                                ntohl(ib_spec->ipv6.val.flow_label),
2451                                ib_spec->type & IB_FLOW_SPEC_INNER);
2452
2453                 break;
2454         case IB_FLOW_SPEC_TCP:
2455                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2456                                          LAST_TCP_UDP_FIELD))
2457                         return -EOPNOTSUPP;
2458
2459                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2460                          0xff);
2461                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2462                          IPPROTO_TCP);
2463
2464                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2465                          ntohs(ib_spec->tcp_udp.mask.src_port));
2466                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2467                          ntohs(ib_spec->tcp_udp.val.src_port));
2468
2469                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2470                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2471                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2472                          ntohs(ib_spec->tcp_udp.val.dst_port));
2473                 break;
2474         case IB_FLOW_SPEC_UDP:
2475                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2476                                          LAST_TCP_UDP_FIELD))
2477                         return -EOPNOTSUPP;
2478
2479                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2480                          0xff);
2481                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2482                          IPPROTO_UDP);
2483
2484                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2485                          ntohs(ib_spec->tcp_udp.mask.src_port));
2486                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2487                          ntohs(ib_spec->tcp_udp.val.src_port));
2488
2489                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2490                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2491                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2492                          ntohs(ib_spec->tcp_udp.val.dst_port));
2493                 break;
2494         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2495                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2496                                          LAST_TUNNEL_FIELD))
2497                         return -EOPNOTSUPP;
2498
2499                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2500                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2501                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2502                          ntohl(ib_spec->tunnel.val.tunnel_id));
2503                 break;
2504         case IB_FLOW_SPEC_ACTION_TAG:
2505                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2506                                          LAST_FLOW_TAG_FIELD))
2507                         return -EOPNOTSUPP;
2508                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2509                         return -EINVAL;
2510
2511                 *tag_id = ib_spec->flow_tag.tag_id;
2512                 break;
2513         case IB_FLOW_SPEC_ACTION_DROP:
2514                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2515                                          LAST_DROP_FIELD))
2516                         return -EOPNOTSUPP;
2517                 *is_drop = true;
2518                 break;
2519         default:
2520                 return -EINVAL;
2521         }
2522
2523         return 0;
2524 }
2525
2526 /* If a flow could catch both multicast and unicast packets,
2527  * it won't fall into the multicast flow steering table and this rule
2528  * could steal other multicast packets.
2529  */
2530 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2531 {
2532         union ib_flow_spec *flow_spec;
2533
2534         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2535             ib_attr->num_of_specs < 1)
2536                 return false;
2537
2538         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2539         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2540                 struct ib_flow_spec_ipv4 *ipv4_spec;
2541
2542                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2543                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2544                         return true;
2545
2546                 return false;
2547         }
2548
2549         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2550                 struct ib_flow_spec_eth *eth_spec;
2551
2552                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2553                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2554                        is_multicast_ether_addr(eth_spec->val.dst_mac);
2555         }
2556
2557         return false;
2558 }
2559
2560 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2561                                const struct ib_flow_attr *flow_attr,
2562                                bool check_inner)
2563 {
2564         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2565         int match_ipv = check_inner ?
2566                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2567                                         ft_field_support.inner_ip_version) :
2568                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2569                                         ft_field_support.outer_ip_version);
2570         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2571         bool ipv4_spec_valid, ipv6_spec_valid;
2572         unsigned int ip_spec_type = 0;
2573         bool has_ethertype = false;
2574         unsigned int spec_index;
2575         bool mask_valid = true;
2576         u16 eth_type = 0;
2577         bool type_valid;
2578
2579         /* Validate that ethertype is correct */
2580         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2581                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2582                     ib_spec->eth.mask.ether_type) {
2583                         mask_valid = (ib_spec->eth.mask.ether_type ==
2584                                       htons(0xffff));
2585                         has_ethertype = true;
2586                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2587                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2588                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2589                         ip_spec_type = ib_spec->type;
2590                 }
2591                 ib_spec = (void *)ib_spec + ib_spec->size;
2592         }
2593
2594         type_valid = (!has_ethertype) || (!ip_spec_type);
2595         if (!type_valid && mask_valid) {
2596                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2597                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2598                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2599                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2600
2601                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2602                              (((eth_type == ETH_P_MPLS_UC) ||
2603                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2604         }
2605
2606         return type_valid;
2607 }
2608
2609 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2610                           const struct ib_flow_attr *flow_attr)
2611 {
2612         return is_valid_ethertype(mdev, flow_attr, false) &&
2613                is_valid_ethertype(mdev, flow_attr, true);
2614 }
2615
2616 static void put_flow_table(struct mlx5_ib_dev *dev,
2617                            struct mlx5_ib_flow_prio *prio, bool ft_added)
2618 {
2619         prio->refcount -= !!ft_added;
2620         if (!prio->refcount) {
2621                 mlx5_destroy_flow_table(prio->flow_table);
2622                 prio->flow_table = NULL;
2623         }
2624 }
2625
2626 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2627 {
2628         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2629         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2630                                                           struct mlx5_ib_flow_handler,
2631                                                           ibflow);
2632         struct mlx5_ib_flow_handler *iter, *tmp;
2633
2634         mutex_lock(&dev->flow_db.lock);
2635
2636         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2637                 mlx5_del_flow_rules(iter->rule);
2638                 put_flow_table(dev, iter->prio, true);
2639                 list_del(&iter->list);
2640                 kfree(iter);
2641         }
2642
2643         mlx5_del_flow_rules(handler->rule);
2644         put_flow_table(dev, handler->prio, true);
2645         mutex_unlock(&dev->flow_db.lock);
2646
2647         kfree(handler);
2648
2649         return 0;
2650 }
2651
2652 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2653 {
2654         priority *= 2;
2655         if (!dont_trap)
2656                 priority++;
2657         return priority;
2658 }
2659
2660 enum flow_table_type {
2661         MLX5_IB_FT_RX,
2662         MLX5_IB_FT_TX
2663 };
2664
2665 #define MLX5_FS_MAX_TYPES        6
2666 #define MLX5_FS_MAX_ENTRIES      BIT(16)
2667 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2668                                                 struct ib_flow_attr *flow_attr,
2669                                                 enum flow_table_type ft_type)
2670 {
2671         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2672         struct mlx5_flow_namespace *ns = NULL;
2673         struct mlx5_ib_flow_prio *prio;
2674         struct mlx5_flow_table *ft;
2675         int max_table_size;
2676         int num_entries;
2677         int num_groups;
2678         int priority;
2679         int err = 0;
2680
2681         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2682                                                        log_max_ft_size));
2683         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2684                 if (flow_is_multicast_only(flow_attr) &&
2685                     !dont_trap)
2686                         priority = MLX5_IB_FLOW_MCAST_PRIO;
2687                 else
2688                         priority = ib_prio_to_core_prio(flow_attr->priority,
2689                                                         dont_trap);
2690                 ns = mlx5_get_flow_namespace(dev->mdev,
2691                                              MLX5_FLOW_NAMESPACE_BYPASS);
2692                 num_entries = MLX5_FS_MAX_ENTRIES;
2693                 num_groups = MLX5_FS_MAX_TYPES;
2694                 prio = &dev->flow_db.prios[priority];
2695         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2696                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2697                 ns = mlx5_get_flow_namespace(dev->mdev,
2698                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
2699                 build_leftovers_ft_param(&priority,
2700                                          &num_entries,
2701                                          &num_groups);
2702                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2703         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2704                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2705                                         allow_sniffer_and_nic_rx_shared_tir))
2706                         return ERR_PTR(-ENOTSUPP);
2707
2708                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2709                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2710                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2711
2712                 prio = &dev->flow_db.sniffer[ft_type];
2713                 priority = 0;
2714                 num_entries = 1;
2715                 num_groups = 1;
2716         }
2717
2718         if (!ns)
2719                 return ERR_PTR(-ENOTSUPP);
2720
2721         if (num_entries > max_table_size)
2722                 return ERR_PTR(-ENOMEM);
2723
2724         ft = prio->flow_table;
2725         if (!ft) {
2726                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2727                                                          num_entries,
2728                                                          num_groups,
2729                                                          0, 0);
2730
2731                 if (!IS_ERR(ft)) {
2732                         prio->refcount = 0;
2733                         prio->flow_table = ft;
2734                 } else {
2735                         err = PTR_ERR(ft);
2736                 }
2737         }
2738
2739         return err ? ERR_PTR(err) : prio;
2740 }
2741
2742 static void set_underlay_qp(struct mlx5_ib_dev *dev,
2743                             struct mlx5_flow_spec *spec,
2744                             u32 underlay_qpn)
2745 {
2746         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
2747                                            spec->match_criteria,
2748                                            misc_parameters);
2749         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2750                                            misc_parameters);
2751
2752         if (underlay_qpn &&
2753             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2754                                       ft_field_support.bth_dst_qp)) {
2755                 MLX5_SET(fte_match_set_misc,
2756                          misc_params_v, bth_dst_qp, underlay_qpn);
2757                 MLX5_SET(fte_match_set_misc,
2758                          misc_params_c, bth_dst_qp, 0xffffff);
2759         }
2760 }
2761
2762 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
2763                                                       struct mlx5_ib_flow_prio *ft_prio,
2764                                                       const struct ib_flow_attr *flow_attr,
2765                                                       struct mlx5_flow_destination *dst,
2766                                                       u32 underlay_qpn)
2767 {
2768         struct mlx5_flow_table  *ft = ft_prio->flow_table;
2769         struct mlx5_ib_flow_handler *handler;
2770         struct mlx5_flow_act flow_act = {0};
2771         struct mlx5_flow_spec *spec;
2772         struct mlx5_flow_destination *rule_dst = dst;
2773         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2774         unsigned int spec_index;
2775         u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2776         bool is_drop = false;
2777         int err = 0;
2778         int dest_num = 1;
2779
2780         if (!is_valid_attr(dev->mdev, flow_attr))
2781                 return ERR_PTR(-EINVAL);
2782
2783         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2784         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2785         if (!handler || !spec) {
2786                 err = -ENOMEM;
2787                 goto free;
2788         }
2789
2790         INIT_LIST_HEAD(&handler->list);
2791
2792         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2793                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
2794                                       spec->match_value,
2795                                       ib_flow, &flow_tag, &is_drop);
2796                 if (err < 0)
2797                         goto free;
2798
2799                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2800         }
2801
2802         if (!flow_is_multicast_only(flow_attr))
2803                 set_underlay_qp(dev, spec, underlay_qpn);
2804
2805         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2806         if (is_drop) {
2807                 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2808                 rule_dst = NULL;
2809                 dest_num = 0;
2810         } else {
2811                 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2812                     MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2813         }
2814
2815         if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2816             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2817              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2818                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2819                              flow_tag, flow_attr->type);
2820                 err = -EINVAL;
2821                 goto free;
2822         }
2823         flow_act.flow_tag = flow_tag;
2824         handler->rule = mlx5_add_flow_rules(ft, spec,
2825                                             &flow_act,
2826                                             rule_dst, dest_num);
2827
2828         if (IS_ERR(handler->rule)) {
2829                 err = PTR_ERR(handler->rule);
2830                 goto free;
2831         }
2832
2833         ft_prio->refcount++;
2834         handler->prio = ft_prio;
2835
2836         ft_prio->flow_table = ft;
2837 free:
2838         if (err)
2839                 kfree(handler);
2840         kvfree(spec);
2841         return err ? ERR_PTR(err) : handler;
2842 }
2843
2844 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2845                                                      struct mlx5_ib_flow_prio *ft_prio,
2846                                                      const struct ib_flow_attr *flow_attr,
2847                                                      struct mlx5_flow_destination *dst)
2848 {
2849         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
2850 }
2851
2852 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2853                                                           struct mlx5_ib_flow_prio *ft_prio,
2854                                                           struct ib_flow_attr *flow_attr,
2855                                                           struct mlx5_flow_destination *dst)
2856 {
2857         struct mlx5_ib_flow_handler *handler_dst = NULL;
2858         struct mlx5_ib_flow_handler *handler = NULL;
2859
2860         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2861         if (!IS_ERR(handler)) {
2862                 handler_dst = create_flow_rule(dev, ft_prio,
2863                                                flow_attr, dst);
2864                 if (IS_ERR(handler_dst)) {
2865                         mlx5_del_flow_rules(handler->rule);
2866                         ft_prio->refcount--;
2867                         kfree(handler);
2868                         handler = handler_dst;
2869                 } else {
2870                         list_add(&handler_dst->list, &handler->list);
2871                 }
2872         }
2873
2874         return handler;
2875 }
2876 enum {
2877         LEFTOVERS_MC,
2878         LEFTOVERS_UC,
2879 };
2880
2881 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2882                                                           struct mlx5_ib_flow_prio *ft_prio,
2883                                                           struct ib_flow_attr *flow_attr,
2884                                                           struct mlx5_flow_destination *dst)
2885 {
2886         struct mlx5_ib_flow_handler *handler_ucast = NULL;
2887         struct mlx5_ib_flow_handler *handler = NULL;
2888
2889         static struct {
2890                 struct ib_flow_attr     flow_attr;
2891                 struct ib_flow_spec_eth eth_flow;
2892         } leftovers_specs[] = {
2893                 [LEFTOVERS_MC] = {
2894                         .flow_attr = {
2895                                 .num_of_specs = 1,
2896                                 .size = sizeof(leftovers_specs[0])
2897                         },
2898                         .eth_flow = {
2899                                 .type = IB_FLOW_SPEC_ETH,
2900                                 .size = sizeof(struct ib_flow_spec_eth),
2901                                 .mask = {.dst_mac = {0x1} },
2902                                 .val =  {.dst_mac = {0x1} }
2903                         }
2904                 },
2905                 [LEFTOVERS_UC] = {
2906                         .flow_attr = {
2907                                 .num_of_specs = 1,
2908                                 .size = sizeof(leftovers_specs[0])
2909                         },
2910                         .eth_flow = {
2911                                 .type = IB_FLOW_SPEC_ETH,
2912                                 .size = sizeof(struct ib_flow_spec_eth),
2913                                 .mask = {.dst_mac = {0x1} },
2914                                 .val = {.dst_mac = {} }
2915                         }
2916                 }
2917         };
2918
2919         handler = create_flow_rule(dev, ft_prio,
2920                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
2921                                    dst);
2922         if (!IS_ERR(handler) &&
2923             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2924                 handler_ucast = create_flow_rule(dev, ft_prio,
2925                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
2926                                                  dst);
2927                 if (IS_ERR(handler_ucast)) {
2928                         mlx5_del_flow_rules(handler->rule);
2929                         ft_prio->refcount--;
2930                         kfree(handler);
2931                         handler = handler_ucast;
2932                 } else {
2933                         list_add(&handler_ucast->list, &handler->list);
2934                 }
2935         }
2936
2937         return handler;
2938 }
2939
2940 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2941                                                         struct mlx5_ib_flow_prio *ft_rx,
2942                                                         struct mlx5_ib_flow_prio *ft_tx,
2943                                                         struct mlx5_flow_destination *dst)
2944 {
2945         struct mlx5_ib_flow_handler *handler_rx;
2946         struct mlx5_ib_flow_handler *handler_tx;
2947         int err;
2948         static const struct ib_flow_attr flow_attr  = {
2949                 .num_of_specs = 0,
2950                 .size = sizeof(flow_attr)
2951         };
2952
2953         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2954         if (IS_ERR(handler_rx)) {
2955                 err = PTR_ERR(handler_rx);
2956                 goto err;
2957         }
2958
2959         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2960         if (IS_ERR(handler_tx)) {
2961                 err = PTR_ERR(handler_tx);
2962                 goto err_tx;
2963         }
2964
2965         list_add(&handler_tx->list, &handler_rx->list);
2966
2967         return handler_rx;
2968
2969 err_tx:
2970         mlx5_del_flow_rules(handler_rx->rule);
2971         ft_rx->refcount--;
2972         kfree(handler_rx);
2973 err:
2974         return ERR_PTR(err);
2975 }
2976
2977 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2978                                            struct ib_flow_attr *flow_attr,
2979                                            int domain)
2980 {
2981         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2982         struct mlx5_ib_qp *mqp = to_mqp(qp);
2983         struct mlx5_ib_flow_handler *handler = NULL;
2984         struct mlx5_flow_destination *dst = NULL;
2985         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2986         struct mlx5_ib_flow_prio *ft_prio;
2987         int err;
2988         int underlay_qpn;
2989
2990         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2991                 return ERR_PTR(-ENOMEM);
2992
2993         if (domain != IB_FLOW_DOMAIN_USER ||
2994             flow_attr->port > dev->num_ports ||
2995             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2996                 return ERR_PTR(-EINVAL);
2997
2998         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2999         if (!dst)
3000                 return ERR_PTR(-ENOMEM);
3001
3002         mutex_lock(&dev->flow_db.lock);
3003
3004         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
3005         if (IS_ERR(ft_prio)) {
3006                 err = PTR_ERR(ft_prio);
3007                 goto unlock;
3008         }
3009         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3010                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3011                 if (IS_ERR(ft_prio_tx)) {
3012                         err = PTR_ERR(ft_prio_tx);
3013                         ft_prio_tx = NULL;
3014                         goto destroy_ft;
3015                 }
3016         }
3017
3018         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3019         if (mqp->flags & MLX5_IB_QP_RSS)
3020                 dst->tir_num = mqp->rss_qp.tirn;
3021         else
3022                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3023
3024         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3025                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3026                         handler = create_dont_trap_rule(dev, ft_prio,
3027                                                         flow_attr, dst);
3028                 } else {
3029                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3030                                         mqp->underlay_qpn : 0;
3031                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3032                                                     dst, underlay_qpn);
3033                 }
3034         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3035                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3036                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3037                                                 dst);
3038         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3039                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3040         } else {
3041                 err = -EINVAL;
3042                 goto destroy_ft;
3043         }
3044
3045         if (IS_ERR(handler)) {
3046                 err = PTR_ERR(handler);
3047                 handler = NULL;
3048                 goto destroy_ft;
3049         }
3050
3051         mutex_unlock(&dev->flow_db.lock);
3052         kfree(dst);
3053
3054         return &handler->ibflow;
3055
3056 destroy_ft:
3057         put_flow_table(dev, ft_prio, false);
3058         if (ft_prio_tx)
3059                 put_flow_table(dev, ft_prio_tx, false);
3060 unlock:
3061         mutex_unlock(&dev->flow_db.lock);
3062         kfree(dst);
3063         kfree(handler);
3064         return ERR_PTR(err);
3065 }
3066
3067 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3068 {
3069         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3070         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
3071         int err;
3072
3073         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3074                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3075                 return -EOPNOTSUPP;
3076         }
3077
3078         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
3079         if (err)
3080                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3081                              ibqp->qp_num, gid->raw);
3082
3083         return err;
3084 }
3085
3086 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3087 {
3088         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3089         int err;
3090
3091         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
3092         if (err)
3093                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3094                              ibqp->qp_num, gid->raw);
3095
3096         return err;
3097 }
3098
3099 static int init_node_data(struct mlx5_ib_dev *dev)
3100 {
3101         int err;
3102
3103         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
3104         if (err)
3105                 return err;
3106
3107         dev->mdev->rev_id = dev->mdev->pdev->revision;
3108
3109         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
3110 }
3111
3112 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3113                              char *buf)
3114 {
3115         struct mlx5_ib_dev *dev =
3116                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3117
3118         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
3119 }
3120
3121 static ssize_t show_reg_pages(struct device *device,
3122                               struct device_attribute *attr, char *buf)
3123 {
3124         struct mlx5_ib_dev *dev =
3125                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3126
3127         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
3128 }
3129
3130 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3131                         char *buf)
3132 {
3133         struct mlx5_ib_dev *dev =
3134                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3135         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
3136 }
3137
3138 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3139                         char *buf)
3140 {
3141         struct mlx5_ib_dev *dev =
3142                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3143         return sprintf(buf, "%x\n", dev->mdev->rev_id);
3144 }
3145
3146 static ssize_t show_board(struct device *device, struct device_attribute *attr,
3147                           char *buf)
3148 {
3149         struct mlx5_ib_dev *dev =
3150                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3151         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
3152                        dev->mdev->board_id);
3153 }
3154
3155 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
3156 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
3157 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
3158 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3159 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3160
3161 static struct device_attribute *mlx5_class_attributes[] = {
3162         &dev_attr_hw_rev,
3163         &dev_attr_hca_type,
3164         &dev_attr_board_id,
3165         &dev_attr_fw_pages,
3166         &dev_attr_reg_pages,
3167 };
3168
3169 static void pkey_change_handler(struct work_struct *work)
3170 {
3171         struct mlx5_ib_port_resources *ports =
3172                 container_of(work, struct mlx5_ib_port_resources,
3173                              pkey_change_work);
3174
3175         mutex_lock(&ports->devr->mutex);
3176         mlx5_ib_gsi_pkey_change(ports->gsi);
3177         mutex_unlock(&ports->devr->mutex);
3178 }
3179
3180 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3181 {
3182         struct mlx5_ib_qp *mqp;
3183         struct mlx5_ib_cq *send_mcq, *recv_mcq;
3184         struct mlx5_core_cq *mcq;
3185         struct list_head cq_armed_list;
3186         unsigned long flags_qp;
3187         unsigned long flags_cq;
3188         unsigned long flags;
3189
3190         INIT_LIST_HEAD(&cq_armed_list);
3191
3192         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3193         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3194         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3195                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3196                 if (mqp->sq.tail != mqp->sq.head) {
3197                         send_mcq = to_mcq(mqp->ibqp.send_cq);
3198                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
3199                         if (send_mcq->mcq.comp &&
3200                             mqp->ibqp.send_cq->comp_handler) {
3201                                 if (!send_mcq->mcq.reset_notify_added) {
3202                                         send_mcq->mcq.reset_notify_added = 1;
3203                                         list_add_tail(&send_mcq->mcq.reset_notify,
3204                                                       &cq_armed_list);
3205                                 }
3206                         }
3207                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3208                 }
3209                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3210                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3211                 /* no handling is needed for SRQ */
3212                 if (!mqp->ibqp.srq) {
3213                         if (mqp->rq.tail != mqp->rq.head) {
3214                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3215                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3216                                 if (recv_mcq->mcq.comp &&
3217                                     mqp->ibqp.recv_cq->comp_handler) {
3218                                         if (!recv_mcq->mcq.reset_notify_added) {
3219                                                 recv_mcq->mcq.reset_notify_added = 1;
3220                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
3221                                                               &cq_armed_list);
3222                                         }
3223                                 }
3224                                 spin_unlock_irqrestore(&recv_mcq->lock,
3225                                                        flags_cq);
3226                         }
3227                 }
3228                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3229         }
3230         /*At that point all inflight post send were put to be executed as of we
3231          * lock/unlock above locks Now need to arm all involved CQs.
3232          */
3233         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3234                 mcq->comp(mcq);
3235         }
3236         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3237 }
3238
3239 static void delay_drop_handler(struct work_struct *work)
3240 {
3241         int err;
3242         struct mlx5_ib_delay_drop *delay_drop =
3243                 container_of(work, struct mlx5_ib_delay_drop,
3244                              delay_drop_work);
3245
3246         atomic_inc(&delay_drop->events_cnt);
3247
3248         mutex_lock(&delay_drop->lock);
3249         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3250                                        delay_drop->timeout);
3251         if (err) {
3252                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3253                              delay_drop->timeout);
3254                 delay_drop->activate = false;
3255         }
3256         mutex_unlock(&delay_drop->lock);
3257 }
3258
3259 static void mlx5_ib_handle_event(struct work_struct *_work)
3260 {
3261         struct mlx5_ib_event_work *work =
3262                 container_of(_work, struct mlx5_ib_event_work, work);
3263         struct mlx5_ib_dev *ibdev;
3264         struct ib_event ibev;
3265         bool fatal = false;
3266         u8 port = 0;
3267
3268         if (mlx5_core_is_mp_slave(work->dev)) {
3269                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3270                 if (!ibdev)
3271                         goto out;
3272         } else {
3273                 ibdev = work->context;
3274         }
3275
3276         switch (work->event) {
3277         case MLX5_DEV_EVENT_SYS_ERROR:
3278                 ibev.event = IB_EVENT_DEVICE_FATAL;
3279                 mlx5_ib_handle_internal_error(ibdev);
3280                 fatal = true;
3281                 break;
3282
3283         case MLX5_DEV_EVENT_PORT_UP:
3284         case MLX5_DEV_EVENT_PORT_DOWN:
3285         case MLX5_DEV_EVENT_PORT_INITIALIZED:
3286                 port = (u8)work->param;
3287
3288                 /* In RoCE, port up/down events are handled in
3289                  * mlx5_netdev_event().
3290                  */
3291                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3292                         IB_LINK_LAYER_ETHERNET)
3293                         goto out;
3294
3295                 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
3296                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3297                 break;
3298
3299         case MLX5_DEV_EVENT_LID_CHANGE:
3300                 ibev.event = IB_EVENT_LID_CHANGE;
3301                 port = (u8)work->param;
3302                 break;
3303
3304         case MLX5_DEV_EVENT_PKEY_CHANGE:
3305                 ibev.event = IB_EVENT_PKEY_CHANGE;
3306                 port = (u8)work->param;
3307
3308                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
3309                 break;
3310
3311         case MLX5_DEV_EVENT_GUID_CHANGE:
3312                 ibev.event = IB_EVENT_GID_CHANGE;
3313                 port = (u8)work->param;
3314                 break;
3315
3316         case MLX5_DEV_EVENT_CLIENT_REREG:
3317                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
3318                 port = (u8)work->param;
3319                 break;
3320         case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3321                 schedule_work(&ibdev->delay_drop.delay_drop_work);
3322                 goto out;
3323         default:
3324                 goto out;
3325         }
3326
3327         ibev.device           = &ibdev->ib_dev;
3328         ibev.element.port_num = port;
3329
3330         if (port < 1 || port > ibdev->num_ports) {
3331                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
3332                 goto out;
3333         }
3334
3335         if (ibdev->ib_active)
3336                 ib_dispatch_event(&ibev);
3337
3338         if (fatal)
3339                 ibdev->ib_active = false;
3340 out:
3341         kfree(work);
3342 }
3343
3344 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3345                           enum mlx5_dev_event event, unsigned long param)
3346 {
3347         struct mlx5_ib_event_work *work;
3348
3349         work = kmalloc(sizeof(*work), GFP_ATOMIC);
3350         if (!work)
3351                 return;
3352
3353         INIT_WORK(&work->work, mlx5_ib_handle_event);
3354         work->dev = dev;
3355         work->param = param;
3356         work->context = context;
3357         work->event = event;
3358
3359         queue_work(mlx5_ib_event_wq, &work->work);
3360 }
3361
3362 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3363 {
3364         struct mlx5_hca_vport_context vport_ctx;
3365         int err;
3366         int port;
3367
3368         for (port = 1; port <= dev->num_ports; port++) {
3369                 dev->mdev->port_caps[port - 1].has_smi = false;
3370                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3371                     MLX5_CAP_PORT_TYPE_IB) {
3372                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3373                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3374                                                                    port, 0,
3375                                                                    &vport_ctx);
3376                                 if (err) {
3377                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3378                                                     port, err);
3379                                         return err;
3380                                 }
3381                                 dev->mdev->port_caps[port - 1].has_smi =
3382                                         vport_ctx.has_smi;
3383                         } else {
3384                                 dev->mdev->port_caps[port - 1].has_smi = true;
3385                         }
3386                 }
3387         }
3388         return 0;
3389 }
3390
3391 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3392 {
3393         int port;
3394
3395         for (port = 1; port <= dev->num_ports; port++)
3396                 mlx5_query_ext_port_caps(dev, port);
3397 }
3398
3399 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
3400 {
3401         struct ib_device_attr *dprops = NULL;
3402         struct ib_port_attr *pprops = NULL;
3403         int err = -ENOMEM;
3404         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
3405
3406         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3407         if (!pprops)
3408                 goto out;
3409
3410         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3411         if (!dprops)
3412                 goto out;
3413
3414         err = set_has_smi_cap(dev);
3415         if (err)
3416                 goto out;
3417
3418         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
3419         if (err) {
3420                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3421                 goto out;
3422         }
3423
3424         memset(pprops, 0, sizeof(*pprops));
3425         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3426         if (err) {
3427                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3428                              port, err);
3429                 goto out;
3430         }
3431
3432         dev->mdev->port_caps[port - 1].pkey_table_len =
3433                                         dprops->max_pkeys;
3434         dev->mdev->port_caps[port - 1].gid_table_len =
3435                                         pprops->gid_tbl_len;
3436         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3437                     port, dprops->max_pkeys, pprops->gid_tbl_len);
3438
3439 out:
3440         kfree(pprops);
3441         kfree(dprops);
3442
3443         return err;
3444 }
3445
3446 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3447 {
3448         int err;
3449
3450         err = mlx5_mr_cache_cleanup(dev);
3451         if (err)
3452                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3453
3454         mlx5_ib_destroy_qp(dev->umrc.qp);
3455         ib_free_cq(dev->umrc.cq);
3456         ib_dealloc_pd(dev->umrc.pd);
3457 }
3458
3459 enum {
3460         MAX_UMR_WR = 128,
3461 };
3462
3463 static int create_umr_res(struct mlx5_ib_dev *dev)
3464 {
3465         struct ib_qp_init_attr *init_attr = NULL;
3466         struct ib_qp_attr *attr = NULL;
3467         struct ib_pd *pd;
3468         struct ib_cq *cq;
3469         struct ib_qp *qp;
3470         int ret;
3471
3472         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3473         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3474         if (!attr || !init_attr) {
3475                 ret = -ENOMEM;
3476                 goto error_0;
3477         }
3478
3479         pd = ib_alloc_pd(&dev->ib_dev, 0);
3480         if (IS_ERR(pd)) {
3481                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3482                 ret = PTR_ERR(pd);
3483                 goto error_0;
3484         }
3485
3486         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
3487         if (IS_ERR(cq)) {
3488                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3489                 ret = PTR_ERR(cq);
3490                 goto error_2;
3491         }
3492
3493         init_attr->send_cq = cq;
3494         init_attr->recv_cq = cq;
3495         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3496         init_attr->cap.max_send_wr = MAX_UMR_WR;
3497         init_attr->cap.max_send_sge = 1;
3498         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3499         init_attr->port_num = 1;
3500         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3501         if (IS_ERR(qp)) {
3502                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3503                 ret = PTR_ERR(qp);
3504                 goto error_3;
3505         }
3506         qp->device     = &dev->ib_dev;
3507         qp->real_qp    = qp;
3508         qp->uobject    = NULL;
3509         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
3510         qp->send_cq    = init_attr->send_cq;
3511         qp->recv_cq    = init_attr->recv_cq;
3512
3513         attr->qp_state = IB_QPS_INIT;
3514         attr->port_num = 1;
3515         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3516                                 IB_QP_PORT, NULL);
3517         if (ret) {
3518                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3519                 goto error_4;
3520         }
3521
3522         memset(attr, 0, sizeof(*attr));
3523         attr->qp_state = IB_QPS_RTR;
3524         attr->path_mtu = IB_MTU_256;
3525
3526         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3527         if (ret) {
3528                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3529                 goto error_4;
3530         }
3531
3532         memset(attr, 0, sizeof(*attr));
3533         attr->qp_state = IB_QPS_RTS;
3534         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3535         if (ret) {
3536                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3537                 goto error_4;
3538         }
3539
3540         dev->umrc.qp = qp;
3541         dev->umrc.cq = cq;
3542         dev->umrc.pd = pd;
3543
3544         sema_init(&dev->umrc.sem, MAX_UMR_WR);
3545         ret = mlx5_mr_cache_init(dev);
3546         if (ret) {
3547                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3548                 goto error_4;
3549         }
3550
3551         kfree(attr);
3552         kfree(init_attr);
3553
3554         return 0;
3555
3556 error_4:
3557         mlx5_ib_destroy_qp(qp);
3558
3559 error_3:
3560         ib_free_cq(cq);
3561
3562 error_2:
3563         ib_dealloc_pd(pd);
3564
3565 error_0:
3566         kfree(attr);
3567         kfree(init_attr);
3568         return ret;
3569 }
3570
3571 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
3572 {
3573         switch (umr_fence_cap) {
3574         case MLX5_CAP_UMR_FENCE_NONE:
3575                 return MLX5_FENCE_MODE_NONE;
3576         case MLX5_CAP_UMR_FENCE_SMALL:
3577                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
3578         default:
3579                 return MLX5_FENCE_MODE_STRONG_ORDERING;
3580         }
3581 }
3582
3583 static int create_dev_resources(struct mlx5_ib_resources *devr)
3584 {
3585         struct ib_srq_init_attr attr;
3586         struct mlx5_ib_dev *dev;
3587         struct ib_cq_init_attr cq_attr = {.cqe = 1};
3588         int port;
3589         int ret = 0;
3590
3591         dev = container_of(devr, struct mlx5_ib_dev, devr);
3592
3593         mutex_init(&devr->mutex);
3594
3595         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
3596         if (IS_ERR(devr->p0)) {
3597                 ret = PTR_ERR(devr->p0);
3598                 goto error0;
3599         }
3600         devr->p0->device  = &dev->ib_dev;
3601         devr->p0->uobject = NULL;
3602         atomic_set(&devr->p0->usecnt, 0);
3603
3604         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
3605         if (IS_ERR(devr->c0)) {
3606                 ret = PTR_ERR(devr->c0);
3607                 goto error1;
3608         }
3609         devr->c0->device        = &dev->ib_dev;
3610         devr->c0->uobject       = NULL;
3611         devr->c0->comp_handler  = NULL;
3612         devr->c0->event_handler = NULL;
3613         devr->c0->cq_context    = NULL;
3614         atomic_set(&devr->c0->usecnt, 0);
3615
3616         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3617         if (IS_ERR(devr->x0)) {
3618                 ret = PTR_ERR(devr->x0);
3619                 goto error2;
3620         }
3621         devr->x0->device = &dev->ib_dev;
3622         devr->x0->inode = NULL;
3623         atomic_set(&devr->x0->usecnt, 0);
3624         mutex_init(&devr->x0->tgt_qp_mutex);
3625         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3626
3627         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3628         if (IS_ERR(devr->x1)) {
3629                 ret = PTR_ERR(devr->x1);
3630                 goto error3;
3631         }
3632         devr->x1->device = &dev->ib_dev;
3633         devr->x1->inode = NULL;
3634         atomic_set(&devr->x1->usecnt, 0);
3635         mutex_init(&devr->x1->tgt_qp_mutex);
3636         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3637
3638         memset(&attr, 0, sizeof(attr));
3639         attr.attr.max_sge = 1;
3640         attr.attr.max_wr = 1;
3641         attr.srq_type = IB_SRQT_XRC;
3642         attr.ext.cq = devr->c0;
3643         attr.ext.xrc.xrcd = devr->x0;
3644
3645         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3646         if (IS_ERR(devr->s0)) {
3647                 ret = PTR_ERR(devr->s0);
3648                 goto error4;
3649         }
3650         devr->s0->device        = &dev->ib_dev;
3651         devr->s0->pd            = devr->p0;
3652         devr->s0->uobject       = NULL;
3653         devr->s0->event_handler = NULL;
3654         devr->s0->srq_context   = NULL;
3655         devr->s0->srq_type      = IB_SRQT_XRC;
3656         devr->s0->ext.xrc.xrcd  = devr->x0;
3657         devr->s0->ext.cq        = devr->c0;
3658         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3659         atomic_inc(&devr->s0->ext.cq->usecnt);
3660         atomic_inc(&devr->p0->usecnt);
3661         atomic_set(&devr->s0->usecnt, 0);
3662
3663         memset(&attr, 0, sizeof(attr));
3664         attr.attr.max_sge = 1;
3665         attr.attr.max_wr = 1;
3666         attr.srq_type = IB_SRQT_BASIC;
3667         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3668         if (IS_ERR(devr->s1)) {
3669                 ret = PTR_ERR(devr->s1);
3670                 goto error5;
3671         }
3672         devr->s1->device        = &dev->ib_dev;
3673         devr->s1->pd            = devr->p0;
3674         devr->s1->uobject       = NULL;
3675         devr->s1->event_handler = NULL;
3676         devr->s1->srq_context   = NULL;
3677         devr->s1->srq_type      = IB_SRQT_BASIC;
3678         devr->s1->ext.cq        = devr->c0;
3679         atomic_inc(&devr->p0->usecnt);
3680         atomic_set(&devr->s1->usecnt, 0);
3681
3682         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3683                 INIT_WORK(&devr->ports[port].pkey_change_work,
3684                           pkey_change_handler);
3685                 devr->ports[port].devr = devr;
3686         }
3687
3688         return 0;
3689
3690 error5:
3691         mlx5_ib_destroy_srq(devr->s0);
3692 error4:
3693         mlx5_ib_dealloc_xrcd(devr->x1);
3694 error3:
3695         mlx5_ib_dealloc_xrcd(devr->x0);
3696 error2:
3697         mlx5_ib_destroy_cq(devr->c0);
3698 error1:
3699         mlx5_ib_dealloc_pd(devr->p0);
3700 error0:
3701         return ret;
3702 }
3703
3704 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3705 {
3706         struct mlx5_ib_dev *dev =
3707                 container_of(devr, struct mlx5_ib_dev, devr);
3708         int port;
3709
3710         mlx5_ib_destroy_srq(devr->s1);
3711         mlx5_ib_destroy_srq(devr->s0);
3712         mlx5_ib_dealloc_xrcd(devr->x0);
3713         mlx5_ib_dealloc_xrcd(devr->x1);
3714         mlx5_ib_destroy_cq(devr->c0);
3715         mlx5_ib_dealloc_pd(devr->p0);
3716
3717         /* Make sure no change P_Key work items are still executing */
3718         for (port = 0; port < dev->num_ports; ++port)
3719                 cancel_work_sync(&devr->ports[port].pkey_change_work);
3720 }
3721
3722 static u32 get_core_cap_flags(struct ib_device *ibdev)
3723 {
3724         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3725         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3726         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3727         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3728         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
3729         u32 ret = 0;
3730
3731         if (ll == IB_LINK_LAYER_INFINIBAND)
3732                 return RDMA_CORE_PORT_IBA_IB;
3733
3734         if (raw_support)
3735                 ret = RDMA_CORE_PORT_RAW_PACKET;
3736
3737         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3738                 return ret;
3739
3740         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3741                 return ret;
3742
3743         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3744                 ret |= RDMA_CORE_PORT_IBA_ROCE;
3745
3746         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3747                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3748
3749         return ret;
3750 }
3751
3752 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3753                                struct ib_port_immutable *immutable)
3754 {
3755         struct ib_port_attr attr;
3756         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3757         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3758         int err;
3759
3760         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3761
3762         err = ib_query_port(ibdev, port_num, &attr);
3763         if (err)
3764                 return err;
3765
3766         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3767         immutable->gid_tbl_len = attr.gid_tbl_len;
3768         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3769         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3770                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3771
3772         return 0;
3773 }
3774
3775 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3776 {
3777         struct mlx5_ib_dev *dev =
3778                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3779         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3780                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3781                  fw_rev_sub(dev->mdev));
3782 }
3783
3784 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3785 {
3786         struct mlx5_core_dev *mdev = dev->mdev;
3787         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3788                                                                  MLX5_FLOW_NAMESPACE_LAG);
3789         struct mlx5_flow_table *ft;
3790         int err;
3791
3792         if (!ns || !mlx5_lag_is_active(mdev))
3793                 return 0;
3794
3795         err = mlx5_cmd_create_vport_lag(mdev);
3796         if (err)
3797                 return err;
3798
3799         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3800         if (IS_ERR(ft)) {
3801                 err = PTR_ERR(ft);
3802                 goto err_destroy_vport_lag;
3803         }
3804
3805         dev->flow_db.lag_demux_ft = ft;
3806         return 0;
3807
3808 err_destroy_vport_lag:
3809         mlx5_cmd_destroy_vport_lag(mdev);
3810         return err;
3811 }
3812
3813 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3814 {
3815         struct mlx5_core_dev *mdev = dev->mdev;
3816
3817         if (dev->flow_db.lag_demux_ft) {
3818                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3819                 dev->flow_db.lag_demux_ft = NULL;
3820
3821                 mlx5_cmd_destroy_vport_lag(mdev);
3822         }
3823 }
3824
3825 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3826 {
3827         int err;
3828
3829         dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
3830         err = register_netdevice_notifier(&dev->roce[port_num].nb);
3831         if (err) {
3832                 dev->roce[port_num].nb.notifier_call = NULL;
3833                 return err;
3834         }
3835
3836         return 0;
3837 }
3838
3839 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
3840 {
3841         if (dev->roce[port_num].nb.notifier_call) {
3842                 unregister_netdevice_notifier(&dev->roce[port_num].nb);
3843                 dev->roce[port_num].nb.notifier_call = NULL;
3844         }
3845 }
3846
3847 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
3848 {
3849         int err;
3850
3851         err = mlx5_add_netdev_notifier(dev, port_num);
3852         if (err)
3853                 return err;
3854
3855         if (MLX5_CAP_GEN(dev->mdev, roce)) {
3856                 err = mlx5_nic_vport_enable_roce(dev->mdev);
3857                 if (err)
3858                         goto err_unregister_netdevice_notifier;
3859         }
3860
3861         err = mlx5_eth_lag_init(dev);
3862         if (err)
3863                 goto err_disable_roce;
3864
3865         return 0;
3866
3867 err_disable_roce:
3868         if (MLX5_CAP_GEN(dev->mdev, roce))
3869                 mlx5_nic_vport_disable_roce(dev->mdev);
3870
3871 err_unregister_netdevice_notifier:
3872         mlx5_remove_netdev_notifier(dev, port_num);
3873         return err;
3874 }
3875
3876 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3877 {
3878         mlx5_eth_lag_cleanup(dev);
3879         if (MLX5_CAP_GEN(dev->mdev, roce))
3880                 mlx5_nic_vport_disable_roce(dev->mdev);
3881 }
3882
3883 struct mlx5_ib_counter {
3884         const char *name;
3885         size_t offset;
3886 };
3887
3888 #define INIT_Q_COUNTER(_name)           \
3889         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3890
3891 static const struct mlx5_ib_counter basic_q_cnts[] = {
3892         INIT_Q_COUNTER(rx_write_requests),
3893         INIT_Q_COUNTER(rx_read_requests),
3894         INIT_Q_COUNTER(rx_atomic_requests),
3895         INIT_Q_COUNTER(out_of_buffer),
3896 };
3897
3898 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
3899         INIT_Q_COUNTER(out_of_sequence),
3900 };
3901
3902 static const struct mlx5_ib_counter retrans_q_cnts[] = {
3903         INIT_Q_COUNTER(duplicate_request),
3904         INIT_Q_COUNTER(rnr_nak_retry_err),
3905         INIT_Q_COUNTER(packet_seq_err),
3906         INIT_Q_COUNTER(implied_nak_seq_err),
3907         INIT_Q_COUNTER(local_ack_timeout_err),
3908 };
3909
3910 #define INIT_CONG_COUNTER(_name)                \
3911         { .name = #_name, .offset =     \
3912                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3913
3914 static const struct mlx5_ib_counter cong_cnts[] = {
3915         INIT_CONG_COUNTER(rp_cnp_ignored),
3916         INIT_CONG_COUNTER(rp_cnp_handled),
3917         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3918         INIT_CONG_COUNTER(np_cnp_sent),
3919 };
3920
3921 static const struct mlx5_ib_counter extended_err_cnts[] = {
3922         INIT_Q_COUNTER(resp_local_length_error),
3923         INIT_Q_COUNTER(resp_cqe_error),
3924         INIT_Q_COUNTER(req_cqe_error),
3925         INIT_Q_COUNTER(req_remote_invalid_request),
3926         INIT_Q_COUNTER(req_remote_access_errors),
3927         INIT_Q_COUNTER(resp_remote_access_errors),
3928         INIT_Q_COUNTER(resp_cqe_flush_error),
3929         INIT_Q_COUNTER(req_cqe_flush_error),
3930 };
3931
3932 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
3933 {
3934         int i;
3935
3936         for (i = 0; i < dev->num_ports; i++) {
3937                 if (dev->port[i].cnts.set_id)
3938                         mlx5_core_dealloc_q_counter(dev->mdev,
3939                                                     dev->port[i].cnts.set_id);
3940                 kfree(dev->port[i].cnts.names);
3941                 kfree(dev->port[i].cnts.offsets);
3942         }
3943 }
3944
3945 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3946                                     struct mlx5_ib_counters *cnts)
3947 {
3948         u32 num_counters;
3949
3950         num_counters = ARRAY_SIZE(basic_q_cnts);
3951
3952         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3953                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3954
3955         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3956                 num_counters += ARRAY_SIZE(retrans_q_cnts);
3957
3958         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
3959                 num_counters += ARRAY_SIZE(extended_err_cnts);
3960
3961         cnts->num_q_counters = num_counters;
3962
3963         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3964                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3965                 num_counters += ARRAY_SIZE(cong_cnts);
3966         }
3967
3968         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3969         if (!cnts->names)
3970                 return -ENOMEM;
3971
3972         cnts->offsets = kcalloc(num_counters,
3973                                 sizeof(cnts->offsets), GFP_KERNEL);
3974         if (!cnts->offsets)
3975                 goto err_names;
3976
3977         return 0;
3978
3979 err_names:
3980         kfree(cnts->names);
3981         cnts->names = NULL;
3982         return -ENOMEM;
3983 }
3984
3985 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3986                                   const char **names,
3987                                   size_t *offsets)
3988 {
3989         int i;
3990         int j = 0;
3991
3992         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3993                 names[j] = basic_q_cnts[i].name;
3994                 offsets[j] = basic_q_cnts[i].offset;
3995         }
3996
3997         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3998                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3999                         names[j] = out_of_seq_q_cnts[i].name;
4000                         offsets[j] = out_of_seq_q_cnts[i].offset;
4001                 }
4002         }
4003
4004         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4005                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4006                         names[j] = retrans_q_cnts[i].name;
4007                         offsets[j] = retrans_q_cnts[i].offset;
4008                 }
4009         }
4010
4011         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4012                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4013                         names[j] = extended_err_cnts[i].name;
4014                         offsets[j] = extended_err_cnts[i].offset;
4015                 }
4016         }
4017
4018         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4019                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4020                         names[j] = cong_cnts[i].name;
4021                         offsets[j] = cong_cnts[i].offset;
4022                 }
4023         }
4024 }
4025
4026 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
4027 {
4028         int err = 0;
4029         int i;
4030
4031         for (i = 0; i < dev->num_ports; i++) {
4032                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4033                 if (err)
4034                         goto err_alloc;
4035
4036                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4037                                       dev->port[i].cnts.offsets);
4038
4039                 err = mlx5_core_alloc_q_counter(dev->mdev,
4040                                                 &dev->port[i].cnts.set_id);
4041                 if (err) {
4042                         mlx5_ib_warn(dev,
4043                                      "couldn't allocate queue counter for port %d, err %d\n",
4044                                      i + 1, err);
4045                         goto err_alloc;
4046                 }
4047                 dev->port[i].cnts.set_id_valid = true;
4048         }
4049
4050         return 0;
4051
4052 err_alloc:
4053         mlx5_ib_dealloc_counters(dev);
4054         return err;
4055 }
4056
4057 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4058                                                     u8 port_num)
4059 {
4060         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4061         struct mlx5_ib_port *port = &dev->port[port_num - 1];
4062
4063         /* We support only per port stats */
4064         if (port_num == 0)
4065                 return NULL;
4066
4067         return rdma_alloc_hw_stats_struct(port->cnts.names,
4068                                           port->cnts.num_q_counters +
4069                                           port->cnts.num_cong_counters,
4070                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
4071 }
4072
4073 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
4074                                     struct mlx5_ib_port *port,
4075                                     struct rdma_hw_stats *stats)
4076 {
4077         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4078         void *out;
4079         __be32 val;
4080         int ret, i;
4081
4082         out = kvzalloc(outlen, GFP_KERNEL);
4083         if (!out)
4084                 return -ENOMEM;
4085
4086         ret = mlx5_core_query_q_counter(mdev,
4087                                         port->cnts.set_id, 0,
4088                                         out, outlen);
4089         if (ret)
4090                 goto free;
4091
4092         for (i = 0; i < port->cnts.num_q_counters; i++) {
4093                 val = *(__be32 *)(out + port->cnts.offsets[i]);
4094                 stats->value[i] = (u64)be32_to_cpu(val);
4095         }
4096
4097 free:
4098         kvfree(out);
4099         return ret;
4100 }
4101
4102 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4103                                 struct rdma_hw_stats *stats,
4104                                 u8 port_num, int index)
4105 {
4106         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4107         struct mlx5_ib_port *port = &dev->port[port_num - 1];
4108         struct mlx5_core_dev *mdev;
4109         int ret, num_counters;
4110         u8 mdev_port_num;
4111
4112         if (!stats)
4113                 return -EINVAL;
4114
4115         num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4116
4117         /* q_counters are per IB device, query the master mdev */
4118         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
4119         if (ret)
4120                 return ret;
4121
4122         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4123                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4124                                                     &mdev_port_num);
4125                 if (!mdev) {
4126                         /* If port is not affiliated yet, its in down state
4127                          * which doesn't have any counters yet, so it would be
4128                          * zero. So no need to read from the HCA.
4129                          */
4130                         goto done;
4131                 }
4132                 ret = mlx5_lag_query_cong_counters(dev->mdev,
4133                                                    stats->value +
4134                                                    port->cnts.num_q_counters,
4135                                                    port->cnts.num_cong_counters,
4136                                                    port->cnts.offsets +
4137                                                    port->cnts.num_q_counters);
4138
4139                 mlx5_ib_put_native_port_mdev(dev, port_num);
4140                 if (ret)
4141                         return ret;
4142         }
4143
4144 done:
4145         return num_counters;
4146 }
4147
4148 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4149 {
4150         return mlx5_rdma_netdev_free(netdev);
4151 }
4152
4153 static struct net_device*
4154 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4155                           u8 port_num,
4156                           enum rdma_netdev_t type,
4157                           const char *name,
4158                           unsigned char name_assign_type,
4159                           void (*setup)(struct net_device *))
4160 {
4161         struct net_device *netdev;
4162         struct rdma_netdev *rn;
4163
4164         if (type != RDMA_NETDEV_IPOIB)
4165                 return ERR_PTR(-EOPNOTSUPP);
4166
4167         netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4168                                         name, setup);
4169         if (likely(!IS_ERR_OR_NULL(netdev))) {
4170                 rn = netdev_priv(netdev);
4171                 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4172         }
4173         return netdev;
4174 }
4175
4176 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4177 {
4178         if (!dev->delay_drop.dbg)
4179                 return;
4180         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4181         kfree(dev->delay_drop.dbg);
4182         dev->delay_drop.dbg = NULL;
4183 }
4184
4185 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4186 {
4187         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4188                 return;
4189
4190         cancel_work_sync(&dev->delay_drop.delay_drop_work);
4191         delay_drop_debugfs_cleanup(dev);
4192 }
4193
4194 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4195                                        size_t count, loff_t *pos)
4196 {
4197         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4198         char lbuf[20];
4199         int len;
4200
4201         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4202         return simple_read_from_buffer(buf, count, pos, lbuf, len);
4203 }
4204
4205 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4206                                         size_t count, loff_t *pos)
4207 {
4208         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4209         u32 timeout;
4210         u32 var;
4211
4212         if (kstrtouint_from_user(buf, count, 0, &var))
4213                 return -EFAULT;
4214
4215         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4216                         1000);
4217         if (timeout != var)
4218                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4219                             timeout);
4220
4221         delay_drop->timeout = timeout;
4222
4223         return count;
4224 }
4225
4226 static const struct file_operations fops_delay_drop_timeout = {
4227         .owner  = THIS_MODULE,
4228         .open   = simple_open,
4229         .write  = delay_drop_timeout_write,
4230         .read   = delay_drop_timeout_read,
4231 };
4232
4233 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4234 {
4235         struct mlx5_ib_dbg_delay_drop *dbg;
4236
4237         if (!mlx5_debugfs_root)
4238                 return 0;
4239
4240         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4241         if (!dbg)
4242                 return -ENOMEM;
4243
4244         dev->delay_drop.dbg = dbg;
4245
4246         dbg->dir_debugfs =
4247                 debugfs_create_dir("delay_drop",
4248                                    dev->mdev->priv.dbg_root);
4249         if (!dbg->dir_debugfs)
4250                 goto out_debugfs;
4251
4252         dbg->events_cnt_debugfs =
4253                 debugfs_create_atomic_t("num_timeout_events", 0400,
4254                                         dbg->dir_debugfs,
4255                                         &dev->delay_drop.events_cnt);
4256         if (!dbg->events_cnt_debugfs)
4257                 goto out_debugfs;
4258
4259         dbg->rqs_cnt_debugfs =
4260                 debugfs_create_atomic_t("num_rqs", 0400,
4261                                         dbg->dir_debugfs,
4262                                         &dev->delay_drop.rqs_cnt);
4263         if (!dbg->rqs_cnt_debugfs)
4264                 goto out_debugfs;
4265
4266         dbg->timeout_debugfs =
4267                 debugfs_create_file("timeout", 0600,
4268                                     dbg->dir_debugfs,
4269                                     &dev->delay_drop,
4270                                     &fops_delay_drop_timeout);
4271         if (!dbg->timeout_debugfs)
4272                 goto out_debugfs;
4273
4274         return 0;
4275
4276 out_debugfs:
4277         delay_drop_debugfs_cleanup(dev);
4278         return -ENOMEM;
4279 }
4280
4281 static void init_delay_drop(struct mlx5_ib_dev *dev)
4282 {
4283         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4284                 return;
4285
4286         mutex_init(&dev->delay_drop.lock);
4287         dev->delay_drop.dev = dev;
4288         dev->delay_drop.activate = false;
4289         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4290         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4291         atomic_set(&dev->delay_drop.rqs_cnt, 0);
4292         atomic_set(&dev->delay_drop.events_cnt, 0);
4293
4294         if (delay_drop_debugfs_init(dev))
4295                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
4296 }
4297
4298 static const struct cpumask *
4299 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
4300 {
4301         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4302
4303         return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4304 }
4305
4306 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4307 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4308                                       struct mlx5_ib_multiport_info *mpi)
4309 {
4310         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4311         struct mlx5_ib_port *port = &ibdev->port[port_num];
4312         int comps;
4313         int err;
4314         int i;
4315
4316         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4317
4318         spin_lock(&port->mp.mpi_lock);
4319         if (!mpi->ibdev) {
4320                 spin_unlock(&port->mp.mpi_lock);
4321                 return;
4322         }
4323         mpi->ibdev = NULL;
4324
4325         spin_unlock(&port->mp.mpi_lock);
4326         mlx5_remove_netdev_notifier(ibdev, port_num);
4327         spin_lock(&port->mp.mpi_lock);
4328
4329         comps = mpi->mdev_refcnt;
4330         if (comps) {
4331                 mpi->unaffiliate = true;
4332                 init_completion(&mpi->unref_comp);
4333                 spin_unlock(&port->mp.mpi_lock);
4334
4335                 for (i = 0; i < comps; i++)
4336                         wait_for_completion(&mpi->unref_comp);
4337
4338                 spin_lock(&port->mp.mpi_lock);
4339                 mpi->unaffiliate = false;
4340         }
4341
4342         port->mp.mpi = NULL;
4343
4344         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4345
4346         spin_unlock(&port->mp.mpi_lock);
4347
4348         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4349
4350         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4351         /* Log an error, still needed to cleanup the pointers and add
4352          * it back to the list.
4353          */
4354         if (err)
4355                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4356                             port_num + 1);
4357
4358         ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4359 }
4360
4361 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4362 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4363                                     struct mlx5_ib_multiport_info *mpi)
4364 {
4365         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4366         int err;
4367
4368         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4369         if (ibdev->port[port_num].mp.mpi) {
4370                 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4371                              port_num + 1);
4372                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4373                 return false;
4374         }
4375
4376         ibdev->port[port_num].mp.mpi = mpi;
4377         mpi->ibdev = ibdev;
4378         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4379
4380         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4381         if (err)
4382                 goto unbind;
4383
4384         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4385         if (err)
4386                 goto unbind;
4387
4388         err = mlx5_add_netdev_notifier(ibdev, port_num);
4389         if (err) {
4390                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4391                             port_num + 1);
4392                 goto unbind;
4393         }
4394
4395         err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
4396         if (err)
4397                 goto unbind;
4398
4399         return true;
4400
4401 unbind:
4402         mlx5_ib_unbind_slave_port(ibdev, mpi);
4403         return false;
4404 }
4405
4406 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4407 {
4408         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4409         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4410                                                           port_num + 1);
4411         struct mlx5_ib_multiport_info *mpi;
4412         int err;
4413         int i;
4414
4415         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4416                 return 0;
4417
4418         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4419                                                      &dev->sys_image_guid);
4420         if (err)
4421                 return err;
4422
4423         err = mlx5_nic_vport_enable_roce(dev->mdev);
4424         if (err)
4425                 return err;
4426
4427         mutex_lock(&mlx5_ib_multiport_mutex);
4428         for (i = 0; i < dev->num_ports; i++) {
4429                 bool bound = false;
4430
4431                 /* build a stub multiport info struct for the native port. */
4432                 if (i == port_num) {
4433                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4434                         if (!mpi) {
4435                                 mutex_unlock(&mlx5_ib_multiport_mutex);
4436                                 mlx5_nic_vport_disable_roce(dev->mdev);
4437                                 return -ENOMEM;
4438                         }
4439
4440                         mpi->is_master = true;
4441                         mpi->mdev = dev->mdev;
4442                         mpi->sys_image_guid = dev->sys_image_guid;
4443                         dev->port[i].mp.mpi = mpi;
4444                         mpi->ibdev = dev;
4445                         mpi = NULL;
4446                         continue;
4447                 }
4448
4449                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4450                                     list) {
4451                         if (dev->sys_image_guid == mpi->sys_image_guid &&
4452                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4453                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
4454                         }
4455
4456                         if (bound) {
4457                                 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4458                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4459                                 list_del(&mpi->list);
4460                                 break;
4461                         }
4462                 }
4463                 if (!bound) {
4464                         get_port_caps(dev, i + 1);
4465                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
4466                                     i + 1);
4467                 }
4468         }
4469
4470         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4471         mutex_unlock(&mlx5_ib_multiport_mutex);
4472         return err;
4473 }
4474
4475 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4476 {
4477         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4478         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4479                                                           port_num + 1);
4480         int i;
4481
4482         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4483                 return;
4484
4485         mutex_lock(&mlx5_ib_multiport_mutex);
4486         for (i = 0; i < dev->num_ports; i++) {
4487                 if (dev->port[i].mp.mpi) {
4488                         /* Destroy the native port stub */
4489                         if (i == port_num) {
4490                                 kfree(dev->port[i].mp.mpi);
4491                                 dev->port[i].mp.mpi = NULL;
4492                         } else {
4493                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4494                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4495                         }
4496                 }
4497         }
4498
4499         mlx5_ib_dbg(dev, "removing from devlist\n");
4500         list_del(&dev->ib_dev_list);
4501         mutex_unlock(&mlx5_ib_multiport_mutex);
4502
4503         mlx5_nic_vport_disable_roce(dev->mdev);
4504 }
4505
4506 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
4507 {
4508         mlx5_ib_cleanup_multiport_master(dev);
4509 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4510         cleanup_srcu_struct(&dev->mr_srcu);
4511 #endif
4512         kfree(dev->port);
4513 }
4514
4515 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
4516 {
4517         struct mlx5_core_dev *mdev = dev->mdev;
4518         const char *name;
4519         int err;
4520         int i;
4521
4522         dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
4523                             GFP_KERNEL);
4524         if (!dev->port)
4525                 return -ENOMEM;
4526
4527         for (i = 0; i < dev->num_ports; i++) {
4528                 spin_lock_init(&dev->port[i].mp.mpi_lock);
4529                 rwlock_init(&dev->roce[i].netdev_lock);
4530         }
4531
4532         err = mlx5_ib_init_multiport_master(dev);
4533         if (err)
4534                 goto err_free_port;
4535
4536         if (!mlx5_core_mp_enabled(mdev)) {
4537                 int i;
4538
4539                 for (i = 1; i <= dev->num_ports; i++) {
4540                         err = get_port_caps(dev, i);
4541                         if (err)
4542                                 break;
4543                 }
4544         } else {
4545                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
4546         }
4547         if (err)
4548                 goto err_mp;
4549
4550         if (mlx5_use_mad_ifc(dev))
4551                 get_ext_port_caps(dev);
4552
4553         if (!mlx5_lag_is_active(mdev))
4554                 name = "mlx5_%d";
4555         else
4556                 name = "mlx5_bond_%d";
4557
4558         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
4559         dev->ib_dev.owner               = THIS_MODULE;
4560         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
4561         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
4562         dev->ib_dev.phys_port_cnt       = dev->num_ports;
4563         dev->ib_dev.num_comp_vectors    =
4564                 dev->mdev->priv.eq_table.num_comp_vectors;
4565         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
4566
4567         mutex_init(&dev->flow_db.lock);
4568         mutex_init(&dev->cap_mask_mutex);
4569         INIT_LIST_HEAD(&dev->qp_list);
4570         spin_lock_init(&dev->reset_flow_resource_lock);
4571
4572 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4573         err = init_srcu_struct(&dev->mr_srcu);
4574         if (err)
4575                 goto err_free_port;
4576 #endif
4577
4578         return 0;
4579 err_mp:
4580         mlx5_ib_cleanup_multiport_master(dev);
4581
4582 err_free_port:
4583         kfree(dev->port);
4584
4585         return -ENOMEM;
4586 }
4587
4588 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
4589 {
4590         struct mlx5_core_dev *mdev = dev->mdev;
4591         int err;
4592
4593         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
4594         dev->ib_dev.uverbs_cmd_mask     =
4595                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
4596                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
4597                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
4598                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
4599                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
4600                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
4601                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
4602                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
4603                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
4604                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
4605                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
4606                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
4607                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
4608                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
4609                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
4610                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
4611                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
4612                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
4613                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
4614                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
4615                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
4616                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
4617                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
4618                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
4619                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
4620                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
4621         dev->ib_dev.uverbs_ex_cmd_mask =
4622                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
4623                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
4624                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
4625                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
4626                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
4627
4628         dev->ib_dev.query_device        = mlx5_ib_query_device;
4629         dev->ib_dev.query_port          = mlx5_ib_query_port;
4630         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
4631         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
4632         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
4633         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
4634         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
4635         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
4636         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
4637         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
4638         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
4639         dev->ib_dev.mmap                = mlx5_ib_mmap;
4640         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
4641         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
4642         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
4643         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
4644         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
4645         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
4646         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
4647         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
4648         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
4649         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
4650         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
4651         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
4652         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
4653         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
4654         dev->ib_dev.post_send           = mlx5_ib_post_send;
4655         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
4656         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
4657         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
4658         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
4659         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
4660         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
4661         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
4662         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
4663         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
4664         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
4665         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
4666         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
4667         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
4668         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
4669         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
4670         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
4671         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
4672         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
4673         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
4674         dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
4675         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
4676                 dev->ib_dev.alloc_rdma_netdev   = mlx5_ib_alloc_rdma_netdev;
4677
4678         if (mlx5_core_is_pf(mdev)) {
4679                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
4680                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
4681                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
4682                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
4683         }
4684
4685         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
4686
4687         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
4688
4689         if (MLX5_CAP_GEN(mdev, imaicl)) {
4690                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
4691                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
4692                 dev->ib_dev.uverbs_cmd_mask |=
4693                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
4694                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
4695         }
4696
4697         if (MLX5_CAP_GEN(mdev, xrc)) {
4698                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
4699                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
4700                 dev->ib_dev.uverbs_cmd_mask |=
4701                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
4702                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
4703         }
4704
4705         dev->ib_dev.create_flow = mlx5_ib_create_flow;
4706         dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
4707         dev->ib_dev.uverbs_ex_cmd_mask |=
4708                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
4709                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
4710
4711         err = init_node_data(dev);
4712         if (err)
4713                 return err;
4714
4715         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
4716             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
4717              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
4718                 mutex_init(&dev->lb_mutex);
4719
4720         return 0;
4721 }
4722
4723 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
4724 {
4725         struct mlx5_core_dev *mdev = dev->mdev;
4726         enum rdma_link_layer ll;
4727         int port_type_cap;
4728         u8 port_num;
4729         int err;
4730         int i;
4731
4732         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4733         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4734         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4735
4736         if (ll == IB_LINK_LAYER_ETHERNET) {
4737                 for (i = 0; i < dev->num_ports; i++) {
4738                         dev->roce[i].dev = dev;
4739                         dev->roce[i].native_port_num = i + 1;
4740                         dev->roce[i].last_port_state = IB_PORT_DOWN;
4741                 }
4742
4743                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
4744                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
4745                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
4746                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
4747                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
4748                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
4749                 dev->ib_dev.uverbs_ex_cmd_mask |=
4750                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
4751                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
4752                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
4753                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
4754                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
4755                 err = mlx5_enable_eth(dev, port_num);
4756                 if (err)
4757                         return err;
4758         }
4759
4760         return 0;
4761 }
4762
4763 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
4764 {
4765         struct mlx5_core_dev *mdev = dev->mdev;
4766         enum rdma_link_layer ll;
4767         int port_type_cap;
4768         u8 port_num;
4769
4770         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4771         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4772         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4773
4774         if (ll == IB_LINK_LAYER_ETHERNET) {
4775                 mlx5_disable_eth(dev);
4776                 mlx5_remove_netdev_notifier(dev, port_num);
4777         }
4778 }
4779
4780 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
4781 {
4782         return create_dev_resources(&dev->devr);
4783 }
4784
4785 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
4786 {
4787         destroy_dev_resources(&dev->devr);
4788 }
4789
4790 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
4791 {
4792         mlx5_ib_internal_fill_odp_caps(dev);
4793
4794         return mlx5_ib_odp_init_one(dev);
4795 }
4796
4797 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
4798 {
4799         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
4800                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
4801                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
4802
4803                 return mlx5_ib_alloc_counters(dev);
4804         }
4805
4806         return 0;
4807 }
4808
4809 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
4810 {
4811         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
4812                 mlx5_ib_dealloc_counters(dev);
4813 }
4814
4815 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4816 {
4817         return mlx5_ib_init_cong_debugfs(dev,
4818                                          mlx5_core_native_port_num(dev->mdev) - 1);
4819 }
4820
4821 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4822 {
4823         mlx5_ib_cleanup_cong_debugfs(dev,
4824                                      mlx5_core_native_port_num(dev->mdev) - 1);
4825 }
4826
4827 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4828 {
4829         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4830         if (!dev->mdev->priv.uar)
4831                 return -ENOMEM;
4832         return 0;
4833 }
4834
4835 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4836 {
4837         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4838 }
4839
4840 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4841 {
4842         int err;
4843
4844         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4845         if (err)
4846                 return err;
4847
4848         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4849         if (err)
4850                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4851
4852         return err;
4853 }
4854
4855 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4856 {
4857         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4858         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4859 }
4860
4861 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4862 {
4863         return ib_register_device(&dev->ib_dev, NULL);
4864 }
4865
4866 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4867 {
4868         ib_unregister_device(&dev->ib_dev);
4869 }
4870
4871 static int mlx5_ib_stage_umr_res_init(struct mlx5_ib_dev *dev)
4872 {
4873         return create_umr_res(dev);
4874 }
4875
4876 static void mlx5_ib_stage_umr_res_cleanup(struct mlx5_ib_dev *dev)
4877 {
4878         destroy_umrc_res(dev);
4879 }
4880
4881 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4882 {
4883         init_delay_drop(dev);
4884
4885         return 0;
4886 }
4887
4888 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4889 {
4890         cancel_delay_drop(dev);
4891 }
4892
4893 static int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
4894 {
4895         int err;
4896         int i;
4897
4898         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
4899                 err = device_create_file(&dev->ib_dev.dev,
4900                                          mlx5_class_attributes[i]);
4901                 if (err)
4902                         return err;
4903         }
4904
4905         return 0;
4906 }
4907
4908 static void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4909                              const struct mlx5_ib_profile *profile,
4910                              int stage)
4911 {
4912         /* Number of stages to cleanup */
4913         while (stage) {
4914                 stage--;
4915                 if (profile->stage[stage].cleanup)
4916                         profile->stage[stage].cleanup(dev);
4917         }
4918
4919         ib_dealloc_device((struct ib_device *)dev);
4920 }
4921
4922 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
4923
4924 static void *__mlx5_ib_add(struct mlx5_core_dev *mdev,
4925                            const struct mlx5_ib_profile *profile)
4926 {
4927         struct mlx5_ib_dev *dev;
4928         int err;
4929         int i;
4930
4931         printk_once(KERN_INFO "%s", mlx5_version);
4932
4933         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
4934         if (!dev)
4935                 return NULL;
4936
4937         dev->mdev = mdev;
4938         dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4939                              MLX5_CAP_GEN(mdev, num_vhca_ports));
4940
4941         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4942                 if (profile->stage[i].init) {
4943                         err = profile->stage[i].init(dev);
4944                         if (err)
4945                                 goto err_out;
4946                 }
4947         }
4948
4949         dev->profile = profile;
4950         dev->ib_active = true;
4951
4952         return dev;
4953
4954 err_out:
4955         __mlx5_ib_remove(dev, profile, i);
4956
4957         return NULL;
4958 }
4959
4960 static const struct mlx5_ib_profile pf_profile = {
4961         STAGE_CREATE(MLX5_IB_STAGE_INIT,
4962                      mlx5_ib_stage_init_init,
4963                      mlx5_ib_stage_init_cleanup),
4964         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4965                      mlx5_ib_stage_caps_init,
4966                      NULL),
4967         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4968                      mlx5_ib_stage_roce_init,
4969                      mlx5_ib_stage_roce_cleanup),
4970         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4971                      mlx5_ib_stage_dev_res_init,
4972                      mlx5_ib_stage_dev_res_cleanup),
4973         STAGE_CREATE(MLX5_IB_STAGE_ODP,
4974                      mlx5_ib_stage_odp_init,
4975                      NULL),
4976         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4977                      mlx5_ib_stage_counters_init,
4978                      mlx5_ib_stage_counters_cleanup),
4979         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4980                      mlx5_ib_stage_cong_debugfs_init,
4981                      mlx5_ib_stage_cong_debugfs_cleanup),
4982         STAGE_CREATE(MLX5_IB_STAGE_UAR,
4983                      mlx5_ib_stage_uar_init,
4984                      mlx5_ib_stage_uar_cleanup),
4985         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4986                      mlx5_ib_stage_bfrag_init,
4987                      mlx5_ib_stage_bfrag_cleanup),
4988         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4989                      mlx5_ib_stage_ib_reg_init,
4990                      mlx5_ib_stage_ib_reg_cleanup),
4991         STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES,
4992                      mlx5_ib_stage_umr_res_init,
4993                      mlx5_ib_stage_umr_res_cleanup),
4994         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4995                      mlx5_ib_stage_delay_drop_init,
4996                      mlx5_ib_stage_delay_drop_cleanup),
4997         STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
4998                      mlx5_ib_stage_class_attr_init,
4999                      NULL),
5000 };
5001
5002 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
5003 {
5004         struct mlx5_ib_multiport_info *mpi;
5005         struct mlx5_ib_dev *dev;
5006         bool bound = false;
5007         int err;
5008
5009         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5010         if (!mpi)
5011                 return NULL;
5012
5013         mpi->mdev = mdev;
5014
5015         err = mlx5_query_nic_vport_system_image_guid(mdev,
5016                                                      &mpi->sys_image_guid);
5017         if (err) {
5018                 kfree(mpi);
5019                 return NULL;
5020         }
5021
5022         mutex_lock(&mlx5_ib_multiport_mutex);
5023         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5024                 if (dev->sys_image_guid == mpi->sys_image_guid)
5025                         bound = mlx5_ib_bind_slave_port(dev, mpi);
5026
5027                 if (bound) {
5028                         rdma_roce_rescan_device(&dev->ib_dev);
5029                         break;
5030                 }
5031         }
5032
5033         if (!bound) {
5034                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5035                 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5036         } else {
5037                 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
5038         }
5039         mutex_unlock(&mlx5_ib_multiport_mutex);
5040
5041         return mpi;
5042 }
5043
5044 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
5045 {
5046         enum rdma_link_layer ll;
5047         int port_type_cap;
5048
5049         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5050         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5051
5052         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5053                 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5054
5055                 return mlx5_ib_add_slave_port(mdev, port_num);
5056         }
5057
5058         return __mlx5_ib_add(mdev, &pf_profile);
5059 }
5060
5061 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
5062 {
5063         struct mlx5_ib_multiport_info *mpi;
5064         struct mlx5_ib_dev *dev;
5065
5066         if (mlx5_core_is_mp_slave(mdev)) {
5067                 mpi = context;
5068                 mutex_lock(&mlx5_ib_multiport_mutex);
5069                 if (mpi->ibdev)
5070                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5071                 list_del(&mpi->list);
5072                 mutex_unlock(&mlx5_ib_multiport_mutex);
5073                 return;
5074         }
5075
5076         dev = context;
5077         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
5078 }
5079
5080 static struct mlx5_interface mlx5_ib_interface = {
5081         .add            = mlx5_ib_add,
5082         .remove         = mlx5_ib_remove,
5083         .event          = mlx5_ib_event,
5084 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5085         .pfault         = mlx5_ib_pfault,
5086 #endif
5087         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
5088 };
5089
5090 static int __init mlx5_ib_init(void)
5091 {
5092         int err;
5093
5094         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
5095         if (!mlx5_ib_event_wq)
5096                 return -ENOMEM;
5097
5098         mlx5_ib_odp_init();
5099
5100         err = mlx5_register_interface(&mlx5_ib_interface);
5101
5102         return err;
5103 }
5104
5105 static void __exit mlx5_ib_cleanup(void)
5106 {
5107         mlx5_unregister_interface(&mlx5_ib_interface);
5108         destroy_workqueue(mlx5_ib_event_wq);
5109 }
5110
5111 module_init(mlx5_ib_init);
5112 module_exit(mlx5_ib_cleanup);