drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <linux/bitmap.h>
  42 #if defined(CONFIG_X86)
  43 #include <asm/pat.h>
  44 #endif
  45 #include <linux/sched.h>
  46 #include <linux/sched/mm.h>
  47 #include <linux/sched/task.h>
  48 #include <linux/delay.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <rdma/ib_addr.h>
  51 #include <rdma/ib_cache.h>
  52 #include <linux/mlx5/port.h>
  53 #include <linux/mlx5/vport.h>
  54 #include <linux/mlx5/fs.h>
  55 #include <linux/list.h>
  56 #include <rdma/ib_smi.h>
  57 #include <rdma/ib_umem.h>
  58 #include <linux/in.h>
  59 #include <linux/etherdevice.h>
  60 #include "mlx5_ib.h"
  61 #include "ib_rep.h"
  62 #include "cmd.h"
  63 #include <linux/mlx5/fs_helpers.h>
  64 #include <linux/mlx5/accel.h>
  65 #include <rdma/uverbs_std_types.h>
  66 #include <rdma/mlx5_user_ioctl_verbs.h>
  67 #include <rdma/mlx5_user_ioctl_cmds.h>
  68
  69 #define UVERBS_MODULE_NAME mlx5_ib
  70 #include <rdma/uverbs_named_ioctl.h>
  71
  72 #define DRIVER_NAME "mlx5_ib"
  73 #define DRIVER_VERSION "5.0-0"
  74
  75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  77 MODULE_LICENSE("Dual BSD/GPL");
  78
  79 static char mlx5_version[] =
  80         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  81         DRIVER_VERSION "\n";
  82
  83 struct mlx5_ib_event_work {
  84         struct work_struct      work;
  85         union {
  86                 struct mlx5_ib_dev            *dev;
  87                 struct mlx5_ib_multiport_info *mpi;
  88         };
  89         bool                    is_slave;
  90         unsigned int            event;
  91         void                    *param;
  92 };
  93
  94 enum {
  95         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  96 };
  97
  98 static struct workqueue_struct *mlx5_ib_event_wq;
  99 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
 100 static LIST_HEAD(mlx5_ib_dev_list);
 101 /*
 102  * This mutex should be held when accessing either of the above lists
 103  */
 104 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
 105
 106 /* We can't use an array for xlt_emergency_page because dma_map_single
 107  * doesn't work on kernel modules memory
 108  */
 109 static unsigned long xlt_emergency_page;
 110 static struct mutex xlt_emergency_page_mutex;
 111
 112 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
 113 {
 114         struct mlx5_ib_dev *dev;
 115
 116         mutex_lock(&mlx5_ib_multiport_mutex);
 117         dev = mpi->ibdev;
 118         mutex_unlock(&mlx5_ib_multiport_mutex);
 119         return dev;
 120 }
 121
 122 static enum rdma_link_layer
 123 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 124 {
 125         switch (port_type_cap) {
 126         case MLX5_CAP_PORT_TYPE_IB:
 127                 return IB_LINK_LAYER_INFINIBAND;
 128         case MLX5_CAP_PORT_TYPE_ETH:
 129                 return IB_LINK_LAYER_ETHERNET;
 130         default:
 131                 return IB_LINK_LAYER_UNSPECIFIED;
 132         }
 133 }
 134
 135 static enum rdma_link_layer
 136 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 137 {
 138         struct mlx5_ib_dev *dev = to_mdev(device);
 139         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 140
 141         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 142 }
 143
 144 static int get_port_state(struct ib_device *ibdev,
 145                           u8 port_num,
 146                           enum ib_port_state *state)
 147 {
 148         struct ib_port_attr attr;
 149         int ret;
 150
 151         memset(&attr, 0, sizeof(attr));
 152         ret = ibdev->query_port(ibdev, port_num, &attr);
 153         if (!ret)
 154                 *state = attr.state;
 155         return ret;
 156 }
 157
 158 static int mlx5_netdev_event(struct notifier_block *this,
 159                              unsigned long event, void *ptr)
 160 {
 161         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 162         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 163         u8 port_num = roce->native_port_num;
 164         struct mlx5_core_dev *mdev;
 165         struct mlx5_ib_dev *ibdev;
 166
 167         ibdev = roce->dev;
 168         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 169         if (!mdev)
 170                 return NOTIFY_DONE;
 171
 172         switch (event) {
 173         case NETDEV_REGISTER:
 174         case NETDEV_UNREGISTER:
 175                 write_lock(&roce->netdev_lock);
 176                 if (ibdev->rep) {
 177                         struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
 178                         struct net_device *rep_ndev;
 179
 180                         rep_ndev = mlx5_ib_get_rep_netdev(esw,
 181                                                           ibdev->rep->vport);
 182                         if (rep_ndev == ndev)
 183                                 roce->netdev = (event == NETDEV_UNREGISTER) ?
 184                                         NULL : ndev;
 185                 } else if (ndev->dev.parent == &mdev->pdev->dev) {
 186                         roce->netdev = (event == NETDEV_UNREGISTER) ?
 187                                 NULL : ndev;
 188                 }
 189                 write_unlock(&roce->netdev_lock);
 190                 break;
 191
 192         case NETDEV_CHANGE:
 193         case NETDEV_UP:
 194         case NETDEV_DOWN: {
 195                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 196                 struct net_device *upper = NULL;
 197
 198                 if (lag_ndev) {
 199                         upper = netdev_master_upper_dev_get(lag_ndev);
 200                         dev_put(lag_ndev);
 201                 }
 202
 203                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 204                     && ibdev->ib_active) {
 205                         struct ib_event ibev = { };
 206                         enum ib_port_state port_state;
 207
 208                         if (get_port_state(&ibdev->ib_dev, port_num,
 209                                            &port_state))
 210                                 goto done;
 211
 212                         if (roce->last_port_state == port_state)
 213                                 goto done;
 214
 215                         roce->last_port_state = port_state;
 216                         ibev.device = &ibdev->ib_dev;
 217                         if (port_state == IB_PORT_DOWN)
 218                                 ibev.event = IB_EVENT_PORT_ERR;
 219                         else if (port_state == IB_PORT_ACTIVE)
 220                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 221                         else
 222                                 goto done;
 223
 224                         ibev.element.port_num = port_num;
 225                         ib_dispatch_event(&ibev);
 226                 }
 227                 break;
 228         }
 229
 230         default:
 231                 break;
 232         }
 233 done:
 234         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 235         return NOTIFY_DONE;
 236 }
 237
 238 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 239                                              u8 port_num)
 240 {
 241         struct mlx5_ib_dev *ibdev = to_mdev(device);
 242         struct net_device *ndev;
 243         struct mlx5_core_dev *mdev;
 244
 245         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 246         if (!mdev)
 247                 return NULL;
 248
 249         ndev = mlx5_lag_get_roce_netdev(mdev);
 250         if (ndev)
 251                 goto out;
 252
 253         /* Ensure ndev does not disappear before we invoke dev_hold()
 254          */
 255         read_lock(&ibdev->roce[port_num - 1].netdev_lock);
 256         ndev = ibdev->roce[port_num - 1].netdev;
 257         if (ndev)
 258                 dev_hold(ndev);
 259         read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
 260
 261 out:
 262         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 263         return ndev;
 264 }
 265
 266 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 267                                                    u8 ib_port_num,
 268                                                    u8 *native_port_num)
 269 {
 270         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 271                                                           ib_port_num);
 272         struct mlx5_core_dev *mdev = NULL;
 273         struct mlx5_ib_multiport_info *mpi;
 274         struct mlx5_ib_port *port;
 275
 276         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 277             ll != IB_LINK_LAYER_ETHERNET) {
 278                 if (native_port_num)
 279                         *native_port_num = ib_port_num;
 280                 return ibdev->mdev;
 281         }
 282
 283         if (native_port_num)
 284                 *native_port_num = 1;
 285
 286         port = &ibdev->port[ib_port_num - 1];
 287         if (!port)
 288                 return NULL;
 289
 290         spin_lock(&port->mp.mpi_lock);
 291         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 292         if (mpi && !mpi->unaffiliate) {
 293                 mdev = mpi->mdev;
 294                 /* If it's the master no need to refcount, it'll exist
 295                  * as long as the ib_dev exists.
 296                  */
 297                 if (!mpi->is_master)
 298                         mpi->mdev_refcnt++;
 299         }
 300         spin_unlock(&port->mp.mpi_lock);
 301
 302         return mdev;
 303 }
 304
 305 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 306 {
 307         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 308                                                           port_num);
 309         struct mlx5_ib_multiport_info *mpi;
 310         struct mlx5_ib_port *port;
 311
 312         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 313                 return;
 314
 315         port = &ibdev->port[port_num - 1];
 316
 317         spin_lock(&port->mp.mpi_lock);
 318         mpi = ibdev->port[port_num - 1].mp.mpi;
 319         if (mpi->is_master)
 320                 goto out;
 321
 322         mpi->mdev_refcnt--;
 323         if (mpi->unaffiliate)
 324                 complete(&mpi->unref_comp);
 325 out:
 326         spin_unlock(&port->mp.mpi_lock);
 327 }
 328
 329 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 330                                     u8 *active_width)
 331 {
 332         switch (eth_proto_oper) {
 333         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 334         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 335         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 336         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 337                 *active_width = IB_WIDTH_1X;
 338                 *active_speed = IB_SPEED_SDR;
 339                 break;
 340         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 341         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 342         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 343         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 344         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 345         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 346         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 347                 *active_width = IB_WIDTH_1X;
 348                 *active_speed = IB_SPEED_QDR;
 349                 break;
 350         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 351         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 352         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 353                 *active_width = IB_WIDTH_1X;
 354                 *active_speed = IB_SPEED_EDR;
 355                 break;
 356         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 357         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 358         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 359         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 360                 *active_width = IB_WIDTH_4X;
 361                 *active_speed = IB_SPEED_QDR;
 362                 break;
 363         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 364         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 365         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 366                 *active_width = IB_WIDTH_1X;
 367                 *active_speed = IB_SPEED_HDR;
 368                 break;
 369         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 370                 *active_width = IB_WIDTH_4X;
 371                 *active_speed = IB_SPEED_FDR;
 372                 break;
 373         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 374         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 375         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 376         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 377                 *active_width = IB_WIDTH_4X;
 378                 *active_speed = IB_SPEED_EDR;
 379                 break;
 380         default:
 381                 return -EINVAL;
 382         }
 383
 384         return 0;
 385 }
 386
 387 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 388                                 struct ib_port_attr *props)
 389 {
 390         struct mlx5_ib_dev *dev = to_mdev(device);
 391         struct mlx5_core_dev *mdev;
 392         struct net_device *ndev, *upper;
 393         enum ib_mtu ndev_ib_mtu;
 394         bool put_mdev = true;
 395         u16 qkey_viol_cntr;
 396         u32 eth_prot_oper;
 397         u8 mdev_port_num;
 398         int err;
 399
 400         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 401         if (!mdev) {
 402                 /* This means the port isn't affiliated yet. Get the
 403                  * info for the master port instead.
 404                  */
 405                 put_mdev = false;
 406                 mdev = dev->mdev;
 407                 mdev_port_num = 1;
 408                 port_num = 1;
 409         }
 410
 411         /* Possible bad flows are checked before filling out props so in case
 412          * of an error it will still be zeroed out.
 413          */
 414         err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
 415                                              mdev_port_num);
 416         if (err)
 417                 goto out;
 418
 419         props->active_width     = IB_WIDTH_4X;
 420         props->active_speed     = IB_SPEED_QDR;
 421
 422         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 423                                  &props->active_width);
 424
 425         props->port_cap_flags |= IB_PORT_CM_SUP;
 426         props->ip_gids = true;
 427
 428         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 429                                                 roce_address_table_size);
 430         props->max_mtu          = IB_MTU_4096;
 431         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 432         props->pkey_tbl_len     = 1;
 433         props->state            = IB_PORT_DOWN;
 434         props->phys_state       = 3;
 435
 436         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 437         props->qkey_viol_cntr = qkey_viol_cntr;
 438
 439         /* If this is a stub query for an unaffiliated port stop here */
 440         if (!put_mdev)
 441                 goto out;
 442
 443         ndev = mlx5_ib_get_netdev(device, port_num);
 444         if (!ndev)
 445                 goto out;
 446
 447         if (mlx5_lag_is_active(dev->mdev)) {
 448                 rcu_read_lock();
 449                 upper = netdev_master_upper_dev_get_rcu(ndev);
 450                 if (upper) {
 451                         dev_put(ndev);
 452                         ndev = upper;
 453                         dev_hold(ndev);
 454                 }
 455                 rcu_read_unlock();
 456         }
 457
 458         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 459                 props->state      = IB_PORT_ACTIVE;
 460                 props->phys_state = 5;
 461         }
 462
 463         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 464
 465         dev_put(ndev);
 466
 467         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 468 out:
 469         if (put_mdev)
 470                 mlx5_ib_put_native_port_mdev(dev, port_num);
 471         return err;
 472 }
 473
 474 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 475                          unsigned int index, const union ib_gid *gid,
 476                          const struct ib_gid_attr *attr)
 477 {
 478         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 479         u8 roce_version = 0;
 480         u8 roce_l3_type = 0;
 481         bool vlan = false;
 482         u8 mac[ETH_ALEN];
 483         u16 vlan_id = 0;
 484
 485         if (gid) {
 486                 gid_type = attr->gid_type;
 487                 ether_addr_copy(mac, attr->ndev->dev_addr);
 488
 489                 if (is_vlan_dev(attr->ndev)) {
 490                         vlan = true;
 491                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 492                 }
 493         }
 494
 495         switch (gid_type) {
 496         case IB_GID_TYPE_IB:
 497                 roce_version = MLX5_ROCE_VERSION_1;
 498                 break;
 499         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 500                 roce_version = MLX5_ROCE_VERSION_2;
 501                 if (ipv6_addr_v4mapped((void *)gid))
 502                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 503                 else
 504                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 505                 break;
 506
 507         default:
 508                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 509         }
 510
 511         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 512                                       roce_l3_type, gid->raw, mac, vlan,
 513                                       vlan_id, port_num);
 514 }
 515
 516 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 517                            __always_unused void **context)
 518 {
 519         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 520                              attr->index, &attr->gid, attr);
 521 }
 522
 523 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 524                            __always_unused void **context)
 525 {
 526         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 527                              attr->index, NULL, NULL);
 528 }
 529
 530 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
 531                                const struct ib_gid_attr *attr)
 532 {
 533         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 534                 return 0;
 535
 536         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 537 }
 538
 539 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 540 {
 541         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 542                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 543         return 0;
 544 }
 545
 546 enum {
 547         MLX5_VPORT_ACCESS_METHOD_MAD,
 548         MLX5_VPORT_ACCESS_METHOD_HCA,
 549         MLX5_VPORT_ACCESS_METHOD_NIC,
 550 };
 551
 552 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 553 {
 554         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 555                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 556
 557         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 558             IB_LINK_LAYER_ETHERNET)
 559                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 560
 561         return MLX5_VPORT_ACCESS_METHOD_HCA;
 562 }
 563
 564 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 565                             u8 atomic_size_qp,
 566                             struct ib_device_attr *props)
 567 {
 568         u8 tmp;
 569         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 570         u8 atomic_req_8B_endianness_mode =
 571                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 572
 573         /* Check if HW supports 8 bytes standard atomic operations and capable
 574          * of host endianness respond
 575          */
 576         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 577         if (((atomic_operations & tmp) == tmp) &&
 578             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 579             (atomic_req_8B_endianness_mode)) {
 580                 props->atomic_cap = IB_ATOMIC_HCA;
 581         } else {
 582                 props->atomic_cap = IB_ATOMIC_NONE;
 583         }
 584 }
 585
 586 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 587                                struct ib_device_attr *props)
 588 {
 589         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 590
 591         get_atomic_caps(dev, atomic_size_qp, props);
 592 }
 593
 594 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 595                                struct ib_device_attr *props)
 596 {
 597         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 598
 599         get_atomic_caps(dev, atomic_size_qp, props);
 600 }
 601
 602 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 603 {
 604         struct ib_device_attr props = {};
 605
 606         get_atomic_caps_dc(dev, &props);
 607         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 608 }
 609 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 610                                         __be64 *sys_image_guid)
 611 {
 612         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 613         struct mlx5_core_dev *mdev = dev->mdev;
 614         u64 tmp;
 615         int err;
 616
 617         switch (mlx5_get_vport_access_method(ibdev)) {
 618         case MLX5_VPORT_ACCESS_METHOD_MAD:
 619                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 620                                                             sys_image_guid);
 621
 622         case MLX5_VPORT_ACCESS_METHOD_HCA:
 623                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 624                 break;
 625
 626         case MLX5_VPORT_ACCESS_METHOD_NIC:
 627                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 628                 break;
 629
 630         default:
 631                 return -EINVAL;
 632         }
 633
 634         if (!err)
 635                 *sys_image_guid = cpu_to_be64(tmp);
 636
 637         return err;
 638
 639 }
 640
 641 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 642                                 u16 *max_pkeys)
 643 {
 644         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 645         struct mlx5_core_dev *mdev = dev->mdev;
 646
 647         switch (mlx5_get_vport_access_method(ibdev)) {
 648         case MLX5_VPORT_ACCESS_METHOD_MAD:
 649                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 650
 651         case MLX5_VPORT_ACCESS_METHOD_HCA:
 652         case MLX5_VPORT_ACCESS_METHOD_NIC:
 653                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 654                                                 pkey_table_size));
 655                 return 0;
 656
 657         default:
 658                 return -EINVAL;
 659         }
 660 }
 661
 662 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 663                                 u32 *vendor_id)
 664 {
 665         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 666
 667         switch (mlx5_get_vport_access_method(ibdev)) {
 668         case MLX5_VPORT_ACCESS_METHOD_MAD:
 669                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 670
 671         case MLX5_VPORT_ACCESS_METHOD_HCA:
 672         case MLX5_VPORT_ACCESS_METHOD_NIC:
 673                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 674
 675         default:
 676                 return -EINVAL;
 677         }
 678 }
 679
 680 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 681                                 __be64 *node_guid)
 682 {
 683         u64 tmp;
 684         int err;
 685
 686         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 687         case MLX5_VPORT_ACCESS_METHOD_MAD:
 688                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 689
 690         case MLX5_VPORT_ACCESS_METHOD_HCA:
 691                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 692                 break;
 693
 694         case MLX5_VPORT_ACCESS_METHOD_NIC:
 695                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 696                 break;
 697
 698         default:
 699                 return -EINVAL;
 700         }
 701
 702         if (!err)
 703                 *node_guid = cpu_to_be64(tmp);
 704
 705         return err;
 706 }
 707
 708 struct mlx5_reg_node_desc {
 709         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 710 };
 711
 712 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 713 {
 714         struct mlx5_reg_node_desc in;
 715
 716         if (mlx5_use_mad_ifc(dev))
 717                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 718
 719         memset(&in, 0, sizeof(in));
 720
 721         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 722                                     sizeof(struct mlx5_reg_node_desc),
 723                                     MLX5_REG_NODE_DESC, 0, 0);
 724 }
 725
 726 static int mlx5_ib_query_device(struct ib_device *ibdev,
 727                                 struct ib_device_attr *props,
 728                                 struct ib_udata *uhw)
 729 {
 730         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 731         struct mlx5_core_dev *mdev = dev->mdev;
 732         int err = -ENOMEM;
 733         int max_sq_desc;
 734         int max_rq_sg;
 735         int max_sq_sg;
 736         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 737         bool raw_support = !mlx5_core_mp_enabled(mdev);
 738         struct mlx5_ib_query_device_resp resp = {};
 739         size_t resp_len;
 740         u64 max_tso;
 741
 742         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 743         if (uhw->outlen && uhw->outlen < resp_len)
 744                 return -EINVAL;
 745         else
 746                 resp.response_length = resp_len;
 747
 748         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 749                 return -EINVAL;
 750
 751         memset(props, 0, sizeof(*props));
 752         err = mlx5_query_system_image_guid(ibdev,
 753                                            &props->sys_image_guid);
 754         if (err)
 755                 return err;
 756
 757         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 758         if (err)
 759                 return err;
 760
 761         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 762         if (err)
 763                 return err;
 764
 765         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 766                 (fw_rev_min(dev->mdev) << 16) |
 767                 fw_rev_sub(dev->mdev);
 768         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 769                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 770                 IB_DEVICE_SYS_IMAGE_GUID                |
 771                 IB_DEVICE_RC_RNR_NAK_GEN;
 772
 773         if (MLX5_CAP_GEN(mdev, pkv))
 774                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 775         if (MLX5_CAP_GEN(mdev, qkv))
 776                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 777         if (MLX5_CAP_GEN(mdev, apm))
 778                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 779         if (MLX5_CAP_GEN(mdev, xrc))
 780                 props->device_cap_flags |= IB_DEVICE_XRC;
 781         if (MLX5_CAP_GEN(mdev, imaicl)) {
 782                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 783                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 784                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 785                 /* We support 'Gappy' memory registration too */
 786                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 787         }
 788         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 789         if (MLX5_CAP_GEN(mdev, sho)) {
 790                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 791                 /* At this stage no support for signature handover */
 792                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 793                                       IB_PROT_T10DIF_TYPE_2 |
 794                                       IB_PROT_T10DIF_TYPE_3;
 795                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 796                                        IB_GUARD_T10DIF_CSUM;
 797         }
 798         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 799                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 800
 801         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 802                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 803                         /* Legacy bit to support old userspace libraries */
 804                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 805                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 806                 }
 807
 808                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 809                         props->raw_packet_caps |=
 810                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 811
 812                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 813                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 814                         if (max_tso) {
 815                                 resp.tso_caps.max_tso = 1 << max_tso;
 816                                 resp.tso_caps.supported_qpts |=
 817                                         1 << IB_QPT_RAW_PACKET;
 818                                 resp.response_length += sizeof(resp.tso_caps);
 819                         }
 820                 }
 821
 822                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 823                         resp.rss_caps.rx_hash_function =
 824                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 825                         resp.rss_caps.rx_hash_fields_mask =
 826                                                 MLX5_RX_HASH_SRC_IPV4 |
 827                                                 MLX5_RX_HASH_DST_IPV4 |
 828                                                 MLX5_RX_HASH_SRC_IPV6 |
 829                                                 MLX5_RX_HASH_DST_IPV6 |
 830                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 831                                                 MLX5_RX_HASH_DST_PORT_TCP |
 832                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 833                                                 MLX5_RX_HASH_DST_PORT_UDP |
 834                                                 MLX5_RX_HASH_INNER;
 835                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 836                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 837                                 resp.rss_caps.rx_hash_fields_mask |=
 838                                         MLX5_RX_HASH_IPSEC_SPI;
 839                         resp.response_length += sizeof(resp.rss_caps);
 840                 }
 841         } else {
 842                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 843                         resp.response_length += sizeof(resp.tso_caps);
 844                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 845                         resp.response_length += sizeof(resp.rss_caps);
 846         }
 847
 848         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 849                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 850                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 851         }
 852
 853         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 854             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 855             raw_support)
 856                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 857
 858         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 859             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 860                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 861
 862         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 863             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 864             raw_support) {
 865                 /* Legacy bit to support old userspace libraries */
 866                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 867                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 868         }
 869
 870         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 871                 props->max_dm_size =
 872                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 873         }
 874
 875         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 876                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 877
 878         if (MLX5_CAP_GEN(mdev, end_pad))
 879                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 880
 881         props->vendor_part_id      = mdev->pdev->device;
 882         props->hw_ver              = mdev->pdev->revision;
 883
 884         props->max_mr_size         = ~0ull;
 885         props->page_size_cap       = ~(min_page_size - 1);
 886         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 887         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 888         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 889                      sizeof(struct mlx5_wqe_data_seg);
 890         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 891         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 892                      sizeof(struct mlx5_wqe_raddr_seg)) /
 893                 sizeof(struct mlx5_wqe_data_seg);
 894         props->max_send_sge = max_sq_sg;
 895         props->max_recv_sge = max_rq_sg;
 896         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 897         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 898         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 899         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 900         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 901         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 902         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 903         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 904         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 905         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 906         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 907         props->max_srq_sge         = max_rq_sg - 1;
 908         props->max_fast_reg_page_list_len =
 909                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 910         get_atomic_caps_qp(dev, props);
 911         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 912         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 913         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 914         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 915                                            props->max_mcast_grp;
 916         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 917         props->max_ah = INT_MAX;
 918         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 919         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 920
 921 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 922         if (MLX5_CAP_GEN(mdev, pg))
 923                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 924         props->odp_caps = dev->odp_caps;
 925 #endif
 926
 927         if (MLX5_CAP_GEN(mdev, cd))
 928                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 929
 930         if (!mlx5_core_is_pf(mdev))
 931                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 932
 933         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 934             IB_LINK_LAYER_ETHERNET && raw_support) {
 935                 props->rss_caps.max_rwq_indirection_tables =
 936                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 937                 props->rss_caps.max_rwq_indirection_table_size =
 938                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 939                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 940                 props->max_wq_type_rq =
 941                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 942         }
 943
 944         if (MLX5_CAP_GEN(mdev, tag_matching)) {
 945                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
 946                 props->tm_caps.max_num_tags =
 947                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
 948                 props->tm_caps.flags = IB_TM_CAP_RC;
 949                 props->tm_caps.max_ops =
 950                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 951                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
 952         }
 953
 954         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
 955                 props->cq_caps.max_cq_moderation_count =
 956                                                 MLX5_MAX_CQ_COUNT;
 957                 props->cq_caps.max_cq_moderation_period =
 958                                                 MLX5_MAX_CQ_PERIOD;
 959         }
 960
 961         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 962                 resp.response_length += sizeof(resp.cqe_comp_caps);
 963
 964                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
 965                         resp.cqe_comp_caps.max_num =
 966                                 MLX5_CAP_GEN(dev->mdev,
 967                                              cqe_compression_max_num);
 968
 969                         resp.cqe_comp_caps.supported_format =
 970                                 MLX5_IB_CQE_RES_FORMAT_HASH |
 971                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
 972
 973                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
 974                                 resp.cqe_comp_caps.supported_format |=
 975                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
 976                 }
 977         }
 978
 979         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
 980             raw_support) {
 981                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
 982                     MLX5_CAP_GEN(mdev, qos)) {
 983                         resp.packet_pacing_caps.qp_rate_limit_max =
 984                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
 985                         resp.packet_pacing_caps.qp_rate_limit_min =
 986                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
 987                         resp.packet_pacing_caps.supported_qpts |=
 988                                 1 << IB_QPT_RAW_PACKET;
 989                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
 990                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
 991                                 resp.packet_pacing_caps.cap_flags |=
 992                                         MLX5_IB_PP_SUPPORT_BURST;
 993                 }
 994                 resp.response_length += sizeof(resp.packet_pacing_caps);
 995         }
 996
 997         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
 998                         uhw->outlen)) {
 999                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1000                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1001                                 MLX5_IB_ALLOW_MPW;
1002
1003                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1004                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1005                                 MLX5_IB_SUPPORT_EMPW;
1006
1007                 resp.response_length +=
1008                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1009         }
1010
1011         if (field_avail(typeof(resp), flags, uhw->outlen)) {
1012                 resp.response_length += sizeof(resp.flags);
1013
1014                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1015                         resp.flags |=
1016                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1017
1018                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1019                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1020         }
1021
1022         if (field_avail(typeof(resp), sw_parsing_caps,
1023                         uhw->outlen)) {
1024                 resp.response_length += sizeof(resp.sw_parsing_caps);
1025                 if (MLX5_CAP_ETH(mdev, swp)) {
1026                         resp.sw_parsing_caps.sw_parsing_offloads |=
1027                                 MLX5_IB_SW_PARSING;
1028
1029                         if (MLX5_CAP_ETH(mdev, swp_csum))
1030                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1031                                         MLX5_IB_SW_PARSING_CSUM;
1032
1033                         if (MLX5_CAP_ETH(mdev, swp_lso))
1034                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1035                                         MLX5_IB_SW_PARSING_LSO;
1036
1037                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1038                                 resp.sw_parsing_caps.supported_qpts =
1039                                         BIT(IB_QPT_RAW_PACKET);
1040                 }
1041         }
1042
1043         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1044             raw_support) {
1045                 resp.response_length += sizeof(resp.striding_rq_caps);
1046                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1047                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1048                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1049                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1050                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1051                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1052                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1053                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1054                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1055                         resp.striding_rq_caps.supported_qpts =
1056                                 BIT(IB_QPT_RAW_PACKET);
1057                 }
1058         }
1059
1060         if (field_avail(typeof(resp), tunnel_offloads_caps,
1061                         uhw->outlen)) {
1062                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1063                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1064                         resp.tunnel_offloads_caps |=
1065                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1066                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1067                         resp.tunnel_offloads_caps |=
1068                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1069                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1070                         resp.tunnel_offloads_caps |=
1071                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1072                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1073                     MLX5_FLEX_PROTO_CW_MPLS_GRE)
1074                         resp.tunnel_offloads_caps |=
1075                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1076                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1077                     MLX5_FLEX_PROTO_CW_MPLS_UDP)
1078                         resp.tunnel_offloads_caps |=
1079                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1080         }
1081
1082         if (uhw->outlen) {
1083                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1084
1085                 if (err)
1086                         return err;
1087         }
1088
1089         return 0;
1090 }
1091
1092 enum mlx5_ib_width {
1093         MLX5_IB_WIDTH_1X        = 1 << 0,
1094         MLX5_IB_WIDTH_2X        = 1 << 1,
1095         MLX5_IB_WIDTH_4X        = 1 << 2,
1096         MLX5_IB_WIDTH_8X        = 1 << 3,
1097         MLX5_IB_WIDTH_12X       = 1 << 4
1098 };
1099
1100 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1101                                   u8 *ib_width)
1102 {
1103         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1104         int err = 0;
1105
1106         if (active_width & MLX5_IB_WIDTH_1X) {
1107                 *ib_width = IB_WIDTH_1X;
1108         } else if (active_width & MLX5_IB_WIDTH_2X) {
1109                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1110                             (int)active_width);
1111                 err = -EINVAL;
1112         } else if (active_width & MLX5_IB_WIDTH_4X) {
1113                 *ib_width = IB_WIDTH_4X;
1114         } else if (active_width & MLX5_IB_WIDTH_8X) {
1115                 *ib_width = IB_WIDTH_8X;
1116         } else if (active_width & MLX5_IB_WIDTH_12X) {
1117                 *ib_width = IB_WIDTH_12X;
1118         } else {
1119                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1120                             (int)active_width);
1121                 err = -EINVAL;
1122         }
1123
1124         return err;
1125 }
1126
1127 static int mlx5_mtu_to_ib_mtu(int mtu)
1128 {
1129         switch (mtu) {
1130         case 256: return 1;
1131         case 512: return 2;
1132         case 1024: return 3;
1133         case 2048: return 4;
1134         case 4096: return 5;
1135         default:
1136                 pr_warn("invalid mtu\n");
1137                 return -1;
1138         }
1139 }
1140
1141 enum ib_max_vl_num {
1142         __IB_MAX_VL_0           = 1,
1143         __IB_MAX_VL_0_1         = 2,
1144         __IB_MAX_VL_0_3         = 3,
1145         __IB_MAX_VL_0_7         = 4,
1146         __IB_MAX_VL_0_14        = 5,
1147 };
1148
1149 enum mlx5_vl_hw_cap {
1150         MLX5_VL_HW_0    = 1,
1151         MLX5_VL_HW_0_1  = 2,
1152         MLX5_VL_HW_0_2  = 3,
1153         MLX5_VL_HW_0_3  = 4,
1154         MLX5_VL_HW_0_4  = 5,
1155         MLX5_VL_HW_0_5  = 6,
1156         MLX5_VL_HW_0_6  = 7,
1157         MLX5_VL_HW_0_7  = 8,
1158         MLX5_VL_HW_0_14 = 15
1159 };
1160
1161 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1162                                 u8 *max_vl_num)
1163 {
1164         switch (vl_hw_cap) {
1165         case MLX5_VL_HW_0:
1166                 *max_vl_num = __IB_MAX_VL_0;
1167                 break;
1168         case MLX5_VL_HW_0_1:
1169                 *max_vl_num = __IB_MAX_VL_0_1;
1170                 break;
1171         case MLX5_VL_HW_0_3:
1172                 *max_vl_num = __IB_MAX_VL_0_3;
1173                 break;
1174         case MLX5_VL_HW_0_7:
1175                 *max_vl_num = __IB_MAX_VL_0_7;
1176                 break;
1177         case MLX5_VL_HW_0_14:
1178                 *max_vl_num = __IB_MAX_VL_0_14;
1179                 break;
1180
1181         default:
1182                 return -EINVAL;
1183         }
1184
1185         return 0;
1186 }
1187
1188 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1189                                struct ib_port_attr *props)
1190 {
1191         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1192         struct mlx5_core_dev *mdev = dev->mdev;
1193         struct mlx5_hca_vport_context *rep;
1194         u16 max_mtu;
1195         u16 oper_mtu;
1196         int err;
1197         u8 ib_link_width_oper;
1198         u8 vl_hw_cap;
1199
1200         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1201         if (!rep) {
1202                 err = -ENOMEM;
1203                 goto out;
1204         }
1205
1206         /* props being zeroed by the caller, avoid zeroing it here */
1207
1208         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1209         if (err)
1210                 goto out;
1211
1212         props->lid              = rep->lid;
1213         props->lmc              = rep->lmc;
1214         props->sm_lid           = rep->sm_lid;
1215         props->sm_sl            = rep->sm_sl;
1216         props->state            = rep->vport_state;
1217         props->phys_state       = rep->port_physical_state;
1218         props->port_cap_flags   = rep->cap_mask1;
1219         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1220         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1221         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1222         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1223         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1224         props->subnet_timeout   = rep->subnet_timeout;
1225         props->init_type_reply  = rep->init_type_reply;
1226
1227         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1228         if (err)
1229                 goto out;
1230
1231         err = translate_active_width(ibdev, ib_link_width_oper,
1232                                      &props->active_width);
1233         if (err)
1234                 goto out;
1235         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1236         if (err)
1237                 goto out;
1238
1239         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1240
1241         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1242
1243         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1244
1245         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1246
1247         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1248         if (err)
1249                 goto out;
1250
1251         err = translate_max_vl_num(ibdev, vl_hw_cap,
1252                                    &props->max_vl_num);
1253 out:
1254         kfree(rep);
1255         return err;
1256 }
1257
1258 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1259                        struct ib_port_attr *props)
1260 {
1261         unsigned int count;
1262         int ret;
1263
1264         switch (mlx5_get_vport_access_method(ibdev)) {
1265         case MLX5_VPORT_ACCESS_METHOD_MAD:
1266                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1267                 break;
1268
1269         case MLX5_VPORT_ACCESS_METHOD_HCA:
1270                 ret = mlx5_query_hca_port(ibdev, port, props);
1271                 break;
1272
1273         case MLX5_VPORT_ACCESS_METHOD_NIC:
1274                 ret = mlx5_query_port_roce(ibdev, port, props);
1275                 break;
1276
1277         default:
1278                 ret = -EINVAL;
1279         }
1280
1281         if (!ret && props) {
1282                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1283                 struct mlx5_core_dev *mdev;
1284                 bool put_mdev = true;
1285
1286                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1287                 if (!mdev) {
1288                         /* If the port isn't affiliated yet query the master.
1289                          * The master and slave will have the same values.
1290                          */
1291                         mdev = dev->mdev;
1292                         port = 1;
1293                         put_mdev = false;
1294                 }
1295                 count = mlx5_core_reserved_gids_count(mdev);
1296                 if (put_mdev)
1297                         mlx5_ib_put_native_port_mdev(dev, port);
1298                 props->gid_tbl_len -= count;
1299         }
1300         return ret;
1301 }
1302
1303 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1304                                   struct ib_port_attr *props)
1305 {
1306         int ret;
1307
1308         /* Only link layer == ethernet is valid for representors */
1309         ret = mlx5_query_port_roce(ibdev, port, props);
1310         if (ret || !props)
1311                 return ret;
1312
1313         /* We don't support GIDS */
1314         props->gid_tbl_len = 0;
1315
1316         return ret;
1317 }
1318
1319 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1320                              union ib_gid *gid)
1321 {
1322         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1323         struct mlx5_core_dev *mdev = dev->mdev;
1324
1325         switch (mlx5_get_vport_access_method(ibdev)) {
1326         case MLX5_VPORT_ACCESS_METHOD_MAD:
1327                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1328
1329         case MLX5_VPORT_ACCESS_METHOD_HCA:
1330                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1331
1332         default:
1333                 return -EINVAL;
1334         }
1335
1336 }
1337
1338 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1339                                    u16 index, u16 *pkey)
1340 {
1341         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1342         struct mlx5_core_dev *mdev;
1343         bool put_mdev = true;
1344         u8 mdev_port_num;
1345         int err;
1346
1347         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1348         if (!mdev) {
1349                 /* The port isn't affiliated yet, get the PKey from the master
1350                  * port. For RoCE the PKey tables will be the same.
1351                  */
1352                 put_mdev = false;
1353                 mdev = dev->mdev;
1354                 mdev_port_num = 1;
1355         }
1356
1357         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1358                                         index, pkey);
1359         if (put_mdev)
1360                 mlx5_ib_put_native_port_mdev(dev, port);
1361
1362         return err;
1363 }
1364
1365 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1366                               u16 *pkey)
1367 {
1368         switch (mlx5_get_vport_access_method(ibdev)) {
1369         case MLX5_VPORT_ACCESS_METHOD_MAD:
1370                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1371
1372         case MLX5_VPORT_ACCESS_METHOD_HCA:
1373         case MLX5_VPORT_ACCESS_METHOD_NIC:
1374                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1375         default:
1376                 return -EINVAL;
1377         }
1378 }
1379
1380 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1381                                  struct ib_device_modify *props)
1382 {
1383         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1384         struct mlx5_reg_node_desc in;
1385         struct mlx5_reg_node_desc out;
1386         int err;
1387
1388         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1389                 return -EOPNOTSUPP;
1390
1391         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1392                 return 0;
1393
1394         /*
1395          * If possible, pass node desc to FW, so it can generate
1396          * a 144 trap.  If cmd fails, just ignore.
1397          */
1398         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1399         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1400                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1401         if (err)
1402                 return err;
1403
1404         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1405
1406         return err;
1407 }
1408
1409 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1410                                 u32 value)
1411 {
1412         struct mlx5_hca_vport_context ctx = {};
1413         struct mlx5_core_dev *mdev;
1414         u8 mdev_port_num;
1415         int err;
1416
1417         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1418         if (!mdev)
1419                 return -ENODEV;
1420
1421         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1422         if (err)
1423                 goto out;
1424
1425         if (~ctx.cap_mask1_perm & mask) {
1426                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1427                              mask, ctx.cap_mask1_perm);
1428                 err = -EINVAL;
1429                 goto out;
1430         }
1431
1432         ctx.cap_mask1 = value;
1433         ctx.cap_mask1_perm = mask;
1434         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1435                                                  0, &ctx);
1436
1437 out:
1438         mlx5_ib_put_native_port_mdev(dev, port_num);
1439
1440         return err;
1441 }
1442
1443 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1444                                struct ib_port_modify *props)
1445 {
1446         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1447         struct ib_port_attr attr;
1448         u32 tmp;
1449         int err;
1450         u32 change_mask;
1451         u32 value;
1452         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1453                       IB_LINK_LAYER_INFINIBAND);
1454
1455         /* CM layer calls ib_modify_port() regardless of the link layer. For
1456          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1457          */
1458         if (!is_ib)
1459                 return 0;
1460
1461         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1462                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1463                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1464                 return set_port_caps_atomic(dev, port, change_mask, value);
1465         }
1466
1467         mutex_lock(&dev->cap_mask_mutex);
1468
1469         err = ib_query_port(ibdev, port, &attr);
1470         if (err)
1471                 goto out;
1472
1473         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1474                 ~props->clr_port_cap_mask;
1475
1476         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1477
1478 out:
1479         mutex_unlock(&dev->cap_mask_mutex);
1480         return err;
1481 }
1482
1483 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1484 {
1485         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1486                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1487 }
1488
1489 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1490 {
1491         /* Large page with non 4k uar support might limit the dynamic size */
1492         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1493                 return MLX5_MIN_DYN_BFREGS;
1494
1495         return MLX5_MAX_DYN_BFREGS;
1496 }
1497
1498 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1499                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1500                              struct mlx5_bfreg_info *bfregi)
1501 {
1502         int uars_per_sys_page;
1503         int bfregs_per_sys_page;
1504         int ref_bfregs = req->total_num_bfregs;
1505
1506         if (req->total_num_bfregs == 0)
1507                 return -EINVAL;
1508
1509         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1510         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1511
1512         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1513                 return -ENOMEM;
1514
1515         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1516         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1517         /* This holds the required static allocation asked by the user */
1518         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1519         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1520                 return -EINVAL;
1521
1522         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1523         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1524         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1525         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1526
1527         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1528                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1529                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1530                     req->total_num_bfregs, bfregi->total_num_bfregs,
1531                     bfregi->num_sys_pages);
1532
1533         return 0;
1534 }
1535
1536 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1537 {
1538         struct mlx5_bfreg_info *bfregi;
1539         int err;
1540         int i;
1541
1542         bfregi = &context->bfregi;
1543         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1544                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1545                 if (err)
1546                         goto error;
1547
1548                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1549         }
1550
1551         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1552                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1553
1554         return 0;
1555
1556 error:
1557         for (--i; i >= 0; i--)
1558                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1559                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1560
1561         return err;
1562 }
1563
1564 static void deallocate_uars(struct mlx5_ib_dev *dev,
1565                             struct mlx5_ib_ucontext *context)
1566 {
1567         struct mlx5_bfreg_info *bfregi;
1568         int i;
1569
1570         bfregi = &context->bfregi;
1571         for (i = 0; i < bfregi->num_sys_pages; i++)
1572                 if (i < bfregi->num_static_sys_pages ||
1573                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1574                         mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1575 }
1576
1577 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1578 {
1579         int err = 0;
1580
1581         mutex_lock(&dev->lb.mutex);
1582         if (td)
1583                 dev->lb.user_td++;
1584         if (qp)
1585                 dev->lb.qps++;
1586
1587         if (dev->lb.user_td == 2 ||
1588             dev->lb.qps == 1) {
1589                 if (!dev->lb.enabled) {
1590                         err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1591                         dev->lb.enabled = true;
1592                 }
1593         }
1594
1595         mutex_unlock(&dev->lb.mutex);
1596
1597         return err;
1598 }
1599
1600 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1601 {
1602         mutex_lock(&dev->lb.mutex);
1603         if (td)
1604                 dev->lb.user_td--;
1605         if (qp)
1606                 dev->lb.qps--;
1607
1608         if (dev->lb.user_td == 1 &&
1609             dev->lb.qps == 0) {
1610                 if (dev->lb.enabled) {
1611                         mlx5_nic_vport_update_local_lb(dev->mdev, false);
1612                         dev->lb.enabled = false;
1613                 }
1614         }
1615
1616         mutex_unlock(&dev->lb.mutex);
1617 }
1618
1619 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1620                                           u16 uid)
1621 {
1622         int err;
1623
1624         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1625                 return 0;
1626
1627         err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1628         if (err)
1629                 return err;
1630
1631         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1632             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1633              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1634                 return err;
1635
1636         return mlx5_ib_enable_lb(dev, true, false);
1637 }
1638
1639 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1640                                              u16 uid)
1641 {
1642         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1643                 return;
1644
1645         mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1646
1647         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1648             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1649              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1650                 return;
1651
1652         mlx5_ib_disable_lb(dev, true, false);
1653 }
1654
1655 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1656                                                   struct ib_udata *udata)
1657 {
1658         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1659         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1660         struct mlx5_ib_alloc_ucontext_resp resp = {};
1661         struct mlx5_core_dev *mdev = dev->mdev;
1662         struct mlx5_ib_ucontext *context;
1663         struct mlx5_bfreg_info *bfregi;
1664         int ver;
1665         int err;
1666         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1667                                      max_cqe_version);
1668         u32 dump_fill_mkey;
1669         bool lib_uar_4k;
1670
1671         if (!dev->ib_active)
1672                 return ERR_PTR(-EAGAIN);
1673
1674         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1675                 ver = 0;
1676         else if (udata->inlen >= min_req_v2)
1677                 ver = 2;
1678         else
1679                 return ERR_PTR(-EINVAL);
1680
1681         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1682         if (err)
1683                 return ERR_PTR(err);
1684
1685         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1686                 return ERR_PTR(-EOPNOTSUPP);
1687
1688         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1689                 return ERR_PTR(-EOPNOTSUPP);
1690
1691         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1692                                     MLX5_NON_FP_BFREGS_PER_UAR);
1693         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1694                 return ERR_PTR(-EINVAL);
1695
1696         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1697         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1698                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1699         resp.cache_line_size = cache_line_size();
1700         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1701         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1702         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1703         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1704         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1705         resp.cqe_version = min_t(__u8,
1706                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1707                                  req.max_cqe_version);
1708         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1709                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1710         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1711                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1712         resp.response_length = min(offsetof(typeof(resp), response_length) +
1713                                    sizeof(resp.response_length), udata->outlen);
1714
1715         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1716                 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1717                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1718                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1719                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1720                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1721                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1722                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1723                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1724                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1725         }
1726
1727         context = kzalloc(sizeof(*context), GFP_KERNEL);
1728         if (!context)
1729                 return ERR_PTR(-ENOMEM);
1730
1731         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1732         bfregi = &context->bfregi;
1733
1734         /* updates req->total_num_bfregs */
1735         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1736         if (err)
1737                 goto out_ctx;
1738
1739         mutex_init(&bfregi->lock);
1740         bfregi->lib_uar_4k = lib_uar_4k;
1741         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1742                                 GFP_KERNEL);
1743         if (!bfregi->count) {
1744                 err = -ENOMEM;
1745                 goto out_ctx;
1746         }
1747
1748         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1749                                     sizeof(*bfregi->sys_pages),
1750                                     GFP_KERNEL);
1751         if (!bfregi->sys_pages) {
1752                 err = -ENOMEM;
1753                 goto out_count;
1754         }
1755
1756         err = allocate_uars(dev, context);
1757         if (err)
1758                 goto out_sys_pages;
1759
1760 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1761         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1762 #endif
1763
1764         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1765                 err = mlx5_ib_devx_create(dev);
1766                 if (err < 0)
1767                         goto out_uars;
1768                 context->devx_uid = err;
1769         }
1770
1771         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1772                                              context->devx_uid);
1773         if (err)
1774                 goto out_devx;
1775
1776         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1777                 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1778                 if (err)
1779                         goto out_mdev;
1780         }
1781
1782         INIT_LIST_HEAD(&context->db_page_list);
1783         mutex_init(&context->db_page_mutex);
1784
1785         resp.tot_bfregs = req.total_num_bfregs;
1786         resp.num_ports = dev->num_ports;
1787
1788         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1789                 resp.response_length += sizeof(resp.cqe_version);
1790
1791         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1792                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1793                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1794                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1795         }
1796
1797         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1798                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1799                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1800                         resp.eth_min_inline++;
1801                 }
1802                 resp.response_length += sizeof(resp.eth_min_inline);
1803         }
1804
1805         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1806                 if (mdev->clock_info)
1807                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1808                 resp.response_length += sizeof(resp.clock_info_versions);
1809         }
1810
1811         /*
1812          * We don't want to expose information from the PCI bar that is located
1813          * after 4096 bytes, so if the arch only supports larger pages, let's
1814          * pretend we don't support reading the HCA's core clock. This is also
1815          * forced by mmap function.
1816          */
1817         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1818                 if (PAGE_SIZE <= 4096) {
1819                         resp.comp_mask |=
1820                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1821                         resp.hca_core_clock_offset =
1822                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1823                 }
1824                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1825         }
1826
1827         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1828                 resp.response_length += sizeof(resp.log_uar_size);
1829
1830         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1831                 resp.response_length += sizeof(resp.num_uars_per_page);
1832
1833         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1834                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1835                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1836         }
1837
1838         if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1839                 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1840                         resp.dump_fill_mkey = dump_fill_mkey;
1841                         resp.comp_mask |=
1842                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1843                 }
1844                 resp.response_length += sizeof(resp.dump_fill_mkey);
1845         }
1846
1847         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1848         if (err)
1849                 goto out_mdev;
1850
1851         bfregi->ver = ver;
1852         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1853         context->cqe_version = resp.cqe_version;
1854         context->lib_caps = req.lib_caps;
1855         print_lib_caps(dev, context->lib_caps);
1856
1857         if (mlx5_lag_is_active(dev->mdev)) {
1858                 u8 port = mlx5_core_native_port_num(dev->mdev);
1859
1860                 atomic_set(&context->tx_port_affinity,
1861                            atomic_add_return(
1862                                    1, &dev->roce[port].tx_port_affinity));
1863         }
1864
1865         return &context->ibucontext;
1866
1867 out_mdev:
1868         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1869 out_devx:
1870         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1871                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1872
1873 out_uars:
1874         deallocate_uars(dev, context);
1875
1876 out_sys_pages:
1877         kfree(bfregi->sys_pages);
1878
1879 out_count:
1880         kfree(bfregi->count);
1881
1882 out_ctx:
1883         kfree(context);
1884
1885         return ERR_PTR(err);
1886 }
1887
1888 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1889 {
1890         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1891         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1892         struct mlx5_bfreg_info *bfregi;
1893
1894 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1895         /* All umem's must be destroyed before destroying the ucontext. */
1896         mutex_lock(&ibcontext->per_mm_list_lock);
1897         WARN_ON(!list_empty(&ibcontext->per_mm_list));
1898         mutex_unlock(&ibcontext->per_mm_list_lock);
1899 #endif
1900
1901         bfregi = &context->bfregi;
1902         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1903
1904         if (context->devx_uid)
1905                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1906
1907         deallocate_uars(dev, context);
1908         kfree(bfregi->sys_pages);
1909         kfree(bfregi->count);
1910         kfree(context);
1911
1912         return 0;
1913 }
1914
1915 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1916                                  int uar_idx)
1917 {
1918         int fw_uars_per_page;
1919
1920         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1921
1922         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1923 }
1924
1925 static int get_command(unsigned long offset)
1926 {
1927         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1928 }
1929
1930 static int get_arg(unsigned long offset)
1931 {
1932         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1933 }
1934
1935 static int get_index(unsigned long offset)
1936 {
1937         return get_arg(offset);
1938 }
1939
1940 /* Index resides in an extra byte to enable larger values than 255 */
1941 static int get_extended_index(unsigned long offset)
1942 {
1943         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1944 }
1945
1946
1947 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1948 {
1949 }
1950
1951 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1952 {
1953         switch (cmd) {
1954         case MLX5_IB_MMAP_WC_PAGE:
1955                 return "WC";
1956         case MLX5_IB_MMAP_REGULAR_PAGE:
1957                 return "best effort WC";
1958         case MLX5_IB_MMAP_NC_PAGE:
1959                 return "NC";
1960         case MLX5_IB_MMAP_DEVICE_MEM:
1961                 return "Device Memory";
1962         default:
1963                 return NULL;
1964         }
1965 }
1966
1967 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1968                                         struct vm_area_struct *vma,
1969                                         struct mlx5_ib_ucontext *context)
1970 {
1971         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1972                 return -EINVAL;
1973
1974         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
1975                 return -EOPNOTSUPP;
1976
1977         if (vma->vm_flags & VM_WRITE)
1978                 return -EPERM;
1979
1980         if (!dev->mdev->clock_info_page)
1981                 return -EOPNOTSUPP;
1982
1983         return rdma_user_mmap_page(&context->ibucontext, vma,
1984                                    dev->mdev->clock_info_page, PAGE_SIZE);
1985 }
1986
1987 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1988                     struct vm_area_struct *vma,
1989                     struct mlx5_ib_ucontext *context)
1990 {
1991         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1992         int err;
1993         unsigned long idx;
1994         phys_addr_t pfn;
1995         pgprot_t prot;
1996         u32 bfreg_dyn_idx = 0;
1997         u32 uar_index;
1998         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
1999         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2000                                 bfregi->num_static_sys_pages;
2001
2002         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2003                 return -EINVAL;
2004
2005         if (dyn_uar)
2006                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2007         else
2008                 idx = get_index(vma->vm_pgoff);
2009
2010         if (idx >= max_valid_idx) {
2011                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2012                              idx, max_valid_idx);
2013                 return -EINVAL;
2014         }
2015
2016         switch (cmd) {
2017         case MLX5_IB_MMAP_WC_PAGE:
2018         case MLX5_IB_MMAP_ALLOC_WC:
2019 /* Some architectures don't support WC memory */
2020 #if defined(CONFIG_X86)
2021                 if (!pat_enabled())
2022                         return -EPERM;
2023 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2024                         return -EPERM;
2025 #endif
2026         /* fall through */
2027         case MLX5_IB_MMAP_REGULAR_PAGE:
2028                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2029                 prot = pgprot_writecombine(vma->vm_page_prot);
2030                 break;
2031         case MLX5_IB_MMAP_NC_PAGE:
2032                 prot = pgprot_noncached(vma->vm_page_prot);
2033                 break;
2034         default:
2035                 return -EINVAL;
2036         }
2037
2038         if (dyn_uar) {
2039                 int uars_per_page;
2040
2041                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2042                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2043                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2044                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2045                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2046                         return -EINVAL;
2047                 }
2048
2049                 mutex_lock(&bfregi->lock);
2050                 /* Fail if uar already allocated, first bfreg index of each
2051                  * page holds its count.
2052                  */
2053                 if (bfregi->count[bfreg_dyn_idx]) {
2054                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2055                         mutex_unlock(&bfregi->lock);
2056                         return -EINVAL;
2057                 }
2058
2059                 bfregi->count[bfreg_dyn_idx]++;
2060                 mutex_unlock(&bfregi->lock);
2061
2062                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2063                 if (err) {
2064                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2065                         goto free_bfreg;
2066                 }
2067         } else {
2068                 uar_index = bfregi->sys_pages[idx];
2069         }
2070
2071         pfn = uar_index2pfn(dev, uar_index);
2072         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2073
2074         err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2075                                 prot);
2076         if (err) {
2077                 mlx5_ib_err(dev,
2078                             "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2079                             err, mmap_cmd2str(cmd));
2080                 goto err;
2081         }
2082
2083         if (dyn_uar)
2084                 bfregi->sys_pages[idx] = uar_index;
2085         return 0;
2086
2087 err:
2088         if (!dyn_uar)
2089                 return err;
2090
2091         mlx5_cmd_free_uar(dev->mdev, idx);
2092
2093 free_bfreg:
2094         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2095
2096         return err;
2097 }
2098
2099 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2100 {
2101         struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2102         struct mlx5_ib_dev *dev = to_mdev(context->device);
2103         u16 page_idx = get_extended_index(vma->vm_pgoff);
2104         size_t map_size = vma->vm_end - vma->vm_start;
2105         u32 npages = map_size >> PAGE_SHIFT;
2106         phys_addr_t pfn;
2107
2108         if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2109             page_idx + npages)
2110                 return -EINVAL;
2111
2112         pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2113               MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2114               PAGE_SHIFT) +
2115               page_idx;
2116         return rdma_user_mmap_io(context, vma, pfn, map_size,
2117                                  pgprot_writecombine(vma->vm_page_prot));
2118 }
2119
2120 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2121 {
2122         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2123         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2124         unsigned long command;
2125         phys_addr_t pfn;
2126
2127         command = get_command(vma->vm_pgoff);
2128         switch (command) {
2129         case MLX5_IB_MMAP_WC_PAGE:
2130         case MLX5_IB_MMAP_NC_PAGE:
2131         case MLX5_IB_MMAP_REGULAR_PAGE:
2132         case MLX5_IB_MMAP_ALLOC_WC:
2133                 return uar_mmap(dev, command, vma, context);
2134
2135         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2136                 return -ENOSYS;
2137
2138         case MLX5_IB_MMAP_CORE_CLOCK:
2139                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2140                         return -EINVAL;
2141
2142                 if (vma->vm_flags & VM_WRITE)
2143                         return -EPERM;
2144
2145                 /* Don't expose to user-space information it shouldn't have */
2146                 if (PAGE_SIZE > 4096)
2147                         return -EOPNOTSUPP;
2148
2149                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2150                 pfn = (dev->mdev->iseg_base +
2151                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2152                         PAGE_SHIFT;
2153                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2154                                        PAGE_SIZE, vma->vm_page_prot))
2155                         return -EAGAIN;
2156                 break;
2157         case MLX5_IB_MMAP_CLOCK_INFO:
2158                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2159
2160         case MLX5_IB_MMAP_DEVICE_MEM:
2161                 return dm_mmap(ibcontext, vma);
2162
2163         default:
2164                 return -EINVAL;
2165         }
2166
2167         return 0;
2168 }
2169
2170 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2171                                struct ib_ucontext *context,
2172                                struct ib_dm_alloc_attr *attr,
2173                                struct uverbs_attr_bundle *attrs)
2174 {
2175         u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2176         struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2177         phys_addr_t memic_addr;
2178         struct mlx5_ib_dm *dm;
2179         u64 start_offset;
2180         u32 page_idx;
2181         int err;
2182
2183         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2184         if (!dm)
2185                 return ERR_PTR(-ENOMEM);
2186
2187         mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2188                     attr->length, act_size, attr->alignment);
2189
2190         err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2191                                    act_size, attr->alignment);
2192         if (err)
2193                 goto err_free;
2194
2195         start_offset = memic_addr & ~PAGE_MASK;
2196         page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2197                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2198                     PAGE_SHIFT;
2199
2200         err = uverbs_copy_to(attrs,
2201                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2202                              &start_offset, sizeof(start_offset));
2203         if (err)
2204                 goto err_dealloc;
2205
2206         err = uverbs_copy_to(attrs,
2207                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2208                              &page_idx, sizeof(page_idx));
2209         if (err)
2210                 goto err_dealloc;
2211
2212         bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2213                    DIV_ROUND_UP(act_size, PAGE_SIZE));
2214
2215         dm->dev_addr = memic_addr;
2216
2217         return &dm->ibdm;
2218
2219 err_dealloc:
2220         mlx5_cmd_dealloc_memic(memic, memic_addr,
2221                                act_size);
2222 err_free:
2223         kfree(dm);
2224         return ERR_PTR(err);
2225 }
2226
2227 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2228 {
2229         struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2230         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2231         u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2232         u32 page_idx;
2233         int ret;
2234
2235         ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2236         if (ret)
2237                 return ret;
2238
2239         page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2240                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2241                     PAGE_SHIFT;
2242         bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2243                      page_idx,
2244                      DIV_ROUND_UP(act_size, PAGE_SIZE));
2245
2246         kfree(dm);
2247
2248         return 0;
2249 }
2250
2251 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2252                                       struct ib_ucontext *context,
2253                                       struct ib_udata *udata)
2254 {
2255         struct mlx5_ib_alloc_pd_resp resp;
2256         struct mlx5_ib_pd *pd;
2257         int err;
2258         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2259         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)]   = {};
2260         u16 uid = 0;
2261
2262         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2263         if (!pd)
2264                 return ERR_PTR(-ENOMEM);
2265
2266         uid = context ? to_mucontext(context)->devx_uid : 0;
2267         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2268         MLX5_SET(alloc_pd_in, in, uid, uid);
2269         err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2270                             out, sizeof(out));
2271         if (err) {
2272                 kfree(pd);
2273                 return ERR_PTR(err);
2274         }
2275
2276         pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2277         pd->uid = uid;
2278         if (context) {
2279                 resp.pdn = pd->pdn;
2280                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2281                         mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2282                         kfree(pd);
2283                         return ERR_PTR(-EFAULT);
2284                 }
2285         }
2286
2287         return &pd->ibpd;
2288 }
2289
2290 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2291 {
2292         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2293         struct mlx5_ib_pd *mpd = to_mpd(pd);
2294
2295         mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2296         kfree(mpd);
2297
2298         return 0;
2299 }
2300
2301 enum {
2302         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2303         MATCH_CRITERIA_ENABLE_MISC_BIT,
2304         MATCH_CRITERIA_ENABLE_INNER_BIT,
2305         MATCH_CRITERIA_ENABLE_MISC2_BIT
2306 };
2307
2308 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2309         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2310                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2311
2312 static u8 get_match_criteria_enable(u32 *match_criteria)
2313 {
2314         u8 match_criteria_enable;
2315
2316         match_criteria_enable =
2317                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2318                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2319         match_criteria_enable |=
2320                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2321                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2322         match_criteria_enable |=
2323                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2324                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2325         match_criteria_enable |=
2326                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2327                 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2328
2329         return match_criteria_enable;
2330 }
2331
2332 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2333 {
2334         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2335         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2336 }
2337
2338 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2339                            bool inner)
2340 {
2341         if (inner) {
2342                 MLX5_SET(fte_match_set_misc,
2343                          misc_c, inner_ipv6_flow_label, mask);
2344                 MLX5_SET(fte_match_set_misc,
2345                          misc_v, inner_ipv6_flow_label, val);
2346         } else {
2347                 MLX5_SET(fte_match_set_misc,
2348                          misc_c, outer_ipv6_flow_label, mask);
2349                 MLX5_SET(fte_match_set_misc,
2350                          misc_v, outer_ipv6_flow_label, val);
2351         }
2352 }
2353
2354 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2355 {
2356         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2357         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2358         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2359         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2360 }
2361
2362 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2363 {
2364         if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2365             !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2366                 return -EOPNOTSUPP;
2367
2368         if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2369             !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2370                 return -EOPNOTSUPP;
2371
2372         if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2373             !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2374                 return -EOPNOTSUPP;
2375
2376         if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2377             !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2378                 return -EOPNOTSUPP;
2379
2380         return 0;
2381 }
2382
2383 #define LAST_ETH_FIELD vlan_tag
2384 #define LAST_IB_FIELD sl
2385 #define LAST_IPV4_FIELD tos
2386 #define LAST_IPV6_FIELD traffic_class
2387 #define LAST_TCP_UDP_FIELD src_port
2388 #define LAST_TUNNEL_FIELD tunnel_id
2389 #define LAST_FLOW_TAG_FIELD tag_id
2390 #define LAST_DROP_FIELD size
2391 #define LAST_COUNTERS_FIELD counters
2392
2393 /* Field is the last supported field */
2394 #define FIELDS_NOT_SUPPORTED(filter, field)\
2395         memchr_inv((void *)&filter.field  +\
2396                    sizeof(filter.field), 0,\
2397                    sizeof(filter) -\
2398                    offsetof(typeof(filter), field) -\
2399                    sizeof(filter.field))
2400
2401 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2402                            bool is_egress,
2403                            struct mlx5_flow_act *action)
2404 {
2405
2406         switch (maction->ib_action.type) {
2407         case IB_FLOW_ACTION_ESP:
2408                 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2409                                       MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2410                         return -EINVAL;
2411                 /* Currently only AES_GCM keymat is supported by the driver */
2412                 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2413                 action->action |= is_egress ?
2414                         MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2415                         MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2416                 return 0;
2417         case IB_FLOW_ACTION_UNSPECIFIED:
2418                 if (maction->flow_action_raw.sub_type ==
2419                     MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
2420                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2421                                 return -EINVAL;
2422                         action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2423                         action->modify_id = maction->flow_action_raw.action_id;
2424                         return 0;
2425                 }
2426                 if (maction->flow_action_raw.sub_type ==
2427                     MLX5_IB_FLOW_ACTION_DECAP) {
2428                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2429                                 return -EINVAL;
2430                         action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2431                         return 0;
2432                 }
2433                 if (maction->flow_action_raw.sub_type ==
2434                     MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
2435                         if (action->action &
2436                             MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2437                                 return -EINVAL;
2438                         action->action |=
2439                                 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2440                         action->reformat_id =
2441                                 maction->flow_action_raw.action_id;
2442                         return 0;
2443                 }
2444                 /* fall through */
2445         default:
2446                 return -EOPNOTSUPP;
2447         }
2448 }
2449
2450 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2451                            u32 *match_v, const union ib_flow_spec *ib_spec,
2452                            const struct ib_flow_attr *flow_attr,
2453                            struct mlx5_flow_act *action, u32 prev_type)
2454 {
2455         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2456                                            misc_parameters);
2457         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2458                                            misc_parameters);
2459         void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2460                                             misc_parameters_2);
2461         void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2462                                             misc_parameters_2);
2463         void *headers_c;
2464         void *headers_v;
2465         int match_ipv;
2466         int ret;
2467
2468         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2469                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2470                                          inner_headers);
2471                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2472                                          inner_headers);
2473                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2474                                         ft_field_support.inner_ip_version);
2475         } else {
2476                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2477                                          outer_headers);
2478                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2479                                          outer_headers);
2480                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2481                                         ft_field_support.outer_ip_version);
2482         }
2483
2484         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2485         case IB_FLOW_SPEC_ETH:
2486                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2487                         return -EOPNOTSUPP;
2488
2489                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2490                                              dmac_47_16),
2491                                 ib_spec->eth.mask.dst_mac);
2492                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2493                                              dmac_47_16),
2494                                 ib_spec->eth.val.dst_mac);
2495
2496                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2497                                              smac_47_16),
2498                                 ib_spec->eth.mask.src_mac);
2499                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2500                                              smac_47_16),
2501                                 ib_spec->eth.val.src_mac);
2502
2503                 if (ib_spec->eth.mask.vlan_tag) {
2504                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2505                                  cvlan_tag, 1);
2506                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2507                                  cvlan_tag, 1);
2508
2509                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2510                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2511                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2512                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2513
2514                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2515                                  first_cfi,
2516                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2517                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2518                                  first_cfi,
2519                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2520
2521                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2522                                  first_prio,
2523                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2524                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2525                                  first_prio,
2526                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2527                 }
2528                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2529                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2530                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2531                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2532                 break;
2533         case IB_FLOW_SPEC_IPV4:
2534                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2535                         return -EOPNOTSUPP;
2536
2537                 if (match_ipv) {
2538                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2539                                  ip_version, 0xf);
2540                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2541                                  ip_version, MLX5_FS_IPV4_VERSION);
2542                 } else {
2543                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2544                                  ethertype, 0xffff);
2545                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2546                                  ethertype, ETH_P_IP);
2547                 }
2548
2549                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2550                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2551                        &ib_spec->ipv4.mask.src_ip,
2552                        sizeof(ib_spec->ipv4.mask.src_ip));
2553                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2554                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2555                        &ib_spec->ipv4.val.src_ip,
2556                        sizeof(ib_spec->ipv4.val.src_ip));
2557                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2558                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2559                        &ib_spec->ipv4.mask.dst_ip,
2560                        sizeof(ib_spec->ipv4.mask.dst_ip));
2561                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2562                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2563                        &ib_spec->ipv4.val.dst_ip,
2564                        sizeof(ib_spec->ipv4.val.dst_ip));
2565
2566                 set_tos(headers_c, headers_v,
2567                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2568
2569                 set_proto(headers_c, headers_v,
2570                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2571                 break;
2572         case IB_FLOW_SPEC_IPV6:
2573                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2574                         return -EOPNOTSUPP;
2575
2576                 if (match_ipv) {
2577                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2578                                  ip_version, 0xf);
2579                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2580                                  ip_version, MLX5_FS_IPV6_VERSION);
2581                 } else {
2582                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2583                                  ethertype, 0xffff);
2584                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2585                                  ethertype, ETH_P_IPV6);
2586                 }
2587
2588                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2589                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2590                        &ib_spec->ipv6.mask.src_ip,
2591                        sizeof(ib_spec->ipv6.mask.src_ip));
2592                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2593                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2594                        &ib_spec->ipv6.val.src_ip,
2595                        sizeof(ib_spec->ipv6.val.src_ip));
2596                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2597                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2598                        &ib_spec->ipv6.mask.dst_ip,
2599                        sizeof(ib_spec->ipv6.mask.dst_ip));
2600                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2601                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2602                        &ib_spec->ipv6.val.dst_ip,
2603                        sizeof(ib_spec->ipv6.val.dst_ip));
2604
2605                 set_tos(headers_c, headers_v,
2606                         ib_spec->ipv6.mask.traffic_class,
2607                         ib_spec->ipv6.val.traffic_class);
2608
2609                 set_proto(headers_c, headers_v,
2610                           ib_spec->ipv6.mask.next_hdr,
2611                           ib_spec->ipv6.val.next_hdr);
2612
2613                 set_flow_label(misc_params_c, misc_params_v,
2614                                ntohl(ib_spec->ipv6.mask.flow_label),
2615                                ntohl(ib_spec->ipv6.val.flow_label),
2616                                ib_spec->type & IB_FLOW_SPEC_INNER);
2617                 break;
2618         case IB_FLOW_SPEC_ESP:
2619                 if (ib_spec->esp.mask.seq)
2620                         return -EOPNOTSUPP;
2621
2622                 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2623                          ntohl(ib_spec->esp.mask.spi));
2624                 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2625                          ntohl(ib_spec->esp.val.spi));
2626                 break;
2627         case IB_FLOW_SPEC_TCP:
2628                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2629                                          LAST_TCP_UDP_FIELD))
2630                         return -EOPNOTSUPP;
2631
2632                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2633                          0xff);
2634                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2635                          IPPROTO_TCP);
2636
2637                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2638                          ntohs(ib_spec->tcp_udp.mask.src_port));
2639                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2640                          ntohs(ib_spec->tcp_udp.val.src_port));
2641
2642                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2643                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2644                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2645                          ntohs(ib_spec->tcp_udp.val.dst_port));
2646                 break;
2647         case IB_FLOW_SPEC_UDP:
2648                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2649                                          LAST_TCP_UDP_FIELD))
2650                         return -EOPNOTSUPP;
2651
2652                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2653                          0xff);
2654                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2655                          IPPROTO_UDP);
2656
2657                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2658                          ntohs(ib_spec->tcp_udp.mask.src_port));
2659                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2660                          ntohs(ib_spec->tcp_udp.val.src_port));
2661
2662                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2663                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2664                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2665                          ntohs(ib_spec->tcp_udp.val.dst_port));
2666                 break;
2667         case IB_FLOW_SPEC_GRE:
2668                 if (ib_spec->gre.mask.c_ks_res0_ver)
2669                         return -EOPNOTSUPP;
2670
2671                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2672                          0xff);
2673                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2674                          IPPROTO_GRE);
2675
2676                 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2677                          ntohs(ib_spec->gre.mask.protocol));
2678                 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2679                          ntohs(ib_spec->gre.val.protocol));
2680
2681                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2682                                     gre_key_h),
2683                        &ib_spec->gre.mask.key,
2684                        sizeof(ib_spec->gre.mask.key));
2685                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2686                                     gre_key_h),
2687                        &ib_spec->gre.val.key,
2688                        sizeof(ib_spec->gre.val.key));
2689                 break;
2690         case IB_FLOW_SPEC_MPLS:
2691                 switch (prev_type) {
2692                 case IB_FLOW_SPEC_UDP:
2693                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2694                                                    ft_field_support.outer_first_mpls_over_udp),
2695                                                    &ib_spec->mpls.mask.tag))
2696                                 return -EOPNOTSUPP;
2697
2698                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2699                                             outer_first_mpls_over_udp),
2700                                &ib_spec->mpls.val.tag,
2701                                sizeof(ib_spec->mpls.val.tag));
2702                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2703                                             outer_first_mpls_over_udp),
2704                                &ib_spec->mpls.mask.tag,
2705                                sizeof(ib_spec->mpls.mask.tag));
2706                         break;
2707                 case IB_FLOW_SPEC_GRE:
2708                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2709                                                    ft_field_support.outer_first_mpls_over_gre),
2710                                                    &ib_spec->mpls.mask.tag))
2711                                 return -EOPNOTSUPP;
2712
2713                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2714                                             outer_first_mpls_over_gre),
2715                                &ib_spec->mpls.val.tag,
2716                                sizeof(ib_spec->mpls.val.tag));
2717                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2718                                             outer_first_mpls_over_gre),
2719                                &ib_spec->mpls.mask.tag,
2720                                sizeof(ib_spec->mpls.mask.tag));
2721                         break;
2722                 default:
2723                         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2724                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2725                                                            ft_field_support.inner_first_mpls),
2726                                                            &ib_spec->mpls.mask.tag))
2727                                         return -EOPNOTSUPP;
2728
2729                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2730                                                     inner_first_mpls),
2731                                        &ib_spec->mpls.val.tag,
2732                                        sizeof(ib_spec->mpls.val.tag));
2733                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2734                                                     inner_first_mpls),
2735                                        &ib_spec->mpls.mask.tag,
2736                                        sizeof(ib_spec->mpls.mask.tag));
2737                         } else {
2738                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2739                                                            ft_field_support.outer_first_mpls),
2740                                                            &ib_spec->mpls.mask.tag))
2741                                         return -EOPNOTSUPP;
2742
2743                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2744                                                     outer_first_mpls),
2745                                        &ib_spec->mpls.val.tag,
2746                                        sizeof(ib_spec->mpls.val.tag));
2747                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2748                                                     outer_first_mpls),
2749                                        &ib_spec->mpls.mask.tag,
2750                                        sizeof(ib_spec->mpls.mask.tag));
2751                         }
2752                 }
2753                 break;
2754         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2755                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2756                                          LAST_TUNNEL_FIELD))
2757                         return -EOPNOTSUPP;
2758
2759                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2760                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2761                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2762                          ntohl(ib_spec->tunnel.val.tunnel_id));
2763                 break;
2764         case IB_FLOW_SPEC_ACTION_TAG:
2765                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2766                                          LAST_FLOW_TAG_FIELD))
2767                         return -EOPNOTSUPP;
2768                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2769                         return -EINVAL;
2770
2771                 action->flow_tag = ib_spec->flow_tag.tag_id;
2772                 action->flags |= FLOW_ACT_HAS_TAG;
2773                 break;
2774         case IB_FLOW_SPEC_ACTION_DROP:
2775                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2776                                          LAST_DROP_FIELD))
2777                         return -EOPNOTSUPP;
2778                 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2779                 break;
2780         case IB_FLOW_SPEC_ACTION_HANDLE:
2781                 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
2782                         flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
2783                 if (ret)
2784                         return ret;
2785                 break;
2786         case IB_FLOW_SPEC_ACTION_COUNT:
2787                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2788                                          LAST_COUNTERS_FIELD))
2789                         return -EOPNOTSUPP;
2790
2791                 /* for now support only one counters spec per flow */
2792                 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2793                         return -EINVAL;
2794
2795                 action->counters = ib_spec->flow_count.counters;
2796                 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2797                 break;
2798         default:
2799                 return -EINVAL;
2800         }
2801
2802         return 0;
2803 }
2804
2805 /* If a flow could catch both multicast and unicast packets,
2806  * it won't fall into the multicast flow steering table and this rule
2807  * could steal other multicast packets.
2808  */
2809 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2810 {
2811         union ib_flow_spec *flow_spec;
2812
2813         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2814             ib_attr->num_of_specs < 1)
2815                 return false;
2816
2817         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2818         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2819                 struct ib_flow_spec_ipv4 *ipv4_spec;
2820
2821                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2822                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2823                         return true;
2824
2825                 return false;
2826         }
2827
2828         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2829                 struct ib_flow_spec_eth *eth_spec;
2830
2831                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2832                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2833                        is_multicast_ether_addr(eth_spec->val.dst_mac);
2834         }
2835
2836         return false;
2837 }
2838
2839 enum valid_spec {
2840         VALID_SPEC_INVALID,
2841         VALID_SPEC_VALID,
2842         VALID_SPEC_NA,
2843 };
2844
2845 static enum valid_spec
2846 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2847                      const struct mlx5_flow_spec *spec,
2848                      const struct mlx5_flow_act *flow_act,
2849                      bool egress)
2850 {
2851         const u32 *match_c = spec->match_criteria;
2852         bool is_crypto =
2853                 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2854                                      MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2855         bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2856         bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2857
2858         /*
2859          * Currently only crypto is supported in egress, when regular egress
2860          * rules would be supported, always return VALID_SPEC_NA.
2861          */
2862         if (!is_crypto)
2863                 return VALID_SPEC_NA;
2864
2865         return is_crypto && is_ipsec &&
2866                 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ?
2867                 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2868 }
2869
2870 static bool is_valid_spec(struct mlx5_core_dev *mdev,
2871                           const struct mlx5_flow_spec *spec,
2872                           const struct mlx5_flow_act *flow_act,
2873                           bool egress)
2874 {
2875         /* We curretly only support ipsec egress flow */
2876         return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2877 }
2878
2879 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2880                                const struct ib_flow_attr *flow_attr,
2881                                bool check_inner)
2882 {
2883         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2884         int match_ipv = check_inner ?
2885                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2886                                         ft_field_support.inner_ip_version) :
2887                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2888                                         ft_field_support.outer_ip_version);
2889         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2890         bool ipv4_spec_valid, ipv6_spec_valid;
2891         unsigned int ip_spec_type = 0;
2892         bool has_ethertype = false;
2893         unsigned int spec_index;
2894         bool mask_valid = true;
2895         u16 eth_type = 0;
2896         bool type_valid;
2897
2898         /* Validate that ethertype is correct */
2899         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2900                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2901                     ib_spec->eth.mask.ether_type) {
2902                         mask_valid = (ib_spec->eth.mask.ether_type ==
2903                                       htons(0xffff));
2904                         has_ethertype = true;
2905                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2906                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2907                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2908                         ip_spec_type = ib_spec->type;
2909                 }
2910                 ib_spec = (void *)ib_spec + ib_spec->size;
2911         }
2912
2913         type_valid = (!has_ethertype) || (!ip_spec_type);
2914         if (!type_valid && mask_valid) {
2915                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2916                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2917                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2918                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2919
2920                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2921                              (((eth_type == ETH_P_MPLS_UC) ||
2922                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2923         }
2924
2925         return type_valid;
2926 }
2927
2928 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2929                           const struct ib_flow_attr *flow_attr)
2930 {
2931         return is_valid_ethertype(mdev, flow_attr, false) &&
2932                is_valid_ethertype(mdev, flow_attr, true);
2933 }
2934
2935 static void put_flow_table(struct mlx5_ib_dev *dev,
2936                            struct mlx5_ib_flow_prio *prio, bool ft_added)
2937 {
2938         prio->refcount -= !!ft_added;
2939         if (!prio->refcount) {
2940                 mlx5_destroy_flow_table(prio->flow_table);
2941                 prio->flow_table = NULL;
2942         }
2943 }
2944
2945 static void counters_clear_description(struct ib_counters *counters)
2946 {
2947         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2948
2949         mutex_lock(&mcounters->mcntrs_mutex);
2950         kfree(mcounters->counters_data);
2951         mcounters->counters_data = NULL;
2952         mcounters->cntrs_max_index = 0;
2953         mutex_unlock(&mcounters->mcntrs_mutex);
2954 }
2955
2956 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2957 {
2958         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2959                                                           struct mlx5_ib_flow_handler,
2960                                                           ibflow);
2961         struct mlx5_ib_flow_handler *iter, *tmp;
2962         struct mlx5_ib_dev *dev = handler->dev;
2963
2964         mutex_lock(&dev->flow_db->lock);
2965
2966         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2967                 mlx5_del_flow_rules(iter->rule);
2968                 put_flow_table(dev, iter->prio, true);
2969                 list_del(&iter->list);
2970                 kfree(iter);
2971         }
2972
2973         mlx5_del_flow_rules(handler->rule);
2974         put_flow_table(dev, handler->prio, true);
2975         if (handler->ibcounters &&
2976             atomic_read(&handler->ibcounters->usecnt) == 1)
2977                 counters_clear_description(handler->ibcounters);
2978
2979         mutex_unlock(&dev->flow_db->lock);
2980         if (handler->flow_matcher)
2981                 atomic_dec(&handler->flow_matcher->usecnt);
2982         kfree(handler);
2983
2984         return 0;
2985 }
2986
2987 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2988 {
2989         priority *= 2;
2990         if (!dont_trap)
2991                 priority++;
2992         return priority;
2993 }
2994
2995 enum flow_table_type {
2996         MLX5_IB_FT_RX,
2997         MLX5_IB_FT_TX
2998 };
2999
3000 #define MLX5_FS_MAX_TYPES        6
3001 #define MLX5_FS_MAX_ENTRIES      BIT(16)
3002
3003 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3004                                            struct mlx5_ib_flow_prio *prio,
3005                                            int priority,
3006                                            int num_entries, int num_groups,
3007                                            u32 flags)
3008 {
3009         struct mlx5_flow_table *ft;
3010
3011         ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3012                                                  num_entries,
3013                                                  num_groups,
3014                                                  0, flags);
3015         if (IS_ERR(ft))
3016                 return ERR_CAST(ft);
3017
3018         prio->flow_table = ft;
3019         prio->refcount = 0;
3020         return prio;
3021 }
3022
3023 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3024                                                 struct ib_flow_attr *flow_attr,
3025                                                 enum flow_table_type ft_type)
3026 {
3027         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3028         struct mlx5_flow_namespace *ns = NULL;
3029         struct mlx5_ib_flow_prio *prio;
3030         struct mlx5_flow_table *ft;
3031         int max_table_size;
3032         int num_entries;
3033         int num_groups;
3034         u32 flags = 0;
3035         int priority;
3036
3037         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3038                                                        log_max_ft_size));
3039         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3040                 enum mlx5_flow_namespace_type fn_type;
3041
3042                 if (flow_is_multicast_only(flow_attr) &&
3043                     !dont_trap)
3044                         priority = MLX5_IB_FLOW_MCAST_PRIO;
3045                 else
3046                         priority = ib_prio_to_core_prio(flow_attr->priority,
3047                                                         dont_trap);
3048                 if (ft_type == MLX5_IB_FT_RX) {
3049                         fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3050                         prio = &dev->flow_db->prios[priority];
3051                         if (!dev->rep &&
3052                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3053                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3054                         if (!dev->rep &&
3055                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3056                                         reformat_l3_tunnel_to_l2))
3057                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3058                 } else {
3059                         max_table_size =
3060                                 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3061                                                               log_max_ft_size));
3062                         fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3063                         prio = &dev->flow_db->egress_prios[priority];
3064                         if (!dev->rep &&
3065                             MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3066                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3067                 }
3068                 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
3069                 num_entries = MLX5_FS_MAX_ENTRIES;
3070                 num_groups = MLX5_FS_MAX_TYPES;
3071         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3072                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3073                 ns = mlx5_get_flow_namespace(dev->mdev,
3074                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
3075                 build_leftovers_ft_param(&priority,
3076                                          &num_entries,
3077                                          &num_groups);
3078                 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3079         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3080                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3081                                         allow_sniffer_and_nic_rx_shared_tir))
3082                         return ERR_PTR(-ENOTSUPP);
3083
3084                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3085                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3086                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3087
3088                 prio = &dev->flow_db->sniffer[ft_type];
3089                 priority = 0;
3090                 num_entries = 1;
3091                 num_groups = 1;
3092         }
3093
3094         if (!ns)
3095                 return ERR_PTR(-ENOTSUPP);
3096
3097         if (num_entries > max_table_size)
3098                 return ERR_PTR(-ENOMEM);
3099
3100         ft = prio->flow_table;
3101         if (!ft)
3102                 return _get_prio(ns, prio, priority, num_entries, num_groups,
3103                                  flags);
3104
3105         return prio;
3106 }
3107
3108 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3109                             struct mlx5_flow_spec *spec,
3110                             u32 underlay_qpn)
3111 {
3112         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3113                                            spec->match_criteria,
3114                                            misc_parameters);
3115         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3116                                            misc_parameters);
3117
3118         if (underlay_qpn &&
3119             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3120                                       ft_field_support.bth_dst_qp)) {
3121                 MLX5_SET(fte_match_set_misc,
3122                          misc_params_v, bth_dst_qp, underlay_qpn);
3123                 MLX5_SET(fte_match_set_misc,
3124                          misc_params_c, bth_dst_qp, 0xffffff);
3125         }
3126 }
3127
3128 static int read_flow_counters(struct ib_device *ibdev,
3129                               struct mlx5_read_counters_attr *read_attr)
3130 {
3131         struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3132         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3133
3134         return mlx5_fc_query(dev->mdev, fc,
3135                              &read_attr->out[IB_COUNTER_PACKETS],
3136                              &read_attr->out[IB_COUNTER_BYTES]);
3137 }
3138
3139 /* flow counters currently expose two counters packets and bytes */
3140 #define FLOW_COUNTERS_NUM 2
3141 static int counters_set_description(struct ib_counters *counters,
3142                                     enum mlx5_ib_counters_type counters_type,
3143                                     struct mlx5_ib_flow_counters_desc *desc_data,
3144                                     u32 ncounters)
3145 {
3146         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3147         u32 cntrs_max_index = 0;
3148         int i;
3149
3150         if (counters_type != MLX5_IB_COUNTERS_FLOW)
3151                 return -EINVAL;
3152
3153         /* init the fields for the object */
3154         mcounters->type = counters_type;
3155         mcounters->read_counters = read_flow_counters;
3156         mcounters->counters_num = FLOW_COUNTERS_NUM;
3157         mcounters->ncounters = ncounters;
3158         /* each counter entry have both description and index pair */
3159         for (i = 0; i < ncounters; i++) {
3160                 if (desc_data[i].description > IB_COUNTER_BYTES)
3161                         return -EINVAL;
3162
3163                 if (cntrs_max_index <= desc_data[i].index)
3164                         cntrs_max_index = desc_data[i].index + 1;
3165         }
3166
3167         mutex_lock(&mcounters->mcntrs_mutex);
3168         mcounters->counters_data = desc_data;
3169         mcounters->cntrs_max_index = cntrs_max_index;
3170         mutex_unlock(&mcounters->mcntrs_mutex);
3171
3172         return 0;
3173 }
3174
3175 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3176 static int flow_counters_set_data(struct ib_counters *ibcounters,
3177                                   struct mlx5_ib_create_flow *ucmd)
3178 {
3179         struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3180         struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3181         struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3182         bool hw_hndl = false;
3183         int ret = 0;
3184
3185         if (ucmd && ucmd->ncounters_data != 0) {
3186                 cntrs_data = ucmd->data;
3187                 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3188                         return -EINVAL;
3189
3190                 desc_data = kcalloc(cntrs_data->ncounters,
3191                                     sizeof(*desc_data),
3192                                     GFP_KERNEL);
3193                 if (!desc_data)
3194                         return  -ENOMEM;
3195
3196                 if (copy_from_user(desc_data,
3197                                    u64_to_user_ptr(cntrs_data->counters_data),
3198                                    sizeof(*desc_data) * cntrs_data->ncounters)) {
3199                         ret = -EFAULT;
3200                         goto free;
3201                 }
3202         }
3203
3204         if (!mcounters->hw_cntrs_hndl) {
3205                 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3206                         to_mdev(ibcounters->device)->mdev, false);
3207                 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3208                         ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3209                         goto free;
3210                 }
3211                 hw_hndl = true;
3212         }
3213
3214         if (desc_data) {
3215                 /* counters already bound to at least one flow */
3216                 if (mcounters->cntrs_max_index) {
3217                         ret = -EINVAL;
3218                         goto free_hndl;
3219                 }
3220
3221                 ret = counters_set_description(ibcounters,
3222                                                MLX5_IB_COUNTERS_FLOW,
3223                                                desc_data,
3224                                                cntrs_data->ncounters);
3225                 if (ret)
3226                         goto free_hndl;
3227
3228         } else if (!mcounters->cntrs_max_index) {
3229                 /* counters not bound yet, must have udata passed */
3230                 ret = -EINVAL;
3231                 goto free_hndl;
3232         }
3233
3234         return 0;
3235
3236 free_hndl:
3237         if (hw_hndl) {
3238                 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3239                                 mcounters->hw_cntrs_hndl);
3240                 mcounters->hw_cntrs_hndl = NULL;
3241         }
3242 free:
3243         kfree(desc_data);
3244         return ret;
3245 }
3246
3247 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3248                                                       struct mlx5_ib_flow_prio *ft_prio,
3249                                                       const struct ib_flow_attr *flow_attr,
3250                                                       struct mlx5_flow_destination *dst,
3251                                                       u32 underlay_qpn,
3252                                                       struct mlx5_ib_create_flow *ucmd)
3253 {
3254         struct mlx5_flow_table  *ft = ft_prio->flow_table;
3255         struct mlx5_ib_flow_handler *handler;
3256         struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3257         struct mlx5_flow_spec *spec;
3258         struct mlx5_flow_destination dest_arr[2] = {};
3259         struct mlx5_flow_destination *rule_dst = dest_arr;
3260         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3261         unsigned int spec_index;
3262         u32 prev_type = 0;
3263         int err = 0;
3264         int dest_num = 0;
3265         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3266
3267         if (!is_valid_attr(dev->mdev, flow_attr))
3268                 return ERR_PTR(-EINVAL);
3269
3270         if (dev->rep && is_egress)
3271                 return ERR_PTR(-EINVAL);
3272
3273         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3274         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3275         if (!handler || !spec) {
3276                 err = -ENOMEM;
3277                 goto free;
3278         }
3279
3280         INIT_LIST_HEAD(&handler->list);
3281         if (dst) {
3282                 memcpy(&dest_arr[0], dst, sizeof(*dst));
3283                 dest_num++;
3284         }
3285
3286         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3287                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3288                                       spec->match_value,
3289                                       ib_flow, flow_attr, &flow_act,
3290                                       prev_type);
3291                 if (err < 0)
3292                         goto free;
3293
3294                 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3295                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3296         }
3297
3298         if (!flow_is_multicast_only(flow_attr))
3299                 set_underlay_qp(dev, spec, underlay_qpn);
3300
3301         if (dev->rep) {
3302                 void *misc;
3303
3304                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3305                                     misc_parameters);
3306                 MLX5_SET(fte_match_set_misc, misc, source_port,
3307                          dev->rep->vport);
3308                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3309                                     misc_parameters);
3310                 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3311         }
3312
3313         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3314
3315         if (is_egress &&
3316             !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3317                 err = -EINVAL;
3318                 goto free;
3319         }
3320
3321         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3322                 struct mlx5_ib_mcounters *mcounters;
3323
3324                 err = flow_counters_set_data(flow_act.counters, ucmd);
3325                 if (err)
3326                         goto free;
3327
3328                 mcounters = to_mcounters(flow_act.counters);
3329                 handler->ibcounters = flow_act.counters;
3330                 dest_arr[dest_num].type =
3331                         MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3332                 dest_arr[dest_num].counter_id =
3333                         mlx5_fc_id(mcounters->hw_cntrs_hndl);
3334                 dest_num++;
3335         }
3336
3337         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3338                 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3339                         rule_dst = NULL;
3340                         dest_num = 0;
3341                 }
3342         } else {
3343                 if (is_egress)
3344                         flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3345                 else
3346                         flow_act.action |=
3347                                 dest_num ?  MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3348                                         MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3349         }
3350
3351         if ((flow_act.flags & FLOW_ACT_HAS_TAG)  &&
3352             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3353              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3354                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3355                              flow_act.flow_tag, flow_attr->type);
3356                 err = -EINVAL;
3357                 goto free;
3358         }
3359         handler->rule = mlx5_add_flow_rules(ft, spec,
3360                                             &flow_act,
3361                                             rule_dst, dest_num);
3362
3363         if (IS_ERR(handler->rule)) {
3364                 err = PTR_ERR(handler->rule);
3365                 goto free;
3366         }
3367
3368         ft_prio->refcount++;
3369         handler->prio = ft_prio;
3370         handler->dev = dev;
3371
3372         ft_prio->flow_table = ft;
3373 free:
3374         if (err && handler) {
3375                 if (handler->ibcounters &&
3376                     atomic_read(&handler->ibcounters->usecnt) == 1)
3377                         counters_clear_description(handler->ibcounters);
3378                 kfree(handler);
3379         }
3380         kvfree(spec);
3381         return err ? ERR_PTR(err) : handler;
3382 }
3383
3384 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3385                                                      struct mlx5_ib_flow_prio *ft_prio,
3386                                                      const struct ib_flow_attr *flow_attr,
3387                                                      struct mlx5_flow_destination *dst)
3388 {
3389         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3390 }
3391
3392 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3393                                                           struct mlx5_ib_flow_prio *ft_prio,
3394                                                           struct ib_flow_attr *flow_attr,
3395                                                           struct mlx5_flow_destination *dst)
3396 {
3397         struct mlx5_ib_flow_handler *handler_dst = NULL;
3398         struct mlx5_ib_flow_handler *handler = NULL;
3399
3400         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3401         if (!IS_ERR(handler)) {
3402                 handler_dst = create_flow_rule(dev, ft_prio,
3403                                                flow_attr, dst);
3404                 if (IS_ERR(handler_dst)) {
3405                         mlx5_del_flow_rules(handler->rule);
3406                         ft_prio->refcount--;
3407                         kfree(handler);
3408                         handler = handler_dst;
3409                 } else {
3410                         list_add(&handler_dst->list, &handler->list);
3411                 }
3412         }
3413
3414         return handler;
3415 }
3416 enum {
3417         LEFTOVERS_MC,
3418         LEFTOVERS_UC,
3419 };
3420
3421 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3422                                                           struct mlx5_ib_flow_prio *ft_prio,
3423                                                           struct ib_flow_attr *flow_attr,
3424                                                           struct mlx5_flow_destination *dst)
3425 {
3426         struct mlx5_ib_flow_handler *handler_ucast = NULL;
3427         struct mlx5_ib_flow_handler *handler = NULL;
3428
3429         static struct {
3430                 struct ib_flow_attr     flow_attr;
3431                 struct ib_flow_spec_eth eth_flow;
3432         } leftovers_specs[] = {
3433                 [LEFTOVERS_MC] = {
3434                         .flow_attr = {
3435                                 .num_of_specs = 1,
3436                                 .size = sizeof(leftovers_specs[0])
3437                         },
3438                         .eth_flow = {
3439                                 .type = IB_FLOW_SPEC_ETH,
3440                                 .size = sizeof(struct ib_flow_spec_eth),
3441                                 .mask = {.dst_mac = {0x1} },
3442                                 .val =  {.dst_mac = {0x1} }
3443                         }
3444                 },
3445                 [LEFTOVERS_UC] = {
3446                         .flow_attr = {
3447                                 .num_of_specs = 1,
3448                                 .size = sizeof(leftovers_specs[0])
3449                         },
3450                         .eth_flow = {
3451                                 .type = IB_FLOW_SPEC_ETH,
3452                                 .size = sizeof(struct ib_flow_spec_eth),
3453                                 .mask = {.dst_mac = {0x1} },
3454                                 .val = {.dst_mac = {} }
3455                         }
3456                 }
3457         };
3458
3459         handler = create_flow_rule(dev, ft_prio,
3460                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
3461                                    dst);
3462         if (!IS_ERR(handler) &&
3463             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3464                 handler_ucast = create_flow_rule(dev, ft_prio,
3465                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
3466                                                  dst);
3467                 if (IS_ERR(handler_ucast)) {
3468                         mlx5_del_flow_rules(handler->rule);
3469                         ft_prio->refcount--;
3470                         kfree(handler);
3471                         handler = handler_ucast;
3472                 } else {
3473                         list_add(&handler_ucast->list, &handler->list);
3474                 }
3475         }
3476
3477         return handler;
3478 }
3479
3480 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3481                                                         struct mlx5_ib_flow_prio *ft_rx,
3482                                                         struct mlx5_ib_flow_prio *ft_tx,
3483                                                         struct mlx5_flow_destination *dst)
3484 {
3485         struct mlx5_ib_flow_handler *handler_rx;
3486         struct mlx5_ib_flow_handler *handler_tx;
3487         int err;
3488         static const struct ib_flow_attr flow_attr  = {
3489                 .num_of_specs = 0,
3490                 .size = sizeof(flow_attr)
3491         };
3492
3493         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3494         if (IS_ERR(handler_rx)) {
3495                 err = PTR_ERR(handler_rx);
3496                 goto err;
3497         }
3498
3499         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3500         if (IS_ERR(handler_tx)) {
3501                 err = PTR_ERR(handler_tx);
3502                 goto err_tx;
3503         }
3504
3505         list_add(&handler_tx->list, &handler_rx->list);
3506
3507         return handler_rx;
3508
3509 err_tx:
3510         mlx5_del_flow_rules(handler_rx->rule);
3511         ft_rx->refcount--;
3512         kfree(handler_rx);
3513 err:
3514         return ERR_PTR(err);
3515 }
3516
3517 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3518                                            struct ib_flow_attr *flow_attr,
3519                                            int domain,
3520                                            struct ib_udata *udata)
3521 {
3522         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3523         struct mlx5_ib_qp *mqp = to_mqp(qp);
3524         struct mlx5_ib_flow_handler *handler = NULL;
3525         struct mlx5_flow_destination *dst = NULL;
3526         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3527         struct mlx5_ib_flow_prio *ft_prio;
3528         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3529         struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3530         size_t min_ucmd_sz, required_ucmd_sz;
3531         int err;
3532         int underlay_qpn;
3533
3534         if (udata && udata->inlen) {
3535                 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3536                                 sizeof(ucmd_hdr.reserved);
3537                 if (udata->inlen < min_ucmd_sz)
3538                         return ERR_PTR(-EOPNOTSUPP);
3539
3540                 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3541                 if (err)
3542                         return ERR_PTR(err);
3543
3544                 /* currently supports only one counters data */
3545                 if (ucmd_hdr.ncounters_data > 1)
3546                         return ERR_PTR(-EINVAL);
3547
3548                 required_ucmd_sz = min_ucmd_sz +
3549                         sizeof(struct mlx5_ib_flow_counters_data) *
3550                         ucmd_hdr.ncounters_data;
3551                 if (udata->inlen > required_ucmd_sz &&
3552                     !ib_is_udata_cleared(udata, required_ucmd_sz,
3553                                          udata->inlen - required_ucmd_sz))
3554                         return ERR_PTR(-EOPNOTSUPP);
3555
3556                 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3557                 if (!ucmd)
3558                         return ERR_PTR(-ENOMEM);
3559
3560                 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3561                 if (err)
3562                         goto free_ucmd;
3563         }
3564
3565         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3566                 err = -ENOMEM;
3567                 goto free_ucmd;
3568         }
3569
3570         if (domain != IB_FLOW_DOMAIN_USER ||
3571             flow_attr->port > dev->num_ports ||
3572             (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3573                                   IB_FLOW_ATTR_FLAGS_EGRESS))) {
3574                 err = -EINVAL;
3575                 goto free_ucmd;
3576         }
3577
3578         if (is_egress &&
3579             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3580              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3581                 err = -EINVAL;
3582                 goto free_ucmd;
3583         }
3584
3585         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3586         if (!dst) {
3587                 err = -ENOMEM;
3588                 goto free_ucmd;
3589         }
3590
3591         mutex_lock(&dev->flow_db->lock);
3592
3593         ft_prio = get_flow_table(dev, flow_attr,
3594                                  is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3595         if (IS_ERR(ft_prio)) {
3596                 err = PTR_ERR(ft_prio);
3597                 goto unlock;
3598         }
3599         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3600                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3601                 if (IS_ERR(ft_prio_tx)) {
3602                         err = PTR_ERR(ft_prio_tx);
3603                         ft_prio_tx = NULL;
3604                         goto destroy_ft;
3605                 }
3606         }
3607
3608         if (is_egress) {
3609                 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3610         } else {
3611                 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3612                 if (mqp->flags & MLX5_IB_QP_RSS)
3613                         dst->tir_num = mqp->rss_qp.tirn;
3614                 else
3615                         dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3616         }
3617
3618         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3619                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3620                         handler = create_dont_trap_rule(dev, ft_prio,
3621                                                         flow_attr, dst);
3622                 } else {
3623                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3624                                         mqp->underlay_qpn : 0;
3625                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3626                                                     dst, underlay_qpn, ucmd);
3627                 }
3628         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3629                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3630                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3631                                                 dst);
3632         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3633                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3634         } else {
3635                 err = -EINVAL;
3636                 goto destroy_ft;
3637         }
3638
3639         if (IS_ERR(handler)) {
3640                 err = PTR_ERR(handler);
3641                 handler = NULL;
3642                 goto destroy_ft;
3643         }
3644
3645         mutex_unlock(&dev->flow_db->lock);
3646         kfree(dst);
3647         kfree(ucmd);
3648
3649         return &handler->ibflow;
3650
3651 destroy_ft:
3652         put_flow_table(dev, ft_prio, false);
3653         if (ft_prio_tx)
3654                 put_flow_table(dev, ft_prio_tx, false);
3655 unlock:
3656         mutex_unlock(&dev->flow_db->lock);
3657         kfree(dst);
3658 free_ucmd:
3659         kfree(ucmd);
3660         return ERR_PTR(err);
3661 }
3662
3663 static struct mlx5_ib_flow_prio *
3664 _get_flow_table(struct mlx5_ib_dev *dev,
3665                 struct mlx5_ib_flow_matcher *fs_matcher,
3666                 bool mcast)
3667 {
3668         struct mlx5_flow_namespace *ns = NULL;
3669         struct mlx5_ib_flow_prio *prio;
3670         int max_table_size;
3671         u32 flags = 0;
3672         int priority;
3673
3674         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3675                 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3676                                         log_max_ft_size));
3677                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3678                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3679                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3680                                               reformat_l3_tunnel_to_l2))
3681                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3682         } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */
3683                 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3684                                         log_max_ft_size));
3685                 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3686                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3687         }
3688
3689         if (max_table_size < MLX5_FS_MAX_ENTRIES)
3690                 return ERR_PTR(-ENOMEM);
3691
3692         if (mcast)
3693                 priority = MLX5_IB_FLOW_MCAST_PRIO;
3694         else
3695                 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3696
3697         ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
3698         if (!ns)
3699                 return ERR_PTR(-ENOTSUPP);
3700
3701         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3702                 prio = &dev->flow_db->prios[priority];
3703         else
3704                 prio = &dev->flow_db->egress_prios[priority];
3705
3706         if (prio->flow_table)
3707                 return prio;
3708
3709         return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
3710                          MLX5_FS_MAX_TYPES, flags);
3711 }
3712
3713 static struct mlx5_ib_flow_handler *
3714 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
3715                       struct mlx5_ib_flow_prio *ft_prio,
3716                       struct mlx5_flow_destination *dst,
3717                       struct mlx5_ib_flow_matcher  *fs_matcher,
3718                       struct mlx5_flow_act *flow_act,
3719                       void *cmd_in, int inlen)
3720 {
3721         struct mlx5_ib_flow_handler *handler;
3722         struct mlx5_flow_spec *spec;
3723         struct mlx5_flow_table *ft = ft_prio->flow_table;
3724         int err = 0;
3725
3726         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3727         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3728         if (!handler || !spec) {
3729                 err = -ENOMEM;
3730                 goto free;
3731         }
3732
3733         INIT_LIST_HEAD(&handler->list);
3734
3735         memcpy(spec->match_value, cmd_in, inlen);
3736         memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3737                fs_matcher->mask_len);
3738         spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3739
3740         handler->rule = mlx5_add_flow_rules(ft, spec,
3741                                             flow_act, dst, 1);
3742
3743         if (IS_ERR(handler->rule)) {
3744                 err = PTR_ERR(handler->rule);
3745                 goto free;
3746         }
3747
3748         ft_prio->refcount++;
3749         handler->prio = ft_prio;
3750         handler->dev = dev;
3751         ft_prio->flow_table = ft;
3752
3753 free:
3754         if (err)
3755                 kfree(handler);
3756         kvfree(spec);
3757         return err ? ERR_PTR(err) : handler;
3758 }
3759
3760 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3761                                 void *match_v)
3762 {
3763         void *match_c;
3764         void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3765         void *dmac, *dmac_mask;
3766         void *ipv4, *ipv4_mask;
3767
3768         if (!(fs_matcher->match_criteria_enable &
3769               (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3770                 return false;
3771
3772         match_c = fs_matcher->matcher_mask.match_params;
3773         match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3774                                            outer_headers);
3775         match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3776                                            outer_headers);
3777
3778         dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3779                             dmac_47_16);
3780         dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3781                                  dmac_47_16);
3782
3783         if (is_multicast_ether_addr(dmac) &&
3784             is_multicast_ether_addr(dmac_mask))
3785                 return true;
3786
3787         ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3788                             dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3789
3790         ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3791                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3792
3793         if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3794             ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3795                 return true;
3796
3797         return false;
3798 }
3799
3800 struct mlx5_ib_flow_handler *
3801 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3802                         struct mlx5_ib_flow_matcher *fs_matcher,
3803                         struct mlx5_flow_act *flow_act,
3804                         void *cmd_in, int inlen, int dest_id,
3805                         int dest_type)
3806 {
3807         struct mlx5_flow_destination *dst;
3808         struct mlx5_ib_flow_prio *ft_prio;
3809         struct mlx5_ib_flow_handler *handler;
3810         bool mcast;
3811         int err;
3812
3813         if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3814                 return ERR_PTR(-EOPNOTSUPP);
3815
3816         if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3817                 return ERR_PTR(-ENOMEM);
3818
3819         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3820         if (!dst)
3821                 return ERR_PTR(-ENOMEM);
3822
3823         mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3824         mutex_lock(&dev->flow_db->lock);
3825
3826         ft_prio = _get_flow_table(dev, fs_matcher, mcast);
3827         if (IS_ERR(ft_prio)) {
3828                 err = PTR_ERR(ft_prio);
3829                 goto unlock;
3830         }
3831
3832         if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
3833                 dst->type = dest_type;
3834                 dst->tir_num = dest_id;
3835                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3836         } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
3837                 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3838                 dst->ft_num = dest_id;
3839                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3840         } else {
3841                 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3842                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3843         }
3844
3845         handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act,
3846                                         cmd_in, inlen);
3847
3848         if (IS_ERR(handler)) {
3849                 err = PTR_ERR(handler);
3850                 goto destroy_ft;
3851         }
3852
3853         mutex_unlock(&dev->flow_db->lock);
3854         atomic_inc(&fs_matcher->usecnt);
3855         handler->flow_matcher = fs_matcher;
3856
3857         kfree(dst);
3858
3859         return handler;
3860
3861 destroy_ft:
3862         put_flow_table(dev, ft_prio, false);
3863 unlock:
3864         mutex_unlock(&dev->flow_db->lock);
3865         kfree(dst);
3866
3867         return ERR_PTR(err);
3868 }
3869
3870 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3871 {
3872         u32 flags = 0;
3873
3874         if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3875                 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3876
3877         return flags;
3878 }
3879
3880 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED      MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3881 static struct ib_flow_action *
3882 mlx5_ib_create_flow_action_esp(struct ib_device *device,
3883                                const struct ib_flow_action_attrs_esp *attr,
3884                                struct uverbs_attr_bundle *attrs)
3885 {
3886         struct mlx5_ib_dev *mdev = to_mdev(device);
3887         struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3888         struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3889         struct mlx5_ib_flow_action *action;
3890         u64 action_flags;
3891         u64 flags;
3892         int err = 0;
3893
3894         err = uverbs_get_flags64(
3895                 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3896                 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3897         if (err)
3898                 return ERR_PTR(err);
3899
3900         flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3901
3902         /* We current only support a subset of the standard features. Only a
3903          * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3904          * (with overlap). Full offload mode isn't supported.
3905          */
3906         if (!attr->keymat || attr->replay || attr->encap ||
3907             attr->spi || attr->seq || attr->tfc_pad ||
3908             attr->hard_limit_pkts ||
3909             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3910                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3911                 return ERR_PTR(-EOPNOTSUPP);
3912
3913         if (attr->keymat->protocol !=
3914             IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3915                 return ERR_PTR(-EOPNOTSUPP);
3916
3917         aes_gcm = &attr->keymat->keymat.aes_gcm;
3918
3919         if (aes_gcm->icv_len != 16 ||
3920             aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3921                 return ERR_PTR(-EOPNOTSUPP);
3922
3923         action = kmalloc(sizeof(*action), GFP_KERNEL);
3924         if (!action)
3925                 return ERR_PTR(-ENOMEM);
3926
3927         action->esp_aes_gcm.ib_flags = attr->flags;
3928         memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3929                sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3930         accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3931         memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3932                sizeof(accel_attrs.keymat.aes_gcm.salt));
3933         memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3934                sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3935         accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3936         accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3937         accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3938
3939         accel_attrs.esn = attr->esn;
3940         if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3941                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3942         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3943                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3944
3945         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3946                 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3947
3948         action->esp_aes_gcm.ctx =
3949                 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3950         if (IS_ERR(action->esp_aes_gcm.ctx)) {
3951                 err = PTR_ERR(action->esp_aes_gcm.ctx);
3952                 goto err_parse;
3953         }
3954
3955         action->esp_aes_gcm.ib_flags = attr->flags;
3956
3957         return &action->ib_action;
3958
3959 err_parse:
3960         kfree(action);
3961         return ERR_PTR(err);
3962 }
3963
3964 static int
3965 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3966                                const struct ib_flow_action_attrs_esp *attr,
3967                                struct uverbs_attr_bundle *attrs)
3968 {
3969         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3970         struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3971         int err = 0;
3972
3973         if (attr->keymat || attr->replay || attr->encap ||
3974             attr->spi || attr->seq || attr->tfc_pad ||
3975             attr->hard_limit_pkts ||
3976             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3977                              IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3978                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3979                 return -EOPNOTSUPP;
3980
3981         /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3982          * be modified.
3983          */
3984         if (!(maction->esp_aes_gcm.ib_flags &
3985               IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3986             attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3987                            IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3988                 return -EINVAL;
3989
3990         memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3991                sizeof(accel_attrs));
3992
3993         accel_attrs.esn = attr->esn;
3994         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3995                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3996         else
3997                 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3998
3999         err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4000                                          &accel_attrs);
4001         if (err)
4002                 return err;
4003
4004         maction->esp_aes_gcm.ib_flags &=
4005                 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4006         maction->esp_aes_gcm.ib_flags |=
4007                 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4008
4009         return 0;
4010 }
4011
4012 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4013 {
4014         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4015
4016         switch (action->type) {
4017         case IB_FLOW_ACTION_ESP:
4018                 /*
4019                  * We only support aes_gcm by now, so we implicitly know this is
4020                  * the underline crypto.
4021                  */
4022                 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4023                 break;
4024         case IB_FLOW_ACTION_UNSPECIFIED:
4025                 mlx5_ib_destroy_flow_action_raw(maction);
4026                 break;
4027         default:
4028                 WARN_ON(true);
4029                 break;
4030         }
4031
4032         kfree(maction);
4033         return 0;
4034 }
4035
4036 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4037 {
4038         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4039         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4040         int err;
4041         u16 uid;
4042
4043         uid = ibqp->pd ?
4044                 to_mpd(ibqp->pd)->uid : 0;
4045
4046         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4047                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4048                 return -EOPNOTSUPP;
4049         }
4050
4051         err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4052         if (err)
4053                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4054                              ibqp->qp_num, gid->raw);
4055
4056         return err;
4057 }
4058
4059 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4060 {
4061         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4062         int err;
4063         u16 uid;
4064
4065         uid = ibqp->pd ?
4066                 to_mpd(ibqp->pd)->uid : 0;
4067         err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4068         if (err)
4069                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4070                              ibqp->qp_num, gid->raw);
4071
4072         return err;
4073 }
4074
4075 static int init_node_data(struct mlx5_ib_dev *dev)
4076 {
4077         int err;
4078
4079         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4080         if (err)
4081                 return err;
4082
4083         dev->mdev->rev_id = dev->mdev->pdev->revision;
4084
4085         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4086 }
4087
4088 static ssize_t fw_pages_show(struct device *device,
4089                              struct device_attribute *attr, char *buf)
4090 {
4091         struct mlx5_ib_dev *dev =
4092                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4093
4094         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4095 }
4096 static DEVICE_ATTR_RO(fw_pages);
4097
4098 static ssize_t reg_pages_show(struct device *device,
4099                               struct device_attribute *attr, char *buf)
4100 {
4101         struct mlx5_ib_dev *dev =
4102                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4103
4104         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4105 }
4106 static DEVICE_ATTR_RO(reg_pages);
4107
4108 static ssize_t hca_type_show(struct device *device,
4109                              struct device_attribute *attr, char *buf)
4110 {
4111         struct mlx5_ib_dev *dev =
4112                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4113         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4114 }
4115 static DEVICE_ATTR_RO(hca_type);
4116
4117 static ssize_t hw_rev_show(struct device *device,
4118                            struct device_attribute *attr, char *buf)
4119 {
4120         struct mlx5_ib_dev *dev =
4121                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4122         return sprintf(buf, "%x\n", dev->mdev->rev_id);
4123 }
4124 static DEVICE_ATTR_RO(hw_rev);
4125
4126 static ssize_t board_id_show(struct device *device,
4127                              struct device_attribute *attr, char *buf)
4128 {
4129         struct mlx5_ib_dev *dev =
4130                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4131         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4132                        dev->mdev->board_id);
4133 }
4134 static DEVICE_ATTR_RO(board_id);
4135
4136 static struct attribute *mlx5_class_attributes[] = {
4137         &dev_attr_hw_rev.attr,
4138         &dev_attr_hca_type.attr,
4139         &dev_attr_board_id.attr,
4140         &dev_attr_fw_pages.attr,
4141         &dev_attr_reg_pages.attr,
4142         NULL,
4143 };
4144
4145 static const struct attribute_group mlx5_attr_group = {
4146         .attrs = mlx5_class_attributes,
4147 };
4148
4149 static void pkey_change_handler(struct work_struct *work)
4150 {
4151         struct mlx5_ib_port_resources *ports =
4152                 container_of(work, struct mlx5_ib_port_resources,
4153                              pkey_change_work);
4154
4155         mutex_lock(&ports->devr->mutex);
4156         mlx5_ib_gsi_pkey_change(ports->gsi);
4157         mutex_unlock(&ports->devr->mutex);
4158 }
4159
4160 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4161 {
4162         struct mlx5_ib_qp *mqp;
4163         struct mlx5_ib_cq *send_mcq, *recv_mcq;
4164         struct mlx5_core_cq *mcq;
4165         struct list_head cq_armed_list;
4166         unsigned long flags_qp;
4167         unsigned long flags_cq;
4168         unsigned long flags;
4169
4170         INIT_LIST_HEAD(&cq_armed_list);
4171
4172         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4173         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4174         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4175                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4176                 if (mqp->sq.tail != mqp->sq.head) {
4177                         send_mcq = to_mcq(mqp->ibqp.send_cq);
4178                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
4179                         if (send_mcq->mcq.comp &&
4180                             mqp->ibqp.send_cq->comp_handler) {
4181                                 if (!send_mcq->mcq.reset_notify_added) {
4182                                         send_mcq->mcq.reset_notify_added = 1;
4183                                         list_add_tail(&send_mcq->mcq.reset_notify,
4184                                                       &cq_armed_list);
4185                                 }
4186                         }
4187                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4188                 }
4189                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4190                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4191                 /* no handling is needed for SRQ */
4192                 if (!mqp->ibqp.srq) {
4193                         if (mqp->rq.tail != mqp->rq.head) {
4194                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4195                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4196                                 if (recv_mcq->mcq.comp &&
4197                                     mqp->ibqp.recv_cq->comp_handler) {
4198                                         if (!recv_mcq->mcq.reset_notify_added) {
4199                                                 recv_mcq->mcq.reset_notify_added = 1;
4200                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
4201                                                               &cq_armed_list);
4202                                         }
4203                                 }
4204                                 spin_unlock_irqrestore(&recv_mcq->lock,
4205                                                        flags_cq);
4206                         }
4207                 }
4208                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4209         }
4210         /*At that point all inflight post send were put to be executed as of we
4211          * lock/unlock above locks Now need to arm all involved CQs.
4212          */
4213         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4214                 mcq->comp(mcq);
4215         }
4216         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4217 }
4218
4219 static void delay_drop_handler(struct work_struct *work)
4220 {
4221         int err;
4222         struct mlx5_ib_delay_drop *delay_drop =
4223                 container_of(work, struct mlx5_ib_delay_drop,
4224                              delay_drop_work);
4225
4226         atomic_inc(&delay_drop->events_cnt);
4227
4228         mutex_lock(&delay_drop->lock);
4229         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4230                                        delay_drop->timeout);
4231         if (err) {
4232                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4233                              delay_drop->timeout);
4234                 delay_drop->activate = false;
4235         }
4236         mutex_unlock(&delay_drop->lock);
4237 }
4238
4239 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4240                               struct ib_event *ibev)
4241 {
4242         u8 port = (eqe->data.port.port >> 4) & 0xf;
4243
4244         ibev->element.port_num = port;
4245
4246         switch (eqe->sub_type) {
4247         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4248         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4249         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4250                 /* In RoCE, port up/down events are handled in
4251                  * mlx5_netdev_event().
4252                  */
4253                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4254                                             IB_LINK_LAYER_ETHERNET)
4255                         return -EINVAL;
4256
4257                 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4258                                 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4259                 break;
4260
4261         case MLX5_PORT_CHANGE_SUBTYPE_LID:
4262                 ibev->event = IB_EVENT_LID_CHANGE;
4263                 break;
4264
4265         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4266                 ibev->event = IB_EVENT_PKEY_CHANGE;
4267                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4268                 break;
4269
4270         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4271                 ibev->event = IB_EVENT_GID_CHANGE;
4272                 break;
4273
4274         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4275                 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4276                 break;
4277         default:
4278                 return -EINVAL;
4279         }
4280
4281         return 0;
4282 }
4283
4284 static void mlx5_ib_handle_event(struct work_struct *_work)
4285 {
4286         struct mlx5_ib_event_work *work =
4287                 container_of(_work, struct mlx5_ib_event_work, work);
4288         struct mlx5_ib_dev *ibdev;
4289         struct ib_event ibev;
4290         bool fatal = false;
4291
4292         if (work->is_slave) {
4293                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
4294                 if (!ibdev)
4295                         goto out;
4296         } else {
4297                 ibdev = work->dev;
4298         }
4299
4300         switch (work->event) {
4301         case MLX5_DEV_EVENT_SYS_ERROR:
4302                 ibev.event = IB_EVENT_DEVICE_FATAL;
4303                 mlx5_ib_handle_internal_error(ibdev);
4304                 ibev.element.port_num  = (u8)(unsigned long)work->param;
4305                 fatal = true;
4306                 break;
4307         case MLX5_EVENT_TYPE_PORT_CHANGE:
4308                 if (handle_port_change(ibdev, work->param, &ibev))
4309                         goto out;
4310                 break;
4311         case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4312                 schedule_work(&ibdev->delay_drop.delay_drop_work);
4313                 goto out;
4314         default:
4315                 goto out;
4316         }
4317
4318         ibev.device = &ibdev->ib_dev;
4319
4320         if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4321                 mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
4322                 goto out;
4323         }
4324
4325         if (ibdev->ib_active)
4326                 ib_dispatch_event(&ibev);
4327
4328         if (fatal)
4329                 ibdev->ib_active = false;
4330 out:
4331         kfree(work);
4332 }
4333
4334 static int mlx5_ib_event(struct notifier_block *nb,
4335                          unsigned long event, void *param)
4336 {
4337         struct mlx5_ib_event_work *work;
4338
4339         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4340         if (!work)
4341                 return NOTIFY_DONE;
4342
4343         INIT_WORK(&work->work, mlx5_ib_handle_event);
4344         work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4345         work->is_slave = false;
4346         work->param = param;
4347         work->event = event;
4348
4349         queue_work(mlx5_ib_event_wq, &work->work);
4350
4351         return NOTIFY_OK;
4352 }
4353
4354 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4355                                     unsigned long event, void *param)
4356 {
4357         struct mlx5_ib_event_work *work;
4358
4359         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4360         if (!work)
4361                 return NOTIFY_DONE;
4362
4363         INIT_WORK(&work->work, mlx5_ib_handle_event);
4364         work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4365         work->is_slave = true;
4366         work->param = param;
4367         work->event = event;
4368         queue_work(mlx5_ib_event_wq, &work->work);
4369
4370         return NOTIFY_OK;
4371 }
4372
4373 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4374 {
4375         struct mlx5_hca_vport_context vport_ctx;
4376         int err;
4377         int port;
4378
4379         for (port = 1; port <= dev->num_ports; port++) {
4380                 dev->mdev->port_caps[port - 1].has_smi = false;
4381                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4382                     MLX5_CAP_PORT_TYPE_IB) {
4383                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4384                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4385                                                                    port, 0,
4386                                                                    &vport_ctx);
4387                                 if (err) {
4388                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4389                                                     port, err);
4390                                         return err;
4391                                 }
4392                                 dev->mdev->port_caps[port - 1].has_smi =
4393                                         vport_ctx.has_smi;
4394                         } else {
4395                                 dev->mdev->port_caps[port - 1].has_smi = true;
4396                         }
4397                 }
4398         }
4399         return 0;
4400 }
4401
4402 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4403 {
4404         int port;
4405
4406         for (port = 1; port <= dev->num_ports; port++)
4407                 mlx5_query_ext_port_caps(dev, port);
4408 }
4409
4410 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4411 {
4412         struct ib_device_attr *dprops = NULL;
4413         struct ib_port_attr *pprops = NULL;
4414         int err = -ENOMEM;
4415         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4416
4417         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4418         if (!pprops)
4419                 goto out;
4420
4421         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4422         if (!dprops)
4423                 goto out;
4424
4425         err = set_has_smi_cap(dev);
4426         if (err)
4427                 goto out;
4428
4429         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4430         if (err) {
4431                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4432                 goto out;
4433         }
4434
4435         memset(pprops, 0, sizeof(*pprops));
4436         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4437         if (err) {
4438                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4439                              port, err);
4440                 goto out;
4441         }
4442
4443         dev->mdev->port_caps[port - 1].pkey_table_len =
4444                                         dprops->max_pkeys;
4445         dev->mdev->port_caps[port - 1].gid_table_len =
4446                                         pprops->gid_tbl_len;
4447         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4448                     port, dprops->max_pkeys, pprops->gid_tbl_len);
4449
4450 out:
4451         kfree(pprops);
4452         kfree(dprops);
4453
4454         return err;
4455 }
4456
4457 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4458 {
4459         int err;
4460
4461         err = mlx5_mr_cache_cleanup(dev);
4462         if (err)
4463                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4464
4465         if (dev->umrc.qp)
4466                 mlx5_ib_destroy_qp(dev->umrc.qp);
4467         if (dev->umrc.cq)
4468                 ib_free_cq(dev->umrc.cq);
4469         if (dev->umrc.pd)
4470                 ib_dealloc_pd(dev->umrc.pd);
4471 }
4472
4473 enum {
4474         MAX_UMR_WR = 128,
4475 };
4476
4477 static int create_umr_res(struct mlx5_ib_dev *dev)
4478 {
4479         struct ib_qp_init_attr *init_attr = NULL;
4480         struct ib_qp_attr *attr = NULL;
4481         struct ib_pd *pd;
4482         struct ib_cq *cq;
4483         struct ib_qp *qp;
4484         int ret;
4485
4486         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4487         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4488         if (!attr || !init_attr) {
4489                 ret = -ENOMEM;
4490                 goto error_0;
4491         }
4492
4493         pd = ib_alloc_pd(&dev->ib_dev, 0);
4494         if (IS_ERR(pd)) {
4495                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4496                 ret = PTR_ERR(pd);
4497                 goto error_0;
4498         }
4499
4500         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4501         if (IS_ERR(cq)) {
4502                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4503                 ret = PTR_ERR(cq);
4504                 goto error_2;
4505         }
4506
4507         init_attr->send_cq = cq;
4508         init_attr->recv_cq = cq;
4509         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4510         init_attr->cap.max_send_wr = MAX_UMR_WR;
4511         init_attr->cap.max_send_sge = 1;
4512         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4513         init_attr->port_num = 1;
4514         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4515         if (IS_ERR(qp)) {
4516                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4517                 ret = PTR_ERR(qp);
4518                 goto error_3;
4519         }
4520         qp->device     = &dev->ib_dev;
4521         qp->real_qp    = qp;
4522         qp->uobject    = NULL;
4523         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4524         qp->send_cq    = init_attr->send_cq;
4525         qp->recv_cq    = init_attr->recv_cq;
4526
4527         attr->qp_state = IB_QPS_INIT;
4528         attr->port_num = 1;
4529         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4530                                 IB_QP_PORT, NULL);
4531         if (ret) {
4532                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4533                 goto error_4;
4534         }
4535
4536         memset(attr, 0, sizeof(*attr));
4537         attr->qp_state = IB_QPS_RTR;
4538         attr->path_mtu = IB_MTU_256;
4539
4540         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4541         if (ret) {
4542                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4543                 goto error_4;
4544         }
4545
4546         memset(attr, 0, sizeof(*attr));
4547         attr->qp_state = IB_QPS_RTS;
4548         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4549         if (ret) {
4550                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4551                 goto error_4;
4552         }
4553
4554         dev->umrc.qp = qp;
4555         dev->umrc.cq = cq;
4556         dev->umrc.pd = pd;
4557
4558         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4559         ret = mlx5_mr_cache_init(dev);
4560         if (ret) {
4561                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4562                 goto error_4;
4563         }
4564
4565         kfree(attr);
4566         kfree(init_attr);
4567
4568         return 0;
4569
4570 error_4:
4571         mlx5_ib_destroy_qp(qp);
4572         dev->umrc.qp = NULL;
4573
4574 error_3:
4575         ib_free_cq(cq);
4576         dev->umrc.cq = NULL;
4577
4578 error_2:
4579         ib_dealloc_pd(pd);
4580         dev->umrc.pd = NULL;
4581
4582 error_0:
4583         kfree(attr);
4584         kfree(init_attr);
4585         return ret;
4586 }
4587
4588 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4589 {
4590         switch (umr_fence_cap) {
4591         case MLX5_CAP_UMR_FENCE_NONE:
4592                 return MLX5_FENCE_MODE_NONE;
4593         case MLX5_CAP_UMR_FENCE_SMALL:
4594                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4595         default:
4596                 return MLX5_FENCE_MODE_STRONG_ORDERING;
4597         }
4598 }
4599
4600 static int create_dev_resources(struct mlx5_ib_resources *devr)
4601 {
4602         struct ib_srq_init_attr attr;
4603         struct mlx5_ib_dev *dev;
4604         struct ib_cq_init_attr cq_attr = {.cqe = 1};
4605         int port;
4606         int ret = 0;
4607
4608         dev = container_of(devr, struct mlx5_ib_dev, devr);
4609
4610         mutex_init(&devr->mutex);
4611
4612         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4613         if (IS_ERR(devr->p0)) {
4614                 ret = PTR_ERR(devr->p0);
4615                 goto error0;
4616         }
4617         devr->p0->device  = &dev->ib_dev;
4618         devr->p0->uobject = NULL;
4619         atomic_set(&devr->p0->usecnt, 0);
4620
4621         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
4622         if (IS_ERR(devr->c0)) {
4623                 ret = PTR_ERR(devr->c0);
4624                 goto error1;
4625         }
4626         devr->c0->device        = &dev->ib_dev;
4627         devr->c0->uobject       = NULL;
4628         devr->c0->comp_handler  = NULL;
4629         devr->c0->event_handler = NULL;
4630         devr->c0->cq_context    = NULL;
4631         atomic_set(&devr->c0->usecnt, 0);
4632
4633         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4634         if (IS_ERR(devr->x0)) {
4635                 ret = PTR_ERR(devr->x0);
4636                 goto error2;
4637         }
4638         devr->x0->device = &dev->ib_dev;
4639         devr->x0->inode = NULL;
4640         atomic_set(&devr->x0->usecnt, 0);
4641         mutex_init(&devr->x0->tgt_qp_mutex);
4642         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4643
4644         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4645         if (IS_ERR(devr->x1)) {
4646                 ret = PTR_ERR(devr->x1);
4647                 goto error3;
4648         }
4649         devr->x1->device = &dev->ib_dev;
4650         devr->x1->inode = NULL;
4651         atomic_set(&devr->x1->usecnt, 0);
4652         mutex_init(&devr->x1->tgt_qp_mutex);
4653         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4654
4655         memset(&attr, 0, sizeof(attr));
4656         attr.attr.max_sge = 1;
4657         attr.attr.max_wr = 1;
4658         attr.srq_type = IB_SRQT_XRC;
4659         attr.ext.cq = devr->c0;
4660         attr.ext.xrc.xrcd = devr->x0;
4661
4662         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4663         if (IS_ERR(devr->s0)) {
4664                 ret = PTR_ERR(devr->s0);
4665                 goto error4;
4666         }
4667         devr->s0->device        = &dev->ib_dev;
4668         devr->s0->pd            = devr->p0;
4669         devr->s0->uobject       = NULL;
4670         devr->s0->event_handler = NULL;
4671         devr->s0->srq_context   = NULL;
4672         devr->s0->srq_type      = IB_SRQT_XRC;
4673         devr->s0->ext.xrc.xrcd  = devr->x0;
4674         devr->s0->ext.cq        = devr->c0;
4675         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4676         atomic_inc(&devr->s0->ext.cq->usecnt);
4677         atomic_inc(&devr->p0->usecnt);
4678         atomic_set(&devr->s0->usecnt, 0);
4679
4680         memset(&attr, 0, sizeof(attr));
4681         attr.attr.max_sge = 1;
4682         attr.attr.max_wr = 1;
4683         attr.srq_type = IB_SRQT_BASIC;
4684         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4685         if (IS_ERR(devr->s1)) {
4686                 ret = PTR_ERR(devr->s1);
4687                 goto error5;
4688         }
4689         devr->s1->device        = &dev->ib_dev;
4690         devr->s1->pd            = devr->p0;
4691         devr->s1->uobject       = NULL;
4692         devr->s1->event_handler = NULL;
4693         devr->s1->srq_context   = NULL;
4694         devr->s1->srq_type      = IB_SRQT_BASIC;
4695         devr->s1->ext.cq        = devr->c0;
4696         atomic_inc(&devr->p0->usecnt);
4697         atomic_set(&devr->s1->usecnt, 0);
4698
4699         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4700                 INIT_WORK(&devr->ports[port].pkey_change_work,
4701                           pkey_change_handler);
4702                 devr->ports[port].devr = devr;
4703         }
4704
4705         return 0;
4706
4707 error5:
4708         mlx5_ib_destroy_srq(devr->s0);
4709 error4:
4710         mlx5_ib_dealloc_xrcd(devr->x1);
4711 error3:
4712         mlx5_ib_dealloc_xrcd(devr->x0);
4713 error2:
4714         mlx5_ib_destroy_cq(devr->c0);
4715 error1:
4716         mlx5_ib_dealloc_pd(devr->p0);
4717 error0:
4718         return ret;
4719 }
4720
4721 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4722 {
4723         struct mlx5_ib_dev *dev =
4724                 container_of(devr, struct mlx5_ib_dev, devr);
4725         int port;
4726
4727         mlx5_ib_destroy_srq(devr->s1);
4728         mlx5_ib_destroy_srq(devr->s0);
4729         mlx5_ib_dealloc_xrcd(devr->x0);
4730         mlx5_ib_dealloc_xrcd(devr->x1);
4731         mlx5_ib_destroy_cq(devr->c0);
4732         mlx5_ib_dealloc_pd(devr->p0);
4733
4734         /* Make sure no change P_Key work items are still executing */
4735         for (port = 0; port < dev->num_ports; ++port)
4736                 cancel_work_sync(&devr->ports[port].pkey_change_work);
4737 }
4738
4739 static u32 get_core_cap_flags(struct ib_device *ibdev,
4740                               struct mlx5_hca_vport_context *rep)
4741 {
4742         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4743         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4744         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4745         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
4746         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
4747         u32 ret = 0;
4748
4749         if (rep->grh_required)
4750                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4751
4752         if (ll == IB_LINK_LAYER_INFINIBAND)
4753                 return ret | RDMA_CORE_PORT_IBA_IB;
4754
4755         if (raw_support)
4756                 ret |= RDMA_CORE_PORT_RAW_PACKET;
4757
4758         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
4759                 return ret;
4760
4761         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
4762                 return ret;
4763
4764         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4765                 ret |= RDMA_CORE_PORT_IBA_ROCE;
4766
4767         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4768                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4769
4770         return ret;
4771 }
4772
4773 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4774                                struct ib_port_immutable *immutable)
4775 {
4776         struct ib_port_attr attr;
4777         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4778         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
4779         struct mlx5_hca_vport_context rep = {0};
4780         int err;
4781
4782         err = ib_query_port(ibdev, port_num, &attr);
4783         if (err)
4784                 return err;
4785
4786         if (ll == IB_LINK_LAYER_INFINIBAND) {
4787                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4788                                                    &rep);
4789                 if (err)
4790                         return err;
4791         }
4792
4793         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4794         immutable->gid_tbl_len = attr.gid_tbl_len;
4795         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
4796         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4797                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4798
4799         return 0;
4800 }
4801
4802 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4803                                    struct ib_port_immutable *immutable)
4804 {
4805         struct ib_port_attr attr;
4806         int err;
4807
4808         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4809
4810         err = ib_query_port(ibdev, port_num, &attr);
4811         if (err)
4812                 return err;
4813
4814         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4815         immutable->gid_tbl_len = attr.gid_tbl_len;
4816         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4817
4818         return 0;
4819 }
4820
4821 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
4822 {
4823         struct mlx5_ib_dev *dev =
4824                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
4825         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4826                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4827                  fw_rev_sub(dev->mdev));
4828 }
4829
4830 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
4831 {
4832         struct mlx5_core_dev *mdev = dev->mdev;
4833         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4834                                                                  MLX5_FLOW_NAMESPACE_LAG);
4835         struct mlx5_flow_table *ft;
4836         int err;
4837
4838         if (!ns || !mlx5_lag_is_active(mdev))
4839                 return 0;
4840
4841         err = mlx5_cmd_create_vport_lag(mdev);
4842         if (err)
4843                 return err;
4844
4845         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4846         if (IS_ERR(ft)) {
4847                 err = PTR_ERR(ft);
4848                 goto err_destroy_vport_lag;
4849         }
4850
4851         dev->flow_db->lag_demux_ft = ft;
4852         return 0;
4853
4854 err_destroy_vport_lag:
4855         mlx5_cmd_destroy_vport_lag(mdev);
4856         return err;
4857 }
4858
4859 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
4860 {
4861         struct mlx5_core_dev *mdev = dev->mdev;
4862
4863         if (dev->flow_db->lag_demux_ft) {
4864                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4865                 dev->flow_db->lag_demux_ft = NULL;
4866
4867                 mlx5_cmd_destroy_vport_lag(mdev);
4868         }
4869 }
4870
4871 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4872 {
4873         int err;
4874
4875         dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4876         err = register_netdevice_notifier(&dev->roce[port_num].nb);
4877         if (err) {
4878                 dev->roce[port_num].nb.notifier_call = NULL;
4879                 return err;
4880         }
4881
4882         return 0;
4883 }
4884
4885 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4886 {
4887         if (dev->roce[port_num].nb.notifier_call) {
4888                 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4889                 dev->roce[port_num].nb.notifier_call = NULL;
4890         }
4891 }
4892
4893 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
4894 {
4895         int err;
4896
4897         if (MLX5_CAP_GEN(dev->mdev, roce)) {
4898                 err = mlx5_nic_vport_enable_roce(dev->mdev);
4899                 if (err)
4900                         return err;
4901         }
4902
4903         err = mlx5_eth_lag_init(dev);
4904         if (err)
4905                 goto err_disable_roce;
4906
4907         return 0;
4908
4909 err_disable_roce:
4910         if (MLX5_CAP_GEN(dev->mdev, roce))
4911                 mlx5_nic_vport_disable_roce(dev->mdev);
4912
4913         return err;
4914 }
4915
4916 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
4917 {
4918         mlx5_eth_lag_cleanup(dev);
4919         if (MLX5_CAP_GEN(dev->mdev, roce))
4920                 mlx5_nic_vport_disable_roce(dev->mdev);
4921 }
4922
4923 struct mlx5_ib_counter {
4924         const char *name;
4925         size_t offset;
4926 };
4927
4928 #define INIT_Q_COUNTER(_name)           \
4929         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4930
4931 static const struct mlx5_ib_counter basic_q_cnts[] = {
4932         INIT_Q_COUNTER(rx_write_requests),
4933         INIT_Q_COUNTER(rx_read_requests),
4934         INIT_Q_COUNTER(rx_atomic_requests),
4935         INIT_Q_COUNTER(out_of_buffer),
4936 };
4937
4938 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
4939         INIT_Q_COUNTER(out_of_sequence),
4940 };
4941
4942 static const struct mlx5_ib_counter retrans_q_cnts[] = {
4943         INIT_Q_COUNTER(duplicate_request),
4944         INIT_Q_COUNTER(rnr_nak_retry_err),
4945         INIT_Q_COUNTER(packet_seq_err),
4946         INIT_Q_COUNTER(implied_nak_seq_err),
4947         INIT_Q_COUNTER(local_ack_timeout_err),
4948 };
4949
4950 #define INIT_CONG_COUNTER(_name)                \
4951         { .name = #_name, .offset =     \
4952                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4953
4954 static const struct mlx5_ib_counter cong_cnts[] = {
4955         INIT_CONG_COUNTER(rp_cnp_ignored),
4956         INIT_CONG_COUNTER(rp_cnp_handled),
4957         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4958         INIT_CONG_COUNTER(np_cnp_sent),
4959 };
4960
4961 static const struct mlx5_ib_counter extended_err_cnts[] = {
4962         INIT_Q_COUNTER(resp_local_length_error),
4963         INIT_Q_COUNTER(resp_cqe_error),
4964         INIT_Q_COUNTER(req_cqe_error),
4965         INIT_Q_COUNTER(req_remote_invalid_request),
4966         INIT_Q_COUNTER(req_remote_access_errors),
4967         INIT_Q_COUNTER(resp_remote_access_errors),
4968         INIT_Q_COUNTER(resp_cqe_flush_error),
4969         INIT_Q_COUNTER(req_cqe_flush_error),
4970 };
4971
4972 #define INIT_EXT_PPCNT_COUNTER(_name)           \
4973         { .name = #_name, .offset =     \
4974         MLX5_BYTE_OFF(ppcnt_reg, \
4975                       counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
4976
4977 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
4978         INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
4979 };
4980
4981 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
4982 {
4983         int i;
4984
4985         for (i = 0; i < dev->num_ports; i++) {
4986                 if (dev->port[i].cnts.set_id_valid)
4987                         mlx5_core_dealloc_q_counter(dev->mdev,
4988                                                     dev->port[i].cnts.set_id);
4989                 kfree(dev->port[i].cnts.names);
4990                 kfree(dev->port[i].cnts.offsets);
4991         }
4992 }
4993
4994 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4995                                     struct mlx5_ib_counters *cnts)
4996 {
4997         u32 num_counters;
4998
4999         num_counters = ARRAY_SIZE(basic_q_cnts);
5000
5001         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5002                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5003
5004         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5005                 num_counters += ARRAY_SIZE(retrans_q_cnts);
5006
5007         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5008                 num_counters += ARRAY_SIZE(extended_err_cnts);
5009
5010         cnts->num_q_counters = num_counters;
5011
5012         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5013                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5014                 num_counters += ARRAY_SIZE(cong_cnts);
5015         }
5016         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5017                 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5018                 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5019         }
5020         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5021         if (!cnts->names)
5022                 return -ENOMEM;
5023
5024         cnts->offsets = kcalloc(num_counters,
5025                                 sizeof(cnts->offsets), GFP_KERNEL);
5026         if (!cnts->offsets)
5027                 goto err_names;
5028
5029         return 0;
5030
5031 err_names:
5032         kfree(cnts->names);
5033         cnts->names = NULL;
5034         return -ENOMEM;
5035 }
5036
5037 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5038                                   const char **names,
5039                                   size_t *offsets)
5040 {
5041         int i;
5042         int j = 0;
5043
5044         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5045                 names[j] = basic_q_cnts[i].name;
5046                 offsets[j] = basic_q_cnts[i].offset;
5047         }
5048
5049         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5050                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5051                         names[j] = out_of_seq_q_cnts[i].name;
5052                         offsets[j] = out_of_seq_q_cnts[i].offset;
5053                 }
5054         }
5055
5056         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5057                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5058                         names[j] = retrans_q_cnts[i].name;
5059                         offsets[j] = retrans_q_cnts[i].offset;
5060                 }
5061         }
5062
5063         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5064                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5065                         names[j] = extended_err_cnts[i].name;
5066                         offsets[j] = extended_err_cnts[i].offset;
5067                 }
5068         }
5069
5070         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5071                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5072                         names[j] = cong_cnts[i].name;
5073                         offsets[j] = cong_cnts[i].offset;
5074                 }
5075         }
5076
5077         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5078                 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5079                         names[j] = ext_ppcnt_cnts[i].name;
5080                         offsets[j] = ext_ppcnt_cnts[i].offset;
5081                 }
5082         }
5083 }
5084
5085 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5086 {
5087         int err = 0;
5088         int i;
5089
5090         for (i = 0; i < dev->num_ports; i++) {
5091                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5092                 if (err)
5093                         goto err_alloc;
5094
5095                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5096                                       dev->port[i].cnts.offsets);
5097
5098                 err = mlx5_core_alloc_q_counter(dev->mdev,
5099                                                 &dev->port[i].cnts.set_id);
5100                 if (err) {
5101                         mlx5_ib_warn(dev,
5102                                      "couldn't allocate queue counter for port %d, err %d\n",
5103                                      i + 1, err);
5104                         goto err_alloc;
5105                 }
5106                 dev->port[i].cnts.set_id_valid = true;
5107         }
5108
5109         return 0;
5110
5111 err_alloc:
5112         mlx5_ib_dealloc_counters(dev);
5113         return err;
5114 }
5115
5116 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5117                                                     u8 port_num)
5118 {
5119         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5120         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5121
5122         /* We support only per port stats */
5123         if (port_num == 0)
5124                 return NULL;
5125
5126         return rdma_alloc_hw_stats_struct(port->cnts.names,
5127                                           port->cnts.num_q_counters +
5128                                           port->cnts.num_cong_counters +
5129                                           port->cnts.num_ext_ppcnt_counters,
5130                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
5131 }
5132
5133 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5134                                     struct mlx5_ib_port *port,
5135                                     struct rdma_hw_stats *stats)
5136 {
5137         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5138         void *out;
5139         __be32 val;
5140         int ret, i;
5141
5142         out = kvzalloc(outlen, GFP_KERNEL);
5143         if (!out)
5144                 return -ENOMEM;
5145
5146         ret = mlx5_core_query_q_counter(mdev,
5147                                         port->cnts.set_id, 0,
5148                                         out, outlen);
5149         if (ret)
5150                 goto free;
5151
5152         for (i = 0; i < port->cnts.num_q_counters; i++) {
5153                 val = *(__be32 *)(out + port->cnts.offsets[i]);
5154                 stats->value[i] = (u64)be32_to_cpu(val);
5155         }
5156
5157 free:
5158         kvfree(out);
5159         return ret;
5160 }
5161
5162 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5163                                           struct mlx5_ib_port *port,
5164                                           struct rdma_hw_stats *stats)
5165 {
5166         int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5167         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5168         int ret, i;
5169         void *out;
5170
5171         out = kvzalloc(sz, GFP_KERNEL);
5172         if (!out)
5173                 return -ENOMEM;
5174
5175         ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5176         if (ret)
5177                 goto free;
5178
5179         for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5180                 stats->value[i + offset] =
5181                         be64_to_cpup((__be64 *)(out +
5182                                     port->cnts.offsets[i + offset]));
5183         }
5184
5185 free:
5186         kvfree(out);
5187         return ret;
5188 }
5189
5190 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5191                                 struct rdma_hw_stats *stats,
5192                                 u8 port_num, int index)
5193 {
5194         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5195         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5196         struct mlx5_core_dev *mdev;
5197         int ret, num_counters;
5198         u8 mdev_port_num;
5199
5200         if (!stats)
5201                 return -EINVAL;
5202
5203         num_counters = port->cnts.num_q_counters +
5204                        port->cnts.num_cong_counters +
5205                        port->cnts.num_ext_ppcnt_counters;
5206
5207         /* q_counters are per IB device, query the master mdev */
5208         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
5209         if (ret)
5210                 return ret;
5211
5212         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5213                 ret =  mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5214                 if (ret)
5215                         return ret;
5216         }
5217
5218         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5219                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5220                                                     &mdev_port_num);
5221                 if (!mdev) {
5222                         /* If port is not affiliated yet, its in down state
5223                          * which doesn't have any counters yet, so it would be
5224                          * zero. So no need to read from the HCA.
5225                          */
5226                         goto done;
5227                 }
5228                 ret = mlx5_lag_query_cong_counters(dev->mdev,
5229                                                    stats->value +
5230                                                    port->cnts.num_q_counters,
5231                                                    port->cnts.num_cong_counters,
5232                                                    port->cnts.offsets +
5233                                                    port->cnts.num_q_counters);
5234
5235                 mlx5_ib_put_native_port_mdev(dev, port_num);
5236                 if (ret)
5237                         return ret;
5238         }
5239
5240 done:
5241         return num_counters;
5242 }
5243
5244 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5245                                  enum rdma_netdev_t type,
5246                                  struct rdma_netdev_alloc_params *params)
5247 {
5248         if (type != RDMA_NETDEV_IPOIB)
5249                 return -EOPNOTSUPP;
5250
5251         return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
5252 }
5253
5254 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5255 {
5256         if (!dev->delay_drop.dbg)
5257                 return;
5258         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5259         kfree(dev->delay_drop.dbg);
5260         dev->delay_drop.dbg = NULL;
5261 }
5262
5263 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5264 {
5265         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5266                 return;
5267
5268         cancel_work_sync(&dev->delay_drop.delay_drop_work);
5269         delay_drop_debugfs_cleanup(dev);
5270 }
5271
5272 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5273                                        size_t count, loff_t *pos)
5274 {
5275         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5276         char lbuf[20];
5277         int len;
5278
5279         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5280         return simple_read_from_buffer(buf, count, pos, lbuf, len);
5281 }
5282
5283 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5284                                         size_t count, loff_t *pos)
5285 {
5286         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5287         u32 timeout;
5288         u32 var;
5289
5290         if (kstrtouint_from_user(buf, count, 0, &var))
5291                 return -EFAULT;
5292
5293         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5294                         1000);
5295         if (timeout != var)
5296                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5297                             timeout);
5298
5299         delay_drop->timeout = timeout;
5300
5301         return count;
5302 }
5303
5304 static const struct file_operations fops_delay_drop_timeout = {
5305         .owner  = THIS_MODULE,
5306         .open   = simple_open,
5307         .write  = delay_drop_timeout_write,
5308         .read   = delay_drop_timeout_read,
5309 };
5310
5311 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5312 {
5313         struct mlx5_ib_dbg_delay_drop *dbg;
5314
5315         if (!mlx5_debugfs_root)
5316                 return 0;
5317
5318         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5319         if (!dbg)
5320                 return -ENOMEM;
5321
5322         dev->delay_drop.dbg = dbg;
5323
5324         dbg->dir_debugfs =
5325                 debugfs_create_dir("delay_drop",
5326                                    dev->mdev->priv.dbg_root);
5327         if (!dbg->dir_debugfs)
5328                 goto out_debugfs;
5329
5330         dbg->events_cnt_debugfs =
5331                 debugfs_create_atomic_t("num_timeout_events", 0400,
5332                                         dbg->dir_debugfs,
5333                                         &dev->delay_drop.events_cnt);
5334         if (!dbg->events_cnt_debugfs)
5335                 goto out_debugfs;
5336
5337         dbg->rqs_cnt_debugfs =
5338                 debugfs_create_atomic_t("num_rqs", 0400,
5339                                         dbg->dir_debugfs,
5340                                         &dev->delay_drop.rqs_cnt);
5341         if (!dbg->rqs_cnt_debugfs)
5342                 goto out_debugfs;
5343
5344         dbg->timeout_debugfs =
5345                 debugfs_create_file("timeout", 0600,
5346                                     dbg->dir_debugfs,
5347                                     &dev->delay_drop,
5348                                     &fops_delay_drop_timeout);
5349         if (!dbg->timeout_debugfs)
5350                 goto out_debugfs;
5351
5352         return 0;
5353
5354 out_debugfs:
5355         delay_drop_debugfs_cleanup(dev);
5356         return -ENOMEM;
5357 }
5358
5359 static void init_delay_drop(struct mlx5_ib_dev *dev)
5360 {
5361         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5362                 return;
5363
5364         mutex_init(&dev->delay_drop.lock);
5365         dev->delay_drop.dev = dev;
5366         dev->delay_drop.activate = false;
5367         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5368         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5369         atomic_set(&dev->delay_drop.rqs_cnt, 0);
5370         atomic_set(&dev->delay_drop.events_cnt, 0);
5371
5372         if (delay_drop_debugfs_init(dev))
5373                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5374 }
5375
5376 static const struct cpumask *
5377 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
5378 {
5379         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5380
5381         return mlx5_comp_irq_get_affinity_mask(dev->mdev, comp_vector);
5382 }
5383
5384 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5385 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5386                                       struct mlx5_ib_multiport_info *mpi)
5387 {
5388         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5389         struct mlx5_ib_port *port = &ibdev->port[port_num];
5390         int comps;
5391         int err;
5392         int i;
5393
5394         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5395
5396         spin_lock(&port->mp.mpi_lock);
5397         if (!mpi->ibdev) {
5398                 spin_unlock(&port->mp.mpi_lock);
5399                 return;
5400         }
5401
5402         if (mpi->mdev_events.notifier_call)
5403                 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5404         mpi->mdev_events.notifier_call = NULL;
5405
5406         mpi->ibdev = NULL;
5407
5408         spin_unlock(&port->mp.mpi_lock);
5409         mlx5_remove_netdev_notifier(ibdev, port_num);
5410         spin_lock(&port->mp.mpi_lock);
5411
5412         comps = mpi->mdev_refcnt;
5413         if (comps) {
5414                 mpi->unaffiliate = true;
5415                 init_completion(&mpi->unref_comp);
5416                 spin_unlock(&port->mp.mpi_lock);
5417
5418                 for (i = 0; i < comps; i++)
5419                         wait_for_completion(&mpi->unref_comp);
5420
5421                 spin_lock(&port->mp.mpi_lock);
5422                 mpi->unaffiliate = false;
5423         }
5424
5425         port->mp.mpi = NULL;
5426
5427         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5428
5429         spin_unlock(&port->mp.mpi_lock);
5430
5431         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5432
5433         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5434         /* Log an error, still needed to cleanup the pointers and add
5435          * it back to the list.
5436          */
5437         if (err)
5438                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5439                             port_num + 1);
5440
5441         ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5442 }
5443
5444 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5445 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5446                                     struct mlx5_ib_multiport_info *mpi)
5447 {
5448         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5449         int err;
5450
5451         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5452         if (ibdev->port[port_num].mp.mpi) {
5453                 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5454                             port_num + 1);
5455                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5456                 return false;
5457         }
5458
5459         ibdev->port[port_num].mp.mpi = mpi;
5460         mpi->ibdev = ibdev;
5461         mpi->mdev_events.notifier_call = NULL;
5462         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5463
5464         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5465         if (err)
5466                 goto unbind;
5467
5468         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5469         if (err)
5470                 goto unbind;
5471
5472         err = mlx5_add_netdev_notifier(ibdev, port_num);
5473         if (err) {
5474                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5475                             port_num + 1);
5476                 goto unbind;
5477         }
5478
5479         mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5480         mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5481
5482         err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5483         if (err)
5484                 goto unbind;
5485
5486         return true;
5487
5488 unbind:
5489         mlx5_ib_unbind_slave_port(ibdev, mpi);
5490         return false;
5491 }
5492
5493 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5494 {
5495         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5496         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5497                                                           port_num + 1);
5498         struct mlx5_ib_multiport_info *mpi;
5499         int err;
5500         int i;
5501
5502         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5503                 return 0;
5504
5505         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5506                                                      &dev->sys_image_guid);
5507         if (err)
5508                 return err;
5509
5510         err = mlx5_nic_vport_enable_roce(dev->mdev);
5511         if (err)
5512                 return err;
5513
5514         mutex_lock(&mlx5_ib_multiport_mutex);
5515         for (i = 0; i < dev->num_ports; i++) {
5516                 bool bound = false;
5517
5518                 /* build a stub multiport info struct for the native port. */
5519                 if (i == port_num) {
5520                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5521                         if (!mpi) {
5522                                 mutex_unlock(&mlx5_ib_multiport_mutex);
5523                                 mlx5_nic_vport_disable_roce(dev->mdev);
5524                                 return -ENOMEM;
5525                         }
5526
5527                         mpi->is_master = true;
5528                         mpi->mdev = dev->mdev;
5529                         mpi->sys_image_guid = dev->sys_image_guid;
5530                         dev->port[i].mp.mpi = mpi;
5531                         mpi->ibdev = dev;
5532                         mpi = NULL;
5533                         continue;
5534                 }
5535
5536                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5537                                     list) {
5538                         if (dev->sys_image_guid == mpi->sys_image_guid &&
5539                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5540                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
5541                         }
5542
5543                         if (bound) {
5544                                 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5545                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5546                                 list_del(&mpi->list);
5547                                 break;
5548                         }
5549                 }
5550                 if (!bound) {
5551                         get_port_caps(dev, i + 1);
5552                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
5553                                     i + 1);
5554                 }
5555         }
5556
5557         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5558         mutex_unlock(&mlx5_ib_multiport_mutex);
5559         return err;
5560 }
5561
5562 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5563 {
5564         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5565         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5566                                                           port_num + 1);
5567         int i;
5568
5569         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5570                 return;
5571
5572         mutex_lock(&mlx5_ib_multiport_mutex);
5573         for (i = 0; i < dev->num_ports; i++) {
5574                 if (dev->port[i].mp.mpi) {
5575                         /* Destroy the native port stub */
5576                         if (i == port_num) {
5577                                 kfree(dev->port[i].mp.mpi);
5578                                 dev->port[i].mp.mpi = NULL;
5579                         } else {
5580                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5581                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5582                         }
5583                 }
5584         }
5585
5586         mlx5_ib_dbg(dev, "removing from devlist\n");
5587         list_del(&dev->ib_dev_list);
5588         mutex_unlock(&mlx5_ib_multiport_mutex);
5589
5590         mlx5_nic_vport_disable_roce(dev->mdev);
5591 }
5592
5593 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5594         mlx5_ib_dm,
5595         UVERBS_OBJECT_DM,
5596         UVERBS_METHOD_DM_ALLOC,
5597         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5598                             UVERBS_ATTR_TYPE(u64),
5599                             UA_MANDATORY),
5600         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5601                             UVERBS_ATTR_TYPE(u16),
5602                             UA_MANDATORY));
5603
5604 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5605         mlx5_ib_flow_action,
5606         UVERBS_OBJECT_FLOW_ACTION,
5607         UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5608         UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5609                              enum mlx5_ib_uapi_flow_action_flags));
5610
5611 static int populate_specs_root(struct mlx5_ib_dev *dev)
5612 {
5613         const struct uverbs_object_tree_def **trees = dev->driver_trees;
5614         size_t num_trees = 0;
5615
5616         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
5617             MLX5_ACCEL_IPSEC_CAP_DEVICE)
5618                 trees[num_trees++] = &mlx5_ib_flow_action;
5619
5620         if (MLX5_CAP_DEV_MEM(dev->mdev, memic))
5621                 trees[num_trees++] = &mlx5_ib_dm;
5622
5623         if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
5624             MLX5_GENERAL_OBJ_TYPES_CAP_UCTX)
5625                 trees[num_trees++] = mlx5_ib_get_devx_tree();
5626
5627         num_trees += mlx5_ib_get_flow_trees(trees + num_trees);
5628
5629         WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees));
5630         trees[num_trees] = NULL;
5631         dev->ib_dev.driver_specs = trees;
5632
5633         return 0;
5634 }
5635
5636 static int mlx5_ib_read_counters(struct ib_counters *counters,
5637                                  struct ib_counters_read_attr *read_attr,
5638                                  struct uverbs_attr_bundle *attrs)
5639 {
5640         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5641         struct mlx5_read_counters_attr mread_attr = {};
5642         struct mlx5_ib_flow_counters_desc *desc;
5643         int ret, i;
5644
5645         mutex_lock(&mcounters->mcntrs_mutex);
5646         if (mcounters->cntrs_max_index > read_attr->ncounters) {
5647                 ret = -EINVAL;
5648                 goto err_bound;
5649         }
5650
5651         mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5652                                  GFP_KERNEL);
5653         if (!mread_attr.out) {
5654                 ret = -ENOMEM;
5655                 goto err_bound;
5656         }
5657
5658         mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5659         mread_attr.flags = read_attr->flags;
5660         ret = mcounters->read_counters(counters->device, &mread_attr);
5661         if (ret)
5662                 goto err_read;
5663
5664         /* do the pass over the counters data array to assign according to the
5665          * descriptions and indexing pairs
5666          */
5667         desc = mcounters->counters_data;
5668         for (i = 0; i < mcounters->ncounters; i++)
5669                 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5670
5671 err_read:
5672         kfree(mread_attr.out);
5673 err_bound:
5674         mutex_unlock(&mcounters->mcntrs_mutex);
5675         return ret;
5676 }
5677
5678 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5679 {
5680         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5681
5682         counters_clear_description(counters);
5683         if (mcounters->hw_cntrs_hndl)
5684                 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5685                                 mcounters->hw_cntrs_hndl);
5686
5687         kfree(mcounters);
5688
5689         return 0;
5690 }
5691
5692 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5693                                                    struct uverbs_attr_bundle *attrs)
5694 {
5695         struct mlx5_ib_mcounters *mcounters;
5696
5697         mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5698         if (!mcounters)
5699                 return ERR_PTR(-ENOMEM);
5700
5701         mutex_init(&mcounters->mcntrs_mutex);
5702
5703         return &mcounters->ibcntrs;
5704 }
5705
5706 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5707 {
5708         mlx5_ib_cleanup_multiport_master(dev);
5709 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5710         cleanup_srcu_struct(&dev->mr_srcu);
5711 #endif
5712         kfree(dev->port);
5713 }
5714
5715 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
5716 {
5717         struct mlx5_core_dev *mdev = dev->mdev;
5718         int err;
5719         int i;
5720
5721         dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
5722                             GFP_KERNEL);
5723         if (!dev->port)
5724                 return -ENOMEM;
5725
5726         for (i = 0; i < dev->num_ports; i++) {
5727                 spin_lock_init(&dev->port[i].mp.mpi_lock);
5728                 rwlock_init(&dev->roce[i].netdev_lock);
5729         }
5730
5731         err = mlx5_ib_init_multiport_master(dev);
5732         if (err)
5733                 goto err_free_port;
5734
5735         if (!mlx5_core_mp_enabled(mdev)) {
5736                 for (i = 1; i <= dev->num_ports; i++) {
5737                         err = get_port_caps(dev, i);
5738                         if (err)
5739                                 break;
5740                 }
5741         } else {
5742                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5743         }
5744         if (err)
5745                 goto err_mp;
5746
5747         if (mlx5_use_mad_ifc(dev))
5748                 get_ext_port_caps(dev);
5749
5750         dev->ib_dev.owner               = THIS_MODULE;
5751         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
5752         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
5753         dev->ib_dev.phys_port_cnt       = dev->num_ports;
5754         dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_count(mdev);
5755         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
5756
5757         mutex_init(&dev->cap_mask_mutex);
5758         INIT_LIST_HEAD(&dev->qp_list);
5759         spin_lock_init(&dev->reset_flow_resource_lock);
5760
5761         spin_lock_init(&dev->memic.memic_lock);
5762         dev->memic.dev = mdev;
5763
5764 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5765         err = init_srcu_struct(&dev->mr_srcu);
5766         if (err)
5767                 goto err_free_port;
5768 #endif
5769
5770         return 0;
5771 err_mp:
5772         mlx5_ib_cleanup_multiport_master(dev);
5773
5774 err_free_port:
5775         kfree(dev->port);
5776
5777         return -ENOMEM;
5778 }
5779
5780 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5781 {
5782         dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5783
5784         if (!dev->flow_db)
5785                 return -ENOMEM;
5786
5787         mutex_init(&dev->flow_db->lock);
5788
5789         return 0;
5790 }
5791
5792 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5793 {
5794         struct mlx5_ib_dev *nic_dev;
5795
5796         nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5797
5798         if (!nic_dev)
5799                 return -EINVAL;
5800
5801         dev->flow_db = nic_dev->flow_db;
5802
5803         return 0;
5804 }
5805
5806 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5807 {
5808         kfree(dev->flow_db);
5809 }
5810
5811 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
5812 {
5813         struct mlx5_core_dev *mdev = dev->mdev;
5814         int err;
5815
5816         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
5817         dev->ib_dev.uverbs_cmd_mask     =
5818                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
5819                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
5820                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
5821                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
5822                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
5823                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
5824                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
5825                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
5826                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
5827                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
5828                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5829                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
5830                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
5831                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
5832                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
5833                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
5834                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
5835                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
5836                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
5837                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
5838                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
5839                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
5840                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
5841                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
5842                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
5843                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
5844         dev->ib_dev.uverbs_ex_cmd_mask =
5845                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
5846                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
5847                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
5848                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
5849                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
5850
5851         dev->ib_dev.query_device        = mlx5_ib_query_device;
5852         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
5853         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
5854         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
5855         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
5856         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
5857         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
5858         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
5859         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
5860         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
5861         dev->ib_dev.mmap                = mlx5_ib_mmap;
5862         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
5863         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
5864         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
5865         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
5866         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
5867         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
5868         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
5869         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
5870         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
5871         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
5872         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
5873         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
5874         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
5875         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
5876         dev->ib_dev.drain_sq            = mlx5_ib_drain_sq;
5877         dev->ib_dev.drain_rq            = mlx5_ib_drain_rq;
5878         dev->ib_dev.post_send           = mlx5_ib_post_send;
5879         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
5880         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
5881         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
5882         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
5883         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
5884         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
5885         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
5886         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
5887         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
5888         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
5889         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
5890         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
5891         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
5892         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
5893         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
5894         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
5895         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
5896         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
5897         dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
5898         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
5899             IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
5900                 dev->ib_dev.rdma_netdev_get_params = mlx5_ib_rn_get_params;
5901
5902         if (mlx5_core_is_pf(mdev)) {
5903                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
5904                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
5905                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
5906                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
5907         }
5908
5909         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5910
5911         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5912
5913         if (MLX5_CAP_GEN(mdev, imaicl)) {
5914                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
5915                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
5916                 dev->ib_dev.uverbs_cmd_mask |=
5917                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
5918                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5919         }
5920
5921         if (MLX5_CAP_GEN(mdev, xrc)) {
5922                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5923                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5924                 dev->ib_dev.uverbs_cmd_mask |=
5925                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5926                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5927         }
5928
5929         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5930                 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5931                 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
5932                 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
5933         }
5934
5935         dev->ib_dev.create_flow = mlx5_ib_create_flow;
5936         dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5937         dev->ib_dev.uverbs_ex_cmd_mask |=
5938                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5939                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5940         dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5941         dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
5942         dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
5943         dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
5944         dev->ib_dev.create_counters = mlx5_ib_create_counters;
5945         dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
5946         dev->ib_dev.read_counters = mlx5_ib_read_counters;
5947
5948         err = init_node_data(dev);
5949         if (err)
5950                 return err;
5951
5952         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
5953             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5954              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
5955                 mutex_init(&dev->lb.mutex);
5956
5957         return 0;
5958 }
5959
5960 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5961 {
5962         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
5963         dev->ib_dev.query_port          = mlx5_ib_query_port;
5964
5965         return 0;
5966 }
5967
5968 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
5969 {
5970         dev->ib_dev.get_port_immutable  = mlx5_port_rep_immutable;
5971         dev->ib_dev.query_port          = mlx5_ib_rep_query_port;
5972
5973         return 0;
5974 }
5975
5976 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
5977 {
5978         u8 port_num;
5979         int i;
5980
5981         for (i = 0; i < dev->num_ports; i++) {
5982                 dev->roce[i].dev = dev;
5983                 dev->roce[i].native_port_num = i + 1;
5984                 dev->roce[i].last_port_state = IB_PORT_DOWN;
5985         }
5986
5987         dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
5988         dev->ib_dev.create_wq    = mlx5_ib_create_wq;
5989         dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
5990         dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
5991         dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5992         dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5993
5994         dev->ib_dev.uverbs_ex_cmd_mask |=
5995                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5996                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5997                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5998                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5999                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
6000
6001         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6002
6003         return mlx5_add_netdev_notifier(dev, port_num);
6004 }
6005
6006 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6007 {
6008         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6009
6010         mlx5_remove_netdev_notifier(dev, port_num);
6011 }
6012
6013 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
6014 {
6015         struct mlx5_core_dev *mdev = dev->mdev;
6016         enum rdma_link_layer ll;
6017         int port_type_cap;
6018         int err = 0;
6019
6020         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6021         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6022
6023         if (ll == IB_LINK_LAYER_ETHERNET)
6024                 err = mlx5_ib_stage_common_roce_init(dev);
6025
6026         return err;
6027 }
6028
6029 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
6030 {
6031         mlx5_ib_stage_common_roce_cleanup(dev);
6032 }
6033
6034 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6035 {
6036         struct mlx5_core_dev *mdev = dev->mdev;
6037         enum rdma_link_layer ll;
6038         int port_type_cap;
6039         int err;
6040
6041         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6042         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6043
6044         if (ll == IB_LINK_LAYER_ETHERNET) {
6045                 err = mlx5_ib_stage_common_roce_init(dev);
6046                 if (err)
6047                         return err;
6048
6049                 err = mlx5_enable_eth(dev);
6050                 if (err)
6051                         goto cleanup;
6052         }
6053
6054         return 0;
6055 cleanup:
6056         mlx5_ib_stage_common_roce_cleanup(dev);
6057
6058         return err;
6059 }
6060
6061 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6062 {
6063         struct mlx5_core_dev *mdev = dev->mdev;
6064         enum rdma_link_layer ll;
6065         int port_type_cap;
6066
6067         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6068         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6069
6070         if (ll == IB_LINK_LAYER_ETHERNET) {
6071                 mlx5_disable_eth(dev);
6072                 mlx5_ib_stage_common_roce_cleanup(dev);
6073         }
6074 }
6075
6076 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6077 {
6078         return create_dev_resources(&dev->devr);
6079 }
6080
6081 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6082 {
6083         destroy_dev_resources(&dev->devr);
6084 }
6085
6086 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6087 {
6088         mlx5_ib_internal_fill_odp_caps(dev);
6089
6090         return mlx5_ib_odp_init_one(dev);
6091 }
6092
6093 void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
6094 {
6095         mlx5_ib_odp_cleanup_one(dev);
6096 }
6097
6098 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6099 {
6100         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6101                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
6102                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
6103
6104                 return mlx5_ib_alloc_counters(dev);
6105         }
6106
6107         return 0;
6108 }
6109
6110 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6111 {
6112         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6113                 mlx5_ib_dealloc_counters(dev);
6114 }
6115
6116 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6117 {
6118         return mlx5_ib_init_cong_debugfs(dev,
6119                                          mlx5_core_native_port_num(dev->mdev) - 1);
6120 }
6121
6122 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6123 {
6124         mlx5_ib_cleanup_cong_debugfs(dev,
6125                                      mlx5_core_native_port_num(dev->mdev) - 1);
6126 }
6127
6128 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6129 {
6130         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6131         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6132 }
6133
6134 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6135 {
6136         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6137 }
6138
6139 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6140 {
6141         int err;
6142
6143         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6144         if (err)
6145                 return err;
6146
6147         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6148         if (err)
6149                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6150
6151         return err;
6152 }
6153
6154 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6155 {
6156         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6157         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6158 }
6159
6160 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
6161 {
6162         return populate_specs_root(dev);
6163 }
6164
6165 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6166 {
6167         const char *name;
6168
6169         rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
6170         if (!mlx5_lag_is_active(dev->mdev))
6171                 name = "mlx5_%d";
6172         else
6173                 name = "mlx5_bond_%d";
6174         return ib_register_device(&dev->ib_dev, name, NULL);
6175 }
6176
6177 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6178 {
6179         destroy_umrc_res(dev);
6180 }
6181
6182 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6183 {
6184         ib_unregister_device(&dev->ib_dev);
6185 }
6186
6187 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6188 {
6189         return create_umr_res(dev);
6190 }
6191
6192 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6193 {
6194         init_delay_drop(dev);
6195
6196         return 0;
6197 }
6198
6199 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6200 {
6201         cancel_delay_drop(dev);
6202 }
6203
6204 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
6205 {
6206         mlx5_ib_register_vport_reps(dev);
6207
6208         return 0;
6209 }
6210
6211 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
6212 {
6213         mlx5_ib_unregister_vport_reps(dev);
6214 }
6215
6216 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6217 {
6218         dev->mdev_events.notifier_call = mlx5_ib_event;
6219         mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6220         return 0;
6221 }
6222
6223 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6224 {
6225         mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6226 }
6227
6228 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6229                       const struct mlx5_ib_profile *profile,
6230                       int stage)
6231 {
6232         /* Number of stages to cleanup */
6233         while (stage) {
6234                 stage--;
6235                 if (profile->stage[stage].cleanup)
6236                         profile->stage[stage].cleanup(dev);
6237         }
6238
6239         if (dev->devx_whitelist_uid)
6240                 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
6241         ib_dealloc_device((struct ib_device *)dev);
6242 }
6243
6244 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6245                     const struct mlx5_ib_profile *profile)
6246 {
6247         int err;
6248         int i;
6249         int uid;
6250
6251         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6252                 if (profile->stage[i].init) {
6253                         err = profile->stage[i].init(dev);
6254                         if (err)
6255                                 goto err_out;
6256                 }
6257         }
6258
6259         uid = mlx5_ib_devx_create(dev);
6260         if (uid > 0)
6261                 dev->devx_whitelist_uid = uid;
6262
6263         dev->profile = profile;
6264         dev->ib_active = true;
6265
6266         return dev;
6267
6268 err_out:
6269         __mlx5_ib_remove(dev, profile, i);
6270
6271         return NULL;
6272 }
6273
6274 static const struct mlx5_ib_profile pf_profile = {
6275         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6276                      mlx5_ib_stage_init_init,
6277                      mlx5_ib_stage_init_cleanup),
6278         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6279                      mlx5_ib_stage_flow_db_init,
6280                      mlx5_ib_stage_flow_db_cleanup),
6281         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6282                      mlx5_ib_stage_caps_init,
6283                      NULL),
6284         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6285                      mlx5_ib_stage_non_default_cb,
6286                      NULL),
6287         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6288                      mlx5_ib_stage_roce_init,
6289                      mlx5_ib_stage_roce_cleanup),
6290         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6291                      mlx5_ib_stage_dev_res_init,
6292                      mlx5_ib_stage_dev_res_cleanup),
6293         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6294                      mlx5_ib_stage_dev_notifier_init,
6295                      mlx5_ib_stage_dev_notifier_cleanup),
6296         STAGE_CREATE(MLX5_IB_STAGE_ODP,
6297                      mlx5_ib_stage_odp_init,
6298                      mlx5_ib_stage_odp_cleanup),
6299         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6300                      mlx5_ib_stage_counters_init,
6301                      mlx5_ib_stage_counters_cleanup),
6302         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6303                      mlx5_ib_stage_cong_debugfs_init,
6304                      mlx5_ib_stage_cong_debugfs_cleanup),
6305         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6306                      mlx5_ib_stage_uar_init,
6307                      mlx5_ib_stage_uar_cleanup),
6308         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6309                      mlx5_ib_stage_bfrag_init,
6310                      mlx5_ib_stage_bfrag_cleanup),
6311         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6312                      NULL,
6313                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6314         STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6315                      mlx5_ib_stage_populate_specs,
6316                      NULL),
6317         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6318                      mlx5_ib_stage_ib_reg_init,
6319                      mlx5_ib_stage_ib_reg_cleanup),
6320         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6321                      mlx5_ib_stage_post_ib_reg_umr_init,
6322                      NULL),
6323         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6324                      mlx5_ib_stage_delay_drop_init,
6325                      mlx5_ib_stage_delay_drop_cleanup),
6326 };
6327
6328 static const struct mlx5_ib_profile nic_rep_profile = {
6329         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6330                      mlx5_ib_stage_init_init,
6331                      mlx5_ib_stage_init_cleanup),
6332         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6333                      mlx5_ib_stage_flow_db_init,
6334                      mlx5_ib_stage_flow_db_cleanup),
6335         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6336                      mlx5_ib_stage_caps_init,
6337                      NULL),
6338         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6339                      mlx5_ib_stage_rep_non_default_cb,
6340                      NULL),
6341         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6342                      mlx5_ib_stage_rep_roce_init,
6343                      mlx5_ib_stage_rep_roce_cleanup),
6344         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6345                      mlx5_ib_stage_dev_res_init,
6346                      mlx5_ib_stage_dev_res_cleanup),
6347         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6348                      mlx5_ib_stage_dev_notifier_init,
6349                      mlx5_ib_stage_dev_notifier_cleanup),
6350         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6351                      mlx5_ib_stage_counters_init,
6352                      mlx5_ib_stage_counters_cleanup),
6353         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6354                      mlx5_ib_stage_uar_init,
6355                      mlx5_ib_stage_uar_cleanup),
6356         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6357                      mlx5_ib_stage_bfrag_init,
6358                      mlx5_ib_stage_bfrag_cleanup),
6359         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6360                      NULL,
6361                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6362         STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6363                      mlx5_ib_stage_populate_specs,
6364                      NULL),
6365         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6366                      mlx5_ib_stage_ib_reg_init,
6367                      mlx5_ib_stage_ib_reg_cleanup),
6368         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6369                      mlx5_ib_stage_post_ib_reg_umr_init,
6370                      NULL),
6371         STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6372                      mlx5_ib_stage_rep_reg_init,
6373                      mlx5_ib_stage_rep_reg_cleanup),
6374 };
6375
6376 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6377 {
6378         struct mlx5_ib_multiport_info *mpi;
6379         struct mlx5_ib_dev *dev;
6380         bool bound = false;
6381         int err;
6382
6383         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6384         if (!mpi)
6385                 return NULL;
6386
6387         mpi->mdev = mdev;
6388
6389         err = mlx5_query_nic_vport_system_image_guid(mdev,
6390                                                      &mpi->sys_image_guid);
6391         if (err) {
6392                 kfree(mpi);
6393                 return NULL;
6394         }
6395
6396         mutex_lock(&mlx5_ib_multiport_mutex);
6397         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6398                 if (dev->sys_image_guid == mpi->sys_image_guid)
6399                         bound = mlx5_ib_bind_slave_port(dev, mpi);
6400
6401                 if (bound) {
6402                         rdma_roce_rescan_device(&dev->ib_dev);
6403                         break;
6404                 }
6405         }
6406
6407         if (!bound) {
6408                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6409                 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
6410         }
6411         mutex_unlock(&mlx5_ib_multiport_mutex);
6412
6413         return mpi;
6414 }
6415
6416 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6417 {
6418         enum rdma_link_layer ll;
6419         struct mlx5_ib_dev *dev;
6420         int port_type_cap;
6421
6422         printk_once(KERN_INFO "%s", mlx5_version);
6423
6424         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6425         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6426
6427         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6428                 return mlx5_ib_add_slave_port(mdev);
6429
6430         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6431         if (!dev)
6432                 return NULL;
6433
6434         dev->mdev = mdev;
6435         dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6436                              MLX5_CAP_GEN(mdev, num_vhca_ports));
6437
6438         if (MLX5_ESWITCH_MANAGER(mdev) &&
6439             mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6440                 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6441
6442                 return __mlx5_ib_add(dev, &nic_rep_profile);
6443         }
6444
6445         return __mlx5_ib_add(dev, &pf_profile);
6446 }
6447
6448 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6449 {
6450         struct mlx5_ib_multiport_info *mpi;
6451         struct mlx5_ib_dev *dev;
6452
6453         if (mlx5_core_is_mp_slave(mdev)) {
6454                 mpi = context;
6455                 mutex_lock(&mlx5_ib_multiport_mutex);
6456                 if (mpi->ibdev)
6457                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6458                 list_del(&mpi->list);
6459                 mutex_unlock(&mlx5_ib_multiport_mutex);
6460                 return;
6461         }
6462
6463         dev = context;
6464         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6465 }
6466
6467 static struct mlx5_interface mlx5_ib_interface = {
6468         .add            = mlx5_ib_add,
6469         .remove         = mlx5_ib_remove,
6470         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
6471 };
6472
6473 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6474 {
6475         mutex_lock(&xlt_emergency_page_mutex);
6476         return xlt_emergency_page;
6477 }
6478
6479 void mlx5_ib_put_xlt_emergency_page(void)
6480 {
6481         mutex_unlock(&xlt_emergency_page_mutex);
6482 }
6483
6484 static int __init mlx5_ib_init(void)
6485 {
6486         int err;
6487
6488         xlt_emergency_page = __get_free_page(GFP_KERNEL);
6489         if (!xlt_emergency_page)
6490                 return -ENOMEM;
6491
6492         mutex_init(&xlt_emergency_page_mutex);
6493
6494         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6495         if (!mlx5_ib_event_wq) {
6496                 free_page(xlt_emergency_page);
6497                 return -ENOMEM;
6498         }
6499
6500         mlx5_ib_odp_init();
6501
6502         err = mlx5_register_interface(&mlx5_ib_interface);
6503
6504         return err;
6505 }
6506
6507 static void __exit mlx5_ib_cleanup(void)
6508 {
6509         mlx5_unregister_interface(&mlx5_ib_interface);
6510         destroy_workqueue(mlx5_ib_event_wq);
6511         mutex_destroy(&xlt_emergency_page_mutex);
6512         free_page(xlt_emergency_page);
6513 }
6514
6515 module_init(mlx5_ib_init);
6516 module_exit(mlx5_ib_cleanup);