2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/sched.h>
42 #include <rdma/ib_user_verbs.h>
43 #include <rdma/ib_addr.h>
44 #include <rdma/ib_cache.h>
45 #include <linux/mlx5/port.h>
46 #include <linux/mlx5/vport.h>
47 #include <rdma/ib_smi.h>
48 #include <rdma/ib_umem.h>
50 #include <linux/etherdevice.h>
51 #include <linux/mlx5/fs.h>
55 #define DRIVER_NAME "mlx5_ib"
56 #define DRIVER_VERSION "2.2-1"
57 #define DRIVER_RELDATE "Feb 2014"
59 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
60 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
61 MODULE_LICENSE("Dual BSD/GPL");
62 MODULE_VERSION(DRIVER_VERSION);
64 static int deprecated_prof_sel = 2;
65 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
66 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
68 static char mlx5_version[] =
69 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
70 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
73 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
76 static enum rdma_link_layer
77 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
79 switch (port_type_cap) {
80 case MLX5_CAP_PORT_TYPE_IB:
81 return IB_LINK_LAYER_INFINIBAND;
82 case MLX5_CAP_PORT_TYPE_ETH:
83 return IB_LINK_LAYER_ETHERNET;
85 return IB_LINK_LAYER_UNSPECIFIED;
89 static enum rdma_link_layer
90 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
92 struct mlx5_ib_dev *dev = to_mdev(device);
93 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
95 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
98 static int mlx5_netdev_event(struct notifier_block *this,
99 unsigned long event, void *ptr)
101 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
102 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
105 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
108 write_lock(&ibdev->roce.netdev_lock);
109 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
110 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
111 write_unlock(&ibdev->roce.netdev_lock);
116 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
119 struct mlx5_ib_dev *ibdev = to_mdev(device);
120 struct net_device *ndev;
122 /* Ensure ndev does not disappear before we invoke dev_hold()
124 read_lock(&ibdev->roce.netdev_lock);
125 ndev = ibdev->roce.netdev;
128 read_unlock(&ibdev->roce.netdev_lock);
133 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
134 struct ib_port_attr *props)
136 struct mlx5_ib_dev *dev = to_mdev(device);
137 struct net_device *ndev;
138 enum ib_mtu ndev_ib_mtu;
141 memset(props, 0, sizeof(*props));
143 props->port_cap_flags |= IB_PORT_CM_SUP;
144 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
146 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
147 roce_address_table_size);
148 props->max_mtu = IB_MTU_4096;
149 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
150 props->pkey_tbl_len = 1;
151 props->state = IB_PORT_DOWN;
152 props->phys_state = 3;
154 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
155 props->qkey_viol_cntr = qkey_viol_cntr;
157 ndev = mlx5_ib_get_netdev(device, port_num);
161 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
162 props->state = IB_PORT_ACTIVE;
163 props->phys_state = 5;
166 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
170 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
172 props->active_width = IB_WIDTH_4X; /* TODO */
173 props->active_speed = IB_SPEED_QDR; /* TODO */
178 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
179 const struct ib_gid_attr *attr,
182 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
183 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
185 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
191 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
193 if (is_vlan_dev(attr->ndev)) {
194 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
195 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
198 switch (attr->gid_type) {
200 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
202 case IB_GID_TYPE_ROCE_UDP_ENCAP:
203 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
210 if (attr->gid_type != IB_GID_TYPE_IB) {
211 if (ipv6_addr_v4mapped((void *)gid))
212 MLX5_SET_RA(mlx5_addr, roce_l3_type,
213 MLX5_ROCE_L3_TYPE_IPV4);
215 MLX5_SET_RA(mlx5_addr, roce_l3_type,
216 MLX5_ROCE_L3_TYPE_IPV6);
219 if ((attr->gid_type == IB_GID_TYPE_IB) ||
220 !ipv6_addr_v4mapped((void *)gid))
221 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
223 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
226 static int set_roce_addr(struct ib_device *device, u8 port_num,
228 const union ib_gid *gid,
229 const struct ib_gid_attr *attr)
231 struct mlx5_ib_dev *dev = to_mdev(device);
232 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)];
233 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)];
234 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
235 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
237 if (ll != IB_LINK_LAYER_ETHERNET)
240 memset(in, 0, sizeof(in));
242 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
244 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
245 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
247 memset(out, 0, sizeof(out));
248 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
251 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
252 unsigned int index, const union ib_gid *gid,
253 const struct ib_gid_attr *attr,
254 __always_unused void **context)
256 return set_roce_addr(device, port_num, index, gid, attr);
259 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
260 unsigned int index, __always_unused void **context)
262 return set_roce_addr(device, port_num, index, NULL, NULL);
265 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
268 struct ib_gid_attr attr;
271 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
279 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
282 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
285 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
287 return !dev->mdev->issi;
291 MLX5_VPORT_ACCESS_METHOD_MAD,
292 MLX5_VPORT_ACCESS_METHOD_HCA,
293 MLX5_VPORT_ACCESS_METHOD_NIC,
296 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
298 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
299 return MLX5_VPORT_ACCESS_METHOD_MAD;
301 if (mlx5_ib_port_link_layer(ibdev, 1) ==
302 IB_LINK_LAYER_ETHERNET)
303 return MLX5_VPORT_ACCESS_METHOD_NIC;
305 return MLX5_VPORT_ACCESS_METHOD_HCA;
308 static void get_atomic_caps(struct mlx5_ib_dev *dev,
309 struct ib_device_attr *props)
312 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
313 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
314 u8 atomic_req_8B_endianness_mode =
315 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
317 /* Check if HW supports 8 bytes standard atomic operations and capable
318 * of host endianness respond
320 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
321 if (((atomic_operations & tmp) == tmp) &&
322 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
323 (atomic_req_8B_endianness_mode)) {
324 props->atomic_cap = IB_ATOMIC_HCA;
326 props->atomic_cap = IB_ATOMIC_NONE;
330 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
331 __be64 *sys_image_guid)
333 struct mlx5_ib_dev *dev = to_mdev(ibdev);
334 struct mlx5_core_dev *mdev = dev->mdev;
338 switch (mlx5_get_vport_access_method(ibdev)) {
339 case MLX5_VPORT_ACCESS_METHOD_MAD:
340 return mlx5_query_mad_ifc_system_image_guid(ibdev,
343 case MLX5_VPORT_ACCESS_METHOD_HCA:
344 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
347 case MLX5_VPORT_ACCESS_METHOD_NIC:
348 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
356 *sys_image_guid = cpu_to_be64(tmp);
362 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
365 struct mlx5_ib_dev *dev = to_mdev(ibdev);
366 struct mlx5_core_dev *mdev = dev->mdev;
368 switch (mlx5_get_vport_access_method(ibdev)) {
369 case MLX5_VPORT_ACCESS_METHOD_MAD:
370 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
372 case MLX5_VPORT_ACCESS_METHOD_HCA:
373 case MLX5_VPORT_ACCESS_METHOD_NIC:
374 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
383 static int mlx5_query_vendor_id(struct ib_device *ibdev,
386 struct mlx5_ib_dev *dev = to_mdev(ibdev);
388 switch (mlx5_get_vport_access_method(ibdev)) {
389 case MLX5_VPORT_ACCESS_METHOD_MAD:
390 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
392 case MLX5_VPORT_ACCESS_METHOD_HCA:
393 case MLX5_VPORT_ACCESS_METHOD_NIC:
394 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
401 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
407 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
408 case MLX5_VPORT_ACCESS_METHOD_MAD:
409 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
411 case MLX5_VPORT_ACCESS_METHOD_HCA:
412 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
415 case MLX5_VPORT_ACCESS_METHOD_NIC:
416 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
424 *node_guid = cpu_to_be64(tmp);
429 struct mlx5_reg_node_desc {
433 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
435 struct mlx5_reg_node_desc in;
437 if (mlx5_use_mad_ifc(dev))
438 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
440 memset(&in, 0, sizeof(in));
442 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
443 sizeof(struct mlx5_reg_node_desc),
444 MLX5_REG_NODE_DESC, 0, 0);
447 static int mlx5_ib_query_device(struct ib_device *ibdev,
448 struct ib_device_attr *props,
449 struct ib_udata *uhw)
451 struct mlx5_ib_dev *dev = to_mdev(ibdev);
452 struct mlx5_core_dev *mdev = dev->mdev;
456 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
458 if (uhw->inlen || uhw->outlen)
461 memset(props, 0, sizeof(*props));
462 err = mlx5_query_system_image_guid(ibdev,
463 &props->sys_image_guid);
467 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
471 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
475 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
476 (fw_rev_min(dev->mdev) << 16) |
477 fw_rev_sub(dev->mdev);
478 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
479 IB_DEVICE_PORT_ACTIVE_EVENT |
480 IB_DEVICE_SYS_IMAGE_GUID |
481 IB_DEVICE_RC_RNR_NAK_GEN;
483 if (MLX5_CAP_GEN(mdev, pkv))
484 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
485 if (MLX5_CAP_GEN(mdev, qkv))
486 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
487 if (MLX5_CAP_GEN(mdev, apm))
488 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
489 if (MLX5_CAP_GEN(mdev, xrc))
490 props->device_cap_flags |= IB_DEVICE_XRC;
491 if (MLX5_CAP_GEN(mdev, imaicl)) {
492 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
493 IB_DEVICE_MEM_WINDOW_TYPE_2B;
494 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
495 /* We support 'Gappy' memory registration too */
496 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
498 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
499 if (MLX5_CAP_GEN(mdev, sho)) {
500 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
501 /* At this stage no support for signature handover */
502 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
503 IB_PROT_T10DIF_TYPE_2 |
504 IB_PROT_T10DIF_TYPE_3;
505 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
506 IB_GUARD_T10DIF_CSUM;
508 if (MLX5_CAP_GEN(mdev, block_lb_mc))
509 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
511 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
512 (MLX5_CAP_ETH(dev->mdev, csum_cap)))
513 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
515 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
516 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
517 props->device_cap_flags |= IB_DEVICE_UD_TSO;
520 props->vendor_part_id = mdev->pdev->device;
521 props->hw_ver = mdev->pdev->revision;
523 props->max_mr_size = ~0ull;
524 props->page_size_cap = ~(min_page_size - 1);
525 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
526 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
527 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
528 sizeof(struct mlx5_wqe_data_seg);
529 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
530 sizeof(struct mlx5_wqe_ctrl_seg)) /
531 sizeof(struct mlx5_wqe_data_seg);
532 props->max_sge = min(max_rq_sg, max_sq_sg);
533 props->max_sge_rd = props->max_sge;
534 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
535 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
536 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
537 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
538 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
539 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
540 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
541 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
542 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
543 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
544 props->max_srq_sge = max_rq_sg - 1;
545 props->max_fast_reg_page_list_len =
546 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
547 get_atomic_caps(dev, props);
548 props->masked_atomic_cap = IB_ATOMIC_NONE;
549 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
550 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
551 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
552 props->max_mcast_grp;
553 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
554 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
555 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
557 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
558 if (MLX5_CAP_GEN(mdev, pg))
559 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
560 props->odp_caps = dev->odp_caps;
563 if (MLX5_CAP_GEN(mdev, cd))
564 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
570 MLX5_IB_WIDTH_1X = 1 << 0,
571 MLX5_IB_WIDTH_2X = 1 << 1,
572 MLX5_IB_WIDTH_4X = 1 << 2,
573 MLX5_IB_WIDTH_8X = 1 << 3,
574 MLX5_IB_WIDTH_12X = 1 << 4
577 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
580 struct mlx5_ib_dev *dev = to_mdev(ibdev);
583 if (active_width & MLX5_IB_WIDTH_1X) {
584 *ib_width = IB_WIDTH_1X;
585 } else if (active_width & MLX5_IB_WIDTH_2X) {
586 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
589 } else if (active_width & MLX5_IB_WIDTH_4X) {
590 *ib_width = IB_WIDTH_4X;
591 } else if (active_width & MLX5_IB_WIDTH_8X) {
592 *ib_width = IB_WIDTH_8X;
593 } else if (active_width & MLX5_IB_WIDTH_12X) {
594 *ib_width = IB_WIDTH_12X;
596 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
604 static int mlx5_mtu_to_ib_mtu(int mtu)
613 pr_warn("invalid mtu\n");
623 __IB_MAX_VL_0_14 = 5,
626 enum mlx5_vl_hw_cap {
638 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
643 *max_vl_num = __IB_MAX_VL_0;
646 *max_vl_num = __IB_MAX_VL_0_1;
649 *max_vl_num = __IB_MAX_VL_0_3;
652 *max_vl_num = __IB_MAX_VL_0_7;
654 case MLX5_VL_HW_0_14:
655 *max_vl_num = __IB_MAX_VL_0_14;
665 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
666 struct ib_port_attr *props)
668 struct mlx5_ib_dev *dev = to_mdev(ibdev);
669 struct mlx5_core_dev *mdev = dev->mdev;
670 struct mlx5_hca_vport_context *rep;
674 u8 ib_link_width_oper;
677 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
683 memset(props, 0, sizeof(*props));
685 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
689 props->lid = rep->lid;
690 props->lmc = rep->lmc;
691 props->sm_lid = rep->sm_lid;
692 props->sm_sl = rep->sm_sl;
693 props->state = rep->vport_state;
694 props->phys_state = rep->port_physical_state;
695 props->port_cap_flags = rep->cap_mask1;
696 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
697 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
698 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
699 props->bad_pkey_cntr = rep->pkey_violation_counter;
700 props->qkey_viol_cntr = rep->qkey_violation_counter;
701 props->subnet_timeout = rep->subnet_timeout;
702 props->init_type_reply = rep->init_type_reply;
704 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
708 err = translate_active_width(ibdev, ib_link_width_oper,
709 &props->active_width);
712 err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
717 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
719 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
721 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
723 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
725 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
729 err = translate_max_vl_num(ibdev, vl_hw_cap,
736 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
737 struct ib_port_attr *props)
739 switch (mlx5_get_vport_access_method(ibdev)) {
740 case MLX5_VPORT_ACCESS_METHOD_MAD:
741 return mlx5_query_mad_ifc_port(ibdev, port, props);
743 case MLX5_VPORT_ACCESS_METHOD_HCA:
744 return mlx5_query_hca_port(ibdev, port, props);
746 case MLX5_VPORT_ACCESS_METHOD_NIC:
747 return mlx5_query_port_roce(ibdev, port, props);
754 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
757 struct mlx5_ib_dev *dev = to_mdev(ibdev);
758 struct mlx5_core_dev *mdev = dev->mdev;
760 switch (mlx5_get_vport_access_method(ibdev)) {
761 case MLX5_VPORT_ACCESS_METHOD_MAD:
762 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
764 case MLX5_VPORT_ACCESS_METHOD_HCA:
765 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
773 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
776 struct mlx5_ib_dev *dev = to_mdev(ibdev);
777 struct mlx5_core_dev *mdev = dev->mdev;
779 switch (mlx5_get_vport_access_method(ibdev)) {
780 case MLX5_VPORT_ACCESS_METHOD_MAD:
781 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
783 case MLX5_VPORT_ACCESS_METHOD_HCA:
784 case MLX5_VPORT_ACCESS_METHOD_NIC:
785 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
792 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
793 struct ib_device_modify *props)
795 struct mlx5_ib_dev *dev = to_mdev(ibdev);
796 struct mlx5_reg_node_desc in;
797 struct mlx5_reg_node_desc out;
800 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
803 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
807 * If possible, pass node desc to FW, so it can generate
808 * a 144 trap. If cmd fails, just ignore.
810 memcpy(&in, props->node_desc, 64);
811 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
812 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
816 memcpy(ibdev->node_desc, props->node_desc, 64);
821 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
822 struct ib_port_modify *props)
824 struct mlx5_ib_dev *dev = to_mdev(ibdev);
825 struct ib_port_attr attr;
829 mutex_lock(&dev->cap_mask_mutex);
831 err = mlx5_ib_query_port(ibdev, port, &attr);
835 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
836 ~props->clr_port_cap_mask;
838 err = mlx5_set_port_caps(dev->mdev, port, tmp);
841 mutex_unlock(&dev->cap_mask_mutex);
845 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
846 struct ib_udata *udata)
848 struct mlx5_ib_dev *dev = to_mdev(ibdev);
849 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
850 struct mlx5_ib_alloc_ucontext_resp resp = {};
851 struct mlx5_ib_ucontext *context;
852 struct mlx5_uuar_info *uuari;
853 struct mlx5_uar *uars;
861 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
865 return ERR_PTR(-EAGAIN);
867 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
868 return ERR_PTR(-EINVAL);
870 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
871 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
873 else if (reqlen >= min_req_v2)
876 return ERR_PTR(-EINVAL);
878 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
883 return ERR_PTR(-EINVAL);
885 if (req.total_num_uuars > MLX5_MAX_UUARS)
886 return ERR_PTR(-ENOMEM);
888 if (req.total_num_uuars == 0)
889 return ERR_PTR(-EINVAL);
891 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
892 return ERR_PTR(-EOPNOTSUPP);
894 if (reqlen > sizeof(req) &&
895 !ib_is_udata_cleared(udata, sizeof(req),
896 reqlen - sizeof(req)))
897 return ERR_PTR(-EOPNOTSUPP);
899 req.total_num_uuars = ALIGN(req.total_num_uuars,
900 MLX5_NON_FP_BF_REGS_PER_PAGE);
901 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
902 return ERR_PTR(-EINVAL);
904 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
905 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
906 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
907 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
908 resp.cache_line_size = L1_CACHE_BYTES;
909 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
910 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
911 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
912 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
913 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
914 resp.cqe_version = min_t(__u8,
915 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
916 req.max_cqe_version);
917 resp.response_length = min(offsetof(typeof(resp), response_length) +
918 sizeof(resp.response_length), udata->outlen);
920 context = kzalloc(sizeof(*context), GFP_KERNEL);
922 return ERR_PTR(-ENOMEM);
924 uuari = &context->uuari;
925 mutex_init(&uuari->lock);
926 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
932 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
933 sizeof(*uuari->bitmap),
935 if (!uuari->bitmap) {
940 * clear all fast path uuars
942 for (i = 0; i < gross_uuars; i++) {
944 if (uuarn == 2 || uuarn == 3)
945 set_bit(i, uuari->bitmap);
948 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
954 for (i = 0; i < num_uars; i++) {
955 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
960 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
961 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
964 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
965 err = mlx5_core_alloc_transport_domain(dev->mdev,
971 INIT_LIST_HEAD(&context->db_page_list);
972 mutex_init(&context->db_page_mutex);
974 resp.tot_uuars = req.total_num_uuars;
975 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
977 if (field_avail(typeof(resp), cqe_version, udata->outlen))
978 resp.response_length += sizeof(resp.cqe_version);
980 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
982 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
983 resp.hca_core_clock_offset =
984 offsetof(struct mlx5_init_seg, internal_timer_h) %
986 resp.response_length += sizeof(resp.hca_core_clock_offset) +
987 sizeof(resp.reserved2) +
988 sizeof(resp.reserved3);
991 err = ib_copy_to_udata(udata, &resp, resp.response_length);
996 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
998 uuari->num_uars = num_uars;
999 context->cqe_version = resp.cqe_version;
1001 return &context->ibucontext;
1004 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1005 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1008 for (i--; i >= 0; i--)
1009 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1011 kfree(uuari->count);
1014 kfree(uuari->bitmap);
1021 return ERR_PTR(err);
1024 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1026 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1027 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1028 struct mlx5_uuar_info *uuari = &context->uuari;
1031 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1032 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1034 for (i = 0; i < uuari->num_uars; i++) {
1035 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1036 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1039 kfree(uuari->count);
1040 kfree(uuari->bitmap);
1047 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1049 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1052 static int get_command(unsigned long offset)
1054 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1057 static int get_arg(unsigned long offset)
1059 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1062 static int get_index(unsigned long offset)
1064 return get_arg(offset);
1067 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1069 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1070 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1071 struct mlx5_uuar_info *uuari = &context->uuari;
1072 unsigned long command;
1076 command = get_command(vma->vm_pgoff);
1078 case MLX5_IB_MMAP_REGULAR_PAGE:
1079 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1082 idx = get_index(vma->vm_pgoff);
1083 if (idx >= uuari->num_uars)
1086 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1087 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
1088 (unsigned long long)pfn);
1090 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1091 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1092 PAGE_SIZE, vma->vm_page_prot))
1095 mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
1097 (unsigned long long)pfn << PAGE_SHIFT);
1100 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1103 case MLX5_IB_MMAP_CORE_CLOCK:
1104 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1107 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
1110 /* Don't expose to user-space information it shouldn't have */
1111 if (PAGE_SIZE > 4096)
1114 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1115 pfn = (dev->mdev->iseg_base +
1116 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1118 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1119 PAGE_SIZE, vma->vm_page_prot))
1122 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1124 (unsigned long long)pfn << PAGE_SHIFT);
1134 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1135 struct ib_ucontext *context,
1136 struct ib_udata *udata)
1138 struct mlx5_ib_alloc_pd_resp resp;
1139 struct mlx5_ib_pd *pd;
1142 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1144 return ERR_PTR(-ENOMEM);
1146 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1149 return ERR_PTR(err);
1154 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1155 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1157 return ERR_PTR(-EFAULT);
1164 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1166 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1167 struct mlx5_ib_pd *mpd = to_mpd(pd);
1169 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1175 static bool outer_header_zero(u32 *match_criteria)
1177 int size = MLX5_ST_SZ_BYTES(fte_match_param);
1178 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1181 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1182 outer_headers_c + 1,
1186 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1187 union ib_flow_spec *ib_spec)
1189 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1191 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1193 switch (ib_spec->type) {
1194 case IB_FLOW_SPEC_ETH:
1195 if (ib_spec->size != sizeof(ib_spec->eth))
1198 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1200 ib_spec->eth.mask.dst_mac);
1201 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1203 ib_spec->eth.val.dst_mac);
1205 if (ib_spec->eth.mask.vlan_tag) {
1206 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1208 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1211 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1212 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1213 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1214 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1216 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1218 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1219 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1221 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1223 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1225 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1226 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1228 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1230 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1231 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1232 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1233 ethertype, ntohs(ib_spec->eth.val.ether_type));
1235 case IB_FLOW_SPEC_IPV4:
1236 if (ib_spec->size != sizeof(ib_spec->ipv4))
1239 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1241 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1242 ethertype, ETH_P_IP);
1244 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1245 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1246 &ib_spec->ipv4.mask.src_ip,
1247 sizeof(ib_spec->ipv4.mask.src_ip));
1248 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1249 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1250 &ib_spec->ipv4.val.src_ip,
1251 sizeof(ib_spec->ipv4.val.src_ip));
1252 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1253 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1254 &ib_spec->ipv4.mask.dst_ip,
1255 sizeof(ib_spec->ipv4.mask.dst_ip));
1256 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1257 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1258 &ib_spec->ipv4.val.dst_ip,
1259 sizeof(ib_spec->ipv4.val.dst_ip));
1261 case IB_FLOW_SPEC_TCP:
1262 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1265 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1267 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1270 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1271 ntohs(ib_spec->tcp_udp.mask.src_port));
1272 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1273 ntohs(ib_spec->tcp_udp.val.src_port));
1275 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1276 ntohs(ib_spec->tcp_udp.mask.dst_port));
1277 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1278 ntohs(ib_spec->tcp_udp.val.dst_port));
1280 case IB_FLOW_SPEC_UDP:
1281 if (ib_spec->size != sizeof(ib_spec->tcp_udp))
1284 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1286 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1289 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1290 ntohs(ib_spec->tcp_udp.mask.src_port));
1291 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1292 ntohs(ib_spec->tcp_udp.val.src_port));
1294 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1295 ntohs(ib_spec->tcp_udp.mask.dst_port));
1296 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1297 ntohs(ib_spec->tcp_udp.val.dst_port));
1306 /* If a flow could catch both multicast and unicast packets,
1307 * it won't fall into the multicast flow steering table and this rule
1308 * could steal other multicast packets.
1310 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1312 struct ib_flow_spec_eth *eth_spec;
1314 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1315 ib_attr->size < sizeof(struct ib_flow_attr) +
1316 sizeof(struct ib_flow_spec_eth) ||
1317 ib_attr->num_of_specs < 1)
1320 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1321 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1322 eth_spec->size != sizeof(*eth_spec))
1325 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1326 is_multicast_ether_addr(eth_spec->val.dst_mac);
1329 static bool is_valid_attr(struct ib_flow_attr *flow_attr)
1331 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1332 bool has_ipv4_spec = false;
1333 bool eth_type_ipv4 = true;
1334 unsigned int spec_index;
1336 /* Validate that ethertype is correct */
1337 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1338 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1339 ib_spec->eth.mask.ether_type) {
1340 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1341 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1342 eth_type_ipv4 = false;
1343 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1344 has_ipv4_spec = true;
1346 ib_spec = (void *)ib_spec + ib_spec->size;
1348 return !has_ipv4_spec || eth_type_ipv4;
1351 static void put_flow_table(struct mlx5_ib_dev *dev,
1352 struct mlx5_ib_flow_prio *prio, bool ft_added)
1354 prio->refcount -= !!ft_added;
1355 if (!prio->refcount) {
1356 mlx5_destroy_flow_table(prio->flow_table);
1357 prio->flow_table = NULL;
1361 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1363 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1364 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1365 struct mlx5_ib_flow_handler,
1367 struct mlx5_ib_flow_handler *iter, *tmp;
1369 mutex_lock(&dev->flow_db.lock);
1371 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1372 mlx5_del_flow_rule(iter->rule);
1373 list_del(&iter->list);
1377 mlx5_del_flow_rule(handler->rule);
1378 put_flow_table(dev, &dev->flow_db.prios[handler->prio], true);
1379 mutex_unlock(&dev->flow_db.lock);
1386 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1394 #define MLX5_FS_MAX_TYPES 10
1395 #define MLX5_FS_MAX_ENTRIES 32000UL
1396 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1397 struct ib_flow_attr *flow_attr)
1399 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1400 struct mlx5_flow_namespace *ns = NULL;
1401 struct mlx5_ib_flow_prio *prio;
1402 struct mlx5_flow_table *ft;
1408 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1409 if (flow_is_multicast_only(flow_attr) &&
1411 priority = MLX5_IB_FLOW_MCAST_PRIO;
1413 priority = ib_prio_to_core_prio(flow_attr->priority,
1415 ns = mlx5_get_flow_namespace(dev->mdev,
1416 MLX5_FLOW_NAMESPACE_BYPASS);
1417 num_entries = MLX5_FS_MAX_ENTRIES;
1418 num_groups = MLX5_FS_MAX_TYPES;
1419 prio = &dev->flow_db.prios[priority];
1420 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1421 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1422 ns = mlx5_get_flow_namespace(dev->mdev,
1423 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1424 build_leftovers_ft_param(&priority,
1427 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1431 return ERR_PTR(-ENOTSUPP);
1433 ft = prio->flow_table;
1435 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1441 prio->flow_table = ft;
1447 return err ? ERR_PTR(err) : prio;
1450 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1451 struct mlx5_ib_flow_prio *ft_prio,
1452 struct ib_flow_attr *flow_attr,
1453 struct mlx5_flow_destination *dst)
1455 struct mlx5_flow_table *ft = ft_prio->flow_table;
1456 struct mlx5_ib_flow_handler *handler;
1457 void *ib_flow = flow_attr + 1;
1458 u8 match_criteria_enable = 0;
1459 unsigned int spec_index;
1465 if (!is_valid_attr(flow_attr))
1466 return ERR_PTR(-EINVAL);
1468 match_c = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1469 match_v = kzalloc(MLX5_ST_SZ_BYTES(fte_match_param), GFP_KERNEL);
1470 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1471 if (!handler || !match_c || !match_v) {
1476 INIT_LIST_HEAD(&handler->list);
1478 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1479 err = parse_flow_attr(match_c, match_v, ib_flow);
1483 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1486 /* Outer header support only */
1487 match_criteria_enable = (!outer_header_zero(match_c)) << 0;
1488 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1489 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1490 handler->rule = mlx5_add_flow_rule(ft, match_criteria_enable,
1493 MLX5_FS_DEFAULT_FLOW_TAG,
1496 if (IS_ERR(handler->rule)) {
1497 err = PTR_ERR(handler->rule);
1501 handler->prio = ft_prio - dev->flow_db.prios;
1503 ft_prio->flow_table = ft;
1509 return err ? ERR_PTR(err) : handler;
1512 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1513 struct mlx5_ib_flow_prio *ft_prio,
1514 struct ib_flow_attr *flow_attr,
1515 struct mlx5_flow_destination *dst)
1517 struct mlx5_ib_flow_handler *handler_dst = NULL;
1518 struct mlx5_ib_flow_handler *handler = NULL;
1520 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1521 if (!IS_ERR(handler)) {
1522 handler_dst = create_flow_rule(dev, ft_prio,
1524 if (IS_ERR(handler_dst)) {
1525 mlx5_del_flow_rule(handler->rule);
1527 handler = handler_dst;
1529 list_add(&handler_dst->list, &handler->list);
1540 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1541 struct mlx5_ib_flow_prio *ft_prio,
1542 struct ib_flow_attr *flow_attr,
1543 struct mlx5_flow_destination *dst)
1545 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1546 struct mlx5_ib_flow_handler *handler = NULL;
1549 struct ib_flow_attr flow_attr;
1550 struct ib_flow_spec_eth eth_flow;
1551 } leftovers_specs[] = {
1555 .size = sizeof(leftovers_specs[0])
1558 .type = IB_FLOW_SPEC_ETH,
1559 .size = sizeof(struct ib_flow_spec_eth),
1560 .mask = {.dst_mac = {0x1} },
1561 .val = {.dst_mac = {0x1} }
1567 .size = sizeof(leftovers_specs[0])
1570 .type = IB_FLOW_SPEC_ETH,
1571 .size = sizeof(struct ib_flow_spec_eth),
1572 .mask = {.dst_mac = {0x1} },
1573 .val = {.dst_mac = {} }
1578 handler = create_flow_rule(dev, ft_prio,
1579 &leftovers_specs[LEFTOVERS_MC].flow_attr,
1581 if (!IS_ERR(handler) &&
1582 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1583 handler_ucast = create_flow_rule(dev, ft_prio,
1584 &leftovers_specs[LEFTOVERS_UC].flow_attr,
1586 if (IS_ERR(handler_ucast)) {
1588 handler = handler_ucast;
1590 list_add(&handler_ucast->list, &handler->list);
1597 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1598 struct ib_flow_attr *flow_attr,
1601 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1602 struct mlx5_ib_flow_handler *handler = NULL;
1603 struct mlx5_flow_destination *dst = NULL;
1604 struct mlx5_ib_flow_prio *ft_prio;
1607 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1608 return ERR_PTR(-ENOSPC);
1610 if (domain != IB_FLOW_DOMAIN_USER ||
1611 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
1612 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
1613 return ERR_PTR(-EINVAL);
1615 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1617 return ERR_PTR(-ENOMEM);
1619 mutex_lock(&dev->flow_db.lock);
1621 ft_prio = get_flow_table(dev, flow_attr);
1622 if (IS_ERR(ft_prio)) {
1623 err = PTR_ERR(ft_prio);
1627 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1628 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1630 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1631 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
1632 handler = create_dont_trap_rule(dev, ft_prio,
1635 handler = create_flow_rule(dev, ft_prio, flow_attr,
1638 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1639 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1640 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
1647 if (IS_ERR(handler)) {
1648 err = PTR_ERR(handler);
1653 ft_prio->refcount++;
1654 mutex_unlock(&dev->flow_db.lock);
1657 return &handler->ibflow;
1660 put_flow_table(dev, ft_prio, false);
1662 mutex_unlock(&dev->flow_db.lock);
1665 return ERR_PTR(err);
1668 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1670 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1673 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
1675 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
1676 ibqp->qp_num, gid->raw);
1681 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1683 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1686 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
1688 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
1689 ibqp->qp_num, gid->raw);
1694 static int init_node_data(struct mlx5_ib_dev *dev)
1698 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
1702 dev->mdev->rev_id = dev->mdev->pdev->revision;
1704 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
1707 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
1710 struct mlx5_ib_dev *dev =
1711 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1713 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
1716 static ssize_t show_reg_pages(struct device *device,
1717 struct device_attribute *attr, char *buf)
1719 struct mlx5_ib_dev *dev =
1720 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1722 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
1725 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
1728 struct mlx5_ib_dev *dev =
1729 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1730 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
1733 static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
1736 struct mlx5_ib_dev *dev =
1737 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1738 return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
1739 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
1742 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
1745 struct mlx5_ib_dev *dev =
1746 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1747 return sprintf(buf, "%x\n", dev->mdev->rev_id);
1750 static ssize_t show_board(struct device *device, struct device_attribute *attr,
1753 struct mlx5_ib_dev *dev =
1754 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
1755 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
1756 dev->mdev->board_id);
1759 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
1760 static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
1761 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
1762 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
1763 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
1764 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
1766 static struct device_attribute *mlx5_class_attributes[] = {
1772 &dev_attr_reg_pages,
1775 static void pkey_change_handler(struct work_struct *work)
1777 struct mlx5_ib_port_resources *ports =
1778 container_of(work, struct mlx5_ib_port_resources,
1781 mutex_lock(&ports->devr->mutex);
1782 mlx5_ib_gsi_pkey_change(ports->gsi);
1783 mutex_unlock(&ports->devr->mutex);
1786 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
1787 enum mlx5_dev_event event, unsigned long param)
1789 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
1790 struct ib_event ibev;
1795 case MLX5_DEV_EVENT_SYS_ERROR:
1796 ibdev->ib_active = false;
1797 ibev.event = IB_EVENT_DEVICE_FATAL;
1800 case MLX5_DEV_EVENT_PORT_UP:
1801 ibev.event = IB_EVENT_PORT_ACTIVE;
1805 case MLX5_DEV_EVENT_PORT_DOWN:
1806 ibev.event = IB_EVENT_PORT_ERR;
1810 case MLX5_DEV_EVENT_PORT_INITIALIZED:
1811 /* not used by ULPs */
1814 case MLX5_DEV_EVENT_LID_CHANGE:
1815 ibev.event = IB_EVENT_LID_CHANGE;
1819 case MLX5_DEV_EVENT_PKEY_CHANGE:
1820 ibev.event = IB_EVENT_PKEY_CHANGE;
1823 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
1826 case MLX5_DEV_EVENT_GUID_CHANGE:
1827 ibev.event = IB_EVENT_GID_CHANGE;
1831 case MLX5_DEV_EVENT_CLIENT_REREG:
1832 ibev.event = IB_EVENT_CLIENT_REREGISTER;
1837 ibev.device = &ibdev->ib_dev;
1838 ibev.element.port_num = port;
1840 if (port < 1 || port > ibdev->num_ports) {
1841 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
1845 if (ibdev->ib_active)
1846 ib_dispatch_event(&ibev);
1849 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
1853 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
1854 mlx5_query_ext_port_caps(dev, port);
1857 static int get_port_caps(struct mlx5_ib_dev *dev)
1859 struct ib_device_attr *dprops = NULL;
1860 struct ib_port_attr *pprops = NULL;
1863 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
1865 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
1869 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
1873 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
1875 mlx5_ib_warn(dev, "query_device failed %d\n", err);
1879 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
1880 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
1882 mlx5_ib_warn(dev, "query_port %d failed %d\n",
1886 dev->mdev->port_caps[port - 1].pkey_table_len =
1888 dev->mdev->port_caps[port - 1].gid_table_len =
1889 pprops->gid_tbl_len;
1890 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
1891 dprops->max_pkeys, pprops->gid_tbl_len);
1901 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
1905 err = mlx5_mr_cache_cleanup(dev);
1907 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
1909 mlx5_ib_destroy_qp(dev->umrc.qp);
1910 ib_free_cq(dev->umrc.cq);
1911 ib_dealloc_pd(dev->umrc.pd);
1918 static int create_umr_res(struct mlx5_ib_dev *dev)
1920 struct ib_qp_init_attr *init_attr = NULL;
1921 struct ib_qp_attr *attr = NULL;
1927 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
1928 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
1929 if (!attr || !init_attr) {
1934 pd = ib_alloc_pd(&dev->ib_dev);
1936 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
1941 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
1943 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
1948 init_attr->send_cq = cq;
1949 init_attr->recv_cq = cq;
1950 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
1951 init_attr->cap.max_send_wr = MAX_UMR_WR;
1952 init_attr->cap.max_send_sge = 1;
1953 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
1954 init_attr->port_num = 1;
1955 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
1957 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
1961 qp->device = &dev->ib_dev;
1964 qp->qp_type = MLX5_IB_QPT_REG_UMR;
1966 attr->qp_state = IB_QPS_INIT;
1968 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
1971 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
1975 memset(attr, 0, sizeof(*attr));
1976 attr->qp_state = IB_QPS_RTR;
1977 attr->path_mtu = IB_MTU_256;
1979 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1981 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
1985 memset(attr, 0, sizeof(*attr));
1986 attr->qp_state = IB_QPS_RTS;
1987 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
1989 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
1997 sema_init(&dev->umrc.sem, MAX_UMR_WR);
1998 ret = mlx5_mr_cache_init(dev);
2000 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2010 mlx5_ib_destroy_qp(qp);
2024 static int create_dev_resources(struct mlx5_ib_resources *devr)
2026 struct ib_srq_init_attr attr;
2027 struct mlx5_ib_dev *dev;
2028 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2032 dev = container_of(devr, struct mlx5_ib_dev, devr);
2034 mutex_init(&devr->mutex);
2036 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2037 if (IS_ERR(devr->p0)) {
2038 ret = PTR_ERR(devr->p0);
2041 devr->p0->device = &dev->ib_dev;
2042 devr->p0->uobject = NULL;
2043 atomic_set(&devr->p0->usecnt, 0);
2045 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2046 if (IS_ERR(devr->c0)) {
2047 ret = PTR_ERR(devr->c0);
2050 devr->c0->device = &dev->ib_dev;
2051 devr->c0->uobject = NULL;
2052 devr->c0->comp_handler = NULL;
2053 devr->c0->event_handler = NULL;
2054 devr->c0->cq_context = NULL;
2055 atomic_set(&devr->c0->usecnt, 0);
2057 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2058 if (IS_ERR(devr->x0)) {
2059 ret = PTR_ERR(devr->x0);
2062 devr->x0->device = &dev->ib_dev;
2063 devr->x0->inode = NULL;
2064 atomic_set(&devr->x0->usecnt, 0);
2065 mutex_init(&devr->x0->tgt_qp_mutex);
2066 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2068 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2069 if (IS_ERR(devr->x1)) {
2070 ret = PTR_ERR(devr->x1);
2073 devr->x1->device = &dev->ib_dev;
2074 devr->x1->inode = NULL;
2075 atomic_set(&devr->x1->usecnt, 0);
2076 mutex_init(&devr->x1->tgt_qp_mutex);
2077 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2079 memset(&attr, 0, sizeof(attr));
2080 attr.attr.max_sge = 1;
2081 attr.attr.max_wr = 1;
2082 attr.srq_type = IB_SRQT_XRC;
2083 attr.ext.xrc.cq = devr->c0;
2084 attr.ext.xrc.xrcd = devr->x0;
2086 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2087 if (IS_ERR(devr->s0)) {
2088 ret = PTR_ERR(devr->s0);
2091 devr->s0->device = &dev->ib_dev;
2092 devr->s0->pd = devr->p0;
2093 devr->s0->uobject = NULL;
2094 devr->s0->event_handler = NULL;
2095 devr->s0->srq_context = NULL;
2096 devr->s0->srq_type = IB_SRQT_XRC;
2097 devr->s0->ext.xrc.xrcd = devr->x0;
2098 devr->s0->ext.xrc.cq = devr->c0;
2099 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2100 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2101 atomic_inc(&devr->p0->usecnt);
2102 atomic_set(&devr->s0->usecnt, 0);
2104 memset(&attr, 0, sizeof(attr));
2105 attr.attr.max_sge = 1;
2106 attr.attr.max_wr = 1;
2107 attr.srq_type = IB_SRQT_BASIC;
2108 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2109 if (IS_ERR(devr->s1)) {
2110 ret = PTR_ERR(devr->s1);
2113 devr->s1->device = &dev->ib_dev;
2114 devr->s1->pd = devr->p0;
2115 devr->s1->uobject = NULL;
2116 devr->s1->event_handler = NULL;
2117 devr->s1->srq_context = NULL;
2118 devr->s1->srq_type = IB_SRQT_BASIC;
2119 devr->s1->ext.xrc.cq = devr->c0;
2120 atomic_inc(&devr->p0->usecnt);
2121 atomic_set(&devr->s0->usecnt, 0);
2123 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2124 INIT_WORK(&devr->ports[port].pkey_change_work,
2125 pkey_change_handler);
2126 devr->ports[port].devr = devr;
2132 mlx5_ib_destroy_srq(devr->s0);
2134 mlx5_ib_dealloc_xrcd(devr->x1);
2136 mlx5_ib_dealloc_xrcd(devr->x0);
2138 mlx5_ib_destroy_cq(devr->c0);
2140 mlx5_ib_dealloc_pd(devr->p0);
2145 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2147 struct mlx5_ib_dev *dev =
2148 container_of(devr, struct mlx5_ib_dev, devr);
2151 mlx5_ib_destroy_srq(devr->s1);
2152 mlx5_ib_destroy_srq(devr->s0);
2153 mlx5_ib_dealloc_xrcd(devr->x0);
2154 mlx5_ib_dealloc_xrcd(devr->x1);
2155 mlx5_ib_destroy_cq(devr->c0);
2156 mlx5_ib_dealloc_pd(devr->p0);
2158 /* Make sure no change P_Key work items are still executing */
2159 for (port = 0; port < dev->num_ports; ++port)
2160 cancel_work_sync(&devr->ports[port].pkey_change_work);
2163 static u32 get_core_cap_flags(struct ib_device *ibdev)
2165 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2166 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2167 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2168 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2171 if (ll == IB_LINK_LAYER_INFINIBAND)
2172 return RDMA_CORE_PORT_IBA_IB;
2174 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2177 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2180 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2181 ret |= RDMA_CORE_PORT_IBA_ROCE;
2183 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2184 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2189 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2190 struct ib_port_immutable *immutable)
2192 struct ib_port_attr attr;
2195 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2199 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2200 immutable->gid_tbl_len = attr.gid_tbl_len;
2201 immutable->core_cap_flags = get_core_cap_flags(ibdev);
2202 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2207 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2211 dev->roce.nb.notifier_call = mlx5_netdev_event;
2212 err = register_netdevice_notifier(&dev->roce.nb);
2216 err = mlx5_nic_vport_enable_roce(dev->mdev);
2218 goto err_unregister_netdevice_notifier;
2222 err_unregister_netdevice_notifier:
2223 unregister_netdevice_notifier(&dev->roce.nb);
2227 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2229 mlx5_nic_vport_disable_roce(dev->mdev);
2230 unregister_netdevice_notifier(&dev->roce.nb);
2233 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2235 struct mlx5_ib_dev *dev;
2236 enum rdma_link_layer ll;
2241 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2242 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2244 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2247 printk_once(KERN_INFO "%s", mlx5_version);
2249 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2255 rwlock_init(&dev->roce.netdev_lock);
2256 err = get_port_caps(dev);
2260 if (mlx5_use_mad_ifc(dev))
2261 get_ext_port_caps(dev);
2263 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2265 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2266 dev->ib_dev.owner = THIS_MODULE;
2267 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
2268 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
2269 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
2270 dev->ib_dev.phys_port_cnt = dev->num_ports;
2271 dev->ib_dev.num_comp_vectors =
2272 dev->mdev->priv.eq_table.num_comp_vectors;
2273 dev->ib_dev.dma_device = &mdev->pdev->dev;
2275 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2276 dev->ib_dev.uverbs_cmd_mask =
2277 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2278 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2279 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2280 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2281 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2282 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2283 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2284 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2285 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2286 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2287 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2288 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2289 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2290 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2291 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2292 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2293 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2294 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2295 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2296 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2297 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2298 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2299 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2300 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2301 dev->ib_dev.uverbs_ex_cmd_mask =
2302 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2303 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2304 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2306 dev->ib_dev.query_device = mlx5_ib_query_device;
2307 dev->ib_dev.query_port = mlx5_ib_query_port;
2308 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
2309 if (ll == IB_LINK_LAYER_ETHERNET)
2310 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
2311 dev->ib_dev.query_gid = mlx5_ib_query_gid;
2312 dev->ib_dev.add_gid = mlx5_ib_add_gid;
2313 dev->ib_dev.del_gid = mlx5_ib_del_gid;
2314 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
2315 dev->ib_dev.modify_device = mlx5_ib_modify_device;
2316 dev->ib_dev.modify_port = mlx5_ib_modify_port;
2317 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
2318 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
2319 dev->ib_dev.mmap = mlx5_ib_mmap;
2320 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
2321 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
2322 dev->ib_dev.create_ah = mlx5_ib_create_ah;
2323 dev->ib_dev.query_ah = mlx5_ib_query_ah;
2324 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
2325 dev->ib_dev.create_srq = mlx5_ib_create_srq;
2326 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
2327 dev->ib_dev.query_srq = mlx5_ib_query_srq;
2328 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
2329 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
2330 dev->ib_dev.create_qp = mlx5_ib_create_qp;
2331 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
2332 dev->ib_dev.query_qp = mlx5_ib_query_qp;
2333 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
2334 dev->ib_dev.post_send = mlx5_ib_post_send;
2335 dev->ib_dev.post_recv = mlx5_ib_post_recv;
2336 dev->ib_dev.create_cq = mlx5_ib_create_cq;
2337 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
2338 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
2339 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
2340 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
2341 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
2342 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
2343 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
2344 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
2345 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
2346 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
2347 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
2348 dev->ib_dev.process_mad = mlx5_ib_process_mad;
2349 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
2350 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
2351 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
2352 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
2354 mlx5_ib_internal_fill_odp_caps(dev);
2356 if (MLX5_CAP_GEN(mdev, imaicl)) {
2357 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
2358 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
2359 dev->ib_dev.uverbs_cmd_mask |=
2360 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2361 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2364 if (MLX5_CAP_GEN(mdev, xrc)) {
2365 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2366 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2367 dev->ib_dev.uverbs_cmd_mask |=
2368 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2369 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2372 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
2373 IB_LINK_LAYER_ETHERNET) {
2374 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2375 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
2376 dev->ib_dev.uverbs_ex_cmd_mask |=
2377 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2378 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2380 err = init_node_data(dev);
2384 mutex_init(&dev->flow_db.lock);
2385 mutex_init(&dev->cap_mask_mutex);
2387 if (ll == IB_LINK_LAYER_ETHERNET) {
2388 err = mlx5_enable_roce(dev);
2393 err = create_dev_resources(&dev->devr);
2395 goto err_disable_roce;
2397 err = mlx5_ib_odp_init_one(dev);
2401 err = ib_register_device(&dev->ib_dev, NULL);
2405 err = create_umr_res(dev);
2409 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
2410 err = device_create_file(&dev->ib_dev.dev,
2411 mlx5_class_attributes[i]);
2416 dev->ib_active = true;
2421 destroy_umrc_res(dev);
2424 ib_unregister_device(&dev->ib_dev);
2427 mlx5_ib_odp_remove_one(dev);
2430 destroy_dev_resources(&dev->devr);
2433 if (ll == IB_LINK_LAYER_ETHERNET)
2434 mlx5_disable_roce(dev);
2437 ib_dealloc_device((struct ib_device *)dev);
2442 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
2444 struct mlx5_ib_dev *dev = context;
2445 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
2447 ib_unregister_device(&dev->ib_dev);
2448 destroy_umrc_res(dev);
2449 mlx5_ib_odp_remove_one(dev);
2450 destroy_dev_resources(&dev->devr);
2451 if (ll == IB_LINK_LAYER_ETHERNET)
2452 mlx5_disable_roce(dev);
2453 ib_dealloc_device(&dev->ib_dev);
2456 static struct mlx5_interface mlx5_ib_interface = {
2458 .remove = mlx5_ib_remove,
2459 .event = mlx5_ib_event,
2460 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
2463 static int __init mlx5_ib_init(void)
2467 if (deprecated_prof_sel != 2)
2468 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
2470 err = mlx5_ib_odp_init();
2474 err = mlx5_register_interface(&mlx5_ib_interface);
2481 mlx5_ib_odp_cleanup();
2485 static void __exit mlx5_ib_cleanup(void)
2487 mlx5_unregister_interface(&mlx5_ib_interface);
2488 mlx5_ib_odp_cleanup();
2491 module_init(mlx5_ib_init);
2492 module_exit(mlx5_ib_cleanup);