drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <linux/bitmap.h>
  42 #if defined(CONFIG_X86)
  43 #include <asm/pat.h>
  44 #endif
  45 #include <linux/sched.h>
  46 #include <linux/sched/mm.h>
  47 #include <linux/sched/task.h>
  48 #include <linux/delay.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <rdma/ib_addr.h>
  51 #include <rdma/ib_cache.h>
  52 #include <linux/mlx5/port.h>
  53 #include <linux/mlx5/vport.h>
  54 #include <linux/mlx5/fs.h>
  55 #include <linux/mlx5/fs_helpers.h>
  56 #include <linux/list.h>
  57 #include <rdma/ib_smi.h>
  58 #include <rdma/ib_umem.h>
  59 #include <linux/in.h>
  60 #include <linux/etherdevice.h>
  61 #include "mlx5_ib.h"
  62 #include "ib_rep.h"
  63 #include "cmd.h"
  64 #include <linux/mlx5/fs_helpers.h>
  65 #include <linux/mlx5/accel.h>
  66 #include <rdma/uverbs_std_types.h>
  67 #include <rdma/mlx5_user_ioctl_verbs.h>
  68 #include <rdma/mlx5_user_ioctl_cmds.h>
  69
  70 #define UVERBS_MODULE_NAME mlx5_ib
  71 #include <rdma/uverbs_named_ioctl.h>
  72
  73 #define DRIVER_NAME "mlx5_ib"
  74 #define DRIVER_VERSION "5.0-0"
  75
  76 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  77 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  78 MODULE_LICENSE("Dual BSD/GPL");
  79
  80 static char mlx5_version[] =
  81         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  82         DRIVER_VERSION "\n";
  83
  84 struct mlx5_ib_event_work {
  85         struct work_struct      work;
  86         struct mlx5_core_dev    *dev;
  87         void                    *context;
  88         enum mlx5_dev_event     event;
  89         unsigned long           param;
  90 };
  91
  92 enum {
  93         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  94 };
  95
  96 static struct workqueue_struct *mlx5_ib_event_wq;
  97 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  98 static LIST_HEAD(mlx5_ib_dev_list);
  99 /*
 100  * This mutex should be held when accessing either of the above lists
 101  */
 102 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
 103
 104 /* We can't use an array for xlt_emergency_page because dma_map_single
 105  * doesn't work on kernel modules memory
 106  */
 107 static unsigned long xlt_emergency_page;
 108 static struct mutex xlt_emergency_page_mutex;
 109
 110 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
 111 {
 112         struct mlx5_ib_dev *dev;
 113
 114         mutex_lock(&mlx5_ib_multiport_mutex);
 115         dev = mpi->ibdev;
 116         mutex_unlock(&mlx5_ib_multiport_mutex);
 117         return dev;
 118 }
 119
 120 static enum rdma_link_layer
 121 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 122 {
 123         switch (port_type_cap) {
 124         case MLX5_CAP_PORT_TYPE_IB:
 125                 return IB_LINK_LAYER_INFINIBAND;
 126         case MLX5_CAP_PORT_TYPE_ETH:
 127                 return IB_LINK_LAYER_ETHERNET;
 128         default:
 129                 return IB_LINK_LAYER_UNSPECIFIED;
 130         }
 131 }
 132
 133 static enum rdma_link_layer
 134 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 135 {
 136         struct mlx5_ib_dev *dev = to_mdev(device);
 137         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 138
 139         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 140 }
 141
 142 static int get_port_state(struct ib_device *ibdev,
 143                           u8 port_num,
 144                           enum ib_port_state *state)
 145 {
 146         struct ib_port_attr attr;
 147         int ret;
 148
 149         memset(&attr, 0, sizeof(attr));
 150         ret = ibdev->query_port(ibdev, port_num, &attr);
 151         if (!ret)
 152                 *state = attr.state;
 153         return ret;
 154 }
 155
 156 static int mlx5_netdev_event(struct notifier_block *this,
 157                              unsigned long event, void *ptr)
 158 {
 159         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 160         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 161         u8 port_num = roce->native_port_num;
 162         struct mlx5_core_dev *mdev;
 163         struct mlx5_ib_dev *ibdev;
 164
 165         ibdev = roce->dev;
 166         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 167         if (!mdev)
 168                 return NOTIFY_DONE;
 169
 170         switch (event) {
 171         case NETDEV_REGISTER:
 172         case NETDEV_UNREGISTER:
 173                 write_lock(&roce->netdev_lock);
 174                 if (ibdev->rep) {
 175                         struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
 176                         struct net_device *rep_ndev;
 177
 178                         rep_ndev = mlx5_ib_get_rep_netdev(esw,
 179                                                           ibdev->rep->vport);
 180                         if (rep_ndev == ndev)
 181                                 roce->netdev = (event == NETDEV_UNREGISTER) ?
 182                                         NULL : ndev;
 183                 } else if (ndev->dev.parent == &ibdev->mdev->pdev->dev) {
 184                         roce->netdev = (event == NETDEV_UNREGISTER) ?
 185                                 NULL : ndev;
 186                 }
 187                 write_unlock(&roce->netdev_lock);
 188                 break;
 189
 190         case NETDEV_CHANGE:
 191         case NETDEV_UP:
 192         case NETDEV_DOWN: {
 193                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 194                 struct net_device *upper = NULL;
 195
 196                 if (lag_ndev) {
 197                         upper = netdev_master_upper_dev_get(lag_ndev);
 198                         dev_put(lag_ndev);
 199                 }
 200
 201                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 202                     && ibdev->ib_active) {
 203                         struct ib_event ibev = { };
 204                         enum ib_port_state port_state;
 205
 206                         if (get_port_state(&ibdev->ib_dev, port_num,
 207                                            &port_state))
 208                                 goto done;
 209
 210                         if (roce->last_port_state == port_state)
 211                                 goto done;
 212
 213                         roce->last_port_state = port_state;
 214                         ibev.device = &ibdev->ib_dev;
 215                         if (port_state == IB_PORT_DOWN)
 216                                 ibev.event = IB_EVENT_PORT_ERR;
 217                         else if (port_state == IB_PORT_ACTIVE)
 218                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 219                         else
 220                                 goto done;
 221
 222                         ibev.element.port_num = port_num;
 223                         ib_dispatch_event(&ibev);
 224                 }
 225                 break;
 226         }
 227
 228         default:
 229                 break;
 230         }
 231 done:
 232         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 233         return NOTIFY_DONE;
 234 }
 235
 236 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 237                                              u8 port_num)
 238 {
 239         struct mlx5_ib_dev *ibdev = to_mdev(device);
 240         struct net_device *ndev;
 241         struct mlx5_core_dev *mdev;
 242
 243         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 244         if (!mdev)
 245                 return NULL;
 246
 247         ndev = mlx5_lag_get_roce_netdev(mdev);
 248         if (ndev)
 249                 goto out;
 250
 251         /* Ensure ndev does not disappear before we invoke dev_hold()
 252          */
 253         read_lock(&ibdev->roce[port_num - 1].netdev_lock);
 254         ndev = ibdev->roce[port_num - 1].netdev;
 255         if (ndev)
 256                 dev_hold(ndev);
 257         read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
 258
 259 out:
 260         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 261         return ndev;
 262 }
 263
 264 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 265                                                    u8 ib_port_num,
 266                                                    u8 *native_port_num)
 267 {
 268         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 269                                                           ib_port_num);
 270         struct mlx5_core_dev *mdev = NULL;
 271         struct mlx5_ib_multiport_info *mpi;
 272         struct mlx5_ib_port *port;
 273
 274         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 275             ll != IB_LINK_LAYER_ETHERNET) {
 276                 if (native_port_num)
 277                         *native_port_num = ib_port_num;
 278                 return ibdev->mdev;
 279         }
 280
 281         if (native_port_num)
 282                 *native_port_num = 1;
 283
 284         port = &ibdev->port[ib_port_num - 1];
 285         if (!port)
 286                 return NULL;
 287
 288         spin_lock(&port->mp.mpi_lock);
 289         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 290         if (mpi && !mpi->unaffiliate) {
 291                 mdev = mpi->mdev;
 292                 /* If it's the master no need to refcount, it'll exist
 293                  * as long as the ib_dev exists.
 294                  */
 295                 if (!mpi->is_master)
 296                         mpi->mdev_refcnt++;
 297         }
 298         spin_unlock(&port->mp.mpi_lock);
 299
 300         return mdev;
 301 }
 302
 303 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 304 {
 305         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 306                                                           port_num);
 307         struct mlx5_ib_multiport_info *mpi;
 308         struct mlx5_ib_port *port;
 309
 310         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 311                 return;
 312
 313         port = &ibdev->port[port_num - 1];
 314
 315         spin_lock(&port->mp.mpi_lock);
 316         mpi = ibdev->port[port_num - 1].mp.mpi;
 317         if (mpi->is_master)
 318                 goto out;
 319
 320         mpi->mdev_refcnt--;
 321         if (mpi->unaffiliate)
 322                 complete(&mpi->unref_comp);
 323 out:
 324         spin_unlock(&port->mp.mpi_lock);
 325 }
 326
 327 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 328                                     u8 *active_width)
 329 {
 330         switch (eth_proto_oper) {
 331         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 332         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 333         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 334         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 335                 *active_width = IB_WIDTH_1X;
 336                 *active_speed = IB_SPEED_SDR;
 337                 break;
 338         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 339         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 340         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 341         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 342         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 343         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 344         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 345                 *active_width = IB_WIDTH_1X;
 346                 *active_speed = IB_SPEED_QDR;
 347                 break;
 348         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 349         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 350         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 351                 *active_width = IB_WIDTH_1X;
 352                 *active_speed = IB_SPEED_EDR;
 353                 break;
 354         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 355         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 356         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 357         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 358                 *active_width = IB_WIDTH_4X;
 359                 *active_speed = IB_SPEED_QDR;
 360                 break;
 361         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 362         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 363         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 364                 *active_width = IB_WIDTH_1X;
 365                 *active_speed = IB_SPEED_HDR;
 366                 break;
 367         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 368                 *active_width = IB_WIDTH_4X;
 369                 *active_speed = IB_SPEED_FDR;
 370                 break;
 371         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 372         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 373         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 374         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 375                 *active_width = IB_WIDTH_4X;
 376                 *active_speed = IB_SPEED_EDR;
 377                 break;
 378         default:
 379                 return -EINVAL;
 380         }
 381
 382         return 0;
 383 }
 384
 385 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 386                                 struct ib_port_attr *props)
 387 {
 388         struct mlx5_ib_dev *dev = to_mdev(device);
 389         struct mlx5_core_dev *mdev;
 390         struct net_device *ndev, *upper;
 391         enum ib_mtu ndev_ib_mtu;
 392         bool put_mdev = true;
 393         u16 qkey_viol_cntr;
 394         u32 eth_prot_oper;
 395         u8 mdev_port_num;
 396         int err;
 397
 398         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 399         if (!mdev) {
 400                 /* This means the port isn't affiliated yet. Get the
 401                  * info for the master port instead.
 402                  */
 403                 put_mdev = false;
 404                 mdev = dev->mdev;
 405                 mdev_port_num = 1;
 406                 port_num = 1;
 407         }
 408
 409         /* Possible bad flows are checked before filling out props so in case
 410          * of an error it will still be zeroed out.
 411          */
 412         err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
 413                                              mdev_port_num);
 414         if (err)
 415                 goto out;
 416
 417         props->active_width     = IB_WIDTH_4X;
 418         props->active_speed     = IB_SPEED_QDR;
 419
 420         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 421                                  &props->active_width);
 422
 423         props->port_cap_flags  |= IB_PORT_CM_SUP;
 424         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 425
 426         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 427                                                 roce_address_table_size);
 428         props->max_mtu          = IB_MTU_4096;
 429         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 430         props->pkey_tbl_len     = 1;
 431         props->state            = IB_PORT_DOWN;
 432         props->phys_state       = 3;
 433
 434         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 435         props->qkey_viol_cntr = qkey_viol_cntr;
 436
 437         /* If this is a stub query for an unaffiliated port stop here */
 438         if (!put_mdev)
 439                 goto out;
 440
 441         ndev = mlx5_ib_get_netdev(device, port_num);
 442         if (!ndev)
 443                 goto out;
 444
 445         if (mlx5_lag_is_active(dev->mdev)) {
 446                 rcu_read_lock();
 447                 upper = netdev_master_upper_dev_get_rcu(ndev);
 448                 if (upper) {
 449                         dev_put(ndev);
 450                         ndev = upper;
 451                         dev_hold(ndev);
 452                 }
 453                 rcu_read_unlock();
 454         }
 455
 456         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 457                 props->state      = IB_PORT_ACTIVE;
 458                 props->phys_state = 5;
 459         }
 460
 461         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 462
 463         dev_put(ndev);
 464
 465         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 466 out:
 467         if (put_mdev)
 468                 mlx5_ib_put_native_port_mdev(dev, port_num);
 469         return err;
 470 }
 471
 472 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 473                          unsigned int index, const union ib_gid *gid,
 474                          const struct ib_gid_attr *attr)
 475 {
 476         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 477         u8 roce_version = 0;
 478         u8 roce_l3_type = 0;
 479         bool vlan = false;
 480         u8 mac[ETH_ALEN];
 481         u16 vlan_id = 0;
 482
 483         if (gid) {
 484                 gid_type = attr->gid_type;
 485                 ether_addr_copy(mac, attr->ndev->dev_addr);
 486
 487                 if (is_vlan_dev(attr->ndev)) {
 488                         vlan = true;
 489                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 490                 }
 491         }
 492
 493         switch (gid_type) {
 494         case IB_GID_TYPE_IB:
 495                 roce_version = MLX5_ROCE_VERSION_1;
 496                 break;
 497         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 498                 roce_version = MLX5_ROCE_VERSION_2;
 499                 if (ipv6_addr_v4mapped((void *)gid))
 500                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 501                 else
 502                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 503                 break;
 504
 505         default:
 506                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 507         }
 508
 509         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 510                                       roce_l3_type, gid->raw, mac, vlan,
 511                                       vlan_id, port_num);
 512 }
 513
 514 static int mlx5_ib_add_gid(const union ib_gid *gid,
 515                            const struct ib_gid_attr *attr,
 516                            __always_unused void **context)
 517 {
 518         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 519                              attr->index, gid, attr);
 520 }
 521
 522 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 523                            __always_unused void **context)
 524 {
 525         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 526                              attr->index, NULL, NULL);
 527 }
 528
 529 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 530                                int index)
 531 {
 532         struct ib_gid_attr attr;
 533         union ib_gid gid;
 534
 535         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 536                 return 0;
 537
 538         dev_put(attr.ndev);
 539
 540         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 541                 return 0;
 542
 543         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 544 }
 545
 546 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
 547                            int index, enum ib_gid_type *gid_type)
 548 {
 549         struct ib_gid_attr attr;
 550         union ib_gid gid;
 551         int ret;
 552
 553         ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
 554         if (ret)
 555                 return ret;
 556
 557         dev_put(attr.ndev);
 558
 559         *gid_type = attr.gid_type;
 560
 561         return 0;
 562 }
 563
 564 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 565 {
 566         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 567                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 568         return 0;
 569 }
 570
 571 enum {
 572         MLX5_VPORT_ACCESS_METHOD_MAD,
 573         MLX5_VPORT_ACCESS_METHOD_HCA,
 574         MLX5_VPORT_ACCESS_METHOD_NIC,
 575 };
 576
 577 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 578 {
 579         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 580                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 581
 582         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 583             IB_LINK_LAYER_ETHERNET)
 584                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 585
 586         return MLX5_VPORT_ACCESS_METHOD_HCA;
 587 }
 588
 589 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 590                             u8 atomic_size_qp,
 591                             struct ib_device_attr *props)
 592 {
 593         u8 tmp;
 594         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 595         u8 atomic_req_8B_endianness_mode =
 596                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 597
 598         /* Check if HW supports 8 bytes standard atomic operations and capable
 599          * of host endianness respond
 600          */
 601         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 602         if (((atomic_operations & tmp) == tmp) &&
 603             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 604             (atomic_req_8B_endianness_mode)) {
 605                 props->atomic_cap = IB_ATOMIC_HCA;
 606         } else {
 607                 props->atomic_cap = IB_ATOMIC_NONE;
 608         }
 609 }
 610
 611 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 612                                struct ib_device_attr *props)
 613 {
 614         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 615
 616         get_atomic_caps(dev, atomic_size_qp, props);
 617 }
 618
 619 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 620                                struct ib_device_attr *props)
 621 {
 622         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 623
 624         get_atomic_caps(dev, atomic_size_qp, props);
 625 }
 626
 627 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 628 {
 629         struct ib_device_attr props = {};
 630
 631         get_atomic_caps_dc(dev, &props);
 632         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 633 }
 634 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 635                                         __be64 *sys_image_guid)
 636 {
 637         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 638         struct mlx5_core_dev *mdev = dev->mdev;
 639         u64 tmp;
 640         int err;
 641
 642         switch (mlx5_get_vport_access_method(ibdev)) {
 643         case MLX5_VPORT_ACCESS_METHOD_MAD:
 644                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 645                                                             sys_image_guid);
 646
 647         case MLX5_VPORT_ACCESS_METHOD_HCA:
 648                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 649                 break;
 650
 651         case MLX5_VPORT_ACCESS_METHOD_NIC:
 652                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 653                 break;
 654
 655         default:
 656                 return -EINVAL;
 657         }
 658
 659         if (!err)
 660                 *sys_image_guid = cpu_to_be64(tmp);
 661
 662         return err;
 663
 664 }
 665
 666 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 667                                 u16 *max_pkeys)
 668 {
 669         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 670         struct mlx5_core_dev *mdev = dev->mdev;
 671
 672         switch (mlx5_get_vport_access_method(ibdev)) {
 673         case MLX5_VPORT_ACCESS_METHOD_MAD:
 674                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 675
 676         case MLX5_VPORT_ACCESS_METHOD_HCA:
 677         case MLX5_VPORT_ACCESS_METHOD_NIC:
 678                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 679                                                 pkey_table_size));
 680                 return 0;
 681
 682         default:
 683                 return -EINVAL;
 684         }
 685 }
 686
 687 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 688                                 u32 *vendor_id)
 689 {
 690         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 691
 692         switch (mlx5_get_vport_access_method(ibdev)) {
 693         case MLX5_VPORT_ACCESS_METHOD_MAD:
 694                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 695
 696         case MLX5_VPORT_ACCESS_METHOD_HCA:
 697         case MLX5_VPORT_ACCESS_METHOD_NIC:
 698                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 699
 700         default:
 701                 return -EINVAL;
 702         }
 703 }
 704
 705 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 706                                 __be64 *node_guid)
 707 {
 708         u64 tmp;
 709         int err;
 710
 711         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 712         case MLX5_VPORT_ACCESS_METHOD_MAD:
 713                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 714
 715         case MLX5_VPORT_ACCESS_METHOD_HCA:
 716                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 717                 break;
 718
 719         case MLX5_VPORT_ACCESS_METHOD_NIC:
 720                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 721                 break;
 722
 723         default:
 724                 return -EINVAL;
 725         }
 726
 727         if (!err)
 728                 *node_guid = cpu_to_be64(tmp);
 729
 730         return err;
 731 }
 732
 733 struct mlx5_reg_node_desc {
 734         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 735 };
 736
 737 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 738 {
 739         struct mlx5_reg_node_desc in;
 740
 741         if (mlx5_use_mad_ifc(dev))
 742                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 743
 744         memset(&in, 0, sizeof(in));
 745
 746         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 747                                     sizeof(struct mlx5_reg_node_desc),
 748                                     MLX5_REG_NODE_DESC, 0, 0);
 749 }
 750
 751 static int mlx5_ib_query_device(struct ib_device *ibdev,
 752                                 struct ib_device_attr *props,
 753                                 struct ib_udata *uhw)
 754 {
 755         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 756         struct mlx5_core_dev *mdev = dev->mdev;
 757         int err = -ENOMEM;
 758         int max_sq_desc;
 759         int max_rq_sg;
 760         int max_sq_sg;
 761         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 762         bool raw_support = !mlx5_core_mp_enabled(mdev);
 763         struct mlx5_ib_query_device_resp resp = {};
 764         size_t resp_len;
 765         u64 max_tso;
 766
 767         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 768         if (uhw->outlen && uhw->outlen < resp_len)
 769                 return -EINVAL;
 770         else
 771                 resp.response_length = resp_len;
 772
 773         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 774                 return -EINVAL;
 775
 776         memset(props, 0, sizeof(*props));
 777         err = mlx5_query_system_image_guid(ibdev,
 778                                            &props->sys_image_guid);
 779         if (err)
 780                 return err;
 781
 782         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 783         if (err)
 784                 return err;
 785
 786         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 787         if (err)
 788                 return err;
 789
 790         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 791                 (fw_rev_min(dev->mdev) << 16) |
 792                 fw_rev_sub(dev->mdev);
 793         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 794                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 795                 IB_DEVICE_SYS_IMAGE_GUID                |
 796                 IB_DEVICE_RC_RNR_NAK_GEN;
 797
 798         if (MLX5_CAP_GEN(mdev, pkv))
 799                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 800         if (MLX5_CAP_GEN(mdev, qkv))
 801                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 802         if (MLX5_CAP_GEN(mdev, apm))
 803                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 804         if (MLX5_CAP_GEN(mdev, xrc))
 805                 props->device_cap_flags |= IB_DEVICE_XRC;
 806         if (MLX5_CAP_GEN(mdev, imaicl)) {
 807                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 808                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 809                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 810                 /* We support 'Gappy' memory registration too */
 811                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 812         }
 813         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 814         if (MLX5_CAP_GEN(mdev, sho)) {
 815                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 816                 /* At this stage no support for signature handover */
 817                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 818                                       IB_PROT_T10DIF_TYPE_2 |
 819                                       IB_PROT_T10DIF_TYPE_3;
 820                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 821                                        IB_GUARD_T10DIF_CSUM;
 822         }
 823         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 824                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 825
 826         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 827                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 828                         /* Legacy bit to support old userspace libraries */
 829                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 830                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 831                 }
 832
 833                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 834                         props->raw_packet_caps |=
 835                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 836
 837                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 838                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 839                         if (max_tso) {
 840                                 resp.tso_caps.max_tso = 1 << max_tso;
 841                                 resp.tso_caps.supported_qpts |=
 842                                         1 << IB_QPT_RAW_PACKET;
 843                                 resp.response_length += sizeof(resp.tso_caps);
 844                         }
 845                 }
 846
 847                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 848                         resp.rss_caps.rx_hash_function =
 849                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 850                         resp.rss_caps.rx_hash_fields_mask =
 851                                                 MLX5_RX_HASH_SRC_IPV4 |
 852                                                 MLX5_RX_HASH_DST_IPV4 |
 853                                                 MLX5_RX_HASH_SRC_IPV6 |
 854                                                 MLX5_RX_HASH_DST_IPV6 |
 855                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 856                                                 MLX5_RX_HASH_DST_PORT_TCP |
 857                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 858                                                 MLX5_RX_HASH_DST_PORT_UDP |
 859                                                 MLX5_RX_HASH_INNER;
 860                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 861                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 862                                 resp.rss_caps.rx_hash_fields_mask |=
 863                                         MLX5_RX_HASH_IPSEC_SPI;
 864                         resp.response_length += sizeof(resp.rss_caps);
 865                 }
 866         } else {
 867                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 868                         resp.response_length += sizeof(resp.tso_caps);
 869                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 870                         resp.response_length += sizeof(resp.rss_caps);
 871         }
 872
 873         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 874                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 875                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 876         }
 877
 878         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 879             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 880             raw_support)
 881                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 882
 883         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 884             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 885                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 886
 887         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 888             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 889             raw_support) {
 890                 /* Legacy bit to support old userspace libraries */
 891                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 892                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 893         }
 894
 895         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 896                 props->max_dm_size =
 897                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 898         }
 899
 900         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 901                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 902
 903         if (MLX5_CAP_GEN(mdev, end_pad))
 904                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 905
 906         props->vendor_part_id      = mdev->pdev->device;
 907         props->hw_ver              = mdev->pdev->revision;
 908
 909         props->max_mr_size         = ~0ull;
 910         props->page_size_cap       = ~(min_page_size - 1);
 911         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 912         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 913         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 914                      sizeof(struct mlx5_wqe_data_seg);
 915         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 916         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 917                      sizeof(struct mlx5_wqe_raddr_seg)) /
 918                 sizeof(struct mlx5_wqe_data_seg);
 919         props->max_sge = min(max_rq_sg, max_sq_sg);
 920         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 921         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 922         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 923         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 924         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 925         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 926         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 927         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 928         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 929         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 930         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 931         props->max_srq_sge         = max_rq_sg - 1;
 932         props->max_fast_reg_page_list_len =
 933                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 934         get_atomic_caps_qp(dev, props);
 935         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 936         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 937         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 938         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 939                                            props->max_mcast_grp;
 940         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 941         props->max_ah = INT_MAX;
 942         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 943         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 944
 945 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 946         if (MLX5_CAP_GEN(mdev, pg))
 947                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 948         props->odp_caps = dev->odp_caps;
 949 #endif
 950
 951         if (MLX5_CAP_GEN(mdev, cd))
 952                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 953
 954         if (!mlx5_core_is_pf(mdev))
 955                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 956
 957         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 958             IB_LINK_LAYER_ETHERNET && raw_support) {
 959                 props->rss_caps.max_rwq_indirection_tables =
 960                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 961                 props->rss_caps.max_rwq_indirection_table_size =
 962                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 963                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 964                 props->max_wq_type_rq =
 965                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 966         }
 967
 968         if (MLX5_CAP_GEN(mdev, tag_matching)) {
 969                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
 970                 props->tm_caps.max_num_tags =
 971                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
 972                 props->tm_caps.flags = IB_TM_CAP_RC;
 973                 props->tm_caps.max_ops =
 974                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 975                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
 976         }
 977
 978         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
 979                 props->cq_caps.max_cq_moderation_count =
 980                                                 MLX5_MAX_CQ_COUNT;
 981                 props->cq_caps.max_cq_moderation_period =
 982                                                 MLX5_MAX_CQ_PERIOD;
 983         }
 984
 985         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 986                 resp.response_length += sizeof(resp.cqe_comp_caps);
 987
 988                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
 989                         resp.cqe_comp_caps.max_num =
 990                                 MLX5_CAP_GEN(dev->mdev,
 991                                              cqe_compression_max_num);
 992
 993                         resp.cqe_comp_caps.supported_format =
 994                                 MLX5_IB_CQE_RES_FORMAT_HASH |
 995                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
 996
 997                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
 998                                 resp.cqe_comp_caps.supported_format |=
 999                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1000                 }
1001         }
1002
1003         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1004             raw_support) {
1005                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1006                     MLX5_CAP_GEN(mdev, qos)) {
1007                         resp.packet_pacing_caps.qp_rate_limit_max =
1008                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1009                         resp.packet_pacing_caps.qp_rate_limit_min =
1010                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1011                         resp.packet_pacing_caps.supported_qpts |=
1012                                 1 << IB_QPT_RAW_PACKET;
1013                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1014                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1015                                 resp.packet_pacing_caps.cap_flags |=
1016                                         MLX5_IB_PP_SUPPORT_BURST;
1017                 }
1018                 resp.response_length += sizeof(resp.packet_pacing_caps);
1019         }
1020
1021         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1022                         uhw->outlen)) {
1023                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1024                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1025                                 MLX5_IB_ALLOW_MPW;
1026
1027                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1028                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1029                                 MLX5_IB_SUPPORT_EMPW;
1030
1031                 resp.response_length +=
1032                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1033         }
1034
1035         if (field_avail(typeof(resp), flags, uhw->outlen)) {
1036                 resp.response_length += sizeof(resp.flags);
1037
1038                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1039                         resp.flags |=
1040                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1041
1042                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1043                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1044         }
1045
1046         if (field_avail(typeof(resp), sw_parsing_caps,
1047                         uhw->outlen)) {
1048                 resp.response_length += sizeof(resp.sw_parsing_caps);
1049                 if (MLX5_CAP_ETH(mdev, swp)) {
1050                         resp.sw_parsing_caps.sw_parsing_offloads |=
1051                                 MLX5_IB_SW_PARSING;
1052
1053                         if (MLX5_CAP_ETH(mdev, swp_csum))
1054                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1055                                         MLX5_IB_SW_PARSING_CSUM;
1056
1057                         if (MLX5_CAP_ETH(mdev, swp_lso))
1058                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1059                                         MLX5_IB_SW_PARSING_LSO;
1060
1061                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1062                                 resp.sw_parsing_caps.supported_qpts =
1063                                         BIT(IB_QPT_RAW_PACKET);
1064                 }
1065         }
1066
1067         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1068             raw_support) {
1069                 resp.response_length += sizeof(resp.striding_rq_caps);
1070                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1071                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1072                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1073                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1074                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1075                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1076                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1077                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1078                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1079                         resp.striding_rq_caps.supported_qpts =
1080                                 BIT(IB_QPT_RAW_PACKET);
1081                 }
1082         }
1083
1084         if (field_avail(typeof(resp), tunnel_offloads_caps,
1085                         uhw->outlen)) {
1086                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1087                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1088                         resp.tunnel_offloads_caps |=
1089                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1090                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1091                         resp.tunnel_offloads_caps |=
1092                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1093                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1094                         resp.tunnel_offloads_caps |=
1095                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1096         }
1097
1098         if (uhw->outlen) {
1099                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1100
1101                 if (err)
1102                         return err;
1103         }
1104
1105         return 0;
1106 }
1107
1108 enum mlx5_ib_width {
1109         MLX5_IB_WIDTH_1X        = 1 << 0,
1110         MLX5_IB_WIDTH_2X        = 1 << 1,
1111         MLX5_IB_WIDTH_4X        = 1 << 2,
1112         MLX5_IB_WIDTH_8X        = 1 << 3,
1113         MLX5_IB_WIDTH_12X       = 1 << 4
1114 };
1115
1116 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1117                                   u8 *ib_width)
1118 {
1119         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1120         int err = 0;
1121
1122         if (active_width & MLX5_IB_WIDTH_1X) {
1123                 *ib_width = IB_WIDTH_1X;
1124         } else if (active_width & MLX5_IB_WIDTH_2X) {
1125                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1126                             (int)active_width);
1127                 err = -EINVAL;
1128         } else if (active_width & MLX5_IB_WIDTH_4X) {
1129                 *ib_width = IB_WIDTH_4X;
1130         } else if (active_width & MLX5_IB_WIDTH_8X) {
1131                 *ib_width = IB_WIDTH_8X;
1132         } else if (active_width & MLX5_IB_WIDTH_12X) {
1133                 *ib_width = IB_WIDTH_12X;
1134         } else {
1135                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1136                             (int)active_width);
1137                 err = -EINVAL;
1138         }
1139
1140         return err;
1141 }
1142
1143 static int mlx5_mtu_to_ib_mtu(int mtu)
1144 {
1145         switch (mtu) {
1146         case 256: return 1;
1147         case 512: return 2;
1148         case 1024: return 3;
1149         case 2048: return 4;
1150         case 4096: return 5;
1151         default:
1152                 pr_warn("invalid mtu\n");
1153                 return -1;
1154         }
1155 }
1156
1157 enum ib_max_vl_num {
1158         __IB_MAX_VL_0           = 1,
1159         __IB_MAX_VL_0_1         = 2,
1160         __IB_MAX_VL_0_3         = 3,
1161         __IB_MAX_VL_0_7         = 4,
1162         __IB_MAX_VL_0_14        = 5,
1163 };
1164
1165 enum mlx5_vl_hw_cap {
1166         MLX5_VL_HW_0    = 1,
1167         MLX5_VL_HW_0_1  = 2,
1168         MLX5_VL_HW_0_2  = 3,
1169         MLX5_VL_HW_0_3  = 4,
1170         MLX5_VL_HW_0_4  = 5,
1171         MLX5_VL_HW_0_5  = 6,
1172         MLX5_VL_HW_0_6  = 7,
1173         MLX5_VL_HW_0_7  = 8,
1174         MLX5_VL_HW_0_14 = 15
1175 };
1176
1177 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1178                                 u8 *max_vl_num)
1179 {
1180         switch (vl_hw_cap) {
1181         case MLX5_VL_HW_0:
1182                 *max_vl_num = __IB_MAX_VL_0;
1183                 break;
1184         case MLX5_VL_HW_0_1:
1185                 *max_vl_num = __IB_MAX_VL_0_1;
1186                 break;
1187         case MLX5_VL_HW_0_3:
1188                 *max_vl_num = __IB_MAX_VL_0_3;
1189                 break;
1190         case MLX5_VL_HW_0_7:
1191                 *max_vl_num = __IB_MAX_VL_0_7;
1192                 break;
1193         case MLX5_VL_HW_0_14:
1194                 *max_vl_num = __IB_MAX_VL_0_14;
1195                 break;
1196
1197         default:
1198                 return -EINVAL;
1199         }
1200
1201         return 0;
1202 }
1203
1204 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1205                                struct ib_port_attr *props)
1206 {
1207         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1208         struct mlx5_core_dev *mdev = dev->mdev;
1209         struct mlx5_hca_vport_context *rep;
1210         u16 max_mtu;
1211         u16 oper_mtu;
1212         int err;
1213         u8 ib_link_width_oper;
1214         u8 vl_hw_cap;
1215
1216         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1217         if (!rep) {
1218                 err = -ENOMEM;
1219                 goto out;
1220         }
1221
1222         /* props being zeroed by the caller, avoid zeroing it here */
1223
1224         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1225         if (err)
1226                 goto out;
1227
1228         props->lid              = rep->lid;
1229         props->lmc              = rep->lmc;
1230         props->sm_lid           = rep->sm_lid;
1231         props->sm_sl            = rep->sm_sl;
1232         props->state            = rep->vport_state;
1233         props->phys_state       = rep->port_physical_state;
1234         props->port_cap_flags   = rep->cap_mask1;
1235         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1236         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1237         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1238         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1239         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1240         props->subnet_timeout   = rep->subnet_timeout;
1241         props->init_type_reply  = rep->init_type_reply;
1242         props->grh_required     = rep->grh_required;
1243
1244         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1245         if (err)
1246                 goto out;
1247
1248         err = translate_active_width(ibdev, ib_link_width_oper,
1249                                      &props->active_width);
1250         if (err)
1251                 goto out;
1252         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1253         if (err)
1254                 goto out;
1255
1256         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1257
1258         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1259
1260         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1261
1262         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1263
1264         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1265         if (err)
1266                 goto out;
1267
1268         err = translate_max_vl_num(ibdev, vl_hw_cap,
1269                                    &props->max_vl_num);
1270 out:
1271         kfree(rep);
1272         return err;
1273 }
1274
1275 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1276                        struct ib_port_attr *props)
1277 {
1278         unsigned int count;
1279         int ret;
1280
1281         switch (mlx5_get_vport_access_method(ibdev)) {
1282         case MLX5_VPORT_ACCESS_METHOD_MAD:
1283                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1284                 break;
1285
1286         case MLX5_VPORT_ACCESS_METHOD_HCA:
1287                 ret = mlx5_query_hca_port(ibdev, port, props);
1288                 break;
1289
1290         case MLX5_VPORT_ACCESS_METHOD_NIC:
1291                 ret = mlx5_query_port_roce(ibdev, port, props);
1292                 break;
1293
1294         default:
1295                 ret = -EINVAL;
1296         }
1297
1298         if (!ret && props) {
1299                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1300                 struct mlx5_core_dev *mdev;
1301                 bool put_mdev = true;
1302
1303                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1304                 if (!mdev) {
1305                         /* If the port isn't affiliated yet query the master.
1306                          * The master and slave will have the same values.
1307                          */
1308                         mdev = dev->mdev;
1309                         port = 1;
1310                         put_mdev = false;
1311                 }
1312                 count = mlx5_core_reserved_gids_count(mdev);
1313                 if (put_mdev)
1314                         mlx5_ib_put_native_port_mdev(dev, port);
1315                 props->gid_tbl_len -= count;
1316         }
1317         return ret;
1318 }
1319
1320 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1321                                   struct ib_port_attr *props)
1322 {
1323         int ret;
1324
1325         /* Only link layer == ethernet is valid for representors */
1326         ret = mlx5_query_port_roce(ibdev, port, props);
1327         if (ret || !props)
1328                 return ret;
1329
1330         /* We don't support GIDS */
1331         props->gid_tbl_len = 0;
1332
1333         return ret;
1334 }
1335
1336 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1337                              union ib_gid *gid)
1338 {
1339         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1340         struct mlx5_core_dev *mdev = dev->mdev;
1341
1342         switch (mlx5_get_vport_access_method(ibdev)) {
1343         case MLX5_VPORT_ACCESS_METHOD_MAD:
1344                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1345
1346         case MLX5_VPORT_ACCESS_METHOD_HCA:
1347                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1348
1349         default:
1350                 return -EINVAL;
1351         }
1352
1353 }
1354
1355 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1356                                    u16 index, u16 *pkey)
1357 {
1358         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1359         struct mlx5_core_dev *mdev;
1360         bool put_mdev = true;
1361         u8 mdev_port_num;
1362         int err;
1363
1364         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1365         if (!mdev) {
1366                 /* The port isn't affiliated yet, get the PKey from the master
1367                  * port. For RoCE the PKey tables will be the same.
1368                  */
1369                 put_mdev = false;
1370                 mdev = dev->mdev;
1371                 mdev_port_num = 1;
1372         }
1373
1374         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1375                                         index, pkey);
1376         if (put_mdev)
1377                 mlx5_ib_put_native_port_mdev(dev, port);
1378
1379         return err;
1380 }
1381
1382 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1383                               u16 *pkey)
1384 {
1385         switch (mlx5_get_vport_access_method(ibdev)) {
1386         case MLX5_VPORT_ACCESS_METHOD_MAD:
1387                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1388
1389         case MLX5_VPORT_ACCESS_METHOD_HCA:
1390         case MLX5_VPORT_ACCESS_METHOD_NIC:
1391                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1392         default:
1393                 return -EINVAL;
1394         }
1395 }
1396
1397 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1398                                  struct ib_device_modify *props)
1399 {
1400         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1401         struct mlx5_reg_node_desc in;
1402         struct mlx5_reg_node_desc out;
1403         int err;
1404
1405         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1406                 return -EOPNOTSUPP;
1407
1408         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1409                 return 0;
1410
1411         /*
1412          * If possible, pass node desc to FW, so it can generate
1413          * a 144 trap.  If cmd fails, just ignore.
1414          */
1415         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1416         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1417                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1418         if (err)
1419                 return err;
1420
1421         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1422
1423         return err;
1424 }
1425
1426 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1427                                 u32 value)
1428 {
1429         struct mlx5_hca_vport_context ctx = {};
1430         struct mlx5_core_dev *mdev;
1431         u8 mdev_port_num;
1432         int err;
1433
1434         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1435         if (!mdev)
1436                 return -ENODEV;
1437
1438         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1439         if (err)
1440                 goto out;
1441
1442         if (~ctx.cap_mask1_perm & mask) {
1443                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1444                              mask, ctx.cap_mask1_perm);
1445                 err = -EINVAL;
1446                 goto out;
1447         }
1448
1449         ctx.cap_mask1 = value;
1450         ctx.cap_mask1_perm = mask;
1451         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1452                                                  0, &ctx);
1453
1454 out:
1455         mlx5_ib_put_native_port_mdev(dev, port_num);
1456
1457         return err;
1458 }
1459
1460 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1461                                struct ib_port_modify *props)
1462 {
1463         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1464         struct ib_port_attr attr;
1465         u32 tmp;
1466         int err;
1467         u32 change_mask;
1468         u32 value;
1469         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1470                       IB_LINK_LAYER_INFINIBAND);
1471
1472         /* CM layer calls ib_modify_port() regardless of the link layer. For
1473          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1474          */
1475         if (!is_ib)
1476                 return 0;
1477
1478         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1479                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1480                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1481                 return set_port_caps_atomic(dev, port, change_mask, value);
1482         }
1483
1484         mutex_lock(&dev->cap_mask_mutex);
1485
1486         err = ib_query_port(ibdev, port, &attr);
1487         if (err)
1488                 goto out;
1489
1490         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1491                 ~props->clr_port_cap_mask;
1492
1493         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1494
1495 out:
1496         mutex_unlock(&dev->cap_mask_mutex);
1497         return err;
1498 }
1499
1500 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1501 {
1502         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1503                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1504 }
1505
1506 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1507 {
1508         /* Large page with non 4k uar support might limit the dynamic size */
1509         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1510                 return MLX5_MIN_DYN_BFREGS;
1511
1512         return MLX5_MAX_DYN_BFREGS;
1513 }
1514
1515 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1516                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1517                              struct mlx5_bfreg_info *bfregi)
1518 {
1519         int uars_per_sys_page;
1520         int bfregs_per_sys_page;
1521         int ref_bfregs = req->total_num_bfregs;
1522
1523         if (req->total_num_bfregs == 0)
1524                 return -EINVAL;
1525
1526         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1527         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1528
1529         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1530                 return -ENOMEM;
1531
1532         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1533         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1534         /* This holds the required static allocation asked by the user */
1535         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1536         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1537                 return -EINVAL;
1538
1539         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1540         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1541         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1542         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1543
1544         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1545                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1546                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1547                     req->total_num_bfregs, bfregi->total_num_bfregs,
1548                     bfregi->num_sys_pages);
1549
1550         return 0;
1551 }
1552
1553 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1554 {
1555         struct mlx5_bfreg_info *bfregi;
1556         int err;
1557         int i;
1558
1559         bfregi = &context->bfregi;
1560         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1561                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1562                 if (err)
1563                         goto error;
1564
1565                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1566         }
1567
1568         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1569                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1570
1571         return 0;
1572
1573 error:
1574         for (--i; i >= 0; i--)
1575                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1576                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1577
1578         return err;
1579 }
1580
1581 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1582 {
1583         struct mlx5_bfreg_info *bfregi;
1584         int err;
1585         int i;
1586
1587         bfregi = &context->bfregi;
1588         for (i = 0; i < bfregi->num_sys_pages; i++) {
1589                 if (i < bfregi->num_static_sys_pages ||
1590                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1591                         err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1592                         if (err) {
1593                                 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1594                                 return err;
1595                         }
1596                 }
1597         }
1598
1599         return 0;
1600 }
1601
1602 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1603 {
1604         int err;
1605
1606         err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1607         if (err)
1608                 return err;
1609
1610         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1611             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1612              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1613                 return err;
1614
1615         mutex_lock(&dev->lb_mutex);
1616         dev->user_td++;
1617
1618         if (dev->user_td == 2)
1619                 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1620
1621         mutex_unlock(&dev->lb_mutex);
1622         return err;
1623 }
1624
1625 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1626 {
1627         mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1628
1629         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1630             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1631              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1632                 return;
1633
1634         mutex_lock(&dev->lb_mutex);
1635         dev->user_td--;
1636
1637         if (dev->user_td < 2)
1638                 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1639
1640         mutex_unlock(&dev->lb_mutex);
1641 }
1642
1643 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1644                                                   struct ib_udata *udata)
1645 {
1646         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1647         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1648         struct mlx5_ib_alloc_ucontext_resp resp = {};
1649         struct mlx5_core_dev *mdev = dev->mdev;
1650         struct mlx5_ib_ucontext *context;
1651         struct mlx5_bfreg_info *bfregi;
1652         int ver;
1653         int err;
1654         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1655                                      max_cqe_version);
1656         bool lib_uar_4k;
1657
1658         if (!dev->ib_active)
1659                 return ERR_PTR(-EAGAIN);
1660
1661         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1662                 ver = 0;
1663         else if (udata->inlen >= min_req_v2)
1664                 ver = 2;
1665         else
1666                 return ERR_PTR(-EINVAL);
1667
1668         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1669         if (err)
1670                 return ERR_PTR(err);
1671
1672         if (req.flags)
1673                 return ERR_PTR(-EINVAL);
1674
1675         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1676                 return ERR_PTR(-EOPNOTSUPP);
1677
1678         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1679                                     MLX5_NON_FP_BFREGS_PER_UAR);
1680         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1681                 return ERR_PTR(-EINVAL);
1682
1683         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1684         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1685                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1686         resp.cache_line_size = cache_line_size();
1687         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1688         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1689         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1690         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1691         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1692         resp.cqe_version = min_t(__u8,
1693                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1694                                  req.max_cqe_version);
1695         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1696                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1697         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1698                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1699         resp.response_length = min(offsetof(typeof(resp), response_length) +
1700                                    sizeof(resp.response_length), udata->outlen);
1701
1702         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1703                 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1704                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1705                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1706                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1707                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1708                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1709                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1710                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1711                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1712         }
1713
1714         context = kzalloc(sizeof(*context), GFP_KERNEL);
1715         if (!context)
1716                 return ERR_PTR(-ENOMEM);
1717
1718         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1719         bfregi = &context->bfregi;
1720
1721         /* updates req->total_num_bfregs */
1722         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1723         if (err)
1724                 goto out_ctx;
1725
1726         mutex_init(&bfregi->lock);
1727         bfregi->lib_uar_4k = lib_uar_4k;
1728         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1729                                 GFP_KERNEL);
1730         if (!bfregi->count) {
1731                 err = -ENOMEM;
1732                 goto out_ctx;
1733         }
1734
1735         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1736                                     sizeof(*bfregi->sys_pages),
1737                                     GFP_KERNEL);
1738         if (!bfregi->sys_pages) {
1739                 err = -ENOMEM;
1740                 goto out_count;
1741         }
1742
1743         err = allocate_uars(dev, context);
1744         if (err)
1745                 goto out_sys_pages;
1746
1747 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1748         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1749 #endif
1750
1751         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1752                 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1753                 if (err)
1754                         goto out_uars;
1755         }
1756
1757         INIT_LIST_HEAD(&context->vma_private_list);
1758         mutex_init(&context->vma_private_list_mutex);
1759         INIT_LIST_HEAD(&context->db_page_list);
1760         mutex_init(&context->db_page_mutex);
1761
1762         resp.tot_bfregs = req.total_num_bfregs;
1763         resp.num_ports = dev->num_ports;
1764
1765         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1766                 resp.response_length += sizeof(resp.cqe_version);
1767
1768         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1769                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1770                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1771                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1772         }
1773
1774         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1775                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1776                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1777                         resp.eth_min_inline++;
1778                 }
1779                 resp.response_length += sizeof(resp.eth_min_inline);
1780         }
1781
1782         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1783                 if (mdev->clock_info)
1784                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1785                 resp.response_length += sizeof(resp.clock_info_versions);
1786         }
1787
1788         /*
1789          * We don't want to expose information from the PCI bar that is located
1790          * after 4096 bytes, so if the arch only supports larger pages, let's
1791          * pretend we don't support reading the HCA's core clock. This is also
1792          * forced by mmap function.
1793          */
1794         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1795                 if (PAGE_SIZE <= 4096) {
1796                         resp.comp_mask |=
1797                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1798                         resp.hca_core_clock_offset =
1799                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1800                 }
1801                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1802         }
1803
1804         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1805                 resp.response_length += sizeof(resp.log_uar_size);
1806
1807         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1808                 resp.response_length += sizeof(resp.num_uars_per_page);
1809
1810         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1811                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1812                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1813         }
1814
1815         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1816         if (err)
1817                 goto out_td;
1818
1819         bfregi->ver = ver;
1820         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1821         context->cqe_version = resp.cqe_version;
1822         context->lib_caps = req.lib_caps;
1823         print_lib_caps(dev, context->lib_caps);
1824
1825         return &context->ibucontext;
1826
1827 out_td:
1828         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1829                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1830
1831 out_uars:
1832         deallocate_uars(dev, context);
1833
1834 out_sys_pages:
1835         kfree(bfregi->sys_pages);
1836
1837 out_count:
1838         kfree(bfregi->count);
1839
1840 out_ctx:
1841         kfree(context);
1842
1843         return ERR_PTR(err);
1844 }
1845
1846 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1847 {
1848         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1849         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1850         struct mlx5_bfreg_info *bfregi;
1851
1852         bfregi = &context->bfregi;
1853         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1854                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1855
1856         deallocate_uars(dev, context);
1857         kfree(bfregi->sys_pages);
1858         kfree(bfregi->count);
1859         kfree(context);
1860
1861         return 0;
1862 }
1863
1864 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1865                                  int uar_idx)
1866 {
1867         int fw_uars_per_page;
1868
1869         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1870
1871         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1872 }
1873
1874 static int get_command(unsigned long offset)
1875 {
1876         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1877 }
1878
1879 static int get_arg(unsigned long offset)
1880 {
1881         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1882 }
1883
1884 static int get_index(unsigned long offset)
1885 {
1886         return get_arg(offset);
1887 }
1888
1889 /* Index resides in an extra byte to enable larger values than 255 */
1890 static int get_extended_index(unsigned long offset)
1891 {
1892         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1893 }
1894
1895 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1896 {
1897         /* vma_open is called when a new VMA is created on top of our VMA.  This
1898          * is done through either mremap flow or split_vma (usually due to
1899          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1900          * as this VMA is strongly hardware related.  Therefore we set the
1901          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1902          * calling us again and trying to do incorrect actions.  We assume that
1903          * the original VMA size is exactly a single page, and therefore all
1904          * "splitting" operation will not happen to it.
1905          */
1906         area->vm_ops = NULL;
1907 }
1908
1909 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1910 {
1911         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1912
1913         /* It's guaranteed that all VMAs opened on a FD are closed before the
1914          * file itself is closed, therefore no sync is needed with the regular
1915          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1916          * However need a sync with accessing the vma as part of
1917          * mlx5_ib_disassociate_ucontext.
1918          * The close operation is usually called under mm->mmap_sem except when
1919          * process is exiting.
1920          * The exiting case is handled explicitly as part of
1921          * mlx5_ib_disassociate_ucontext.
1922          */
1923         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1924
1925         /* setting the vma context pointer to null in the mlx5_ib driver's
1926          * private data, to protect a race condition in
1927          * mlx5_ib_disassociate_ucontext().
1928          */
1929         mlx5_ib_vma_priv_data->vma = NULL;
1930         mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1931         list_del(&mlx5_ib_vma_priv_data->list);
1932         mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1933         kfree(mlx5_ib_vma_priv_data);
1934 }
1935
1936 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1937         .open = mlx5_ib_vma_open,
1938         .close = mlx5_ib_vma_close
1939 };
1940
1941 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1942                                 struct mlx5_ib_ucontext *ctx)
1943 {
1944         struct mlx5_ib_vma_private_data *vma_prv;
1945         struct list_head *vma_head = &ctx->vma_private_list;
1946
1947         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1948         if (!vma_prv)
1949                 return -ENOMEM;
1950
1951         vma_prv->vma = vma;
1952         vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1953         vma->vm_private_data = vma_prv;
1954         vma->vm_ops =  &mlx5_ib_vm_ops;
1955
1956         mutex_lock(&ctx->vma_private_list_mutex);
1957         list_add(&vma_prv->list, vma_head);
1958         mutex_unlock(&ctx->vma_private_list_mutex);
1959
1960         return 0;
1961 }
1962
1963 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1964 {
1965         int ret;
1966         struct vm_area_struct *vma;
1967         struct mlx5_ib_vma_private_data *vma_private, *n;
1968         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1969         struct task_struct *owning_process  = NULL;
1970         struct mm_struct   *owning_mm       = NULL;
1971
1972         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1973         if (!owning_process)
1974                 return;
1975
1976         owning_mm = get_task_mm(owning_process);
1977         if (!owning_mm) {
1978                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1979                 while (1) {
1980                         put_task_struct(owning_process);
1981                         usleep_range(1000, 2000);
1982                         owning_process = get_pid_task(ibcontext->tgid,
1983                                                       PIDTYPE_PID);
1984                         if (!owning_process ||
1985                             owning_process->state == TASK_DEAD) {
1986                                 pr_info("disassociate ucontext done, task was terminated\n");
1987                                 /* in case task was dead need to release the
1988                                  * task struct.
1989                                  */
1990                                 if (owning_process)
1991                                         put_task_struct(owning_process);
1992                                 return;
1993                         }
1994                 }
1995         }
1996
1997         /* need to protect from a race on closing the vma as part of
1998          * mlx5_ib_vma_close.
1999          */
2000         down_write(&owning_mm->mmap_sem);
2001         mutex_lock(&context->vma_private_list_mutex);
2002         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
2003                                  list) {
2004                 vma = vma_private->vma;
2005                 ret = zap_vma_ptes(vma, vma->vm_start,
2006                                    PAGE_SIZE);
2007                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
2008                 /* context going to be destroyed, should
2009                  * not access ops any more.
2010                  */
2011                 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
2012                 vma->vm_ops = NULL;
2013                 list_del(&vma_private->list);
2014                 kfree(vma_private);
2015         }
2016         mutex_unlock(&context->vma_private_list_mutex);
2017         up_write(&owning_mm->mmap_sem);
2018         mmput(owning_mm);
2019         put_task_struct(owning_process);
2020 }
2021
2022 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2023 {
2024         switch (cmd) {
2025         case MLX5_IB_MMAP_WC_PAGE:
2026                 return "WC";
2027         case MLX5_IB_MMAP_REGULAR_PAGE:
2028                 return "best effort WC";
2029         case MLX5_IB_MMAP_NC_PAGE:
2030                 return "NC";
2031         case MLX5_IB_MMAP_DEVICE_MEM:
2032                 return "Device Memory";
2033         default:
2034                 return NULL;
2035         }
2036 }
2037
2038 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2039                                         struct vm_area_struct *vma,
2040                                         struct mlx5_ib_ucontext *context)
2041 {
2042         phys_addr_t pfn;
2043         int err;
2044
2045         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2046                 return -EINVAL;
2047
2048         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2049                 return -EOPNOTSUPP;
2050
2051         if (vma->vm_flags & VM_WRITE)
2052                 return -EPERM;
2053
2054         if (!dev->mdev->clock_info_page)
2055                 return -EOPNOTSUPP;
2056
2057         pfn = page_to_pfn(dev->mdev->clock_info_page);
2058         err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2059                               vma->vm_page_prot);
2060         if (err)
2061                 return err;
2062
2063         mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
2064                     vma->vm_start,
2065                     (unsigned long long)pfn << PAGE_SHIFT);
2066
2067         return mlx5_ib_set_vma_data(vma, context);
2068 }
2069
2070 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2071                     struct vm_area_struct *vma,
2072                     struct mlx5_ib_ucontext *context)
2073 {
2074         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2075         int err;
2076         unsigned long idx;
2077         phys_addr_t pfn, pa;
2078         pgprot_t prot;
2079         u32 bfreg_dyn_idx = 0;
2080         u32 uar_index;
2081         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2082         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2083                                 bfregi->num_static_sys_pages;
2084
2085         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2086                 return -EINVAL;
2087
2088         if (dyn_uar)
2089                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2090         else
2091                 idx = get_index(vma->vm_pgoff);
2092
2093         if (idx >= max_valid_idx) {
2094                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2095                              idx, max_valid_idx);
2096                 return -EINVAL;
2097         }
2098
2099         switch (cmd) {
2100         case MLX5_IB_MMAP_WC_PAGE:
2101         case MLX5_IB_MMAP_ALLOC_WC:
2102 /* Some architectures don't support WC memory */
2103 #if defined(CONFIG_X86)
2104                 if (!pat_enabled())
2105                         return -EPERM;
2106 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2107                         return -EPERM;
2108 #endif
2109         /* fall through */
2110         case MLX5_IB_MMAP_REGULAR_PAGE:
2111                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2112                 prot = pgprot_writecombine(vma->vm_page_prot);
2113                 break;
2114         case MLX5_IB_MMAP_NC_PAGE:
2115                 prot = pgprot_noncached(vma->vm_page_prot);
2116                 break;
2117         default:
2118                 return -EINVAL;
2119         }
2120
2121         if (dyn_uar) {
2122                 int uars_per_page;
2123
2124                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2125                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2126                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2127                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2128                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2129                         return -EINVAL;
2130                 }
2131
2132                 mutex_lock(&bfregi->lock);
2133                 /* Fail if uar already allocated, first bfreg index of each
2134                  * page holds its count.
2135                  */
2136                 if (bfregi->count[bfreg_dyn_idx]) {
2137                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2138                         mutex_unlock(&bfregi->lock);
2139                         return -EINVAL;
2140                 }
2141
2142                 bfregi->count[bfreg_dyn_idx]++;
2143                 mutex_unlock(&bfregi->lock);
2144
2145                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2146                 if (err) {
2147                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2148                         goto free_bfreg;
2149                 }
2150         } else {
2151                 uar_index = bfregi->sys_pages[idx];
2152         }
2153
2154         pfn = uar_index2pfn(dev, uar_index);
2155         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2156
2157         vma->vm_page_prot = prot;
2158         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2159                                  PAGE_SIZE, vma->vm_page_prot);
2160         if (err) {
2161                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2162                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
2163                 err = -EAGAIN;
2164                 goto err;
2165         }
2166
2167         pa = pfn << PAGE_SHIFT;
2168         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2169                     vma->vm_start, &pa);
2170
2171         err = mlx5_ib_set_vma_data(vma, context);
2172         if (err)
2173                 goto err;
2174
2175         if (dyn_uar)
2176                 bfregi->sys_pages[idx] = uar_index;
2177         return 0;
2178
2179 err:
2180         if (!dyn_uar)
2181                 return err;
2182
2183         mlx5_cmd_free_uar(dev->mdev, idx);
2184
2185 free_bfreg:
2186         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2187
2188         return err;
2189 }
2190
2191 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2192 {
2193         struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2194         struct mlx5_ib_dev *dev = to_mdev(context->device);
2195         u16 page_idx = get_extended_index(vma->vm_pgoff);
2196         size_t map_size = vma->vm_end - vma->vm_start;
2197         u32 npages = map_size >> PAGE_SHIFT;
2198         phys_addr_t pfn;
2199         pgprot_t prot;
2200
2201         if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2202             page_idx + npages)
2203                 return -EINVAL;
2204
2205         pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2206               MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2207               PAGE_SHIFT) +
2208               page_idx;
2209         prot = pgprot_writecombine(vma->vm_page_prot);
2210         vma->vm_page_prot = prot;
2211
2212         if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2213                                vma->vm_page_prot))
2214                 return -EAGAIN;
2215
2216         return mlx5_ib_set_vma_data(vma, mctx);
2217 }
2218
2219 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2220 {
2221         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2222         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2223         unsigned long command;
2224         phys_addr_t pfn;
2225
2226         command = get_command(vma->vm_pgoff);
2227         switch (command) {
2228         case MLX5_IB_MMAP_WC_PAGE:
2229         case MLX5_IB_MMAP_NC_PAGE:
2230         case MLX5_IB_MMAP_REGULAR_PAGE:
2231         case MLX5_IB_MMAP_ALLOC_WC:
2232                 return uar_mmap(dev, command, vma, context);
2233
2234         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2235                 return -ENOSYS;
2236
2237         case MLX5_IB_MMAP_CORE_CLOCK:
2238                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2239                         return -EINVAL;
2240
2241                 if (vma->vm_flags & VM_WRITE)
2242                         return -EPERM;
2243
2244                 /* Don't expose to user-space information it shouldn't have */
2245                 if (PAGE_SIZE > 4096)
2246                         return -EOPNOTSUPP;
2247
2248                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2249                 pfn = (dev->mdev->iseg_base +
2250                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2251                         PAGE_SHIFT;
2252                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2253                                        PAGE_SIZE, vma->vm_page_prot))
2254                         return -EAGAIN;
2255
2256                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2257                             vma->vm_start,
2258                             (unsigned long long)pfn << PAGE_SHIFT);
2259                 break;
2260         case MLX5_IB_MMAP_CLOCK_INFO:
2261                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2262
2263         case MLX5_IB_MMAP_DEVICE_MEM:
2264                 return dm_mmap(ibcontext, vma);
2265
2266         default:
2267                 return -EINVAL;
2268         }
2269
2270         return 0;
2271 }
2272
2273 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2274                                struct ib_ucontext *context,
2275                                struct ib_dm_alloc_attr *attr,
2276                                struct uverbs_attr_bundle *attrs)
2277 {
2278         u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2279         struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2280         phys_addr_t memic_addr;
2281         struct mlx5_ib_dm *dm;
2282         u64 start_offset;
2283         u32 page_idx;
2284         int err;
2285
2286         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2287         if (!dm)
2288                 return ERR_PTR(-ENOMEM);
2289
2290         mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2291                     attr->length, act_size, attr->alignment);
2292
2293         err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2294                                    act_size, attr->alignment);
2295         if (err)
2296                 goto err_free;
2297
2298         start_offset = memic_addr & ~PAGE_MASK;
2299         page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2300                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2301                     PAGE_SHIFT;
2302
2303         err = uverbs_copy_to(attrs,
2304                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2305                              &start_offset, sizeof(start_offset));
2306         if (err)
2307                 goto err_dealloc;
2308
2309         err = uverbs_copy_to(attrs,
2310                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2311                              &page_idx, sizeof(page_idx));
2312         if (err)
2313                 goto err_dealloc;
2314
2315         bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2316                    DIV_ROUND_UP(act_size, PAGE_SIZE));
2317
2318         dm->dev_addr = memic_addr;
2319
2320         return &dm->ibdm;
2321
2322 err_dealloc:
2323         mlx5_cmd_dealloc_memic(memic, memic_addr,
2324                                act_size);
2325 err_free:
2326         kfree(dm);
2327         return ERR_PTR(err);
2328 }
2329
2330 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2331 {
2332         struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2333         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2334         u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2335         u32 page_idx;
2336         int ret;
2337
2338         ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2339         if (ret)
2340                 return ret;
2341
2342         page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2343                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2344                     PAGE_SHIFT;
2345         bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2346                      page_idx,
2347                      DIV_ROUND_UP(act_size, PAGE_SIZE));
2348
2349         kfree(dm);
2350
2351         return 0;
2352 }
2353
2354 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2355                                       struct ib_ucontext *context,
2356                                       struct ib_udata *udata)
2357 {
2358         struct mlx5_ib_alloc_pd_resp resp;
2359         struct mlx5_ib_pd *pd;
2360         int err;
2361
2362         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2363         if (!pd)
2364                 return ERR_PTR(-ENOMEM);
2365
2366         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2367         if (err) {
2368                 kfree(pd);
2369                 return ERR_PTR(err);
2370         }
2371
2372         if (context) {
2373                 resp.pdn = pd->pdn;
2374                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2375                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2376                         kfree(pd);
2377                         return ERR_PTR(-EFAULT);
2378                 }
2379         }
2380
2381         return &pd->ibpd;
2382 }
2383
2384 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2385 {
2386         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2387         struct mlx5_ib_pd *mpd = to_mpd(pd);
2388
2389         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2390         kfree(mpd);
2391
2392         return 0;
2393 }
2394
2395 enum {
2396         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2397         MATCH_CRITERIA_ENABLE_MISC_BIT,
2398         MATCH_CRITERIA_ENABLE_INNER_BIT
2399 };
2400
2401 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2402         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2403                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2404
2405 static u8 get_match_criteria_enable(u32 *match_criteria)
2406 {
2407         u8 match_criteria_enable;
2408
2409         match_criteria_enable =
2410                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2411                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2412         match_criteria_enable |=
2413                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2414                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2415         match_criteria_enable |=
2416                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2417                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2418
2419         return match_criteria_enable;
2420 }
2421
2422 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2423 {
2424         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2425         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2426 }
2427
2428 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2429                            bool inner)
2430 {
2431         if (inner) {
2432                 MLX5_SET(fte_match_set_misc,
2433                          misc_c, inner_ipv6_flow_label, mask);
2434                 MLX5_SET(fte_match_set_misc,
2435                          misc_v, inner_ipv6_flow_label, val);
2436         } else {
2437                 MLX5_SET(fte_match_set_misc,
2438                          misc_c, outer_ipv6_flow_label, mask);
2439                 MLX5_SET(fte_match_set_misc,
2440                          misc_v, outer_ipv6_flow_label, val);
2441         }
2442 }
2443
2444 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2445 {
2446         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2447         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2448         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2449         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2450 }
2451
2452 #define LAST_ETH_FIELD vlan_tag
2453 #define LAST_IB_FIELD sl
2454 #define LAST_IPV4_FIELD tos
2455 #define LAST_IPV6_FIELD traffic_class
2456 #define LAST_TCP_UDP_FIELD src_port
2457 #define LAST_TUNNEL_FIELD tunnel_id
2458 #define LAST_FLOW_TAG_FIELD tag_id
2459 #define LAST_DROP_FIELD size
2460
2461 /* Field is the last supported field */
2462 #define FIELDS_NOT_SUPPORTED(filter, field)\
2463         memchr_inv((void *)&filter.field  +\
2464                    sizeof(filter.field), 0,\
2465                    sizeof(filter) -\
2466                    offsetof(typeof(filter), field) -\
2467                    sizeof(filter.field))
2468
2469 static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2470                                   const struct ib_flow_attr *flow_attr,
2471                                   struct mlx5_flow_act *action)
2472 {
2473         struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2474
2475         switch (maction->ib_action.type) {
2476         case IB_FLOW_ACTION_ESP:
2477                 /* Currently only AES_GCM keymat is supported by the driver */
2478                 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2479                 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2480                         MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2481                         MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2482                 return 0;
2483         default:
2484                 return -EOPNOTSUPP;
2485         }
2486 }
2487
2488 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2489                            u32 *match_v, const union ib_flow_spec *ib_spec,
2490                            const struct ib_flow_attr *flow_attr,
2491                            struct mlx5_flow_act *action)
2492 {
2493         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2494                                            misc_parameters);
2495         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2496                                            misc_parameters);
2497         void *headers_c;
2498         void *headers_v;
2499         int match_ipv;
2500         int ret;
2501
2502         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2503                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2504                                          inner_headers);
2505                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2506                                          inner_headers);
2507                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2508                                         ft_field_support.inner_ip_version);
2509         } else {
2510                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2511                                          outer_headers);
2512                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2513                                          outer_headers);
2514                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2515                                         ft_field_support.outer_ip_version);
2516         }
2517
2518         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2519         case IB_FLOW_SPEC_ETH:
2520                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2521                         return -EOPNOTSUPP;
2522
2523                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2524                                              dmac_47_16),
2525                                 ib_spec->eth.mask.dst_mac);
2526                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2527                                              dmac_47_16),
2528                                 ib_spec->eth.val.dst_mac);
2529
2530                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2531                                              smac_47_16),
2532                                 ib_spec->eth.mask.src_mac);
2533                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2534                                              smac_47_16),
2535                                 ib_spec->eth.val.src_mac);
2536
2537                 if (ib_spec->eth.mask.vlan_tag) {
2538                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2539                                  cvlan_tag, 1);
2540                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2541                                  cvlan_tag, 1);
2542
2543                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2544                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2545                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2546                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2547
2548                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2549                                  first_cfi,
2550                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2551                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2552                                  first_cfi,
2553                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2554
2555                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2556                                  first_prio,
2557                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2558                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2559                                  first_prio,
2560                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2561                 }
2562                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2563                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2564                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2565                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2566                 break;
2567         case IB_FLOW_SPEC_IPV4:
2568                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2569                         return -EOPNOTSUPP;
2570
2571                 if (match_ipv) {
2572                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2573                                  ip_version, 0xf);
2574                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2575                                  ip_version, MLX5_FS_IPV4_VERSION);
2576                 } else {
2577                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2578                                  ethertype, 0xffff);
2579                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2580                                  ethertype, ETH_P_IP);
2581                 }
2582
2583                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2584                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2585                        &ib_spec->ipv4.mask.src_ip,
2586                        sizeof(ib_spec->ipv4.mask.src_ip));
2587                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2588                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2589                        &ib_spec->ipv4.val.src_ip,
2590                        sizeof(ib_spec->ipv4.val.src_ip));
2591                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2592                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2593                        &ib_spec->ipv4.mask.dst_ip,
2594                        sizeof(ib_spec->ipv4.mask.dst_ip));
2595                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2596                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2597                        &ib_spec->ipv4.val.dst_ip,
2598                        sizeof(ib_spec->ipv4.val.dst_ip));
2599
2600                 set_tos(headers_c, headers_v,
2601                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2602
2603                 set_proto(headers_c, headers_v,
2604                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2605                 break;
2606         case IB_FLOW_SPEC_IPV6:
2607                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2608                         return -EOPNOTSUPP;
2609
2610                 if (match_ipv) {
2611                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2612                                  ip_version, 0xf);
2613                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2614                                  ip_version, MLX5_FS_IPV6_VERSION);
2615                 } else {
2616                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2617                                  ethertype, 0xffff);
2618                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2619                                  ethertype, ETH_P_IPV6);
2620                 }
2621
2622                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2623                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2624                        &ib_spec->ipv6.mask.src_ip,
2625                        sizeof(ib_spec->ipv6.mask.src_ip));
2626                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2627                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2628                        &ib_spec->ipv6.val.src_ip,
2629                        sizeof(ib_spec->ipv6.val.src_ip));
2630                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2631                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2632                        &ib_spec->ipv6.mask.dst_ip,
2633                        sizeof(ib_spec->ipv6.mask.dst_ip));
2634                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2635                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2636                        &ib_spec->ipv6.val.dst_ip,
2637                        sizeof(ib_spec->ipv6.val.dst_ip));
2638
2639                 set_tos(headers_c, headers_v,
2640                         ib_spec->ipv6.mask.traffic_class,
2641                         ib_spec->ipv6.val.traffic_class);
2642
2643                 set_proto(headers_c, headers_v,
2644                           ib_spec->ipv6.mask.next_hdr,
2645                           ib_spec->ipv6.val.next_hdr);
2646
2647                 set_flow_label(misc_params_c, misc_params_v,
2648                                ntohl(ib_spec->ipv6.mask.flow_label),
2649                                ntohl(ib_spec->ipv6.val.flow_label),
2650                                ib_spec->type & IB_FLOW_SPEC_INNER);
2651                 break;
2652         case IB_FLOW_SPEC_ESP:
2653                 if (ib_spec->esp.mask.seq)
2654                         return -EOPNOTSUPP;
2655
2656                 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2657                          ntohl(ib_spec->esp.mask.spi));
2658                 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2659                          ntohl(ib_spec->esp.val.spi));
2660                 break;
2661         case IB_FLOW_SPEC_TCP:
2662                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2663                                          LAST_TCP_UDP_FIELD))
2664                         return -EOPNOTSUPP;
2665
2666                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2667                          0xff);
2668                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2669                          IPPROTO_TCP);
2670
2671                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2672                          ntohs(ib_spec->tcp_udp.mask.src_port));
2673                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2674                          ntohs(ib_spec->tcp_udp.val.src_port));
2675
2676                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2677                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2678                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2679                          ntohs(ib_spec->tcp_udp.val.dst_port));
2680                 break;
2681         case IB_FLOW_SPEC_UDP:
2682                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2683                                          LAST_TCP_UDP_FIELD))
2684                         return -EOPNOTSUPP;
2685
2686                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2687                          0xff);
2688                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2689                          IPPROTO_UDP);
2690
2691                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2692                          ntohs(ib_spec->tcp_udp.mask.src_port));
2693                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2694                          ntohs(ib_spec->tcp_udp.val.src_port));
2695
2696                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2697                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2698                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2699                          ntohs(ib_spec->tcp_udp.val.dst_port));
2700                 break;
2701         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2702                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2703                                          LAST_TUNNEL_FIELD))
2704                         return -EOPNOTSUPP;
2705
2706                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2707                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2708                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2709                          ntohl(ib_spec->tunnel.val.tunnel_id));
2710                 break;
2711         case IB_FLOW_SPEC_ACTION_TAG:
2712                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2713                                          LAST_FLOW_TAG_FIELD))
2714                         return -EOPNOTSUPP;
2715                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2716                         return -EINVAL;
2717
2718                 action->flow_tag = ib_spec->flow_tag.tag_id;
2719                 action->has_flow_tag = true;
2720                 break;
2721         case IB_FLOW_SPEC_ACTION_DROP:
2722                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2723                                          LAST_DROP_FIELD))
2724                         return -EOPNOTSUPP;
2725                 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2726                 break;
2727         case IB_FLOW_SPEC_ACTION_HANDLE:
2728                 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2729                 if (ret)
2730                         return ret;
2731                 break;
2732         default:
2733                 return -EINVAL;
2734         }
2735
2736         return 0;
2737 }
2738
2739 /* If a flow could catch both multicast and unicast packets,
2740  * it won't fall into the multicast flow steering table and this rule
2741  * could steal other multicast packets.
2742  */
2743 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2744 {
2745         union ib_flow_spec *flow_spec;
2746
2747         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2748             ib_attr->num_of_specs < 1)
2749                 return false;
2750
2751         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2752         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2753                 struct ib_flow_spec_ipv4 *ipv4_spec;
2754
2755                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2756                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2757                         return true;
2758
2759                 return false;
2760         }
2761
2762         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2763                 struct ib_flow_spec_eth *eth_spec;
2764
2765                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2766                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2767                        is_multicast_ether_addr(eth_spec->val.dst_mac);
2768         }
2769
2770         return false;
2771 }
2772
2773 enum valid_spec {
2774         VALID_SPEC_INVALID,
2775         VALID_SPEC_VALID,
2776         VALID_SPEC_NA,
2777 };
2778
2779 static enum valid_spec
2780 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2781                      const struct mlx5_flow_spec *spec,
2782                      const struct mlx5_flow_act *flow_act,
2783                      bool egress)
2784 {
2785         const u32 *match_c = spec->match_criteria;
2786         bool is_crypto =
2787                 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2788                                      MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2789         bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2790         bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2791
2792         /*
2793          * Currently only crypto is supported in egress, when regular egress
2794          * rules would be supported, always return VALID_SPEC_NA.
2795          */
2796         if (!is_crypto)
2797                 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2798
2799         return is_crypto && is_ipsec &&
2800                 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2801                 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2802 }
2803
2804 static bool is_valid_spec(struct mlx5_core_dev *mdev,
2805                           const struct mlx5_flow_spec *spec,
2806                           const struct mlx5_flow_act *flow_act,
2807                           bool egress)
2808 {
2809         /* We curretly only support ipsec egress flow */
2810         return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2811 }
2812
2813 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2814                                const struct ib_flow_attr *flow_attr,
2815                                bool check_inner)
2816 {
2817         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2818         int match_ipv = check_inner ?
2819                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2820                                         ft_field_support.inner_ip_version) :
2821                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2822                                         ft_field_support.outer_ip_version);
2823         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2824         bool ipv4_spec_valid, ipv6_spec_valid;
2825         unsigned int ip_spec_type = 0;
2826         bool has_ethertype = false;
2827         unsigned int spec_index;
2828         bool mask_valid = true;
2829         u16 eth_type = 0;
2830         bool type_valid;
2831
2832         /* Validate that ethertype is correct */
2833         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2834                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2835                     ib_spec->eth.mask.ether_type) {
2836                         mask_valid = (ib_spec->eth.mask.ether_type ==
2837                                       htons(0xffff));
2838                         has_ethertype = true;
2839                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2840                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2841                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2842                         ip_spec_type = ib_spec->type;
2843                 }
2844                 ib_spec = (void *)ib_spec + ib_spec->size;
2845         }
2846
2847         type_valid = (!has_ethertype) || (!ip_spec_type);
2848         if (!type_valid && mask_valid) {
2849                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2850                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2851                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2852                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2853
2854                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2855                              (((eth_type == ETH_P_MPLS_UC) ||
2856                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2857         }
2858
2859         return type_valid;
2860 }
2861
2862 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2863                           const struct ib_flow_attr *flow_attr)
2864 {
2865         return is_valid_ethertype(mdev, flow_attr, false) &&
2866                is_valid_ethertype(mdev, flow_attr, true);
2867 }
2868
2869 static void put_flow_table(struct mlx5_ib_dev *dev,
2870                            struct mlx5_ib_flow_prio *prio, bool ft_added)
2871 {
2872         prio->refcount -= !!ft_added;
2873         if (!prio->refcount) {
2874                 mlx5_destroy_flow_table(prio->flow_table);
2875                 prio->flow_table = NULL;
2876         }
2877 }
2878
2879 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2880 {
2881         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2882         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2883                                                           struct mlx5_ib_flow_handler,
2884                                                           ibflow);
2885         struct mlx5_ib_flow_handler *iter, *tmp;
2886
2887         mutex_lock(&dev->flow_db->lock);
2888
2889         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2890                 mlx5_del_flow_rules(iter->rule);
2891                 put_flow_table(dev, iter->prio, true);
2892                 list_del(&iter->list);
2893                 kfree(iter);
2894         }
2895
2896         mlx5_del_flow_rules(handler->rule);
2897         put_flow_table(dev, handler->prio, true);
2898         mutex_unlock(&dev->flow_db->lock);
2899
2900         kfree(handler);
2901
2902         return 0;
2903 }
2904
2905 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2906 {
2907         priority *= 2;
2908         if (!dont_trap)
2909                 priority++;
2910         return priority;
2911 }
2912
2913 enum flow_table_type {
2914         MLX5_IB_FT_RX,
2915         MLX5_IB_FT_TX
2916 };
2917
2918 #define MLX5_FS_MAX_TYPES        6
2919 #define MLX5_FS_MAX_ENTRIES      BIT(16)
2920 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2921                                                 struct ib_flow_attr *flow_attr,
2922                                                 enum flow_table_type ft_type)
2923 {
2924         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2925         struct mlx5_flow_namespace *ns = NULL;
2926         struct mlx5_ib_flow_prio *prio;
2927         struct mlx5_flow_table *ft;
2928         int max_table_size;
2929         int num_entries;
2930         int num_groups;
2931         int priority;
2932         int err = 0;
2933
2934         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2935                                                        log_max_ft_size));
2936         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2937                 if (ft_type == MLX5_IB_FT_TX)
2938                         priority = 0;
2939                 else if (flow_is_multicast_only(flow_attr) &&
2940                          !dont_trap)
2941                         priority = MLX5_IB_FLOW_MCAST_PRIO;
2942                 else
2943                         priority = ib_prio_to_core_prio(flow_attr->priority,
2944                                                         dont_trap);
2945                 ns = mlx5_get_flow_namespace(dev->mdev,
2946                                              ft_type == MLX5_IB_FT_TX ?
2947                                              MLX5_FLOW_NAMESPACE_EGRESS :
2948                                              MLX5_FLOW_NAMESPACE_BYPASS);
2949                 num_entries = MLX5_FS_MAX_ENTRIES;
2950                 num_groups = MLX5_FS_MAX_TYPES;
2951                 prio = &dev->flow_db->prios[priority];
2952         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2953                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2954                 ns = mlx5_get_flow_namespace(dev->mdev,
2955                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
2956                 build_leftovers_ft_param(&priority,
2957                                          &num_entries,
2958                                          &num_groups);
2959                 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2960         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2961                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2962                                         allow_sniffer_and_nic_rx_shared_tir))
2963                         return ERR_PTR(-ENOTSUPP);
2964
2965                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2966                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2967                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2968
2969                 prio = &dev->flow_db->sniffer[ft_type];
2970                 priority = 0;
2971                 num_entries = 1;
2972                 num_groups = 1;
2973         }
2974
2975         if (!ns)
2976                 return ERR_PTR(-ENOTSUPP);
2977
2978         if (num_entries > max_table_size)
2979                 return ERR_PTR(-ENOMEM);
2980
2981         ft = prio->flow_table;
2982         if (!ft) {
2983                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2984                                                          num_entries,
2985                                                          num_groups,
2986                                                          0, 0);
2987
2988                 if (!IS_ERR(ft)) {
2989                         prio->refcount = 0;
2990                         prio->flow_table = ft;
2991                 } else {
2992                         err = PTR_ERR(ft);
2993                 }
2994         }
2995
2996         return err ? ERR_PTR(err) : prio;
2997 }
2998
2999 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3000                             struct mlx5_flow_spec *spec,
3001                             u32 underlay_qpn)
3002 {
3003         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3004                                            spec->match_criteria,
3005                                            misc_parameters);
3006         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3007                                            misc_parameters);
3008
3009         if (underlay_qpn &&
3010             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3011                                       ft_field_support.bth_dst_qp)) {
3012                 MLX5_SET(fte_match_set_misc,
3013                          misc_params_v, bth_dst_qp, underlay_qpn);
3014                 MLX5_SET(fte_match_set_misc,
3015                          misc_params_c, bth_dst_qp, 0xffffff);
3016         }
3017 }
3018
3019 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3020                                                       struct mlx5_ib_flow_prio *ft_prio,
3021                                                       const struct ib_flow_attr *flow_attr,
3022                                                       struct mlx5_flow_destination *dst,
3023                                                       u32 underlay_qpn)
3024 {
3025         struct mlx5_flow_table  *ft = ft_prio->flow_table;
3026         struct mlx5_ib_flow_handler *handler;
3027         struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3028         struct mlx5_flow_spec *spec;
3029         struct mlx5_flow_destination *rule_dst = dst;
3030         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3031         unsigned int spec_index;
3032         int err = 0;
3033         int dest_num = 1;
3034         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3035
3036         if (!is_valid_attr(dev->mdev, flow_attr))
3037                 return ERR_PTR(-EINVAL);
3038
3039         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3040         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3041         if (!handler || !spec) {
3042                 err = -ENOMEM;
3043                 goto free;
3044         }
3045
3046         INIT_LIST_HEAD(&handler->list);
3047
3048         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3049                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3050                                       spec->match_value,
3051                                       ib_flow, flow_attr, &flow_act);
3052                 if (err < 0)
3053                         goto free;
3054
3055                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3056         }
3057
3058         if (!flow_is_multicast_only(flow_attr))
3059                 set_underlay_qp(dev, spec, underlay_qpn);
3060
3061         if (dev->rep) {
3062                 void *misc;
3063
3064                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3065                                     misc_parameters);
3066                 MLX5_SET(fte_match_set_misc, misc, source_port,
3067                          dev->rep->vport);
3068                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3069                                     misc_parameters);
3070                 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3071         }
3072
3073         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3074
3075         if (is_egress &&
3076             !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3077                 err = -EINVAL;
3078                 goto free;
3079         }
3080
3081         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3082                 rule_dst = NULL;
3083                 dest_num = 0;
3084         } else {
3085                 if (is_egress)
3086                         flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3087                 else
3088                         flow_act.action |=
3089                                 dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3090                                         MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3091         }
3092
3093         if (flow_act.has_flow_tag &&
3094             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3095              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3096                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3097                              flow_act.flow_tag, flow_attr->type);
3098                 err = -EINVAL;
3099                 goto free;
3100         }
3101         handler->rule = mlx5_add_flow_rules(ft, spec,
3102                                             &flow_act,
3103                                             rule_dst, dest_num);
3104
3105         if (IS_ERR(handler->rule)) {
3106                 err = PTR_ERR(handler->rule);
3107                 goto free;
3108         }
3109
3110         ft_prio->refcount++;
3111         handler->prio = ft_prio;
3112
3113         ft_prio->flow_table = ft;
3114 free:
3115         if (err)
3116                 kfree(handler);
3117         kvfree(spec);
3118         return err ? ERR_PTR(err) : handler;
3119 }
3120
3121 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3122                                                      struct mlx5_ib_flow_prio *ft_prio,
3123                                                      const struct ib_flow_attr *flow_attr,
3124                                                      struct mlx5_flow_destination *dst)
3125 {
3126         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0);
3127 }
3128
3129 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3130                                                           struct mlx5_ib_flow_prio *ft_prio,
3131                                                           struct ib_flow_attr *flow_attr,
3132                                                           struct mlx5_flow_destination *dst)
3133 {
3134         struct mlx5_ib_flow_handler *handler_dst = NULL;
3135         struct mlx5_ib_flow_handler *handler = NULL;
3136
3137         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3138         if (!IS_ERR(handler)) {
3139                 handler_dst = create_flow_rule(dev, ft_prio,
3140                                                flow_attr, dst);
3141                 if (IS_ERR(handler_dst)) {
3142                         mlx5_del_flow_rules(handler->rule);
3143                         ft_prio->refcount--;
3144                         kfree(handler);
3145                         handler = handler_dst;
3146                 } else {
3147                         list_add(&handler_dst->list, &handler->list);
3148                 }
3149         }
3150
3151         return handler;
3152 }
3153 enum {
3154         LEFTOVERS_MC,
3155         LEFTOVERS_UC,
3156 };
3157
3158 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3159                                                           struct mlx5_ib_flow_prio *ft_prio,
3160                                                           struct ib_flow_attr *flow_attr,
3161                                                           struct mlx5_flow_destination *dst)
3162 {
3163         struct mlx5_ib_flow_handler *handler_ucast = NULL;
3164         struct mlx5_ib_flow_handler *handler = NULL;
3165
3166         static struct {
3167                 struct ib_flow_attr     flow_attr;
3168                 struct ib_flow_spec_eth eth_flow;
3169         } leftovers_specs[] = {
3170                 [LEFTOVERS_MC] = {
3171                         .flow_attr = {
3172                                 .num_of_specs = 1,
3173                                 .size = sizeof(leftovers_specs[0])
3174                         },
3175                         .eth_flow = {
3176                                 .type = IB_FLOW_SPEC_ETH,
3177                                 .size = sizeof(struct ib_flow_spec_eth),
3178                                 .mask = {.dst_mac = {0x1} },
3179                                 .val =  {.dst_mac = {0x1} }
3180                         }
3181                 },
3182                 [LEFTOVERS_UC] = {
3183                         .flow_attr = {
3184                                 .num_of_specs = 1,
3185                                 .size = sizeof(leftovers_specs[0])
3186                         },
3187                         .eth_flow = {
3188                                 .type = IB_FLOW_SPEC_ETH,
3189                                 .size = sizeof(struct ib_flow_spec_eth),
3190                                 .mask = {.dst_mac = {0x1} },
3191                                 .val = {.dst_mac = {} }
3192                         }
3193                 }
3194         };
3195
3196         handler = create_flow_rule(dev, ft_prio,
3197                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
3198                                    dst);
3199         if (!IS_ERR(handler) &&
3200             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3201                 handler_ucast = create_flow_rule(dev, ft_prio,
3202                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
3203                                                  dst);
3204                 if (IS_ERR(handler_ucast)) {
3205                         mlx5_del_flow_rules(handler->rule);
3206                         ft_prio->refcount--;
3207                         kfree(handler);
3208                         handler = handler_ucast;
3209                 } else {
3210                         list_add(&handler_ucast->list, &handler->list);
3211                 }
3212         }
3213
3214         return handler;
3215 }
3216
3217 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3218                                                         struct mlx5_ib_flow_prio *ft_rx,
3219                                                         struct mlx5_ib_flow_prio *ft_tx,
3220                                                         struct mlx5_flow_destination *dst)
3221 {
3222         struct mlx5_ib_flow_handler *handler_rx;
3223         struct mlx5_ib_flow_handler *handler_tx;
3224         int err;
3225         static const struct ib_flow_attr flow_attr  = {
3226                 .num_of_specs = 0,
3227                 .size = sizeof(flow_attr)
3228         };
3229
3230         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3231         if (IS_ERR(handler_rx)) {
3232                 err = PTR_ERR(handler_rx);
3233                 goto err;
3234         }
3235
3236         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3237         if (IS_ERR(handler_tx)) {
3238                 err = PTR_ERR(handler_tx);
3239                 goto err_tx;
3240         }
3241
3242         list_add(&handler_tx->list, &handler_rx->list);
3243
3244         return handler_rx;
3245
3246 err_tx:
3247         mlx5_del_flow_rules(handler_rx->rule);
3248         ft_rx->refcount--;
3249         kfree(handler_rx);
3250 err:
3251         return ERR_PTR(err);
3252 }
3253
3254 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3255                                            struct ib_flow_attr *flow_attr,
3256                                            int domain)
3257 {
3258         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3259         struct mlx5_ib_qp *mqp = to_mqp(qp);
3260         struct mlx5_ib_flow_handler *handler = NULL;
3261         struct mlx5_flow_destination *dst = NULL;
3262         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3263         struct mlx5_ib_flow_prio *ft_prio;
3264         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3265         int err;
3266         int underlay_qpn;
3267
3268         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
3269                 return ERR_PTR(-ENOMEM);
3270
3271         if (domain != IB_FLOW_DOMAIN_USER ||
3272             flow_attr->port > dev->num_ports ||
3273             (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3274                                   IB_FLOW_ATTR_FLAGS_EGRESS)))
3275                 return ERR_PTR(-EINVAL);
3276
3277         if (is_egress &&
3278             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3279              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT))
3280                 return ERR_PTR(-EINVAL);
3281
3282         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3283         if (!dst)
3284                 return ERR_PTR(-ENOMEM);
3285
3286         mutex_lock(&dev->flow_db->lock);
3287
3288         ft_prio = get_flow_table(dev, flow_attr,
3289                                  is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3290         if (IS_ERR(ft_prio)) {
3291                 err = PTR_ERR(ft_prio);
3292                 goto unlock;
3293         }
3294         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3295                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3296                 if (IS_ERR(ft_prio_tx)) {
3297                         err = PTR_ERR(ft_prio_tx);
3298                         ft_prio_tx = NULL;
3299                         goto destroy_ft;
3300                 }
3301         }
3302
3303         if (is_egress) {
3304                 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3305         } else {
3306                 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3307                 if (mqp->flags & MLX5_IB_QP_RSS)
3308                         dst->tir_num = mqp->rss_qp.tirn;
3309                 else
3310                         dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3311         }
3312
3313         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3314                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3315                         handler = create_dont_trap_rule(dev, ft_prio,
3316                                                         flow_attr, dst);
3317                 } else {
3318                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3319                                         mqp->underlay_qpn : 0;
3320                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3321                                                     dst, underlay_qpn);
3322                 }
3323         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3324                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3325                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3326                                                 dst);
3327         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3328                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3329         } else {
3330                 err = -EINVAL;
3331                 goto destroy_ft;
3332         }
3333
3334         if (IS_ERR(handler)) {
3335                 err = PTR_ERR(handler);
3336                 handler = NULL;
3337                 goto destroy_ft;
3338         }
3339
3340         mutex_unlock(&dev->flow_db->lock);
3341         kfree(dst);
3342
3343         return &handler->ibflow;
3344
3345 destroy_ft:
3346         put_flow_table(dev, ft_prio, false);
3347         if (ft_prio_tx)
3348                 put_flow_table(dev, ft_prio_tx, false);
3349 unlock:
3350         mutex_unlock(&dev->flow_db->lock);
3351         kfree(dst);
3352         kfree(handler);
3353         return ERR_PTR(err);
3354 }
3355
3356 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3357 {
3358         u32 flags = 0;
3359
3360         if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3361                 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3362
3363         return flags;
3364 }
3365
3366 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED      MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3367 static struct ib_flow_action *
3368 mlx5_ib_create_flow_action_esp(struct ib_device *device,
3369                                const struct ib_flow_action_attrs_esp *attr,
3370                                struct uverbs_attr_bundle *attrs)
3371 {
3372         struct mlx5_ib_dev *mdev = to_mdev(device);
3373         struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3374         struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3375         struct mlx5_ib_flow_action *action;
3376         u64 action_flags;
3377         u64 flags;
3378         int err = 0;
3379
3380         if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs,
3381                                                 MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS)))
3382                 return ERR_PTR(-EFAULT);
3383
3384         if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1))
3385                 return ERR_PTR(-EOPNOTSUPP);
3386
3387         flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3388
3389         /* We current only support a subset of the standard features. Only a
3390          * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3391          * (with overlap). Full offload mode isn't supported.
3392          */
3393         if (!attr->keymat || attr->replay || attr->encap ||
3394             attr->spi || attr->seq || attr->tfc_pad ||
3395             attr->hard_limit_pkts ||
3396             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3397                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3398                 return ERR_PTR(-EOPNOTSUPP);
3399
3400         if (attr->keymat->protocol !=
3401             IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3402                 return ERR_PTR(-EOPNOTSUPP);
3403
3404         aes_gcm = &attr->keymat->keymat.aes_gcm;
3405
3406         if (aes_gcm->icv_len != 16 ||
3407             aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3408                 return ERR_PTR(-EOPNOTSUPP);
3409
3410         action = kmalloc(sizeof(*action), GFP_KERNEL);
3411         if (!action)
3412                 return ERR_PTR(-ENOMEM);
3413
3414         action->esp_aes_gcm.ib_flags = attr->flags;
3415         memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3416                sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3417         accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3418         memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3419                sizeof(accel_attrs.keymat.aes_gcm.salt));
3420         memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3421                sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3422         accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3423         accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3424         accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3425
3426         accel_attrs.esn = attr->esn;
3427         if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3428                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3429         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3430                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3431
3432         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3433                 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3434
3435         action->esp_aes_gcm.ctx =
3436                 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3437         if (IS_ERR(action->esp_aes_gcm.ctx)) {
3438                 err = PTR_ERR(action->esp_aes_gcm.ctx);
3439                 goto err_parse;
3440         }
3441
3442         action->esp_aes_gcm.ib_flags = attr->flags;
3443
3444         return &action->ib_action;
3445
3446 err_parse:
3447         kfree(action);
3448         return ERR_PTR(err);
3449 }
3450
3451 static int
3452 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3453                                const struct ib_flow_action_attrs_esp *attr,
3454                                struct uverbs_attr_bundle *attrs)
3455 {
3456         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3457         struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3458         int err = 0;
3459
3460         if (attr->keymat || attr->replay || attr->encap ||
3461             attr->spi || attr->seq || attr->tfc_pad ||
3462             attr->hard_limit_pkts ||
3463             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3464                              IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3465                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3466                 return -EOPNOTSUPP;
3467
3468         /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3469          * be modified.
3470          */
3471         if (!(maction->esp_aes_gcm.ib_flags &
3472               IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3473             attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3474                            IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3475                 return -EINVAL;
3476
3477         memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3478                sizeof(accel_attrs));
3479
3480         accel_attrs.esn = attr->esn;
3481         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3482                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3483         else
3484                 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3485
3486         err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3487                                          &accel_attrs);
3488         if (err)
3489                 return err;
3490
3491         maction->esp_aes_gcm.ib_flags &=
3492                 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3493         maction->esp_aes_gcm.ib_flags |=
3494                 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3495
3496         return 0;
3497 }
3498
3499 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3500 {
3501         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3502
3503         switch (action->type) {
3504         case IB_FLOW_ACTION_ESP:
3505                 /*
3506                  * We only support aes_gcm by now, so we implicitly know this is
3507                  * the underline crypto.
3508                  */
3509                 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
3510                 break;
3511         default:
3512                 WARN_ON(true);
3513                 break;
3514         }
3515
3516         kfree(maction);
3517         return 0;
3518 }
3519
3520 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3521 {
3522         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3523         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
3524         int err;
3525
3526         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3527                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3528                 return -EOPNOTSUPP;
3529         }
3530
3531         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
3532         if (err)
3533                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3534                              ibqp->qp_num, gid->raw);
3535
3536         return err;
3537 }
3538
3539 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3540 {
3541         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3542         int err;
3543
3544         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
3545         if (err)
3546                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3547                              ibqp->qp_num, gid->raw);
3548
3549         return err;
3550 }
3551
3552 static int init_node_data(struct mlx5_ib_dev *dev)
3553 {
3554         int err;
3555
3556         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
3557         if (err)
3558                 return err;
3559
3560         dev->mdev->rev_id = dev->mdev->pdev->revision;
3561
3562         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
3563 }
3564
3565 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3566                              char *buf)
3567 {
3568         struct mlx5_ib_dev *dev =
3569                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3570
3571         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
3572 }
3573
3574 static ssize_t show_reg_pages(struct device *device,
3575                               struct device_attribute *attr, char *buf)
3576 {
3577         struct mlx5_ib_dev *dev =
3578                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3579
3580         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
3581 }
3582
3583 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3584                         char *buf)
3585 {
3586         struct mlx5_ib_dev *dev =
3587                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3588         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
3589 }
3590
3591 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3592                         char *buf)
3593 {
3594         struct mlx5_ib_dev *dev =
3595                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3596         return sprintf(buf, "%x\n", dev->mdev->rev_id);
3597 }
3598
3599 static ssize_t show_board(struct device *device, struct device_attribute *attr,
3600                           char *buf)
3601 {
3602         struct mlx5_ib_dev *dev =
3603                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3604         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
3605                        dev->mdev->board_id);
3606 }
3607
3608 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
3609 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
3610 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
3611 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3612 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3613
3614 static struct device_attribute *mlx5_class_attributes[] = {
3615         &dev_attr_hw_rev,
3616         &dev_attr_hca_type,
3617         &dev_attr_board_id,
3618         &dev_attr_fw_pages,
3619         &dev_attr_reg_pages,
3620 };
3621
3622 static void pkey_change_handler(struct work_struct *work)
3623 {
3624         struct mlx5_ib_port_resources *ports =
3625                 container_of(work, struct mlx5_ib_port_resources,
3626                              pkey_change_work);
3627
3628         mutex_lock(&ports->devr->mutex);
3629         mlx5_ib_gsi_pkey_change(ports->gsi);
3630         mutex_unlock(&ports->devr->mutex);
3631 }
3632
3633 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3634 {
3635         struct mlx5_ib_qp *mqp;
3636         struct mlx5_ib_cq *send_mcq, *recv_mcq;
3637         struct mlx5_core_cq *mcq;
3638         struct list_head cq_armed_list;
3639         unsigned long flags_qp;
3640         unsigned long flags_cq;
3641         unsigned long flags;
3642
3643         INIT_LIST_HEAD(&cq_armed_list);
3644
3645         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3646         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3647         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3648                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3649                 if (mqp->sq.tail != mqp->sq.head) {
3650                         send_mcq = to_mcq(mqp->ibqp.send_cq);
3651                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
3652                         if (send_mcq->mcq.comp &&
3653                             mqp->ibqp.send_cq->comp_handler) {
3654                                 if (!send_mcq->mcq.reset_notify_added) {
3655                                         send_mcq->mcq.reset_notify_added = 1;
3656                                         list_add_tail(&send_mcq->mcq.reset_notify,
3657                                                       &cq_armed_list);
3658                                 }
3659                         }
3660                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3661                 }
3662                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3663                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3664                 /* no handling is needed for SRQ */
3665                 if (!mqp->ibqp.srq) {
3666                         if (mqp->rq.tail != mqp->rq.head) {
3667                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3668                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3669                                 if (recv_mcq->mcq.comp &&
3670                                     mqp->ibqp.recv_cq->comp_handler) {
3671                                         if (!recv_mcq->mcq.reset_notify_added) {
3672                                                 recv_mcq->mcq.reset_notify_added = 1;
3673                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
3674                                                               &cq_armed_list);
3675                                         }
3676                                 }
3677                                 spin_unlock_irqrestore(&recv_mcq->lock,
3678                                                        flags_cq);
3679                         }
3680                 }
3681                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3682         }
3683         /*At that point all inflight post send were put to be executed as of we
3684          * lock/unlock above locks Now need to arm all involved CQs.
3685          */
3686         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3687                 mcq->comp(mcq);
3688         }
3689         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3690 }
3691
3692 static void delay_drop_handler(struct work_struct *work)
3693 {
3694         int err;
3695         struct mlx5_ib_delay_drop *delay_drop =
3696                 container_of(work, struct mlx5_ib_delay_drop,
3697                              delay_drop_work);
3698
3699         atomic_inc(&delay_drop->events_cnt);
3700
3701         mutex_lock(&delay_drop->lock);
3702         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3703                                        delay_drop->timeout);
3704         if (err) {
3705                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3706                              delay_drop->timeout);
3707                 delay_drop->activate = false;
3708         }
3709         mutex_unlock(&delay_drop->lock);
3710 }
3711
3712 static void mlx5_ib_handle_event(struct work_struct *_work)
3713 {
3714         struct mlx5_ib_event_work *work =
3715                 container_of(_work, struct mlx5_ib_event_work, work);
3716         struct mlx5_ib_dev *ibdev;
3717         struct ib_event ibev;
3718         bool fatal = false;
3719         u8 port = (u8)work->param;
3720
3721         if (mlx5_core_is_mp_slave(work->dev)) {
3722                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3723                 if (!ibdev)
3724                         goto out;
3725         } else {
3726                 ibdev = work->context;
3727         }
3728
3729         switch (work->event) {
3730         case MLX5_DEV_EVENT_SYS_ERROR:
3731                 ibev.event = IB_EVENT_DEVICE_FATAL;
3732                 mlx5_ib_handle_internal_error(ibdev);
3733                 fatal = true;
3734                 break;
3735
3736         case MLX5_DEV_EVENT_PORT_UP:
3737         case MLX5_DEV_EVENT_PORT_DOWN:
3738         case MLX5_DEV_EVENT_PORT_INITIALIZED:
3739                 /* In RoCE, port up/down events are handled in
3740                  * mlx5_netdev_event().
3741                  */
3742                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3743                         IB_LINK_LAYER_ETHERNET)
3744                         goto out;
3745
3746                 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
3747                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3748                 break;
3749
3750         case MLX5_DEV_EVENT_LID_CHANGE:
3751                 ibev.event = IB_EVENT_LID_CHANGE;
3752                 break;
3753
3754         case MLX5_DEV_EVENT_PKEY_CHANGE:
3755                 ibev.event = IB_EVENT_PKEY_CHANGE;
3756                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
3757                 break;
3758
3759         case MLX5_DEV_EVENT_GUID_CHANGE:
3760                 ibev.event = IB_EVENT_GID_CHANGE;
3761                 break;
3762
3763         case MLX5_DEV_EVENT_CLIENT_REREG:
3764                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
3765                 break;
3766         case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3767                 schedule_work(&ibdev->delay_drop.delay_drop_work);
3768                 goto out;
3769         default:
3770                 goto out;
3771         }
3772
3773         ibev.device           = &ibdev->ib_dev;
3774         ibev.element.port_num = port;
3775
3776         if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
3777                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
3778                 goto out;
3779         }
3780
3781         if (ibdev->ib_active)
3782                 ib_dispatch_event(&ibev);
3783
3784         if (fatal)
3785                 ibdev->ib_active = false;
3786 out:
3787         kfree(work);
3788 }
3789
3790 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3791                           enum mlx5_dev_event event, unsigned long param)
3792 {
3793         struct mlx5_ib_event_work *work;
3794
3795         work = kmalloc(sizeof(*work), GFP_ATOMIC);
3796         if (!work)
3797                 return;
3798
3799         INIT_WORK(&work->work, mlx5_ib_handle_event);
3800         work->dev = dev;
3801         work->param = param;
3802         work->context = context;
3803         work->event = event;
3804
3805         queue_work(mlx5_ib_event_wq, &work->work);
3806 }
3807
3808 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3809 {
3810         struct mlx5_hca_vport_context vport_ctx;
3811         int err;
3812         int port;
3813
3814         for (port = 1; port <= dev->num_ports; port++) {
3815                 dev->mdev->port_caps[port - 1].has_smi = false;
3816                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
3817                     MLX5_CAP_PORT_TYPE_IB) {
3818                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
3819                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
3820                                                                    port, 0,
3821                                                                    &vport_ctx);
3822                                 if (err) {
3823                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
3824                                                     port, err);
3825                                         return err;
3826                                 }
3827                                 dev->mdev->port_caps[port - 1].has_smi =
3828                                         vport_ctx.has_smi;
3829                         } else {
3830                                 dev->mdev->port_caps[port - 1].has_smi = true;
3831                         }
3832                 }
3833         }
3834         return 0;
3835 }
3836
3837 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
3838 {
3839         int port;
3840
3841         for (port = 1; port <= dev->num_ports; port++)
3842                 mlx5_query_ext_port_caps(dev, port);
3843 }
3844
3845 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
3846 {
3847         struct ib_device_attr *dprops = NULL;
3848         struct ib_port_attr *pprops = NULL;
3849         int err = -ENOMEM;
3850         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
3851
3852         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
3853         if (!pprops)
3854                 goto out;
3855
3856         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
3857         if (!dprops)
3858                 goto out;
3859
3860         err = set_has_smi_cap(dev);
3861         if (err)
3862                 goto out;
3863
3864         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
3865         if (err) {
3866                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
3867                 goto out;
3868         }
3869
3870         memset(pprops, 0, sizeof(*pprops));
3871         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
3872         if (err) {
3873                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
3874                              port, err);
3875                 goto out;
3876         }
3877
3878         dev->mdev->port_caps[port - 1].pkey_table_len =
3879                                         dprops->max_pkeys;
3880         dev->mdev->port_caps[port - 1].gid_table_len =
3881                                         pprops->gid_tbl_len;
3882         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
3883                     port, dprops->max_pkeys, pprops->gid_tbl_len);
3884
3885 out:
3886         kfree(pprops);
3887         kfree(dprops);
3888
3889         return err;
3890 }
3891
3892 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
3893 {
3894         int err;
3895
3896         err = mlx5_mr_cache_cleanup(dev);
3897         if (err)
3898                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
3899
3900         if (dev->umrc.qp)
3901                 mlx5_ib_destroy_qp(dev->umrc.qp);
3902         if (dev->umrc.cq)
3903                 ib_free_cq(dev->umrc.cq);
3904         if (dev->umrc.pd)
3905                 ib_dealloc_pd(dev->umrc.pd);
3906 }
3907
3908 enum {
3909         MAX_UMR_WR = 128,
3910 };
3911
3912 static int create_umr_res(struct mlx5_ib_dev *dev)
3913 {
3914         struct ib_qp_init_attr *init_attr = NULL;
3915         struct ib_qp_attr *attr = NULL;
3916         struct ib_pd *pd;
3917         struct ib_cq *cq;
3918         struct ib_qp *qp;
3919         int ret;
3920
3921         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
3922         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
3923         if (!attr || !init_attr) {
3924                 ret = -ENOMEM;
3925                 goto error_0;
3926         }
3927
3928         pd = ib_alloc_pd(&dev->ib_dev, 0);
3929         if (IS_ERR(pd)) {
3930                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
3931                 ret = PTR_ERR(pd);
3932                 goto error_0;
3933         }
3934
3935         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
3936         if (IS_ERR(cq)) {
3937                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
3938                 ret = PTR_ERR(cq);
3939                 goto error_2;
3940         }
3941
3942         init_attr->send_cq = cq;
3943         init_attr->recv_cq = cq;
3944         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
3945         init_attr->cap.max_send_wr = MAX_UMR_WR;
3946         init_attr->cap.max_send_sge = 1;
3947         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
3948         init_attr->port_num = 1;
3949         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
3950         if (IS_ERR(qp)) {
3951                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
3952                 ret = PTR_ERR(qp);
3953                 goto error_3;
3954         }
3955         qp->device     = &dev->ib_dev;
3956         qp->real_qp    = qp;
3957         qp->uobject    = NULL;
3958         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
3959         qp->send_cq    = init_attr->send_cq;
3960         qp->recv_cq    = init_attr->recv_cq;
3961
3962         attr->qp_state = IB_QPS_INIT;
3963         attr->port_num = 1;
3964         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
3965                                 IB_QP_PORT, NULL);
3966         if (ret) {
3967                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
3968                 goto error_4;
3969         }
3970
3971         memset(attr, 0, sizeof(*attr));
3972         attr->qp_state = IB_QPS_RTR;
3973         attr->path_mtu = IB_MTU_256;
3974
3975         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3976         if (ret) {
3977                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
3978                 goto error_4;
3979         }
3980
3981         memset(attr, 0, sizeof(*attr));
3982         attr->qp_state = IB_QPS_RTS;
3983         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
3984         if (ret) {
3985                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
3986                 goto error_4;
3987         }
3988
3989         dev->umrc.qp = qp;
3990         dev->umrc.cq = cq;
3991         dev->umrc.pd = pd;
3992
3993         sema_init(&dev->umrc.sem, MAX_UMR_WR);
3994         ret = mlx5_mr_cache_init(dev);
3995         if (ret) {
3996                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
3997                 goto error_4;
3998         }
3999
4000         kfree(attr);
4001         kfree(init_attr);
4002
4003         return 0;
4004
4005 error_4:
4006         mlx5_ib_destroy_qp(qp);
4007         dev->umrc.qp = NULL;
4008
4009 error_3:
4010         ib_free_cq(cq);
4011         dev->umrc.cq = NULL;
4012
4013 error_2:
4014         ib_dealloc_pd(pd);
4015         dev->umrc.pd = NULL;
4016
4017 error_0:
4018         kfree(attr);
4019         kfree(init_attr);
4020         return ret;
4021 }
4022
4023 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4024 {
4025         switch (umr_fence_cap) {
4026         case MLX5_CAP_UMR_FENCE_NONE:
4027                 return MLX5_FENCE_MODE_NONE;
4028         case MLX5_CAP_UMR_FENCE_SMALL:
4029                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4030         default:
4031                 return MLX5_FENCE_MODE_STRONG_ORDERING;
4032         }
4033 }
4034
4035 static int create_dev_resources(struct mlx5_ib_resources *devr)
4036 {
4037         struct ib_srq_init_attr attr;
4038         struct mlx5_ib_dev *dev;
4039         struct ib_cq_init_attr cq_attr = {.cqe = 1};
4040         int port;
4041         int ret = 0;
4042
4043         dev = container_of(devr, struct mlx5_ib_dev, devr);
4044
4045         mutex_init(&devr->mutex);
4046
4047         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4048         if (IS_ERR(devr->p0)) {
4049                 ret = PTR_ERR(devr->p0);
4050                 goto error0;
4051         }
4052         devr->p0->device  = &dev->ib_dev;
4053         devr->p0->uobject = NULL;
4054         atomic_set(&devr->p0->usecnt, 0);
4055
4056         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
4057         if (IS_ERR(devr->c0)) {
4058                 ret = PTR_ERR(devr->c0);
4059                 goto error1;
4060         }
4061         devr->c0->device        = &dev->ib_dev;
4062         devr->c0->uobject       = NULL;
4063         devr->c0->comp_handler  = NULL;
4064         devr->c0->event_handler = NULL;
4065         devr->c0->cq_context    = NULL;
4066         atomic_set(&devr->c0->usecnt, 0);
4067
4068         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4069         if (IS_ERR(devr->x0)) {
4070                 ret = PTR_ERR(devr->x0);
4071                 goto error2;
4072         }
4073         devr->x0->device = &dev->ib_dev;
4074         devr->x0->inode = NULL;
4075         atomic_set(&devr->x0->usecnt, 0);
4076         mutex_init(&devr->x0->tgt_qp_mutex);
4077         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4078
4079         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4080         if (IS_ERR(devr->x1)) {
4081                 ret = PTR_ERR(devr->x1);
4082                 goto error3;
4083         }
4084         devr->x1->device = &dev->ib_dev;
4085         devr->x1->inode = NULL;
4086         atomic_set(&devr->x1->usecnt, 0);
4087         mutex_init(&devr->x1->tgt_qp_mutex);
4088         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4089
4090         memset(&attr, 0, sizeof(attr));
4091         attr.attr.max_sge = 1;
4092         attr.attr.max_wr = 1;
4093         attr.srq_type = IB_SRQT_XRC;
4094         attr.ext.cq = devr->c0;
4095         attr.ext.xrc.xrcd = devr->x0;
4096
4097         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4098         if (IS_ERR(devr->s0)) {
4099                 ret = PTR_ERR(devr->s0);
4100                 goto error4;
4101         }
4102         devr->s0->device        = &dev->ib_dev;
4103         devr->s0->pd            = devr->p0;
4104         devr->s0->uobject       = NULL;
4105         devr->s0->event_handler = NULL;
4106         devr->s0->srq_context   = NULL;
4107         devr->s0->srq_type      = IB_SRQT_XRC;
4108         devr->s0->ext.xrc.xrcd  = devr->x0;
4109         devr->s0->ext.cq        = devr->c0;
4110         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4111         atomic_inc(&devr->s0->ext.cq->usecnt);
4112         atomic_inc(&devr->p0->usecnt);
4113         atomic_set(&devr->s0->usecnt, 0);
4114
4115         memset(&attr, 0, sizeof(attr));
4116         attr.attr.max_sge = 1;
4117         attr.attr.max_wr = 1;
4118         attr.srq_type = IB_SRQT_BASIC;
4119         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4120         if (IS_ERR(devr->s1)) {
4121                 ret = PTR_ERR(devr->s1);
4122                 goto error5;
4123         }
4124         devr->s1->device        = &dev->ib_dev;
4125         devr->s1->pd            = devr->p0;
4126         devr->s1->uobject       = NULL;
4127         devr->s1->event_handler = NULL;
4128         devr->s1->srq_context   = NULL;
4129         devr->s1->srq_type      = IB_SRQT_BASIC;
4130         devr->s1->ext.cq        = devr->c0;
4131         atomic_inc(&devr->p0->usecnt);
4132         atomic_set(&devr->s1->usecnt, 0);
4133
4134         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4135                 INIT_WORK(&devr->ports[port].pkey_change_work,
4136                           pkey_change_handler);
4137                 devr->ports[port].devr = devr;
4138         }
4139
4140         return 0;
4141
4142 error5:
4143         mlx5_ib_destroy_srq(devr->s0);
4144 error4:
4145         mlx5_ib_dealloc_xrcd(devr->x1);
4146 error3:
4147         mlx5_ib_dealloc_xrcd(devr->x0);
4148 error2:
4149         mlx5_ib_destroy_cq(devr->c0);
4150 error1:
4151         mlx5_ib_dealloc_pd(devr->p0);
4152 error0:
4153         return ret;
4154 }
4155
4156 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4157 {
4158         struct mlx5_ib_dev *dev =
4159                 container_of(devr, struct mlx5_ib_dev, devr);
4160         int port;
4161
4162         mlx5_ib_destroy_srq(devr->s1);
4163         mlx5_ib_destroy_srq(devr->s0);
4164         mlx5_ib_dealloc_xrcd(devr->x0);
4165         mlx5_ib_dealloc_xrcd(devr->x1);
4166         mlx5_ib_destroy_cq(devr->c0);
4167         mlx5_ib_dealloc_pd(devr->p0);
4168
4169         /* Make sure no change P_Key work items are still executing */
4170         for (port = 0; port < dev->num_ports; ++port)
4171                 cancel_work_sync(&devr->ports[port].pkey_change_work);
4172 }
4173
4174 static u32 get_core_cap_flags(struct ib_device *ibdev)
4175 {
4176         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4177         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4178         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4179         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
4180         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
4181         u32 ret = 0;
4182
4183         if (ll == IB_LINK_LAYER_INFINIBAND)
4184                 return RDMA_CORE_PORT_IBA_IB;
4185
4186         if (raw_support)
4187                 ret = RDMA_CORE_PORT_RAW_PACKET;
4188
4189         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
4190                 return ret;
4191
4192         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
4193                 return ret;
4194
4195         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4196                 ret |= RDMA_CORE_PORT_IBA_ROCE;
4197
4198         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4199                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4200
4201         return ret;
4202 }
4203
4204 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4205                                struct ib_port_immutable *immutable)
4206 {
4207         struct ib_port_attr attr;
4208         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4209         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
4210         int err;
4211
4212         immutable->core_cap_flags = get_core_cap_flags(ibdev);
4213
4214         err = ib_query_port(ibdev, port_num, &attr);
4215         if (err)
4216                 return err;
4217
4218         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4219         immutable->gid_tbl_len = attr.gid_tbl_len;
4220         immutable->core_cap_flags = get_core_cap_flags(ibdev);
4221         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4222                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4223
4224         return 0;
4225 }
4226
4227 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4228                                    struct ib_port_immutable *immutable)
4229 {
4230         struct ib_port_attr attr;
4231         int err;
4232
4233         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4234
4235         err = ib_query_port(ibdev, port_num, &attr);
4236         if (err)
4237                 return err;
4238
4239         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4240         immutable->gid_tbl_len = attr.gid_tbl_len;
4241         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4242
4243         return 0;
4244 }
4245
4246 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
4247 {
4248         struct mlx5_ib_dev *dev =
4249                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
4250         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4251                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4252                  fw_rev_sub(dev->mdev));
4253 }
4254
4255 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
4256 {
4257         struct mlx5_core_dev *mdev = dev->mdev;
4258         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4259                                                                  MLX5_FLOW_NAMESPACE_LAG);
4260         struct mlx5_flow_table *ft;
4261         int err;
4262
4263         if (!ns || !mlx5_lag_is_active(mdev))
4264                 return 0;
4265
4266         err = mlx5_cmd_create_vport_lag(mdev);
4267         if (err)
4268                 return err;
4269
4270         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4271         if (IS_ERR(ft)) {
4272                 err = PTR_ERR(ft);
4273                 goto err_destroy_vport_lag;
4274         }
4275
4276         dev->flow_db->lag_demux_ft = ft;
4277         return 0;
4278
4279 err_destroy_vport_lag:
4280         mlx5_cmd_destroy_vport_lag(mdev);
4281         return err;
4282 }
4283
4284 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
4285 {
4286         struct mlx5_core_dev *mdev = dev->mdev;
4287
4288         if (dev->flow_db->lag_demux_ft) {
4289                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4290                 dev->flow_db->lag_demux_ft = NULL;
4291
4292                 mlx5_cmd_destroy_vport_lag(mdev);
4293         }
4294 }
4295
4296 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4297 {
4298         int err;
4299
4300         dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4301         err = register_netdevice_notifier(&dev->roce[port_num].nb);
4302         if (err) {
4303                 dev->roce[port_num].nb.notifier_call = NULL;
4304                 return err;
4305         }
4306
4307         return 0;
4308 }
4309
4310 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4311 {
4312         if (dev->roce[port_num].nb.notifier_call) {
4313                 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4314                 dev->roce[port_num].nb.notifier_call = NULL;
4315         }
4316 }
4317
4318 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
4319 {
4320         int err;
4321
4322         if (MLX5_CAP_GEN(dev->mdev, roce)) {
4323                 err = mlx5_nic_vport_enable_roce(dev->mdev);
4324                 if (err)
4325                         return err;
4326         }
4327
4328         err = mlx5_eth_lag_init(dev);
4329         if (err)
4330                 goto err_disable_roce;
4331
4332         return 0;
4333
4334 err_disable_roce:
4335         if (MLX5_CAP_GEN(dev->mdev, roce))
4336                 mlx5_nic_vport_disable_roce(dev->mdev);
4337
4338         return err;
4339 }
4340
4341 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
4342 {
4343         mlx5_eth_lag_cleanup(dev);
4344         if (MLX5_CAP_GEN(dev->mdev, roce))
4345                 mlx5_nic_vport_disable_roce(dev->mdev);
4346 }
4347
4348 struct mlx5_ib_counter {
4349         const char *name;
4350         size_t offset;
4351 };
4352
4353 #define INIT_Q_COUNTER(_name)           \
4354         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4355
4356 static const struct mlx5_ib_counter basic_q_cnts[] = {
4357         INIT_Q_COUNTER(rx_write_requests),
4358         INIT_Q_COUNTER(rx_read_requests),
4359         INIT_Q_COUNTER(rx_atomic_requests),
4360         INIT_Q_COUNTER(out_of_buffer),
4361 };
4362
4363 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
4364         INIT_Q_COUNTER(out_of_sequence),
4365 };
4366
4367 static const struct mlx5_ib_counter retrans_q_cnts[] = {
4368         INIT_Q_COUNTER(duplicate_request),
4369         INIT_Q_COUNTER(rnr_nak_retry_err),
4370         INIT_Q_COUNTER(packet_seq_err),
4371         INIT_Q_COUNTER(implied_nak_seq_err),
4372         INIT_Q_COUNTER(local_ack_timeout_err),
4373 };
4374
4375 #define INIT_CONG_COUNTER(_name)                \
4376         { .name = #_name, .offset =     \
4377                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4378
4379 static const struct mlx5_ib_counter cong_cnts[] = {
4380         INIT_CONG_COUNTER(rp_cnp_ignored),
4381         INIT_CONG_COUNTER(rp_cnp_handled),
4382         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4383         INIT_CONG_COUNTER(np_cnp_sent),
4384 };
4385
4386 static const struct mlx5_ib_counter extended_err_cnts[] = {
4387         INIT_Q_COUNTER(resp_local_length_error),
4388         INIT_Q_COUNTER(resp_cqe_error),
4389         INIT_Q_COUNTER(req_cqe_error),
4390         INIT_Q_COUNTER(req_remote_invalid_request),
4391         INIT_Q_COUNTER(req_remote_access_errors),
4392         INIT_Q_COUNTER(resp_remote_access_errors),
4393         INIT_Q_COUNTER(resp_cqe_flush_error),
4394         INIT_Q_COUNTER(req_cqe_flush_error),
4395 };
4396
4397 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
4398 {
4399         int i;
4400
4401         for (i = 0; i < dev->num_ports; i++) {
4402                 if (dev->port[i].cnts.set_id)
4403                         mlx5_core_dealloc_q_counter(dev->mdev,
4404                                                     dev->port[i].cnts.set_id);
4405                 kfree(dev->port[i].cnts.names);
4406                 kfree(dev->port[i].cnts.offsets);
4407         }
4408 }
4409
4410 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4411                                     struct mlx5_ib_counters *cnts)
4412 {
4413         u32 num_counters;
4414
4415         num_counters = ARRAY_SIZE(basic_q_cnts);
4416
4417         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4418                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4419
4420         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4421                 num_counters += ARRAY_SIZE(retrans_q_cnts);
4422
4423         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4424                 num_counters += ARRAY_SIZE(extended_err_cnts);
4425
4426         cnts->num_q_counters = num_counters;
4427
4428         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4429                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4430                 num_counters += ARRAY_SIZE(cong_cnts);
4431         }
4432
4433         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4434         if (!cnts->names)
4435                 return -ENOMEM;
4436
4437         cnts->offsets = kcalloc(num_counters,
4438                                 sizeof(cnts->offsets), GFP_KERNEL);
4439         if (!cnts->offsets)
4440                 goto err_names;
4441
4442         return 0;
4443
4444 err_names:
4445         kfree(cnts->names);
4446         cnts->names = NULL;
4447         return -ENOMEM;
4448 }
4449
4450 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4451                                   const char **names,
4452                                   size_t *offsets)
4453 {
4454         int i;
4455         int j = 0;
4456
4457         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4458                 names[j] = basic_q_cnts[i].name;
4459                 offsets[j] = basic_q_cnts[i].offset;
4460         }
4461
4462         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4463                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4464                         names[j] = out_of_seq_q_cnts[i].name;
4465                         offsets[j] = out_of_seq_q_cnts[i].offset;
4466                 }
4467         }
4468
4469         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4470                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4471                         names[j] = retrans_q_cnts[i].name;
4472                         offsets[j] = retrans_q_cnts[i].offset;
4473                 }
4474         }
4475
4476         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4477                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4478                         names[j] = extended_err_cnts[i].name;
4479                         offsets[j] = extended_err_cnts[i].offset;
4480                 }
4481         }
4482
4483         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4484                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4485                         names[j] = cong_cnts[i].name;
4486                         offsets[j] = cong_cnts[i].offset;
4487                 }
4488         }
4489 }
4490
4491 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
4492 {
4493         int err = 0;
4494         int i;
4495
4496         for (i = 0; i < dev->num_ports; i++) {
4497                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4498                 if (err)
4499                         goto err_alloc;
4500
4501                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4502                                       dev->port[i].cnts.offsets);
4503
4504                 err = mlx5_core_alloc_q_counter(dev->mdev,
4505                                                 &dev->port[i].cnts.set_id);
4506                 if (err) {
4507                         mlx5_ib_warn(dev,
4508                                      "couldn't allocate queue counter for port %d, err %d\n",
4509                                      i + 1, err);
4510                         goto err_alloc;
4511                 }
4512                 dev->port[i].cnts.set_id_valid = true;
4513         }
4514
4515         return 0;
4516
4517 err_alloc:
4518         mlx5_ib_dealloc_counters(dev);
4519         return err;
4520 }
4521
4522 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4523                                                     u8 port_num)
4524 {
4525         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4526         struct mlx5_ib_port *port = &dev->port[port_num - 1];
4527
4528         /* We support only per port stats */
4529         if (port_num == 0)
4530                 return NULL;
4531
4532         return rdma_alloc_hw_stats_struct(port->cnts.names,
4533                                           port->cnts.num_q_counters +
4534                                           port->cnts.num_cong_counters,
4535                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
4536 }
4537
4538 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
4539                                     struct mlx5_ib_port *port,
4540                                     struct rdma_hw_stats *stats)
4541 {
4542         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4543         void *out;
4544         __be32 val;
4545         int ret, i;
4546
4547         out = kvzalloc(outlen, GFP_KERNEL);
4548         if (!out)
4549                 return -ENOMEM;
4550
4551         ret = mlx5_core_query_q_counter(mdev,
4552                                         port->cnts.set_id, 0,
4553                                         out, outlen);
4554         if (ret)
4555                 goto free;
4556
4557         for (i = 0; i < port->cnts.num_q_counters; i++) {
4558                 val = *(__be32 *)(out + port->cnts.offsets[i]);
4559                 stats->value[i] = (u64)be32_to_cpu(val);
4560         }
4561
4562 free:
4563         kvfree(out);
4564         return ret;
4565 }
4566
4567 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4568                                 struct rdma_hw_stats *stats,
4569                                 u8 port_num, int index)
4570 {
4571         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4572         struct mlx5_ib_port *port = &dev->port[port_num - 1];
4573         struct mlx5_core_dev *mdev;
4574         int ret, num_counters;
4575         u8 mdev_port_num;
4576
4577         if (!stats)
4578                 return -EINVAL;
4579
4580         num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4581
4582         /* q_counters are per IB device, query the master mdev */
4583         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
4584         if (ret)
4585                 return ret;
4586
4587         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4588                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4589                                                     &mdev_port_num);
4590                 if (!mdev) {
4591                         /* If port is not affiliated yet, its in down state
4592                          * which doesn't have any counters yet, so it would be
4593                          * zero. So no need to read from the HCA.
4594                          */
4595                         goto done;
4596                 }
4597                 ret = mlx5_lag_query_cong_counters(dev->mdev,
4598                                                    stats->value +
4599                                                    port->cnts.num_q_counters,
4600                                                    port->cnts.num_cong_counters,
4601                                                    port->cnts.offsets +
4602                                                    port->cnts.num_q_counters);
4603
4604                 mlx5_ib_put_native_port_mdev(dev, port_num);
4605                 if (ret)
4606                         return ret;
4607         }
4608
4609 done:
4610         return num_counters;
4611 }
4612
4613 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4614 {
4615         return mlx5_rdma_netdev_free(netdev);
4616 }
4617
4618 static struct net_device*
4619 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4620                           u8 port_num,
4621                           enum rdma_netdev_t type,
4622                           const char *name,
4623                           unsigned char name_assign_type,
4624                           void (*setup)(struct net_device *))
4625 {
4626         struct net_device *netdev;
4627         struct rdma_netdev *rn;
4628
4629         if (type != RDMA_NETDEV_IPOIB)
4630                 return ERR_PTR(-EOPNOTSUPP);
4631
4632         netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4633                                         name, setup);
4634         if (likely(!IS_ERR_OR_NULL(netdev))) {
4635                 rn = netdev_priv(netdev);
4636                 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4637         }
4638         return netdev;
4639 }
4640
4641 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4642 {
4643         if (!dev->delay_drop.dbg)
4644                 return;
4645         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4646         kfree(dev->delay_drop.dbg);
4647         dev->delay_drop.dbg = NULL;
4648 }
4649
4650 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4651 {
4652         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4653                 return;
4654
4655         cancel_work_sync(&dev->delay_drop.delay_drop_work);
4656         delay_drop_debugfs_cleanup(dev);
4657 }
4658
4659 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4660                                        size_t count, loff_t *pos)
4661 {
4662         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4663         char lbuf[20];
4664         int len;
4665
4666         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4667         return simple_read_from_buffer(buf, count, pos, lbuf, len);
4668 }
4669
4670 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4671                                         size_t count, loff_t *pos)
4672 {
4673         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4674         u32 timeout;
4675         u32 var;
4676
4677         if (kstrtouint_from_user(buf, count, 0, &var))
4678                 return -EFAULT;
4679
4680         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4681                         1000);
4682         if (timeout != var)
4683                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4684                             timeout);
4685
4686         delay_drop->timeout = timeout;
4687
4688         return count;
4689 }
4690
4691 static const struct file_operations fops_delay_drop_timeout = {
4692         .owner  = THIS_MODULE,
4693         .open   = simple_open,
4694         .write  = delay_drop_timeout_write,
4695         .read   = delay_drop_timeout_read,
4696 };
4697
4698 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4699 {
4700         struct mlx5_ib_dbg_delay_drop *dbg;
4701
4702         if (!mlx5_debugfs_root)
4703                 return 0;
4704
4705         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4706         if (!dbg)
4707                 return -ENOMEM;
4708
4709         dev->delay_drop.dbg = dbg;
4710
4711         dbg->dir_debugfs =
4712                 debugfs_create_dir("delay_drop",
4713                                    dev->mdev->priv.dbg_root);
4714         if (!dbg->dir_debugfs)
4715                 goto out_debugfs;
4716
4717         dbg->events_cnt_debugfs =
4718                 debugfs_create_atomic_t("num_timeout_events", 0400,
4719                                         dbg->dir_debugfs,
4720                                         &dev->delay_drop.events_cnt);
4721         if (!dbg->events_cnt_debugfs)
4722                 goto out_debugfs;
4723
4724         dbg->rqs_cnt_debugfs =
4725                 debugfs_create_atomic_t("num_rqs", 0400,
4726                                         dbg->dir_debugfs,
4727                                         &dev->delay_drop.rqs_cnt);
4728         if (!dbg->rqs_cnt_debugfs)
4729                 goto out_debugfs;
4730
4731         dbg->timeout_debugfs =
4732                 debugfs_create_file("timeout", 0600,
4733                                     dbg->dir_debugfs,
4734                                     &dev->delay_drop,
4735                                     &fops_delay_drop_timeout);
4736         if (!dbg->timeout_debugfs)
4737                 goto out_debugfs;
4738
4739         return 0;
4740
4741 out_debugfs:
4742         delay_drop_debugfs_cleanup(dev);
4743         return -ENOMEM;
4744 }
4745
4746 static void init_delay_drop(struct mlx5_ib_dev *dev)
4747 {
4748         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4749                 return;
4750
4751         mutex_init(&dev->delay_drop.lock);
4752         dev->delay_drop.dev = dev;
4753         dev->delay_drop.activate = false;
4754         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4755         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4756         atomic_set(&dev->delay_drop.rqs_cnt, 0);
4757         atomic_set(&dev->delay_drop.events_cnt, 0);
4758
4759         if (delay_drop_debugfs_init(dev))
4760                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
4761 }
4762
4763 static const struct cpumask *
4764 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
4765 {
4766         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4767
4768         return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4769 }
4770
4771 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4772 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4773                                       struct mlx5_ib_multiport_info *mpi)
4774 {
4775         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4776         struct mlx5_ib_port *port = &ibdev->port[port_num];
4777         int comps;
4778         int err;
4779         int i;
4780
4781         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4782
4783         spin_lock(&port->mp.mpi_lock);
4784         if (!mpi->ibdev) {
4785                 spin_unlock(&port->mp.mpi_lock);
4786                 return;
4787         }
4788         mpi->ibdev = NULL;
4789
4790         spin_unlock(&port->mp.mpi_lock);
4791         mlx5_remove_netdev_notifier(ibdev, port_num);
4792         spin_lock(&port->mp.mpi_lock);
4793
4794         comps = mpi->mdev_refcnt;
4795         if (comps) {
4796                 mpi->unaffiliate = true;
4797                 init_completion(&mpi->unref_comp);
4798                 spin_unlock(&port->mp.mpi_lock);
4799
4800                 for (i = 0; i < comps; i++)
4801                         wait_for_completion(&mpi->unref_comp);
4802
4803                 spin_lock(&port->mp.mpi_lock);
4804                 mpi->unaffiliate = false;
4805         }
4806
4807         port->mp.mpi = NULL;
4808
4809         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4810
4811         spin_unlock(&port->mp.mpi_lock);
4812
4813         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
4814
4815         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
4816         /* Log an error, still needed to cleanup the pointers and add
4817          * it back to the list.
4818          */
4819         if (err)
4820                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
4821                             port_num + 1);
4822
4823         ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
4824 }
4825
4826 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4827 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
4828                                     struct mlx5_ib_multiport_info *mpi)
4829 {
4830         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4831         int err;
4832
4833         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
4834         if (ibdev->port[port_num].mp.mpi) {
4835                 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
4836                              port_num + 1);
4837                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4838                 return false;
4839         }
4840
4841         ibdev->port[port_num].mp.mpi = mpi;
4842         mpi->ibdev = ibdev;
4843         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
4844
4845         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
4846         if (err)
4847                 goto unbind;
4848
4849         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
4850         if (err)
4851                 goto unbind;
4852
4853         err = mlx5_add_netdev_notifier(ibdev, port_num);
4854         if (err) {
4855                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
4856                             port_num + 1);
4857                 goto unbind;
4858         }
4859
4860         err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
4861         if (err)
4862                 goto unbind;
4863
4864         return true;
4865
4866 unbind:
4867         mlx5_ib_unbind_slave_port(ibdev, mpi);
4868         return false;
4869 }
4870
4871 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
4872 {
4873         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4874         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4875                                                           port_num + 1);
4876         struct mlx5_ib_multiport_info *mpi;
4877         int err;
4878         int i;
4879
4880         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4881                 return 0;
4882
4883         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
4884                                                      &dev->sys_image_guid);
4885         if (err)
4886                 return err;
4887
4888         err = mlx5_nic_vport_enable_roce(dev->mdev);
4889         if (err)
4890                 return err;
4891
4892         mutex_lock(&mlx5_ib_multiport_mutex);
4893         for (i = 0; i < dev->num_ports; i++) {
4894                 bool bound = false;
4895
4896                 /* build a stub multiport info struct for the native port. */
4897                 if (i == port_num) {
4898                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4899                         if (!mpi) {
4900                                 mutex_unlock(&mlx5_ib_multiport_mutex);
4901                                 mlx5_nic_vport_disable_roce(dev->mdev);
4902                                 return -ENOMEM;
4903                         }
4904
4905                         mpi->is_master = true;
4906                         mpi->mdev = dev->mdev;
4907                         mpi->sys_image_guid = dev->sys_image_guid;
4908                         dev->port[i].mp.mpi = mpi;
4909                         mpi->ibdev = dev;
4910                         mpi = NULL;
4911                         continue;
4912                 }
4913
4914                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
4915                                     list) {
4916                         if (dev->sys_image_guid == mpi->sys_image_guid &&
4917                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
4918                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
4919                         }
4920
4921                         if (bound) {
4922                                 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
4923                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
4924                                 list_del(&mpi->list);
4925                                 break;
4926                         }
4927                 }
4928                 if (!bound) {
4929                         get_port_caps(dev, i + 1);
4930                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
4931                                     i + 1);
4932                 }
4933         }
4934
4935         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
4936         mutex_unlock(&mlx5_ib_multiport_mutex);
4937         return err;
4938 }
4939
4940 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
4941 {
4942         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4943         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
4944                                                           port_num + 1);
4945         int i;
4946
4947         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
4948                 return;
4949
4950         mutex_lock(&mlx5_ib_multiport_mutex);
4951         for (i = 0; i < dev->num_ports; i++) {
4952                 if (dev->port[i].mp.mpi) {
4953                         /* Destroy the native port stub */
4954                         if (i == port_num) {
4955                                 kfree(dev->port[i].mp.mpi);
4956                                 dev->port[i].mp.mpi = NULL;
4957                         } else {
4958                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
4959                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
4960                         }
4961                 }
4962         }
4963
4964         mlx5_ib_dbg(dev, "removing from devlist\n");
4965         list_del(&dev->ib_dev_list);
4966         mutex_unlock(&mlx5_ib_multiport_mutex);
4967
4968         mlx5_nic_vport_disable_roce(dev->mdev);
4969 }
4970
4971 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_dm, UVERBS_OBJECT_DM,
4972                              UVERBS_METHOD_DM_ALLOC,
4973                              &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
4974                                                   UVERBS_ATTR_TYPE(u64),
4975                                                   UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)),
4976                              &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
4977                                                   UVERBS_ATTR_TYPE(u16),
4978                                                   UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
4979
4980 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION,
4981                              UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
4982                              &UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4983                                                  UVERBS_ATTR_TYPE(u64),
4984                                                  UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
4985
4986 #define NUM_TREES       2
4987 static int populate_specs_root(struct mlx5_ib_dev *dev)
4988 {
4989         const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
4990                 uverbs_default_get_objects()};
4991         size_t num_trees = 1;
4992
4993         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
4994             !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
4995                 default_root[num_trees++] = &mlx5_ib_flow_action;
4996
4997         if (MLX5_CAP_DEV_MEM(dev->mdev, memic) &&
4998             !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
4999                 default_root[num_trees++] = &mlx5_ib_dm;
5000
5001         dev->ib_dev.specs_root =
5002                 uverbs_alloc_spec_tree(num_trees, default_root);
5003
5004         return PTR_ERR_OR_ZERO(dev->ib_dev.specs_root);
5005 }
5006
5007 static void depopulate_specs_root(struct mlx5_ib_dev *dev)
5008 {
5009         uverbs_free_spec_tree(dev->ib_dev.specs_root);
5010 }
5011
5012 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5013 {
5014         mlx5_ib_cleanup_multiport_master(dev);
5015 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5016         cleanup_srcu_struct(&dev->mr_srcu);
5017 #endif
5018         kfree(dev->port);
5019 }
5020
5021 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
5022 {
5023         struct mlx5_core_dev *mdev = dev->mdev;
5024         const char *name;
5025         int err;
5026         int i;
5027
5028         dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
5029                             GFP_KERNEL);
5030         if (!dev->port)
5031                 return -ENOMEM;
5032
5033         for (i = 0; i < dev->num_ports; i++) {
5034                 spin_lock_init(&dev->port[i].mp.mpi_lock);
5035                 rwlock_init(&dev->roce[i].netdev_lock);
5036         }
5037
5038         err = mlx5_ib_init_multiport_master(dev);
5039         if (err)
5040                 goto err_free_port;
5041
5042         if (!mlx5_core_mp_enabled(mdev)) {
5043                 for (i = 1; i <= dev->num_ports; i++) {
5044                         err = get_port_caps(dev, i);
5045                         if (err)
5046                                 break;
5047                 }
5048         } else {
5049                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5050         }
5051         if (err)
5052                 goto err_mp;
5053
5054         if (mlx5_use_mad_ifc(dev))
5055                 get_ext_port_caps(dev);
5056
5057         if (!mlx5_lag_is_active(mdev))
5058                 name = "mlx5_%d";
5059         else
5060                 name = "mlx5_bond_%d";
5061
5062         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
5063         dev->ib_dev.owner               = THIS_MODULE;
5064         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
5065         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
5066         dev->ib_dev.phys_port_cnt       = dev->num_ports;
5067         dev->ib_dev.num_comp_vectors    =
5068                 dev->mdev->priv.eq_table.num_comp_vectors;
5069         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
5070
5071         mutex_init(&dev->cap_mask_mutex);
5072         INIT_LIST_HEAD(&dev->qp_list);
5073         spin_lock_init(&dev->reset_flow_resource_lock);
5074
5075         spin_lock_init(&dev->memic.memic_lock);
5076         dev->memic.dev = mdev;
5077
5078 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5079         err = init_srcu_struct(&dev->mr_srcu);
5080         if (err)
5081                 goto err_free_port;
5082 #endif
5083
5084         return 0;
5085 err_mp:
5086         mlx5_ib_cleanup_multiport_master(dev);
5087
5088 err_free_port:
5089         kfree(dev->port);
5090
5091         return -ENOMEM;
5092 }
5093
5094 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5095 {
5096         dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5097
5098         if (!dev->flow_db)
5099                 return -ENOMEM;
5100
5101         mutex_init(&dev->flow_db->lock);
5102
5103         return 0;
5104 }
5105
5106 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5107 {
5108         struct mlx5_ib_dev *nic_dev;
5109
5110         nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5111
5112         if (!nic_dev)
5113                 return -EINVAL;
5114
5115         dev->flow_db = nic_dev->flow_db;
5116
5117         return 0;
5118 }
5119
5120 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5121 {
5122         kfree(dev->flow_db);
5123 }
5124
5125 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
5126 {
5127         struct mlx5_core_dev *mdev = dev->mdev;
5128         int err;
5129
5130         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
5131         dev->ib_dev.uverbs_cmd_mask     =
5132                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
5133                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
5134                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
5135                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
5136                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
5137                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
5138                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
5139                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
5140                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
5141                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
5142                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5143                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
5144                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
5145                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
5146                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
5147                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
5148                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
5149                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
5150                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
5151                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
5152                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
5153                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
5154                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
5155                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
5156                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
5157                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
5158         dev->ib_dev.uverbs_ex_cmd_mask =
5159                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
5160                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
5161                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
5162                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
5163                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
5164
5165         dev->ib_dev.query_device        = mlx5_ib_query_device;
5166         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
5167         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
5168         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
5169         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
5170         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
5171         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
5172         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
5173         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
5174         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
5175         dev->ib_dev.mmap                = mlx5_ib_mmap;
5176         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
5177         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
5178         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
5179         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
5180         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
5181         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
5182         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
5183         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
5184         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
5185         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
5186         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
5187         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
5188         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
5189         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
5190         dev->ib_dev.post_send           = mlx5_ib_post_send;
5191         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
5192         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
5193         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
5194         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
5195         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
5196         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
5197         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
5198         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
5199         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
5200         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
5201         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
5202         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
5203         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
5204         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
5205         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
5206         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
5207         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
5208         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
5209         dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
5210         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
5211                 dev->ib_dev.alloc_rdma_netdev   = mlx5_ib_alloc_rdma_netdev;
5212
5213         if (mlx5_core_is_pf(mdev)) {
5214                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
5215                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
5216                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
5217                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
5218         }
5219
5220         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5221
5222         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5223
5224         if (MLX5_CAP_GEN(mdev, imaicl)) {
5225                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
5226                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
5227                 dev->ib_dev.uverbs_cmd_mask |=
5228                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
5229                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5230         }
5231
5232         if (MLX5_CAP_GEN(mdev, xrc)) {
5233                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5234                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5235                 dev->ib_dev.uverbs_cmd_mask |=
5236                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5237                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5238         }
5239
5240         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5241                 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5242                 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
5243                 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
5244         }
5245
5246         dev->ib_dev.create_flow = mlx5_ib_create_flow;
5247         dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5248         dev->ib_dev.uverbs_ex_cmd_mask |=
5249                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5250                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5251         dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5252         dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
5253         dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
5254         dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
5255
5256         err = init_node_data(dev);
5257         if (err)
5258                 return err;
5259
5260         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
5261             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5262              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
5263                 mutex_init(&dev->lb_mutex);
5264
5265         return 0;
5266 }
5267
5268 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5269 {
5270         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
5271         dev->ib_dev.query_port          = mlx5_ib_query_port;
5272
5273         return 0;
5274 }
5275
5276 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
5277 {
5278         dev->ib_dev.get_port_immutable  = mlx5_port_rep_immutable;
5279         dev->ib_dev.query_port          = mlx5_ib_rep_query_port;
5280
5281         return 0;
5282 }
5283
5284 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev,
5285                                           u8 port_num)
5286 {
5287         int i;
5288
5289         for (i = 0; i < dev->num_ports; i++) {
5290                 dev->roce[i].dev = dev;
5291                 dev->roce[i].native_port_num = i + 1;
5292                 dev->roce[i].last_port_state = IB_PORT_DOWN;
5293         }
5294
5295         dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
5296         dev->ib_dev.create_wq    = mlx5_ib_create_wq;
5297         dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
5298         dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
5299         dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5300         dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5301
5302         dev->ib_dev.uverbs_ex_cmd_mask |=
5303                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5304                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5305                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5306                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5307                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5308
5309         return mlx5_add_netdev_notifier(dev, port_num);
5310 }
5311
5312 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5313 {
5314         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5315
5316         mlx5_remove_netdev_notifier(dev, port_num);
5317 }
5318
5319 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5320 {
5321         struct mlx5_core_dev *mdev = dev->mdev;
5322         enum rdma_link_layer ll;
5323         int port_type_cap;
5324         int err = 0;
5325         u8 port_num;
5326
5327         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5328         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5329         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5330
5331         if (ll == IB_LINK_LAYER_ETHERNET)
5332                 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5333
5334         return err;
5335 }
5336
5337 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5338 {
5339         mlx5_ib_stage_common_roce_cleanup(dev);
5340 }
5341
5342 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5343 {
5344         struct mlx5_core_dev *mdev = dev->mdev;
5345         enum rdma_link_layer ll;
5346         int port_type_cap;
5347         u8 port_num;
5348         int err;
5349
5350         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5351         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5352         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5353
5354         if (ll == IB_LINK_LAYER_ETHERNET) {
5355                 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5356                 if (err)
5357                         return err;
5358
5359                 err = mlx5_enable_eth(dev, port_num);
5360                 if (err)
5361                         goto cleanup;
5362         }
5363
5364         return 0;
5365 cleanup:
5366         mlx5_ib_stage_common_roce_cleanup(dev);
5367
5368         return err;
5369 }
5370
5371 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5372 {
5373         struct mlx5_core_dev *mdev = dev->mdev;
5374         enum rdma_link_layer ll;
5375         int port_type_cap;
5376         u8 port_num;
5377
5378         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5379         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5380         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5381
5382         if (ll == IB_LINK_LAYER_ETHERNET) {
5383                 mlx5_disable_eth(dev);
5384                 mlx5_ib_stage_common_roce_cleanup(dev);
5385         }
5386 }
5387
5388 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
5389 {
5390         return create_dev_resources(&dev->devr);
5391 }
5392
5393 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
5394 {
5395         destroy_dev_resources(&dev->devr);
5396 }
5397
5398 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
5399 {
5400         mlx5_ib_internal_fill_odp_caps(dev);
5401
5402         return mlx5_ib_odp_init_one(dev);
5403 }
5404
5405 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
5406 {
5407         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
5408                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
5409                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
5410
5411                 return mlx5_ib_alloc_counters(dev);
5412         }
5413
5414         return 0;
5415 }
5416
5417 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
5418 {
5419         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
5420                 mlx5_ib_dealloc_counters(dev);
5421 }
5422
5423 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
5424 {
5425         return mlx5_ib_init_cong_debugfs(dev,
5426                                          mlx5_core_native_port_num(dev->mdev) - 1);
5427 }
5428
5429 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
5430 {
5431         mlx5_ib_cleanup_cong_debugfs(dev,
5432                                      mlx5_core_native_port_num(dev->mdev) - 1);
5433 }
5434
5435 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
5436 {
5437         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
5438         if (!dev->mdev->priv.uar)
5439                 return -ENOMEM;
5440         return 0;
5441 }
5442
5443 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
5444 {
5445         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
5446 }
5447
5448 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
5449 {
5450         int err;
5451
5452         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
5453         if (err)
5454                 return err;
5455
5456         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
5457         if (err)
5458                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5459
5460         return err;
5461 }
5462
5463 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
5464 {
5465         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5466         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
5467 }
5468
5469 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
5470 {
5471         return populate_specs_root(dev);
5472 }
5473
5474 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
5475 {
5476         return ib_register_device(&dev->ib_dev, NULL);
5477 }
5478
5479 static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev)
5480 {
5481         depopulate_specs_root(dev);
5482 }
5483
5484 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
5485 {
5486         destroy_umrc_res(dev);
5487 }
5488
5489 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
5490 {
5491         ib_unregister_device(&dev->ib_dev);
5492 }
5493
5494 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
5495 {
5496         return create_umr_res(dev);
5497 }
5498
5499 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
5500 {
5501         init_delay_drop(dev);
5502
5503         return 0;
5504 }
5505
5506 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
5507 {
5508         cancel_delay_drop(dev);
5509 }
5510
5511 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
5512 {
5513         int err;
5514         int i;
5515
5516         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
5517                 err = device_create_file(&dev->ib_dev.dev,
5518                                          mlx5_class_attributes[i]);
5519                 if (err)
5520                         return err;
5521         }
5522
5523         return 0;
5524 }
5525
5526 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
5527 {
5528         mlx5_ib_register_vport_reps(dev);
5529
5530         return 0;
5531 }
5532
5533 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
5534 {
5535         mlx5_ib_unregister_vport_reps(dev);
5536 }
5537
5538 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
5539                       const struct mlx5_ib_profile *profile,
5540                       int stage)
5541 {
5542         /* Number of stages to cleanup */
5543         while (stage) {
5544                 stage--;
5545                 if (profile->stage[stage].cleanup)
5546                         profile->stage[stage].cleanup(dev);
5547         }
5548
5549         ib_dealloc_device((struct ib_device *)dev);
5550 }
5551
5552 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
5553
5554 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
5555                     const struct mlx5_ib_profile *profile)
5556 {
5557         int err;
5558         int i;
5559
5560         printk_once(KERN_INFO "%s", mlx5_version);
5561
5562         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
5563                 if (profile->stage[i].init) {
5564                         err = profile->stage[i].init(dev);
5565                         if (err)
5566                                 goto err_out;
5567                 }
5568         }
5569
5570         dev->profile = profile;
5571         dev->ib_active = true;
5572
5573         return dev;
5574
5575 err_out:
5576         __mlx5_ib_remove(dev, profile, i);
5577
5578         return NULL;
5579 }
5580
5581 static const struct mlx5_ib_profile pf_profile = {
5582         STAGE_CREATE(MLX5_IB_STAGE_INIT,
5583                      mlx5_ib_stage_init_init,
5584                      mlx5_ib_stage_init_cleanup),
5585         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5586                      mlx5_ib_stage_flow_db_init,
5587                      mlx5_ib_stage_flow_db_cleanup),
5588         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5589                      mlx5_ib_stage_caps_init,
5590                      NULL),
5591         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5592                      mlx5_ib_stage_non_default_cb,
5593                      NULL),
5594         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5595                      mlx5_ib_stage_roce_init,
5596                      mlx5_ib_stage_roce_cleanup),
5597         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5598                      mlx5_ib_stage_dev_res_init,
5599                      mlx5_ib_stage_dev_res_cleanup),
5600         STAGE_CREATE(MLX5_IB_STAGE_ODP,
5601                      mlx5_ib_stage_odp_init,
5602                      NULL),
5603         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5604                      mlx5_ib_stage_counters_init,
5605                      mlx5_ib_stage_counters_cleanup),
5606         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
5607                      mlx5_ib_stage_cong_debugfs_init,
5608                      mlx5_ib_stage_cong_debugfs_cleanup),
5609         STAGE_CREATE(MLX5_IB_STAGE_UAR,
5610                      mlx5_ib_stage_uar_init,
5611                      mlx5_ib_stage_uar_cleanup),
5612         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5613                      mlx5_ib_stage_bfrag_init,
5614                      mlx5_ib_stage_bfrag_cleanup),
5615         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5616                      NULL,
5617                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
5618         STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5619                      mlx5_ib_stage_populate_specs,
5620                      mlx5_ib_stage_depopulate_specs),
5621         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5622                      mlx5_ib_stage_ib_reg_init,
5623                      mlx5_ib_stage_ib_reg_cleanup),
5624         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5625                      mlx5_ib_stage_post_ib_reg_umr_init,
5626                      NULL),
5627         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
5628                      mlx5_ib_stage_delay_drop_init,
5629                      mlx5_ib_stage_delay_drop_cleanup),
5630         STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5631                      mlx5_ib_stage_class_attr_init,
5632                      NULL),
5633 };
5634
5635 static const struct mlx5_ib_profile nic_rep_profile = {
5636         STAGE_CREATE(MLX5_IB_STAGE_INIT,
5637                      mlx5_ib_stage_init_init,
5638                      mlx5_ib_stage_init_cleanup),
5639         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5640                      mlx5_ib_stage_flow_db_init,
5641                      mlx5_ib_stage_flow_db_cleanup),
5642         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5643                      mlx5_ib_stage_caps_init,
5644                      NULL),
5645         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5646                      mlx5_ib_stage_rep_non_default_cb,
5647                      NULL),
5648         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5649                      mlx5_ib_stage_rep_roce_init,
5650                      mlx5_ib_stage_rep_roce_cleanup),
5651         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5652                      mlx5_ib_stage_dev_res_init,
5653                      mlx5_ib_stage_dev_res_cleanup),
5654         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5655                      mlx5_ib_stage_counters_init,
5656                      mlx5_ib_stage_counters_cleanup),
5657         STAGE_CREATE(MLX5_IB_STAGE_UAR,
5658                      mlx5_ib_stage_uar_init,
5659                      mlx5_ib_stage_uar_cleanup),
5660         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5661                      mlx5_ib_stage_bfrag_init,
5662                      mlx5_ib_stage_bfrag_cleanup),
5663         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5664                      NULL,
5665                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
5666         STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5667                      mlx5_ib_stage_populate_specs,
5668                      mlx5_ib_stage_depopulate_specs),
5669         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5670                      mlx5_ib_stage_ib_reg_init,
5671                      mlx5_ib_stage_ib_reg_cleanup),
5672         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5673                      mlx5_ib_stage_post_ib_reg_umr_init,
5674                      NULL),
5675         STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5676                      mlx5_ib_stage_class_attr_init,
5677                      NULL),
5678         STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
5679                      mlx5_ib_stage_rep_reg_init,
5680                      mlx5_ib_stage_rep_reg_cleanup),
5681 };
5682
5683 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
5684 {
5685         struct mlx5_ib_multiport_info *mpi;
5686         struct mlx5_ib_dev *dev;
5687         bool bound = false;
5688         int err;
5689
5690         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5691         if (!mpi)
5692                 return NULL;
5693
5694         mpi->mdev = mdev;
5695
5696         err = mlx5_query_nic_vport_system_image_guid(mdev,
5697                                                      &mpi->sys_image_guid);
5698         if (err) {
5699                 kfree(mpi);
5700                 return NULL;
5701         }
5702
5703         mutex_lock(&mlx5_ib_multiport_mutex);
5704         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5705                 if (dev->sys_image_guid == mpi->sys_image_guid)
5706                         bound = mlx5_ib_bind_slave_port(dev, mpi);
5707
5708                 if (bound) {
5709                         rdma_roce_rescan_device(&dev->ib_dev);
5710                         break;
5711                 }
5712         }
5713
5714         if (!bound) {
5715                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5716                 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5717         } else {
5718                 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
5719         }
5720         mutex_unlock(&mlx5_ib_multiport_mutex);
5721
5722         return mpi;
5723 }
5724
5725 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
5726 {
5727         enum rdma_link_layer ll;
5728         struct mlx5_ib_dev *dev;
5729         int port_type_cap;
5730
5731         printk_once(KERN_INFO "%s", mlx5_version);
5732
5733         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5734         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5735
5736         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5737                 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5738
5739                 return mlx5_ib_add_slave_port(mdev, port_num);
5740         }
5741
5742         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
5743         if (!dev)
5744                 return NULL;
5745
5746         dev->mdev = mdev;
5747         dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
5748                              MLX5_CAP_GEN(mdev, num_vhca_ports));
5749
5750         if (MLX5_VPORT_MANAGER(mdev) &&
5751             mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5752                 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
5753
5754                 return __mlx5_ib_add(dev, &nic_rep_profile);
5755         }
5756
5757         return __mlx5_ib_add(dev, &pf_profile);
5758 }
5759
5760 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
5761 {
5762         struct mlx5_ib_multiport_info *mpi;
5763         struct mlx5_ib_dev *dev;
5764
5765         if (mlx5_core_is_mp_slave(mdev)) {
5766                 mpi = context;
5767                 mutex_lock(&mlx5_ib_multiport_mutex);
5768                 if (mpi->ibdev)
5769                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5770                 list_del(&mpi->list);
5771                 mutex_unlock(&mlx5_ib_multiport_mutex);
5772                 return;
5773         }
5774
5775         dev = context;
5776         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
5777 }
5778
5779 static struct mlx5_interface mlx5_ib_interface = {
5780         .add            = mlx5_ib_add,
5781         .remove         = mlx5_ib_remove,
5782         .event          = mlx5_ib_event,
5783 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5784         .pfault         = mlx5_ib_pfault,
5785 #endif
5786         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
5787 };
5788
5789 unsigned long mlx5_ib_get_xlt_emergency_page(void)
5790 {
5791         mutex_lock(&xlt_emergency_page_mutex);
5792         return xlt_emergency_page;
5793 }
5794
5795 void mlx5_ib_put_xlt_emergency_page(void)
5796 {
5797         mutex_unlock(&xlt_emergency_page_mutex);
5798 }
5799
5800 static int __init mlx5_ib_init(void)
5801 {
5802         int err;
5803
5804         xlt_emergency_page = __get_free_page(GFP_KERNEL);
5805         if (!xlt_emergency_page)
5806                 return -ENOMEM;
5807
5808         mutex_init(&xlt_emergency_page_mutex);
5809
5810         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
5811         if (!mlx5_ib_event_wq) {
5812                 free_page(xlt_emergency_page);
5813                 return -ENOMEM;
5814         }
5815
5816         mlx5_ib_odp_init();
5817
5818         err = mlx5_register_interface(&mlx5_ib_interface);
5819
5820         return err;
5821 }
5822
5823 static void __exit mlx5_ib_cleanup(void)
5824 {
5825         mlx5_unregister_interface(&mlx5_ib_interface);
5826         destroy_workqueue(mlx5_ib_event_wq);
5827         mutex_destroy(&xlt_emergency_page_mutex);
5828         free_page(xlt_emergency_page);
5829 }
5830
5831 module_init(mlx5_ib_init);
5832 module_exit(mlx5_ib_cleanup);