drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <linux/bitmap.h>
  42 #if defined(CONFIG_X86)
  43 #include <asm/pat.h>
  44 #endif
  45 #include <linux/sched.h>
  46 #include <linux/sched/mm.h>
  47 #include <linux/sched/task.h>
  48 #include <linux/delay.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <rdma/ib_addr.h>
  51 #include <rdma/ib_cache.h>
  52 #include <linux/mlx5/port.h>
  53 #include <linux/mlx5/vport.h>
  54 #include <linux/mlx5/fs.h>
  55 #include <linux/mlx5/fs_helpers.h>
  56 #include <linux/list.h>
  57 #include <rdma/ib_smi.h>
  58 #include <rdma/ib_umem.h>
  59 #include <linux/in.h>
  60 #include <linux/etherdevice.h>
  61 #include "mlx5_ib.h"
  62 #include "ib_rep.h"
  63 #include "cmd.h"
  64 #include <linux/mlx5/fs_helpers.h>
  65 #include <linux/mlx5/accel.h>
  66 #include <rdma/uverbs_std_types.h>
  67 #include <rdma/mlx5_user_ioctl_verbs.h>
  68 #include <rdma/mlx5_user_ioctl_cmds.h>
  69
  70 #define UVERBS_MODULE_NAME mlx5_ib
  71 #include <rdma/uverbs_named_ioctl.h>
  72
  73 #define DRIVER_NAME "mlx5_ib"
  74 #define DRIVER_VERSION "5.0-0"
  75
  76 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  77 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  78 MODULE_LICENSE("Dual BSD/GPL");
  79
  80 static char mlx5_version[] =
  81         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  82         DRIVER_VERSION "\n";
  83
  84 struct mlx5_ib_event_work {
  85         struct work_struct      work;
  86         struct mlx5_core_dev    *dev;
  87         void                    *context;
  88         enum mlx5_dev_event     event;
  89         unsigned long           param;
  90 };
  91
  92 enum {
  93         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  94 };
  95
  96 static struct workqueue_struct *mlx5_ib_event_wq;
  97 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  98 static LIST_HEAD(mlx5_ib_dev_list);
  99 /*
 100  * This mutex should be held when accessing either of the above lists
 101  */
 102 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
 103
 104 /* We can't use an array for xlt_emergency_page because dma_map_single
 105  * doesn't work on kernel modules memory
 106  */
 107 static unsigned long xlt_emergency_page;
 108 static struct mutex xlt_emergency_page_mutex;
 109
 110 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
 111 {
 112         struct mlx5_ib_dev *dev;
 113
 114         mutex_lock(&mlx5_ib_multiport_mutex);
 115         dev = mpi->ibdev;
 116         mutex_unlock(&mlx5_ib_multiport_mutex);
 117         return dev;
 118 }
 119
 120 static enum rdma_link_layer
 121 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 122 {
 123         switch (port_type_cap) {
 124         case MLX5_CAP_PORT_TYPE_IB:
 125                 return IB_LINK_LAYER_INFINIBAND;
 126         case MLX5_CAP_PORT_TYPE_ETH:
 127                 return IB_LINK_LAYER_ETHERNET;
 128         default:
 129                 return IB_LINK_LAYER_UNSPECIFIED;
 130         }
 131 }
 132
 133 static enum rdma_link_layer
 134 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 135 {
 136         struct mlx5_ib_dev *dev = to_mdev(device);
 137         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 138
 139         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 140 }
 141
 142 static int get_port_state(struct ib_device *ibdev,
 143                           u8 port_num,
 144                           enum ib_port_state *state)
 145 {
 146         struct ib_port_attr attr;
 147         int ret;
 148
 149         memset(&attr, 0, sizeof(attr));
 150         ret = ibdev->query_port(ibdev, port_num, &attr);
 151         if (!ret)
 152                 *state = attr.state;
 153         return ret;
 154 }
 155
 156 static int mlx5_netdev_event(struct notifier_block *this,
 157                              unsigned long event, void *ptr)
 158 {
 159         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 160         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 161         u8 port_num = roce->native_port_num;
 162         struct mlx5_core_dev *mdev;
 163         struct mlx5_ib_dev *ibdev;
 164
 165         ibdev = roce->dev;
 166         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 167         if (!mdev)
 168                 return NOTIFY_DONE;
 169
 170         switch (event) {
 171         case NETDEV_REGISTER:
 172         case NETDEV_UNREGISTER:
 173                 write_lock(&roce->netdev_lock);
 174                 if (ibdev->rep) {
 175                         struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
 176                         struct net_device *rep_ndev;
 177
 178                         rep_ndev = mlx5_ib_get_rep_netdev(esw,
 179                                                           ibdev->rep->vport);
 180                         if (rep_ndev == ndev)
 181                                 roce->netdev = (event == NETDEV_UNREGISTER) ?
 182                                         NULL : ndev;
 183                 } else if (ndev->dev.parent == &ibdev->mdev->pdev->dev) {
 184                         roce->netdev = (event == NETDEV_UNREGISTER) ?
 185                                 NULL : ndev;
 186                 }
 187                 write_unlock(&roce->netdev_lock);
 188                 break;
 189
 190         case NETDEV_CHANGE:
 191         case NETDEV_UP:
 192         case NETDEV_DOWN: {
 193                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 194                 struct net_device *upper = NULL;
 195
 196                 if (lag_ndev) {
 197                         upper = netdev_master_upper_dev_get(lag_ndev);
 198                         dev_put(lag_ndev);
 199                 }
 200
 201                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 202                     && ibdev->ib_active) {
 203                         struct ib_event ibev = { };
 204                         enum ib_port_state port_state;
 205
 206                         if (get_port_state(&ibdev->ib_dev, port_num,
 207                                            &port_state))
 208                                 goto done;
 209
 210                         if (roce->last_port_state == port_state)
 211                                 goto done;
 212
 213                         roce->last_port_state = port_state;
 214                         ibev.device = &ibdev->ib_dev;
 215                         if (port_state == IB_PORT_DOWN)
 216                                 ibev.event = IB_EVENT_PORT_ERR;
 217                         else if (port_state == IB_PORT_ACTIVE)
 218                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 219                         else
 220                                 goto done;
 221
 222                         ibev.element.port_num = port_num;
 223                         ib_dispatch_event(&ibev);
 224                 }
 225                 break;
 226         }
 227
 228         default:
 229                 break;
 230         }
 231 done:
 232         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 233         return NOTIFY_DONE;
 234 }
 235
 236 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 237                                              u8 port_num)
 238 {
 239         struct mlx5_ib_dev *ibdev = to_mdev(device);
 240         struct net_device *ndev;
 241         struct mlx5_core_dev *mdev;
 242
 243         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 244         if (!mdev)
 245                 return NULL;
 246
 247         ndev = mlx5_lag_get_roce_netdev(mdev);
 248         if (ndev)
 249                 goto out;
 250
 251         /* Ensure ndev does not disappear before we invoke dev_hold()
 252          */
 253         read_lock(&ibdev->roce[port_num - 1].netdev_lock);
 254         ndev = ibdev->roce[port_num - 1].netdev;
 255         if (ndev)
 256                 dev_hold(ndev);
 257         read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
 258
 259 out:
 260         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 261         return ndev;
 262 }
 263
 264 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 265                                                    u8 ib_port_num,
 266                                                    u8 *native_port_num)
 267 {
 268         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 269                                                           ib_port_num);
 270         struct mlx5_core_dev *mdev = NULL;
 271         struct mlx5_ib_multiport_info *mpi;
 272         struct mlx5_ib_port *port;
 273
 274         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 275             ll != IB_LINK_LAYER_ETHERNET) {
 276                 if (native_port_num)
 277                         *native_port_num = ib_port_num;
 278                 return ibdev->mdev;
 279         }
 280
 281         if (native_port_num)
 282                 *native_port_num = 1;
 283
 284         port = &ibdev->port[ib_port_num - 1];
 285         if (!port)
 286                 return NULL;
 287
 288         spin_lock(&port->mp.mpi_lock);
 289         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 290         if (mpi && !mpi->unaffiliate) {
 291                 mdev = mpi->mdev;
 292                 /* If it's the master no need to refcount, it'll exist
 293                  * as long as the ib_dev exists.
 294                  */
 295                 if (!mpi->is_master)
 296                         mpi->mdev_refcnt++;
 297         }
 298         spin_unlock(&port->mp.mpi_lock);
 299
 300         return mdev;
 301 }
 302
 303 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 304 {
 305         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 306                                                           port_num);
 307         struct mlx5_ib_multiport_info *mpi;
 308         struct mlx5_ib_port *port;
 309
 310         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 311                 return;
 312
 313         port = &ibdev->port[port_num - 1];
 314
 315         spin_lock(&port->mp.mpi_lock);
 316         mpi = ibdev->port[port_num - 1].mp.mpi;
 317         if (mpi->is_master)
 318                 goto out;
 319
 320         mpi->mdev_refcnt--;
 321         if (mpi->unaffiliate)
 322                 complete(&mpi->unref_comp);
 323 out:
 324         spin_unlock(&port->mp.mpi_lock);
 325 }
 326
 327 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 328                                     u8 *active_width)
 329 {
 330         switch (eth_proto_oper) {
 331         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 332         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 333         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 334         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 335                 *active_width = IB_WIDTH_1X;
 336                 *active_speed = IB_SPEED_SDR;
 337                 break;
 338         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 339         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 340         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 341         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 342         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 343         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 344         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 345                 *active_width = IB_WIDTH_1X;
 346                 *active_speed = IB_SPEED_QDR;
 347                 break;
 348         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 349         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 350         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 351                 *active_width = IB_WIDTH_1X;
 352                 *active_speed = IB_SPEED_EDR;
 353                 break;
 354         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 355         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 356         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 357         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 358                 *active_width = IB_WIDTH_4X;
 359                 *active_speed = IB_SPEED_QDR;
 360                 break;
 361         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 362         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 363         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 364                 *active_width = IB_WIDTH_1X;
 365                 *active_speed = IB_SPEED_HDR;
 366                 break;
 367         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 368                 *active_width = IB_WIDTH_4X;
 369                 *active_speed = IB_SPEED_FDR;
 370                 break;
 371         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 372         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 373         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 374         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 375                 *active_width = IB_WIDTH_4X;
 376                 *active_speed = IB_SPEED_EDR;
 377                 break;
 378         default:
 379                 return -EINVAL;
 380         }
 381
 382         return 0;
 383 }
 384
 385 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 386                                 struct ib_port_attr *props)
 387 {
 388         struct mlx5_ib_dev *dev = to_mdev(device);
 389         struct mlx5_core_dev *mdev;
 390         struct net_device *ndev, *upper;
 391         enum ib_mtu ndev_ib_mtu;
 392         bool put_mdev = true;
 393         u16 qkey_viol_cntr;
 394         u32 eth_prot_oper;
 395         u8 mdev_port_num;
 396         int err;
 397
 398         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 399         if (!mdev) {
 400                 /* This means the port isn't affiliated yet. Get the
 401                  * info for the master port instead.
 402                  */
 403                 put_mdev = false;
 404                 mdev = dev->mdev;
 405                 mdev_port_num = 1;
 406                 port_num = 1;
 407         }
 408
 409         /* Possible bad flows are checked before filling out props so in case
 410          * of an error it will still be zeroed out.
 411          */
 412         err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
 413                                              mdev_port_num);
 414         if (err)
 415                 goto out;
 416
 417         props->active_width     = IB_WIDTH_4X;
 418         props->active_speed     = IB_SPEED_QDR;
 419
 420         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 421                                  &props->active_width);
 422
 423         props->port_cap_flags  |= IB_PORT_CM_SUP;
 424         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 425
 426         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 427                                                 roce_address_table_size);
 428         props->max_mtu          = IB_MTU_4096;
 429         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 430         props->pkey_tbl_len     = 1;
 431         props->state            = IB_PORT_DOWN;
 432         props->phys_state       = 3;
 433
 434         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 435         props->qkey_viol_cntr = qkey_viol_cntr;
 436
 437         /* If this is a stub query for an unaffiliated port stop here */
 438         if (!put_mdev)
 439                 goto out;
 440
 441         ndev = mlx5_ib_get_netdev(device, port_num);
 442         if (!ndev)
 443                 goto out;
 444
 445         if (mlx5_lag_is_active(dev->mdev)) {
 446                 rcu_read_lock();
 447                 upper = netdev_master_upper_dev_get_rcu(ndev);
 448                 if (upper) {
 449                         dev_put(ndev);
 450                         ndev = upper;
 451                         dev_hold(ndev);
 452                 }
 453                 rcu_read_unlock();
 454         }
 455
 456         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 457                 props->state      = IB_PORT_ACTIVE;
 458                 props->phys_state = 5;
 459         }
 460
 461         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 462
 463         dev_put(ndev);
 464
 465         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 466 out:
 467         if (put_mdev)
 468                 mlx5_ib_put_native_port_mdev(dev, port_num);
 469         return err;
 470 }
 471
 472 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 473                          unsigned int index, const union ib_gid *gid,
 474                          const struct ib_gid_attr *attr)
 475 {
 476         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 477         u8 roce_version = 0;
 478         u8 roce_l3_type = 0;
 479         bool vlan = false;
 480         u8 mac[ETH_ALEN];
 481         u16 vlan_id = 0;
 482
 483         if (gid) {
 484                 gid_type = attr->gid_type;
 485                 ether_addr_copy(mac, attr->ndev->dev_addr);
 486
 487                 if (is_vlan_dev(attr->ndev)) {
 488                         vlan = true;
 489                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 490                 }
 491         }
 492
 493         switch (gid_type) {
 494         case IB_GID_TYPE_IB:
 495                 roce_version = MLX5_ROCE_VERSION_1;
 496                 break;
 497         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 498                 roce_version = MLX5_ROCE_VERSION_2;
 499                 if (ipv6_addr_v4mapped((void *)gid))
 500                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 501                 else
 502                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 503                 break;
 504
 505         default:
 506                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 507         }
 508
 509         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 510                                       roce_l3_type, gid->raw, mac, vlan,
 511                                       vlan_id, port_num);
 512 }
 513
 514 static int mlx5_ib_add_gid(const union ib_gid *gid,
 515                            const struct ib_gid_attr *attr,
 516                            __always_unused void **context)
 517 {
 518         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 519                              attr->index, gid, attr);
 520 }
 521
 522 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 523                            __always_unused void **context)
 524 {
 525         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 526                              attr->index, NULL, NULL);
 527 }
 528
 529 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 530                                int index)
 531 {
 532         struct ib_gid_attr attr;
 533         union ib_gid gid;
 534
 535         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 536                 return 0;
 537
 538         dev_put(attr.ndev);
 539
 540         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 541                 return 0;
 542
 543         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 544 }
 545
 546 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
 547                            int index, enum ib_gid_type *gid_type)
 548 {
 549         struct ib_gid_attr attr;
 550         union ib_gid gid;
 551         int ret;
 552
 553         ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
 554         if (ret)
 555                 return ret;
 556
 557         dev_put(attr.ndev);
 558
 559         *gid_type = attr.gid_type;
 560
 561         return 0;
 562 }
 563
 564 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 565 {
 566         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 567                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 568         return 0;
 569 }
 570
 571 enum {
 572         MLX5_VPORT_ACCESS_METHOD_MAD,
 573         MLX5_VPORT_ACCESS_METHOD_HCA,
 574         MLX5_VPORT_ACCESS_METHOD_NIC,
 575 };
 576
 577 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 578 {
 579         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 580                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 581
 582         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 583             IB_LINK_LAYER_ETHERNET)
 584                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 585
 586         return MLX5_VPORT_ACCESS_METHOD_HCA;
 587 }
 588
 589 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 590                             u8 atomic_size_qp,
 591                             struct ib_device_attr *props)
 592 {
 593         u8 tmp;
 594         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 595         u8 atomic_req_8B_endianness_mode =
 596                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 597
 598         /* Check if HW supports 8 bytes standard atomic operations and capable
 599          * of host endianness respond
 600          */
 601         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 602         if (((atomic_operations & tmp) == tmp) &&
 603             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 604             (atomic_req_8B_endianness_mode)) {
 605                 props->atomic_cap = IB_ATOMIC_HCA;
 606         } else {
 607                 props->atomic_cap = IB_ATOMIC_NONE;
 608         }
 609 }
 610
 611 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 612                                struct ib_device_attr *props)
 613 {
 614         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 615
 616         get_atomic_caps(dev, atomic_size_qp, props);
 617 }
 618
 619 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 620                                struct ib_device_attr *props)
 621 {
 622         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 623
 624         get_atomic_caps(dev, atomic_size_qp, props);
 625 }
 626
 627 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 628 {
 629         struct ib_device_attr props = {};
 630
 631         get_atomic_caps_dc(dev, &props);
 632         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 633 }
 634 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 635                                         __be64 *sys_image_guid)
 636 {
 637         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 638         struct mlx5_core_dev *mdev = dev->mdev;
 639         u64 tmp;
 640         int err;
 641
 642         switch (mlx5_get_vport_access_method(ibdev)) {
 643         case MLX5_VPORT_ACCESS_METHOD_MAD:
 644                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 645                                                             sys_image_guid);
 646
 647         case MLX5_VPORT_ACCESS_METHOD_HCA:
 648                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 649                 break;
 650
 651         case MLX5_VPORT_ACCESS_METHOD_NIC:
 652                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 653                 break;
 654
 655         default:
 656                 return -EINVAL;
 657         }
 658
 659         if (!err)
 660                 *sys_image_guid = cpu_to_be64(tmp);
 661
 662         return err;
 663
 664 }
 665
 666 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 667                                 u16 *max_pkeys)
 668 {
 669         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 670         struct mlx5_core_dev *mdev = dev->mdev;
 671
 672         switch (mlx5_get_vport_access_method(ibdev)) {
 673         case MLX5_VPORT_ACCESS_METHOD_MAD:
 674                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 675
 676         case MLX5_VPORT_ACCESS_METHOD_HCA:
 677         case MLX5_VPORT_ACCESS_METHOD_NIC:
 678                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 679                                                 pkey_table_size));
 680                 return 0;
 681
 682         default:
 683                 return -EINVAL;
 684         }
 685 }
 686
 687 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 688                                 u32 *vendor_id)
 689 {
 690         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 691
 692         switch (mlx5_get_vport_access_method(ibdev)) {
 693         case MLX5_VPORT_ACCESS_METHOD_MAD:
 694                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 695
 696         case MLX5_VPORT_ACCESS_METHOD_HCA:
 697         case MLX5_VPORT_ACCESS_METHOD_NIC:
 698                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 699
 700         default:
 701                 return -EINVAL;
 702         }
 703 }
 704
 705 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 706                                 __be64 *node_guid)
 707 {
 708         u64 tmp;
 709         int err;
 710
 711         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 712         case MLX5_VPORT_ACCESS_METHOD_MAD:
 713                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 714
 715         case MLX5_VPORT_ACCESS_METHOD_HCA:
 716                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 717                 break;
 718
 719         case MLX5_VPORT_ACCESS_METHOD_NIC:
 720                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 721                 break;
 722
 723         default:
 724                 return -EINVAL;
 725         }
 726
 727         if (!err)
 728                 *node_guid = cpu_to_be64(tmp);
 729
 730         return err;
 731 }
 732
 733 struct mlx5_reg_node_desc {
 734         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 735 };
 736
 737 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 738 {
 739         struct mlx5_reg_node_desc in;
 740
 741         if (mlx5_use_mad_ifc(dev))
 742                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 743
 744         memset(&in, 0, sizeof(in));
 745
 746         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 747                                     sizeof(struct mlx5_reg_node_desc),
 748                                     MLX5_REG_NODE_DESC, 0, 0);
 749 }
 750
 751 static int mlx5_ib_query_device(struct ib_device *ibdev,
 752                                 struct ib_device_attr *props,
 753                                 struct ib_udata *uhw)
 754 {
 755         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 756         struct mlx5_core_dev *mdev = dev->mdev;
 757         int err = -ENOMEM;
 758         int max_sq_desc;
 759         int max_rq_sg;
 760         int max_sq_sg;
 761         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 762         bool raw_support = !mlx5_core_mp_enabled(mdev);
 763         struct mlx5_ib_query_device_resp resp = {};
 764         size_t resp_len;
 765         u64 max_tso;
 766
 767         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 768         if (uhw->outlen && uhw->outlen < resp_len)
 769                 return -EINVAL;
 770         else
 771                 resp.response_length = resp_len;
 772
 773         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 774                 return -EINVAL;
 775
 776         memset(props, 0, sizeof(*props));
 777         err = mlx5_query_system_image_guid(ibdev,
 778                                            &props->sys_image_guid);
 779         if (err)
 780                 return err;
 781
 782         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 783         if (err)
 784                 return err;
 785
 786         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 787         if (err)
 788                 return err;
 789
 790         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 791                 (fw_rev_min(dev->mdev) << 16) |
 792                 fw_rev_sub(dev->mdev);
 793         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 794                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 795                 IB_DEVICE_SYS_IMAGE_GUID                |
 796                 IB_DEVICE_RC_RNR_NAK_GEN;
 797
 798         if (MLX5_CAP_GEN(mdev, pkv))
 799                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 800         if (MLX5_CAP_GEN(mdev, qkv))
 801                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 802         if (MLX5_CAP_GEN(mdev, apm))
 803                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 804         if (MLX5_CAP_GEN(mdev, xrc))
 805                 props->device_cap_flags |= IB_DEVICE_XRC;
 806         if (MLX5_CAP_GEN(mdev, imaicl)) {
 807                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 808                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 809                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 810                 /* We support 'Gappy' memory registration too */
 811                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 812         }
 813         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 814         if (MLX5_CAP_GEN(mdev, sho)) {
 815                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 816                 /* At this stage no support for signature handover */
 817                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 818                                       IB_PROT_T10DIF_TYPE_2 |
 819                                       IB_PROT_T10DIF_TYPE_3;
 820                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 821                                        IB_GUARD_T10DIF_CSUM;
 822         }
 823         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 824                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 825
 826         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 827                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 828                         /* Legacy bit to support old userspace libraries */
 829                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 830                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 831                 }
 832
 833                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 834                         props->raw_packet_caps |=
 835                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 836
 837                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 838                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 839                         if (max_tso) {
 840                                 resp.tso_caps.max_tso = 1 << max_tso;
 841                                 resp.tso_caps.supported_qpts |=
 842                                         1 << IB_QPT_RAW_PACKET;
 843                                 resp.response_length += sizeof(resp.tso_caps);
 844                         }
 845                 }
 846
 847                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 848                         resp.rss_caps.rx_hash_function =
 849                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 850                         resp.rss_caps.rx_hash_fields_mask =
 851                                                 MLX5_RX_HASH_SRC_IPV4 |
 852                                                 MLX5_RX_HASH_DST_IPV4 |
 853                                                 MLX5_RX_HASH_SRC_IPV6 |
 854                                                 MLX5_RX_HASH_DST_IPV6 |
 855                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 856                                                 MLX5_RX_HASH_DST_PORT_TCP |
 857                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 858                                                 MLX5_RX_HASH_DST_PORT_UDP |
 859                                                 MLX5_RX_HASH_INNER;
 860                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 861                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 862                                 resp.rss_caps.rx_hash_fields_mask |=
 863                                         MLX5_RX_HASH_IPSEC_SPI;
 864                         resp.response_length += sizeof(resp.rss_caps);
 865                 }
 866         } else {
 867                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 868                         resp.response_length += sizeof(resp.tso_caps);
 869                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 870                         resp.response_length += sizeof(resp.rss_caps);
 871         }
 872
 873         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 874                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 875                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 876         }
 877
 878         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 879             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 880             raw_support)
 881                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 882
 883         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 884             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 885                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 886
 887         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 888             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 889             raw_support) {
 890                 /* Legacy bit to support old userspace libraries */
 891                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 892                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 893         }
 894
 895         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 896                 props->max_dm_size =
 897                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 898         }
 899
 900         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 901                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 902
 903         if (MLX5_CAP_GEN(mdev, end_pad))
 904                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 905
 906         props->vendor_part_id      = mdev->pdev->device;
 907         props->hw_ver              = mdev->pdev->revision;
 908
 909         props->max_mr_size         = ~0ull;
 910         props->page_size_cap       = ~(min_page_size - 1);
 911         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 912         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 913         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 914                      sizeof(struct mlx5_wqe_data_seg);
 915         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 916         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 917                      sizeof(struct mlx5_wqe_raddr_seg)) /
 918                 sizeof(struct mlx5_wqe_data_seg);
 919         props->max_sge = min(max_rq_sg, max_sq_sg);
 920         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 921         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 922         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 923         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 924         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 925         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 926         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 927         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 928         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 929         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 930         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 931         props->max_srq_sge         = max_rq_sg - 1;
 932         props->max_fast_reg_page_list_len =
 933                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 934         get_atomic_caps_qp(dev, props);
 935         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 936         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 937         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 938         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 939                                            props->max_mcast_grp;
 940         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 941         props->max_ah = INT_MAX;
 942         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 943         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 944
 945 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 946         if (MLX5_CAP_GEN(mdev, pg))
 947                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 948         props->odp_caps = dev->odp_caps;
 949 #endif
 950
 951         if (MLX5_CAP_GEN(mdev, cd))
 952                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 953
 954         if (!mlx5_core_is_pf(mdev))
 955                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 956
 957         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 958             IB_LINK_LAYER_ETHERNET && raw_support) {
 959                 props->rss_caps.max_rwq_indirection_tables =
 960                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 961                 props->rss_caps.max_rwq_indirection_table_size =
 962                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 963                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 964                 props->max_wq_type_rq =
 965                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 966         }
 967
 968         if (MLX5_CAP_GEN(mdev, tag_matching)) {
 969                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
 970                 props->tm_caps.max_num_tags =
 971                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
 972                 props->tm_caps.flags = IB_TM_CAP_RC;
 973                 props->tm_caps.max_ops =
 974                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 975                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
 976         }
 977
 978         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
 979                 props->cq_caps.max_cq_moderation_count =
 980                                                 MLX5_MAX_CQ_COUNT;
 981                 props->cq_caps.max_cq_moderation_period =
 982                                                 MLX5_MAX_CQ_PERIOD;
 983         }
 984
 985         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 986                 resp.cqe_comp_caps.max_num =
 987                         MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
 988                         MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
 989                 resp.cqe_comp_caps.supported_format =
 990                         MLX5_IB_CQE_RES_FORMAT_HASH |
 991                         MLX5_IB_CQE_RES_FORMAT_CSUM;
 992                 resp.response_length += sizeof(resp.cqe_comp_caps);
 993         }
 994
 995         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
 996             raw_support) {
 997                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
 998                     MLX5_CAP_GEN(mdev, qos)) {
 999                         resp.packet_pacing_caps.qp_rate_limit_max =
1000                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1001                         resp.packet_pacing_caps.qp_rate_limit_min =
1002                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1003                         resp.packet_pacing_caps.supported_qpts |=
1004                                 1 << IB_QPT_RAW_PACKET;
1005                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1006                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1007                                 resp.packet_pacing_caps.cap_flags |=
1008                                         MLX5_IB_PP_SUPPORT_BURST;
1009                 }
1010                 resp.response_length += sizeof(resp.packet_pacing_caps);
1011         }
1012
1013         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1014                         uhw->outlen)) {
1015                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1016                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1017                                 MLX5_IB_ALLOW_MPW;
1018
1019                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1020                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1021                                 MLX5_IB_SUPPORT_EMPW;
1022
1023                 resp.response_length +=
1024                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1025         }
1026
1027         if (field_avail(typeof(resp), flags, uhw->outlen)) {
1028                 resp.response_length += sizeof(resp.flags);
1029
1030                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1031                         resp.flags |=
1032                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1033
1034                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1035                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1036         }
1037
1038         if (field_avail(typeof(resp), sw_parsing_caps,
1039                         uhw->outlen)) {
1040                 resp.response_length += sizeof(resp.sw_parsing_caps);
1041                 if (MLX5_CAP_ETH(mdev, swp)) {
1042                         resp.sw_parsing_caps.sw_parsing_offloads |=
1043                                 MLX5_IB_SW_PARSING;
1044
1045                         if (MLX5_CAP_ETH(mdev, swp_csum))
1046                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1047                                         MLX5_IB_SW_PARSING_CSUM;
1048
1049                         if (MLX5_CAP_ETH(mdev, swp_lso))
1050                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1051                                         MLX5_IB_SW_PARSING_LSO;
1052
1053                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1054                                 resp.sw_parsing_caps.supported_qpts =
1055                                         BIT(IB_QPT_RAW_PACKET);
1056                 }
1057         }
1058
1059         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1060             raw_support) {
1061                 resp.response_length += sizeof(resp.striding_rq_caps);
1062                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1063                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1064                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1065                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1066                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1067                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1068                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1069                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1070                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1071                         resp.striding_rq_caps.supported_qpts =
1072                                 BIT(IB_QPT_RAW_PACKET);
1073                 }
1074         }
1075
1076         if (field_avail(typeof(resp), tunnel_offloads_caps,
1077                         uhw->outlen)) {
1078                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1079                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1080                         resp.tunnel_offloads_caps |=
1081                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1082                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1083                         resp.tunnel_offloads_caps |=
1084                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1085                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1086                         resp.tunnel_offloads_caps |=
1087                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1088         }
1089
1090         if (uhw->outlen) {
1091                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1092
1093                 if (err)
1094                         return err;
1095         }
1096
1097         return 0;
1098 }
1099
1100 enum mlx5_ib_width {
1101         MLX5_IB_WIDTH_1X        = 1 << 0,
1102         MLX5_IB_WIDTH_2X        = 1 << 1,
1103         MLX5_IB_WIDTH_4X        = 1 << 2,
1104         MLX5_IB_WIDTH_8X        = 1 << 3,
1105         MLX5_IB_WIDTH_12X       = 1 << 4
1106 };
1107
1108 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1109                                   u8 *ib_width)
1110 {
1111         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1112         int err = 0;
1113
1114         if (active_width & MLX5_IB_WIDTH_1X) {
1115                 *ib_width = IB_WIDTH_1X;
1116         } else if (active_width & MLX5_IB_WIDTH_2X) {
1117                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1118                             (int)active_width);
1119                 err = -EINVAL;
1120         } else if (active_width & MLX5_IB_WIDTH_4X) {
1121                 *ib_width = IB_WIDTH_4X;
1122         } else if (active_width & MLX5_IB_WIDTH_8X) {
1123                 *ib_width = IB_WIDTH_8X;
1124         } else if (active_width & MLX5_IB_WIDTH_12X) {
1125                 *ib_width = IB_WIDTH_12X;
1126         } else {
1127                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1128                             (int)active_width);
1129                 err = -EINVAL;
1130         }
1131
1132         return err;
1133 }
1134
1135 static int mlx5_mtu_to_ib_mtu(int mtu)
1136 {
1137         switch (mtu) {
1138         case 256: return 1;
1139         case 512: return 2;
1140         case 1024: return 3;
1141         case 2048: return 4;
1142         case 4096: return 5;
1143         default:
1144                 pr_warn("invalid mtu\n");
1145                 return -1;
1146         }
1147 }
1148
1149 enum ib_max_vl_num {
1150         __IB_MAX_VL_0           = 1,
1151         __IB_MAX_VL_0_1         = 2,
1152         __IB_MAX_VL_0_3         = 3,
1153         __IB_MAX_VL_0_7         = 4,
1154         __IB_MAX_VL_0_14        = 5,
1155 };
1156
1157 enum mlx5_vl_hw_cap {
1158         MLX5_VL_HW_0    = 1,
1159         MLX5_VL_HW_0_1  = 2,
1160         MLX5_VL_HW_0_2  = 3,
1161         MLX5_VL_HW_0_3  = 4,
1162         MLX5_VL_HW_0_4  = 5,
1163         MLX5_VL_HW_0_5  = 6,
1164         MLX5_VL_HW_0_6  = 7,
1165         MLX5_VL_HW_0_7  = 8,
1166         MLX5_VL_HW_0_14 = 15
1167 };
1168
1169 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1170                                 u8 *max_vl_num)
1171 {
1172         switch (vl_hw_cap) {
1173         case MLX5_VL_HW_0:
1174                 *max_vl_num = __IB_MAX_VL_0;
1175                 break;
1176         case MLX5_VL_HW_0_1:
1177                 *max_vl_num = __IB_MAX_VL_0_1;
1178                 break;
1179         case MLX5_VL_HW_0_3:
1180                 *max_vl_num = __IB_MAX_VL_0_3;
1181                 break;
1182         case MLX5_VL_HW_0_7:
1183                 *max_vl_num = __IB_MAX_VL_0_7;
1184                 break;
1185         case MLX5_VL_HW_0_14:
1186                 *max_vl_num = __IB_MAX_VL_0_14;
1187                 break;
1188
1189         default:
1190                 return -EINVAL;
1191         }
1192
1193         return 0;
1194 }
1195
1196 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1197                                struct ib_port_attr *props)
1198 {
1199         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1200         struct mlx5_core_dev *mdev = dev->mdev;
1201         struct mlx5_hca_vport_context *rep;
1202         u16 max_mtu;
1203         u16 oper_mtu;
1204         int err;
1205         u8 ib_link_width_oper;
1206         u8 vl_hw_cap;
1207
1208         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1209         if (!rep) {
1210                 err = -ENOMEM;
1211                 goto out;
1212         }
1213
1214         /* props being zeroed by the caller, avoid zeroing it here */
1215
1216         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1217         if (err)
1218                 goto out;
1219
1220         props->lid              = rep->lid;
1221         props->lmc              = rep->lmc;
1222         props->sm_lid           = rep->sm_lid;
1223         props->sm_sl            = rep->sm_sl;
1224         props->state            = rep->vport_state;
1225         props->phys_state       = rep->port_physical_state;
1226         props->port_cap_flags   = rep->cap_mask1;
1227         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1228         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1229         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1230         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1231         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1232         props->subnet_timeout   = rep->subnet_timeout;
1233         props->init_type_reply  = rep->init_type_reply;
1234         props->grh_required     = rep->grh_required;
1235
1236         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1237         if (err)
1238                 goto out;
1239
1240         err = translate_active_width(ibdev, ib_link_width_oper,
1241                                      &props->active_width);
1242         if (err)
1243                 goto out;
1244         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1245         if (err)
1246                 goto out;
1247
1248         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1249
1250         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1251
1252         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1253
1254         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1255
1256         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1257         if (err)
1258                 goto out;
1259
1260         err = translate_max_vl_num(ibdev, vl_hw_cap,
1261                                    &props->max_vl_num);
1262 out:
1263         kfree(rep);
1264         return err;
1265 }
1266
1267 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1268                        struct ib_port_attr *props)
1269 {
1270         unsigned int count;
1271         int ret;
1272
1273         switch (mlx5_get_vport_access_method(ibdev)) {
1274         case MLX5_VPORT_ACCESS_METHOD_MAD:
1275                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1276                 break;
1277
1278         case MLX5_VPORT_ACCESS_METHOD_HCA:
1279                 ret = mlx5_query_hca_port(ibdev, port, props);
1280                 break;
1281
1282         case MLX5_VPORT_ACCESS_METHOD_NIC:
1283                 ret = mlx5_query_port_roce(ibdev, port, props);
1284                 break;
1285
1286         default:
1287                 ret = -EINVAL;
1288         }
1289
1290         if (!ret && props) {
1291                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1292                 struct mlx5_core_dev *mdev;
1293                 bool put_mdev = true;
1294
1295                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1296                 if (!mdev) {
1297                         /* If the port isn't affiliated yet query the master.
1298                          * The master and slave will have the same values.
1299                          */
1300                         mdev = dev->mdev;
1301                         port = 1;
1302                         put_mdev = false;
1303                 }
1304                 count = mlx5_core_reserved_gids_count(mdev);
1305                 if (put_mdev)
1306                         mlx5_ib_put_native_port_mdev(dev, port);
1307                 props->gid_tbl_len -= count;
1308         }
1309         return ret;
1310 }
1311
1312 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1313                                   struct ib_port_attr *props)
1314 {
1315         int ret;
1316
1317         /* Only link layer == ethernet is valid for representors */
1318         ret = mlx5_query_port_roce(ibdev, port, props);
1319         if (ret || !props)
1320                 return ret;
1321
1322         /* We don't support GIDS */
1323         props->gid_tbl_len = 0;
1324
1325         return ret;
1326 }
1327
1328 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1329                              union ib_gid *gid)
1330 {
1331         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1332         struct mlx5_core_dev *mdev = dev->mdev;
1333
1334         switch (mlx5_get_vport_access_method(ibdev)) {
1335         case MLX5_VPORT_ACCESS_METHOD_MAD:
1336                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1337
1338         case MLX5_VPORT_ACCESS_METHOD_HCA:
1339                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1340
1341         default:
1342                 return -EINVAL;
1343         }
1344
1345 }
1346
1347 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1348                                    u16 index, u16 *pkey)
1349 {
1350         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1351         struct mlx5_core_dev *mdev;
1352         bool put_mdev = true;
1353         u8 mdev_port_num;
1354         int err;
1355
1356         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1357         if (!mdev) {
1358                 /* The port isn't affiliated yet, get the PKey from the master
1359                  * port. For RoCE the PKey tables will be the same.
1360                  */
1361                 put_mdev = false;
1362                 mdev = dev->mdev;
1363                 mdev_port_num = 1;
1364         }
1365
1366         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1367                                         index, pkey);
1368         if (put_mdev)
1369                 mlx5_ib_put_native_port_mdev(dev, port);
1370
1371         return err;
1372 }
1373
1374 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1375                               u16 *pkey)
1376 {
1377         switch (mlx5_get_vport_access_method(ibdev)) {
1378         case MLX5_VPORT_ACCESS_METHOD_MAD:
1379                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1380
1381         case MLX5_VPORT_ACCESS_METHOD_HCA:
1382         case MLX5_VPORT_ACCESS_METHOD_NIC:
1383                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1384         default:
1385                 return -EINVAL;
1386         }
1387 }
1388
1389 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1390                                  struct ib_device_modify *props)
1391 {
1392         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1393         struct mlx5_reg_node_desc in;
1394         struct mlx5_reg_node_desc out;
1395         int err;
1396
1397         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1398                 return -EOPNOTSUPP;
1399
1400         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1401                 return 0;
1402
1403         /*
1404          * If possible, pass node desc to FW, so it can generate
1405          * a 144 trap.  If cmd fails, just ignore.
1406          */
1407         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1408         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1409                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1410         if (err)
1411                 return err;
1412
1413         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1414
1415         return err;
1416 }
1417
1418 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1419                                 u32 value)
1420 {
1421         struct mlx5_hca_vport_context ctx = {};
1422         struct mlx5_core_dev *mdev;
1423         u8 mdev_port_num;
1424         int err;
1425
1426         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1427         if (!mdev)
1428                 return -ENODEV;
1429
1430         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1431         if (err)
1432                 goto out;
1433
1434         if (~ctx.cap_mask1_perm & mask) {
1435                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1436                              mask, ctx.cap_mask1_perm);
1437                 err = -EINVAL;
1438                 goto out;
1439         }
1440
1441         ctx.cap_mask1 = value;
1442         ctx.cap_mask1_perm = mask;
1443         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1444                                                  0, &ctx);
1445
1446 out:
1447         mlx5_ib_put_native_port_mdev(dev, port_num);
1448
1449         return err;
1450 }
1451
1452 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1453                                struct ib_port_modify *props)
1454 {
1455         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1456         struct ib_port_attr attr;
1457         u32 tmp;
1458         int err;
1459         u32 change_mask;
1460         u32 value;
1461         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1462                       IB_LINK_LAYER_INFINIBAND);
1463
1464         /* CM layer calls ib_modify_port() regardless of the link layer. For
1465          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1466          */
1467         if (!is_ib)
1468                 return 0;
1469
1470         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1471                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1472                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1473                 return set_port_caps_atomic(dev, port, change_mask, value);
1474         }
1475
1476         mutex_lock(&dev->cap_mask_mutex);
1477
1478         err = ib_query_port(ibdev, port, &attr);
1479         if (err)
1480                 goto out;
1481
1482         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1483                 ~props->clr_port_cap_mask;
1484
1485         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1486
1487 out:
1488         mutex_unlock(&dev->cap_mask_mutex);
1489         return err;
1490 }
1491
1492 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1493 {
1494         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1495                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1496 }
1497
1498 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1499 {
1500         /* Large page with non 4k uar support might limit the dynamic size */
1501         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1502                 return MLX5_MIN_DYN_BFREGS;
1503
1504         return MLX5_MAX_DYN_BFREGS;
1505 }
1506
1507 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1508                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1509                              struct mlx5_bfreg_info *bfregi)
1510 {
1511         int uars_per_sys_page;
1512         int bfregs_per_sys_page;
1513         int ref_bfregs = req->total_num_bfregs;
1514
1515         if (req->total_num_bfregs == 0)
1516                 return -EINVAL;
1517
1518         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1519         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1520
1521         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1522                 return -ENOMEM;
1523
1524         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1525         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1526         /* This holds the required static allocation asked by the user */
1527         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1528         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1529                 return -EINVAL;
1530
1531         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1532         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1533         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1534         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1535
1536         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1537                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1538                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1539                     req->total_num_bfregs, bfregi->total_num_bfregs,
1540                     bfregi->num_sys_pages);
1541
1542         return 0;
1543 }
1544
1545 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1546 {
1547         struct mlx5_bfreg_info *bfregi;
1548         int err;
1549         int i;
1550
1551         bfregi = &context->bfregi;
1552         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1553                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1554                 if (err)
1555                         goto error;
1556
1557                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1558         }
1559
1560         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1561                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1562
1563         return 0;
1564
1565 error:
1566         for (--i; i >= 0; i--)
1567                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1568                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1569
1570         return err;
1571 }
1572
1573 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1574 {
1575         struct mlx5_bfreg_info *bfregi;
1576         int err;
1577         int i;
1578
1579         bfregi = &context->bfregi;
1580         for (i = 0; i < bfregi->num_sys_pages; i++) {
1581                 if (i < bfregi->num_static_sys_pages ||
1582                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1583                         err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1584                         if (err) {
1585                                 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1586                                 return err;
1587                         }
1588                 }
1589         }
1590
1591         return 0;
1592 }
1593
1594 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1595 {
1596         int err;
1597
1598         err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1599         if (err)
1600                 return err;
1601
1602         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1603             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1604              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1605                 return err;
1606
1607         mutex_lock(&dev->lb_mutex);
1608         dev->user_td++;
1609
1610         if (dev->user_td == 2)
1611                 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1612
1613         mutex_unlock(&dev->lb_mutex);
1614         return err;
1615 }
1616
1617 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1618 {
1619         mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1620
1621         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1622             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1623              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1624                 return;
1625
1626         mutex_lock(&dev->lb_mutex);
1627         dev->user_td--;
1628
1629         if (dev->user_td < 2)
1630                 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1631
1632         mutex_unlock(&dev->lb_mutex);
1633 }
1634
1635 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1636                                                   struct ib_udata *udata)
1637 {
1638         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1639         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1640         struct mlx5_ib_alloc_ucontext_resp resp = {};
1641         struct mlx5_core_dev *mdev = dev->mdev;
1642         struct mlx5_ib_ucontext *context;
1643         struct mlx5_bfreg_info *bfregi;
1644         int ver;
1645         int err;
1646         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1647                                      max_cqe_version);
1648         bool lib_uar_4k;
1649
1650         if (!dev->ib_active)
1651                 return ERR_PTR(-EAGAIN);
1652
1653         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1654                 ver = 0;
1655         else if (udata->inlen >= min_req_v2)
1656                 ver = 2;
1657         else
1658                 return ERR_PTR(-EINVAL);
1659
1660         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1661         if (err)
1662                 return ERR_PTR(err);
1663
1664         if (req.flags)
1665                 return ERR_PTR(-EINVAL);
1666
1667         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1668                 return ERR_PTR(-EOPNOTSUPP);
1669
1670         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1671                                     MLX5_NON_FP_BFREGS_PER_UAR);
1672         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1673                 return ERR_PTR(-EINVAL);
1674
1675         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1676         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1677                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1678         resp.cache_line_size = cache_line_size();
1679         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1680         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1681         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1682         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1683         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1684         resp.cqe_version = min_t(__u8,
1685                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1686                                  req.max_cqe_version);
1687         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1688                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1689         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1690                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1691         resp.response_length = min(offsetof(typeof(resp), response_length) +
1692                                    sizeof(resp.response_length), udata->outlen);
1693
1694         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1695                 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1696                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1697                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1698                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1699                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1700                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1701                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1702                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1703                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1704         }
1705
1706         context = kzalloc(sizeof(*context), GFP_KERNEL);
1707         if (!context)
1708                 return ERR_PTR(-ENOMEM);
1709
1710         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1711         bfregi = &context->bfregi;
1712
1713         /* updates req->total_num_bfregs */
1714         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1715         if (err)
1716                 goto out_ctx;
1717
1718         mutex_init(&bfregi->lock);
1719         bfregi->lib_uar_4k = lib_uar_4k;
1720         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1721                                 GFP_KERNEL);
1722         if (!bfregi->count) {
1723                 err = -ENOMEM;
1724                 goto out_ctx;
1725         }
1726
1727         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1728                                     sizeof(*bfregi->sys_pages),
1729                                     GFP_KERNEL);
1730         if (!bfregi->sys_pages) {
1731                 err = -ENOMEM;
1732                 goto out_count;
1733         }
1734
1735         err = allocate_uars(dev, context);
1736         if (err)
1737                 goto out_sys_pages;
1738
1739 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1740         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1741 #endif
1742
1743         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1744                 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1745                 if (err)
1746                         goto out_uars;
1747         }
1748
1749         INIT_LIST_HEAD(&context->vma_private_list);
1750         mutex_init(&context->vma_private_list_mutex);
1751         INIT_LIST_HEAD(&context->db_page_list);
1752         mutex_init(&context->db_page_mutex);
1753
1754         resp.tot_bfregs = req.total_num_bfregs;
1755         resp.num_ports = dev->num_ports;
1756
1757         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1758                 resp.response_length += sizeof(resp.cqe_version);
1759
1760         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1761                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1762                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1763                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1764         }
1765
1766         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1767                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1768                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1769                         resp.eth_min_inline++;
1770                 }
1771                 resp.response_length += sizeof(resp.eth_min_inline);
1772         }
1773
1774         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1775                 if (mdev->clock_info)
1776                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1777                 resp.response_length += sizeof(resp.clock_info_versions);
1778         }
1779
1780         /*
1781          * We don't want to expose information from the PCI bar that is located
1782          * after 4096 bytes, so if the arch only supports larger pages, let's
1783          * pretend we don't support reading the HCA's core clock. This is also
1784          * forced by mmap function.
1785          */
1786         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1787                 if (PAGE_SIZE <= 4096) {
1788                         resp.comp_mask |=
1789                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1790                         resp.hca_core_clock_offset =
1791                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1792                 }
1793                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1794         }
1795
1796         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1797                 resp.response_length += sizeof(resp.log_uar_size);
1798
1799         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1800                 resp.response_length += sizeof(resp.num_uars_per_page);
1801
1802         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1803                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1804                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1805         }
1806
1807         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1808         if (err)
1809                 goto out_td;
1810
1811         bfregi->ver = ver;
1812         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1813         context->cqe_version = resp.cqe_version;
1814         context->lib_caps = req.lib_caps;
1815         print_lib_caps(dev, context->lib_caps);
1816
1817         return &context->ibucontext;
1818
1819 out_td:
1820         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1821                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1822
1823 out_uars:
1824         deallocate_uars(dev, context);
1825
1826 out_sys_pages:
1827         kfree(bfregi->sys_pages);
1828
1829 out_count:
1830         kfree(bfregi->count);
1831
1832 out_ctx:
1833         kfree(context);
1834
1835         return ERR_PTR(err);
1836 }
1837
1838 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1839 {
1840         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1841         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1842         struct mlx5_bfreg_info *bfregi;
1843
1844         bfregi = &context->bfregi;
1845         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1846                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1847
1848         deallocate_uars(dev, context);
1849         kfree(bfregi->sys_pages);
1850         kfree(bfregi->count);
1851         kfree(context);
1852
1853         return 0;
1854 }
1855
1856 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1857                                  int uar_idx)
1858 {
1859         int fw_uars_per_page;
1860
1861         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1862
1863         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1864 }
1865
1866 static int get_command(unsigned long offset)
1867 {
1868         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1869 }
1870
1871 static int get_arg(unsigned long offset)
1872 {
1873         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1874 }
1875
1876 static int get_index(unsigned long offset)
1877 {
1878         return get_arg(offset);
1879 }
1880
1881 /* Index resides in an extra byte to enable larger values than 255 */
1882 static int get_extended_index(unsigned long offset)
1883 {
1884         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1885 }
1886
1887 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1888 {
1889         /* vma_open is called when a new VMA is created on top of our VMA.  This
1890          * is done through either mremap flow or split_vma (usually due to
1891          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1892          * as this VMA is strongly hardware related.  Therefore we set the
1893          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1894          * calling us again and trying to do incorrect actions.  We assume that
1895          * the original VMA size is exactly a single page, and therefore all
1896          * "splitting" operation will not happen to it.
1897          */
1898         area->vm_ops = NULL;
1899 }
1900
1901 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1902 {
1903         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1904
1905         /* It's guaranteed that all VMAs opened on a FD are closed before the
1906          * file itself is closed, therefore no sync is needed with the regular
1907          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1908          * However need a sync with accessing the vma as part of
1909          * mlx5_ib_disassociate_ucontext.
1910          * The close operation is usually called under mm->mmap_sem except when
1911          * process is exiting.
1912          * The exiting case is handled explicitly as part of
1913          * mlx5_ib_disassociate_ucontext.
1914          */
1915         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1916
1917         /* setting the vma context pointer to null in the mlx5_ib driver's
1918          * private data, to protect a race condition in
1919          * mlx5_ib_disassociate_ucontext().
1920          */
1921         mlx5_ib_vma_priv_data->vma = NULL;
1922         mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1923         list_del(&mlx5_ib_vma_priv_data->list);
1924         mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1925         kfree(mlx5_ib_vma_priv_data);
1926 }
1927
1928 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1929         .open = mlx5_ib_vma_open,
1930         .close = mlx5_ib_vma_close
1931 };
1932
1933 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1934                                 struct mlx5_ib_ucontext *ctx)
1935 {
1936         struct mlx5_ib_vma_private_data *vma_prv;
1937         struct list_head *vma_head = &ctx->vma_private_list;
1938
1939         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1940         if (!vma_prv)
1941                 return -ENOMEM;
1942
1943         vma_prv->vma = vma;
1944         vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1945         vma->vm_private_data = vma_prv;
1946         vma->vm_ops =  &mlx5_ib_vm_ops;
1947
1948         mutex_lock(&ctx->vma_private_list_mutex);
1949         list_add(&vma_prv->list, vma_head);
1950         mutex_unlock(&ctx->vma_private_list_mutex);
1951
1952         return 0;
1953 }
1954
1955 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1956 {
1957         int ret;
1958         struct vm_area_struct *vma;
1959         struct mlx5_ib_vma_private_data *vma_private, *n;
1960         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1961         struct task_struct *owning_process  = NULL;
1962         struct mm_struct   *owning_mm       = NULL;
1963
1964         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1965         if (!owning_process)
1966                 return;
1967
1968         owning_mm = get_task_mm(owning_process);
1969         if (!owning_mm) {
1970                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1971                 while (1) {
1972                         put_task_struct(owning_process);
1973                         usleep_range(1000, 2000);
1974                         owning_process = get_pid_task(ibcontext->tgid,
1975                                                       PIDTYPE_PID);
1976                         if (!owning_process ||
1977                             owning_process->state == TASK_DEAD) {
1978                                 pr_info("disassociate ucontext done, task was terminated\n");
1979                                 /* in case task was dead need to release the
1980                                  * task struct.
1981                                  */
1982                                 if (owning_process)
1983                                         put_task_struct(owning_process);
1984                                 return;
1985                         }
1986                 }
1987         }
1988
1989         /* need to protect from a race on closing the vma as part of
1990          * mlx5_ib_vma_close.
1991          */
1992         down_write(&owning_mm->mmap_sem);
1993         mutex_lock(&context->vma_private_list_mutex);
1994         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1995                                  list) {
1996                 vma = vma_private->vma;
1997                 ret = zap_vma_ptes(vma, vma->vm_start,
1998                                    PAGE_SIZE);
1999                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
2000                 /* context going to be destroyed, should
2001                  * not access ops any more.
2002                  */
2003                 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
2004                 vma->vm_ops = NULL;
2005                 list_del(&vma_private->list);
2006                 kfree(vma_private);
2007         }
2008         mutex_unlock(&context->vma_private_list_mutex);
2009         up_write(&owning_mm->mmap_sem);
2010         mmput(owning_mm);
2011         put_task_struct(owning_process);
2012 }
2013
2014 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2015 {
2016         switch (cmd) {
2017         case MLX5_IB_MMAP_WC_PAGE:
2018                 return "WC";
2019         case MLX5_IB_MMAP_REGULAR_PAGE:
2020                 return "best effort WC";
2021         case MLX5_IB_MMAP_NC_PAGE:
2022                 return "NC";
2023         case MLX5_IB_MMAP_DEVICE_MEM:
2024                 return "Device Memory";
2025         default:
2026                 return NULL;
2027         }
2028 }
2029
2030 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2031                                         struct vm_area_struct *vma,
2032                                         struct mlx5_ib_ucontext *context)
2033 {
2034         phys_addr_t pfn;
2035         int err;
2036
2037         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2038                 return -EINVAL;
2039
2040         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2041                 return -EOPNOTSUPP;
2042
2043         if (vma->vm_flags & VM_WRITE)
2044                 return -EPERM;
2045
2046         if (!dev->mdev->clock_info_page)
2047                 return -EOPNOTSUPP;
2048
2049         pfn = page_to_pfn(dev->mdev->clock_info_page);
2050         err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2051                               vma->vm_page_prot);
2052         if (err)
2053                 return err;
2054
2055         mlx5_ib_dbg(dev, "mapped clock info at 0x%lx, PA 0x%llx\n",
2056                     vma->vm_start,
2057                     (unsigned long long)pfn << PAGE_SHIFT);
2058
2059         return mlx5_ib_set_vma_data(vma, context);
2060 }
2061
2062 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2063                     struct vm_area_struct *vma,
2064                     struct mlx5_ib_ucontext *context)
2065 {
2066         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2067         int err;
2068         unsigned long idx;
2069         phys_addr_t pfn, pa;
2070         pgprot_t prot;
2071         u32 bfreg_dyn_idx = 0;
2072         u32 uar_index;
2073         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2074         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2075                                 bfregi->num_static_sys_pages;
2076
2077         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2078                 return -EINVAL;
2079
2080         if (dyn_uar)
2081                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2082         else
2083                 idx = get_index(vma->vm_pgoff);
2084
2085         if (idx >= max_valid_idx) {
2086                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2087                              idx, max_valid_idx);
2088                 return -EINVAL;
2089         }
2090
2091         switch (cmd) {
2092         case MLX5_IB_MMAP_WC_PAGE:
2093         case MLX5_IB_MMAP_ALLOC_WC:
2094 /* Some architectures don't support WC memory */
2095 #if defined(CONFIG_X86)
2096                 if (!pat_enabled())
2097                         return -EPERM;
2098 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2099                         return -EPERM;
2100 #endif
2101         /* fall through */
2102         case MLX5_IB_MMAP_REGULAR_PAGE:
2103                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2104                 prot = pgprot_writecombine(vma->vm_page_prot);
2105                 break;
2106         case MLX5_IB_MMAP_NC_PAGE:
2107                 prot = pgprot_noncached(vma->vm_page_prot);
2108                 break;
2109         default:
2110                 return -EINVAL;
2111         }
2112
2113         if (dyn_uar) {
2114                 int uars_per_page;
2115
2116                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2117                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2118                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2119                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2120                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2121                         return -EINVAL;
2122                 }
2123
2124                 mutex_lock(&bfregi->lock);
2125                 /* Fail if uar already allocated, first bfreg index of each
2126                  * page holds its count.
2127                  */
2128                 if (bfregi->count[bfreg_dyn_idx]) {
2129                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2130                         mutex_unlock(&bfregi->lock);
2131                         return -EINVAL;
2132                 }
2133
2134                 bfregi->count[bfreg_dyn_idx]++;
2135                 mutex_unlock(&bfregi->lock);
2136
2137                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2138                 if (err) {
2139                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2140                         goto free_bfreg;
2141                 }
2142         } else {
2143                 uar_index = bfregi->sys_pages[idx];
2144         }
2145
2146         pfn = uar_index2pfn(dev, uar_index);
2147         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2148
2149         vma->vm_page_prot = prot;
2150         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2151                                  PAGE_SIZE, vma->vm_page_prot);
2152         if (err) {
2153                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2154                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
2155                 err = -EAGAIN;
2156                 goto err;
2157         }
2158
2159         pa = pfn << PAGE_SHIFT;
2160         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
2161                     vma->vm_start, &pa);
2162
2163         err = mlx5_ib_set_vma_data(vma, context);
2164         if (err)
2165                 goto err;
2166
2167         if (dyn_uar)
2168                 bfregi->sys_pages[idx] = uar_index;
2169         return 0;
2170
2171 err:
2172         if (!dyn_uar)
2173                 return err;
2174
2175         mlx5_cmd_free_uar(dev->mdev, idx);
2176
2177 free_bfreg:
2178         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2179
2180         return err;
2181 }
2182
2183 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2184 {
2185         struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2186         struct mlx5_ib_dev *dev = to_mdev(context->device);
2187         u16 page_idx = get_extended_index(vma->vm_pgoff);
2188         size_t map_size = vma->vm_end - vma->vm_start;
2189         u32 npages = map_size >> PAGE_SHIFT;
2190         phys_addr_t pfn;
2191         pgprot_t prot;
2192
2193         if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2194             page_idx + npages)
2195                 return -EINVAL;
2196
2197         pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2198               MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2199               PAGE_SHIFT) +
2200               page_idx;
2201         prot = pgprot_writecombine(vma->vm_page_prot);
2202         vma->vm_page_prot = prot;
2203
2204         if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2205                                vma->vm_page_prot))
2206                 return -EAGAIN;
2207
2208         return mlx5_ib_set_vma_data(vma, mctx);
2209 }
2210
2211 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2212 {
2213         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2214         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2215         unsigned long command;
2216         phys_addr_t pfn;
2217
2218         command = get_command(vma->vm_pgoff);
2219         switch (command) {
2220         case MLX5_IB_MMAP_WC_PAGE:
2221         case MLX5_IB_MMAP_NC_PAGE:
2222         case MLX5_IB_MMAP_REGULAR_PAGE:
2223         case MLX5_IB_MMAP_ALLOC_WC:
2224                 return uar_mmap(dev, command, vma, context);
2225
2226         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2227                 return -ENOSYS;
2228
2229         case MLX5_IB_MMAP_CORE_CLOCK:
2230                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2231                         return -EINVAL;
2232
2233                 if (vma->vm_flags & VM_WRITE)
2234                         return -EPERM;
2235
2236                 /* Don't expose to user-space information it shouldn't have */
2237                 if (PAGE_SIZE > 4096)
2238                         return -EOPNOTSUPP;
2239
2240                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2241                 pfn = (dev->mdev->iseg_base +
2242                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2243                         PAGE_SHIFT;
2244                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2245                                        PAGE_SIZE, vma->vm_page_prot))
2246                         return -EAGAIN;
2247
2248                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2249                             vma->vm_start,
2250                             (unsigned long long)pfn << PAGE_SHIFT);
2251                 break;
2252         case MLX5_IB_MMAP_CLOCK_INFO:
2253                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2254
2255         case MLX5_IB_MMAP_DEVICE_MEM:
2256                 return dm_mmap(ibcontext, vma);
2257
2258         default:
2259                 return -EINVAL;
2260         }
2261
2262         return 0;
2263 }
2264
2265 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2266                                struct ib_ucontext *context,
2267                                struct ib_dm_alloc_attr *attr,
2268                                struct uverbs_attr_bundle *attrs)
2269 {
2270         u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2271         struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2272         phys_addr_t memic_addr;
2273         struct mlx5_ib_dm *dm;
2274         u64 start_offset;
2275         u32 page_idx;
2276         int err;
2277
2278         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2279         if (!dm)
2280                 return ERR_PTR(-ENOMEM);
2281
2282         mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2283                     attr->length, act_size, attr->alignment);
2284
2285         err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2286                                    act_size, attr->alignment);
2287         if (err)
2288                 goto err_free;
2289
2290         start_offset = memic_addr & ~PAGE_MASK;
2291         page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2292                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2293                     PAGE_SHIFT;
2294
2295         err = uverbs_copy_to(attrs,
2296                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2297                              &start_offset, sizeof(start_offset));
2298         if (err)
2299                 goto err_dealloc;
2300
2301         err = uverbs_copy_to(attrs,
2302                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2303                              &page_idx, sizeof(page_idx));
2304         if (err)
2305                 goto err_dealloc;
2306
2307         bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2308                    DIV_ROUND_UP(act_size, PAGE_SIZE));
2309
2310         dm->dev_addr = memic_addr;
2311
2312         return &dm->ibdm;
2313
2314 err_dealloc:
2315         mlx5_cmd_dealloc_memic(memic, memic_addr,
2316                                act_size);
2317 err_free:
2318         kfree(dm);
2319         return ERR_PTR(err);
2320 }
2321
2322 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2323 {
2324         struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2325         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2326         u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2327         u32 page_idx;
2328         int ret;
2329
2330         ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2331         if (ret)
2332                 return ret;
2333
2334         page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2335                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2336                     PAGE_SHIFT;
2337         bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2338                      page_idx,
2339                      DIV_ROUND_UP(act_size, PAGE_SIZE));
2340
2341         kfree(dm);
2342
2343         return 0;
2344 }
2345
2346 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2347                                       struct ib_ucontext *context,
2348                                       struct ib_udata *udata)
2349 {
2350         struct mlx5_ib_alloc_pd_resp resp;
2351         struct mlx5_ib_pd *pd;
2352         int err;
2353
2354         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2355         if (!pd)
2356                 return ERR_PTR(-ENOMEM);
2357
2358         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2359         if (err) {
2360                 kfree(pd);
2361                 return ERR_PTR(err);
2362         }
2363
2364         if (context) {
2365                 resp.pdn = pd->pdn;
2366                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2367                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2368                         kfree(pd);
2369                         return ERR_PTR(-EFAULT);
2370                 }
2371         }
2372
2373         return &pd->ibpd;
2374 }
2375
2376 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2377 {
2378         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2379         struct mlx5_ib_pd *mpd = to_mpd(pd);
2380
2381         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2382         kfree(mpd);
2383
2384         return 0;
2385 }
2386
2387 enum {
2388         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2389         MATCH_CRITERIA_ENABLE_MISC_BIT,
2390         MATCH_CRITERIA_ENABLE_INNER_BIT
2391 };
2392
2393 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2394         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2395                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2396
2397 static u8 get_match_criteria_enable(u32 *match_criteria)
2398 {
2399         u8 match_criteria_enable;
2400
2401         match_criteria_enable =
2402                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2403                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2404         match_criteria_enable |=
2405                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2406                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2407         match_criteria_enable |=
2408                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2409                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2410
2411         return match_criteria_enable;
2412 }
2413
2414 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2415 {
2416         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2417         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2418 }
2419
2420 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
2421                            bool inner)
2422 {
2423         if (inner) {
2424                 MLX5_SET(fte_match_set_misc,
2425                          misc_c, inner_ipv6_flow_label, mask);
2426                 MLX5_SET(fte_match_set_misc,
2427                          misc_v, inner_ipv6_flow_label, val);
2428         } else {
2429                 MLX5_SET(fte_match_set_misc,
2430                          misc_c, outer_ipv6_flow_label, mask);
2431                 MLX5_SET(fte_match_set_misc,
2432                          misc_v, outer_ipv6_flow_label, val);
2433         }
2434 }
2435
2436 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2437 {
2438         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2439         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2440         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2441         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2442 }
2443
2444 #define LAST_ETH_FIELD vlan_tag
2445 #define LAST_IB_FIELD sl
2446 #define LAST_IPV4_FIELD tos
2447 #define LAST_IPV6_FIELD traffic_class
2448 #define LAST_TCP_UDP_FIELD src_port
2449 #define LAST_TUNNEL_FIELD tunnel_id
2450 #define LAST_FLOW_TAG_FIELD tag_id
2451 #define LAST_DROP_FIELD size
2452 #define LAST_COUNTERS_FIELD counters
2453
2454 /* Field is the last supported field */
2455 #define FIELDS_NOT_SUPPORTED(filter, field)\
2456         memchr_inv((void *)&filter.field  +\
2457                    sizeof(filter.field), 0,\
2458                    sizeof(filter) -\
2459                    offsetof(typeof(filter), field) -\
2460                    sizeof(filter.field))
2461
2462 static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2463                                   const struct ib_flow_attr *flow_attr,
2464                                   struct mlx5_flow_act *action)
2465 {
2466         struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2467
2468         switch (maction->ib_action.type) {
2469         case IB_FLOW_ACTION_ESP:
2470                 /* Currently only AES_GCM keymat is supported by the driver */
2471                 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2472                 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2473                         MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2474                         MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2475                 return 0;
2476         default:
2477                 return -EOPNOTSUPP;
2478         }
2479 }
2480
2481 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2482                            u32 *match_v, const union ib_flow_spec *ib_spec,
2483                            const struct ib_flow_attr *flow_attr,
2484                            struct mlx5_flow_act *action)
2485 {
2486         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2487                                            misc_parameters);
2488         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2489                                            misc_parameters);
2490         void *headers_c;
2491         void *headers_v;
2492         int match_ipv;
2493         int ret;
2494
2495         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2496                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2497                                          inner_headers);
2498                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2499                                          inner_headers);
2500                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2501                                         ft_field_support.inner_ip_version);
2502         } else {
2503                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2504                                          outer_headers);
2505                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2506                                          outer_headers);
2507                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2508                                         ft_field_support.outer_ip_version);
2509         }
2510
2511         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2512         case IB_FLOW_SPEC_ETH:
2513                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2514                         return -EOPNOTSUPP;
2515
2516                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2517                                              dmac_47_16),
2518                                 ib_spec->eth.mask.dst_mac);
2519                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2520                                              dmac_47_16),
2521                                 ib_spec->eth.val.dst_mac);
2522
2523                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2524                                              smac_47_16),
2525                                 ib_spec->eth.mask.src_mac);
2526                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2527                                              smac_47_16),
2528                                 ib_spec->eth.val.src_mac);
2529
2530                 if (ib_spec->eth.mask.vlan_tag) {
2531                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2532                                  cvlan_tag, 1);
2533                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2534                                  cvlan_tag, 1);
2535
2536                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2537                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2538                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2539                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2540
2541                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2542                                  first_cfi,
2543                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2544                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2545                                  first_cfi,
2546                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2547
2548                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2549                                  first_prio,
2550                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2551                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2552                                  first_prio,
2553                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2554                 }
2555                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2556                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2557                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2558                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2559                 break;
2560         case IB_FLOW_SPEC_IPV4:
2561                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2562                         return -EOPNOTSUPP;
2563
2564                 if (match_ipv) {
2565                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2566                                  ip_version, 0xf);
2567                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2568                                  ip_version, MLX5_FS_IPV4_VERSION);
2569                 } else {
2570                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2571                                  ethertype, 0xffff);
2572                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2573                                  ethertype, ETH_P_IP);
2574                 }
2575
2576                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2577                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2578                        &ib_spec->ipv4.mask.src_ip,
2579                        sizeof(ib_spec->ipv4.mask.src_ip));
2580                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2581                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2582                        &ib_spec->ipv4.val.src_ip,
2583                        sizeof(ib_spec->ipv4.val.src_ip));
2584                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2585                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2586                        &ib_spec->ipv4.mask.dst_ip,
2587                        sizeof(ib_spec->ipv4.mask.dst_ip));
2588                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2589                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2590                        &ib_spec->ipv4.val.dst_ip,
2591                        sizeof(ib_spec->ipv4.val.dst_ip));
2592
2593                 set_tos(headers_c, headers_v,
2594                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2595
2596                 set_proto(headers_c, headers_v,
2597                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2598                 break;
2599         case IB_FLOW_SPEC_IPV6:
2600                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2601                         return -EOPNOTSUPP;
2602
2603                 if (match_ipv) {
2604                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2605                                  ip_version, 0xf);
2606                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2607                                  ip_version, MLX5_FS_IPV6_VERSION);
2608                 } else {
2609                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2610                                  ethertype, 0xffff);
2611                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2612                                  ethertype, ETH_P_IPV6);
2613                 }
2614
2615                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2616                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2617                        &ib_spec->ipv6.mask.src_ip,
2618                        sizeof(ib_spec->ipv6.mask.src_ip));
2619                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2620                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2621                        &ib_spec->ipv6.val.src_ip,
2622                        sizeof(ib_spec->ipv6.val.src_ip));
2623                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2624                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2625                        &ib_spec->ipv6.mask.dst_ip,
2626                        sizeof(ib_spec->ipv6.mask.dst_ip));
2627                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2628                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2629                        &ib_spec->ipv6.val.dst_ip,
2630                        sizeof(ib_spec->ipv6.val.dst_ip));
2631
2632                 set_tos(headers_c, headers_v,
2633                         ib_spec->ipv6.mask.traffic_class,
2634                         ib_spec->ipv6.val.traffic_class);
2635
2636                 set_proto(headers_c, headers_v,
2637                           ib_spec->ipv6.mask.next_hdr,
2638                           ib_spec->ipv6.val.next_hdr);
2639
2640                 set_flow_label(misc_params_c, misc_params_v,
2641                                ntohl(ib_spec->ipv6.mask.flow_label),
2642                                ntohl(ib_spec->ipv6.val.flow_label),
2643                                ib_spec->type & IB_FLOW_SPEC_INNER);
2644                 break;
2645         case IB_FLOW_SPEC_ESP:
2646                 if (ib_spec->esp.mask.seq)
2647                         return -EOPNOTSUPP;
2648
2649                 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2650                          ntohl(ib_spec->esp.mask.spi));
2651                 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2652                          ntohl(ib_spec->esp.val.spi));
2653                 break;
2654         case IB_FLOW_SPEC_TCP:
2655                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2656                                          LAST_TCP_UDP_FIELD))
2657                         return -EOPNOTSUPP;
2658
2659                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2660                          0xff);
2661                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2662                          IPPROTO_TCP);
2663
2664                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2665                          ntohs(ib_spec->tcp_udp.mask.src_port));
2666                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2667                          ntohs(ib_spec->tcp_udp.val.src_port));
2668
2669                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2670                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2671                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2672                          ntohs(ib_spec->tcp_udp.val.dst_port));
2673                 break;
2674         case IB_FLOW_SPEC_UDP:
2675                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2676                                          LAST_TCP_UDP_FIELD))
2677                         return -EOPNOTSUPP;
2678
2679                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2680                          0xff);
2681                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2682                          IPPROTO_UDP);
2683
2684                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2685                          ntohs(ib_spec->tcp_udp.mask.src_port));
2686                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2687                          ntohs(ib_spec->tcp_udp.val.src_port));
2688
2689                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2690                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2691                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2692                          ntohs(ib_spec->tcp_udp.val.dst_port));
2693                 break;
2694         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2695                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2696                                          LAST_TUNNEL_FIELD))
2697                         return -EOPNOTSUPP;
2698
2699                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2700                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2701                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2702                          ntohl(ib_spec->tunnel.val.tunnel_id));
2703                 break;
2704         case IB_FLOW_SPEC_ACTION_TAG:
2705                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2706                                          LAST_FLOW_TAG_FIELD))
2707                         return -EOPNOTSUPP;
2708                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2709                         return -EINVAL;
2710
2711                 action->flow_tag = ib_spec->flow_tag.tag_id;
2712                 action->has_flow_tag = true;
2713                 break;
2714         case IB_FLOW_SPEC_ACTION_DROP:
2715                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2716                                          LAST_DROP_FIELD))
2717                         return -EOPNOTSUPP;
2718                 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2719                 break;
2720         case IB_FLOW_SPEC_ACTION_HANDLE:
2721                 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2722                 if (ret)
2723                         return ret;
2724                 break;
2725         case IB_FLOW_SPEC_ACTION_COUNT:
2726                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2727                                          LAST_COUNTERS_FIELD))
2728                         return -EOPNOTSUPP;
2729
2730                 /* for now support only one counters spec per flow */
2731                 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2732                         return -EINVAL;
2733
2734                 action->counters = ib_spec->flow_count.counters;
2735                 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2736                 break;
2737         default:
2738                 return -EINVAL;
2739         }
2740
2741         return 0;
2742 }
2743
2744 /* If a flow could catch both multicast and unicast packets,
2745  * it won't fall into the multicast flow steering table and this rule
2746  * could steal other multicast packets.
2747  */
2748 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2749 {
2750         union ib_flow_spec *flow_spec;
2751
2752         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2753             ib_attr->num_of_specs < 1)
2754                 return false;
2755
2756         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2757         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2758                 struct ib_flow_spec_ipv4 *ipv4_spec;
2759
2760                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2761                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2762                         return true;
2763
2764                 return false;
2765         }
2766
2767         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2768                 struct ib_flow_spec_eth *eth_spec;
2769
2770                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2771                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2772                        is_multicast_ether_addr(eth_spec->val.dst_mac);
2773         }
2774
2775         return false;
2776 }
2777
2778 enum valid_spec {
2779         VALID_SPEC_INVALID,
2780         VALID_SPEC_VALID,
2781         VALID_SPEC_NA,
2782 };
2783
2784 static enum valid_spec
2785 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2786                      const struct mlx5_flow_spec *spec,
2787                      const struct mlx5_flow_act *flow_act,
2788                      bool egress)
2789 {
2790         const u32 *match_c = spec->match_criteria;
2791         bool is_crypto =
2792                 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2793                                      MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2794         bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2795         bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2796
2797         /*
2798          * Currently only crypto is supported in egress, when regular egress
2799          * rules would be supported, always return VALID_SPEC_NA.
2800          */
2801         if (!is_crypto)
2802                 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2803
2804         return is_crypto && is_ipsec &&
2805                 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2806                 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2807 }
2808
2809 static bool is_valid_spec(struct mlx5_core_dev *mdev,
2810                           const struct mlx5_flow_spec *spec,
2811                           const struct mlx5_flow_act *flow_act,
2812                           bool egress)
2813 {
2814         /* We curretly only support ipsec egress flow */
2815         return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2816 }
2817
2818 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2819                                const struct ib_flow_attr *flow_attr,
2820                                bool check_inner)
2821 {
2822         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2823         int match_ipv = check_inner ?
2824                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2825                                         ft_field_support.inner_ip_version) :
2826                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2827                                         ft_field_support.outer_ip_version);
2828         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2829         bool ipv4_spec_valid, ipv6_spec_valid;
2830         unsigned int ip_spec_type = 0;
2831         bool has_ethertype = false;
2832         unsigned int spec_index;
2833         bool mask_valid = true;
2834         u16 eth_type = 0;
2835         bool type_valid;
2836
2837         /* Validate that ethertype is correct */
2838         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2839                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2840                     ib_spec->eth.mask.ether_type) {
2841                         mask_valid = (ib_spec->eth.mask.ether_type ==
2842                                       htons(0xffff));
2843                         has_ethertype = true;
2844                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2845                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2846                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2847                         ip_spec_type = ib_spec->type;
2848                 }
2849                 ib_spec = (void *)ib_spec + ib_spec->size;
2850         }
2851
2852         type_valid = (!has_ethertype) || (!ip_spec_type);
2853         if (!type_valid && mask_valid) {
2854                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2855                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2856                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2857                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2858
2859                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2860                              (((eth_type == ETH_P_MPLS_UC) ||
2861                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2862         }
2863
2864         return type_valid;
2865 }
2866
2867 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2868                           const struct ib_flow_attr *flow_attr)
2869 {
2870         return is_valid_ethertype(mdev, flow_attr, false) &&
2871                is_valid_ethertype(mdev, flow_attr, true);
2872 }
2873
2874 static void put_flow_table(struct mlx5_ib_dev *dev,
2875                            struct mlx5_ib_flow_prio *prio, bool ft_added)
2876 {
2877         prio->refcount -= !!ft_added;
2878         if (!prio->refcount) {
2879                 mlx5_destroy_flow_table(prio->flow_table);
2880                 prio->flow_table = NULL;
2881         }
2882 }
2883
2884 static void counters_clear_description(struct ib_counters *counters)
2885 {
2886         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2887
2888         mutex_lock(&mcounters->mcntrs_mutex);
2889         kfree(mcounters->counters_data);
2890         mcounters->counters_data = NULL;
2891         mcounters->cntrs_max_index = 0;
2892         mutex_unlock(&mcounters->mcntrs_mutex);
2893 }
2894
2895 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2896 {
2897         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2898         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2899                                                           struct mlx5_ib_flow_handler,
2900                                                           ibflow);
2901         struct mlx5_ib_flow_handler *iter, *tmp;
2902
2903         mutex_lock(&dev->flow_db->lock);
2904
2905         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2906                 mlx5_del_flow_rules(iter->rule);
2907                 put_flow_table(dev, iter->prio, true);
2908                 list_del(&iter->list);
2909                 kfree(iter);
2910         }
2911
2912         mlx5_del_flow_rules(handler->rule);
2913         put_flow_table(dev, handler->prio, true);
2914         if (handler->ibcounters &&
2915             atomic_read(&handler->ibcounters->usecnt) == 1)
2916                 counters_clear_description(handler->ibcounters);
2917
2918         mutex_unlock(&dev->flow_db->lock);
2919         kfree(handler);
2920
2921         return 0;
2922 }
2923
2924 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2925 {
2926         priority *= 2;
2927         if (!dont_trap)
2928                 priority++;
2929         return priority;
2930 }
2931
2932 enum flow_table_type {
2933         MLX5_IB_FT_RX,
2934         MLX5_IB_FT_TX
2935 };
2936
2937 #define MLX5_FS_MAX_TYPES        6
2938 #define MLX5_FS_MAX_ENTRIES      BIT(16)
2939 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2940                                                 struct ib_flow_attr *flow_attr,
2941                                                 enum flow_table_type ft_type)
2942 {
2943         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2944         struct mlx5_flow_namespace *ns = NULL;
2945         struct mlx5_ib_flow_prio *prio;
2946         struct mlx5_flow_table *ft;
2947         int max_table_size;
2948         int num_entries;
2949         int num_groups;
2950         int priority;
2951         int err = 0;
2952
2953         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2954                                                        log_max_ft_size));
2955         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2956                 if (ft_type == MLX5_IB_FT_TX)
2957                         priority = 0;
2958                 else if (flow_is_multicast_only(flow_attr) &&
2959                          !dont_trap)
2960                         priority = MLX5_IB_FLOW_MCAST_PRIO;
2961                 else
2962                         priority = ib_prio_to_core_prio(flow_attr->priority,
2963                                                         dont_trap);
2964                 ns = mlx5_get_flow_namespace(dev->mdev,
2965                                              ft_type == MLX5_IB_FT_TX ?
2966                                              MLX5_FLOW_NAMESPACE_EGRESS :
2967                                              MLX5_FLOW_NAMESPACE_BYPASS);
2968                 num_entries = MLX5_FS_MAX_ENTRIES;
2969                 num_groups = MLX5_FS_MAX_TYPES;
2970                 prio = &dev->flow_db->prios[priority];
2971         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2972                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2973                 ns = mlx5_get_flow_namespace(dev->mdev,
2974                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
2975                 build_leftovers_ft_param(&priority,
2976                                          &num_entries,
2977                                          &num_groups);
2978                 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2979         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2980                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2981                                         allow_sniffer_and_nic_rx_shared_tir))
2982                         return ERR_PTR(-ENOTSUPP);
2983
2984                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2985                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2986                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2987
2988                 prio = &dev->flow_db->sniffer[ft_type];
2989                 priority = 0;
2990                 num_entries = 1;
2991                 num_groups = 1;
2992         }
2993
2994         if (!ns)
2995                 return ERR_PTR(-ENOTSUPP);
2996
2997         if (num_entries > max_table_size)
2998                 return ERR_PTR(-ENOMEM);
2999
3000         ft = prio->flow_table;
3001         if (!ft) {
3002                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3003                                                          num_entries,
3004                                                          num_groups,
3005                                                          0, 0);
3006
3007                 if (!IS_ERR(ft)) {
3008                         prio->refcount = 0;
3009                         prio->flow_table = ft;
3010                 } else {
3011                         err = PTR_ERR(ft);
3012                 }
3013         }
3014
3015         return err ? ERR_PTR(err) : prio;
3016 }
3017
3018 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3019                             struct mlx5_flow_spec *spec,
3020                             u32 underlay_qpn)
3021 {
3022         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3023                                            spec->match_criteria,
3024                                            misc_parameters);
3025         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3026                                            misc_parameters);
3027
3028         if (underlay_qpn &&
3029             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3030                                       ft_field_support.bth_dst_qp)) {
3031                 MLX5_SET(fte_match_set_misc,
3032                          misc_params_v, bth_dst_qp, underlay_qpn);
3033                 MLX5_SET(fte_match_set_misc,
3034                          misc_params_c, bth_dst_qp, 0xffffff);
3035         }
3036 }
3037
3038 static int counters_set_description(struct ib_counters *counters,
3039                                     enum mlx5_ib_counters_type counters_type,
3040                                     struct mlx5_ib_flow_counters_desc *desc_data,
3041                                     u32 ncounters)
3042 {
3043         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3044         u32 cntrs_max_index = 0;
3045         int i;
3046
3047         if (counters_type != MLX5_IB_COUNTERS_FLOW)
3048                 return -EINVAL;
3049
3050         /* init the fields for the object */
3051         mcounters->type = counters_type;
3052         mcounters->ncounters = ncounters;
3053         /* each counter entry have both description and index pair */
3054         for (i = 0; i < ncounters; i++) {
3055                 if (desc_data[i].description > IB_COUNTER_BYTES)
3056                         return -EINVAL;
3057
3058                 if (cntrs_max_index <= desc_data[i].index)
3059                         cntrs_max_index = desc_data[i].index + 1;
3060         }
3061
3062         mutex_lock(&mcounters->mcntrs_mutex);
3063         mcounters->counters_data = desc_data;
3064         mcounters->cntrs_max_index = cntrs_max_index;
3065         mutex_unlock(&mcounters->mcntrs_mutex);
3066
3067         return 0;
3068 }
3069
3070 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3071 static int flow_counters_set_data(struct ib_counters *ibcounters,
3072                                   struct mlx5_ib_create_flow *ucmd)
3073 {
3074         struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3075         struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3076         struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3077         bool hw_hndl = false;
3078         int ret = 0;
3079
3080         if (ucmd && ucmd->ncounters_data != 0) {
3081                 cntrs_data = ucmd->data;
3082                 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3083                         return -EINVAL;
3084
3085                 desc_data = kcalloc(cntrs_data->ncounters,
3086                                     sizeof(*desc_data),
3087                                     GFP_KERNEL);
3088                 if (!desc_data)
3089                         return  -ENOMEM;
3090
3091                 if (copy_from_user(desc_data,
3092                                    u64_to_user_ptr(cntrs_data->counters_data),
3093                                    sizeof(*desc_data) * cntrs_data->ncounters)) {
3094                         ret = -EFAULT;
3095                         goto free;
3096                 }
3097         }
3098
3099         if (!mcounters->hw_cntrs_hndl) {
3100                 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3101                         to_mdev(ibcounters->device)->mdev, false);
3102                 if (!mcounters->hw_cntrs_hndl) {
3103                         ret = -ENOMEM;
3104                         goto free;
3105                 }
3106                 hw_hndl = true;
3107         }
3108
3109         if (desc_data) {
3110                 /* counters already bound to at least one flow */
3111                 if (mcounters->cntrs_max_index) {
3112                         ret = -EINVAL;
3113                         goto free_hndl;
3114                 }
3115
3116                 ret = counters_set_description(ibcounters,
3117                                                MLX5_IB_COUNTERS_FLOW,
3118                                                desc_data,
3119                                                cntrs_data->ncounters);
3120                 if (ret)
3121                         goto free_hndl;
3122
3123         } else if (!mcounters->cntrs_max_index) {
3124                 /* counters not bound yet, must have udata passed */
3125                 ret = -EINVAL;
3126                 goto free_hndl;
3127         }
3128
3129         return 0;
3130
3131 free_hndl:
3132         if (hw_hndl) {
3133                 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3134                                 mcounters->hw_cntrs_hndl);
3135                 mcounters->hw_cntrs_hndl = NULL;
3136         }
3137 free:
3138         kfree(desc_data);
3139         return ret;
3140 }
3141
3142 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3143                                                       struct mlx5_ib_flow_prio *ft_prio,
3144                                                       const struct ib_flow_attr *flow_attr,
3145                                                       struct mlx5_flow_destination *dst,
3146                                                       u32 underlay_qpn,
3147                                                       struct mlx5_ib_create_flow *ucmd)
3148 {
3149         struct mlx5_flow_table  *ft = ft_prio->flow_table;
3150         struct mlx5_ib_flow_handler *handler;
3151         struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3152         struct mlx5_flow_spec *spec;
3153         struct mlx5_flow_destination dest_arr[2] = {};
3154         struct mlx5_flow_destination *rule_dst = dest_arr;
3155         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3156         unsigned int spec_index;
3157         int err = 0;
3158         int dest_num = 0;
3159         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3160
3161         if (!is_valid_attr(dev->mdev, flow_attr))
3162                 return ERR_PTR(-EINVAL);
3163
3164         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3165         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3166         if (!handler || !spec) {
3167                 err = -ENOMEM;
3168                 goto free;
3169         }
3170
3171         INIT_LIST_HEAD(&handler->list);
3172         if (dst) {
3173                 memcpy(&dest_arr[0], dst, sizeof(*dst));
3174                 dest_num++;
3175         }
3176
3177         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3178                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3179                                       spec->match_value,
3180                                       ib_flow, flow_attr, &flow_act);
3181                 if (err < 0)
3182                         goto free;
3183
3184                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3185         }
3186
3187         if (!flow_is_multicast_only(flow_attr))
3188                 set_underlay_qp(dev, spec, underlay_qpn);
3189
3190         if (dev->rep) {
3191                 void *misc;
3192
3193                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3194                                     misc_parameters);
3195                 MLX5_SET(fte_match_set_misc, misc, source_port,
3196                          dev->rep->vport);
3197                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3198                                     misc_parameters);
3199                 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3200         }
3201
3202         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3203
3204         if (is_egress &&
3205             !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3206                 err = -EINVAL;
3207                 goto free;
3208         }
3209
3210         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3211                 err = flow_counters_set_data(flow_act.counters, ucmd);
3212                 if (err)
3213                         goto free;
3214
3215                 handler->ibcounters = flow_act.counters;
3216                 dest_arr[dest_num].type =
3217                         MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3218                 dest_arr[dest_num].counter =
3219                         to_mcounters(flow_act.counters)->hw_cntrs_hndl;
3220                 dest_num++;
3221         }
3222
3223         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3224                 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3225                         rule_dst = NULL;
3226                         dest_num = 0;
3227                 }
3228         } else {
3229                 if (is_egress)
3230                         flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3231                 else
3232                         flow_act.action |=
3233                                 dest_num ?  MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3234                                         MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3235         }
3236
3237         if (flow_act.has_flow_tag &&
3238             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3239              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3240                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3241                              flow_act.flow_tag, flow_attr->type);
3242                 err = -EINVAL;
3243                 goto free;
3244         }
3245         handler->rule = mlx5_add_flow_rules(ft, spec,
3246                                             &flow_act,
3247                                             rule_dst, dest_num);
3248
3249         if (IS_ERR(handler->rule)) {
3250                 err = PTR_ERR(handler->rule);
3251                 goto free;
3252         }
3253
3254         ft_prio->refcount++;
3255         handler->prio = ft_prio;
3256
3257         ft_prio->flow_table = ft;
3258 free:
3259         if (err && handler) {
3260                 if (handler->ibcounters &&
3261                     atomic_read(&handler->ibcounters->usecnt) == 1)
3262                         counters_clear_description(handler->ibcounters);
3263                 kfree(handler);
3264         }
3265         kvfree(spec);
3266         return err ? ERR_PTR(err) : handler;
3267 }
3268
3269 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3270                                                      struct mlx5_ib_flow_prio *ft_prio,
3271                                                      const struct ib_flow_attr *flow_attr,
3272                                                      struct mlx5_flow_destination *dst)
3273 {
3274         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3275 }
3276
3277 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3278                                                           struct mlx5_ib_flow_prio *ft_prio,
3279                                                           struct ib_flow_attr *flow_attr,
3280                                                           struct mlx5_flow_destination *dst)
3281 {
3282         struct mlx5_ib_flow_handler *handler_dst = NULL;
3283         struct mlx5_ib_flow_handler *handler = NULL;
3284
3285         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3286         if (!IS_ERR(handler)) {
3287                 handler_dst = create_flow_rule(dev, ft_prio,
3288                                                flow_attr, dst);
3289                 if (IS_ERR(handler_dst)) {
3290                         mlx5_del_flow_rules(handler->rule);
3291                         ft_prio->refcount--;
3292                         kfree(handler);
3293                         handler = handler_dst;
3294                 } else {
3295                         list_add(&handler_dst->list, &handler->list);
3296                 }
3297         }
3298
3299         return handler;
3300 }
3301 enum {
3302         LEFTOVERS_MC,
3303         LEFTOVERS_UC,
3304 };
3305
3306 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3307                                                           struct mlx5_ib_flow_prio *ft_prio,
3308                                                           struct ib_flow_attr *flow_attr,
3309                                                           struct mlx5_flow_destination *dst)
3310 {
3311         struct mlx5_ib_flow_handler *handler_ucast = NULL;
3312         struct mlx5_ib_flow_handler *handler = NULL;
3313
3314         static struct {
3315                 struct ib_flow_attr     flow_attr;
3316                 struct ib_flow_spec_eth eth_flow;
3317         } leftovers_specs[] = {
3318                 [LEFTOVERS_MC] = {
3319                         .flow_attr = {
3320                                 .num_of_specs = 1,
3321                                 .size = sizeof(leftovers_specs[0])
3322                         },
3323                         .eth_flow = {
3324                                 .type = IB_FLOW_SPEC_ETH,
3325                                 .size = sizeof(struct ib_flow_spec_eth),
3326                                 .mask = {.dst_mac = {0x1} },
3327                                 .val =  {.dst_mac = {0x1} }
3328                         }
3329                 },
3330                 [LEFTOVERS_UC] = {
3331                         .flow_attr = {
3332                                 .num_of_specs = 1,
3333                                 .size = sizeof(leftovers_specs[0])
3334                         },
3335                         .eth_flow = {
3336                                 .type = IB_FLOW_SPEC_ETH,
3337                                 .size = sizeof(struct ib_flow_spec_eth),
3338                                 .mask = {.dst_mac = {0x1} },
3339                                 .val = {.dst_mac = {} }
3340                         }
3341                 }
3342         };
3343
3344         handler = create_flow_rule(dev, ft_prio,
3345                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
3346                                    dst);
3347         if (!IS_ERR(handler) &&
3348             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3349                 handler_ucast = create_flow_rule(dev, ft_prio,
3350                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
3351                                                  dst);
3352                 if (IS_ERR(handler_ucast)) {
3353                         mlx5_del_flow_rules(handler->rule);
3354                         ft_prio->refcount--;
3355                         kfree(handler);
3356                         handler = handler_ucast;
3357                 } else {
3358                         list_add(&handler_ucast->list, &handler->list);
3359                 }
3360         }
3361
3362         return handler;
3363 }
3364
3365 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3366                                                         struct mlx5_ib_flow_prio *ft_rx,
3367                                                         struct mlx5_ib_flow_prio *ft_tx,
3368                                                         struct mlx5_flow_destination *dst)
3369 {
3370         struct mlx5_ib_flow_handler *handler_rx;
3371         struct mlx5_ib_flow_handler *handler_tx;
3372         int err;
3373         static const struct ib_flow_attr flow_attr  = {
3374                 .num_of_specs = 0,
3375                 .size = sizeof(flow_attr)
3376         };
3377
3378         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3379         if (IS_ERR(handler_rx)) {
3380                 err = PTR_ERR(handler_rx);
3381                 goto err;
3382         }
3383
3384         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3385         if (IS_ERR(handler_tx)) {
3386                 err = PTR_ERR(handler_tx);
3387                 goto err_tx;
3388         }
3389
3390         list_add(&handler_tx->list, &handler_rx->list);
3391
3392         return handler_rx;
3393
3394 err_tx:
3395         mlx5_del_flow_rules(handler_rx->rule);
3396         ft_rx->refcount--;
3397         kfree(handler_rx);
3398 err:
3399         return ERR_PTR(err);
3400 }
3401
3402 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3403                                            struct ib_flow_attr *flow_attr,
3404                                            int domain,
3405                                            struct ib_udata *udata)
3406 {
3407         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3408         struct mlx5_ib_qp *mqp = to_mqp(qp);
3409         struct mlx5_ib_flow_handler *handler = NULL;
3410         struct mlx5_flow_destination *dst = NULL;
3411         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3412         struct mlx5_ib_flow_prio *ft_prio;
3413         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3414         struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3415         size_t min_ucmd_sz, required_ucmd_sz;
3416         int err;
3417         int underlay_qpn;
3418
3419         if (udata && udata->inlen) {
3420                 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3421                                 sizeof(ucmd_hdr.reserved);
3422                 if (udata->inlen < min_ucmd_sz)
3423                         return ERR_PTR(-EOPNOTSUPP);
3424
3425                 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3426                 if (err)
3427                         return ERR_PTR(err);
3428
3429                 /* currently supports only one counters data */
3430                 if (ucmd_hdr.ncounters_data > 1)
3431                         return ERR_PTR(-EINVAL);
3432
3433                 required_ucmd_sz = min_ucmd_sz +
3434                         sizeof(struct mlx5_ib_flow_counters_data) *
3435                         ucmd_hdr.ncounters_data;
3436                 if (udata->inlen > required_ucmd_sz &&
3437                     !ib_is_udata_cleared(udata, required_ucmd_sz,
3438                                          udata->inlen - required_ucmd_sz))
3439                         return ERR_PTR(-EOPNOTSUPP);
3440
3441                 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3442                 if (!ucmd)
3443                         return ERR_PTR(-ENOMEM);
3444
3445                 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3446                 if (err) {
3447                         kfree(ucmd);
3448                         return ERR_PTR(err);
3449                 }
3450         }
3451
3452         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
3453                 return ERR_PTR(-ENOMEM);
3454
3455         if (domain != IB_FLOW_DOMAIN_USER ||
3456             flow_attr->port > dev->num_ports ||
3457             (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3458                                   IB_FLOW_ATTR_FLAGS_EGRESS)))
3459                 return ERR_PTR(-EINVAL);
3460
3461         if (is_egress &&
3462             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3463              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT))
3464                 return ERR_PTR(-EINVAL);
3465
3466         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3467         if (!dst)
3468                 return ERR_PTR(-ENOMEM);
3469
3470         mutex_lock(&dev->flow_db->lock);
3471
3472         ft_prio = get_flow_table(dev, flow_attr,
3473                                  is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3474         if (IS_ERR(ft_prio)) {
3475                 err = PTR_ERR(ft_prio);
3476                 goto unlock;
3477         }
3478         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3479                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3480                 if (IS_ERR(ft_prio_tx)) {
3481                         err = PTR_ERR(ft_prio_tx);
3482                         ft_prio_tx = NULL;
3483                         goto destroy_ft;
3484                 }
3485         }
3486
3487         if (is_egress) {
3488                 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3489         } else {
3490                 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3491                 if (mqp->flags & MLX5_IB_QP_RSS)
3492                         dst->tir_num = mqp->rss_qp.tirn;
3493                 else
3494                         dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3495         }
3496
3497         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3498                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3499                         handler = create_dont_trap_rule(dev, ft_prio,
3500                                                         flow_attr, dst);
3501                 } else {
3502                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3503                                         mqp->underlay_qpn : 0;
3504                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3505                                                     dst, underlay_qpn, ucmd);
3506                 }
3507         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3508                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3509                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3510                                                 dst);
3511         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3512                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3513         } else {
3514                 err = -EINVAL;
3515                 goto destroy_ft;
3516         }
3517
3518         if (IS_ERR(handler)) {
3519                 err = PTR_ERR(handler);
3520                 handler = NULL;
3521                 goto destroy_ft;
3522         }
3523
3524         mutex_unlock(&dev->flow_db->lock);
3525         kfree(dst);
3526         kfree(ucmd);
3527
3528         return &handler->ibflow;
3529
3530 destroy_ft:
3531         put_flow_table(dev, ft_prio, false);
3532         if (ft_prio_tx)
3533                 put_flow_table(dev, ft_prio_tx, false);
3534 unlock:
3535         mutex_unlock(&dev->flow_db->lock);
3536         kfree(dst);
3537         kfree(ucmd);
3538         kfree(handler);
3539         return ERR_PTR(err);
3540 }
3541
3542 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3543 {
3544         u32 flags = 0;
3545
3546         if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3547                 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3548
3549         return flags;
3550 }
3551
3552 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED      MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3553 static struct ib_flow_action *
3554 mlx5_ib_create_flow_action_esp(struct ib_device *device,
3555                                const struct ib_flow_action_attrs_esp *attr,
3556                                struct uverbs_attr_bundle *attrs)
3557 {
3558         struct mlx5_ib_dev *mdev = to_mdev(device);
3559         struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3560         struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3561         struct mlx5_ib_flow_action *action;
3562         u64 action_flags;
3563         u64 flags;
3564         int err = 0;
3565
3566         if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs,
3567                                                 MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS)))
3568                 return ERR_PTR(-EFAULT);
3569
3570         if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1))
3571                 return ERR_PTR(-EOPNOTSUPP);
3572
3573         flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3574
3575         /* We current only support a subset of the standard features. Only a
3576          * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3577          * (with overlap). Full offload mode isn't supported.
3578          */
3579         if (!attr->keymat || attr->replay || attr->encap ||
3580             attr->spi || attr->seq || attr->tfc_pad ||
3581             attr->hard_limit_pkts ||
3582             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3583                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3584                 return ERR_PTR(-EOPNOTSUPP);
3585
3586         if (attr->keymat->protocol !=
3587             IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3588                 return ERR_PTR(-EOPNOTSUPP);
3589
3590         aes_gcm = &attr->keymat->keymat.aes_gcm;
3591
3592         if (aes_gcm->icv_len != 16 ||
3593             aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3594                 return ERR_PTR(-EOPNOTSUPP);
3595
3596         action = kmalloc(sizeof(*action), GFP_KERNEL);
3597         if (!action)
3598                 return ERR_PTR(-ENOMEM);
3599
3600         action->esp_aes_gcm.ib_flags = attr->flags;
3601         memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3602                sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3603         accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3604         memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3605                sizeof(accel_attrs.keymat.aes_gcm.salt));
3606         memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3607                sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3608         accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3609         accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3610         accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3611
3612         accel_attrs.esn = attr->esn;
3613         if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3614                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3615         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3616                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3617
3618         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3619                 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3620
3621         action->esp_aes_gcm.ctx =
3622                 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3623         if (IS_ERR(action->esp_aes_gcm.ctx)) {
3624                 err = PTR_ERR(action->esp_aes_gcm.ctx);
3625                 goto err_parse;
3626         }
3627
3628         action->esp_aes_gcm.ib_flags = attr->flags;
3629
3630         return &action->ib_action;
3631
3632 err_parse:
3633         kfree(action);
3634         return ERR_PTR(err);
3635 }
3636
3637 static int
3638 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3639                                const struct ib_flow_action_attrs_esp *attr,
3640                                struct uverbs_attr_bundle *attrs)
3641 {
3642         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3643         struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3644         int err = 0;
3645
3646         if (attr->keymat || attr->replay || attr->encap ||
3647             attr->spi || attr->seq || attr->tfc_pad ||
3648             attr->hard_limit_pkts ||
3649             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3650                              IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3651                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3652                 return -EOPNOTSUPP;
3653
3654         /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3655          * be modified.
3656          */
3657         if (!(maction->esp_aes_gcm.ib_flags &
3658               IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3659             attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3660                            IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3661                 return -EINVAL;
3662
3663         memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3664                sizeof(accel_attrs));
3665
3666         accel_attrs.esn = attr->esn;
3667         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3668                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3669         else
3670                 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3671
3672         err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3673                                          &accel_attrs);
3674         if (err)
3675                 return err;
3676
3677         maction->esp_aes_gcm.ib_flags &=
3678                 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3679         maction->esp_aes_gcm.ib_flags |=
3680                 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3681
3682         return 0;
3683 }
3684
3685 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3686 {
3687         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3688
3689         switch (action->type) {
3690         case IB_FLOW_ACTION_ESP:
3691                 /*
3692                  * We only support aes_gcm by now, so we implicitly know this is
3693                  * the underline crypto.
3694                  */
3695                 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
3696                 break;
3697         default:
3698                 WARN_ON(true);
3699                 break;
3700         }
3701
3702         kfree(maction);
3703         return 0;
3704 }
3705
3706 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3707 {
3708         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3709         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
3710         int err;
3711
3712         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3713                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3714                 return -EOPNOTSUPP;
3715         }
3716
3717         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
3718         if (err)
3719                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3720                              ibqp->qp_num, gid->raw);
3721
3722         return err;
3723 }
3724
3725 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3726 {
3727         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3728         int err;
3729
3730         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
3731         if (err)
3732                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3733                              ibqp->qp_num, gid->raw);
3734
3735         return err;
3736 }
3737
3738 static int init_node_data(struct mlx5_ib_dev *dev)
3739 {
3740         int err;
3741
3742         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
3743         if (err)
3744                 return err;
3745
3746         dev->mdev->rev_id = dev->mdev->pdev->revision;
3747
3748         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
3749 }
3750
3751 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3752                              char *buf)
3753 {
3754         struct mlx5_ib_dev *dev =
3755                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3756
3757         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
3758 }
3759
3760 static ssize_t show_reg_pages(struct device *device,
3761                               struct device_attribute *attr, char *buf)
3762 {
3763         struct mlx5_ib_dev *dev =
3764                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3765
3766         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
3767 }
3768
3769 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3770                         char *buf)
3771 {
3772         struct mlx5_ib_dev *dev =
3773                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3774         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
3775 }
3776
3777 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3778                         char *buf)
3779 {
3780         struct mlx5_ib_dev *dev =
3781                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3782         return sprintf(buf, "%x\n", dev->mdev->rev_id);
3783 }
3784
3785 static ssize_t show_board(struct device *device, struct device_attribute *attr,
3786                           char *buf)
3787 {
3788         struct mlx5_ib_dev *dev =
3789                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3790         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
3791                        dev->mdev->board_id);
3792 }
3793
3794 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
3795 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
3796 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
3797 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3798 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3799
3800 static struct device_attribute *mlx5_class_attributes[] = {
3801         &dev_attr_hw_rev,
3802         &dev_attr_hca_type,
3803         &dev_attr_board_id,
3804         &dev_attr_fw_pages,
3805         &dev_attr_reg_pages,
3806 };
3807
3808 static void pkey_change_handler(struct work_struct *work)
3809 {
3810         struct mlx5_ib_port_resources *ports =
3811                 container_of(work, struct mlx5_ib_port_resources,
3812                              pkey_change_work);
3813
3814         mutex_lock(&ports->devr->mutex);
3815         mlx5_ib_gsi_pkey_change(ports->gsi);
3816         mutex_unlock(&ports->devr->mutex);
3817 }
3818
3819 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3820 {
3821         struct mlx5_ib_qp *mqp;
3822         struct mlx5_ib_cq *send_mcq, *recv_mcq;
3823         struct mlx5_core_cq *mcq;
3824         struct list_head cq_armed_list;
3825         unsigned long flags_qp;
3826         unsigned long flags_cq;
3827         unsigned long flags;
3828
3829         INIT_LIST_HEAD(&cq_armed_list);
3830
3831         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3832         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3833         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3834                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3835                 if (mqp->sq.tail != mqp->sq.head) {
3836                         send_mcq = to_mcq(mqp->ibqp.send_cq);
3837                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
3838                         if (send_mcq->mcq.comp &&
3839                             mqp->ibqp.send_cq->comp_handler) {
3840                                 if (!send_mcq->mcq.reset_notify_added) {
3841                                         send_mcq->mcq.reset_notify_added = 1;
3842                                         list_add_tail(&send_mcq->mcq.reset_notify,
3843                                                       &cq_armed_list);
3844                                 }
3845                         }
3846                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3847                 }
3848                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3849                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3850                 /* no handling is needed for SRQ */
3851                 if (!mqp->ibqp.srq) {
3852                         if (mqp->rq.tail != mqp->rq.head) {
3853                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3854                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3855                                 if (recv_mcq->mcq.comp &&
3856                                     mqp->ibqp.recv_cq->comp_handler) {
3857                                         if (!recv_mcq->mcq.reset_notify_added) {
3858                                                 recv_mcq->mcq.reset_notify_added = 1;
3859                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
3860                                                               &cq_armed_list);
3861                                         }
3862                                 }
3863                                 spin_unlock_irqrestore(&recv_mcq->lock,
3864                                                        flags_cq);
3865                         }
3866                 }
3867                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3868         }
3869         /*At that point all inflight post send were put to be executed as of we
3870          * lock/unlock above locks Now need to arm all involved CQs.
3871          */
3872         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3873                 mcq->comp(mcq);
3874         }
3875         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3876 }
3877
3878 static void delay_drop_handler(struct work_struct *work)
3879 {
3880         int err;
3881         struct mlx5_ib_delay_drop *delay_drop =
3882                 container_of(work, struct mlx5_ib_delay_drop,
3883                              delay_drop_work);
3884
3885         atomic_inc(&delay_drop->events_cnt);
3886
3887         mutex_lock(&delay_drop->lock);
3888         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
3889                                        delay_drop->timeout);
3890         if (err) {
3891                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
3892                              delay_drop->timeout);
3893                 delay_drop->activate = false;
3894         }
3895         mutex_unlock(&delay_drop->lock);
3896 }
3897
3898 static void mlx5_ib_handle_event(struct work_struct *_work)
3899 {
3900         struct mlx5_ib_event_work *work =
3901                 container_of(_work, struct mlx5_ib_event_work, work);
3902         struct mlx5_ib_dev *ibdev;
3903         struct ib_event ibev;
3904         bool fatal = false;
3905         u8 port = (u8)work->param;
3906
3907         if (mlx5_core_is_mp_slave(work->dev)) {
3908                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
3909                 if (!ibdev)
3910                         goto out;
3911         } else {
3912                 ibdev = work->context;
3913         }
3914
3915         switch (work->event) {
3916         case MLX5_DEV_EVENT_SYS_ERROR:
3917                 ibev.event = IB_EVENT_DEVICE_FATAL;
3918                 mlx5_ib_handle_internal_error(ibdev);
3919                 fatal = true;
3920                 break;
3921
3922         case MLX5_DEV_EVENT_PORT_UP:
3923         case MLX5_DEV_EVENT_PORT_DOWN:
3924         case MLX5_DEV_EVENT_PORT_INITIALIZED:
3925                 /* In RoCE, port up/down events are handled in
3926                  * mlx5_netdev_event().
3927                  */
3928                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
3929                         IB_LINK_LAYER_ETHERNET)
3930                         goto out;
3931
3932                 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
3933                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3934                 break;
3935
3936         case MLX5_DEV_EVENT_LID_CHANGE:
3937                 ibev.event = IB_EVENT_LID_CHANGE;
3938                 break;
3939
3940         case MLX5_DEV_EVENT_PKEY_CHANGE:
3941                 ibev.event = IB_EVENT_PKEY_CHANGE;
3942                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
3943                 break;
3944
3945         case MLX5_DEV_EVENT_GUID_CHANGE:
3946                 ibev.event = IB_EVENT_GID_CHANGE;
3947                 break;
3948
3949         case MLX5_DEV_EVENT_CLIENT_REREG:
3950                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
3951                 break;
3952         case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
3953                 schedule_work(&ibdev->delay_drop.delay_drop_work);
3954                 goto out;
3955         default:
3956                 goto out;
3957         }
3958
3959         ibev.device           = &ibdev->ib_dev;
3960         ibev.element.port_num = port;
3961
3962         if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
3963                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
3964                 goto out;
3965         }
3966
3967         if (ibdev->ib_active)
3968                 ib_dispatch_event(&ibev);
3969
3970         if (fatal)
3971                 ibdev->ib_active = false;
3972 out:
3973         kfree(work);
3974 }
3975
3976 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
3977                           enum mlx5_dev_event event, unsigned long param)
3978 {
3979         struct mlx5_ib_event_work *work;
3980
3981         work = kmalloc(sizeof(*work), GFP_ATOMIC);
3982         if (!work)
3983                 return;
3984
3985         INIT_WORK(&work->work, mlx5_ib_handle_event);
3986         work->dev = dev;
3987         work->param = param;
3988         work->context = context;
3989         work->event = event;
3990
3991         queue_work(mlx5_ib_event_wq, &work->work);
3992 }
3993
3994 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
3995 {
3996         struct mlx5_hca_vport_context vport_ctx;
3997         int err;
3998         int port;
3999
4000         for (port = 1; port <= dev->num_ports; port++) {
4001                 dev->mdev->port_caps[port - 1].has_smi = false;
4002                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4003                     MLX5_CAP_PORT_TYPE_IB) {
4004                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4005                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4006                                                                    port, 0,
4007                                                                    &vport_ctx);
4008                                 if (err) {
4009                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4010                                                     port, err);
4011                                         return err;
4012                                 }
4013                                 dev->mdev->port_caps[port - 1].has_smi =
4014                                         vport_ctx.has_smi;
4015                         } else {
4016                                 dev->mdev->port_caps[port - 1].has_smi = true;
4017                         }
4018                 }
4019         }
4020         return 0;
4021 }
4022
4023 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4024 {
4025         int port;
4026
4027         for (port = 1; port <= dev->num_ports; port++)
4028                 mlx5_query_ext_port_caps(dev, port);
4029 }
4030
4031 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4032 {
4033         struct ib_device_attr *dprops = NULL;
4034         struct ib_port_attr *pprops = NULL;
4035         int err = -ENOMEM;
4036         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4037
4038         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4039         if (!pprops)
4040                 goto out;
4041
4042         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4043         if (!dprops)
4044                 goto out;
4045
4046         err = set_has_smi_cap(dev);
4047         if (err)
4048                 goto out;
4049
4050         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4051         if (err) {
4052                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4053                 goto out;
4054         }
4055
4056         memset(pprops, 0, sizeof(*pprops));
4057         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4058         if (err) {
4059                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4060                              port, err);
4061                 goto out;
4062         }
4063
4064         dev->mdev->port_caps[port - 1].pkey_table_len =
4065                                         dprops->max_pkeys;
4066         dev->mdev->port_caps[port - 1].gid_table_len =
4067                                         pprops->gid_tbl_len;
4068         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4069                     port, dprops->max_pkeys, pprops->gid_tbl_len);
4070
4071 out:
4072         kfree(pprops);
4073         kfree(dprops);
4074
4075         return err;
4076 }
4077
4078 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4079 {
4080         int err;
4081
4082         err = mlx5_mr_cache_cleanup(dev);
4083         if (err)
4084                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4085
4086         if (dev->umrc.qp)
4087                 mlx5_ib_destroy_qp(dev->umrc.qp);
4088         if (dev->umrc.cq)
4089                 ib_free_cq(dev->umrc.cq);
4090         if (dev->umrc.pd)
4091                 ib_dealloc_pd(dev->umrc.pd);
4092 }
4093
4094 enum {
4095         MAX_UMR_WR = 128,
4096 };
4097
4098 static int create_umr_res(struct mlx5_ib_dev *dev)
4099 {
4100         struct ib_qp_init_attr *init_attr = NULL;
4101         struct ib_qp_attr *attr = NULL;
4102         struct ib_pd *pd;
4103         struct ib_cq *cq;
4104         struct ib_qp *qp;
4105         int ret;
4106
4107         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4108         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4109         if (!attr || !init_attr) {
4110                 ret = -ENOMEM;
4111                 goto error_0;
4112         }
4113
4114         pd = ib_alloc_pd(&dev->ib_dev, 0);
4115         if (IS_ERR(pd)) {
4116                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4117                 ret = PTR_ERR(pd);
4118                 goto error_0;
4119         }
4120
4121         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4122         if (IS_ERR(cq)) {
4123                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4124                 ret = PTR_ERR(cq);
4125                 goto error_2;
4126         }
4127
4128         init_attr->send_cq = cq;
4129         init_attr->recv_cq = cq;
4130         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4131         init_attr->cap.max_send_wr = MAX_UMR_WR;
4132         init_attr->cap.max_send_sge = 1;
4133         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4134         init_attr->port_num = 1;
4135         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4136         if (IS_ERR(qp)) {
4137                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4138                 ret = PTR_ERR(qp);
4139                 goto error_3;
4140         }
4141         qp->device     = &dev->ib_dev;
4142         qp->real_qp    = qp;
4143         qp->uobject    = NULL;
4144         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4145         qp->send_cq    = init_attr->send_cq;
4146         qp->recv_cq    = init_attr->recv_cq;
4147
4148         attr->qp_state = IB_QPS_INIT;
4149         attr->port_num = 1;
4150         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4151                                 IB_QP_PORT, NULL);
4152         if (ret) {
4153                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4154                 goto error_4;
4155         }
4156
4157         memset(attr, 0, sizeof(*attr));
4158         attr->qp_state = IB_QPS_RTR;
4159         attr->path_mtu = IB_MTU_256;
4160
4161         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4162         if (ret) {
4163                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4164                 goto error_4;
4165         }
4166
4167         memset(attr, 0, sizeof(*attr));
4168         attr->qp_state = IB_QPS_RTS;
4169         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4170         if (ret) {
4171                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4172                 goto error_4;
4173         }
4174
4175         dev->umrc.qp = qp;
4176         dev->umrc.cq = cq;
4177         dev->umrc.pd = pd;
4178
4179         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4180         ret = mlx5_mr_cache_init(dev);
4181         if (ret) {
4182                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4183                 goto error_4;
4184         }
4185
4186         kfree(attr);
4187         kfree(init_attr);
4188
4189         return 0;
4190
4191 error_4:
4192         mlx5_ib_destroy_qp(qp);
4193         dev->umrc.qp = NULL;
4194
4195 error_3:
4196         ib_free_cq(cq);
4197         dev->umrc.cq = NULL;
4198
4199 error_2:
4200         ib_dealloc_pd(pd);
4201         dev->umrc.pd = NULL;
4202
4203 error_0:
4204         kfree(attr);
4205         kfree(init_attr);
4206         return ret;
4207 }
4208
4209 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4210 {
4211         switch (umr_fence_cap) {
4212         case MLX5_CAP_UMR_FENCE_NONE:
4213                 return MLX5_FENCE_MODE_NONE;
4214         case MLX5_CAP_UMR_FENCE_SMALL:
4215                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4216         default:
4217                 return MLX5_FENCE_MODE_STRONG_ORDERING;
4218         }
4219 }
4220
4221 static int create_dev_resources(struct mlx5_ib_resources *devr)
4222 {
4223         struct ib_srq_init_attr attr;
4224         struct mlx5_ib_dev *dev;
4225         struct ib_cq_init_attr cq_attr = {.cqe = 1};
4226         int port;
4227         int ret = 0;
4228
4229         dev = container_of(devr, struct mlx5_ib_dev, devr);
4230
4231         mutex_init(&devr->mutex);
4232
4233         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4234         if (IS_ERR(devr->p0)) {
4235                 ret = PTR_ERR(devr->p0);
4236                 goto error0;
4237         }
4238         devr->p0->device  = &dev->ib_dev;
4239         devr->p0->uobject = NULL;
4240         atomic_set(&devr->p0->usecnt, 0);
4241
4242         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
4243         if (IS_ERR(devr->c0)) {
4244                 ret = PTR_ERR(devr->c0);
4245                 goto error1;
4246         }
4247         devr->c0->device        = &dev->ib_dev;
4248         devr->c0->uobject       = NULL;
4249         devr->c0->comp_handler  = NULL;
4250         devr->c0->event_handler = NULL;
4251         devr->c0->cq_context    = NULL;
4252         atomic_set(&devr->c0->usecnt, 0);
4253
4254         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4255         if (IS_ERR(devr->x0)) {
4256                 ret = PTR_ERR(devr->x0);
4257                 goto error2;
4258         }
4259         devr->x0->device = &dev->ib_dev;
4260         devr->x0->inode = NULL;
4261         atomic_set(&devr->x0->usecnt, 0);
4262         mutex_init(&devr->x0->tgt_qp_mutex);
4263         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4264
4265         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4266         if (IS_ERR(devr->x1)) {
4267                 ret = PTR_ERR(devr->x1);
4268                 goto error3;
4269         }
4270         devr->x1->device = &dev->ib_dev;
4271         devr->x1->inode = NULL;
4272         atomic_set(&devr->x1->usecnt, 0);
4273         mutex_init(&devr->x1->tgt_qp_mutex);
4274         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4275
4276         memset(&attr, 0, sizeof(attr));
4277         attr.attr.max_sge = 1;
4278         attr.attr.max_wr = 1;
4279         attr.srq_type = IB_SRQT_XRC;
4280         attr.ext.cq = devr->c0;
4281         attr.ext.xrc.xrcd = devr->x0;
4282
4283         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4284         if (IS_ERR(devr->s0)) {
4285                 ret = PTR_ERR(devr->s0);
4286                 goto error4;
4287         }
4288         devr->s0->device        = &dev->ib_dev;
4289         devr->s0->pd            = devr->p0;
4290         devr->s0->uobject       = NULL;
4291         devr->s0->event_handler = NULL;
4292         devr->s0->srq_context   = NULL;
4293         devr->s0->srq_type      = IB_SRQT_XRC;
4294         devr->s0->ext.xrc.xrcd  = devr->x0;
4295         devr->s0->ext.cq        = devr->c0;
4296         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4297         atomic_inc(&devr->s0->ext.cq->usecnt);
4298         atomic_inc(&devr->p0->usecnt);
4299         atomic_set(&devr->s0->usecnt, 0);
4300
4301         memset(&attr, 0, sizeof(attr));
4302         attr.attr.max_sge = 1;
4303         attr.attr.max_wr = 1;
4304         attr.srq_type = IB_SRQT_BASIC;
4305         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4306         if (IS_ERR(devr->s1)) {
4307                 ret = PTR_ERR(devr->s1);
4308                 goto error5;
4309         }
4310         devr->s1->device        = &dev->ib_dev;
4311         devr->s1->pd            = devr->p0;
4312         devr->s1->uobject       = NULL;
4313         devr->s1->event_handler = NULL;
4314         devr->s1->srq_context   = NULL;
4315         devr->s1->srq_type      = IB_SRQT_BASIC;
4316         devr->s1->ext.cq        = devr->c0;
4317         atomic_inc(&devr->p0->usecnt);
4318         atomic_set(&devr->s1->usecnt, 0);
4319
4320         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4321                 INIT_WORK(&devr->ports[port].pkey_change_work,
4322                           pkey_change_handler);
4323                 devr->ports[port].devr = devr;
4324         }
4325
4326         return 0;
4327
4328 error5:
4329         mlx5_ib_destroy_srq(devr->s0);
4330 error4:
4331         mlx5_ib_dealloc_xrcd(devr->x1);
4332 error3:
4333         mlx5_ib_dealloc_xrcd(devr->x0);
4334 error2:
4335         mlx5_ib_destroy_cq(devr->c0);
4336 error1:
4337         mlx5_ib_dealloc_pd(devr->p0);
4338 error0:
4339         return ret;
4340 }
4341
4342 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4343 {
4344         struct mlx5_ib_dev *dev =
4345                 container_of(devr, struct mlx5_ib_dev, devr);
4346         int port;
4347
4348         mlx5_ib_destroy_srq(devr->s1);
4349         mlx5_ib_destroy_srq(devr->s0);
4350         mlx5_ib_dealloc_xrcd(devr->x0);
4351         mlx5_ib_dealloc_xrcd(devr->x1);
4352         mlx5_ib_destroy_cq(devr->c0);
4353         mlx5_ib_dealloc_pd(devr->p0);
4354
4355         /* Make sure no change P_Key work items are still executing */
4356         for (port = 0; port < dev->num_ports; ++port)
4357                 cancel_work_sync(&devr->ports[port].pkey_change_work);
4358 }
4359
4360 static u32 get_core_cap_flags(struct ib_device *ibdev)
4361 {
4362         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4363         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4364         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4365         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
4366         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
4367         u32 ret = 0;
4368
4369         if (ll == IB_LINK_LAYER_INFINIBAND)
4370                 return RDMA_CORE_PORT_IBA_IB;
4371
4372         if (raw_support)
4373                 ret = RDMA_CORE_PORT_RAW_PACKET;
4374
4375         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
4376                 return ret;
4377
4378         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
4379                 return ret;
4380
4381         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4382                 ret |= RDMA_CORE_PORT_IBA_ROCE;
4383
4384         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4385                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4386
4387         return ret;
4388 }
4389
4390 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4391                                struct ib_port_immutable *immutable)
4392 {
4393         struct ib_port_attr attr;
4394         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4395         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
4396         int err;
4397
4398         immutable->core_cap_flags = get_core_cap_flags(ibdev);
4399
4400         err = ib_query_port(ibdev, port_num, &attr);
4401         if (err)
4402                 return err;
4403
4404         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4405         immutable->gid_tbl_len = attr.gid_tbl_len;
4406         immutable->core_cap_flags = get_core_cap_flags(ibdev);
4407         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4408                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4409
4410         return 0;
4411 }
4412
4413 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4414                                    struct ib_port_immutable *immutable)
4415 {
4416         struct ib_port_attr attr;
4417         int err;
4418
4419         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4420
4421         err = ib_query_port(ibdev, port_num, &attr);
4422         if (err)
4423                 return err;
4424
4425         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4426         immutable->gid_tbl_len = attr.gid_tbl_len;
4427         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4428
4429         return 0;
4430 }
4431
4432 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
4433 {
4434         struct mlx5_ib_dev *dev =
4435                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
4436         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4437                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4438                  fw_rev_sub(dev->mdev));
4439 }
4440
4441 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
4442 {
4443         struct mlx5_core_dev *mdev = dev->mdev;
4444         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4445                                                                  MLX5_FLOW_NAMESPACE_LAG);
4446         struct mlx5_flow_table *ft;
4447         int err;
4448
4449         if (!ns || !mlx5_lag_is_active(mdev))
4450                 return 0;
4451
4452         err = mlx5_cmd_create_vport_lag(mdev);
4453         if (err)
4454                 return err;
4455
4456         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4457         if (IS_ERR(ft)) {
4458                 err = PTR_ERR(ft);
4459                 goto err_destroy_vport_lag;
4460         }
4461
4462         dev->flow_db->lag_demux_ft = ft;
4463         return 0;
4464
4465 err_destroy_vport_lag:
4466         mlx5_cmd_destroy_vport_lag(mdev);
4467         return err;
4468 }
4469
4470 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
4471 {
4472         struct mlx5_core_dev *mdev = dev->mdev;
4473
4474         if (dev->flow_db->lag_demux_ft) {
4475                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4476                 dev->flow_db->lag_demux_ft = NULL;
4477
4478                 mlx5_cmd_destroy_vport_lag(mdev);
4479         }
4480 }
4481
4482 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4483 {
4484         int err;
4485
4486         dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4487         err = register_netdevice_notifier(&dev->roce[port_num].nb);
4488         if (err) {
4489                 dev->roce[port_num].nb.notifier_call = NULL;
4490                 return err;
4491         }
4492
4493         return 0;
4494 }
4495
4496 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4497 {
4498         if (dev->roce[port_num].nb.notifier_call) {
4499                 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4500                 dev->roce[port_num].nb.notifier_call = NULL;
4501         }
4502 }
4503
4504 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
4505 {
4506         int err;
4507
4508         if (MLX5_CAP_GEN(dev->mdev, roce)) {
4509                 err = mlx5_nic_vport_enable_roce(dev->mdev);
4510                 if (err)
4511                         return err;
4512         }
4513
4514         err = mlx5_eth_lag_init(dev);
4515         if (err)
4516                 goto err_disable_roce;
4517
4518         return 0;
4519
4520 err_disable_roce:
4521         if (MLX5_CAP_GEN(dev->mdev, roce))
4522                 mlx5_nic_vport_disable_roce(dev->mdev);
4523
4524         return err;
4525 }
4526
4527 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
4528 {
4529         mlx5_eth_lag_cleanup(dev);
4530         if (MLX5_CAP_GEN(dev->mdev, roce))
4531                 mlx5_nic_vport_disable_roce(dev->mdev);
4532 }
4533
4534 struct mlx5_ib_counter {
4535         const char *name;
4536         size_t offset;
4537 };
4538
4539 #define INIT_Q_COUNTER(_name)           \
4540         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4541
4542 static const struct mlx5_ib_counter basic_q_cnts[] = {
4543         INIT_Q_COUNTER(rx_write_requests),
4544         INIT_Q_COUNTER(rx_read_requests),
4545         INIT_Q_COUNTER(rx_atomic_requests),
4546         INIT_Q_COUNTER(out_of_buffer),
4547 };
4548
4549 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
4550         INIT_Q_COUNTER(out_of_sequence),
4551 };
4552
4553 static const struct mlx5_ib_counter retrans_q_cnts[] = {
4554         INIT_Q_COUNTER(duplicate_request),
4555         INIT_Q_COUNTER(rnr_nak_retry_err),
4556         INIT_Q_COUNTER(packet_seq_err),
4557         INIT_Q_COUNTER(implied_nak_seq_err),
4558         INIT_Q_COUNTER(local_ack_timeout_err),
4559 };
4560
4561 #define INIT_CONG_COUNTER(_name)                \
4562         { .name = #_name, .offset =     \
4563                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4564
4565 static const struct mlx5_ib_counter cong_cnts[] = {
4566         INIT_CONG_COUNTER(rp_cnp_ignored),
4567         INIT_CONG_COUNTER(rp_cnp_handled),
4568         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4569         INIT_CONG_COUNTER(np_cnp_sent),
4570 };
4571
4572 static const struct mlx5_ib_counter extended_err_cnts[] = {
4573         INIT_Q_COUNTER(resp_local_length_error),
4574         INIT_Q_COUNTER(resp_cqe_error),
4575         INIT_Q_COUNTER(req_cqe_error),
4576         INIT_Q_COUNTER(req_remote_invalid_request),
4577         INIT_Q_COUNTER(req_remote_access_errors),
4578         INIT_Q_COUNTER(resp_remote_access_errors),
4579         INIT_Q_COUNTER(resp_cqe_flush_error),
4580         INIT_Q_COUNTER(req_cqe_flush_error),
4581 };
4582
4583 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
4584 {
4585         int i;
4586
4587         for (i = 0; i < dev->num_ports; i++) {
4588                 if (dev->port[i].cnts.set_id)
4589                         mlx5_core_dealloc_q_counter(dev->mdev,
4590                                                     dev->port[i].cnts.set_id);
4591                 kfree(dev->port[i].cnts.names);
4592                 kfree(dev->port[i].cnts.offsets);
4593         }
4594 }
4595
4596 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4597                                     struct mlx5_ib_counters *cnts)
4598 {
4599         u32 num_counters;
4600
4601         num_counters = ARRAY_SIZE(basic_q_cnts);
4602
4603         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4604                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4605
4606         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4607                 num_counters += ARRAY_SIZE(retrans_q_cnts);
4608
4609         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4610                 num_counters += ARRAY_SIZE(extended_err_cnts);
4611
4612         cnts->num_q_counters = num_counters;
4613
4614         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4615                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4616                 num_counters += ARRAY_SIZE(cong_cnts);
4617         }
4618
4619         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4620         if (!cnts->names)
4621                 return -ENOMEM;
4622
4623         cnts->offsets = kcalloc(num_counters,
4624                                 sizeof(cnts->offsets), GFP_KERNEL);
4625         if (!cnts->offsets)
4626                 goto err_names;
4627
4628         return 0;
4629
4630 err_names:
4631         kfree(cnts->names);
4632         cnts->names = NULL;
4633         return -ENOMEM;
4634 }
4635
4636 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4637                                   const char **names,
4638                                   size_t *offsets)
4639 {
4640         int i;
4641         int j = 0;
4642
4643         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4644                 names[j] = basic_q_cnts[i].name;
4645                 offsets[j] = basic_q_cnts[i].offset;
4646         }
4647
4648         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4649                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4650                         names[j] = out_of_seq_q_cnts[i].name;
4651                         offsets[j] = out_of_seq_q_cnts[i].offset;
4652                 }
4653         }
4654
4655         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4656                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4657                         names[j] = retrans_q_cnts[i].name;
4658                         offsets[j] = retrans_q_cnts[i].offset;
4659                 }
4660         }
4661
4662         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4663                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4664                         names[j] = extended_err_cnts[i].name;
4665                         offsets[j] = extended_err_cnts[i].offset;
4666                 }
4667         }
4668
4669         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4670                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4671                         names[j] = cong_cnts[i].name;
4672                         offsets[j] = cong_cnts[i].offset;
4673                 }
4674         }
4675 }
4676
4677 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
4678 {
4679         int err = 0;
4680         int i;
4681
4682         for (i = 0; i < dev->num_ports; i++) {
4683                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4684                 if (err)
4685                         goto err_alloc;
4686
4687                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4688                                       dev->port[i].cnts.offsets);
4689
4690                 err = mlx5_core_alloc_q_counter(dev->mdev,
4691                                                 &dev->port[i].cnts.set_id);
4692                 if (err) {
4693                         mlx5_ib_warn(dev,
4694                                      "couldn't allocate queue counter for port %d, err %d\n",
4695                                      i + 1, err);
4696                         goto err_alloc;
4697                 }
4698                 dev->port[i].cnts.set_id_valid = true;
4699         }
4700
4701         return 0;
4702
4703 err_alloc:
4704         mlx5_ib_dealloc_counters(dev);
4705         return err;
4706 }
4707
4708 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4709                                                     u8 port_num)
4710 {
4711         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4712         struct mlx5_ib_port *port = &dev->port[port_num - 1];
4713
4714         /* We support only per port stats */
4715         if (port_num == 0)
4716                 return NULL;
4717
4718         return rdma_alloc_hw_stats_struct(port->cnts.names,
4719                                           port->cnts.num_q_counters +
4720                                           port->cnts.num_cong_counters,
4721                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
4722 }
4723
4724 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
4725                                     struct mlx5_ib_port *port,
4726                                     struct rdma_hw_stats *stats)
4727 {
4728         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4729         void *out;
4730         __be32 val;
4731         int ret, i;
4732
4733         out = kvzalloc(outlen, GFP_KERNEL);
4734         if (!out)
4735                 return -ENOMEM;
4736
4737         ret = mlx5_core_query_q_counter(mdev,
4738                                         port->cnts.set_id, 0,
4739                                         out, outlen);
4740         if (ret)
4741                 goto free;
4742
4743         for (i = 0; i < port->cnts.num_q_counters; i++) {
4744                 val = *(__be32 *)(out + port->cnts.offsets[i]);
4745                 stats->value[i] = (u64)be32_to_cpu(val);
4746         }
4747
4748 free:
4749         kvfree(out);
4750         return ret;
4751 }
4752
4753 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4754                                 struct rdma_hw_stats *stats,
4755                                 u8 port_num, int index)
4756 {
4757         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4758         struct mlx5_ib_port *port = &dev->port[port_num - 1];
4759         struct mlx5_core_dev *mdev;
4760         int ret, num_counters;
4761         u8 mdev_port_num;
4762
4763         if (!stats)
4764                 return -EINVAL;
4765
4766         num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4767
4768         /* q_counters are per IB device, query the master mdev */
4769         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
4770         if (ret)
4771                 return ret;
4772
4773         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4774                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4775                                                     &mdev_port_num);
4776                 if (!mdev) {
4777                         /* If port is not affiliated yet, its in down state
4778                          * which doesn't have any counters yet, so it would be
4779                          * zero. So no need to read from the HCA.
4780                          */
4781                         goto done;
4782                 }
4783                 ret = mlx5_lag_query_cong_counters(dev->mdev,
4784                                                    stats->value +
4785                                                    port->cnts.num_q_counters,
4786                                                    port->cnts.num_cong_counters,
4787                                                    port->cnts.offsets +
4788                                                    port->cnts.num_q_counters);
4789
4790                 mlx5_ib_put_native_port_mdev(dev, port_num);
4791                 if (ret)
4792                         return ret;
4793         }
4794
4795 done:
4796         return num_counters;
4797 }
4798
4799 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4800 {
4801         return mlx5_rdma_netdev_free(netdev);
4802 }
4803
4804 static struct net_device*
4805 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4806                           u8 port_num,
4807                           enum rdma_netdev_t type,
4808                           const char *name,
4809                           unsigned char name_assign_type,
4810                           void (*setup)(struct net_device *))
4811 {
4812         struct net_device *netdev;
4813         struct rdma_netdev *rn;
4814
4815         if (type != RDMA_NETDEV_IPOIB)
4816                 return ERR_PTR(-EOPNOTSUPP);
4817
4818         netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4819                                         name, setup);
4820         if (likely(!IS_ERR_OR_NULL(netdev))) {
4821                 rn = netdev_priv(netdev);
4822                 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4823         }
4824         return netdev;
4825 }
4826
4827 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4828 {
4829         if (!dev->delay_drop.dbg)
4830                 return;
4831         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4832         kfree(dev->delay_drop.dbg);
4833         dev->delay_drop.dbg = NULL;
4834 }
4835
4836 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4837 {
4838         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4839                 return;
4840
4841         cancel_work_sync(&dev->delay_drop.delay_drop_work);
4842         delay_drop_debugfs_cleanup(dev);
4843 }
4844
4845 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4846                                        size_t count, loff_t *pos)
4847 {
4848         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4849         char lbuf[20];
4850         int len;
4851
4852         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4853         return simple_read_from_buffer(buf, count, pos, lbuf, len);
4854 }
4855
4856 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4857                                         size_t count, loff_t *pos)
4858 {
4859         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4860         u32 timeout;
4861         u32 var;
4862
4863         if (kstrtouint_from_user(buf, count, 0, &var))
4864                 return -EFAULT;
4865
4866         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4867                         1000);
4868         if (timeout != var)
4869                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4870                             timeout);
4871
4872         delay_drop->timeout = timeout;
4873
4874         return count;
4875 }
4876
4877 static const struct file_operations fops_delay_drop_timeout = {
4878         .owner  = THIS_MODULE,
4879         .open   = simple_open,
4880         .write  = delay_drop_timeout_write,
4881         .read   = delay_drop_timeout_read,
4882 };
4883
4884 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
4885 {
4886         struct mlx5_ib_dbg_delay_drop *dbg;
4887
4888         if (!mlx5_debugfs_root)
4889                 return 0;
4890
4891         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
4892         if (!dbg)
4893                 return -ENOMEM;
4894
4895         dev->delay_drop.dbg = dbg;
4896
4897         dbg->dir_debugfs =
4898                 debugfs_create_dir("delay_drop",
4899                                    dev->mdev->priv.dbg_root);
4900         if (!dbg->dir_debugfs)
4901                 goto out_debugfs;
4902
4903         dbg->events_cnt_debugfs =
4904                 debugfs_create_atomic_t("num_timeout_events", 0400,
4905                                         dbg->dir_debugfs,
4906                                         &dev->delay_drop.events_cnt);
4907         if (!dbg->events_cnt_debugfs)
4908                 goto out_debugfs;
4909
4910         dbg->rqs_cnt_debugfs =
4911                 debugfs_create_atomic_t("num_rqs", 0400,
4912                                         dbg->dir_debugfs,
4913                                         &dev->delay_drop.rqs_cnt);
4914         if (!dbg->rqs_cnt_debugfs)
4915                 goto out_debugfs;
4916
4917         dbg->timeout_debugfs =
4918                 debugfs_create_file("timeout", 0600,
4919                                     dbg->dir_debugfs,
4920                                     &dev->delay_drop,
4921                                     &fops_delay_drop_timeout);
4922         if (!dbg->timeout_debugfs)
4923                 goto out_debugfs;
4924
4925         return 0;
4926
4927 out_debugfs:
4928         delay_drop_debugfs_cleanup(dev);
4929         return -ENOMEM;
4930 }
4931
4932 static void init_delay_drop(struct mlx5_ib_dev *dev)
4933 {
4934         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4935                 return;
4936
4937         mutex_init(&dev->delay_drop.lock);
4938         dev->delay_drop.dev = dev;
4939         dev->delay_drop.activate = false;
4940         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4941         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4942         atomic_set(&dev->delay_drop.rqs_cnt, 0);
4943         atomic_set(&dev->delay_drop.events_cnt, 0);
4944
4945         if (delay_drop_debugfs_init(dev))
4946                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
4947 }
4948
4949 static const struct cpumask *
4950 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
4951 {
4952         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4953
4954         return mlx5_get_vector_affinity(dev->mdev, comp_vector);
4955 }
4956
4957 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4958 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
4959                                       struct mlx5_ib_multiport_info *mpi)
4960 {
4961         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
4962         struct mlx5_ib_port *port = &ibdev->port[port_num];
4963         int comps;
4964         int err;
4965         int i;
4966
4967         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
4968
4969         spin_lock(&port->mp.mpi_lock);
4970         if (!mpi->ibdev) {
4971                 spin_unlock(&port->mp.mpi_lock);
4972                 return;
4973         }
4974         mpi->ibdev = NULL;
4975
4976         spin_unlock(&port->mp.mpi_lock);
4977         mlx5_remove_netdev_notifier(ibdev, port_num);
4978         spin_lock(&port->mp.mpi_lock);
4979
4980         comps = mpi->mdev_refcnt;
4981         if (comps) {
4982                 mpi->unaffiliate = true;
4983                 init_completion(&mpi->unref_comp);
4984                 spin_unlock(&port->mp.mpi_lock);
4985
4986                 for (i = 0; i < comps; i++)
4987                         wait_for_completion(&mpi->unref_comp);
4988
4989                 spin_lock(&port->mp.mpi_lock);
4990                 mpi->unaffiliate = false;
4991         }
4992
4993         port->mp.mpi = NULL;
4994
4995         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4996
4997         spin_unlock(&port->mp.mpi_lock);
4998
4999         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5000
5001         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5002         /* Log an error, still needed to cleanup the pointers and add
5003          * it back to the list.
5004          */
5005         if (err)
5006                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5007                             port_num + 1);
5008
5009         ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5010 }
5011
5012 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5013 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5014                                     struct mlx5_ib_multiport_info *mpi)
5015 {
5016         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5017         int err;
5018
5019         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5020         if (ibdev->port[port_num].mp.mpi) {
5021                 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
5022                              port_num + 1);
5023                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5024                 return false;
5025         }
5026
5027         ibdev->port[port_num].mp.mpi = mpi;
5028         mpi->ibdev = ibdev;
5029         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5030
5031         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5032         if (err)
5033                 goto unbind;
5034
5035         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5036         if (err)
5037                 goto unbind;
5038
5039         err = mlx5_add_netdev_notifier(ibdev, port_num);
5040         if (err) {
5041                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5042                             port_num + 1);
5043                 goto unbind;
5044         }
5045
5046         err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5047         if (err)
5048                 goto unbind;
5049
5050         return true;
5051
5052 unbind:
5053         mlx5_ib_unbind_slave_port(ibdev, mpi);
5054         return false;
5055 }
5056
5057 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5058 {
5059         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5060         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5061                                                           port_num + 1);
5062         struct mlx5_ib_multiport_info *mpi;
5063         int err;
5064         int i;
5065
5066         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5067                 return 0;
5068
5069         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5070                                                      &dev->sys_image_guid);
5071         if (err)
5072                 return err;
5073
5074         err = mlx5_nic_vport_enable_roce(dev->mdev);
5075         if (err)
5076                 return err;
5077
5078         mutex_lock(&mlx5_ib_multiport_mutex);
5079         for (i = 0; i < dev->num_ports; i++) {
5080                 bool bound = false;
5081
5082                 /* build a stub multiport info struct for the native port. */
5083                 if (i == port_num) {
5084                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5085                         if (!mpi) {
5086                                 mutex_unlock(&mlx5_ib_multiport_mutex);
5087                                 mlx5_nic_vport_disable_roce(dev->mdev);
5088                                 return -ENOMEM;
5089                         }
5090
5091                         mpi->is_master = true;
5092                         mpi->mdev = dev->mdev;
5093                         mpi->sys_image_guid = dev->sys_image_guid;
5094                         dev->port[i].mp.mpi = mpi;
5095                         mpi->ibdev = dev;
5096                         mpi = NULL;
5097                         continue;
5098                 }
5099
5100                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5101                                     list) {
5102                         if (dev->sys_image_guid == mpi->sys_image_guid &&
5103                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5104                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
5105                         }
5106
5107                         if (bound) {
5108                                 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5109                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5110                                 list_del(&mpi->list);
5111                                 break;
5112                         }
5113                 }
5114                 if (!bound) {
5115                         get_port_caps(dev, i + 1);
5116                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
5117                                     i + 1);
5118                 }
5119         }
5120
5121         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5122         mutex_unlock(&mlx5_ib_multiport_mutex);
5123         return err;
5124 }
5125
5126 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5127 {
5128         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5129         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5130                                                           port_num + 1);
5131         int i;
5132
5133         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5134                 return;
5135
5136         mutex_lock(&mlx5_ib_multiport_mutex);
5137         for (i = 0; i < dev->num_ports; i++) {
5138                 if (dev->port[i].mp.mpi) {
5139                         /* Destroy the native port stub */
5140                         if (i == port_num) {
5141                                 kfree(dev->port[i].mp.mpi);
5142                                 dev->port[i].mp.mpi = NULL;
5143                         } else {
5144                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5145                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5146                         }
5147                 }
5148         }
5149
5150         mlx5_ib_dbg(dev, "removing from devlist\n");
5151         list_del(&dev->ib_dev_list);
5152         mutex_unlock(&mlx5_ib_multiport_mutex);
5153
5154         mlx5_nic_vport_disable_roce(dev->mdev);
5155 }
5156
5157 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_dm, UVERBS_OBJECT_DM,
5158                              UVERBS_METHOD_DM_ALLOC,
5159                              &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5160                                                   UVERBS_ATTR_TYPE(u64),
5161                                                   UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)),
5162                              &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5163                                                   UVERBS_ATTR_TYPE(u16),
5164                                                   UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
5165
5166 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION,
5167                              UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5168                              &UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5169                                                  UVERBS_ATTR_TYPE(u64),
5170                                                  UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
5171
5172 #define NUM_TREES       2
5173 static int populate_specs_root(struct mlx5_ib_dev *dev)
5174 {
5175         const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
5176                 uverbs_default_get_objects()};
5177         size_t num_trees = 1;
5178
5179         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
5180             !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5181                 default_root[num_trees++] = &mlx5_ib_flow_action;
5182
5183         if (MLX5_CAP_DEV_MEM(dev->mdev, memic) &&
5184             !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5185                 default_root[num_trees++] = &mlx5_ib_dm;
5186
5187         dev->ib_dev.specs_root =
5188                 uverbs_alloc_spec_tree(num_trees, default_root);
5189
5190         return PTR_ERR_OR_ZERO(dev->ib_dev.specs_root);
5191 }
5192
5193 static void depopulate_specs_root(struct mlx5_ib_dev *dev)
5194 {
5195         uverbs_free_spec_tree(dev->ib_dev.specs_root);
5196 }
5197
5198 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5199 {
5200         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5201
5202         counters_clear_description(counters);
5203         if (mcounters->hw_cntrs_hndl)
5204                 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5205                                 mcounters->hw_cntrs_hndl);
5206
5207         kfree(mcounters);
5208
5209         return 0;
5210 }
5211
5212 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5213                                                    struct uverbs_attr_bundle *attrs)
5214 {
5215         struct mlx5_ib_mcounters *mcounters;
5216
5217         mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5218         if (!mcounters)
5219                 return ERR_PTR(-ENOMEM);
5220
5221         mutex_init(&mcounters->mcntrs_mutex);
5222
5223         return &mcounters->ibcntrs;
5224 }
5225
5226 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5227 {
5228         mlx5_ib_cleanup_multiport_master(dev);
5229 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5230         cleanup_srcu_struct(&dev->mr_srcu);
5231 #endif
5232         kfree(dev->port);
5233 }
5234
5235 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
5236 {
5237         struct mlx5_core_dev *mdev = dev->mdev;
5238         const char *name;
5239         int err;
5240         int i;
5241
5242         dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
5243                             GFP_KERNEL);
5244         if (!dev->port)
5245                 return -ENOMEM;
5246
5247         for (i = 0; i < dev->num_ports; i++) {
5248                 spin_lock_init(&dev->port[i].mp.mpi_lock);
5249                 rwlock_init(&dev->roce[i].netdev_lock);
5250         }
5251
5252         err = mlx5_ib_init_multiport_master(dev);
5253         if (err)
5254                 goto err_free_port;
5255
5256         if (!mlx5_core_mp_enabled(mdev)) {
5257                 for (i = 1; i <= dev->num_ports; i++) {
5258                         err = get_port_caps(dev, i);
5259                         if (err)
5260                                 break;
5261                 }
5262         } else {
5263                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5264         }
5265         if (err)
5266                 goto err_mp;
5267
5268         if (mlx5_use_mad_ifc(dev))
5269                 get_ext_port_caps(dev);
5270
5271         if (!mlx5_lag_is_active(mdev))
5272                 name = "mlx5_%d";
5273         else
5274                 name = "mlx5_bond_%d";
5275
5276         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
5277         dev->ib_dev.owner               = THIS_MODULE;
5278         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
5279         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
5280         dev->ib_dev.phys_port_cnt       = dev->num_ports;
5281         dev->ib_dev.num_comp_vectors    =
5282                 dev->mdev->priv.eq_table.num_comp_vectors;
5283         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
5284
5285         mutex_init(&dev->cap_mask_mutex);
5286         INIT_LIST_HEAD(&dev->qp_list);
5287         spin_lock_init(&dev->reset_flow_resource_lock);
5288
5289         spin_lock_init(&dev->memic.memic_lock);
5290         dev->memic.dev = mdev;
5291
5292 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5293         err = init_srcu_struct(&dev->mr_srcu);
5294         if (err)
5295                 goto err_free_port;
5296 #endif
5297
5298         return 0;
5299 err_mp:
5300         mlx5_ib_cleanup_multiport_master(dev);
5301
5302 err_free_port:
5303         kfree(dev->port);
5304
5305         return -ENOMEM;
5306 }
5307
5308 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5309 {
5310         dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5311
5312         if (!dev->flow_db)
5313                 return -ENOMEM;
5314
5315         mutex_init(&dev->flow_db->lock);
5316
5317         return 0;
5318 }
5319
5320 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5321 {
5322         struct mlx5_ib_dev *nic_dev;
5323
5324         nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5325
5326         if (!nic_dev)
5327                 return -EINVAL;
5328
5329         dev->flow_db = nic_dev->flow_db;
5330
5331         return 0;
5332 }
5333
5334 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5335 {
5336         kfree(dev->flow_db);
5337 }
5338
5339 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
5340 {
5341         struct mlx5_core_dev *mdev = dev->mdev;
5342         int err;
5343
5344         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
5345         dev->ib_dev.uverbs_cmd_mask     =
5346                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
5347                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
5348                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
5349                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
5350                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
5351                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
5352                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
5353                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
5354                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
5355                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
5356                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5357                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
5358                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
5359                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
5360                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
5361                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
5362                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
5363                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
5364                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
5365                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
5366                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
5367                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
5368                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
5369                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
5370                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
5371                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
5372         dev->ib_dev.uverbs_ex_cmd_mask =
5373                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
5374                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
5375                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
5376                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
5377                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
5378
5379         dev->ib_dev.query_device        = mlx5_ib_query_device;
5380         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
5381         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
5382         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
5383         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
5384         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
5385         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
5386         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
5387         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
5388         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
5389         dev->ib_dev.mmap                = mlx5_ib_mmap;
5390         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
5391         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
5392         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
5393         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
5394         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
5395         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
5396         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
5397         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
5398         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
5399         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
5400         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
5401         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
5402         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
5403         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
5404         dev->ib_dev.post_send           = mlx5_ib_post_send;
5405         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
5406         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
5407         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
5408         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
5409         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
5410         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
5411         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
5412         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
5413         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
5414         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
5415         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
5416         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
5417         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
5418         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
5419         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
5420         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
5421         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
5422         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
5423         dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
5424         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
5425                 dev->ib_dev.alloc_rdma_netdev   = mlx5_ib_alloc_rdma_netdev;
5426
5427         if (mlx5_core_is_pf(mdev)) {
5428                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
5429                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
5430                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
5431                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
5432         }
5433
5434         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5435
5436         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5437
5438         if (MLX5_CAP_GEN(mdev, imaicl)) {
5439                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
5440                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
5441                 dev->ib_dev.uverbs_cmd_mask |=
5442                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
5443                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5444         }
5445
5446         if (MLX5_CAP_GEN(mdev, xrc)) {
5447                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5448                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5449                 dev->ib_dev.uverbs_cmd_mask |=
5450                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5451                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5452         }
5453
5454         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5455                 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5456                 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
5457                 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
5458         }
5459
5460         dev->ib_dev.create_flow = mlx5_ib_create_flow;
5461         dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5462         dev->ib_dev.uverbs_ex_cmd_mask |=
5463                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5464                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5465         dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5466         dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
5467         dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
5468         dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
5469         dev->ib_dev.create_counters = mlx5_ib_create_counters;
5470         dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
5471
5472         err = init_node_data(dev);
5473         if (err)
5474                 return err;
5475
5476         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
5477             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5478              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
5479                 mutex_init(&dev->lb_mutex);
5480
5481         return 0;
5482 }
5483
5484 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5485 {
5486         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
5487         dev->ib_dev.query_port          = mlx5_ib_query_port;
5488
5489         return 0;
5490 }
5491
5492 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
5493 {
5494         dev->ib_dev.get_port_immutable  = mlx5_port_rep_immutable;
5495         dev->ib_dev.query_port          = mlx5_ib_rep_query_port;
5496
5497         return 0;
5498 }
5499
5500 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev,
5501                                           u8 port_num)
5502 {
5503         int i;
5504
5505         for (i = 0; i < dev->num_ports; i++) {
5506                 dev->roce[i].dev = dev;
5507                 dev->roce[i].native_port_num = i + 1;
5508                 dev->roce[i].last_port_state = IB_PORT_DOWN;
5509         }
5510
5511         dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
5512         dev->ib_dev.create_wq    = mlx5_ib_create_wq;
5513         dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
5514         dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
5515         dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5516         dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5517
5518         dev->ib_dev.uverbs_ex_cmd_mask |=
5519                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5520                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5521                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5522                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5523                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5524
5525         return mlx5_add_netdev_notifier(dev, port_num);
5526 }
5527
5528 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5529 {
5530         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5531
5532         mlx5_remove_netdev_notifier(dev, port_num);
5533 }
5534
5535 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5536 {
5537         struct mlx5_core_dev *mdev = dev->mdev;
5538         enum rdma_link_layer ll;
5539         int port_type_cap;
5540         int err = 0;
5541         u8 port_num;
5542
5543         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5544         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5545         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5546
5547         if (ll == IB_LINK_LAYER_ETHERNET)
5548                 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5549
5550         return err;
5551 }
5552
5553 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5554 {
5555         mlx5_ib_stage_common_roce_cleanup(dev);
5556 }
5557
5558 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5559 {
5560         struct mlx5_core_dev *mdev = dev->mdev;
5561         enum rdma_link_layer ll;
5562         int port_type_cap;
5563         u8 port_num;
5564         int err;
5565
5566         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5567         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5568         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5569
5570         if (ll == IB_LINK_LAYER_ETHERNET) {
5571                 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5572                 if (err)
5573                         return err;
5574
5575                 err = mlx5_enable_eth(dev, port_num);
5576                 if (err)
5577                         goto cleanup;
5578         }
5579
5580         return 0;
5581 cleanup:
5582         mlx5_ib_stage_common_roce_cleanup(dev);
5583
5584         return err;
5585 }
5586
5587 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5588 {
5589         struct mlx5_core_dev *mdev = dev->mdev;
5590         enum rdma_link_layer ll;
5591         int port_type_cap;
5592         u8 port_num;
5593
5594         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5595         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5596         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5597
5598         if (ll == IB_LINK_LAYER_ETHERNET) {
5599                 mlx5_disable_eth(dev);
5600                 mlx5_ib_stage_common_roce_cleanup(dev);
5601         }
5602 }
5603
5604 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
5605 {
5606         return create_dev_resources(&dev->devr);
5607 }
5608
5609 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
5610 {
5611         destroy_dev_resources(&dev->devr);
5612 }
5613
5614 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
5615 {
5616         mlx5_ib_internal_fill_odp_caps(dev);
5617
5618         return mlx5_ib_odp_init_one(dev);
5619 }
5620
5621 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
5622 {
5623         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
5624                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
5625                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
5626
5627                 return mlx5_ib_alloc_counters(dev);
5628         }
5629
5630         return 0;
5631 }
5632
5633 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
5634 {
5635         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
5636                 mlx5_ib_dealloc_counters(dev);
5637 }
5638
5639 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
5640 {
5641         return mlx5_ib_init_cong_debugfs(dev,
5642                                          mlx5_core_native_port_num(dev->mdev) - 1);
5643 }
5644
5645 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
5646 {
5647         mlx5_ib_cleanup_cong_debugfs(dev,
5648                                      mlx5_core_native_port_num(dev->mdev) - 1);
5649 }
5650
5651 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
5652 {
5653         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
5654         if (!dev->mdev->priv.uar)
5655                 return -ENOMEM;
5656         return 0;
5657 }
5658
5659 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
5660 {
5661         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
5662 }
5663
5664 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
5665 {
5666         int err;
5667
5668         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
5669         if (err)
5670                 return err;
5671
5672         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
5673         if (err)
5674                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5675
5676         return err;
5677 }
5678
5679 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
5680 {
5681         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5682         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
5683 }
5684
5685 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
5686 {
5687         return populate_specs_root(dev);
5688 }
5689
5690 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
5691 {
5692         return ib_register_device(&dev->ib_dev, NULL);
5693 }
5694
5695 static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev)
5696 {
5697         depopulate_specs_root(dev);
5698 }
5699
5700 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
5701 {
5702         destroy_umrc_res(dev);
5703 }
5704
5705 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
5706 {
5707         ib_unregister_device(&dev->ib_dev);
5708 }
5709
5710 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
5711 {
5712         return create_umr_res(dev);
5713 }
5714
5715 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
5716 {
5717         init_delay_drop(dev);
5718
5719         return 0;
5720 }
5721
5722 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
5723 {
5724         cancel_delay_drop(dev);
5725 }
5726
5727 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
5728 {
5729         int err;
5730         int i;
5731
5732         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
5733                 err = device_create_file(&dev->ib_dev.dev,
5734                                          mlx5_class_attributes[i]);
5735                 if (err)
5736                         return err;
5737         }
5738
5739         return 0;
5740 }
5741
5742 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
5743 {
5744         mlx5_ib_register_vport_reps(dev);
5745
5746         return 0;
5747 }
5748
5749 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
5750 {
5751         mlx5_ib_unregister_vport_reps(dev);
5752 }
5753
5754 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
5755                       const struct mlx5_ib_profile *profile,
5756                       int stage)
5757 {
5758         /* Number of stages to cleanup */
5759         while (stage) {
5760                 stage--;
5761                 if (profile->stage[stage].cleanup)
5762                         profile->stage[stage].cleanup(dev);
5763         }
5764
5765         ib_dealloc_device((struct ib_device *)dev);
5766 }
5767
5768 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
5769
5770 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
5771                     const struct mlx5_ib_profile *profile)
5772 {
5773         int err;
5774         int i;
5775
5776         printk_once(KERN_INFO "%s", mlx5_version);
5777
5778         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
5779                 if (profile->stage[i].init) {
5780                         err = profile->stage[i].init(dev);
5781                         if (err)
5782                                 goto err_out;
5783                 }
5784         }
5785
5786         dev->profile = profile;
5787         dev->ib_active = true;
5788
5789         return dev;
5790
5791 err_out:
5792         __mlx5_ib_remove(dev, profile, i);
5793
5794         return NULL;
5795 }
5796
5797 static const struct mlx5_ib_profile pf_profile = {
5798         STAGE_CREATE(MLX5_IB_STAGE_INIT,
5799                      mlx5_ib_stage_init_init,
5800                      mlx5_ib_stage_init_cleanup),
5801         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5802                      mlx5_ib_stage_flow_db_init,
5803                      mlx5_ib_stage_flow_db_cleanup),
5804         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5805                      mlx5_ib_stage_caps_init,
5806                      NULL),
5807         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5808                      mlx5_ib_stage_non_default_cb,
5809                      NULL),
5810         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5811                      mlx5_ib_stage_roce_init,
5812                      mlx5_ib_stage_roce_cleanup),
5813         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5814                      mlx5_ib_stage_dev_res_init,
5815                      mlx5_ib_stage_dev_res_cleanup),
5816         STAGE_CREATE(MLX5_IB_STAGE_ODP,
5817                      mlx5_ib_stage_odp_init,
5818                      NULL),
5819         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5820                      mlx5_ib_stage_counters_init,
5821                      mlx5_ib_stage_counters_cleanup),
5822         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
5823                      mlx5_ib_stage_cong_debugfs_init,
5824                      mlx5_ib_stage_cong_debugfs_cleanup),
5825         STAGE_CREATE(MLX5_IB_STAGE_UAR,
5826                      mlx5_ib_stage_uar_init,
5827                      mlx5_ib_stage_uar_cleanup),
5828         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5829                      mlx5_ib_stage_bfrag_init,
5830                      mlx5_ib_stage_bfrag_cleanup),
5831         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5832                      NULL,
5833                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
5834         STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5835                      mlx5_ib_stage_populate_specs,
5836                      mlx5_ib_stage_depopulate_specs),
5837         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5838                      mlx5_ib_stage_ib_reg_init,
5839                      mlx5_ib_stage_ib_reg_cleanup),
5840         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5841                      mlx5_ib_stage_post_ib_reg_umr_init,
5842                      NULL),
5843         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
5844                      mlx5_ib_stage_delay_drop_init,
5845                      mlx5_ib_stage_delay_drop_cleanup),
5846         STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5847                      mlx5_ib_stage_class_attr_init,
5848                      NULL),
5849 };
5850
5851 static const struct mlx5_ib_profile nic_rep_profile = {
5852         STAGE_CREATE(MLX5_IB_STAGE_INIT,
5853                      mlx5_ib_stage_init_init,
5854                      mlx5_ib_stage_init_cleanup),
5855         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5856                      mlx5_ib_stage_flow_db_init,
5857                      mlx5_ib_stage_flow_db_cleanup),
5858         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5859                      mlx5_ib_stage_caps_init,
5860                      NULL),
5861         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5862                      mlx5_ib_stage_rep_non_default_cb,
5863                      NULL),
5864         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5865                      mlx5_ib_stage_rep_roce_init,
5866                      mlx5_ib_stage_rep_roce_cleanup),
5867         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5868                      mlx5_ib_stage_dev_res_init,
5869                      mlx5_ib_stage_dev_res_cleanup),
5870         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5871                      mlx5_ib_stage_counters_init,
5872                      mlx5_ib_stage_counters_cleanup),
5873         STAGE_CREATE(MLX5_IB_STAGE_UAR,
5874                      mlx5_ib_stage_uar_init,
5875                      mlx5_ib_stage_uar_cleanup),
5876         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5877                      mlx5_ib_stage_bfrag_init,
5878                      mlx5_ib_stage_bfrag_cleanup),
5879         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5880                      NULL,
5881                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
5882         STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5883                      mlx5_ib_stage_populate_specs,
5884                      mlx5_ib_stage_depopulate_specs),
5885         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5886                      mlx5_ib_stage_ib_reg_init,
5887                      mlx5_ib_stage_ib_reg_cleanup),
5888         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
5889                      mlx5_ib_stage_post_ib_reg_umr_init,
5890                      NULL),
5891         STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
5892                      mlx5_ib_stage_class_attr_init,
5893                      NULL),
5894         STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
5895                      mlx5_ib_stage_rep_reg_init,
5896                      mlx5_ib_stage_rep_reg_cleanup),
5897 };
5898
5899 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
5900 {
5901         struct mlx5_ib_multiport_info *mpi;
5902         struct mlx5_ib_dev *dev;
5903         bool bound = false;
5904         int err;
5905
5906         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5907         if (!mpi)
5908                 return NULL;
5909
5910         mpi->mdev = mdev;
5911
5912         err = mlx5_query_nic_vport_system_image_guid(mdev,
5913                                                      &mpi->sys_image_guid);
5914         if (err) {
5915                 kfree(mpi);
5916                 return NULL;
5917         }
5918
5919         mutex_lock(&mlx5_ib_multiport_mutex);
5920         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
5921                 if (dev->sys_image_guid == mpi->sys_image_guid)
5922                         bound = mlx5_ib_bind_slave_port(dev, mpi);
5923
5924                 if (bound) {
5925                         rdma_roce_rescan_device(&dev->ib_dev);
5926                         break;
5927                 }
5928         }
5929
5930         if (!bound) {
5931                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5932                 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5933         } else {
5934                 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
5935         }
5936         mutex_unlock(&mlx5_ib_multiport_mutex);
5937
5938         return mpi;
5939 }
5940
5941 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
5942 {
5943         enum rdma_link_layer ll;
5944         struct mlx5_ib_dev *dev;
5945         int port_type_cap;
5946
5947         printk_once(KERN_INFO "%s", mlx5_version);
5948
5949         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5950         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5951
5952         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
5953                 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
5954
5955                 return mlx5_ib_add_slave_port(mdev, port_num);
5956         }
5957
5958         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
5959         if (!dev)
5960                 return NULL;
5961
5962         dev->mdev = mdev;
5963         dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
5964                              MLX5_CAP_GEN(mdev, num_vhca_ports));
5965
5966         if (MLX5_VPORT_MANAGER(mdev) &&
5967             mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5968                 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
5969
5970                 return __mlx5_ib_add(dev, &nic_rep_profile);
5971         }
5972
5973         return __mlx5_ib_add(dev, &pf_profile);
5974 }
5975
5976 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
5977 {
5978         struct mlx5_ib_multiport_info *mpi;
5979         struct mlx5_ib_dev *dev;
5980
5981         if (mlx5_core_is_mp_slave(mdev)) {
5982                 mpi = context;
5983                 mutex_lock(&mlx5_ib_multiport_mutex);
5984                 if (mpi->ibdev)
5985                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
5986                 list_del(&mpi->list);
5987                 mutex_unlock(&mlx5_ib_multiport_mutex);
5988                 return;
5989         }
5990
5991         dev = context;
5992         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
5993 }
5994
5995 static struct mlx5_interface mlx5_ib_interface = {
5996         .add            = mlx5_ib_add,
5997         .remove         = mlx5_ib_remove,
5998         .event          = mlx5_ib_event,
5999 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6000         .pfault         = mlx5_ib_pfault,
6001 #endif
6002         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
6003 };
6004
6005 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6006 {
6007         mutex_lock(&xlt_emergency_page_mutex);
6008         return xlt_emergency_page;
6009 }
6010
6011 void mlx5_ib_put_xlt_emergency_page(void)
6012 {
6013         mutex_unlock(&xlt_emergency_page_mutex);
6014 }
6015
6016 static int __init mlx5_ib_init(void)
6017 {
6018         int err;
6019
6020         xlt_emergency_page = __get_free_page(GFP_KERNEL);
6021         if (!xlt_emergency_page)
6022                 return -ENOMEM;
6023
6024         mutex_init(&xlt_emergency_page_mutex);
6025
6026         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6027         if (!mlx5_ib_event_wq) {
6028                 free_page(xlt_emergency_page);
6029                 return -ENOMEM;
6030         }
6031
6032         mlx5_ib_odp_init();
6033
6034         err = mlx5_register_interface(&mlx5_ib_interface);
6035
6036         return err;
6037 }
6038
6039 static void __exit mlx5_ib_cleanup(void)
6040 {
6041         mlx5_unregister_interface(&mlx5_ib_interface);
6042         destroy_workqueue(mlx5_ib_event_wq);
6043         mutex_destroy(&xlt_emergency_page_mutex);
6044         free_page(xlt_emergency_page);
6045 }
6046
6047 module_init(mlx5_ib_init);
6048 module_exit(mlx5_ib_cleanup);