drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <linux/bitmap.h>
  42 #if defined(CONFIG_X86)
  43 #include <asm/pat.h>
  44 #endif
  45 #include <linux/sched.h>
  46 #include <linux/sched/mm.h>
  47 #include <linux/sched/task.h>
  48 #include <linux/delay.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <rdma/ib_addr.h>
  51 #include <rdma/ib_cache.h>
  52 #include <linux/mlx5/port.h>
  53 #include <linux/mlx5/vport.h>
  54 #include <linux/mlx5/fs.h>
  55 #include <linux/list.h>
  56 #include <rdma/ib_smi.h>
  57 #include <rdma/ib_umem.h>
  58 #include <linux/in.h>
  59 #include <linux/etherdevice.h>
  60 #include "mlx5_ib.h"
  61 #include "ib_rep.h"
  62 #include "cmd.h"
  63 #include <linux/mlx5/fs_helpers.h>
  64 #include <linux/mlx5/accel.h>
  65 #include <rdma/uverbs_std_types.h>
  66 #include <rdma/mlx5_user_ioctl_verbs.h>
  67 #include <rdma/mlx5_user_ioctl_cmds.h>
  68
  69 #define UVERBS_MODULE_NAME mlx5_ib
  70 #include <rdma/uverbs_named_ioctl.h>
  71
  72 #define DRIVER_NAME "mlx5_ib"
  73 #define DRIVER_VERSION "5.0-0"
  74
  75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  77 MODULE_LICENSE("Dual BSD/GPL");
  78
  79 static char mlx5_version[] =
  80         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  81         DRIVER_VERSION "\n";
  82
  83 struct mlx5_ib_event_work {
  84         struct work_struct      work;
  85         struct mlx5_core_dev    *dev;
  86         void                    *context;
  87         enum mlx5_dev_event     event;
  88         unsigned long           param;
  89 };
  90
  91 enum {
  92         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  93 };
  94
  95 static struct workqueue_struct *mlx5_ib_event_wq;
  96 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
  97 static LIST_HEAD(mlx5_ib_dev_list);
  98 /*
  99  * This mutex should be held when accessing either of the above lists
 100  */
 101 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
 102
 103 /* We can't use an array for xlt_emergency_page because dma_map_single
 104  * doesn't work on kernel modules memory
 105  */
 106 static unsigned long xlt_emergency_page;
 107 static struct mutex xlt_emergency_page_mutex;
 108
 109 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
 110 {
 111         struct mlx5_ib_dev *dev;
 112
 113         mutex_lock(&mlx5_ib_multiport_mutex);
 114         dev = mpi->ibdev;
 115         mutex_unlock(&mlx5_ib_multiport_mutex);
 116         return dev;
 117 }
 118
 119 static enum rdma_link_layer
 120 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 121 {
 122         switch (port_type_cap) {
 123         case MLX5_CAP_PORT_TYPE_IB:
 124                 return IB_LINK_LAYER_INFINIBAND;
 125         case MLX5_CAP_PORT_TYPE_ETH:
 126                 return IB_LINK_LAYER_ETHERNET;
 127         default:
 128                 return IB_LINK_LAYER_UNSPECIFIED;
 129         }
 130 }
 131
 132 static enum rdma_link_layer
 133 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 134 {
 135         struct mlx5_ib_dev *dev = to_mdev(device);
 136         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 137
 138         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 139 }
 140
 141 static int get_port_state(struct ib_device *ibdev,
 142                           u8 port_num,
 143                           enum ib_port_state *state)
 144 {
 145         struct ib_port_attr attr;
 146         int ret;
 147
 148         memset(&attr, 0, sizeof(attr));
 149         ret = ibdev->query_port(ibdev, port_num, &attr);
 150         if (!ret)
 151                 *state = attr.state;
 152         return ret;
 153 }
 154
 155 static int mlx5_netdev_event(struct notifier_block *this,
 156                              unsigned long event, void *ptr)
 157 {
 158         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 159         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 160         u8 port_num = roce->native_port_num;
 161         struct mlx5_core_dev *mdev;
 162         struct mlx5_ib_dev *ibdev;
 163
 164         ibdev = roce->dev;
 165         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 166         if (!mdev)
 167                 return NOTIFY_DONE;
 168
 169         switch (event) {
 170         case NETDEV_REGISTER:
 171         case NETDEV_UNREGISTER:
 172                 write_lock(&roce->netdev_lock);
 173                 if (ibdev->rep) {
 174                         struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
 175                         struct net_device *rep_ndev;
 176
 177                         rep_ndev = mlx5_ib_get_rep_netdev(esw,
 178                                                           ibdev->rep->vport);
 179                         if (rep_ndev == ndev)
 180                                 roce->netdev = (event == NETDEV_UNREGISTER) ?
 181                                         NULL : ndev;
 182                 } else if (ndev->dev.parent == &mdev->pdev->dev) {
 183                         roce->netdev = (event == NETDEV_UNREGISTER) ?
 184                                 NULL : ndev;
 185                 }
 186                 write_unlock(&roce->netdev_lock);
 187                 break;
 188
 189         case NETDEV_CHANGE:
 190         case NETDEV_UP:
 191         case NETDEV_DOWN: {
 192                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 193                 struct net_device *upper = NULL;
 194
 195                 if (lag_ndev) {
 196                         upper = netdev_master_upper_dev_get(lag_ndev);
 197                         dev_put(lag_ndev);
 198                 }
 199
 200                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 201                     && ibdev->ib_active) {
 202                         struct ib_event ibev = { };
 203                         enum ib_port_state port_state;
 204
 205                         if (get_port_state(&ibdev->ib_dev, port_num,
 206                                            &port_state))
 207                                 goto done;
 208
 209                         if (roce->last_port_state == port_state)
 210                                 goto done;
 211
 212                         roce->last_port_state = port_state;
 213                         ibev.device = &ibdev->ib_dev;
 214                         if (port_state == IB_PORT_DOWN)
 215                                 ibev.event = IB_EVENT_PORT_ERR;
 216                         else if (port_state == IB_PORT_ACTIVE)
 217                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 218                         else
 219                                 goto done;
 220
 221                         ibev.element.port_num = port_num;
 222                         ib_dispatch_event(&ibev);
 223                 }
 224                 break;
 225         }
 226
 227         default:
 228                 break;
 229         }
 230 done:
 231         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 232         return NOTIFY_DONE;
 233 }
 234
 235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 236                                              u8 port_num)
 237 {
 238         struct mlx5_ib_dev *ibdev = to_mdev(device);
 239         struct net_device *ndev;
 240         struct mlx5_core_dev *mdev;
 241
 242         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 243         if (!mdev)
 244                 return NULL;
 245
 246         ndev = mlx5_lag_get_roce_netdev(mdev);
 247         if (ndev)
 248                 goto out;
 249
 250         /* Ensure ndev does not disappear before we invoke dev_hold()
 251          */
 252         read_lock(&ibdev->roce[port_num - 1].netdev_lock);
 253         ndev = ibdev->roce[port_num - 1].netdev;
 254         if (ndev)
 255                 dev_hold(ndev);
 256         read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
 257
 258 out:
 259         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 260         return ndev;
 261 }
 262
 263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 264                                                    u8 ib_port_num,
 265                                                    u8 *native_port_num)
 266 {
 267         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 268                                                           ib_port_num);
 269         struct mlx5_core_dev *mdev = NULL;
 270         struct mlx5_ib_multiport_info *mpi;
 271         struct mlx5_ib_port *port;
 272
 273         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 274             ll != IB_LINK_LAYER_ETHERNET) {
 275                 if (native_port_num)
 276                         *native_port_num = ib_port_num;
 277                 return ibdev->mdev;
 278         }
 279
 280         if (native_port_num)
 281                 *native_port_num = 1;
 282
 283         port = &ibdev->port[ib_port_num - 1];
 284         if (!port)
 285                 return NULL;
 286
 287         spin_lock(&port->mp.mpi_lock);
 288         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 289         if (mpi && !mpi->unaffiliate) {
 290                 mdev = mpi->mdev;
 291                 /* If it's the master no need to refcount, it'll exist
 292                  * as long as the ib_dev exists.
 293                  */
 294                 if (!mpi->is_master)
 295                         mpi->mdev_refcnt++;
 296         }
 297         spin_unlock(&port->mp.mpi_lock);
 298
 299         return mdev;
 300 }
 301
 302 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 303 {
 304         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 305                                                           port_num);
 306         struct mlx5_ib_multiport_info *mpi;
 307         struct mlx5_ib_port *port;
 308
 309         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 310                 return;
 311
 312         port = &ibdev->port[port_num - 1];
 313
 314         spin_lock(&port->mp.mpi_lock);
 315         mpi = ibdev->port[port_num - 1].mp.mpi;
 316         if (mpi->is_master)
 317                 goto out;
 318
 319         mpi->mdev_refcnt--;
 320         if (mpi->unaffiliate)
 321                 complete(&mpi->unref_comp);
 322 out:
 323         spin_unlock(&port->mp.mpi_lock);
 324 }
 325
 326 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 327                                     u8 *active_width)
 328 {
 329         switch (eth_proto_oper) {
 330         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 331         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 332         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 333         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 334                 *active_width = IB_WIDTH_1X;
 335                 *active_speed = IB_SPEED_SDR;
 336                 break;
 337         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 338         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 339         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 340         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 341         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 342         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 343         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 344                 *active_width = IB_WIDTH_1X;
 345                 *active_speed = IB_SPEED_QDR;
 346                 break;
 347         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 348         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 349         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 350                 *active_width = IB_WIDTH_1X;
 351                 *active_speed = IB_SPEED_EDR;
 352                 break;
 353         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 354         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 355         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 356         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 357                 *active_width = IB_WIDTH_4X;
 358                 *active_speed = IB_SPEED_QDR;
 359                 break;
 360         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 361         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 362         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 363                 *active_width = IB_WIDTH_1X;
 364                 *active_speed = IB_SPEED_HDR;
 365                 break;
 366         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 367                 *active_width = IB_WIDTH_4X;
 368                 *active_speed = IB_SPEED_FDR;
 369                 break;
 370         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 371         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 372         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 373         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 374                 *active_width = IB_WIDTH_4X;
 375                 *active_speed = IB_SPEED_EDR;
 376                 break;
 377         default:
 378                 return -EINVAL;
 379         }
 380
 381         return 0;
 382 }
 383
 384 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 385                                 struct ib_port_attr *props)
 386 {
 387         struct mlx5_ib_dev *dev = to_mdev(device);
 388         struct mlx5_core_dev *mdev;
 389         struct net_device *ndev, *upper;
 390         enum ib_mtu ndev_ib_mtu;
 391         bool put_mdev = true;
 392         u16 qkey_viol_cntr;
 393         u32 eth_prot_oper;
 394         u8 mdev_port_num;
 395         int err;
 396
 397         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 398         if (!mdev) {
 399                 /* This means the port isn't affiliated yet. Get the
 400                  * info for the master port instead.
 401                  */
 402                 put_mdev = false;
 403                 mdev = dev->mdev;
 404                 mdev_port_num = 1;
 405                 port_num = 1;
 406         }
 407
 408         /* Possible bad flows are checked before filling out props so in case
 409          * of an error it will still be zeroed out.
 410          */
 411         err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
 412                                              mdev_port_num);
 413         if (err)
 414                 goto out;
 415
 416         props->active_width     = IB_WIDTH_4X;
 417         props->active_speed     = IB_SPEED_QDR;
 418
 419         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 420                                  &props->active_width);
 421
 422         props->port_cap_flags  |= IB_PORT_CM_SUP;
 423         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 424
 425         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 426                                                 roce_address_table_size);
 427         props->max_mtu          = IB_MTU_4096;
 428         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 429         props->pkey_tbl_len     = 1;
 430         props->state            = IB_PORT_DOWN;
 431         props->phys_state       = 3;
 432
 433         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 434         props->qkey_viol_cntr = qkey_viol_cntr;
 435
 436         /* If this is a stub query for an unaffiliated port stop here */
 437         if (!put_mdev)
 438                 goto out;
 439
 440         ndev = mlx5_ib_get_netdev(device, port_num);
 441         if (!ndev)
 442                 goto out;
 443
 444         if (mlx5_lag_is_active(dev->mdev)) {
 445                 rcu_read_lock();
 446                 upper = netdev_master_upper_dev_get_rcu(ndev);
 447                 if (upper) {
 448                         dev_put(ndev);
 449                         ndev = upper;
 450                         dev_hold(ndev);
 451                 }
 452                 rcu_read_unlock();
 453         }
 454
 455         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 456                 props->state      = IB_PORT_ACTIVE;
 457                 props->phys_state = 5;
 458         }
 459
 460         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 461
 462         dev_put(ndev);
 463
 464         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 465 out:
 466         if (put_mdev)
 467                 mlx5_ib_put_native_port_mdev(dev, port_num);
 468         return err;
 469 }
 470
 471 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 472                          unsigned int index, const union ib_gid *gid,
 473                          const struct ib_gid_attr *attr)
 474 {
 475         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 476         u8 roce_version = 0;
 477         u8 roce_l3_type = 0;
 478         bool vlan = false;
 479         u8 mac[ETH_ALEN];
 480         u16 vlan_id = 0;
 481
 482         if (gid) {
 483                 gid_type = attr->gid_type;
 484                 ether_addr_copy(mac, attr->ndev->dev_addr);
 485
 486                 if (is_vlan_dev(attr->ndev)) {
 487                         vlan = true;
 488                         vlan_id = vlan_dev_vlan_id(attr->ndev);
 489                 }
 490         }
 491
 492         switch (gid_type) {
 493         case IB_GID_TYPE_IB:
 494                 roce_version = MLX5_ROCE_VERSION_1;
 495                 break;
 496         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 497                 roce_version = MLX5_ROCE_VERSION_2;
 498                 if (ipv6_addr_v4mapped((void *)gid))
 499                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 500                 else
 501                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 502                 break;
 503
 504         default:
 505                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 506         }
 507
 508         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 509                                       roce_l3_type, gid->raw, mac, vlan,
 510                                       vlan_id, port_num);
 511 }
 512
 513 static int mlx5_ib_add_gid(const union ib_gid *gid,
 514                            const struct ib_gid_attr *attr,
 515                            __always_unused void **context)
 516 {
 517         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 518                              attr->index, gid, attr);
 519 }
 520
 521 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 522                            __always_unused void **context)
 523 {
 524         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 525                              attr->index, NULL, NULL);
 526 }
 527
 528 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 529                                int index)
 530 {
 531         struct ib_gid_attr attr;
 532         union ib_gid gid;
 533
 534         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 535                 return 0;
 536
 537         dev_put(attr.ndev);
 538
 539         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 540                 return 0;
 541
 542         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 543 }
 544
 545 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
 546                            int index, enum ib_gid_type *gid_type)
 547 {
 548         struct ib_gid_attr attr;
 549         union ib_gid gid;
 550         int ret;
 551
 552         ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
 553         if (ret)
 554                 return ret;
 555
 556         dev_put(attr.ndev);
 557
 558         *gid_type = attr.gid_type;
 559
 560         return 0;
 561 }
 562
 563 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 564 {
 565         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 566                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 567         return 0;
 568 }
 569
 570 enum {
 571         MLX5_VPORT_ACCESS_METHOD_MAD,
 572         MLX5_VPORT_ACCESS_METHOD_HCA,
 573         MLX5_VPORT_ACCESS_METHOD_NIC,
 574 };
 575
 576 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 577 {
 578         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 579                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 580
 581         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 582             IB_LINK_LAYER_ETHERNET)
 583                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 584
 585         return MLX5_VPORT_ACCESS_METHOD_HCA;
 586 }
 587
 588 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 589                             u8 atomic_size_qp,
 590                             struct ib_device_attr *props)
 591 {
 592         u8 tmp;
 593         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 594         u8 atomic_req_8B_endianness_mode =
 595                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 596
 597         /* Check if HW supports 8 bytes standard atomic operations and capable
 598          * of host endianness respond
 599          */
 600         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 601         if (((atomic_operations & tmp) == tmp) &&
 602             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 603             (atomic_req_8B_endianness_mode)) {
 604                 props->atomic_cap = IB_ATOMIC_HCA;
 605         } else {
 606                 props->atomic_cap = IB_ATOMIC_NONE;
 607         }
 608 }
 609
 610 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 611                                struct ib_device_attr *props)
 612 {
 613         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 614
 615         get_atomic_caps(dev, atomic_size_qp, props);
 616 }
 617
 618 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 619                                struct ib_device_attr *props)
 620 {
 621         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 622
 623         get_atomic_caps(dev, atomic_size_qp, props);
 624 }
 625
 626 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 627 {
 628         struct ib_device_attr props = {};
 629
 630         get_atomic_caps_dc(dev, &props);
 631         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 632 }
 633 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 634                                         __be64 *sys_image_guid)
 635 {
 636         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 637         struct mlx5_core_dev *mdev = dev->mdev;
 638         u64 tmp;
 639         int err;
 640
 641         switch (mlx5_get_vport_access_method(ibdev)) {
 642         case MLX5_VPORT_ACCESS_METHOD_MAD:
 643                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 644                                                             sys_image_guid);
 645
 646         case MLX5_VPORT_ACCESS_METHOD_HCA:
 647                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 648                 break;
 649
 650         case MLX5_VPORT_ACCESS_METHOD_NIC:
 651                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 652                 break;
 653
 654         default:
 655                 return -EINVAL;
 656         }
 657
 658         if (!err)
 659                 *sys_image_guid = cpu_to_be64(tmp);
 660
 661         return err;
 662
 663 }
 664
 665 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 666                                 u16 *max_pkeys)
 667 {
 668         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 669         struct mlx5_core_dev *mdev = dev->mdev;
 670
 671         switch (mlx5_get_vport_access_method(ibdev)) {
 672         case MLX5_VPORT_ACCESS_METHOD_MAD:
 673                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 674
 675         case MLX5_VPORT_ACCESS_METHOD_HCA:
 676         case MLX5_VPORT_ACCESS_METHOD_NIC:
 677                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 678                                                 pkey_table_size));
 679                 return 0;
 680
 681         default:
 682                 return -EINVAL;
 683         }
 684 }
 685
 686 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 687                                 u32 *vendor_id)
 688 {
 689         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 690
 691         switch (mlx5_get_vport_access_method(ibdev)) {
 692         case MLX5_VPORT_ACCESS_METHOD_MAD:
 693                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 694
 695         case MLX5_VPORT_ACCESS_METHOD_HCA:
 696         case MLX5_VPORT_ACCESS_METHOD_NIC:
 697                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 698
 699         default:
 700                 return -EINVAL;
 701         }
 702 }
 703
 704 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 705                                 __be64 *node_guid)
 706 {
 707         u64 tmp;
 708         int err;
 709
 710         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 711         case MLX5_VPORT_ACCESS_METHOD_MAD:
 712                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 713
 714         case MLX5_VPORT_ACCESS_METHOD_HCA:
 715                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 716                 break;
 717
 718         case MLX5_VPORT_ACCESS_METHOD_NIC:
 719                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 720                 break;
 721
 722         default:
 723                 return -EINVAL;
 724         }
 725
 726         if (!err)
 727                 *node_guid = cpu_to_be64(tmp);
 728
 729         return err;
 730 }
 731
 732 struct mlx5_reg_node_desc {
 733         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 734 };
 735
 736 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 737 {
 738         struct mlx5_reg_node_desc in;
 739
 740         if (mlx5_use_mad_ifc(dev))
 741                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 742
 743         memset(&in, 0, sizeof(in));
 744
 745         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 746                                     sizeof(struct mlx5_reg_node_desc),
 747                                     MLX5_REG_NODE_DESC, 0, 0);
 748 }
 749
 750 static int mlx5_ib_query_device(struct ib_device *ibdev,
 751                                 struct ib_device_attr *props,
 752                                 struct ib_udata *uhw)
 753 {
 754         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 755         struct mlx5_core_dev *mdev = dev->mdev;
 756         int err = -ENOMEM;
 757         int max_sq_desc;
 758         int max_rq_sg;
 759         int max_sq_sg;
 760         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 761         bool raw_support = !mlx5_core_mp_enabled(mdev);
 762         struct mlx5_ib_query_device_resp resp = {};
 763         size_t resp_len;
 764         u64 max_tso;
 765
 766         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 767         if (uhw->outlen && uhw->outlen < resp_len)
 768                 return -EINVAL;
 769         else
 770                 resp.response_length = resp_len;
 771
 772         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 773                 return -EINVAL;
 774
 775         memset(props, 0, sizeof(*props));
 776         err = mlx5_query_system_image_guid(ibdev,
 777                                            &props->sys_image_guid);
 778         if (err)
 779                 return err;
 780
 781         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 782         if (err)
 783                 return err;
 784
 785         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 786         if (err)
 787                 return err;
 788
 789         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 790                 (fw_rev_min(dev->mdev) << 16) |
 791                 fw_rev_sub(dev->mdev);
 792         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 793                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 794                 IB_DEVICE_SYS_IMAGE_GUID                |
 795                 IB_DEVICE_RC_RNR_NAK_GEN;
 796
 797         if (MLX5_CAP_GEN(mdev, pkv))
 798                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 799         if (MLX5_CAP_GEN(mdev, qkv))
 800                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 801         if (MLX5_CAP_GEN(mdev, apm))
 802                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 803         if (MLX5_CAP_GEN(mdev, xrc))
 804                 props->device_cap_flags |= IB_DEVICE_XRC;
 805         if (MLX5_CAP_GEN(mdev, imaicl)) {
 806                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 807                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 808                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 809                 /* We support 'Gappy' memory registration too */
 810                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 811         }
 812         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 813         if (MLX5_CAP_GEN(mdev, sho)) {
 814                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 815                 /* At this stage no support for signature handover */
 816                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 817                                       IB_PROT_T10DIF_TYPE_2 |
 818                                       IB_PROT_T10DIF_TYPE_3;
 819                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 820                                        IB_GUARD_T10DIF_CSUM;
 821         }
 822         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 823                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 824
 825         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 826                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 827                         /* Legacy bit to support old userspace libraries */
 828                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 829                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 830                 }
 831
 832                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 833                         props->raw_packet_caps |=
 834                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 835
 836                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 837                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 838                         if (max_tso) {
 839                                 resp.tso_caps.max_tso = 1 << max_tso;
 840                                 resp.tso_caps.supported_qpts |=
 841                                         1 << IB_QPT_RAW_PACKET;
 842                                 resp.response_length += sizeof(resp.tso_caps);
 843                         }
 844                 }
 845
 846                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 847                         resp.rss_caps.rx_hash_function =
 848                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 849                         resp.rss_caps.rx_hash_fields_mask =
 850                                                 MLX5_RX_HASH_SRC_IPV4 |
 851                                                 MLX5_RX_HASH_DST_IPV4 |
 852                                                 MLX5_RX_HASH_SRC_IPV6 |
 853                                                 MLX5_RX_HASH_DST_IPV6 |
 854                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 855                                                 MLX5_RX_HASH_DST_PORT_TCP |
 856                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 857                                                 MLX5_RX_HASH_DST_PORT_UDP |
 858                                                 MLX5_RX_HASH_INNER;
 859                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 860                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 861                                 resp.rss_caps.rx_hash_fields_mask |=
 862                                         MLX5_RX_HASH_IPSEC_SPI;
 863                         resp.response_length += sizeof(resp.rss_caps);
 864                 }
 865         } else {
 866                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 867                         resp.response_length += sizeof(resp.tso_caps);
 868                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 869                         resp.response_length += sizeof(resp.rss_caps);
 870         }
 871
 872         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 873                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 874                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 875         }
 876
 877         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 878             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 879             raw_support)
 880                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 881
 882         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 883             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 884                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 885
 886         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 887             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 888             raw_support) {
 889                 /* Legacy bit to support old userspace libraries */
 890                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 891                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 892         }
 893
 894         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 895                 props->max_dm_size =
 896                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 897         }
 898
 899         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 900                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 901
 902         if (MLX5_CAP_GEN(mdev, end_pad))
 903                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 904
 905         props->vendor_part_id      = mdev->pdev->device;
 906         props->hw_ver              = mdev->pdev->revision;
 907
 908         props->max_mr_size         = ~0ull;
 909         props->page_size_cap       = ~(min_page_size - 1);
 910         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 911         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 912         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 913                      sizeof(struct mlx5_wqe_data_seg);
 914         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 915         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 916                      sizeof(struct mlx5_wqe_raddr_seg)) /
 917                 sizeof(struct mlx5_wqe_data_seg);
 918         props->max_sge = min(max_rq_sg, max_sq_sg);
 919         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 920         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 921         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 922         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 923         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 924         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 925         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 926         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 927         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 928         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 929         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 930         props->max_srq_sge         = max_rq_sg - 1;
 931         props->max_fast_reg_page_list_len =
 932                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 933         get_atomic_caps_qp(dev, props);
 934         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 935         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 936         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 937         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 938                                            props->max_mcast_grp;
 939         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 940         props->max_ah = INT_MAX;
 941         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 942         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 943
 944 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 945         if (MLX5_CAP_GEN(mdev, pg))
 946                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 947         props->odp_caps = dev->odp_caps;
 948 #endif
 949
 950         if (MLX5_CAP_GEN(mdev, cd))
 951                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 952
 953         if (!mlx5_core_is_pf(mdev))
 954                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 955
 956         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 957             IB_LINK_LAYER_ETHERNET && raw_support) {
 958                 props->rss_caps.max_rwq_indirection_tables =
 959                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 960                 props->rss_caps.max_rwq_indirection_table_size =
 961                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 962                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 963                 props->max_wq_type_rq =
 964                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 965         }
 966
 967         if (MLX5_CAP_GEN(mdev, tag_matching)) {
 968                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
 969                 props->tm_caps.max_num_tags =
 970                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
 971                 props->tm_caps.flags = IB_TM_CAP_RC;
 972                 props->tm_caps.max_ops =
 973                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 974                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
 975         }
 976
 977         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
 978                 props->cq_caps.max_cq_moderation_count =
 979                                                 MLX5_MAX_CQ_COUNT;
 980                 props->cq_caps.max_cq_moderation_period =
 981                                                 MLX5_MAX_CQ_PERIOD;
 982         }
 983
 984         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 985                 resp.response_length += sizeof(resp.cqe_comp_caps);
 986
 987                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
 988                         resp.cqe_comp_caps.max_num =
 989                                 MLX5_CAP_GEN(dev->mdev,
 990                                              cqe_compression_max_num);
 991
 992                         resp.cqe_comp_caps.supported_format =
 993                                 MLX5_IB_CQE_RES_FORMAT_HASH |
 994                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
 995
 996                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
 997                                 resp.cqe_comp_caps.supported_format |=
 998                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
 999                 }
1000         }
1001
1002         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1003             raw_support) {
1004                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1005                     MLX5_CAP_GEN(mdev, qos)) {
1006                         resp.packet_pacing_caps.qp_rate_limit_max =
1007                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1008                         resp.packet_pacing_caps.qp_rate_limit_min =
1009                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1010                         resp.packet_pacing_caps.supported_qpts |=
1011                                 1 << IB_QPT_RAW_PACKET;
1012                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1013                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1014                                 resp.packet_pacing_caps.cap_flags |=
1015                                         MLX5_IB_PP_SUPPORT_BURST;
1016                 }
1017                 resp.response_length += sizeof(resp.packet_pacing_caps);
1018         }
1019
1020         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1021                         uhw->outlen)) {
1022                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1023                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1024                                 MLX5_IB_ALLOW_MPW;
1025
1026                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1027                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1028                                 MLX5_IB_SUPPORT_EMPW;
1029
1030                 resp.response_length +=
1031                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1032         }
1033
1034         if (field_avail(typeof(resp), flags, uhw->outlen)) {
1035                 resp.response_length += sizeof(resp.flags);
1036
1037                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1038                         resp.flags |=
1039                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1040
1041                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1042                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1043         }
1044
1045         if (field_avail(typeof(resp), sw_parsing_caps,
1046                         uhw->outlen)) {
1047                 resp.response_length += sizeof(resp.sw_parsing_caps);
1048                 if (MLX5_CAP_ETH(mdev, swp)) {
1049                         resp.sw_parsing_caps.sw_parsing_offloads |=
1050                                 MLX5_IB_SW_PARSING;
1051
1052                         if (MLX5_CAP_ETH(mdev, swp_csum))
1053                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1054                                         MLX5_IB_SW_PARSING_CSUM;
1055
1056                         if (MLX5_CAP_ETH(mdev, swp_lso))
1057                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1058                                         MLX5_IB_SW_PARSING_LSO;
1059
1060                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1061                                 resp.sw_parsing_caps.supported_qpts =
1062                                         BIT(IB_QPT_RAW_PACKET);
1063                 }
1064         }
1065
1066         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1067             raw_support) {
1068                 resp.response_length += sizeof(resp.striding_rq_caps);
1069                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1070                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1071                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1072                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1073                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1074                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1075                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1076                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1077                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1078                         resp.striding_rq_caps.supported_qpts =
1079                                 BIT(IB_QPT_RAW_PACKET);
1080                 }
1081         }
1082
1083         if (field_avail(typeof(resp), tunnel_offloads_caps,
1084                         uhw->outlen)) {
1085                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1086                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1087                         resp.tunnel_offloads_caps |=
1088                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1089                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1090                         resp.tunnel_offloads_caps |=
1091                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1092                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1093                         resp.tunnel_offloads_caps |=
1094                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1095                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1096                     MLX5_FLEX_PROTO_CW_MPLS_GRE)
1097                         resp.tunnel_offloads_caps |=
1098                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1099                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1100                     MLX5_FLEX_PROTO_CW_MPLS_UDP)
1101                         resp.tunnel_offloads_caps |=
1102                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1103         }
1104
1105         if (uhw->outlen) {
1106                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1107
1108                 if (err)
1109                         return err;
1110         }
1111
1112         return 0;
1113 }
1114
1115 enum mlx5_ib_width {
1116         MLX5_IB_WIDTH_1X        = 1 << 0,
1117         MLX5_IB_WIDTH_2X        = 1 << 1,
1118         MLX5_IB_WIDTH_4X        = 1 << 2,
1119         MLX5_IB_WIDTH_8X        = 1 << 3,
1120         MLX5_IB_WIDTH_12X       = 1 << 4
1121 };
1122
1123 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1124                                   u8 *ib_width)
1125 {
1126         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1127         int err = 0;
1128
1129         if (active_width & MLX5_IB_WIDTH_1X) {
1130                 *ib_width = IB_WIDTH_1X;
1131         } else if (active_width & MLX5_IB_WIDTH_2X) {
1132                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1133                             (int)active_width);
1134                 err = -EINVAL;
1135         } else if (active_width & MLX5_IB_WIDTH_4X) {
1136                 *ib_width = IB_WIDTH_4X;
1137         } else if (active_width & MLX5_IB_WIDTH_8X) {
1138                 *ib_width = IB_WIDTH_8X;
1139         } else if (active_width & MLX5_IB_WIDTH_12X) {
1140                 *ib_width = IB_WIDTH_12X;
1141         } else {
1142                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1143                             (int)active_width);
1144                 err = -EINVAL;
1145         }
1146
1147         return err;
1148 }
1149
1150 static int mlx5_mtu_to_ib_mtu(int mtu)
1151 {
1152         switch (mtu) {
1153         case 256: return 1;
1154         case 512: return 2;
1155         case 1024: return 3;
1156         case 2048: return 4;
1157         case 4096: return 5;
1158         default:
1159                 pr_warn("invalid mtu\n");
1160                 return -1;
1161         }
1162 }
1163
1164 enum ib_max_vl_num {
1165         __IB_MAX_VL_0           = 1,
1166         __IB_MAX_VL_0_1         = 2,
1167         __IB_MAX_VL_0_3         = 3,
1168         __IB_MAX_VL_0_7         = 4,
1169         __IB_MAX_VL_0_14        = 5,
1170 };
1171
1172 enum mlx5_vl_hw_cap {
1173         MLX5_VL_HW_0    = 1,
1174         MLX5_VL_HW_0_1  = 2,
1175         MLX5_VL_HW_0_2  = 3,
1176         MLX5_VL_HW_0_3  = 4,
1177         MLX5_VL_HW_0_4  = 5,
1178         MLX5_VL_HW_0_5  = 6,
1179         MLX5_VL_HW_0_6  = 7,
1180         MLX5_VL_HW_0_7  = 8,
1181         MLX5_VL_HW_0_14 = 15
1182 };
1183
1184 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1185                                 u8 *max_vl_num)
1186 {
1187         switch (vl_hw_cap) {
1188         case MLX5_VL_HW_0:
1189                 *max_vl_num = __IB_MAX_VL_0;
1190                 break;
1191         case MLX5_VL_HW_0_1:
1192                 *max_vl_num = __IB_MAX_VL_0_1;
1193                 break;
1194         case MLX5_VL_HW_0_3:
1195                 *max_vl_num = __IB_MAX_VL_0_3;
1196                 break;
1197         case MLX5_VL_HW_0_7:
1198                 *max_vl_num = __IB_MAX_VL_0_7;
1199                 break;
1200         case MLX5_VL_HW_0_14:
1201                 *max_vl_num = __IB_MAX_VL_0_14;
1202                 break;
1203
1204         default:
1205                 return -EINVAL;
1206         }
1207
1208         return 0;
1209 }
1210
1211 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1212                                struct ib_port_attr *props)
1213 {
1214         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1215         struct mlx5_core_dev *mdev = dev->mdev;
1216         struct mlx5_hca_vport_context *rep;
1217         u16 max_mtu;
1218         u16 oper_mtu;
1219         int err;
1220         u8 ib_link_width_oper;
1221         u8 vl_hw_cap;
1222
1223         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1224         if (!rep) {
1225                 err = -ENOMEM;
1226                 goto out;
1227         }
1228
1229         /* props being zeroed by the caller, avoid zeroing it here */
1230
1231         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1232         if (err)
1233                 goto out;
1234
1235         props->lid              = rep->lid;
1236         props->lmc              = rep->lmc;
1237         props->sm_lid           = rep->sm_lid;
1238         props->sm_sl            = rep->sm_sl;
1239         props->state            = rep->vport_state;
1240         props->phys_state       = rep->port_physical_state;
1241         props->port_cap_flags   = rep->cap_mask1;
1242         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1243         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1244         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1245         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1246         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1247         props->subnet_timeout   = rep->subnet_timeout;
1248         props->init_type_reply  = rep->init_type_reply;
1249         props->grh_required     = rep->grh_required;
1250
1251         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1252         if (err)
1253                 goto out;
1254
1255         err = translate_active_width(ibdev, ib_link_width_oper,
1256                                      &props->active_width);
1257         if (err)
1258                 goto out;
1259         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1260         if (err)
1261                 goto out;
1262
1263         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1264
1265         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1266
1267         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1268
1269         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1270
1271         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1272         if (err)
1273                 goto out;
1274
1275         err = translate_max_vl_num(ibdev, vl_hw_cap,
1276                                    &props->max_vl_num);
1277 out:
1278         kfree(rep);
1279         return err;
1280 }
1281
1282 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1283                        struct ib_port_attr *props)
1284 {
1285         unsigned int count;
1286         int ret;
1287
1288         switch (mlx5_get_vport_access_method(ibdev)) {
1289         case MLX5_VPORT_ACCESS_METHOD_MAD:
1290                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1291                 break;
1292
1293         case MLX5_VPORT_ACCESS_METHOD_HCA:
1294                 ret = mlx5_query_hca_port(ibdev, port, props);
1295                 break;
1296
1297         case MLX5_VPORT_ACCESS_METHOD_NIC:
1298                 ret = mlx5_query_port_roce(ibdev, port, props);
1299                 break;
1300
1301         default:
1302                 ret = -EINVAL;
1303         }
1304
1305         if (!ret && props) {
1306                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1307                 struct mlx5_core_dev *mdev;
1308                 bool put_mdev = true;
1309
1310                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1311                 if (!mdev) {
1312                         /* If the port isn't affiliated yet query the master.
1313                          * The master and slave will have the same values.
1314                          */
1315                         mdev = dev->mdev;
1316                         port = 1;
1317                         put_mdev = false;
1318                 }
1319                 count = mlx5_core_reserved_gids_count(mdev);
1320                 if (put_mdev)
1321                         mlx5_ib_put_native_port_mdev(dev, port);
1322                 props->gid_tbl_len -= count;
1323         }
1324         return ret;
1325 }
1326
1327 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1328                                   struct ib_port_attr *props)
1329 {
1330         int ret;
1331
1332         /* Only link layer == ethernet is valid for representors */
1333         ret = mlx5_query_port_roce(ibdev, port, props);
1334         if (ret || !props)
1335                 return ret;
1336
1337         /* We don't support GIDS */
1338         props->gid_tbl_len = 0;
1339
1340         return ret;
1341 }
1342
1343 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1344                              union ib_gid *gid)
1345 {
1346         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1347         struct mlx5_core_dev *mdev = dev->mdev;
1348
1349         switch (mlx5_get_vport_access_method(ibdev)) {
1350         case MLX5_VPORT_ACCESS_METHOD_MAD:
1351                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1352
1353         case MLX5_VPORT_ACCESS_METHOD_HCA:
1354                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1355
1356         default:
1357                 return -EINVAL;
1358         }
1359
1360 }
1361
1362 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1363                                    u16 index, u16 *pkey)
1364 {
1365         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1366         struct mlx5_core_dev *mdev;
1367         bool put_mdev = true;
1368         u8 mdev_port_num;
1369         int err;
1370
1371         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1372         if (!mdev) {
1373                 /* The port isn't affiliated yet, get the PKey from the master
1374                  * port. For RoCE the PKey tables will be the same.
1375                  */
1376                 put_mdev = false;
1377                 mdev = dev->mdev;
1378                 mdev_port_num = 1;
1379         }
1380
1381         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1382                                         index, pkey);
1383         if (put_mdev)
1384                 mlx5_ib_put_native_port_mdev(dev, port);
1385
1386         return err;
1387 }
1388
1389 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1390                               u16 *pkey)
1391 {
1392         switch (mlx5_get_vport_access_method(ibdev)) {
1393         case MLX5_VPORT_ACCESS_METHOD_MAD:
1394                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1395
1396         case MLX5_VPORT_ACCESS_METHOD_HCA:
1397         case MLX5_VPORT_ACCESS_METHOD_NIC:
1398                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1399         default:
1400                 return -EINVAL;
1401         }
1402 }
1403
1404 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1405                                  struct ib_device_modify *props)
1406 {
1407         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1408         struct mlx5_reg_node_desc in;
1409         struct mlx5_reg_node_desc out;
1410         int err;
1411
1412         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1413                 return -EOPNOTSUPP;
1414
1415         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1416                 return 0;
1417
1418         /*
1419          * If possible, pass node desc to FW, so it can generate
1420          * a 144 trap.  If cmd fails, just ignore.
1421          */
1422         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1423         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1424                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1425         if (err)
1426                 return err;
1427
1428         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1429
1430         return err;
1431 }
1432
1433 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1434                                 u32 value)
1435 {
1436         struct mlx5_hca_vport_context ctx = {};
1437         struct mlx5_core_dev *mdev;
1438         u8 mdev_port_num;
1439         int err;
1440
1441         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1442         if (!mdev)
1443                 return -ENODEV;
1444
1445         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1446         if (err)
1447                 goto out;
1448
1449         if (~ctx.cap_mask1_perm & mask) {
1450                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1451                              mask, ctx.cap_mask1_perm);
1452                 err = -EINVAL;
1453                 goto out;
1454         }
1455
1456         ctx.cap_mask1 = value;
1457         ctx.cap_mask1_perm = mask;
1458         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1459                                                  0, &ctx);
1460
1461 out:
1462         mlx5_ib_put_native_port_mdev(dev, port_num);
1463
1464         return err;
1465 }
1466
1467 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1468                                struct ib_port_modify *props)
1469 {
1470         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1471         struct ib_port_attr attr;
1472         u32 tmp;
1473         int err;
1474         u32 change_mask;
1475         u32 value;
1476         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1477                       IB_LINK_LAYER_INFINIBAND);
1478
1479         /* CM layer calls ib_modify_port() regardless of the link layer. For
1480          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1481          */
1482         if (!is_ib)
1483                 return 0;
1484
1485         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1486                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1487                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1488                 return set_port_caps_atomic(dev, port, change_mask, value);
1489         }
1490
1491         mutex_lock(&dev->cap_mask_mutex);
1492
1493         err = ib_query_port(ibdev, port, &attr);
1494         if (err)
1495                 goto out;
1496
1497         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1498                 ~props->clr_port_cap_mask;
1499
1500         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1501
1502 out:
1503         mutex_unlock(&dev->cap_mask_mutex);
1504         return err;
1505 }
1506
1507 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1508 {
1509         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1510                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1511 }
1512
1513 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1514 {
1515         /* Large page with non 4k uar support might limit the dynamic size */
1516         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1517                 return MLX5_MIN_DYN_BFREGS;
1518
1519         return MLX5_MAX_DYN_BFREGS;
1520 }
1521
1522 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1523                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1524                              struct mlx5_bfreg_info *bfregi)
1525 {
1526         int uars_per_sys_page;
1527         int bfregs_per_sys_page;
1528         int ref_bfregs = req->total_num_bfregs;
1529
1530         if (req->total_num_bfregs == 0)
1531                 return -EINVAL;
1532
1533         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1534         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1535
1536         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1537                 return -ENOMEM;
1538
1539         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1540         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1541         /* This holds the required static allocation asked by the user */
1542         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1543         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1544                 return -EINVAL;
1545
1546         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1547         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1548         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1549         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1550
1551         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1552                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1553                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1554                     req->total_num_bfregs, bfregi->total_num_bfregs,
1555                     bfregi->num_sys_pages);
1556
1557         return 0;
1558 }
1559
1560 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1561 {
1562         struct mlx5_bfreg_info *bfregi;
1563         int err;
1564         int i;
1565
1566         bfregi = &context->bfregi;
1567         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1568                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1569                 if (err)
1570                         goto error;
1571
1572                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1573         }
1574
1575         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1576                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1577
1578         return 0;
1579
1580 error:
1581         for (--i; i >= 0; i--)
1582                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1583                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1584
1585         return err;
1586 }
1587
1588 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1589 {
1590         struct mlx5_bfreg_info *bfregi;
1591         int err;
1592         int i;
1593
1594         bfregi = &context->bfregi;
1595         for (i = 0; i < bfregi->num_sys_pages; i++) {
1596                 if (i < bfregi->num_static_sys_pages ||
1597                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) {
1598                         err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1599                         if (err) {
1600                                 mlx5_ib_warn(dev, "failed to free uar %d, err=%d\n", i, err);
1601                                 return err;
1602                         }
1603                 }
1604         }
1605
1606         return 0;
1607 }
1608
1609 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1610 {
1611         int err;
1612
1613         err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1614         if (err)
1615                 return err;
1616
1617         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1618             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1619              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1620                 return err;
1621
1622         mutex_lock(&dev->lb_mutex);
1623         dev->user_td++;
1624
1625         if (dev->user_td == 2)
1626                 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1627
1628         mutex_unlock(&dev->lb_mutex);
1629         return err;
1630 }
1631
1632 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1633 {
1634         mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1635
1636         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1637             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1638              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1639                 return;
1640
1641         mutex_lock(&dev->lb_mutex);
1642         dev->user_td--;
1643
1644         if (dev->user_td < 2)
1645                 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1646
1647         mutex_unlock(&dev->lb_mutex);
1648 }
1649
1650 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1651                                                   struct ib_udata *udata)
1652 {
1653         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1654         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1655         struct mlx5_ib_alloc_ucontext_resp resp = {};
1656         struct mlx5_core_dev *mdev = dev->mdev;
1657         struct mlx5_ib_ucontext *context;
1658         struct mlx5_bfreg_info *bfregi;
1659         int ver;
1660         int err;
1661         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1662                                      max_cqe_version);
1663         u32 dump_fill_mkey;
1664         bool lib_uar_4k;
1665
1666         if (!dev->ib_active)
1667                 return ERR_PTR(-EAGAIN);
1668
1669         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1670                 ver = 0;
1671         else if (udata->inlen >= min_req_v2)
1672                 ver = 2;
1673         else
1674                 return ERR_PTR(-EINVAL);
1675
1676         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1677         if (err)
1678                 return ERR_PTR(err);
1679
1680         if (req.flags)
1681                 return ERR_PTR(-EINVAL);
1682
1683         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1684                 return ERR_PTR(-EOPNOTSUPP);
1685
1686         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1687                                     MLX5_NON_FP_BFREGS_PER_UAR);
1688         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1689                 return ERR_PTR(-EINVAL);
1690
1691         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1692         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1693                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1694         resp.cache_line_size = cache_line_size();
1695         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1696         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1697         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1698         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1699         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1700         resp.cqe_version = min_t(__u8,
1701                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1702                                  req.max_cqe_version);
1703         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1704                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1705         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1706                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1707         resp.response_length = min(offsetof(typeof(resp), response_length) +
1708                                    sizeof(resp.response_length), udata->outlen);
1709
1710         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1711                 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1712                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1713                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1714                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1715                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1716                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1717                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1718                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1719                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1720         }
1721
1722         context = kzalloc(sizeof(*context), GFP_KERNEL);
1723         if (!context)
1724                 return ERR_PTR(-ENOMEM);
1725
1726         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1727         bfregi = &context->bfregi;
1728
1729         /* updates req->total_num_bfregs */
1730         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1731         if (err)
1732                 goto out_ctx;
1733
1734         mutex_init(&bfregi->lock);
1735         bfregi->lib_uar_4k = lib_uar_4k;
1736         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1737                                 GFP_KERNEL);
1738         if (!bfregi->count) {
1739                 err = -ENOMEM;
1740                 goto out_ctx;
1741         }
1742
1743         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1744                                     sizeof(*bfregi->sys_pages),
1745                                     GFP_KERNEL);
1746         if (!bfregi->sys_pages) {
1747                 err = -ENOMEM;
1748                 goto out_count;
1749         }
1750
1751         err = allocate_uars(dev, context);
1752         if (err)
1753                 goto out_sys_pages;
1754
1755 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1756         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1757 #endif
1758
1759         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1760                 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1761                 if (err)
1762                         goto out_uars;
1763         }
1764
1765         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1766                 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1767                 if (err)
1768                         goto out_td;
1769         }
1770
1771         INIT_LIST_HEAD(&context->vma_private_list);
1772         mutex_init(&context->vma_private_list_mutex);
1773         INIT_LIST_HEAD(&context->db_page_list);
1774         mutex_init(&context->db_page_mutex);
1775
1776         resp.tot_bfregs = req.total_num_bfregs;
1777         resp.num_ports = dev->num_ports;
1778
1779         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1780                 resp.response_length += sizeof(resp.cqe_version);
1781
1782         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1783                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1784                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1785                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1786         }
1787
1788         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1789                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1790                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1791                         resp.eth_min_inline++;
1792                 }
1793                 resp.response_length += sizeof(resp.eth_min_inline);
1794         }
1795
1796         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1797                 if (mdev->clock_info)
1798                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1799                 resp.response_length += sizeof(resp.clock_info_versions);
1800         }
1801
1802         /*
1803          * We don't want to expose information from the PCI bar that is located
1804          * after 4096 bytes, so if the arch only supports larger pages, let's
1805          * pretend we don't support reading the HCA's core clock. This is also
1806          * forced by mmap function.
1807          */
1808         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1809                 if (PAGE_SIZE <= 4096) {
1810                         resp.comp_mask |=
1811                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1812                         resp.hca_core_clock_offset =
1813                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1814                 }
1815                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1816         }
1817
1818         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1819                 resp.response_length += sizeof(resp.log_uar_size);
1820
1821         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1822                 resp.response_length += sizeof(resp.num_uars_per_page);
1823
1824         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1825                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1826                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1827         }
1828
1829         if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1830                 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1831                         resp.dump_fill_mkey = dump_fill_mkey;
1832                         resp.comp_mask |=
1833                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1834                 }
1835                 resp.response_length += sizeof(resp.dump_fill_mkey);
1836         }
1837
1838         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1839         if (err)
1840                 goto out_td;
1841
1842         bfregi->ver = ver;
1843         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1844         context->cqe_version = resp.cqe_version;
1845         context->lib_caps = req.lib_caps;
1846         print_lib_caps(dev, context->lib_caps);
1847
1848         return &context->ibucontext;
1849
1850 out_td:
1851         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1852                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1853
1854 out_uars:
1855         deallocate_uars(dev, context);
1856
1857 out_sys_pages:
1858         kfree(bfregi->sys_pages);
1859
1860 out_count:
1861         kfree(bfregi->count);
1862
1863 out_ctx:
1864         kfree(context);
1865
1866         return ERR_PTR(err);
1867 }
1868
1869 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1870 {
1871         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1872         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1873         struct mlx5_bfreg_info *bfregi;
1874
1875         bfregi = &context->bfregi;
1876         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1877                 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1878
1879         deallocate_uars(dev, context);
1880         kfree(bfregi->sys_pages);
1881         kfree(bfregi->count);
1882         kfree(context);
1883
1884         return 0;
1885 }
1886
1887 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1888                                  int uar_idx)
1889 {
1890         int fw_uars_per_page;
1891
1892         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1893
1894         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1895 }
1896
1897 static int get_command(unsigned long offset)
1898 {
1899         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1900 }
1901
1902 static int get_arg(unsigned long offset)
1903 {
1904         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1905 }
1906
1907 static int get_index(unsigned long offset)
1908 {
1909         return get_arg(offset);
1910 }
1911
1912 /* Index resides in an extra byte to enable larger values than 255 */
1913 static int get_extended_index(unsigned long offset)
1914 {
1915         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1916 }
1917
1918 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1919 {
1920         /* vma_open is called when a new VMA is created on top of our VMA.  This
1921          * is done through either mremap flow or split_vma (usually due to
1922          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1923          * as this VMA is strongly hardware related.  Therefore we set the
1924          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1925          * calling us again and trying to do incorrect actions.  We assume that
1926          * the original VMA size is exactly a single page, and therefore all
1927          * "splitting" operation will not happen to it.
1928          */
1929         area->vm_ops = NULL;
1930 }
1931
1932 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1933 {
1934         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1935
1936         /* It's guaranteed that all VMAs opened on a FD are closed before the
1937          * file itself is closed, therefore no sync is needed with the regular
1938          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1939          * However need a sync with accessing the vma as part of
1940          * mlx5_ib_disassociate_ucontext.
1941          * The close operation is usually called under mm->mmap_sem except when
1942          * process is exiting.
1943          * The exiting case is handled explicitly as part of
1944          * mlx5_ib_disassociate_ucontext.
1945          */
1946         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1947
1948         /* setting the vma context pointer to null in the mlx5_ib driver's
1949          * private data, to protect a race condition in
1950          * mlx5_ib_disassociate_ucontext().
1951          */
1952         mlx5_ib_vma_priv_data->vma = NULL;
1953         mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1954         list_del(&mlx5_ib_vma_priv_data->list);
1955         mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1956         kfree(mlx5_ib_vma_priv_data);
1957 }
1958
1959 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1960         .open = mlx5_ib_vma_open,
1961         .close = mlx5_ib_vma_close
1962 };
1963
1964 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1965                                 struct mlx5_ib_ucontext *ctx)
1966 {
1967         struct mlx5_ib_vma_private_data *vma_prv;
1968         struct list_head *vma_head = &ctx->vma_private_list;
1969
1970         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1971         if (!vma_prv)
1972                 return -ENOMEM;
1973
1974         vma_prv->vma = vma;
1975         vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1976         vma->vm_private_data = vma_prv;
1977         vma->vm_ops =  &mlx5_ib_vm_ops;
1978
1979         mutex_lock(&ctx->vma_private_list_mutex);
1980         list_add(&vma_prv->list, vma_head);
1981         mutex_unlock(&ctx->vma_private_list_mutex);
1982
1983         return 0;
1984 }
1985
1986 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1987 {
1988         struct vm_area_struct *vma;
1989         struct mlx5_ib_vma_private_data *vma_private, *n;
1990         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1991
1992         mutex_lock(&context->vma_private_list_mutex);
1993         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1994                                  list) {
1995                 vma = vma_private->vma;
1996                 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
1997                 /* context going to be destroyed, should
1998                  * not access ops any more.
1999                  */
2000                 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
2001                 vma->vm_ops = NULL;
2002                 list_del(&vma_private->list);
2003                 kfree(vma_private);
2004         }
2005         mutex_unlock(&context->vma_private_list_mutex);
2006 }
2007
2008 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2009 {
2010         switch (cmd) {
2011         case MLX5_IB_MMAP_WC_PAGE:
2012                 return "WC";
2013         case MLX5_IB_MMAP_REGULAR_PAGE:
2014                 return "best effort WC";
2015         case MLX5_IB_MMAP_NC_PAGE:
2016                 return "NC";
2017         case MLX5_IB_MMAP_DEVICE_MEM:
2018                 return "Device Memory";
2019         default:
2020                 return NULL;
2021         }
2022 }
2023
2024 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2025                                         struct vm_area_struct *vma,
2026                                         struct mlx5_ib_ucontext *context)
2027 {
2028         phys_addr_t pfn;
2029         int err;
2030
2031         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2032                 return -EINVAL;
2033
2034         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2035                 return -EOPNOTSUPP;
2036
2037         if (vma->vm_flags & VM_WRITE)
2038                 return -EPERM;
2039
2040         if (!dev->mdev->clock_info_page)
2041                 return -EOPNOTSUPP;
2042
2043         pfn = page_to_pfn(dev->mdev->clock_info_page);
2044         err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2045                               vma->vm_page_prot);
2046         if (err)
2047                 return err;
2048
2049         return mlx5_ib_set_vma_data(vma, context);
2050 }
2051
2052 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2053                     struct vm_area_struct *vma,
2054                     struct mlx5_ib_ucontext *context)
2055 {
2056         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2057         int err;
2058         unsigned long idx;
2059         phys_addr_t pfn, pa;
2060         pgprot_t prot;
2061         u32 bfreg_dyn_idx = 0;
2062         u32 uar_index;
2063         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2064         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2065                                 bfregi->num_static_sys_pages;
2066
2067         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2068                 return -EINVAL;
2069
2070         if (dyn_uar)
2071                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2072         else
2073                 idx = get_index(vma->vm_pgoff);
2074
2075         if (idx >= max_valid_idx) {
2076                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2077                              idx, max_valid_idx);
2078                 return -EINVAL;
2079         }
2080
2081         switch (cmd) {
2082         case MLX5_IB_MMAP_WC_PAGE:
2083         case MLX5_IB_MMAP_ALLOC_WC:
2084 /* Some architectures don't support WC memory */
2085 #if defined(CONFIG_X86)
2086                 if (!pat_enabled())
2087                         return -EPERM;
2088 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2089                         return -EPERM;
2090 #endif
2091         /* fall through */
2092         case MLX5_IB_MMAP_REGULAR_PAGE:
2093                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2094                 prot = pgprot_writecombine(vma->vm_page_prot);
2095                 break;
2096         case MLX5_IB_MMAP_NC_PAGE:
2097                 prot = pgprot_noncached(vma->vm_page_prot);
2098                 break;
2099         default:
2100                 return -EINVAL;
2101         }
2102
2103         if (dyn_uar) {
2104                 int uars_per_page;
2105
2106                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2107                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2108                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2109                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2110                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2111                         return -EINVAL;
2112                 }
2113
2114                 mutex_lock(&bfregi->lock);
2115                 /* Fail if uar already allocated, first bfreg index of each
2116                  * page holds its count.
2117                  */
2118                 if (bfregi->count[bfreg_dyn_idx]) {
2119                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2120                         mutex_unlock(&bfregi->lock);
2121                         return -EINVAL;
2122                 }
2123
2124                 bfregi->count[bfreg_dyn_idx]++;
2125                 mutex_unlock(&bfregi->lock);
2126
2127                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2128                 if (err) {
2129                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2130                         goto free_bfreg;
2131                 }
2132         } else {
2133                 uar_index = bfregi->sys_pages[idx];
2134         }
2135
2136         pfn = uar_index2pfn(dev, uar_index);
2137         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2138
2139         vma->vm_page_prot = prot;
2140         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2141                                  PAGE_SIZE, vma->vm_page_prot);
2142         if (err) {
2143                 mlx5_ib_err(dev,
2144                             "io_remap_pfn_range failed with error=%d, mmap_cmd=%s\n",
2145                             err, mmap_cmd2str(cmd));
2146                 err = -EAGAIN;
2147                 goto err;
2148         }
2149
2150         pa = pfn << PAGE_SHIFT;
2151
2152         err = mlx5_ib_set_vma_data(vma, context);
2153         if (err)
2154                 goto err;
2155
2156         if (dyn_uar)
2157                 bfregi->sys_pages[idx] = uar_index;
2158         return 0;
2159
2160 err:
2161         if (!dyn_uar)
2162                 return err;
2163
2164         mlx5_cmd_free_uar(dev->mdev, idx);
2165
2166 free_bfreg:
2167         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2168
2169         return err;
2170 }
2171
2172 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2173 {
2174         struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2175         struct mlx5_ib_dev *dev = to_mdev(context->device);
2176         u16 page_idx = get_extended_index(vma->vm_pgoff);
2177         size_t map_size = vma->vm_end - vma->vm_start;
2178         u32 npages = map_size >> PAGE_SHIFT;
2179         phys_addr_t pfn;
2180         pgprot_t prot;
2181
2182         if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2183             page_idx + npages)
2184                 return -EINVAL;
2185
2186         pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2187               MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2188               PAGE_SHIFT) +
2189               page_idx;
2190         prot = pgprot_writecombine(vma->vm_page_prot);
2191         vma->vm_page_prot = prot;
2192
2193         if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2194                                vma->vm_page_prot))
2195                 return -EAGAIN;
2196
2197         return mlx5_ib_set_vma_data(vma, mctx);
2198 }
2199
2200 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2201 {
2202         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2203         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2204         unsigned long command;
2205         phys_addr_t pfn;
2206
2207         command = get_command(vma->vm_pgoff);
2208         switch (command) {
2209         case MLX5_IB_MMAP_WC_PAGE:
2210         case MLX5_IB_MMAP_NC_PAGE:
2211         case MLX5_IB_MMAP_REGULAR_PAGE:
2212         case MLX5_IB_MMAP_ALLOC_WC:
2213                 return uar_mmap(dev, command, vma, context);
2214
2215         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2216                 return -ENOSYS;
2217
2218         case MLX5_IB_MMAP_CORE_CLOCK:
2219                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2220                         return -EINVAL;
2221
2222                 if (vma->vm_flags & VM_WRITE)
2223                         return -EPERM;
2224
2225                 /* Don't expose to user-space information it shouldn't have */
2226                 if (PAGE_SIZE > 4096)
2227                         return -EOPNOTSUPP;
2228
2229                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2230                 pfn = (dev->mdev->iseg_base +
2231                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2232                         PAGE_SHIFT;
2233                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2234                                        PAGE_SIZE, vma->vm_page_prot))
2235                         return -EAGAIN;
2236                 break;
2237         case MLX5_IB_MMAP_CLOCK_INFO:
2238                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2239
2240         case MLX5_IB_MMAP_DEVICE_MEM:
2241                 return dm_mmap(ibcontext, vma);
2242
2243         default:
2244                 return -EINVAL;
2245         }
2246
2247         return 0;
2248 }
2249
2250 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2251                                struct ib_ucontext *context,
2252                                struct ib_dm_alloc_attr *attr,
2253                                struct uverbs_attr_bundle *attrs)
2254 {
2255         u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2256         struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2257         phys_addr_t memic_addr;
2258         struct mlx5_ib_dm *dm;
2259         u64 start_offset;
2260         u32 page_idx;
2261         int err;
2262
2263         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2264         if (!dm)
2265                 return ERR_PTR(-ENOMEM);
2266
2267         mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2268                     attr->length, act_size, attr->alignment);
2269
2270         err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2271                                    act_size, attr->alignment);
2272         if (err)
2273                 goto err_free;
2274
2275         start_offset = memic_addr & ~PAGE_MASK;
2276         page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2277                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2278                     PAGE_SHIFT;
2279
2280         err = uverbs_copy_to(attrs,
2281                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2282                              &start_offset, sizeof(start_offset));
2283         if (err)
2284                 goto err_dealloc;
2285
2286         err = uverbs_copy_to(attrs,
2287                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2288                              &page_idx, sizeof(page_idx));
2289         if (err)
2290                 goto err_dealloc;
2291
2292         bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2293                    DIV_ROUND_UP(act_size, PAGE_SIZE));
2294
2295         dm->dev_addr = memic_addr;
2296
2297         return &dm->ibdm;
2298
2299 err_dealloc:
2300         mlx5_cmd_dealloc_memic(memic, memic_addr,
2301                                act_size);
2302 err_free:
2303         kfree(dm);
2304         return ERR_PTR(err);
2305 }
2306
2307 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2308 {
2309         struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2310         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2311         u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2312         u32 page_idx;
2313         int ret;
2314
2315         ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2316         if (ret)
2317                 return ret;
2318
2319         page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2320                     MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2321                     PAGE_SHIFT;
2322         bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2323                      page_idx,
2324                      DIV_ROUND_UP(act_size, PAGE_SIZE));
2325
2326         kfree(dm);
2327
2328         return 0;
2329 }
2330
2331 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2332                                       struct ib_ucontext *context,
2333                                       struct ib_udata *udata)
2334 {
2335         struct mlx5_ib_alloc_pd_resp resp;
2336         struct mlx5_ib_pd *pd;
2337         int err;
2338
2339         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2340         if (!pd)
2341                 return ERR_PTR(-ENOMEM);
2342
2343         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2344         if (err) {
2345                 kfree(pd);
2346                 return ERR_PTR(err);
2347         }
2348
2349         if (context) {
2350                 resp.pdn = pd->pdn;
2351                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2352                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2353                         kfree(pd);
2354                         return ERR_PTR(-EFAULT);
2355                 }
2356         }
2357
2358         return &pd->ibpd;
2359 }
2360
2361 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2362 {
2363         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2364         struct mlx5_ib_pd *mpd = to_mpd(pd);
2365
2366         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2367         kfree(mpd);
2368
2369         return 0;
2370 }
2371
2372 enum {
2373         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2374         MATCH_CRITERIA_ENABLE_MISC_BIT,
2375         MATCH_CRITERIA_ENABLE_INNER_BIT,
2376         MATCH_CRITERIA_ENABLE_MISC2_BIT
2377 };
2378
2379 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2380         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2381                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2382
2383 static u8 get_match_criteria_enable(u32 *match_criteria)
2384 {
2385         u8 match_criteria_enable;
2386
2387         match_criteria_enable =
2388                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2389                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2390         match_criteria_enable |=
2391                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2392                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2393         match_criteria_enable |=
2394                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2395                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2396         match_criteria_enable |=
2397                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2398                 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2399
2400         return match_criteria_enable;
2401 }
2402
2403 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2404 {
2405         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2406         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2407 }
2408
2409 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2410                            bool inner)
2411 {
2412         if (inner) {
2413                 MLX5_SET(fte_match_set_misc,
2414                          misc_c, inner_ipv6_flow_label, mask);
2415                 MLX5_SET(fte_match_set_misc,
2416                          misc_v, inner_ipv6_flow_label, val);
2417         } else {
2418                 MLX5_SET(fte_match_set_misc,
2419                          misc_c, outer_ipv6_flow_label, mask);
2420                 MLX5_SET(fte_match_set_misc,
2421                          misc_v, outer_ipv6_flow_label, val);
2422         }
2423 }
2424
2425 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2426 {
2427         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2428         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2429         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2430         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2431 }
2432
2433 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2434 {
2435         if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2436             !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2437                 return -EOPNOTSUPP;
2438
2439         if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2440             !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2441                 return -EOPNOTSUPP;
2442
2443         if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2444             !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2445                 return -EOPNOTSUPP;
2446
2447         if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2448             !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2449                 return -EOPNOTSUPP;
2450
2451         return 0;
2452 }
2453
2454 #define LAST_ETH_FIELD vlan_tag
2455 #define LAST_IB_FIELD sl
2456 #define LAST_IPV4_FIELD tos
2457 #define LAST_IPV6_FIELD traffic_class
2458 #define LAST_TCP_UDP_FIELD src_port
2459 #define LAST_TUNNEL_FIELD tunnel_id
2460 #define LAST_FLOW_TAG_FIELD tag_id
2461 #define LAST_DROP_FIELD size
2462 #define LAST_COUNTERS_FIELD counters
2463
2464 /* Field is the last supported field */
2465 #define FIELDS_NOT_SUPPORTED(filter, field)\
2466         memchr_inv((void *)&filter.field  +\
2467                    sizeof(filter.field), 0,\
2468                    sizeof(filter) -\
2469                    offsetof(typeof(filter), field) -\
2470                    sizeof(filter.field))
2471
2472 static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2473                                   const struct ib_flow_attr *flow_attr,
2474                                   struct mlx5_flow_act *action)
2475 {
2476         struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2477
2478         switch (maction->ib_action.type) {
2479         case IB_FLOW_ACTION_ESP:
2480                 /* Currently only AES_GCM keymat is supported by the driver */
2481                 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2482                 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2483                         MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2484                         MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2485                 return 0;
2486         default:
2487                 return -EOPNOTSUPP;
2488         }
2489 }
2490
2491 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2492                            u32 *match_v, const union ib_flow_spec *ib_spec,
2493                            const struct ib_flow_attr *flow_attr,
2494                            struct mlx5_flow_act *action, u32 prev_type)
2495 {
2496         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2497                                            misc_parameters);
2498         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2499                                            misc_parameters);
2500         void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2501                                             misc_parameters_2);
2502         void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2503                                             misc_parameters_2);
2504         void *headers_c;
2505         void *headers_v;
2506         int match_ipv;
2507         int ret;
2508
2509         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2510                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2511                                          inner_headers);
2512                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2513                                          inner_headers);
2514                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2515                                         ft_field_support.inner_ip_version);
2516         } else {
2517                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2518                                          outer_headers);
2519                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2520                                          outer_headers);
2521                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2522                                         ft_field_support.outer_ip_version);
2523         }
2524
2525         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2526         case IB_FLOW_SPEC_ETH:
2527                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2528                         return -EOPNOTSUPP;
2529
2530                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2531                                              dmac_47_16),
2532                                 ib_spec->eth.mask.dst_mac);
2533                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2534                                              dmac_47_16),
2535                                 ib_spec->eth.val.dst_mac);
2536
2537                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2538                                              smac_47_16),
2539                                 ib_spec->eth.mask.src_mac);
2540                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2541                                              smac_47_16),
2542                                 ib_spec->eth.val.src_mac);
2543
2544                 if (ib_spec->eth.mask.vlan_tag) {
2545                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2546                                  cvlan_tag, 1);
2547                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2548                                  cvlan_tag, 1);
2549
2550                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2551                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2552                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2553                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2554
2555                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2556                                  first_cfi,
2557                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2558                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2559                                  first_cfi,
2560                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2561
2562                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2563                                  first_prio,
2564                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2565                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2566                                  first_prio,
2567                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2568                 }
2569                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2570                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2571                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2572                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2573                 break;
2574         case IB_FLOW_SPEC_IPV4:
2575                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2576                         return -EOPNOTSUPP;
2577
2578                 if (match_ipv) {
2579                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2580                                  ip_version, 0xf);
2581                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2582                                  ip_version, MLX5_FS_IPV4_VERSION);
2583                 } else {
2584                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2585                                  ethertype, 0xffff);
2586                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2587                                  ethertype, ETH_P_IP);
2588                 }
2589
2590                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2591                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2592                        &ib_spec->ipv4.mask.src_ip,
2593                        sizeof(ib_spec->ipv4.mask.src_ip));
2594                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2595                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2596                        &ib_spec->ipv4.val.src_ip,
2597                        sizeof(ib_spec->ipv4.val.src_ip));
2598                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2599                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2600                        &ib_spec->ipv4.mask.dst_ip,
2601                        sizeof(ib_spec->ipv4.mask.dst_ip));
2602                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2603                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2604                        &ib_spec->ipv4.val.dst_ip,
2605                        sizeof(ib_spec->ipv4.val.dst_ip));
2606
2607                 set_tos(headers_c, headers_v,
2608                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2609
2610                 set_proto(headers_c, headers_v,
2611                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2612                 break;
2613         case IB_FLOW_SPEC_IPV6:
2614                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2615                         return -EOPNOTSUPP;
2616
2617                 if (match_ipv) {
2618                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2619                                  ip_version, 0xf);
2620                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2621                                  ip_version, MLX5_FS_IPV6_VERSION);
2622                 } else {
2623                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2624                                  ethertype, 0xffff);
2625                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2626                                  ethertype, ETH_P_IPV6);
2627                 }
2628
2629                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2630                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2631                        &ib_spec->ipv6.mask.src_ip,
2632                        sizeof(ib_spec->ipv6.mask.src_ip));
2633                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2634                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2635                        &ib_spec->ipv6.val.src_ip,
2636                        sizeof(ib_spec->ipv6.val.src_ip));
2637                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2638                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2639                        &ib_spec->ipv6.mask.dst_ip,
2640                        sizeof(ib_spec->ipv6.mask.dst_ip));
2641                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2642                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2643                        &ib_spec->ipv6.val.dst_ip,
2644                        sizeof(ib_spec->ipv6.val.dst_ip));
2645
2646                 set_tos(headers_c, headers_v,
2647                         ib_spec->ipv6.mask.traffic_class,
2648                         ib_spec->ipv6.val.traffic_class);
2649
2650                 set_proto(headers_c, headers_v,
2651                           ib_spec->ipv6.mask.next_hdr,
2652                           ib_spec->ipv6.val.next_hdr);
2653
2654                 set_flow_label(misc_params_c, misc_params_v,
2655                                ntohl(ib_spec->ipv6.mask.flow_label),
2656                                ntohl(ib_spec->ipv6.val.flow_label),
2657                                ib_spec->type & IB_FLOW_SPEC_INNER);
2658                 break;
2659         case IB_FLOW_SPEC_ESP:
2660                 if (ib_spec->esp.mask.seq)
2661                         return -EOPNOTSUPP;
2662
2663                 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2664                          ntohl(ib_spec->esp.mask.spi));
2665                 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2666                          ntohl(ib_spec->esp.val.spi));
2667                 break;
2668         case IB_FLOW_SPEC_TCP:
2669                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2670                                          LAST_TCP_UDP_FIELD))
2671                         return -EOPNOTSUPP;
2672
2673                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2674                          0xff);
2675                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2676                          IPPROTO_TCP);
2677
2678                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2679                          ntohs(ib_spec->tcp_udp.mask.src_port));
2680                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2681                          ntohs(ib_spec->tcp_udp.val.src_port));
2682
2683                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2684                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2685                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2686                          ntohs(ib_spec->tcp_udp.val.dst_port));
2687                 break;
2688         case IB_FLOW_SPEC_UDP:
2689                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2690                                          LAST_TCP_UDP_FIELD))
2691                         return -EOPNOTSUPP;
2692
2693                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2694                          0xff);
2695                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2696                          IPPROTO_UDP);
2697
2698                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2699                          ntohs(ib_spec->tcp_udp.mask.src_port));
2700                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2701                          ntohs(ib_spec->tcp_udp.val.src_port));
2702
2703                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2704                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2705                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2706                          ntohs(ib_spec->tcp_udp.val.dst_port));
2707                 break;
2708         case IB_FLOW_SPEC_GRE:
2709                 if (ib_spec->gre.mask.c_ks_res0_ver)
2710                         return -EOPNOTSUPP;
2711
2712                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2713                          0xff);
2714                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2715                          IPPROTO_GRE);
2716
2717                 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2718                          0xffff);
2719                 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2720                          ntohs(ib_spec->gre.val.protocol));
2721
2722                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2723                                     gre_key_h),
2724                        &ib_spec->gre.mask.key,
2725                        sizeof(ib_spec->gre.mask.key));
2726                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2727                                     gre_key_h),
2728                        &ib_spec->gre.val.key,
2729                        sizeof(ib_spec->gre.val.key));
2730                 break;
2731         case IB_FLOW_SPEC_MPLS:
2732                 switch (prev_type) {
2733                 case IB_FLOW_SPEC_UDP:
2734                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2735                                                    ft_field_support.outer_first_mpls_over_udp),
2736                                                    &ib_spec->mpls.mask.tag))
2737                                 return -EOPNOTSUPP;
2738
2739                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2740                                             outer_first_mpls_over_udp),
2741                                &ib_spec->mpls.val.tag,
2742                                sizeof(ib_spec->mpls.val.tag));
2743                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2744                                             outer_first_mpls_over_udp),
2745                                &ib_spec->mpls.mask.tag,
2746                                sizeof(ib_spec->mpls.mask.tag));
2747                         break;
2748                 case IB_FLOW_SPEC_GRE:
2749                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2750                                                    ft_field_support.outer_first_mpls_over_gre),
2751                                                    &ib_spec->mpls.mask.tag))
2752                                 return -EOPNOTSUPP;
2753
2754                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2755                                             outer_first_mpls_over_gre),
2756                                &ib_spec->mpls.val.tag,
2757                                sizeof(ib_spec->mpls.val.tag));
2758                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2759                                             outer_first_mpls_over_gre),
2760                                &ib_spec->mpls.mask.tag,
2761                                sizeof(ib_spec->mpls.mask.tag));
2762                         break;
2763                 default:
2764                         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2765                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2766                                                            ft_field_support.inner_first_mpls),
2767                                                            &ib_spec->mpls.mask.tag))
2768                                         return -EOPNOTSUPP;
2769
2770                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2771                                                     inner_first_mpls),
2772                                        &ib_spec->mpls.val.tag,
2773                                        sizeof(ib_spec->mpls.val.tag));
2774                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2775                                                     inner_first_mpls),
2776                                        &ib_spec->mpls.mask.tag,
2777                                        sizeof(ib_spec->mpls.mask.tag));
2778                         } else {
2779                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2780                                                            ft_field_support.outer_first_mpls),
2781                                                            &ib_spec->mpls.mask.tag))
2782                                         return -EOPNOTSUPP;
2783
2784                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2785                                                     outer_first_mpls),
2786                                        &ib_spec->mpls.val.tag,
2787                                        sizeof(ib_spec->mpls.val.tag));
2788                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2789                                                     outer_first_mpls),
2790                                        &ib_spec->mpls.mask.tag,
2791                                        sizeof(ib_spec->mpls.mask.tag));
2792                         }
2793                 }
2794                 break;
2795         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2796                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2797                                          LAST_TUNNEL_FIELD))
2798                         return -EOPNOTSUPP;
2799
2800                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2801                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2802                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2803                          ntohl(ib_spec->tunnel.val.tunnel_id));
2804                 break;
2805         case IB_FLOW_SPEC_ACTION_TAG:
2806                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2807                                          LAST_FLOW_TAG_FIELD))
2808                         return -EOPNOTSUPP;
2809                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2810                         return -EINVAL;
2811
2812                 action->flow_tag = ib_spec->flow_tag.tag_id;
2813                 action->has_flow_tag = true;
2814                 break;
2815         case IB_FLOW_SPEC_ACTION_DROP:
2816                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2817                                          LAST_DROP_FIELD))
2818                         return -EOPNOTSUPP;
2819                 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2820                 break;
2821         case IB_FLOW_SPEC_ACTION_HANDLE:
2822                 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2823                 if (ret)
2824                         return ret;
2825                 break;
2826         case IB_FLOW_SPEC_ACTION_COUNT:
2827                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2828                                          LAST_COUNTERS_FIELD))
2829                         return -EOPNOTSUPP;
2830
2831                 /* for now support only one counters spec per flow */
2832                 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2833                         return -EINVAL;
2834
2835                 action->counters = ib_spec->flow_count.counters;
2836                 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2837                 break;
2838         default:
2839                 return -EINVAL;
2840         }
2841
2842         return 0;
2843 }
2844
2845 /* If a flow could catch both multicast and unicast packets,
2846  * it won't fall into the multicast flow steering table and this rule
2847  * could steal other multicast packets.
2848  */
2849 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2850 {
2851         union ib_flow_spec *flow_spec;
2852
2853         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2854             ib_attr->num_of_specs < 1)
2855                 return false;
2856
2857         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2858         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2859                 struct ib_flow_spec_ipv4 *ipv4_spec;
2860
2861                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2862                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2863                         return true;
2864
2865                 return false;
2866         }
2867
2868         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2869                 struct ib_flow_spec_eth *eth_spec;
2870
2871                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2872                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2873                        is_multicast_ether_addr(eth_spec->val.dst_mac);
2874         }
2875
2876         return false;
2877 }
2878
2879 enum valid_spec {
2880         VALID_SPEC_INVALID,
2881         VALID_SPEC_VALID,
2882         VALID_SPEC_NA,
2883 };
2884
2885 static enum valid_spec
2886 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2887                      const struct mlx5_flow_spec *spec,
2888                      const struct mlx5_flow_act *flow_act,
2889                      bool egress)
2890 {
2891         const u32 *match_c = spec->match_criteria;
2892         bool is_crypto =
2893                 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2894                                      MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2895         bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2896         bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2897
2898         /*
2899          * Currently only crypto is supported in egress, when regular egress
2900          * rules would be supported, always return VALID_SPEC_NA.
2901          */
2902         if (!is_crypto)
2903                 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2904
2905         return is_crypto && is_ipsec &&
2906                 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2907                 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2908 }
2909
2910 static bool is_valid_spec(struct mlx5_core_dev *mdev,
2911                           const struct mlx5_flow_spec *spec,
2912                           const struct mlx5_flow_act *flow_act,
2913                           bool egress)
2914 {
2915         /* We curretly only support ipsec egress flow */
2916         return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2917 }
2918
2919 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2920                                const struct ib_flow_attr *flow_attr,
2921                                bool check_inner)
2922 {
2923         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2924         int match_ipv = check_inner ?
2925                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2926                                         ft_field_support.inner_ip_version) :
2927                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2928                                         ft_field_support.outer_ip_version);
2929         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2930         bool ipv4_spec_valid, ipv6_spec_valid;
2931         unsigned int ip_spec_type = 0;
2932         bool has_ethertype = false;
2933         unsigned int spec_index;
2934         bool mask_valid = true;
2935         u16 eth_type = 0;
2936         bool type_valid;
2937
2938         /* Validate that ethertype is correct */
2939         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2940                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2941                     ib_spec->eth.mask.ether_type) {
2942                         mask_valid = (ib_spec->eth.mask.ether_type ==
2943                                       htons(0xffff));
2944                         has_ethertype = true;
2945                         eth_type = ntohs(ib_spec->eth.val.ether_type);
2946                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2947                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2948                         ip_spec_type = ib_spec->type;
2949                 }
2950                 ib_spec = (void *)ib_spec + ib_spec->size;
2951         }
2952
2953         type_valid = (!has_ethertype) || (!ip_spec_type);
2954         if (!type_valid && mask_valid) {
2955                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2956                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2957                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2958                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2959
2960                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2961                              (((eth_type == ETH_P_MPLS_UC) ||
2962                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2963         }
2964
2965         return type_valid;
2966 }
2967
2968 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2969                           const struct ib_flow_attr *flow_attr)
2970 {
2971         return is_valid_ethertype(mdev, flow_attr, false) &&
2972                is_valid_ethertype(mdev, flow_attr, true);
2973 }
2974
2975 static void put_flow_table(struct mlx5_ib_dev *dev,
2976                            struct mlx5_ib_flow_prio *prio, bool ft_added)
2977 {
2978         prio->refcount -= !!ft_added;
2979         if (!prio->refcount) {
2980                 mlx5_destroy_flow_table(prio->flow_table);
2981                 prio->flow_table = NULL;
2982         }
2983 }
2984
2985 static void counters_clear_description(struct ib_counters *counters)
2986 {
2987         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2988
2989         mutex_lock(&mcounters->mcntrs_mutex);
2990         kfree(mcounters->counters_data);
2991         mcounters->counters_data = NULL;
2992         mcounters->cntrs_max_index = 0;
2993         mutex_unlock(&mcounters->mcntrs_mutex);
2994 }
2995
2996 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2997 {
2998         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2999         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3000                                                           struct mlx5_ib_flow_handler,
3001                                                           ibflow);
3002         struct mlx5_ib_flow_handler *iter, *tmp;
3003
3004         mutex_lock(&dev->flow_db->lock);
3005
3006         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
3007                 mlx5_del_flow_rules(iter->rule);
3008                 put_flow_table(dev, iter->prio, true);
3009                 list_del(&iter->list);
3010                 kfree(iter);
3011         }
3012
3013         mlx5_del_flow_rules(handler->rule);
3014         put_flow_table(dev, handler->prio, true);
3015         if (handler->ibcounters &&
3016             atomic_read(&handler->ibcounters->usecnt) == 1)
3017                 counters_clear_description(handler->ibcounters);
3018
3019         mutex_unlock(&dev->flow_db->lock);
3020         kfree(handler);
3021
3022         return 0;
3023 }
3024
3025 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3026 {
3027         priority *= 2;
3028         if (!dont_trap)
3029                 priority++;
3030         return priority;
3031 }
3032
3033 enum flow_table_type {
3034         MLX5_IB_FT_RX,
3035         MLX5_IB_FT_TX
3036 };
3037
3038 #define MLX5_FS_MAX_TYPES        6
3039 #define MLX5_FS_MAX_ENTRIES      BIT(16)
3040 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3041                                                 struct ib_flow_attr *flow_attr,
3042                                                 enum flow_table_type ft_type)
3043 {
3044         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3045         struct mlx5_flow_namespace *ns = NULL;
3046         struct mlx5_ib_flow_prio *prio;
3047         struct mlx5_flow_table *ft;
3048         int max_table_size;
3049         int num_entries;
3050         int num_groups;
3051         int priority;
3052         int err = 0;
3053
3054         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3055                                                        log_max_ft_size));
3056         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3057                 if (ft_type == MLX5_IB_FT_TX)
3058                         priority = 0;
3059                 else if (flow_is_multicast_only(flow_attr) &&
3060                          !dont_trap)
3061                         priority = MLX5_IB_FLOW_MCAST_PRIO;
3062                 else
3063                         priority = ib_prio_to_core_prio(flow_attr->priority,
3064                                                         dont_trap);
3065                 ns = mlx5_get_flow_namespace(dev->mdev,
3066                                              ft_type == MLX5_IB_FT_TX ?
3067                                              MLX5_FLOW_NAMESPACE_EGRESS :
3068                                              MLX5_FLOW_NAMESPACE_BYPASS);
3069                 num_entries = MLX5_FS_MAX_ENTRIES;
3070                 num_groups = MLX5_FS_MAX_TYPES;
3071                 prio = &dev->flow_db->prios[priority];
3072         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3073                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3074                 ns = mlx5_get_flow_namespace(dev->mdev,
3075                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
3076                 build_leftovers_ft_param(&priority,
3077                                          &num_entries,
3078                                          &num_groups);
3079                 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3080         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3081                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3082                                         allow_sniffer_and_nic_rx_shared_tir))
3083                         return ERR_PTR(-ENOTSUPP);
3084
3085                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3086                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3087                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3088
3089                 prio = &dev->flow_db->sniffer[ft_type];
3090                 priority = 0;
3091                 num_entries = 1;
3092                 num_groups = 1;
3093         }
3094
3095         if (!ns)
3096                 return ERR_PTR(-ENOTSUPP);
3097
3098         if (num_entries > max_table_size)
3099                 return ERR_PTR(-ENOMEM);
3100
3101         ft = prio->flow_table;
3102         if (!ft) {
3103                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3104                                                          num_entries,
3105                                                          num_groups,
3106                                                          0, 0);
3107
3108                 if (!IS_ERR(ft)) {
3109                         prio->refcount = 0;
3110                         prio->flow_table = ft;
3111                 } else {
3112                         err = PTR_ERR(ft);
3113                 }
3114         }
3115
3116         return err ? ERR_PTR(err) : prio;
3117 }
3118
3119 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3120                             struct mlx5_flow_spec *spec,
3121                             u32 underlay_qpn)
3122 {
3123         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3124                                            spec->match_criteria,
3125                                            misc_parameters);
3126         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3127                                            misc_parameters);
3128
3129         if (underlay_qpn &&
3130             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3131                                       ft_field_support.bth_dst_qp)) {
3132                 MLX5_SET(fte_match_set_misc,
3133                          misc_params_v, bth_dst_qp, underlay_qpn);
3134                 MLX5_SET(fte_match_set_misc,
3135                          misc_params_c, bth_dst_qp, 0xffffff);
3136         }
3137 }
3138
3139 static int read_flow_counters(struct ib_device *ibdev,
3140                               struct mlx5_read_counters_attr *read_attr)
3141 {
3142         struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3143         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3144
3145         return mlx5_fc_query(dev->mdev, fc,
3146                              &read_attr->out[IB_COUNTER_PACKETS],
3147                              &read_attr->out[IB_COUNTER_BYTES]);
3148 }
3149
3150 /* flow counters currently expose two counters packets and bytes */
3151 #define FLOW_COUNTERS_NUM 2
3152 static int counters_set_description(struct ib_counters *counters,
3153                                     enum mlx5_ib_counters_type counters_type,
3154                                     struct mlx5_ib_flow_counters_desc *desc_data,
3155                                     u32 ncounters)
3156 {
3157         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3158         u32 cntrs_max_index = 0;
3159         int i;
3160
3161         if (counters_type != MLX5_IB_COUNTERS_FLOW)
3162                 return -EINVAL;
3163
3164         /* init the fields for the object */
3165         mcounters->type = counters_type;
3166         mcounters->read_counters = read_flow_counters;
3167         mcounters->counters_num = FLOW_COUNTERS_NUM;
3168         mcounters->ncounters = ncounters;
3169         /* each counter entry have both description and index pair */
3170         for (i = 0; i < ncounters; i++) {
3171                 if (desc_data[i].description > IB_COUNTER_BYTES)
3172                         return -EINVAL;
3173
3174                 if (cntrs_max_index <= desc_data[i].index)
3175                         cntrs_max_index = desc_data[i].index + 1;
3176         }
3177
3178         mutex_lock(&mcounters->mcntrs_mutex);
3179         mcounters->counters_data = desc_data;
3180         mcounters->cntrs_max_index = cntrs_max_index;
3181         mutex_unlock(&mcounters->mcntrs_mutex);
3182
3183         return 0;
3184 }
3185
3186 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3187 static int flow_counters_set_data(struct ib_counters *ibcounters,
3188                                   struct mlx5_ib_create_flow *ucmd)
3189 {
3190         struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3191         struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3192         struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3193         bool hw_hndl = false;
3194         int ret = 0;
3195
3196         if (ucmd && ucmd->ncounters_data != 0) {
3197                 cntrs_data = ucmd->data;
3198                 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3199                         return -EINVAL;
3200
3201                 desc_data = kcalloc(cntrs_data->ncounters,
3202                                     sizeof(*desc_data),
3203                                     GFP_KERNEL);
3204                 if (!desc_data)
3205                         return  -ENOMEM;
3206
3207                 if (copy_from_user(desc_data,
3208                                    u64_to_user_ptr(cntrs_data->counters_data),
3209                                    sizeof(*desc_data) * cntrs_data->ncounters)) {
3210                         ret = -EFAULT;
3211                         goto free;
3212                 }
3213         }
3214
3215         if (!mcounters->hw_cntrs_hndl) {
3216                 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3217                         to_mdev(ibcounters->device)->mdev, false);
3218                 if (!mcounters->hw_cntrs_hndl) {
3219                         ret = -ENOMEM;
3220                         goto free;
3221                 }
3222                 hw_hndl = true;
3223         }
3224
3225         if (desc_data) {
3226                 /* counters already bound to at least one flow */
3227                 if (mcounters->cntrs_max_index) {
3228                         ret = -EINVAL;
3229                         goto free_hndl;
3230                 }
3231
3232                 ret = counters_set_description(ibcounters,
3233                                                MLX5_IB_COUNTERS_FLOW,
3234                                                desc_data,
3235                                                cntrs_data->ncounters);
3236                 if (ret)
3237                         goto free_hndl;
3238
3239         } else if (!mcounters->cntrs_max_index) {
3240                 /* counters not bound yet, must have udata passed */
3241                 ret = -EINVAL;
3242                 goto free_hndl;
3243         }
3244
3245         return 0;
3246
3247 free_hndl:
3248         if (hw_hndl) {
3249                 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3250                                 mcounters->hw_cntrs_hndl);
3251                 mcounters->hw_cntrs_hndl = NULL;
3252         }
3253 free:
3254         kfree(desc_data);
3255         return ret;
3256 }
3257
3258 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3259                                                       struct mlx5_ib_flow_prio *ft_prio,
3260                                                       const struct ib_flow_attr *flow_attr,
3261                                                       struct mlx5_flow_destination *dst,
3262                                                       u32 underlay_qpn,
3263                                                       struct mlx5_ib_create_flow *ucmd)
3264 {
3265         struct mlx5_flow_table  *ft = ft_prio->flow_table;
3266         struct mlx5_ib_flow_handler *handler;
3267         struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3268         struct mlx5_flow_spec *spec;
3269         struct mlx5_flow_destination dest_arr[2] = {};
3270         struct mlx5_flow_destination *rule_dst = dest_arr;
3271         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3272         unsigned int spec_index;
3273         u32 prev_type = 0;
3274         int err = 0;
3275         int dest_num = 0;
3276         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3277
3278         if (!is_valid_attr(dev->mdev, flow_attr))
3279                 return ERR_PTR(-EINVAL);
3280
3281         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3282         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3283         if (!handler || !spec) {
3284                 err = -ENOMEM;
3285                 goto free;
3286         }
3287
3288         INIT_LIST_HEAD(&handler->list);
3289         if (dst) {
3290                 memcpy(&dest_arr[0], dst, sizeof(*dst));
3291                 dest_num++;
3292         }
3293
3294         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3295                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3296                                       spec->match_value,
3297                                       ib_flow, flow_attr, &flow_act,
3298                                       prev_type);
3299                 if (err < 0)
3300                         goto free;
3301
3302                 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3303                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3304         }
3305
3306         if (!flow_is_multicast_only(flow_attr))
3307                 set_underlay_qp(dev, spec, underlay_qpn);
3308
3309         if (dev->rep) {
3310                 void *misc;
3311
3312                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3313                                     misc_parameters);
3314                 MLX5_SET(fte_match_set_misc, misc, source_port,
3315                          dev->rep->vport);
3316                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3317                                     misc_parameters);
3318                 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3319         }
3320
3321         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3322
3323         if (is_egress &&
3324             !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3325                 err = -EINVAL;
3326                 goto free;
3327         }
3328
3329         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3330                 err = flow_counters_set_data(flow_act.counters, ucmd);
3331                 if (err)
3332                         goto free;
3333
3334                 handler->ibcounters = flow_act.counters;
3335                 dest_arr[dest_num].type =
3336                         MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3337                 dest_arr[dest_num].counter =
3338                         to_mcounters(flow_act.counters)->hw_cntrs_hndl;
3339                 dest_num++;
3340         }
3341
3342         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3343                 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3344                         rule_dst = NULL;
3345                         dest_num = 0;
3346                 }
3347         } else {
3348                 if (is_egress)
3349                         flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3350                 else
3351                         flow_act.action |=
3352                                 dest_num ?  MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3353                                         MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3354         }
3355
3356         if (flow_act.has_flow_tag &&
3357             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3358              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3359                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3360                              flow_act.flow_tag, flow_attr->type);
3361                 err = -EINVAL;
3362                 goto free;
3363         }
3364         handler->rule = mlx5_add_flow_rules(ft, spec,
3365                                             &flow_act,
3366                                             rule_dst, dest_num);
3367
3368         if (IS_ERR(handler->rule)) {
3369                 err = PTR_ERR(handler->rule);
3370                 goto free;
3371         }
3372
3373         ft_prio->refcount++;
3374         handler->prio = ft_prio;
3375
3376         ft_prio->flow_table = ft;
3377 free:
3378         if (err && handler) {
3379                 if (handler->ibcounters &&
3380                     atomic_read(&handler->ibcounters->usecnt) == 1)
3381                         counters_clear_description(handler->ibcounters);
3382                 kfree(handler);
3383         }
3384         kvfree(spec);
3385         return err ? ERR_PTR(err) : handler;
3386 }
3387
3388 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3389                                                      struct mlx5_ib_flow_prio *ft_prio,
3390                                                      const struct ib_flow_attr *flow_attr,
3391                                                      struct mlx5_flow_destination *dst)
3392 {
3393         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3394 }
3395
3396 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3397                                                           struct mlx5_ib_flow_prio *ft_prio,
3398                                                           struct ib_flow_attr *flow_attr,
3399                                                           struct mlx5_flow_destination *dst)
3400 {
3401         struct mlx5_ib_flow_handler *handler_dst = NULL;
3402         struct mlx5_ib_flow_handler *handler = NULL;
3403
3404         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3405         if (!IS_ERR(handler)) {
3406                 handler_dst = create_flow_rule(dev, ft_prio,
3407                                                flow_attr, dst);
3408                 if (IS_ERR(handler_dst)) {
3409                         mlx5_del_flow_rules(handler->rule);
3410                         ft_prio->refcount--;
3411                         kfree(handler);
3412                         handler = handler_dst;
3413                 } else {
3414                         list_add(&handler_dst->list, &handler->list);
3415                 }
3416         }
3417
3418         return handler;
3419 }
3420 enum {
3421         LEFTOVERS_MC,
3422         LEFTOVERS_UC,
3423 };
3424
3425 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3426                                                           struct mlx5_ib_flow_prio *ft_prio,
3427                                                           struct ib_flow_attr *flow_attr,
3428                                                           struct mlx5_flow_destination *dst)
3429 {
3430         struct mlx5_ib_flow_handler *handler_ucast = NULL;
3431         struct mlx5_ib_flow_handler *handler = NULL;
3432
3433         static struct {
3434                 struct ib_flow_attr     flow_attr;
3435                 struct ib_flow_spec_eth eth_flow;
3436         } leftovers_specs[] = {
3437                 [LEFTOVERS_MC] = {
3438                         .flow_attr = {
3439                                 .num_of_specs = 1,
3440                                 .size = sizeof(leftovers_specs[0])
3441                         },
3442                         .eth_flow = {
3443                                 .type = IB_FLOW_SPEC_ETH,
3444                                 .size = sizeof(struct ib_flow_spec_eth),
3445                                 .mask = {.dst_mac = {0x1} },
3446                                 .val =  {.dst_mac = {0x1} }
3447                         }
3448                 },
3449                 [LEFTOVERS_UC] = {
3450                         .flow_attr = {
3451                                 .num_of_specs = 1,
3452                                 .size = sizeof(leftovers_specs[0])
3453                         },
3454                         .eth_flow = {
3455                                 .type = IB_FLOW_SPEC_ETH,
3456                                 .size = sizeof(struct ib_flow_spec_eth),
3457                                 .mask = {.dst_mac = {0x1} },
3458                                 .val = {.dst_mac = {} }
3459                         }
3460                 }
3461         };
3462
3463         handler = create_flow_rule(dev, ft_prio,
3464                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
3465                                    dst);
3466         if (!IS_ERR(handler) &&
3467             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3468                 handler_ucast = create_flow_rule(dev, ft_prio,
3469                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
3470                                                  dst);
3471                 if (IS_ERR(handler_ucast)) {
3472                         mlx5_del_flow_rules(handler->rule);
3473                         ft_prio->refcount--;
3474                         kfree(handler);
3475                         handler = handler_ucast;
3476                 } else {
3477                         list_add(&handler_ucast->list, &handler->list);
3478                 }
3479         }
3480
3481         return handler;
3482 }
3483
3484 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3485                                                         struct mlx5_ib_flow_prio *ft_rx,
3486                                                         struct mlx5_ib_flow_prio *ft_tx,
3487                                                         struct mlx5_flow_destination *dst)
3488 {
3489         struct mlx5_ib_flow_handler *handler_rx;
3490         struct mlx5_ib_flow_handler *handler_tx;
3491         int err;
3492         static const struct ib_flow_attr flow_attr  = {
3493                 .num_of_specs = 0,
3494                 .size = sizeof(flow_attr)
3495         };
3496
3497         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3498         if (IS_ERR(handler_rx)) {
3499                 err = PTR_ERR(handler_rx);
3500                 goto err;
3501         }
3502
3503         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3504         if (IS_ERR(handler_tx)) {
3505                 err = PTR_ERR(handler_tx);
3506                 goto err_tx;
3507         }
3508
3509         list_add(&handler_tx->list, &handler_rx->list);
3510
3511         return handler_rx;
3512
3513 err_tx:
3514         mlx5_del_flow_rules(handler_rx->rule);
3515         ft_rx->refcount--;
3516         kfree(handler_rx);
3517 err:
3518         return ERR_PTR(err);
3519 }
3520
3521 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3522                                            struct ib_flow_attr *flow_attr,
3523                                            int domain,
3524                                            struct ib_udata *udata)
3525 {
3526         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3527         struct mlx5_ib_qp *mqp = to_mqp(qp);
3528         struct mlx5_ib_flow_handler *handler = NULL;
3529         struct mlx5_flow_destination *dst = NULL;
3530         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3531         struct mlx5_ib_flow_prio *ft_prio;
3532         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3533         struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3534         size_t min_ucmd_sz, required_ucmd_sz;
3535         int err;
3536         int underlay_qpn;
3537
3538         if (udata && udata->inlen) {
3539                 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3540                                 sizeof(ucmd_hdr.reserved);
3541                 if (udata->inlen < min_ucmd_sz)
3542                         return ERR_PTR(-EOPNOTSUPP);
3543
3544                 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3545                 if (err)
3546                         return ERR_PTR(err);
3547
3548                 /* currently supports only one counters data */
3549                 if (ucmd_hdr.ncounters_data > 1)
3550                         return ERR_PTR(-EINVAL);
3551
3552                 required_ucmd_sz = min_ucmd_sz +
3553                         sizeof(struct mlx5_ib_flow_counters_data) *
3554                         ucmd_hdr.ncounters_data;
3555                 if (udata->inlen > required_ucmd_sz &&
3556                     !ib_is_udata_cleared(udata, required_ucmd_sz,
3557                                          udata->inlen - required_ucmd_sz))
3558                         return ERR_PTR(-EOPNOTSUPP);
3559
3560                 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3561                 if (!ucmd)
3562                         return ERR_PTR(-ENOMEM);
3563
3564                 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3565                 if (err) {
3566                         kfree(ucmd);
3567                         return ERR_PTR(err);
3568                 }
3569         }
3570
3571         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
3572                 return ERR_PTR(-ENOMEM);
3573
3574         if (domain != IB_FLOW_DOMAIN_USER ||
3575             flow_attr->port > dev->num_ports ||
3576             (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3577                                   IB_FLOW_ATTR_FLAGS_EGRESS)))
3578                 return ERR_PTR(-EINVAL);
3579
3580         if (is_egress &&
3581             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3582              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT))
3583                 return ERR_PTR(-EINVAL);
3584
3585         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3586         if (!dst)
3587                 return ERR_PTR(-ENOMEM);
3588
3589         mutex_lock(&dev->flow_db->lock);
3590
3591         ft_prio = get_flow_table(dev, flow_attr,
3592                                  is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3593         if (IS_ERR(ft_prio)) {
3594                 err = PTR_ERR(ft_prio);
3595                 goto unlock;
3596         }
3597         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3598                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3599                 if (IS_ERR(ft_prio_tx)) {
3600                         err = PTR_ERR(ft_prio_tx);
3601                         ft_prio_tx = NULL;
3602                         goto destroy_ft;
3603                 }
3604         }
3605
3606         if (is_egress) {
3607                 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3608         } else {
3609                 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3610                 if (mqp->flags & MLX5_IB_QP_RSS)
3611                         dst->tir_num = mqp->rss_qp.tirn;
3612                 else
3613                         dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3614         }
3615
3616         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3617                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3618                         handler = create_dont_trap_rule(dev, ft_prio,
3619                                                         flow_attr, dst);
3620                 } else {
3621                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3622                                         mqp->underlay_qpn : 0;
3623                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3624                                                     dst, underlay_qpn, ucmd);
3625                 }
3626         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3627                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3628                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3629                                                 dst);
3630         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3631                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3632         } else {
3633                 err = -EINVAL;
3634                 goto destroy_ft;
3635         }
3636
3637         if (IS_ERR(handler)) {
3638                 err = PTR_ERR(handler);
3639                 handler = NULL;
3640                 goto destroy_ft;
3641         }
3642
3643         mutex_unlock(&dev->flow_db->lock);
3644         kfree(dst);
3645         kfree(ucmd);
3646
3647         return &handler->ibflow;
3648
3649 destroy_ft:
3650         put_flow_table(dev, ft_prio, false);
3651         if (ft_prio_tx)
3652                 put_flow_table(dev, ft_prio_tx, false);
3653 unlock:
3654         mutex_unlock(&dev->flow_db->lock);
3655         kfree(dst);
3656         kfree(ucmd);
3657         kfree(handler);
3658         return ERR_PTR(err);
3659 }
3660
3661 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3662 {
3663         u32 flags = 0;
3664
3665         if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3666                 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3667
3668         return flags;
3669 }
3670
3671 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED      MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3672 static struct ib_flow_action *
3673 mlx5_ib_create_flow_action_esp(struct ib_device *device,
3674                                const struct ib_flow_action_attrs_esp *attr,
3675                                struct uverbs_attr_bundle *attrs)
3676 {
3677         struct mlx5_ib_dev *mdev = to_mdev(device);
3678         struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3679         struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3680         struct mlx5_ib_flow_action *action;
3681         u64 action_flags;
3682         u64 flags;
3683         int err = 0;
3684
3685         if (IS_UVERBS_COPY_ERR(uverbs_copy_from(&action_flags, attrs,
3686                                                 MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS)))
3687                 return ERR_PTR(-EFAULT);
3688
3689         if (action_flags >= (MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1))
3690                 return ERR_PTR(-EOPNOTSUPP);
3691
3692         flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3693
3694         /* We current only support a subset of the standard features. Only a
3695          * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3696          * (with overlap). Full offload mode isn't supported.
3697          */
3698         if (!attr->keymat || attr->replay || attr->encap ||
3699             attr->spi || attr->seq || attr->tfc_pad ||
3700             attr->hard_limit_pkts ||
3701             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3702                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3703                 return ERR_PTR(-EOPNOTSUPP);
3704
3705         if (attr->keymat->protocol !=
3706             IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3707                 return ERR_PTR(-EOPNOTSUPP);
3708
3709         aes_gcm = &attr->keymat->keymat.aes_gcm;
3710
3711         if (aes_gcm->icv_len != 16 ||
3712             aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3713                 return ERR_PTR(-EOPNOTSUPP);
3714
3715         action = kmalloc(sizeof(*action), GFP_KERNEL);
3716         if (!action)
3717                 return ERR_PTR(-ENOMEM);
3718
3719         action->esp_aes_gcm.ib_flags = attr->flags;
3720         memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3721                sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3722         accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3723         memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3724                sizeof(accel_attrs.keymat.aes_gcm.salt));
3725         memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3726                sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3727         accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3728         accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3729         accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3730
3731         accel_attrs.esn = attr->esn;
3732         if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3733                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3734         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3735                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3736
3737         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3738                 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3739
3740         action->esp_aes_gcm.ctx =
3741                 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3742         if (IS_ERR(action->esp_aes_gcm.ctx)) {
3743                 err = PTR_ERR(action->esp_aes_gcm.ctx);
3744                 goto err_parse;
3745         }
3746
3747         action->esp_aes_gcm.ib_flags = attr->flags;
3748
3749         return &action->ib_action;
3750
3751 err_parse:
3752         kfree(action);
3753         return ERR_PTR(err);
3754 }
3755
3756 static int
3757 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3758                                const struct ib_flow_action_attrs_esp *attr,
3759                                struct uverbs_attr_bundle *attrs)
3760 {
3761         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3762         struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3763         int err = 0;
3764
3765         if (attr->keymat || attr->replay || attr->encap ||
3766             attr->spi || attr->seq || attr->tfc_pad ||
3767             attr->hard_limit_pkts ||
3768             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3769                              IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3770                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3771                 return -EOPNOTSUPP;
3772
3773         /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3774          * be modified.
3775          */
3776         if (!(maction->esp_aes_gcm.ib_flags &
3777               IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3778             attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3779                            IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3780                 return -EINVAL;
3781
3782         memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3783                sizeof(accel_attrs));
3784
3785         accel_attrs.esn = attr->esn;
3786         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3787                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3788         else
3789                 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3790
3791         err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3792                                          &accel_attrs);
3793         if (err)
3794                 return err;
3795
3796         maction->esp_aes_gcm.ib_flags &=
3797                 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3798         maction->esp_aes_gcm.ib_flags |=
3799                 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3800
3801         return 0;
3802 }
3803
3804 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3805 {
3806         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3807
3808         switch (action->type) {
3809         case IB_FLOW_ACTION_ESP:
3810                 /*
3811                  * We only support aes_gcm by now, so we implicitly know this is
3812                  * the underline crypto.
3813                  */
3814                 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
3815                 break;
3816         default:
3817                 WARN_ON(true);
3818                 break;
3819         }
3820
3821         kfree(maction);
3822         return 0;
3823 }
3824
3825 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3826 {
3827         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3828         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
3829         int err;
3830
3831         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
3832                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
3833                 return -EOPNOTSUPP;
3834         }
3835
3836         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
3837         if (err)
3838                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
3839                              ibqp->qp_num, gid->raw);
3840
3841         return err;
3842 }
3843
3844 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
3845 {
3846         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3847         int err;
3848
3849         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
3850         if (err)
3851                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
3852                              ibqp->qp_num, gid->raw);
3853
3854         return err;
3855 }
3856
3857 static int init_node_data(struct mlx5_ib_dev *dev)
3858 {
3859         int err;
3860
3861         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
3862         if (err)
3863                 return err;
3864
3865         dev->mdev->rev_id = dev->mdev->pdev->revision;
3866
3867         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
3868 }
3869
3870 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
3871                              char *buf)
3872 {
3873         struct mlx5_ib_dev *dev =
3874                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3875
3876         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
3877 }
3878
3879 static ssize_t show_reg_pages(struct device *device,
3880                               struct device_attribute *attr, char *buf)
3881 {
3882         struct mlx5_ib_dev *dev =
3883                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3884
3885         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
3886 }
3887
3888 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
3889                         char *buf)
3890 {
3891         struct mlx5_ib_dev *dev =
3892                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3893         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
3894 }
3895
3896 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
3897                         char *buf)
3898 {
3899         struct mlx5_ib_dev *dev =
3900                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3901         return sprintf(buf, "%x\n", dev->mdev->rev_id);
3902 }
3903
3904 static ssize_t show_board(struct device *device, struct device_attribute *attr,
3905                           char *buf)
3906 {
3907         struct mlx5_ib_dev *dev =
3908                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
3909         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
3910                        dev->mdev->board_id);
3911 }
3912
3913 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
3914 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
3915 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
3916 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
3917 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
3918
3919 static struct device_attribute *mlx5_class_attributes[] = {
3920         &dev_attr_hw_rev,
3921         &dev_attr_hca_type,
3922         &dev_attr_board_id,
3923         &dev_attr_fw_pages,
3924         &dev_attr_reg_pages,
3925 };
3926
3927 static void pkey_change_handler(struct work_struct *work)
3928 {
3929         struct mlx5_ib_port_resources *ports =
3930                 container_of(work, struct mlx5_ib_port_resources,
3931                              pkey_change_work);
3932
3933         mutex_lock(&ports->devr->mutex);
3934         mlx5_ib_gsi_pkey_change(ports->gsi);
3935         mutex_unlock(&ports->devr->mutex);
3936 }
3937
3938 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
3939 {
3940         struct mlx5_ib_qp *mqp;
3941         struct mlx5_ib_cq *send_mcq, *recv_mcq;
3942         struct mlx5_core_cq *mcq;
3943         struct list_head cq_armed_list;
3944         unsigned long flags_qp;
3945         unsigned long flags_cq;
3946         unsigned long flags;
3947
3948         INIT_LIST_HEAD(&cq_armed_list);
3949
3950         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3951         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3952         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3953                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3954                 if (mqp->sq.tail != mqp->sq.head) {
3955                         send_mcq = to_mcq(mqp->ibqp.send_cq);
3956                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
3957                         if (send_mcq->mcq.comp &&
3958                             mqp->ibqp.send_cq->comp_handler) {
3959                                 if (!send_mcq->mcq.reset_notify_added) {
3960                                         send_mcq->mcq.reset_notify_added = 1;
3961                                         list_add_tail(&send_mcq->mcq.reset_notify,
3962                                                       &cq_armed_list);
3963                                 }
3964                         }
3965                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3966                 }
3967                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3968                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3969                 /* no handling is needed for SRQ */
3970                 if (!mqp->ibqp.srq) {
3971                         if (mqp->rq.tail != mqp->rq.head) {
3972                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3973                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3974                                 if (recv_mcq->mcq.comp &&
3975                                     mqp->ibqp.recv_cq->comp_handler) {
3976                                         if (!recv_mcq->mcq.reset_notify_added) {
3977                                                 recv_mcq->mcq.reset_notify_added = 1;
3978                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
3979                                                               &cq_armed_list);
3980                                         }
3981                                 }
3982                                 spin_unlock_irqrestore(&recv_mcq->lock,
3983                                                        flags_cq);
3984                         }
3985                 }
3986                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3987         }
3988         /*At that point all inflight post send were put to be executed as of we
3989          * lock/unlock above locks Now need to arm all involved CQs.
3990          */
3991         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
3992                 mcq->comp(mcq);
3993         }
3994         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3995 }
3996
3997 static void delay_drop_handler(struct work_struct *work)
3998 {
3999         int err;
4000         struct mlx5_ib_delay_drop *delay_drop =
4001                 container_of(work, struct mlx5_ib_delay_drop,
4002                              delay_drop_work);
4003
4004         atomic_inc(&delay_drop->events_cnt);
4005
4006         mutex_lock(&delay_drop->lock);
4007         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4008                                        delay_drop->timeout);
4009         if (err) {
4010                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4011                              delay_drop->timeout);
4012                 delay_drop->activate = false;
4013         }
4014         mutex_unlock(&delay_drop->lock);
4015 }
4016
4017 static void mlx5_ib_handle_event(struct work_struct *_work)
4018 {
4019         struct mlx5_ib_event_work *work =
4020                 container_of(_work, struct mlx5_ib_event_work, work);
4021         struct mlx5_ib_dev *ibdev;
4022         struct ib_event ibev;
4023         bool fatal = false;
4024         u8 port = (u8)work->param;
4025
4026         if (mlx5_core_is_mp_slave(work->dev)) {
4027                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
4028                 if (!ibdev)
4029                         goto out;
4030         } else {
4031                 ibdev = work->context;
4032         }
4033
4034         switch (work->event) {
4035         case MLX5_DEV_EVENT_SYS_ERROR:
4036                 ibev.event = IB_EVENT_DEVICE_FATAL;
4037                 mlx5_ib_handle_internal_error(ibdev);
4038                 fatal = true;
4039                 break;
4040
4041         case MLX5_DEV_EVENT_PORT_UP:
4042         case MLX5_DEV_EVENT_PORT_DOWN:
4043         case MLX5_DEV_EVENT_PORT_INITIALIZED:
4044                 /* In RoCE, port up/down events are handled in
4045                  * mlx5_netdev_event().
4046                  */
4047                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4048                         IB_LINK_LAYER_ETHERNET)
4049                         goto out;
4050
4051                 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
4052                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4053                 break;
4054
4055         case MLX5_DEV_EVENT_LID_CHANGE:
4056                 ibev.event = IB_EVENT_LID_CHANGE;
4057                 break;
4058
4059         case MLX5_DEV_EVENT_PKEY_CHANGE:
4060                 ibev.event = IB_EVENT_PKEY_CHANGE;
4061                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4062                 break;
4063
4064         case MLX5_DEV_EVENT_GUID_CHANGE:
4065                 ibev.event = IB_EVENT_GID_CHANGE;
4066                 break;
4067
4068         case MLX5_DEV_EVENT_CLIENT_REREG:
4069                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4070                 break;
4071         case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4072                 schedule_work(&ibdev->delay_drop.delay_drop_work);
4073                 goto out;
4074         default:
4075                 goto out;
4076         }
4077
4078         ibev.device           = &ibdev->ib_dev;
4079         ibev.element.port_num = port;
4080
4081         if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
4082                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
4083                 goto out;
4084         }
4085
4086         if (ibdev->ib_active)
4087                 ib_dispatch_event(&ibev);
4088
4089         if (fatal)
4090                 ibdev->ib_active = false;
4091 out:
4092         kfree(work);
4093 }
4094
4095 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4096                           enum mlx5_dev_event event, unsigned long param)
4097 {
4098         struct mlx5_ib_event_work *work;
4099
4100         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4101         if (!work)
4102                 return;
4103
4104         INIT_WORK(&work->work, mlx5_ib_handle_event);
4105         work->dev = dev;
4106         work->param = param;
4107         work->context = context;
4108         work->event = event;
4109
4110         queue_work(mlx5_ib_event_wq, &work->work);
4111 }
4112
4113 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4114 {
4115         struct mlx5_hca_vport_context vport_ctx;
4116         int err;
4117         int port;
4118
4119         for (port = 1; port <= dev->num_ports; port++) {
4120                 dev->mdev->port_caps[port - 1].has_smi = false;
4121                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4122                     MLX5_CAP_PORT_TYPE_IB) {
4123                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4124                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4125                                                                    port, 0,
4126                                                                    &vport_ctx);
4127                                 if (err) {
4128                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4129                                                     port, err);
4130                                         return err;
4131                                 }
4132                                 dev->mdev->port_caps[port - 1].has_smi =
4133                                         vport_ctx.has_smi;
4134                         } else {
4135                                 dev->mdev->port_caps[port - 1].has_smi = true;
4136                         }
4137                 }
4138         }
4139         return 0;
4140 }
4141
4142 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4143 {
4144         int port;
4145
4146         for (port = 1; port <= dev->num_ports; port++)
4147                 mlx5_query_ext_port_caps(dev, port);
4148 }
4149
4150 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4151 {
4152         struct ib_device_attr *dprops = NULL;
4153         struct ib_port_attr *pprops = NULL;
4154         int err = -ENOMEM;
4155         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4156
4157         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4158         if (!pprops)
4159                 goto out;
4160
4161         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4162         if (!dprops)
4163                 goto out;
4164
4165         err = set_has_smi_cap(dev);
4166         if (err)
4167                 goto out;
4168
4169         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4170         if (err) {
4171                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4172                 goto out;
4173         }
4174
4175         memset(pprops, 0, sizeof(*pprops));
4176         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4177         if (err) {
4178                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4179                              port, err);
4180                 goto out;
4181         }
4182
4183         dev->mdev->port_caps[port - 1].pkey_table_len =
4184                                         dprops->max_pkeys;
4185         dev->mdev->port_caps[port - 1].gid_table_len =
4186                                         pprops->gid_tbl_len;
4187         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4188                     port, dprops->max_pkeys, pprops->gid_tbl_len);
4189
4190 out:
4191         kfree(pprops);
4192         kfree(dprops);
4193
4194         return err;
4195 }
4196
4197 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4198 {
4199         int err;
4200
4201         err = mlx5_mr_cache_cleanup(dev);
4202         if (err)
4203                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4204
4205         if (dev->umrc.qp)
4206                 mlx5_ib_destroy_qp(dev->umrc.qp);
4207         if (dev->umrc.cq)
4208                 ib_free_cq(dev->umrc.cq);
4209         if (dev->umrc.pd)
4210                 ib_dealloc_pd(dev->umrc.pd);
4211 }
4212
4213 enum {
4214         MAX_UMR_WR = 128,
4215 };
4216
4217 static int create_umr_res(struct mlx5_ib_dev *dev)
4218 {
4219         struct ib_qp_init_attr *init_attr = NULL;
4220         struct ib_qp_attr *attr = NULL;
4221         struct ib_pd *pd;
4222         struct ib_cq *cq;
4223         struct ib_qp *qp;
4224         int ret;
4225
4226         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4227         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4228         if (!attr || !init_attr) {
4229                 ret = -ENOMEM;
4230                 goto error_0;
4231         }
4232
4233         pd = ib_alloc_pd(&dev->ib_dev, 0);
4234         if (IS_ERR(pd)) {
4235                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4236                 ret = PTR_ERR(pd);
4237                 goto error_0;
4238         }
4239
4240         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4241         if (IS_ERR(cq)) {
4242                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4243                 ret = PTR_ERR(cq);
4244                 goto error_2;
4245         }
4246
4247         init_attr->send_cq = cq;
4248         init_attr->recv_cq = cq;
4249         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4250         init_attr->cap.max_send_wr = MAX_UMR_WR;
4251         init_attr->cap.max_send_sge = 1;
4252         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4253         init_attr->port_num = 1;
4254         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4255         if (IS_ERR(qp)) {
4256                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4257                 ret = PTR_ERR(qp);
4258                 goto error_3;
4259         }
4260         qp->device     = &dev->ib_dev;
4261         qp->real_qp    = qp;
4262         qp->uobject    = NULL;
4263         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4264         qp->send_cq    = init_attr->send_cq;
4265         qp->recv_cq    = init_attr->recv_cq;
4266
4267         attr->qp_state = IB_QPS_INIT;
4268         attr->port_num = 1;
4269         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4270                                 IB_QP_PORT, NULL);
4271         if (ret) {
4272                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4273                 goto error_4;
4274         }
4275
4276         memset(attr, 0, sizeof(*attr));
4277         attr->qp_state = IB_QPS_RTR;
4278         attr->path_mtu = IB_MTU_256;
4279
4280         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4281         if (ret) {
4282                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4283                 goto error_4;
4284         }
4285
4286         memset(attr, 0, sizeof(*attr));
4287         attr->qp_state = IB_QPS_RTS;
4288         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4289         if (ret) {
4290                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4291                 goto error_4;
4292         }
4293
4294         dev->umrc.qp = qp;
4295         dev->umrc.cq = cq;
4296         dev->umrc.pd = pd;
4297
4298         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4299         ret = mlx5_mr_cache_init(dev);
4300         if (ret) {
4301                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4302                 goto error_4;
4303         }
4304
4305         kfree(attr);
4306         kfree(init_attr);
4307
4308         return 0;
4309
4310 error_4:
4311         mlx5_ib_destroy_qp(qp);
4312         dev->umrc.qp = NULL;
4313
4314 error_3:
4315         ib_free_cq(cq);
4316         dev->umrc.cq = NULL;
4317
4318 error_2:
4319         ib_dealloc_pd(pd);
4320         dev->umrc.pd = NULL;
4321
4322 error_0:
4323         kfree(attr);
4324         kfree(init_attr);
4325         return ret;
4326 }
4327
4328 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4329 {
4330         switch (umr_fence_cap) {
4331         case MLX5_CAP_UMR_FENCE_NONE:
4332                 return MLX5_FENCE_MODE_NONE;
4333         case MLX5_CAP_UMR_FENCE_SMALL:
4334                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4335         default:
4336                 return MLX5_FENCE_MODE_STRONG_ORDERING;
4337         }
4338 }
4339
4340 static int create_dev_resources(struct mlx5_ib_resources *devr)
4341 {
4342         struct ib_srq_init_attr attr;
4343         struct mlx5_ib_dev *dev;
4344         struct ib_cq_init_attr cq_attr = {.cqe = 1};
4345         int port;
4346         int ret = 0;
4347
4348         dev = container_of(devr, struct mlx5_ib_dev, devr);
4349
4350         mutex_init(&devr->mutex);
4351
4352         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4353         if (IS_ERR(devr->p0)) {
4354                 ret = PTR_ERR(devr->p0);
4355                 goto error0;
4356         }
4357         devr->p0->device  = &dev->ib_dev;
4358         devr->p0->uobject = NULL;
4359         atomic_set(&devr->p0->usecnt, 0);
4360
4361         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
4362         if (IS_ERR(devr->c0)) {
4363                 ret = PTR_ERR(devr->c0);
4364                 goto error1;
4365         }
4366         devr->c0->device        = &dev->ib_dev;
4367         devr->c0->uobject       = NULL;
4368         devr->c0->comp_handler  = NULL;
4369         devr->c0->event_handler = NULL;
4370         devr->c0->cq_context    = NULL;
4371         atomic_set(&devr->c0->usecnt, 0);
4372
4373         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4374         if (IS_ERR(devr->x0)) {
4375                 ret = PTR_ERR(devr->x0);
4376                 goto error2;
4377         }
4378         devr->x0->device = &dev->ib_dev;
4379         devr->x0->inode = NULL;
4380         atomic_set(&devr->x0->usecnt, 0);
4381         mutex_init(&devr->x0->tgt_qp_mutex);
4382         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4383
4384         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4385         if (IS_ERR(devr->x1)) {
4386                 ret = PTR_ERR(devr->x1);
4387                 goto error3;
4388         }
4389         devr->x1->device = &dev->ib_dev;
4390         devr->x1->inode = NULL;
4391         atomic_set(&devr->x1->usecnt, 0);
4392         mutex_init(&devr->x1->tgt_qp_mutex);
4393         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4394
4395         memset(&attr, 0, sizeof(attr));
4396         attr.attr.max_sge = 1;
4397         attr.attr.max_wr = 1;
4398         attr.srq_type = IB_SRQT_XRC;
4399         attr.ext.cq = devr->c0;
4400         attr.ext.xrc.xrcd = devr->x0;
4401
4402         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4403         if (IS_ERR(devr->s0)) {
4404                 ret = PTR_ERR(devr->s0);
4405                 goto error4;
4406         }
4407         devr->s0->device        = &dev->ib_dev;
4408         devr->s0->pd            = devr->p0;
4409         devr->s0->uobject       = NULL;
4410         devr->s0->event_handler = NULL;
4411         devr->s0->srq_context   = NULL;
4412         devr->s0->srq_type      = IB_SRQT_XRC;
4413         devr->s0->ext.xrc.xrcd  = devr->x0;
4414         devr->s0->ext.cq        = devr->c0;
4415         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4416         atomic_inc(&devr->s0->ext.cq->usecnt);
4417         atomic_inc(&devr->p0->usecnt);
4418         atomic_set(&devr->s0->usecnt, 0);
4419
4420         memset(&attr, 0, sizeof(attr));
4421         attr.attr.max_sge = 1;
4422         attr.attr.max_wr = 1;
4423         attr.srq_type = IB_SRQT_BASIC;
4424         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4425         if (IS_ERR(devr->s1)) {
4426                 ret = PTR_ERR(devr->s1);
4427                 goto error5;
4428         }
4429         devr->s1->device        = &dev->ib_dev;
4430         devr->s1->pd            = devr->p0;
4431         devr->s1->uobject       = NULL;
4432         devr->s1->event_handler = NULL;
4433         devr->s1->srq_context   = NULL;
4434         devr->s1->srq_type      = IB_SRQT_BASIC;
4435         devr->s1->ext.cq        = devr->c0;
4436         atomic_inc(&devr->p0->usecnt);
4437         atomic_set(&devr->s1->usecnt, 0);
4438
4439         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4440                 INIT_WORK(&devr->ports[port].pkey_change_work,
4441                           pkey_change_handler);
4442                 devr->ports[port].devr = devr;
4443         }
4444
4445         return 0;
4446
4447 error5:
4448         mlx5_ib_destroy_srq(devr->s0);
4449 error4:
4450         mlx5_ib_dealloc_xrcd(devr->x1);
4451 error3:
4452         mlx5_ib_dealloc_xrcd(devr->x0);
4453 error2:
4454         mlx5_ib_destroy_cq(devr->c0);
4455 error1:
4456         mlx5_ib_dealloc_pd(devr->p0);
4457 error0:
4458         return ret;
4459 }
4460
4461 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4462 {
4463         struct mlx5_ib_dev *dev =
4464                 container_of(devr, struct mlx5_ib_dev, devr);
4465         int port;
4466
4467         mlx5_ib_destroy_srq(devr->s1);
4468         mlx5_ib_destroy_srq(devr->s0);
4469         mlx5_ib_dealloc_xrcd(devr->x0);
4470         mlx5_ib_dealloc_xrcd(devr->x1);
4471         mlx5_ib_destroy_cq(devr->c0);
4472         mlx5_ib_dealloc_pd(devr->p0);
4473
4474         /* Make sure no change P_Key work items are still executing */
4475         for (port = 0; port < dev->num_ports; ++port)
4476                 cancel_work_sync(&devr->ports[port].pkey_change_work);
4477 }
4478
4479 static u32 get_core_cap_flags(struct ib_device *ibdev)
4480 {
4481         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4482         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4483         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4484         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
4485         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
4486         u32 ret = 0;
4487
4488         if (ll == IB_LINK_LAYER_INFINIBAND)
4489                 return RDMA_CORE_PORT_IBA_IB;
4490
4491         if (raw_support)
4492                 ret = RDMA_CORE_PORT_RAW_PACKET;
4493
4494         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
4495                 return ret;
4496
4497         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
4498                 return ret;
4499
4500         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4501                 ret |= RDMA_CORE_PORT_IBA_ROCE;
4502
4503         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4504                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4505
4506         return ret;
4507 }
4508
4509 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4510                                struct ib_port_immutable *immutable)
4511 {
4512         struct ib_port_attr attr;
4513         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4514         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
4515         int err;
4516
4517         immutable->core_cap_flags = get_core_cap_flags(ibdev);
4518
4519         err = ib_query_port(ibdev, port_num, &attr);
4520         if (err)
4521                 return err;
4522
4523         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4524         immutable->gid_tbl_len = attr.gid_tbl_len;
4525         immutable->core_cap_flags = get_core_cap_flags(ibdev);
4526         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4527                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4528
4529         return 0;
4530 }
4531
4532 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4533                                    struct ib_port_immutable *immutable)
4534 {
4535         struct ib_port_attr attr;
4536         int err;
4537
4538         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4539
4540         err = ib_query_port(ibdev, port_num, &attr);
4541         if (err)
4542                 return err;
4543
4544         immutable->pkey_tbl_len = attr.pkey_tbl_len;
4545         immutable->gid_tbl_len = attr.gid_tbl_len;
4546         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4547
4548         return 0;
4549 }
4550
4551 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
4552 {
4553         struct mlx5_ib_dev *dev =
4554                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
4555         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4556                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4557                  fw_rev_sub(dev->mdev));
4558 }
4559
4560 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
4561 {
4562         struct mlx5_core_dev *mdev = dev->mdev;
4563         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4564                                                                  MLX5_FLOW_NAMESPACE_LAG);
4565         struct mlx5_flow_table *ft;
4566         int err;
4567
4568         if (!ns || !mlx5_lag_is_active(mdev))
4569                 return 0;
4570
4571         err = mlx5_cmd_create_vport_lag(mdev);
4572         if (err)
4573                 return err;
4574
4575         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4576         if (IS_ERR(ft)) {
4577                 err = PTR_ERR(ft);
4578                 goto err_destroy_vport_lag;
4579         }
4580
4581         dev->flow_db->lag_demux_ft = ft;
4582         return 0;
4583
4584 err_destroy_vport_lag:
4585         mlx5_cmd_destroy_vport_lag(mdev);
4586         return err;
4587 }
4588
4589 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
4590 {
4591         struct mlx5_core_dev *mdev = dev->mdev;
4592
4593         if (dev->flow_db->lag_demux_ft) {
4594                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4595                 dev->flow_db->lag_demux_ft = NULL;
4596
4597                 mlx5_cmd_destroy_vport_lag(mdev);
4598         }
4599 }
4600
4601 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4602 {
4603         int err;
4604
4605         dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4606         err = register_netdevice_notifier(&dev->roce[port_num].nb);
4607         if (err) {
4608                 dev->roce[port_num].nb.notifier_call = NULL;
4609                 return err;
4610         }
4611
4612         return 0;
4613 }
4614
4615 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4616 {
4617         if (dev->roce[port_num].nb.notifier_call) {
4618                 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4619                 dev->roce[port_num].nb.notifier_call = NULL;
4620         }
4621 }
4622
4623 static int mlx5_enable_eth(struct mlx5_ib_dev *dev, u8 port_num)
4624 {
4625         int err;
4626
4627         if (MLX5_CAP_GEN(dev->mdev, roce)) {
4628                 err = mlx5_nic_vport_enable_roce(dev->mdev);
4629                 if (err)
4630                         return err;
4631         }
4632
4633         err = mlx5_eth_lag_init(dev);
4634         if (err)
4635                 goto err_disable_roce;
4636
4637         return 0;
4638
4639 err_disable_roce:
4640         if (MLX5_CAP_GEN(dev->mdev, roce))
4641                 mlx5_nic_vport_disable_roce(dev->mdev);
4642
4643         return err;
4644 }
4645
4646 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
4647 {
4648         mlx5_eth_lag_cleanup(dev);
4649         if (MLX5_CAP_GEN(dev->mdev, roce))
4650                 mlx5_nic_vport_disable_roce(dev->mdev);
4651 }
4652
4653 struct mlx5_ib_counter {
4654         const char *name;
4655         size_t offset;
4656 };
4657
4658 #define INIT_Q_COUNTER(_name)           \
4659         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4660
4661 static const struct mlx5_ib_counter basic_q_cnts[] = {
4662         INIT_Q_COUNTER(rx_write_requests),
4663         INIT_Q_COUNTER(rx_read_requests),
4664         INIT_Q_COUNTER(rx_atomic_requests),
4665         INIT_Q_COUNTER(out_of_buffer),
4666 };
4667
4668 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
4669         INIT_Q_COUNTER(out_of_sequence),
4670 };
4671
4672 static const struct mlx5_ib_counter retrans_q_cnts[] = {
4673         INIT_Q_COUNTER(duplicate_request),
4674         INIT_Q_COUNTER(rnr_nak_retry_err),
4675         INIT_Q_COUNTER(packet_seq_err),
4676         INIT_Q_COUNTER(implied_nak_seq_err),
4677         INIT_Q_COUNTER(local_ack_timeout_err),
4678 };
4679
4680 #define INIT_CONG_COUNTER(_name)                \
4681         { .name = #_name, .offset =     \
4682                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4683
4684 static const struct mlx5_ib_counter cong_cnts[] = {
4685         INIT_CONG_COUNTER(rp_cnp_ignored),
4686         INIT_CONG_COUNTER(rp_cnp_handled),
4687         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4688         INIT_CONG_COUNTER(np_cnp_sent),
4689 };
4690
4691 static const struct mlx5_ib_counter extended_err_cnts[] = {
4692         INIT_Q_COUNTER(resp_local_length_error),
4693         INIT_Q_COUNTER(resp_cqe_error),
4694         INIT_Q_COUNTER(req_cqe_error),
4695         INIT_Q_COUNTER(req_remote_invalid_request),
4696         INIT_Q_COUNTER(req_remote_access_errors),
4697         INIT_Q_COUNTER(resp_remote_access_errors),
4698         INIT_Q_COUNTER(resp_cqe_flush_error),
4699         INIT_Q_COUNTER(req_cqe_flush_error),
4700 };
4701
4702 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
4703 {
4704         int i;
4705
4706         for (i = 0; i < dev->num_ports; i++) {
4707                 if (dev->port[i].cnts.set_id)
4708                         mlx5_core_dealloc_q_counter(dev->mdev,
4709                                                     dev->port[i].cnts.set_id);
4710                 kfree(dev->port[i].cnts.names);
4711                 kfree(dev->port[i].cnts.offsets);
4712         }
4713 }
4714
4715 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4716                                     struct mlx5_ib_counters *cnts)
4717 {
4718         u32 num_counters;
4719
4720         num_counters = ARRAY_SIZE(basic_q_cnts);
4721
4722         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4723                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4724
4725         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4726                 num_counters += ARRAY_SIZE(retrans_q_cnts);
4727
4728         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4729                 num_counters += ARRAY_SIZE(extended_err_cnts);
4730
4731         cnts->num_q_counters = num_counters;
4732
4733         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4734                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4735                 num_counters += ARRAY_SIZE(cong_cnts);
4736         }
4737
4738         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4739         if (!cnts->names)
4740                 return -ENOMEM;
4741
4742         cnts->offsets = kcalloc(num_counters,
4743                                 sizeof(cnts->offsets), GFP_KERNEL);
4744         if (!cnts->offsets)
4745                 goto err_names;
4746
4747         return 0;
4748
4749 err_names:
4750         kfree(cnts->names);
4751         cnts->names = NULL;
4752         return -ENOMEM;
4753 }
4754
4755 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4756                                   const char **names,
4757                                   size_t *offsets)
4758 {
4759         int i;
4760         int j = 0;
4761
4762         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4763                 names[j] = basic_q_cnts[i].name;
4764                 offsets[j] = basic_q_cnts[i].offset;
4765         }
4766
4767         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4768                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4769                         names[j] = out_of_seq_q_cnts[i].name;
4770                         offsets[j] = out_of_seq_q_cnts[i].offset;
4771                 }
4772         }
4773
4774         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4775                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4776                         names[j] = retrans_q_cnts[i].name;
4777                         offsets[j] = retrans_q_cnts[i].offset;
4778                 }
4779         }
4780
4781         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4782                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4783                         names[j] = extended_err_cnts[i].name;
4784                         offsets[j] = extended_err_cnts[i].offset;
4785                 }
4786         }
4787
4788         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4789                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4790                         names[j] = cong_cnts[i].name;
4791                         offsets[j] = cong_cnts[i].offset;
4792                 }
4793         }
4794 }
4795
4796 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
4797 {
4798         int err = 0;
4799         int i;
4800
4801         for (i = 0; i < dev->num_ports; i++) {
4802                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
4803                 if (err)
4804                         goto err_alloc;
4805
4806                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
4807                                       dev->port[i].cnts.offsets);
4808
4809                 err = mlx5_core_alloc_q_counter(dev->mdev,
4810                                                 &dev->port[i].cnts.set_id);
4811                 if (err) {
4812                         mlx5_ib_warn(dev,
4813                                      "couldn't allocate queue counter for port %d, err %d\n",
4814                                      i + 1, err);
4815                         goto err_alloc;
4816                 }
4817                 dev->port[i].cnts.set_id_valid = true;
4818         }
4819
4820         return 0;
4821
4822 err_alloc:
4823         mlx5_ib_dealloc_counters(dev);
4824         return err;
4825 }
4826
4827 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
4828                                                     u8 port_num)
4829 {
4830         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4831         struct mlx5_ib_port *port = &dev->port[port_num - 1];
4832
4833         /* We support only per port stats */
4834         if (port_num == 0)
4835                 return NULL;
4836
4837         return rdma_alloc_hw_stats_struct(port->cnts.names,
4838                                           port->cnts.num_q_counters +
4839                                           port->cnts.num_cong_counters,
4840                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
4841 }
4842
4843 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
4844                                     struct mlx5_ib_port *port,
4845                                     struct rdma_hw_stats *stats)
4846 {
4847         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
4848         void *out;
4849         __be32 val;
4850         int ret, i;
4851
4852         out = kvzalloc(outlen, GFP_KERNEL);
4853         if (!out)
4854                 return -ENOMEM;
4855
4856         ret = mlx5_core_query_q_counter(mdev,
4857                                         port->cnts.set_id, 0,
4858                                         out, outlen);
4859         if (ret)
4860                 goto free;
4861
4862         for (i = 0; i < port->cnts.num_q_counters; i++) {
4863                 val = *(__be32 *)(out + port->cnts.offsets[i]);
4864                 stats->value[i] = (u64)be32_to_cpu(val);
4865         }
4866
4867 free:
4868         kvfree(out);
4869         return ret;
4870 }
4871
4872 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
4873                                 struct rdma_hw_stats *stats,
4874                                 u8 port_num, int index)
4875 {
4876         struct mlx5_ib_dev *dev = to_mdev(ibdev);
4877         struct mlx5_ib_port *port = &dev->port[port_num - 1];
4878         struct mlx5_core_dev *mdev;
4879         int ret, num_counters;
4880         u8 mdev_port_num;
4881
4882         if (!stats)
4883                 return -EINVAL;
4884
4885         num_counters = port->cnts.num_q_counters + port->cnts.num_cong_counters;
4886
4887         /* q_counters are per IB device, query the master mdev */
4888         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
4889         if (ret)
4890                 return ret;
4891
4892         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4893                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
4894                                                     &mdev_port_num);
4895                 if (!mdev) {
4896                         /* If port is not affiliated yet, its in down state
4897                          * which doesn't have any counters yet, so it would be
4898                          * zero. So no need to read from the HCA.
4899                          */
4900                         goto done;
4901                 }
4902                 ret = mlx5_lag_query_cong_counters(dev->mdev,
4903                                                    stats->value +
4904                                                    port->cnts.num_q_counters,
4905                                                    port->cnts.num_cong_counters,
4906                                                    port->cnts.offsets +
4907                                                    port->cnts.num_q_counters);
4908
4909                 mlx5_ib_put_native_port_mdev(dev, port_num);
4910                 if (ret)
4911                         return ret;
4912         }
4913
4914 done:
4915         return num_counters;
4916 }
4917
4918 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
4919 {
4920         return mlx5_rdma_netdev_free(netdev);
4921 }
4922
4923 static struct net_device*
4924 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
4925                           u8 port_num,
4926                           enum rdma_netdev_t type,
4927                           const char *name,
4928                           unsigned char name_assign_type,
4929                           void (*setup)(struct net_device *))
4930 {
4931         struct net_device *netdev;
4932         struct rdma_netdev *rn;
4933
4934         if (type != RDMA_NETDEV_IPOIB)
4935                 return ERR_PTR(-EOPNOTSUPP);
4936
4937         netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
4938                                         name, setup);
4939         if (likely(!IS_ERR_OR_NULL(netdev))) {
4940                 rn = netdev_priv(netdev);
4941                 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
4942         }
4943         return netdev;
4944 }
4945
4946 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
4947 {
4948         if (!dev->delay_drop.dbg)
4949                 return;
4950         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
4951         kfree(dev->delay_drop.dbg);
4952         dev->delay_drop.dbg = NULL;
4953 }
4954
4955 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
4956 {
4957         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4958                 return;
4959
4960         cancel_work_sync(&dev->delay_drop.delay_drop_work);
4961         delay_drop_debugfs_cleanup(dev);
4962 }
4963
4964 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
4965                                        size_t count, loff_t *pos)
4966 {
4967         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4968         char lbuf[20];
4969         int len;
4970
4971         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
4972         return simple_read_from_buffer(buf, count, pos, lbuf, len);
4973 }
4974
4975 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
4976                                         size_t count, loff_t *pos)
4977 {
4978         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
4979         u32 timeout;
4980         u32 var;
4981
4982         if (kstrtouint_from_user(buf, count, 0, &var))
4983                 return -EFAULT;
4984
4985         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
4986                         1000);
4987         if (timeout != var)
4988                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
4989                             timeout);
4990
4991         delay_drop->timeout = timeout;
4992
4993         return count;
4994 }
4995
4996 static const struct file_operations fops_delay_drop_timeout = {
4997         .owner  = THIS_MODULE,
4998         .open   = simple_open,
4999         .write  = delay_drop_timeout_write,
5000         .read   = delay_drop_timeout_read,
5001 };
5002
5003 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5004 {
5005         struct mlx5_ib_dbg_delay_drop *dbg;
5006
5007         if (!mlx5_debugfs_root)
5008                 return 0;
5009
5010         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5011         if (!dbg)
5012                 return -ENOMEM;
5013
5014         dev->delay_drop.dbg = dbg;
5015
5016         dbg->dir_debugfs =
5017                 debugfs_create_dir("delay_drop",
5018                                    dev->mdev->priv.dbg_root);
5019         if (!dbg->dir_debugfs)
5020                 goto out_debugfs;
5021
5022         dbg->events_cnt_debugfs =
5023                 debugfs_create_atomic_t("num_timeout_events", 0400,
5024                                         dbg->dir_debugfs,
5025                                         &dev->delay_drop.events_cnt);
5026         if (!dbg->events_cnt_debugfs)
5027                 goto out_debugfs;
5028
5029         dbg->rqs_cnt_debugfs =
5030                 debugfs_create_atomic_t("num_rqs", 0400,
5031                                         dbg->dir_debugfs,
5032                                         &dev->delay_drop.rqs_cnt);
5033         if (!dbg->rqs_cnt_debugfs)
5034                 goto out_debugfs;
5035
5036         dbg->timeout_debugfs =
5037                 debugfs_create_file("timeout", 0600,
5038                                     dbg->dir_debugfs,
5039                                     &dev->delay_drop,
5040                                     &fops_delay_drop_timeout);
5041         if (!dbg->timeout_debugfs)
5042                 goto out_debugfs;
5043
5044         return 0;
5045
5046 out_debugfs:
5047         delay_drop_debugfs_cleanup(dev);
5048         return -ENOMEM;
5049 }
5050
5051 static void init_delay_drop(struct mlx5_ib_dev *dev)
5052 {
5053         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5054                 return;
5055
5056         mutex_init(&dev->delay_drop.lock);
5057         dev->delay_drop.dev = dev;
5058         dev->delay_drop.activate = false;
5059         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5060         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5061         atomic_set(&dev->delay_drop.rqs_cnt, 0);
5062         atomic_set(&dev->delay_drop.events_cnt, 0);
5063
5064         if (delay_drop_debugfs_init(dev))
5065                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5066 }
5067
5068 static const struct cpumask *
5069 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
5070 {
5071         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5072
5073         return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
5074 }
5075
5076 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5077 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5078                                       struct mlx5_ib_multiport_info *mpi)
5079 {
5080         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5081         struct mlx5_ib_port *port = &ibdev->port[port_num];
5082         int comps;
5083         int err;
5084         int i;
5085
5086         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5087
5088         spin_lock(&port->mp.mpi_lock);
5089         if (!mpi->ibdev) {
5090                 spin_unlock(&port->mp.mpi_lock);
5091                 return;
5092         }
5093         mpi->ibdev = NULL;
5094
5095         spin_unlock(&port->mp.mpi_lock);
5096         mlx5_remove_netdev_notifier(ibdev, port_num);
5097         spin_lock(&port->mp.mpi_lock);
5098
5099         comps = mpi->mdev_refcnt;
5100         if (comps) {
5101                 mpi->unaffiliate = true;
5102                 init_completion(&mpi->unref_comp);
5103                 spin_unlock(&port->mp.mpi_lock);
5104
5105                 for (i = 0; i < comps; i++)
5106                         wait_for_completion(&mpi->unref_comp);
5107
5108                 spin_lock(&port->mp.mpi_lock);
5109                 mpi->unaffiliate = false;
5110         }
5111
5112         port->mp.mpi = NULL;
5113
5114         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5115
5116         spin_unlock(&port->mp.mpi_lock);
5117
5118         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5119
5120         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5121         /* Log an error, still needed to cleanup the pointers and add
5122          * it back to the list.
5123          */
5124         if (err)
5125                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5126                             port_num + 1);
5127
5128         ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5129 }
5130
5131 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5132 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5133                                     struct mlx5_ib_multiport_info *mpi)
5134 {
5135         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5136         int err;
5137
5138         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5139         if (ibdev->port[port_num].mp.mpi) {
5140                 mlx5_ib_warn(ibdev, "port %d already affiliated.\n",
5141                              port_num + 1);
5142                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5143                 return false;
5144         }
5145
5146         ibdev->port[port_num].mp.mpi = mpi;
5147         mpi->ibdev = ibdev;
5148         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5149
5150         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5151         if (err)
5152                 goto unbind;
5153
5154         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5155         if (err)
5156                 goto unbind;
5157
5158         err = mlx5_add_netdev_notifier(ibdev, port_num);
5159         if (err) {
5160                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5161                             port_num + 1);
5162                 goto unbind;
5163         }
5164
5165         err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5166         if (err)
5167                 goto unbind;
5168
5169         return true;
5170
5171 unbind:
5172         mlx5_ib_unbind_slave_port(ibdev, mpi);
5173         return false;
5174 }
5175
5176 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5177 {
5178         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5179         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5180                                                           port_num + 1);
5181         struct mlx5_ib_multiport_info *mpi;
5182         int err;
5183         int i;
5184
5185         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5186                 return 0;
5187
5188         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5189                                                      &dev->sys_image_guid);
5190         if (err)
5191                 return err;
5192
5193         err = mlx5_nic_vport_enable_roce(dev->mdev);
5194         if (err)
5195                 return err;
5196
5197         mutex_lock(&mlx5_ib_multiport_mutex);
5198         for (i = 0; i < dev->num_ports; i++) {
5199                 bool bound = false;
5200
5201                 /* build a stub multiport info struct for the native port. */
5202                 if (i == port_num) {
5203                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5204                         if (!mpi) {
5205                                 mutex_unlock(&mlx5_ib_multiport_mutex);
5206                                 mlx5_nic_vport_disable_roce(dev->mdev);
5207                                 return -ENOMEM;
5208                         }
5209
5210                         mpi->is_master = true;
5211                         mpi->mdev = dev->mdev;
5212                         mpi->sys_image_guid = dev->sys_image_guid;
5213                         dev->port[i].mp.mpi = mpi;
5214                         mpi->ibdev = dev;
5215                         mpi = NULL;
5216                         continue;
5217                 }
5218
5219                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5220                                     list) {
5221                         if (dev->sys_image_guid == mpi->sys_image_guid &&
5222                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5223                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
5224                         }
5225
5226                         if (bound) {
5227                                 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5228                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5229                                 list_del(&mpi->list);
5230                                 break;
5231                         }
5232                 }
5233                 if (!bound) {
5234                         get_port_caps(dev, i + 1);
5235                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
5236                                     i + 1);
5237                 }
5238         }
5239
5240         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5241         mutex_unlock(&mlx5_ib_multiport_mutex);
5242         return err;
5243 }
5244
5245 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5246 {
5247         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5248         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5249                                                           port_num + 1);
5250         int i;
5251
5252         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5253                 return;
5254
5255         mutex_lock(&mlx5_ib_multiport_mutex);
5256         for (i = 0; i < dev->num_ports; i++) {
5257                 if (dev->port[i].mp.mpi) {
5258                         /* Destroy the native port stub */
5259                         if (i == port_num) {
5260                                 kfree(dev->port[i].mp.mpi);
5261                                 dev->port[i].mp.mpi = NULL;
5262                         } else {
5263                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5264                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5265                         }
5266                 }
5267         }
5268
5269         mlx5_ib_dbg(dev, "removing from devlist\n");
5270         list_del(&dev->ib_dev_list);
5271         mutex_unlock(&mlx5_ib_multiport_mutex);
5272
5273         mlx5_nic_vport_disable_roce(dev->mdev);
5274 }
5275
5276 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_dm, UVERBS_OBJECT_DM,
5277                              UVERBS_METHOD_DM_ALLOC,
5278                              &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5279                                                   UVERBS_ATTR_TYPE(u64),
5280                                                   UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)),
5281                              &UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5282                                                   UVERBS_ATTR_TYPE(u16),
5283                                                   UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
5284
5285 ADD_UVERBS_ATTRIBUTES_SIMPLE(mlx5_ib_flow_action, UVERBS_OBJECT_FLOW_ACTION,
5286                              UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5287                              &UVERBS_ATTR_PTR_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5288                                                  UVERBS_ATTR_TYPE(u64),
5289                                                  UA_FLAGS(UVERBS_ATTR_SPEC_F_MANDATORY)));
5290
5291 #define NUM_TREES       2
5292 static int populate_specs_root(struct mlx5_ib_dev *dev)
5293 {
5294         const struct uverbs_object_tree_def *default_root[NUM_TREES + 1] = {
5295                 uverbs_default_get_objects()};
5296         size_t num_trees = 1;
5297
5298         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE &&
5299             !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5300                 default_root[num_trees++] = &mlx5_ib_flow_action;
5301
5302         if (MLX5_CAP_DEV_MEM(dev->mdev, memic) &&
5303             !WARN_ON(num_trees >= ARRAY_SIZE(default_root)))
5304                 default_root[num_trees++] = &mlx5_ib_dm;
5305
5306         dev->ib_dev.specs_root =
5307                 uverbs_alloc_spec_tree(num_trees, default_root);
5308
5309         return PTR_ERR_OR_ZERO(dev->ib_dev.specs_root);
5310 }
5311
5312 static void depopulate_specs_root(struct mlx5_ib_dev *dev)
5313 {
5314         uverbs_free_spec_tree(dev->ib_dev.specs_root);
5315 }
5316
5317 static int mlx5_ib_read_counters(struct ib_counters *counters,
5318                                  struct ib_counters_read_attr *read_attr,
5319                                  struct uverbs_attr_bundle *attrs)
5320 {
5321         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5322         struct mlx5_read_counters_attr mread_attr = {};
5323         struct mlx5_ib_flow_counters_desc *desc;
5324         int ret, i;
5325
5326         mutex_lock(&mcounters->mcntrs_mutex);
5327         if (mcounters->cntrs_max_index > read_attr->ncounters) {
5328                 ret = -EINVAL;
5329                 goto err_bound;
5330         }
5331
5332         mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5333                                  GFP_KERNEL);
5334         if (!mread_attr.out) {
5335                 ret = -ENOMEM;
5336                 goto err_bound;
5337         }
5338
5339         mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5340         mread_attr.flags = read_attr->flags;
5341         ret = mcounters->read_counters(counters->device, &mread_attr);
5342         if (ret)
5343                 goto err_read;
5344
5345         /* do the pass over the counters data array to assign according to the
5346          * descriptions and indexing pairs
5347          */
5348         desc = mcounters->counters_data;
5349         for (i = 0; i < mcounters->ncounters; i++)
5350                 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5351
5352 err_read:
5353         kfree(mread_attr.out);
5354 err_bound:
5355         mutex_unlock(&mcounters->mcntrs_mutex);
5356         return ret;
5357 }
5358
5359 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5360 {
5361         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5362
5363         counters_clear_description(counters);
5364         if (mcounters->hw_cntrs_hndl)
5365                 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5366                                 mcounters->hw_cntrs_hndl);
5367
5368         kfree(mcounters);
5369
5370         return 0;
5371 }
5372
5373 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5374                                                    struct uverbs_attr_bundle *attrs)
5375 {
5376         struct mlx5_ib_mcounters *mcounters;
5377
5378         mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5379         if (!mcounters)
5380                 return ERR_PTR(-ENOMEM);
5381
5382         mutex_init(&mcounters->mcntrs_mutex);
5383
5384         return &mcounters->ibcntrs;
5385 }
5386
5387 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5388 {
5389         mlx5_ib_cleanup_multiport_master(dev);
5390 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5391         cleanup_srcu_struct(&dev->mr_srcu);
5392 #endif
5393         kfree(dev->port);
5394 }
5395
5396 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
5397 {
5398         struct mlx5_core_dev *mdev = dev->mdev;
5399         const char *name;
5400         int err;
5401         int i;
5402
5403         dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
5404                             GFP_KERNEL);
5405         if (!dev->port)
5406                 return -ENOMEM;
5407
5408         for (i = 0; i < dev->num_ports; i++) {
5409                 spin_lock_init(&dev->port[i].mp.mpi_lock);
5410                 rwlock_init(&dev->roce[i].netdev_lock);
5411         }
5412
5413         err = mlx5_ib_init_multiport_master(dev);
5414         if (err)
5415                 goto err_free_port;
5416
5417         if (!mlx5_core_mp_enabled(mdev)) {
5418                 for (i = 1; i <= dev->num_ports; i++) {
5419                         err = get_port_caps(dev, i);
5420                         if (err)
5421                                 break;
5422                 }
5423         } else {
5424                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5425         }
5426         if (err)
5427                 goto err_mp;
5428
5429         if (mlx5_use_mad_ifc(dev))
5430                 get_ext_port_caps(dev);
5431
5432         if (!mlx5_lag_is_active(mdev))
5433                 name = "mlx5_%d";
5434         else
5435                 name = "mlx5_bond_%d";
5436
5437         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
5438         dev->ib_dev.owner               = THIS_MODULE;
5439         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
5440         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
5441         dev->ib_dev.phys_port_cnt       = dev->num_ports;
5442         dev->ib_dev.num_comp_vectors    =
5443                 dev->mdev->priv.eq_table.num_comp_vectors;
5444         dev->ib_dev.dev.parent          = &mdev->pdev->dev;
5445
5446         mutex_init(&dev->cap_mask_mutex);
5447         INIT_LIST_HEAD(&dev->qp_list);
5448         spin_lock_init(&dev->reset_flow_resource_lock);
5449
5450         spin_lock_init(&dev->memic.memic_lock);
5451         dev->memic.dev = mdev;
5452
5453 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5454         err = init_srcu_struct(&dev->mr_srcu);
5455         if (err)
5456                 goto err_free_port;
5457 #endif
5458
5459         return 0;
5460 err_mp:
5461         mlx5_ib_cleanup_multiport_master(dev);
5462
5463 err_free_port:
5464         kfree(dev->port);
5465
5466         return -ENOMEM;
5467 }
5468
5469 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5470 {
5471         dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5472
5473         if (!dev->flow_db)
5474                 return -ENOMEM;
5475
5476         mutex_init(&dev->flow_db->lock);
5477
5478         return 0;
5479 }
5480
5481 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5482 {
5483         struct mlx5_ib_dev *nic_dev;
5484
5485         nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5486
5487         if (!nic_dev)
5488                 return -EINVAL;
5489
5490         dev->flow_db = nic_dev->flow_db;
5491
5492         return 0;
5493 }
5494
5495 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5496 {
5497         kfree(dev->flow_db);
5498 }
5499
5500 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
5501 {
5502         struct mlx5_core_dev *mdev = dev->mdev;
5503         int err;
5504
5505         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
5506         dev->ib_dev.uverbs_cmd_mask     =
5507                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
5508                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
5509                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
5510                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
5511                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
5512                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
5513                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
5514                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
5515                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
5516                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
5517                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5518                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
5519                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
5520                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
5521                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
5522                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
5523                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
5524                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
5525                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
5526                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
5527                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
5528                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
5529                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
5530                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
5531                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
5532                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
5533         dev->ib_dev.uverbs_ex_cmd_mask =
5534                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
5535                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
5536                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
5537                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
5538                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
5539
5540         dev->ib_dev.query_device        = mlx5_ib_query_device;
5541         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
5542         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
5543         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
5544         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
5545         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
5546         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
5547         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
5548         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
5549         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
5550         dev->ib_dev.mmap                = mlx5_ib_mmap;
5551         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
5552         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
5553         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
5554         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
5555         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
5556         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
5557         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
5558         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
5559         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
5560         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
5561         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
5562         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
5563         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
5564         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
5565         dev->ib_dev.post_send           = mlx5_ib_post_send;
5566         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
5567         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
5568         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
5569         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
5570         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
5571         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
5572         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
5573         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
5574         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
5575         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
5576         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
5577         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
5578         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
5579         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
5580         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
5581         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
5582         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
5583         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
5584         dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
5585         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
5586                 dev->ib_dev.alloc_rdma_netdev   = mlx5_ib_alloc_rdma_netdev;
5587
5588         if (mlx5_core_is_pf(mdev)) {
5589                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
5590                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
5591                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
5592                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
5593         }
5594
5595         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5596
5597         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5598
5599         if (MLX5_CAP_GEN(mdev, imaicl)) {
5600                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
5601                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
5602                 dev->ib_dev.uverbs_cmd_mask |=
5603                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
5604                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5605         }
5606
5607         if (MLX5_CAP_GEN(mdev, xrc)) {
5608                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5609                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5610                 dev->ib_dev.uverbs_cmd_mask |=
5611                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5612                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5613         }
5614
5615         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5616                 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5617                 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
5618                 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
5619         }
5620
5621         dev->ib_dev.create_flow = mlx5_ib_create_flow;
5622         dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5623         dev->ib_dev.uverbs_ex_cmd_mask |=
5624                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5625                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5626         dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5627         dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
5628         dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
5629         dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
5630         dev->ib_dev.create_counters = mlx5_ib_create_counters;
5631         dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
5632         dev->ib_dev.read_counters = mlx5_ib_read_counters;
5633
5634         err = init_node_data(dev);
5635         if (err)
5636                 return err;
5637
5638         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
5639             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5640              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
5641                 mutex_init(&dev->lb_mutex);
5642
5643         return 0;
5644 }
5645
5646 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5647 {
5648         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
5649         dev->ib_dev.query_port          = mlx5_ib_query_port;
5650
5651         return 0;
5652 }
5653
5654 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
5655 {
5656         dev->ib_dev.get_port_immutable  = mlx5_port_rep_immutable;
5657         dev->ib_dev.query_port          = mlx5_ib_rep_query_port;
5658
5659         return 0;
5660 }
5661
5662 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev,
5663                                           u8 port_num)
5664 {
5665         int i;
5666
5667         for (i = 0; i < dev->num_ports; i++) {
5668                 dev->roce[i].dev = dev;
5669                 dev->roce[i].native_port_num = i + 1;
5670                 dev->roce[i].last_port_state = IB_PORT_DOWN;
5671         }
5672
5673         dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
5674         dev->ib_dev.create_wq    = mlx5_ib_create_wq;
5675         dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
5676         dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
5677         dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5678         dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5679
5680         dev->ib_dev.uverbs_ex_cmd_mask |=
5681                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5682                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5683                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5684                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5685                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5686
5687         return mlx5_add_netdev_notifier(dev, port_num);
5688 }
5689
5690 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5691 {
5692         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5693
5694         mlx5_remove_netdev_notifier(dev, port_num);
5695 }
5696
5697 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5698 {
5699         struct mlx5_core_dev *mdev = dev->mdev;
5700         enum rdma_link_layer ll;
5701         int port_type_cap;
5702         int err = 0;
5703         u8 port_num;
5704
5705         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5706         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5707         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5708
5709         if (ll == IB_LINK_LAYER_ETHERNET)
5710                 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5711
5712         return err;
5713 }
5714
5715 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5716 {
5717         mlx5_ib_stage_common_roce_cleanup(dev);
5718 }
5719
5720 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5721 {
5722         struct mlx5_core_dev *mdev = dev->mdev;
5723         enum rdma_link_layer ll;
5724         int port_type_cap;
5725         u8 port_num;
5726         int err;
5727
5728         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5729         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5730         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5731
5732         if (ll == IB_LINK_LAYER_ETHERNET) {
5733                 err = mlx5_ib_stage_common_roce_init(dev, port_num);
5734                 if (err)
5735                         return err;
5736
5737                 err = mlx5_enable_eth(dev, port_num);
5738                 if (err)
5739                         goto cleanup;
5740         }
5741
5742         return 0;
5743 cleanup:
5744         mlx5_ib_stage_common_roce_cleanup(dev);
5745
5746         return err;
5747 }
5748
5749 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5750 {
5751         struct mlx5_core_dev *mdev = dev->mdev;
5752         enum rdma_link_layer ll;
5753         int port_type_cap;
5754         u8 port_num;
5755
5756         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5757         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5758         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5759
5760         if (ll == IB_LINK_LAYER_ETHERNET) {
5761                 mlx5_disable_eth(dev);
5762                 mlx5_ib_stage_common_roce_cleanup(dev);
5763         }
5764 }
5765
5766 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
5767 {
5768         return create_dev_resources(&dev->devr);
5769 }
5770
5771 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
5772 {
5773         destroy_dev_resources(&dev->devr);
5774 }
5775
5776 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
5777 {
5778         mlx5_ib_internal_fill_odp_caps(dev);
5779
5780         return mlx5_ib_odp_init_one(dev);
5781 }
5782
5783 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
5784 {
5785         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
5786                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
5787                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
5788
5789                 return mlx5_ib_alloc_counters(dev);
5790         }
5791
5792         return 0;
5793 }
5794
5795 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
5796 {
5797         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
5798                 mlx5_ib_dealloc_counters(dev);
5799 }
5800
5801 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
5802 {
5803         return mlx5_ib_init_cong_debugfs(dev,
5804                                          mlx5_core_native_port_num(dev->mdev) - 1);
5805 }
5806
5807 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
5808 {
5809         mlx5_ib_cleanup_cong_debugfs(dev,
5810                                      mlx5_core_native_port_num(dev->mdev) - 1);
5811 }
5812
5813 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
5814 {
5815         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
5816         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
5817 }
5818
5819 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
5820 {
5821         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
5822 }
5823
5824 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
5825 {
5826         int err;
5827
5828         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
5829         if (err)
5830                 return err;
5831
5832         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
5833         if (err)
5834                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5835
5836         return err;
5837 }
5838
5839 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
5840 {
5841         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
5842         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
5843 }
5844
5845 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
5846 {
5847         return populate_specs_root(dev);
5848 }
5849
5850 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
5851 {
5852         return ib_register_device(&dev->ib_dev, NULL);
5853 }
5854
5855 static void mlx5_ib_stage_depopulate_specs(struct mlx5_ib_dev *dev)
5856 {
5857         depopulate_specs_root(dev);
5858 }
5859
5860 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
5861 {
5862         destroy_umrc_res(dev);
5863 }
5864
5865 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
5866 {
5867         ib_unregister_device(&dev->ib_dev);
5868 }
5869
5870 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
5871 {
5872         return create_umr_res(dev);
5873 }
5874
5875 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
5876 {
5877         init_delay_drop(dev);
5878
5879         return 0;
5880 }
5881
5882 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
5883 {
5884         cancel_delay_drop(dev);
5885 }
5886
5887 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
5888 {
5889         int err;
5890         int i;
5891
5892         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
5893                 err = device_create_file(&dev->ib_dev.dev,
5894                                          mlx5_class_attributes[i]);
5895                 if (err)
5896                         return err;
5897         }
5898
5899         return 0;
5900 }
5901
5902 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
5903 {
5904         mlx5_ib_register_vport_reps(dev);
5905
5906         return 0;
5907 }
5908
5909 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
5910 {
5911         mlx5_ib_unregister_vport_reps(dev);
5912 }
5913
5914 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
5915                       const struct mlx5_ib_profile *profile,
5916                       int stage)
5917 {
5918         /* Number of stages to cleanup */
5919         while (stage) {
5920                 stage--;
5921                 if (profile->stage[stage].cleanup)
5922                         profile->stage[stage].cleanup(dev);
5923         }
5924
5925         ib_dealloc_device((struct ib_device *)dev);
5926 }
5927
5928 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num);
5929
5930 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
5931                     const struct mlx5_ib_profile *profile)
5932 {
5933         int err;
5934         int i;
5935
5936         printk_once(KERN_INFO "%s", mlx5_version);
5937
5938         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
5939                 if (profile->stage[i].init) {
5940                         err = profile->stage[i].init(dev);
5941                         if (err)
5942                                 goto err_out;
5943                 }
5944         }
5945
5946         dev->profile = profile;
5947         dev->ib_active = true;
5948
5949         return dev;
5950
5951 err_out:
5952         __mlx5_ib_remove(dev, profile, i);
5953
5954         return NULL;
5955 }
5956
5957 static const struct mlx5_ib_profile pf_profile = {
5958         STAGE_CREATE(MLX5_IB_STAGE_INIT,
5959                      mlx5_ib_stage_init_init,
5960                      mlx5_ib_stage_init_cleanup),
5961         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
5962                      mlx5_ib_stage_flow_db_init,
5963                      mlx5_ib_stage_flow_db_cleanup),
5964         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
5965                      mlx5_ib_stage_caps_init,
5966                      NULL),
5967         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
5968                      mlx5_ib_stage_non_default_cb,
5969                      NULL),
5970         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
5971                      mlx5_ib_stage_roce_init,
5972                      mlx5_ib_stage_roce_cleanup),
5973         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
5974                      mlx5_ib_stage_dev_res_init,
5975                      mlx5_ib_stage_dev_res_cleanup),
5976         STAGE_CREATE(MLX5_IB_STAGE_ODP,
5977                      mlx5_ib_stage_odp_init,
5978                      NULL),
5979         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
5980                      mlx5_ib_stage_counters_init,
5981                      mlx5_ib_stage_counters_cleanup),
5982         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
5983                      mlx5_ib_stage_cong_debugfs_init,
5984                      mlx5_ib_stage_cong_debugfs_cleanup),
5985         STAGE_CREATE(MLX5_IB_STAGE_UAR,
5986                      mlx5_ib_stage_uar_init,
5987                      mlx5_ib_stage_uar_cleanup),
5988         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
5989                      mlx5_ib_stage_bfrag_init,
5990                      mlx5_ib_stage_bfrag_cleanup),
5991         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
5992                      NULL,
5993                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
5994         STAGE_CREATE(MLX5_IB_STAGE_SPECS,
5995                      mlx5_ib_stage_populate_specs,
5996                      mlx5_ib_stage_depopulate_specs),
5997         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
5998                      mlx5_ib_stage_ib_reg_init,
5999                      mlx5_ib_stage_ib_reg_cleanup),
6000         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6001                      mlx5_ib_stage_post_ib_reg_umr_init,
6002                      NULL),
6003         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6004                      mlx5_ib_stage_delay_drop_init,
6005                      mlx5_ib_stage_delay_drop_cleanup),
6006         STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6007                      mlx5_ib_stage_class_attr_init,
6008                      NULL),
6009 };
6010
6011 static const struct mlx5_ib_profile nic_rep_profile = {
6012         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6013                      mlx5_ib_stage_init_init,
6014                      mlx5_ib_stage_init_cleanup),
6015         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6016                      mlx5_ib_stage_flow_db_init,
6017                      mlx5_ib_stage_flow_db_cleanup),
6018         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6019                      mlx5_ib_stage_caps_init,
6020                      NULL),
6021         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6022                      mlx5_ib_stage_rep_non_default_cb,
6023                      NULL),
6024         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6025                      mlx5_ib_stage_rep_roce_init,
6026                      mlx5_ib_stage_rep_roce_cleanup),
6027         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6028                      mlx5_ib_stage_dev_res_init,
6029                      mlx5_ib_stage_dev_res_cleanup),
6030         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6031                      mlx5_ib_stage_counters_init,
6032                      mlx5_ib_stage_counters_cleanup),
6033         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6034                      mlx5_ib_stage_uar_init,
6035                      mlx5_ib_stage_uar_cleanup),
6036         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6037                      mlx5_ib_stage_bfrag_init,
6038                      mlx5_ib_stage_bfrag_cleanup),
6039         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6040                      NULL,
6041                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6042         STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6043                      mlx5_ib_stage_populate_specs,
6044                      mlx5_ib_stage_depopulate_specs),
6045         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6046                      mlx5_ib_stage_ib_reg_init,
6047                      mlx5_ib_stage_ib_reg_cleanup),
6048         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6049                      mlx5_ib_stage_post_ib_reg_umr_init,
6050                      NULL),
6051         STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6052                      mlx5_ib_stage_class_attr_init,
6053                      NULL),
6054         STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6055                      mlx5_ib_stage_rep_reg_init,
6056                      mlx5_ib_stage_rep_reg_cleanup),
6057 };
6058
6059 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev, u8 port_num)
6060 {
6061         struct mlx5_ib_multiport_info *mpi;
6062         struct mlx5_ib_dev *dev;
6063         bool bound = false;
6064         int err;
6065
6066         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6067         if (!mpi)
6068                 return NULL;
6069
6070         mpi->mdev = mdev;
6071
6072         err = mlx5_query_nic_vport_system_image_guid(mdev,
6073                                                      &mpi->sys_image_guid);
6074         if (err) {
6075                 kfree(mpi);
6076                 return NULL;
6077         }
6078
6079         mutex_lock(&mlx5_ib_multiport_mutex);
6080         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6081                 if (dev->sys_image_guid == mpi->sys_image_guid)
6082                         bound = mlx5_ib_bind_slave_port(dev, mpi);
6083
6084                 if (bound) {
6085                         rdma_roce_rescan_device(&dev->ib_dev);
6086                         break;
6087                 }
6088         }
6089
6090         if (!bound) {
6091                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6092                 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
6093         } else {
6094                 mlx5_ib_dbg(dev, "bound port %u\n", port_num + 1);
6095         }
6096         mutex_unlock(&mlx5_ib_multiport_mutex);
6097
6098         return mpi;
6099 }
6100
6101 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6102 {
6103         enum rdma_link_layer ll;
6104         struct mlx5_ib_dev *dev;
6105         int port_type_cap;
6106
6107         printk_once(KERN_INFO "%s", mlx5_version);
6108
6109         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6110         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6111
6112         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET) {
6113                 u8 port_num = mlx5_core_native_port_num(mdev) - 1;
6114
6115                 return mlx5_ib_add_slave_port(mdev, port_num);
6116         }
6117
6118         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6119         if (!dev)
6120                 return NULL;
6121
6122         dev->mdev = mdev;
6123         dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6124                              MLX5_CAP_GEN(mdev, num_vhca_ports));
6125
6126         if (MLX5_VPORT_MANAGER(mdev) &&
6127             mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6128                 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6129
6130                 return __mlx5_ib_add(dev, &nic_rep_profile);
6131         }
6132
6133         return __mlx5_ib_add(dev, &pf_profile);
6134 }
6135
6136 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6137 {
6138         struct mlx5_ib_multiport_info *mpi;
6139         struct mlx5_ib_dev *dev;
6140
6141         if (mlx5_core_is_mp_slave(mdev)) {
6142                 mpi = context;
6143                 mutex_lock(&mlx5_ib_multiport_mutex);
6144                 if (mpi->ibdev)
6145                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6146                 list_del(&mpi->list);
6147                 mutex_unlock(&mlx5_ib_multiport_mutex);
6148                 return;
6149         }
6150
6151         dev = context;
6152         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6153 }
6154
6155 static struct mlx5_interface mlx5_ib_interface = {
6156         .add            = mlx5_ib_add,
6157         .remove         = mlx5_ib_remove,
6158         .event          = mlx5_ib_event,
6159 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6160         .pfault         = mlx5_ib_pfault,
6161 #endif
6162         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
6163 };
6164
6165 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6166 {
6167         mutex_lock(&xlt_emergency_page_mutex);
6168         return xlt_emergency_page;
6169 }
6170
6171 void mlx5_ib_put_xlt_emergency_page(void)
6172 {
6173         mutex_unlock(&xlt_emergency_page_mutex);
6174 }
6175
6176 static int __init mlx5_ib_init(void)
6177 {
6178         int err;
6179
6180         xlt_emergency_page = __get_free_page(GFP_KERNEL);
6181         if (!xlt_emergency_page)
6182                 return -ENOMEM;
6183
6184         mutex_init(&xlt_emergency_page_mutex);
6185
6186         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6187         if (!mlx5_ib_event_wq) {
6188                 free_page(xlt_emergency_page);
6189                 return -ENOMEM;
6190         }
6191
6192         mlx5_ib_odp_init();
6193
6194         err = mlx5_register_interface(&mlx5_ib_interface);
6195
6196         return err;
6197 }
6198
6199 static void __exit mlx5_ib_cleanup(void)
6200 {
6201         mlx5_unregister_interface(&mlx5_ib_interface);
6202         destroy_workqueue(mlx5_ib_event_wq);
6203         mutex_destroy(&xlt_emergency_page_mutex);
6204         free_page(xlt_emergency_page);
6205 }
6206
6207 module_init(mlx5_ib_init);
6208 module_exit(mlx5_ib_cleanup);